Display board, its driving method, and display device.

Abstract

The present invention discloses a display substrate, a driving method thereof, and a display device, the display substrate including a base substrate including a display region and a frame region located on at least one side of the display region, a plurality of pixel islands arranged in an array in the display region, a plurality of data lines extending along a column direction in the display region and arranged along the row direction, a plurality of operational amplifiers located in the frame region, and a plurality of multiplexing circuits located in the frame region, each of the pixel islands having sub-pixels arranged in an array, the data lines being electrically connected to the sub-pixels, each of the operational amplifiers being electrically connected to one column of the sub-pixels via the data lines, each of the multiplexing circuits being connected to at least two of the operational amplifiers, and the sub-pixels electrically connected to each of the multiplexing circuits via the data lines being arranged in at least two columns.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and particularly to a display substrate, a driving method thereof, and a display device.

Background Art

[0002] The term "naked-eye three-dimensional (3D) technology" refers to 3D display technology with spatial recognition and depth recognition obtained without auxiliary devices. As the requirements for users' viewing experiences become increasingly high, naked-eye 3D display technology is gradually being applied to display screens.

Summary of the Invention

Means for Solving the Problems

[0003] Specific solutions for the display substrate, its driving method, and the display device provided by the embodiments of the present invention are as follows. <00000​​​​​​​​​​​​​​​​​​​​​​​In some embodiments, in the display board provided by embodiments of the present invention, one partition is formed for every two adjacent rows of the pixel islands in the row direction, The multiplexing circuit includes a first submultiplexing circuit, and the subpixels electrically connected to each of the first submultiplexing circuits are located in at least two of the partitions.

[0006] In some embodiments, in the display board provided by embodiments of the present invention, each of the first submultiplexing circuits is connected between two operational amplifiers and the data lines electrically connected to the two operational amplifiers, and the subpixels electrically connected to each of the first submultiplexing circuits are located in two partitions.

[0007] In some embodiments, the display board provided by the embodiment of the present invention has 2n partitions in the row direction, where n is a positive integer. The first to the nth consecutive partitions are gaze regions, and the (n+1)th to the 2nth consecutive partitions are non-gaze regions. Each of the subpixels electrically connected to the first submultiplexing circuit is located in the m-th and (m+n)-th partitions, where m is an integer between 1 and n, inclusive.

[0008] In some embodiments, in the display board provided by the embodiment of the present invention, each partition includes i rows of the pixel island, where i is an integer of 2 or more. Each of the subpixels electrically connected to the first submultiplexing circuit is located in the pixel island of the jth column of the m-th partition and in the pixel island of the j-th column of the (m+n)-th partition, where j is an integer between 1 and i.

[0009] In some embodiments, in the display board provided by the embodiment of the present invention, k subpixels are arranged in a single row of each pixel island, where k is an even number. The subpixels electrically connected to each of the first submultiplexing circuits are at least a portion of the subpixels in the h-th column of the pixel island in the j-th column of the m-th partition, and at least a portion of the subpixels in the h-th column of the pixel island in the j-th column of the (m+n)-th partition, where h is an integer between 1 and k.

[0010] In some embodiments, in the display board provided by the embodiment of the present invention, one data line is connected between one operational amplifier and one row of subpixels.

[0011] In some embodiments, in the display board provided by embodiments of the present invention, the subpixels electrically connected to each of the first submultiplexing circuits are the subpixels in the h-th column of the pixel island in the j-th column of the m-th partition, and the subpixels in the h-th column of the pixel island in the j-th column of the (m+n)-th partition.

[0012] In some embodiments, the display board provided by the embodiment of the present invention further includes a second submultiplexing circuit, Each of the second submultiplexing circuits is connected between two rows of subpixels in the pixel island within the same row and two of the first submultiplexing circuits corresponding to the two rows of subpixels.

[0013] In some embodiments, in the display board provided by the embodiment of the present invention, k is a multiple of 4, and h is an integer between 1 and k / 4, and an integer between (1+k / 4) and (k-4). Each of the second submultiplexing circuits is electrically connected to the h-th column subpixel and the (h+k / 4)-th column subpixel of the pixel island in the same row, respectively.

[0014] In some embodiments, in the display board provided by embodiments of the present invention, the first submultiplexing circuit connecting the subpixel of the h-th column of the pixel island in the j-th column of the m-th partition and the subpixel of the h-th column of the pixel island in the j-th column of the (m+n)-th partition includes a first transistor, a second transistor and a third transistor, The first submultiplexing circuit connecting the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the m-th partition and the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the (m+n)-th partition includes a fourth transistor, a fifth transistor and a sixth transistor, The second submultiplexing circuit connecting the subpixel in column h of the pixel island in column j of the m-th partition to the subpixel in column (h+k / 4) includes a seventh transistor, an eighth transistor and a ninth transistor, The second submultiplexing circuit connecting the subpixel in column h of the pixel island in column j of the (m+n)-th partition to the subpixel in column (h+k / 4) includes a 10th transistor, an 11th transistor and a 12th transistor, where, The gate electrode of the first transistor is electrically connected to a first control signal terminal, the first electrode of the first transistor is electrically connected to the operational amplifier corresponding to the subpixel in the h-th column of the pixel island in the j-th column of the (m+n)-th partition, and the second electrode of the first transistor is electrically connected to the operational amplifier corresponding to the subpixel in the h-th column of the pixel island in the j-th column of the m-th partition. The gate electrode of the second transistor is electrically connected to the second control signal terminal, the first electrode of the second transistor is electrically connected to the second electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the first electrode of the seventh transistor. The gate electrode of the third transistor is electrically connected to the third control signal terminal, the first electrode of the third transistor is electrically connected to the first electrode of the first transistor, and the second electrode of the third transistor is electrically connected to the first electrode of the tenth transistor. The gate electrode of the fourth transistor is electrically connected to the fourth control signal terminal, 4 The first electrode of the transistor is electrically connected to the operational amplifier corresponding to the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the (m+n)th partition, and the 4 The second electrode of the transistor is electrically connected to the operational amplifier corresponding to the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the mth partition, The gate electrode of the fifth transistor is electrically connected to the fifth control signal terminal, the first electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is electrically connected to the first electrode of the eighth transistor. The gate electrode of the sixth transistor is electrically connected to the sixth control signal terminal, and the sixth of the sixth transistor 2 The electrode of the 11th transistor is electrically connected to the second electrode of the 6th transistor. 1 The electrode is electrically connected to the first electrode of the fourth transistor. The gate electrode of the seventh transistor is electrically connected to the seventh control signal terminal, and the second electrode of the seventh transistor is electrically connected to the data line corresponding to the h-th subpixel of the pixel island in the j-th column of the m-th partition. The gate electrode of the eighth transistor is electrically connected to the eighth control signal terminal, and the second electrode of the eighth transistor is electrically connected to the data line corresponding to the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the mth partition, The gate electrode of the ninth transistor is electrically connected to the ninth control signal terminal, and the first electrode of the ninth transistor is the 5 second electrode of the transistor is electrically connected, and the second electrode of the ninth transistor is electrically connected to the second electrode of the second transistor. The gate electrode of the tenth transistor is electrically connected to the tenth control signal terminal, and the second electrode of the tenth transistor is electrically connected to the data line corresponding to the sub-pixel at the h-th column of the pixel island in the j-th column within the (m + n)-th partition. The gate electrode of the eleventh transistor is electrically connected to the eleventh control signal terminal, and the second electrode of the eleventh transistor is electrically connected to the data line corresponding to the sub-pixel at the (h + k / 4)-th column of the pixel island in the j-th column within the (m + n)-th partition. The gate electrode of the twelfth transistor is electrically connected to the twelfth control signal terminal, the first electrode of the twelfth transistor is electrically connected to the second electrode of the sixth transistor, and the second electrode of the twelfth transistor is electrically connected to the second electrode of the third transistor.

[0015] In some embodiments, in the above display substrate provided by the embodiments of the present invention, the two data lines are connected between one operational amplifier and one column of sub-pixels, and one of the two data lines is connected to the sub-pixels in the odd rows of one column, and the other is connected to the sub-pixels in the even rows of one column.

[0016] In some embodiments, in the above display substrate provided by the embodiments of the present invention, the sub-pixels electrically connected to each of the first sub-multiplexing circuits are the sub-pixels in the even rows at the h-th column of the pixel island in the j-th column within the m-th partition, and the sub-pixels in the even rows at the h-th column of the pixel island in the j-th column within the (m + n)-th partition.

[0017] In some embodiments, in the above display substrate provided by the embodiments of the present invention, the first sub-multiplexing circuit includes a 13th transistor and a 14th transistor, where the gate electrode of the 13th transistor is electrically connected to a 13th control signal terminal, the first electrode of the 13th transistor is electrically connected to the operational amplifier corresponding to the sub-pixel at the h-th column of the pixel island in the j-th column within the m-th partition, and the second electrode of the 13th transistor is electrically connected to the data line corresponding to the sub-pixel at the even rows of the h-th column of the pixel island in the j-th column within the (m + n)-th partition. the gate electrode of the 14th transistor is electrically connected to a 14th control signal terminal, the first electrode of the 14th transistor is electrically connected to the operational amplifier corresponding to the sub-pixel at the h-th column of the pixel island in the j-th column within the (m + n)-th partition, and the second electrode of the 14th transistor is electrically connected to the data line corresponding to the sub-pixel at the even rows of the h-th column of the pixel island in the j-th column within the m-th partition.

[0018] In some embodiments, in the above display substrate provided by the embodiments of the present invention, the frame region further includes a plurality of gate circuits. Each of the gate circuits is connected between one of the operational amplifiers and two data lines corresponding to the operational amplifier.

[0019] In some embodiments, in the above display substrate provided by the embodiments of the present invention, the gate circuit includes a 15th transistor and a 16th transistor. the gate electrode of the 15th transistor is electrically connected to a 15th control signal terminal, the first electrode of the 15th transistor is electrically connected to one of the operational amplifiers, and the second electrode of the 15th transistor is electrically connected to one of the two data lines. The gate electrode of the 16th transistor is electrically connected to the 16th control signal terminal, the first electrode of the 16th transistor is electrically connected to one of the operational amplifiers, and the second electrode of the 16th transistor is electrically connected to the other of the two data lines.

[0020] In some embodiments, the display board provided by embodiments of the present invention further includes a source driver chip located in the frame region, the source driver chip comprising the plurality of gate circuits, the plurality of multiplexing circuits, and the plurality of operational amplifiers.

[0021] In some embodiments, in the display board provided by the embodiment of the present invention, k subpixels are arranged in a single row of each pixel island, where k is a multiple of 4. The multiplexing circuit includes a third submultiplexing circuit, and the subpixels electrically connected to the third submultiplexing circuit are the subpixels in the h-th column and the subpixels in the (h+k / 4)-th column of the pixel island in the same row, where h is an integer between 1 and k / 4, and an integer between (1+k / 4) and (k-4).

[0022] In some embodiments, in the display board provided by an embodiment of the present invention, one partition is formed for each of the i adjacent pixel islands in the row direction, and there are 2n partitions in the row direction, where i is an integer of 2 or more, and n is a positive integer. The multiplexing circuit further includes a fourth submultiplexing circuit, the fourth submultiplexing circuit connecting the m-th partition and the subpixels of the same sequence of pixel islands within the (m+n)-th partition, where m is an integer between 1 and n.

[0023] In some embodiments, in the display board provided by embodiments of the present invention, a third submultiplexing circuit connecting the subpixel in column h of the pixel island in column j of the m-th partition to the subpixel in column (h+k / 4) includes a 17th transistor, a 18th transistor, a 19th transistor, a 20th transistor, and a 21st transistor, where j is an integer between 1 and i. The third submultiplexing circuit connecting the subpixel in column h of the pixel island in column j of the (m+n)-th partition to the subpixel in column (h+k / 4) includes a 22nd transistor, a 23rd transistor, a 24th transistor, a 25th transistor, and a 26th transistor, The fourth submultiplexing circuit, which connects the subpixel of the h-th column of the pixel island in the j-th column within the m-th partition to the subpixel of the h-th column of the pixel island in the j-th column within the (m+n)-th partition, includes a 27th transistor, The fourth submultiplexing circuit connecting the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the m-th partition to the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the (m+n)-th partition includes a 28th transistor, where, The gate electrode of the 17th transistor is electrically connected to the 17th control signal terminal, the first electrode of the 17th transistor is electrically connected to the second electrode of the 18th transistor, and the second electrode of the 17th transistor is electrically connected to the data line corresponding to the h-th subpixel of the pixel island in the j-th column of the m-th partition. The gate electrode of the 18th transistor is electrically connected to the 18th control signal terminal, and the first electrode of the 18th transistor is electrically connected to the operational amplifier corresponding to the h-th subpixel of the pixel island in the j-th column of the m-th partition, The gate electrode of the 19th transistor is electrically connected to the 19th control signal terminal, the first electrode of the 19th transistor is electrically connected to the second electrode of the 20th transistor, and the second electrode of the 19th transistor is electrically connected to the data line corresponding to the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the mth partition. The gate electrode of the 20th transistor is The The first electrode of the 20 transistor is electrically connected to the 20 control signal terminals, and the first electrode of the 20 transistor is electrically connected to the operational amplifier corresponding to the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the mth partition, The gate electrode of the 21st transistor is The The first electrode of the 21st transistor is electrically connected to the control signal terminal of the 21st transistor, the second electrode of the 21st transistor is electrically connected to the second electrode of the 20th transistor, and the second electrode of the 21st transistor is electrically connected to the second electrode of the 18th transistor. The gate electrode of the 22nd transistor is The The first electrode of the 22 transistor is electrically connected to the control signal terminal of the 22 transistor, the first electrode of the 22 transistor is electrically connected to the second electrode of the 23 transistor, and the second electrode of the 22 transistor is electrically connected to the data line corresponding to the h-th subpixel of the pixel island in the j-th column of the (m+n)-th partition. The gate electrode of the 23rd transistor is The The first electrode of the 23 transistor is electrically connected to the control signal terminals of the 23 transistor, and the first electrode of the 23 transistor is electrically connected to the operational amplifier corresponding to the subpixel of the h-th column of the pixel island in the j-th column of the m-th partition, The gate electrode of the 24th transistor is TheThe transistor is electrically connected to 24 control signal terminals, the first electrode of the 24th transistor is electrically connected to the second electrode of the 25th transistor, and the second electrode of the 24th transistor is electrically connected to the data line corresponding to the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the mth partition. The gate electrode of the 25th transistor is The The first electrode of the 25th transistor is electrically connected to the 25th control signal terminal, and the first electrode of the 25th transistor is electrically connected to the operational amplifier corresponding to the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the mth partition, The gate electrode of the 26th transistor is The The 26th transistor is electrically connected to the 26th control signal terminal, the first electrode of the 26th transistor is electrically connected to the second electrode of the 25th transistor, and the second electrode of the 26th transistor is electrically connected to the second electrode of the 23rd transistor. The gate electrode of the 27th transistor is The The first electrode of the transistor 27 is electrically connected to the control signal terminal of 27, and the first electrode of the transistor 27 is electrically connected to the operational amplifier corresponding to the subpixel of the h-th column of the pixel island in the j-th column of the (m+n)-th partition, and the second electrode of the transistor 27 is electrically connected to the operational amplifier corresponding to the subpixel of the h-th column of the pixel island in the j-th column of the m-th partition, The gate electrode of the 28th transistor is The The transistor 28 is electrically connected to the control signal terminals of the 28, the first electrode of the 28 is electrically connected to the operational amplifier corresponding to the subpixel in the (h+k / 4)th column of the pixel island in the jth column of the (m+n)th partition, and the second electrode of the 28 is electrically connected to the operational amplifier corresponding to the subpixel in the (h+k / 4)th column of the pixel island in the jth column of the mth partition.

[0024] On the other hand, the driving method for the display board provided by the embodiment of the present invention is In multiplexing mode, to provide data signals output from at least two operational amplifiers to the subpixels in the same column electrically connected to the data lines via a conductive multiplexing circuit and the data lines, the steps include controlling the multiplexing circuit to conduct to one of the electrically connected data lines and disconnect from the other electrically connected data lines, The process includes the step of controlling the multiplexing circuit to disconnect from all electrically connected data lines in order to provide the data signals output from each operational amplifier to the subpixels in each row electrically connected to each operational amplifier in a one-to-one correspondence.

[0025] On the other hand, an embodiment of the present invention provides a display device including the display substrate described above, provided by one embodiment of the present invention. [Brief explanation of the drawing]

[0026] [Figure 1] This is a schematic diagram of a display board in conventional technology. [Figure 2] This is a schematic diagram of the display board provided by an embodiment of the present invention. [Figure 3] This is a schematic diagram of the partition structure. [Figure 4] This is a schematic diagram of the multiplexing of operational amplifiers corresponding to different partitions. [Figure 5] This figure shows the multiplexing of operational amplifiers corresponding to different partitions and the multiplexing of operational amplifiers corresponding to different subpixels within the same pixel island. [Figure 6] This is a schematic diagram of the multiplexing of operational amplifiers corresponding to different subpixels within the same pixel island. [Figure 7] Figure 4 is a schematic diagram of the first submultiplexing circuit. [Figure 8] Figure 5 shows schematic diagrams of the first submultiplexing circuit and the second multiplexing circuit. [Figure 9]This is a charging simulation diagram that uses an operational amplifier to provide data signals to subpixels within the same column. [Figure 10] This is a charging simulation diagram showing the use of two operational amplifiers to provide data signals to subpixels within the same column. [Figure 11] This is another multiplexing diagram of operational amplifiers corresponding to different partitions. [Figure 12] Figure 11 is a schematic diagram of the first submultiplexing circuit and gate circuit. [Figure 13] This is a multiplexing diagram of operational amplifiers corresponding to some of the subpixels in Figure 6. [Figure 14] This is a schematic diagram illustrating the multiplexing of operational amplifiers corresponding to different subpixels within the same pixel island, and the multiplexing of operational amplifiers corresponding to different partitions. [Figure 15] Figure 13 is a schematic diagram of the third submultiplexing circuit. [Figure 16] Figure 14 shows schematic diagrams of the third submultiplexing circuit and the fourth multiplexing circuit. [Figure 17] This is a flowchart of a method for driving a display board provided by an embodiment of the present invention. [Modes for carrying out the invention]

[0027] To further clarify the object, technical solution, and advantages of the embodiments of the present invention, the technical solution of the embodiments of the present invention is described below clearly and completely, together with the drawings of the embodiments of the present invention. Note that the size and shape of the figures in the drawings do not reflect actual proportions and are for illustrative purposes only. Also, the same or similar reference numerals throughout represent the same or similar elements, or elements having the same or similar function.

[0028] Unless otherwise defined, technical or scientific terms used herein have the ordinary meanings understood by those skilled in the art in the field to which this invention pertains. The terms “first,” “second,” and similar terms used in this invention and in the claims are not intended to indicate order, quantity, or importance, but are used solely to distinguish different components. Words such as “contains” or “includes” mean that the element or thing preceding the word includes, without exclusion, the elements or things listed after the word and their equivalents. “Inside,” “outside,” “top,” “bottom,” etc., are used solely to express relative positional relationships, and if the absolute position of the described object changes, the relative positional relationship may change accordingly.

[0029] Figure 1 shows the structure of a display board in the related technology, where each operational amplifier OP is electrically connected to a row of subpixels P, and the number of operational amplifiers OP corresponds to the number of subpixels P in one row. The operational amplifiers OP are used to amplify the data signal output by the source driver chip (Source IC) and provide it to the corresponding connected subpixel P. However, in 3D displays, the refresh rate of the human gaze area is faster than the refresh rate of the non-gaze area, or not all subpixels P are lit, so the amplifiers OP corresponding to the non-gaze area or unlit subpixel P are idle, resulting in wasted resources.

[0030] To solve the above-mentioned technical problems present in related technologies, embodiments of the present invention provide a display board as shown in Figures 2 to 4, which includes a base substrate 101, a plurality of pixel islands 102, a plurality of data lines 103, a plurality of operational amplifiers (OPs) 104, and a plurality of multiplexing circuits 105.

[0031] The base substrate 101 includes a display area AA and a frame area BB located on at least one side of the display area AA.

[0032] In the display area AA, multiple pixel islands 102, each having multiple subpixels P arranged in an array, are arranged in an array.

[0033] In the display area AA, the plurality of data lines 103 extend along the column direction Y and are arranged along the row direction X, and the data lines 103 are electrically connected to the subpixels P.

[0034] Multiple operational amplifiers (OPs) 104 are arranged in the frame region BB, and each operational amplifier 104 is electrically connected to a row of subpixels P via data lines 103.

[0035] The multiple multiplexing circuits 105 are located in the frame region BB, and each multiplexing circuit 105 is connected to at least two operational amplifiers 104. Subpixels P, which are electrically connected to each multiplexing circuit 105 via data lines 103, are located in at least two columns.

[0036] In the display board provided by the embodiment of the present invention, the multiplexing circuit 105 is controlled to conduct one of the data lines 103 electrically connected to it and disconnect the remaining data lines 103 electrically connected to it. This provides data signals output from at least two operational amplifiers OP to subpixels P in the same column electrically connected to the data lines 103 via the conducted multiplexing circuit 105 and data lines 103. In this way, the resource utilization of the operational amplifier 104 is improved by dynamically gating the idle operational amplifiers OP in the related technology via the multiplexing circuit 105.

[0037] Furthermore, in this invention, the multiplexing circuit 105 can also be controlled to disconnect from all data lines 103 electrically connected to it. This provides the data signals output from each operational amplifier 104 to the sub-pixels P of each electrically connected column corresponding to each operational amplifier 104 on a one-to-one basis. In this case, each operational amplifier 104 operates independently and is not multiplexed.

[0038] In some embodiments, all subpixels P in each pixel island 102 are located in 3 rows and at least 2 columns, and in each pixel island 102, the display color of subpixels P in the same row is the same, while the display color of subpixels P in different rows is different. For example, in Figure 3, each pixel island 102 can contain red subpixels r, green subpixels g, and blue subpixels b, where the number of red subpixels r, green subpixels g, and blue subpixels b is the same. The red subpixels r are arranged in one row along the row direction X, and the green subpixels g are arranged in one row along the row direction X. The blue subpixels b are arranged in one row along the row direction X. The rows of red subpixels, green subpixels, and blue subpixels are arranged along the column direction Y, so that the pixel island 102 and the subpixels P within the pixel island 102 are arranged in an array.

[0039] In some embodiments, the display board provided by embodiments of the present invention, as shown in Figures 2 to 4, has a partition Z formed for every two columns of adjacent pixel islands 102 in the row direction X. The multiplexing circuit includes a first submultiplexing circuit 1051, and each subpixel P electrically connected to the first submultiplexing circuit 1051 is located in at least two partitions Z, so that it can be reused as an operational amplifier 104 corresponding to a subpixel P in a different partition Z via the first submultiplexing circuit 1051.

[0040] To better understand the technical solution of the present invention, as an example for illustrative purposes, each first submultiplexing circuit 1051 is connected between two operational amplifiers 104 and data lines 103 electrically connected to the two operational amplifiers 104. Subpixels P electrically connected to each first submultiplexing circuit 1051 are located in two partitions Z.

[0041] In some embodiments, the display board provided by the embodiment of the present invention has 2n (e.g., 16) partitions Z in the row direction X, as shown in Figures 2 to 4. Here, n is a positive integer.

[0042] The 1st to the nth consecutive partitions constitute the gaze region W, and the (n+1)th to the 2nth consecutive partitions constitute the non-gaze region NW. Since the gaze region W is a continuous area, it can support half of the continuous area of ​​the display board.

[0043] The sub-pixels P electrically connected to each first sub-multiplexing circuit 1051 are located in the m-th and (m+n)-th partitions Z, where m is an integer between 1 and n (inclusive).

[0044] The m-th partition Z is in the gaze region W. position Furthermore, since the (m+n)th partition Z is located in the non-focused region NW, the non-focused region NW is not refreshed. When the focused region W is refreshed, the first submultiplexing circuit 1051 multiplexes the operational amplifier 104 corresponding to the (m+n)th partition Z in the non-focused region NW to the mth partition Z in the focused region W. As a result, the operational amplifier 104 corresponding to the (m+n)th partition Z supplies data signals to the subpixel P in the mth partition Z simultaneously with the operational amplifier 104 corresponding to the mth partition Z. This shortens the charging time and improves the charge level of the focused region W. Also, when both the focused region W and the non-focused region NW are refreshed, each uses its own operational amplifier 104; that is, they are not reused by each other.

[0045] In some embodiments, in the display board provided by the embodiment of the present invention, as shown in Figures 2 to 4, each partition Z includes i-row pixel islands 102, where i is an integer greater than or equal to 2. Sub-pixels P electrically connected to each first sub-multiplexing circuit 1051 are located at the j-th column pixel island 102 of the m-th partition and the j-th column pixel island 102 of the (m+n)-th partition. Here, j is an integer greater than or equal to 1 and less than or equal to i. With this configuration, the operational amplifier 104 corresponding to the j-th column pixel island 102 of the m-th partition and the operational amplifier 104 corresponding to the j-th column pixel island 102 of the (m+n)-th partition can be multiplexed with each other, and the wiring method can also be simplified.

[0046] In some embodiments, in the display board provided by embodiments of the present invention, as shown in Figures 2 to 4, each pixel island 102 is arranged in a single row with k subpixels P, where k is an even number. The subpixels P electrically connected to each first submultiplexing circuit 1051 are at least some of the subpixels P in the h column of the j column of the j-th pixel island in the m-th partition Z, and at least some of the subpixels P in the h column of the j-th column of the j-th pixel island in the (m+n)-th partition Z, where h is an integer between 1 and k / 4, and an integer between (1+k / 4) and (k-4). This configuration allows for the interconnection of operational amplifiers 104 corresponding to the subpixels P in the h column of the j-th pixel island 102 in the m-th partition Z and operational amplifiers 104 corresponding to the subpixels P in the h column of the j-th pixel island 102 in the (m+n)-th partition Z, and simplifies the wiring method.

[0047] In some embodiments, in the display board provided by embodiments of the present invention, as shown in Figures 2 to 4, one data line 103 is connected between one operational amplifier 104 and one row of subpixels P. In this case, the subpixels P electrically connected to each first submultiplexing circuit 1051 are the subpixels P in the h-th column of the j-th column pixel island in the m-th partition, and the subpixels P in the h-th column of the j-th column pixel island in the (m+n)-th partition.

[0048] In some embodiments, in the display board provided by embodiments of the present invention, the multiplexing circuit 105 may also include a second submultiplexing circuit 1052, as shown in Figure 5. Each second submultiplexing circuit 1052 is located between two rows of subpixels P in the same row of pixel island 102 and two first submultiplexing circuits 1051 corresponding to the two rows of subpixels P.

[0049] The second submultiplexing circuit 1052 can be reused as operational amplifiers 104 corresponding to two rows of subpixels P within the same row of pixel island 102. When the multiplexing circuit 105 has both the first submultiplexing circuit 1051 and the second submultiplexing circuit 1052, the first submultiplexing circuit 1051 can achieve multiplexing of operational amplifiers 104 corresponding to different partitions Z, and can also achieve multiplexing of operational amplifiers 104 corresponding to two rows of subpixels P within the same row of pixel island 102 within the same partition Z.

[0050] In some embodiments, as shown in Figures 5 and 6, in the display board provided by embodiments of the present invention, k is a multiple of 4, and h is an integer between 1 and k / 4, and an integer between (1+k / 4) and (k-4). The light rays emitted from the first subpixel P to the k / 2 subpixel P are focused to the left eye L to form the left eye's view. The light rays emitted from the 1+k / 2 subpixel P to the k subpixel P are focused to the right eye R to form the right eye's view, thereby realizing naked-eye 3D display. Optionally, each second submultiplexing circuit 1052 is electrically connected to the h-th column subpixel P and the (h+k / 4)-th column subpixel P of the same row of pixel island 102, respectively. Operational amplifiers 104 corresponding to the h-th column subpixel P and the (h+k / 4)-th column subpixel P of the same row of pixel island 102 can be multiplexed, respectively. This helps to simplify the wiring design.

[0051] In some embodiments, in the display board provided by embodiments of the present invention, as shown in Figures 7 and 8, a first submultiplexing circuit 1051 connecting the h-column subpixel P of the j-column pixel island 102 in the m-th partition Z and the h-column subpixel P of the j-column pixel island 102 in the (m+n)-th partition Z includes a first transistor M1, a second transistor M2, and a third transistor M3.

[0052] The first submultiplexing circuit 1051, which connects the subpixel P of the (h+k / 4)th column of the pixel island 102 in the mth partition Z and the subpixel P of the (h+k / 4)th column of the pixel island 102 in the jth column of the (m+n)th partition Z, includes a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6.

[0053] A second submultiplexing circuit 1052, which connects the h-column subpixel P and the (h+k / 4)-column subpixel P of the j-column pixel island 102 in the m-th partition Z, includes a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9.

[0054] A second submultiplexing circuit 1052, which connects the h-column subpixel P and the (h+k / 4)-column subpixel P of the j-column pixel island 102 in the (m+n)-th partition Z, includes a 16th transistor M10, an 11th transistor M11, and a 12th transistor M12.

[0055] Here, the gate electrode of the first transistor M1 is electrically connected to the first control signal terminal G1, the first electrode of the first transistor M1 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P in column h of the pixel island 102 in column j in the (m+n)th partition Z, and the second electrode of the first transistor M2 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P in column h of the pixel island 102 in column j in the mth partition Z. The gate electrode of the second transistor M2 is electrically connected to the second control signal terminal G2, the first electrode of the second transistor M2 is electrically connected to the second electrode of the first transistor M1, and the second electrode of the second transistor M2 is electrically connected to the first electrode of the seventh transistor M7. The gate electrode of the third transistor M3 is electrically connected to the third control signal terminal G3, the first electrode of the third transistor M3 is electrically connected to the first electrode of the first transistor M1, and the second electrode of the third transistor M3 is 10 It is electrically connected to the first electrode of transistor M10, The gate electrode of the fourth transistor M4 is electrically connected to the fourth control signal terminal G4, 4 The first electrode of transistor M1 is electrically connected to operational amplifier 104 corresponding to subpixel P in column (h+k / 4) of pixel island 102 in column j within partition Z (m+n), 4 The second electrode of transistor M1 is electrically connected to operational amplifier 104, which corresponds to the sub-pixel P of the (h+k / 4) column of the j-th column pixel island 102 in the m-th partition Z. The gate electrode of the fifth transistor M5 is electrically connected to the fifth control signal terminal G5, the first electrode of the fifth transistor M5 is electrically connected to the second electrode of the fourth transistor M4, and the second electrode of the fifth transistor M5 is electrically connected to the first electrode of the eighth transistor M8. The gate electrode of the sixth transistor M6 is electrically connected to the sixth control signal terminal G6, and the sixth transistor M6 2 The electrode of is electrically connected to the second electrode of the 11th transistor M11, and the electrode of the 6th transistor M6 1 The electrode is electrically connected to the first electrode of the fourth transistor M4. The gate electrode of the seventh transistor M7 is connected to the seventh control signal terminal G7, and the second electrode of the seventh transistor M7 is electrically connected to the data line 103 corresponding to the sub-pixel P in column h of the pixel island 102 in column j in the m-th partition Z. The gate electrode of the eighth transistor M8 is electrically connected to the eighth control signal terminal G8, and the second electrode of the eighth transistor M8 is electrically connected to the data line 103 corresponding to the (h+k / 4) column subpixel P of the j-th column pixel island 102 in the m-th partition Z. The gate electrode of the ninth transistor M9 is electrically connected to the ninth control signal terminal G9, and the first electrode of the ninth transistor M9 is 5 The second electrode of transistor M4 is electrically connected, and the second electrode of transistor M9 is electrically connected to the second electrode of transistor M2. The 10 The gate electrode of transistor M10 is 10 It is electrically connected to the control signal terminal G10, and 10 The second electrode of transistor M10 is electrically connected to the data line 103 corresponding to the subpixel P in column h of the pixel island 102 in column j in the (m+n)th partition Z. The gate electrode of the 11th transistor M11 is electrically connected to the 11th control signal terminal G11, and the second electrode of the 11th transistor M11 is electrically connected to the data line 103 corresponding to the sub-pixel P in the (h+k / 4) column of the j-th column pixel island 102 in the (m+n)-th partition Z. The gate electrode of the 12th transistor M12 is electrically connected to the 12th control signal terminal G12, the first electrode of the 12th transistor M12 is electrically connected to the second electrode of the 6th transistor M6, and the second electrode of the 12th transistor M12 is electrically connected to the second electrode of the 3rd transistor M3.

[0056] Assuming the display board provided by the present invention has a total of 16 partitions Z, for example, each partition Z has 30 pixel islands 102, and each pixel island 102 has 16 sub-pixels P. The total number of transistors included in all first submultiplexing circuits 1051 of the display board shown in Figures 4 and 7 is "3 (number of transistors included in each first submultiplexing circuit 1051) × 8 (8 groups of partitions) × 30 (30 pixel islands in one partition) × 16 (16 sub-pixels in one pixel island) = 11520". If the display state of the sub-pixels P in each partition Z is the same, "3 (number of transistors included in each first submultiplexing circuit 1051) × 8 (8 groups of partitions) × 16 (16 sub-pixels in one pixel island) = 384" control signal terminals are used to determine the switching state of the transistors. The total number of transistors included in all first submultiplexing circuits 1051 and second submultiplexing circuits 1052 of the display board shown in Figures 5 and 8 is "12 (number of transistors included in the two first submultiplexing circuits 1051 and the two second submultiplexing circuits 1052) × 8 ((8 groups in each pixel island)) × 30 (30 pixel islands in one partition) × 8 (partitions of 8 groups) = 23040". If the display state of the subpixels P in each partition Z is the same, the switching state of the transistors is determined using "12 (number of transistors included in the two first submultiplexing circuits 1051 and the two second submultiplexing circuits 1052) × 8 ((8 groups in each pixel island) × 8 (partitions of 8 groups) = 768" control signal terminals.

[0057] Specifically, Figures 7 and 8 show that the sub-pixels P of the first column of the first column pixel island 102 in the first partition Z and the sub-pixels P of the first column of the first column pixel island 102 in the ninth partition Z are electrically connected to the same first submultiplexing circuit 1051. The sub-pixels P of the fifth column of the first column pixel island 102 in the first partition Z and the sub-pixels P of the fifth column of the first column pixel island 102 in the ninth partition Z are electrically connected to another first submultiplexing circuit 1051. Furthermore, Figure 8 shows that the sub-pixels P of the first column and the sub-pixels P of the fifth column of the first column pixel island 102 in the first partition Z are electrically connected to the same second submultiplexing circuit 1052, and the sub-pixels P of the first column and the sub-pixels P of the fifth column of the first column pixel island 102 in the ninth partition Z are electrically connected to another second submultiplexing circuit 1052.

[0058] In some embodiments, 1 represents a high-level signal and 0 represents a low-level signal, with each transistor turning on under a high-level signal and off under a low-level signal. It should be noted that 1 and 0 are logic levels and are not voltages applied to the gate electrode of each transistor during a particular implementation, but are used solely to better illustrate the specific operating processes of embodiments of the invention.

[0059] Table 1 shows the operating states of the operational amplifier 104 corresponding to the sub-pixel P in the first column of the first column pixel island 102 in the first partition Z (i.e., OP1 in Table 1), and the operational amplifier 104 corresponding to the sub-pixel P in the first column of the first column pixel island 102 in the ninth partition Z (i.e., OP1' in Table 1), when each transistor in Figure 7 applies a different logic level. It also shows the operating states of the operational amplifier 104 corresponding to the sub-pixel P in the fifth column of the first column pixel island 102 in the first partition Z (i.e., OP5 in Table 1), and the operational amplifier 104 corresponding to the sub-pixel P in the fifth column of the first column pixel island 102 in the ninth partition Z (i.e., OP5' in Table 1).

[0060] As can be seen from Table 1 and Figure 7, when the first transistor M1 and the third transistor M3 are turned on, and the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are turned off, the operational amplifier 104 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the ninth partition Z (i.e., OP1' in Table 1) is reused as the operational amplifier 104 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the first partition Z (i.e., OP1 in Table 1). When the first transistor M1 and the second transistor M2 are turned on, and the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are turned off, the operational amplifier 104 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the first partition Z (i.e., OP1 in Table 1) is reused as the operational amplifier 104 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the ninth partition Z (i.e., OP1' in Table 1).

[0061] When the fourth transistor M4 and the sixth transistor M6 are turned on, and the first transistor M1, the second transistor M2, the third transistor M3, and the fifth transistor M5 are turned off, the operational amplifier 104 corresponding to the fifth subpixel P of the first column pixel island 102 in the ninth partition Z (i.e., OP5' in Table 1) is reused as the operational amplifier 104 corresponding to the fifth subpixel P of the first column pixel island 102 in the first partition Z (i.e., OP5 in Table 1). When the fourth transistor M4 and the fifth transistor M5 are turned on, and the first transistor M1, the second transistor M2, the third transistor M3, and the sixth transistor M6 are turned off, the operational amplifier 104 corresponding to the fifth subpixel P of the first column pixel island 102 in the first partition Z (i.e., OP5 in Table 1) is reused as the operational amplifier 104 corresponding to the fifth subpixel P of the first column pixel island 102 in the ninth partition Z (i.e., OP5' in Table 1).

[0062] When the first transistor M1, the third transistor M3, the fourth transistor M4, and the sixth transistor M6 are turned on, and the second transistor M2 and the fifth transistor M5 are turned off, the operational amplifier 104 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the ninth partition Z (i.e., OP1' in Table 1) is reused as the operational amplifier 104 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the first partition Z (i.e., OP1 in Table 1). Also, the operational amplifier 104 corresponding to the fifth subpixel P of the first column pixel island 102 in the ninth partition Z (i.e., OP5' in Table 1) is reused as the operational amplifier 104 corresponding to the fifth subpixel P of the first column pixel island 102 in the first partition Z (i.e., OP5 in Table 1). When the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 are turned on, and the third transistor M3 and the sixth transistor M6 are turned off, the operational amplifier 104 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the first partition Z (i.e., OP1 in Table 1) is reused as the operational amplifier 104 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the ninth partition Z (i.e., OP1' in Table 1). Also, the operational amplifier 104 corresponding to the fifth subpixel P of the first column pixel island 102 in the first partition Z (i.e., OP5 in Table 1) is reused as the operational amplifier 104 corresponding to the fifth subpixel P of the first column pixel island 102 in the ninth partition Z (i.e., OP5' in Table 1).

[0063] When the second transistor M2, the third transistor M3, the fifth transistor M5, and the sixth transistor M6 are turned on, and the first transistor M1 and the fourth transistor M4 are turned off, the operational amplifier 104 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the ninth partition Z (i.e., OP1' in Table 1) is not reused as the operational amplifier 104 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the first partition Z (i.e., OP1 in Table 1). Also, the operational amplifier 104 corresponding to the fifth subpixel P of the first column pixel island 102 in the ninth partition Z (i.e., OP5' in Table 1) is not reused as the operational amplifier 104 corresponding to the fifth subpixel P of the first column pixel island 102 in the first partition Z (i.e., OP5 in Table 1).

[0064] [Table 1]

[0065] Tables 2-1 and 2-2 show the operating states of the operational amplifier 104 corresponding to the subpixel P in the first column of the first column pixel island 102 in the first partition Z (i.e., OP1), and the operational amplifier 104 corresponding to the subpixel P in the first column of the first column pixel island 102 in the ninth partition Z (i.e., OP1'), when each transistor in Figure 8 applies a different logic level. The operating states of the operational amplifier 104 corresponding to the subpixel P in the fifth column of the first column pixel island 102 in the first partition Z (i.e., OP5), and the operational amplifier 104 corresponding to the subpixel P in the fifth column of the first column pixel island 102 in the ninth partition Z (i.e., OP5'). The operating states of the operational amplifiers 104 (i.e., OP1 and OP5) corresponding to the first column and the fifth column sub-pixels P of the first column pixel island 102 in the first partition Z, and the operating states of the operational amplifiers 104 (i.e., OP1' and OP5') corresponding to the first column and the fifth column sub-pixels P of the first column pixel island 102 in the ninth partition Z are shown.

[0066] As can be seen from Table 2-1 and Figure 8, when the second transistor M2, the fifth transistor M5, the seventh transistor M7, and the ninth transistor M9 among the first transistor M1 to the twelfth transistor M12 are turned on and the remaining transistors are turned off, the operational amplifier 104 (i.e., OP1) corresponding to the first subpixel P of the first column of the first column pixel island 102 in the first partition Z is reused as the operational amplifier 104 (i.e., OP5) corresponding to the fifth subpixel P of the first column of the first column pixel island 102 in the first partition Z. When the second transistor M2, the fifth transistor M5, the eighth transistor M8, and the ninth transistor M9 among the first transistor M1 to the twelfth transistor M12 are turned on and the remaining transistors are turned off, the operational amplifier 104 (i.e., OP5) corresponding to the first subpixel P of the first column of the first column pixel island 102 in the first partition Z is reused as the operational amplifier 104 (i.e., OP1) corresponding to the first subpixel P of the first column of the first column pixel island 102 in the first partition Z. When the second transistor M2, the fifth transistor M5, the seventh transistor M7, and the eighth transistor M8 among the first transistor M1 to the twelfth transistor M12 are turned on and the remaining transistors are turned off, the operational amplifier 104 (i.e., OP1) corresponding to the first subpixel P of the first column of the first column pixel island 102 in the first partition Z is not reused as the operational amplifier 104 (i.e., OP5) corresponding to the first subpixel P of the first column of the first column pixel island 102 in the first partition Z.

[0067] Of the first transistor M1 to the twelfth transistor M12, the third transistor M3, the sixth transistor M6, and the 10When transistors M10 and M12 turn on and the remaining transistors turn off, the operational amplifier 104 corresponding to the first sub-pixel P of the first column of the first column of the pixel island 102 in the ninth partition Z (i.e., OP1') is reused as the operational amplifier 104 corresponding to the fifth sub-pixel P of the first column of the pixel island 102 in the ninth partition Z (i.e., OP5'). Of the first to twelfth transistors M12, the third transistor M3, the sixth transistor M6, the eleventh transistor M11 and the twelfth transistor M12 turn on and the remaining transistors turn off, the operational amplifier 104 corresponding to the fifth sub-pixel P of the first column of the pixel island 102 in the ninth partition Z (i.e., OP5') is reused as the operational amplifier 104 corresponding to the first sub-pixel P of the first column of the pixel island 102 in the ninth partition Z (i.e., OP1'). Of the first transistor M1 to the twelfth transistor M12, the third transistor M3, the sixth transistor M6, and the 10 When transistors M10 and M11 turn on and the remaining transistors turn off, the operational amplifier 104 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the ninth partition Z (i.e., OP1') is not reused as the operational amplifier 104 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the ninth partition Z (i.e., OP5').

[0068] As can be seen from Table 2-2 and Figure 8, when the first transistor M1, the second transistor M2, and the seventh transistor M7 among the first to twelfth transistors M12 are turned on and the remaining transistors are turned off, the operational amplifier 104 (i.e., OP1) corresponding to the first subpixel P of the first column of the first column pixel island 102 in the first partition Z is reused as the operational amplifier 104 (i.e., OP1') corresponding to the first subpixel P of the first column of the first column pixel island 102 in the ninth partition Z. When the first transistor M1, the third transistor M3, and the sixteenth transistor M10 among the first to twelfth transistors M12 are turned on and the remaining transistors are turned off, the operational amplifier 104 (i.e., OP1') corresponding to the first subpixel P of the first column of the first column pixel island 102 in the ninth partition Z is reused as the operational amplifier 104 (i.e., OP1) corresponding to the first subpixel P of the first column of the first column pixel island 102 in the first partition Z.

[0069] When the fourth transistor M4, the fifth transistor M5, and the eighth transistor M8 of the first transistor M1 through the twelfth transistor M12 are turned on and the remaining transistors are turned off, the operational amplifier 104 (i.e., OP5) corresponding to the fifth subpixel P of the first column pixel island 102 in the first partition Z is reused as the operational amplifier 104 (i.e., OP5') corresponding to the fifth subpixel P of the first column pixel island 102 in the ninth partition Z. When the fourth transistor M4, the sixth transistor M6, and the eleventh transistor M11 of the first to twelfth transistors M12 are turned on and the remaining transistors are turned off, the operational amplifier 104 (i.e., OP5') corresponding to the fifth subpixel P of the first column pixel island 102 in the ninth partition Z is reused as the operational amplifier 104 (i.e., OP5) corresponding to the fifth subpixel P of the first column pixel island 102 in the first partition Z.

[0070] When the first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, and the eighth transistor M8 of the first transistors M12 are turned on and the remaining transistors are turned off, the operational amplifier 104 corresponding to the first subpixel P of the first column of the first column of the pixel island 102 in the first partition Z (i.e., OP1) is reused as the operational amplifier 104 corresponding to the first subpixel P of the first column of the pixel island 102 in the ninth partition Z (i.e., OP1'), and the operational amplifier 104 corresponding to the fifth subpixel P of the first column of the pixel island 102 in the first partition Z (i.e., OP5) is reused as the operational amplifier 104 corresponding to the fifth subpixel P of the first column of the pixel island 102 in the ninth partition Z (i.e., OP5'). When the first transistor M1, the third transistor M3, the fourth transistor M4, the sixth transistor M6, the sixteenth transistor M10, and the eleventh transistor M11 among the first to twelfth transistors M12 are turned on and the remaining transistors are turned off, the operational amplifier 104 corresponding to the first subpixel P of the first column of the first column of the pixel island 102 in the ninth partition Z (i.e., OP1') is reused as the operational amplifier 104 corresponding to the first subpixel P of the first column of the pixel island 102 in the first partition Z (i.e., OP1), and the operational amplifier 104 corresponding to the fifth subpixel P of the first column of the pixel island 102 in the ninth partition Z (i.e., OP5') is reused as the operational amplifier 104 corresponding to the fifth subpixel P of the first column of the pixel island 102 in the first partition Z (i.e., OP5).

[0071] Of the first transistor M1 to the twelfth transistor M12, the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, 10When transistors M10 and the 11th transistor M11 are turned on and the remaining transistors are turned off, the operational amplifier 104 corresponding to the first subpixel P of the first column of the first column of the pixel island 102 in the first partition Z (i.e., OP1), the operational amplifier 104 corresponding to the fifth subpixel P of the first column of the pixel island 102 in the first partition Z (i.e., OP5), the operational amplifier 104 corresponding to the first subpixel P of the first column of the pixel island 102 in the 9th partition Z (i.e., OP1'), and the operational amplifier 104 corresponding to the fifth subpixel P of the first column of the pixel island 102 in the 9th partition Z (i.e., OP5') are not reused.

[0072] [Table 2-1] [Table 2-2]

[0073] Figure 9 shows a charging simulation diagram using one operational amplifier 104 to provide a data signal to subpixel P. Figure 10 shows a charging simulation diagram using two operational amplifiers 104 (i.e., in the case of multiplexing) to provide a data signal to subpixel P. In comparison, it can be seen that the time it takes for one operational amplifier 104 to charge to 90% is 243.846 ns, while the time it takes for two operational amplifiers 104 to charge to 90% is reduced to 136.755 ns. Therefore, the present invention can reduce the charging time and thereby increase the charge rate.

[0074] In some embodiments, in the display board provided by embodiments of the present invention, operational amplifiers 104 can be connected to two data lines 103 between columns of subpixels P, as shown in Figures 11 and 12. One of the two data lines 103 connects the subpixels P of odd-numbered rows in a column, and the other connects the subpixels P of even-numbered rows in a column. In this case, the subpixels P electrically connected to each first submultiplexing circuit 1051 are the subpixels P of even-numbered rows in the h-th column of the j-th column of the pixel island 102 in the m-th partition Z, and the subpixels P of even-numbered rows in the h-th column of the j-th column of the pixel island 102 in the (m+n)-th partition Z. Therefore, the data signal provided by the operational amplifier 104 corresponding to the sub-pixel P in the h column of the j-th column pixel island 102 in the m-th partition Z can be written via the first sub-multiplexing circuit 1051 to the even-numbered sub-pixel P in the h column of the j-th column pixel island 102 in the (m+n)-th partition Z, or the data signal provided by the operational amplifier 104 corresponding to the sub-pixel P in the h column of the j-th column pixel island 102 in the (m+n)-th partition Z can be written via the first sub-multiplexing circuit 1051 to the even-numbered sub-pixel P in the h column of the j-th column pixel island 102 in the m-th partition Z. This reduces the frame charging time and improves the frame rate. In Figures 11 and 12, P1 represents the sub-pixel P in the first column of the first column pixel island 102 in partition Z, and P1' represents the sub-pixel P in the first column of the first column pixel island 102 in the ninth partition Z.

[0075] In some embodiments, in the display board provided by embodiments of the present invention, as shown in Figure 12, the first submultiplexing circuit 1051 includes a 13th transistor M13 and a 14th transistor M14.

[0076] Here, the gate electrode of the 13th transistor M13 is electrically connected to the 13th control signal terminal G13, the first electrode of the 13th transistor M13 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P in the h column of the j-th column pixel island 102 in the m-th partition Z, and the second electrode of the 13th transistor M13 is electrically connected to the data line 103 corresponding to the sub-pixel P in the even row of the h column of the j-th column pixel island 102 in the (m+n)-th partition Z. The gate electrode of the 14th transistor M14 is electrically connected to the 14th control signal terminal G14, the first electrode of the 14th transistor M14 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P in the h column of the j-th column pixel island 102 in the (m+n)th partition Z, and the second electrode of the 14th transistor M14 is electrically connected to the data line 103 corresponding to the sub-pixel P in the even row of the h column of the j-th column pixel island 102 in the m-th partition Z.

[0077] In some embodiments, the display board provided by the embodiment of the present invention further includes a plurality of gate circuits 106 located in the frame region BB, as shown in Figure 11 or Figure 12. Each gate circuit 106 is connected between one operational amplifier 104 and two data lines 103 corresponding to the operational amplifier 104. The gate circuits 106, in cooperation with the first submultiplexing circuit 105, can realize different row multiplexing of the operational amplifier 104 in different partitions Z.

[0078] In some embodiments, in the display board provided by embodiments of the present invention, the gate circuit 106 includes a 15th transistor M15 and a 16th transistor M16, as shown in Figure 12.

[0079] Here, the gate electrode of the 15th transistor M15 is electrically connected to the 15th control signal terminal G15, the first electrode of the 15th transistor M15 is electrically connected to one operational amplifier 104, and the second electrode of the 15th transistor M15 is electrically connected to one of the two data lines 103. The gate electrode of the 16th transistor M16 is electrically connected to the 16th control signal terminal G16, the first electrode of the 16th transistor M16 is electrically connected to one operational amplifier 104, and the second electrode of the 16th transistor M16 is electrically connected to the other of the two data lines 106.

[0080] Assuming the display board provided by the present invention has a total of 16 partitions Z, for example, each partition Z has 30 rows of pixel islands 102, and each pixel island 102 has 16 sub-pixels P. In Figures 11 and 12, the total number of transistors included in all first submultiplexing circuits 1051 and gate circuits 106 of the display board is "6 (number of transistors corresponding to every 2 rows of pixels) × 16 (16 partitions) × 30 (30 pixel islands in one partition) × 8 (sub-pixels in 8 groups in one pixel island) = 23040". If the display state of the sub-pixels P in each partition Z is the same, the switching state of the transistors is determined using "6 (number of transistors corresponding to every 2 rows of pixels) × 16 (16 partitions) × 8 (sub-pixels in 8 groups in one pixel island) = 768" control signal terminals.

[0081] Specifically, Figure 12 shows that the sub-pixels P of the first column of the first column pixel island 102 in the first partition Z are electrically connected to the first submultiplexing circuit 1051 via two data lines 103 and a gate circuit 106, and the sub-pixels P of the first column of the first column pixel island 102 in the ninth partition Z are electrically connected to the same first submultiplexing circuit 1051 via two data lines 103 and another gate circuit 106.

[0082] In some embodiments, 1 represents a high-level signal and 0 represents a low-level signal, with each transistor turning on under a high-level signal and off under a low-level signal. It should be noted that 1 and 0 are logic levels and are used solely to better illustrate the specific operating processes of embodiments of the invention, and are not voltages applied to the gates of each transistor during a particular implementation.

[0083] Table 3 shows the operating states of the operational amplifier 104 corresponding to the subpixel P of the first column of the first column pixel island 102 in the first partition Z (i.e., OP1) and the operational amplifier 104 corresponding to the subpixel P of the first column of the first column pixel island 102 in the ninth partition Z (i.e., OP1') when each transistor in Figure 12 applies a different logic level.

[0084] As can be seen from Table 3 and Figure 12, when the 14th transistor M14 and the 15th transistor M15 of the gate circuit 106 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the first partition Z are turned on, and the 16th transistor M16 of the gate circuit 106 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the first partition Z, and the 15th transistor M15 (i.e., M15' in Table 3) and the 16th transistor M16 (i.e., M16' in Table 3) of the gate circuit 106 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the ninth partition Z are turned off, the operational amplifier 104 (i.e., OP1) corresponding to the even-numbered rows of the first column of the first column pixel island 102 in the first partition Z is reused as the operational amplifier 104 (i.e., OP1') corresponding to the first subpixel P of the first column of the first column pixel island 102 in the ninth partition Z.

[0085] When the 13th transistor M13 and the 15th transistor M15 (i.e., M15') of gate circuit 106 are turned on for the 1st subpixel P of the 1st column of the 1st column pixel island 102 in the 9th partition Z, and the 15th transistor M15 and the 16th transistor M16 of gate circuit 106 corresponding to the 1st subpixel P of the 1st column of the 1st column pixel island 102 in the 1st partition Z, and the 16th transistor M16 (i.e., M16') of gate circuit 106 corresponding to the 1st subpixel P of the 1st column of the 1st column pixel island 102 in the 9th partition Z are turned off, the operational amplifier 104 (i.e., OP1') corresponding to the even-numbered rows of the 1st column of the 1st column pixel island 102 in the 9th partition Z is repurposed as the operational amplifier 104 (i.e., OP1) corresponding to the 1st subpixel P of the 1st column of the 1st column pixel island 102 in the 1st partition Z.

[0086] When reused, the gate scan signal (Gate) must be loaded simultaneously into the odd-numbered subpixels P and the subsequent even-numbered subpixels, reducing the charging time per frame and improving the frame rate.

[0087] When the 15th transistor M15 and the 16th transistor M16 of gate circuit 106 are turned on for the sub-pixels P in the first column of the first column pixel island 102 in the first partition Z, and the 15th transistor M15 (i.e., M15') and the 16th transistor M16 (i.e., M16') of gate circuit 106 corresponding to the sub-pixels P in the first column of the first column pixel island 102 in the ninth partition Z are turned on, and the 13th transistor M13 and the 14th transistor M14 are turned off, the operational amplifier 104 (i.e., OP1) corresponding to the sub-pixels P in the even-numbered rows of the first column of the first column pixel island 102 in the first partition Z, and the operational amplifier 104 (i.e., OP1') corresponding to the sub-pixels P in the even-numbered rows of the first column of the first column pixel island 102 in the ninth partition Z are not reused. Furthermore, the 15th transistor M15 of the gate circuit 106 corresponding to the first sub-pixel P of the first column of the first column pixel island 102 in the first partition Z, and the 15th transistor M15 of the gate circuit 106 corresponding to the first sub-pixel P of the first column of the first column pixel island 102 in the ninth partition Z (i.e., M15') are simultaneously turned on, thereby supplying data signals from the operational amplifier 104 corresponding to the first sub-pixel P of the first column of the first column pixel island 102 in the first partition Z (i.e., OP1), and the operational amplifier 104 corresponding to the first sub-pixel P of the first column of the first column pixel island 102 in the ninth partition Z (i.e., OP1') to the odd-numbered sub-pixels P. Transistor M16 of gate circuit 106 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the first partition Z, and transistor M16 of gate circuit 106 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the ninth partition Z (i.e., M16') are simultaneously turned on, thereby supplying data signals from operational amplifier 104 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the first partition Z (i.e., OP1), and operational amplifier 104 corresponding to the first subpixel P of the first column of the first column pixel island 102 in the ninth partition Z (i.e., OP1') to the subpixel P of the even-numbered rows.

[0088] [Table 3]

[0089] In some embodiments, in the display board provided by embodiments of the present invention, as shown in Figure 13, each pixel island 102 is arranged in a single row with k subpixels P, where k is a multiple of 4. The multiplexing circuit 105 includes a third submultiplexing circuit 1053. The subpixels P electrically connected to the third submultiplexing circuit 1053 are the h-th column subpixel P and the (h+k / 4)-th column subpixel P in the same row of pixel island 102, where h is an integer between 1 and k / 4, and an integer between (1+k / 4) and (k-4). The operational amplifier 104 corresponding to the h-th column subpixel P of the same row of pixel island 102 and the operational amplifier 104 corresponding to the (h+k / 4)-th column subpixel P can be multiplexed, respectively. This helps to simplify the wiring design.

[0090] In some embodiments, as shown in Figures 2, 3, and 14, the display board provided by embodiments of the present invention forms one partition Z for each i-column adjacent pixel island 102 in the row direction, so that there are 2n partition Zs in the row direction X, where i is an integer greater than or equal to 2 and n is a positive integer. The multiplexing circuit 105 further includes a fourth submultiplexing circuit 1054. The fourth submultiplexing circuit 1054 connects the m-th partition Z and the (m+n)-th partition Z sub-pixel P of the same sequence (e.g., the j-th column, where j is an integer greater than or equal to 1 and less than or equal to i) of the pixel island 102, where m is an integer greater than or equal to 1 and less than or equal to n. This configuration not only enables the intermultiplexing of operational amplifiers 104 corresponding to each of the sub-pixel P of the same sequence of the pixel island 102 in the m-th partition Z and the (m+n)-th partition Z, but also simplifies the wiring.

[0091] In some embodiments, in the display board provided by embodiments of the present invention, as shown in Figures 15 and 16, a third submultiplexing circuit 1053 connecting the h-column subpixel P and the (h+k / 4)-column subpixel P of the j-column pixel island 102 in the m-th partition Z includes a 17th transistor M17, a 18th transistor M18, a 19th transistor M19, a 20th transistor M20, and a 21st transistor M21, where j is an integer between 1 and i.

[0092] A third submultiplexing circuit 1053 connecting the h-column subpixel P and the (h+k / 4)-column subpixel P of the j-column pixel island 102 in the (m+n)-th partition Z includes a 22nd transistor M22, a 23rd transistor M23, a 24th transistor M24, a 25th transistor M25, and a 26th transistor M26.

[0093] A fourth submultiplexing circuit 1054, which connects the subpixel P in the h column of the j-th column pixel island 102 in the m-th partition Z and the subpixel P in the h column of the j-th column pixel island 102 in the (m+n)-th partition Z, includes a 27th transistor M27.

[0094] A fourth submultiplexing circuit 1054, which connects the subpixel P of the (h+k / 4)th column of the pixel island 102 in the (m-th)th column within the m-th partition Z with the subpixel P of the (h+k / 4)th column of the pixel island 102 in the (m+n)th partition Z, includes a 28th transistor M28.

[0095] Here, the gate electrode of the 17th transistor M17 is electrically connected to the 17th control signal terminal G17, the first electrode of the 17th transistor M17 is electrically connected to the second electrode of the 18th transistor M18, and the second electrode of the 17th transistor M17 is electrically connected to the data line 103 corresponding to the sub-pixel P in column h of the j-th pixel island 102 in the m-th partition Z. The gate electrode of the 18th transistor M18 is electrically connected to the 18th control signal terminal G18, and the first electrode of the 18th transistor M18 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P in column h of the j-th pixel island 102 in the m-th partition Z. The gate electrode of the 19th transistor M19 is electrically connected to the 19th control signal terminal G19, the first electrode of the 19th transistor M19 is electrically connected to the second electrode of the 20th transistor M20, and the second electrode of the 19th transistor M19 is electrically connected to the data line 103 corresponding to the (h+k / 4) column subpixel P of the j-th column pixel island 102 in the m-th partition Z. The gate electrode of the 20th transistor M20 is The The first electrode of the 20th transistor M20 is electrically connected to the 20th control signal terminal G20, and the first electrode of the 20th transistor M20 is electrically connected to the operational amplifier 104 corresponding to the (h+k / 4) column subpixel P of the j-th column pixel island 102 in the m-th partition Z. The gate electrode of transistor M21, the 21st transistor, is The The first electrode of the 21st transistor M21 is electrically connected to the control signal terminal G21, the first electrode of the 21st transistor M21 is electrically connected to the second electrode of the 20th transistor M20, and the second electrode of the 21st transistor M21 is electrically connected to the second electrode of the 18th transistor M18. The gate electrode of transistor M22 is The The first electrode of the 22nd transistor M22 is electrically connected to the control signal terminal G22, the first electrode of the 22nd transistor M22 is electrically connected to the second electrode of the 23rd transistor M23, and the second electrode of the 22nd transistor M22 is electrically connected to the data line 103 corresponding to the sub-pixel P in column h of the j-th pixel island 102 in the (m+n)th partition Z. The gate electrode of transistor M23, the 23rd transistor, is The The first electrode of the 23rd transistor M23 is electrically connected to the control signal terminal G23, and the first electrode of the 23rd transistor M23 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P in column h of the pixel island 102 in column j in the m-th partition Z. The gate electrode of transistor M24 is The The 24th transistor M24 is electrically connected to the control signal terminal G24, the first electrode of the 24th transistor M24 is electrically connected to the second electrode of the 25th transistor M25, and the second electrode of the 24th transistor M24 is electrically connected to the data line 103 corresponding to the sub-pixel P of the (h+k / 4) column of the j-th column pixel island 102 in the m-th partition Z. The gate electrode of transistor M25, the 25th transistor, is The The first electrode of the 25th transistor M25 is electrically connected to the control signal terminal G25, and the first electrode of the 25th transistor M25 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P of the (h+k / 4) column of the j-th column pixel island 102 in the m-th partition Z. The gate electrode of transistor M26, the 26th transistor, is The The 26th transistor M26 is electrically connected to the control signal terminal G26, the first electrode of the 26th transistor M26 is electrically connected to the second electrode of the 25th transistor M25, and the second electrode of the 26th transistor M26 is electrically connected to the second electrode of the 23rd transistor M23. The gate electrode of transistor M27, the 27th transistor, is The The first electrode of the 27th transistor M27 is electrically connected to the control signal terminal G27, and the first electrode of the 27th transistor M27 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P in the h column of the j-th column pixel island 102 in the (m+n)th partition Z, and the second electrode of the 27th transistor M27 is electrically connected to the operational amplifier 104 corresponding to the sub-pixel P in the h column of the j-th column pixel island 102 in the m-th partition Z, The gate electrode of transistor M28, the 28th transistor, is The The 28th transistor M28 is electrically connected to the control signal terminal G28. The first electrode of the 28th transistor M28 is electrically connected to the operational amplifier 104 corresponding to the (h+k / 4) column subpixel P of the j-th column pixel island 102 in the (m+n)-th partition Z. The second electrode of the 28th transistor M28 is electrically connected to the operational amplifier 104 corresponding to the (h+k / 4) column subpixel P of the j-th column pixel island 102 in the m-th partition Z.

[0096] Assuming the display board provided by the present invention has a total of 16 partitions Z, for example, each partition Z has 30 rows of pixel islands 102, and each pixel island 102 has 16 sub-pixels P. The total number of transistors included in all third submultiplexing circuits 1053 of the display board shown in Figures 13 and 15 is "5 (number of transistors included in each third submultiplexing circuit 1051) × 8 (number of sub-pixel rows of 8 groups in one pixel island) × 30 (30 pixel islands in one partition) × 16 (16 partitions) = 19200". If the display state of the sub-pixels P in each partition Z is the same, the switching state of the transistors is determined using "55 (number of transistors included in each third submultiplexing circuit 1051) × 8 (number of sub-pixel rows of 8 groups in one pixel island) × 16 (16 partitions) = 640" control signal terminals. The total number of transistors in all third submultiplexing circuits 1054 and fourth submultiplexing circuits 1054 of the display board shown in Figures 14 and 16 is "12 (number of transistors in two third submultiplexing circuits 1053 and two fourth submultiplexing circuits 1054) × 8 ((8 groups in each pixel island) × 30 (30 pixel islands in one partition) × 8 (partitions of 8 groups) = 23040". If the display state of subpixels P in each partition Z is the same, the switching state of the transistors is determined using "12 (number of transistors in two first submultiplexing circuits 1051 and two second submultiplexing circuits 1052) × 8 ((8 groups in each pixel island) × 8 (partitions of 8 groups) = 768" control signal terminals.

[0097] Specifically, Figure 15 shows that the sub-pixels P of the first column and the sub-pixels P of the fifth column of the pixel island 102 in the first partition Z are electrically connected to the same third submultiplexing circuit 1053.

[0098] In some embodiments, 1 represents a high-level signal and 0 represents a low-level signal, with each transistor turning on under a high-level signal and off under a low-level signal. It should be noted that 1 and 0 are logic levels and are not voltages applied to the gate of each transistor during a particular implementation, but are used solely to better illustrate the specific operating processes of embodiments of the invention.

[0099] Table 4 shows the operating states of the operational amplifier 104 corresponding to the subpixel P in the first column of the first column pixel island 102 in the first partition Z (i.e., OP1) and the operational amplifier 104 corresponding to the subpixel P in the fifth column of the first column pixel island 102 in the first partition Z (i.e., OP5) when each transistor in Figure 15 applies a different logic level.

[0100] As can be seen from Table 4 and Figure 15, when the 17th transistor M17, the 18th transistor M18, the 20th transistor M20, and the 21st transistor M21 are turned on and the 19th transistor M19 is turned off, the operational amplifier 104 (i.e., OP1) corresponding to the first subpixel P of the first column of the first column pixel island 102 in the first partition Z is reused as the operational amplifier 104 (i.e., OP5) corresponding to the fifth subpixel P of the first column of the first column pixel island 102 in the first partition Z. When the 18th transistor M18, the 19th transistor M19, the 20th transistor M20, and the 21st transistor M21 are turned on and the 17th transistor M17 is turned off, the operational amplifier 104 corresponding to the 5th subpixel P of the 1st column pixel island 102 in the 1st partition Z (i.e., OP5) is reused as the operational amplifier 104 corresponding to the 1st subpixel P of the 1st column pixel island 102 in the 1st partition Z (i.e., OP1). When the 17th transistor M17, the 18th transistor M18, the 19th transistor M19, and the 20th transistor M20 are turned on and the 21st transistor M21 is turned off, the operational amplifier 104 corresponding to the first sub-pixel P of the first column of the first column pixel island 102 in the first partition Z (i.e., OP1), and the operational amplifier 104 corresponding to the fifth sub-pixel P of the first column of the first column pixel island 102 in the first partition Z (i.e., OP5) are not reused.

[0101] [Table 4]

[0102] Tables 5-1 and 5-2 show the operating states of the operational amplifier 104 corresponding to the subpixel P in the first column of the first column pixel island 102 in the first partition Z (i.e., OP1), and the operational amplifier 104 corresponding to the subpixel P in the first column of the first column pixel island 102 in the ninth partition Z (i.e., OP1'), when each transistor in Figure 16 applies a different logic level. The operating states of the operational amplifier 104 corresponding to the subpixel P in the fifth column of the first column pixel island 102 in the first partition Z (i.e., OP5), and the operational amplifier 104 corresponding to the subpixel P in the fifth column of the first column pixel island 102 in the ninth partition Z (i.e., OP5'). The operating states of operational amplifiers 104 (i.e., OP1 and OP5) corresponding to the first column and fifth column sub-pixels P of the first column pixel island 102 in the first partition Z are shown, and the operating states of operational amplifiers 104 (i.e., OP1' and OP5') corresponding to the first column and fifth column sub-pixels P of the first column pixel island 102 in the ninth partition Z are shown.

[0103] As can be seen from Table 5-1 and Figure 16, when transistors M17, M18, M20, and M21 of the 17th to 28th transistors M17, are turned on and the remaining transistors are turned off, the operational amplifier 104 (i.e., OP1) corresponding to the first subpixel P of the first column of the first column pixel island 102 in the first partition Z is reused as the operational amplifier 104 (i.e., OP5) corresponding to the fifth subpixel P of the first column of the first column pixel island 102 in the first partition Z. When transistors M18, M19, M20, and M21 (among the 17th to 28th transistors M28) are turned on and the remaining transistors are turned off, the operational amplifier 104 (i.e., OP5) corresponding to the first sub-pixel P of the first column of the first column of the pixel island 102 in the first partition Z is reused as the operational amplifier 104 (i.e., OP1) corresponding to the first sub-pixel P of the first column of the first column of the pixel island 102 in the first partition Z. When transistors M17, M18, M19, and M20 of the 17th to 28th transistors M28 are turned on and the remaining transistors are turned off, the operational amplifier 104 corresponding to the first sub-pixel P of the first column of the first column pixel island 102 in the first partition Z (i.e., OP1), and the operational amplifier 104 corresponding to the first sub-pixel P of the first column of the first column pixel island 102 in the first partition Z (i.e., OP5) are not reused.

[0104] When transistors 22 (M22), 23 (M23), 25 (M25), and 26 (M26) of the 17th to 28th transistors M17, are turned on and the remaining transistors are turned off, the operational amplifier 104 (i.e., OP1') corresponding to the first subpixel P of the first column of the first column pixel island 102 in the 9th partition Z is reused as the operational amplifier 104 (i.e., OP5') corresponding to the fifth subpixel P of the first column of the first column pixel island 102 in the 9th partition Z. When transistors 23 (M23), 24 (M24), 25 (M25), and 26 (M26) of the 17th to 28th transistors M17, are turned on and the remaining transistors are turned off, the operational amplifier 104 corresponding to the sub-pixel P of the 5th column of the 1st column pixel island 102 in the 9th partition Z (i.e., OP5') is reused as the operational amplifier 104 corresponding to the sub-pixel P of the 1st column of the 1st column pixel island 102 in the 9th partition Z (i.e., OP1'). When transistors 22 (M22), 23 (M23), 24 (M24), and 25 (M25) of the 17th transistor M17 through the 28th transistor M28 are turned on and the remaining transistors are turned off, the operational amplifier 104 corresponding to the first sub-pixel P of the first column of the first column pixel island 102 in the 9th partition Z (i.e., OP1') and the operational amplifier 104 corresponding to the first sub-pixel P of the first column of the first column pixel island 102 in the 9th partition Z (i.e., OP5') are not reused.

[0105] As can be seen from Table 5-2 and Figure 16, when transistors M17, M18, and M27 are turned on and the remaining transistors are turned off, the operational amplifier 104 (i.e., OP1) corresponding to the first sub-pixel P of the first column of the first column pixel island 102 in the first partition Z is reused as the operational amplifier 104 (i.e., OP1') corresponding to the first sub-pixel P of the first column of the first column pixel island 102 in the ninth partition Z. When transistors 22 (M22), 23 (M23), and 27 (M27) of the 17th to 28th transistors M17, are turned on and the remaining transistors are turned off, the operational amplifier 104 (i.e., OP1') corresponding to the first sub-pixel P of the first column of the first column pixel island 102 in the 9th partition Z is reused as the operational amplifier 104 (i.e., OP1) corresponding to the first sub-pixel P of the first column of the first column pixel island 102 in the first partition Z.

[0106] When transistors M19 (19th), M20 (20th), and M28 (28th) of the 17th to 28th transistors M17 are turned on and the remaining transistors are turned off, the operational amplifier 104 (i.e., OP5) corresponding to the subpixel P in the 5th column of the first column pixel island 102 in the first partition Z is reused as the operational amplifier 104 (i.e., OP5') corresponding to the subpixel P in the 5th column of the first column pixel island 102 in the 9th partition Z. When transistors 24 (M24), 25 (M25), and 28 (M28) of the 17th to 28th transistors M17, are turned on and the remaining transistors are turned off, the operational amplifier 104 (i.e., OP5') corresponding to the sub-pixel P of the 5th column of the 1st column pixel island 102 in the 9th partition Z is reused as the operational amplifier 104 (i.e., OP5) corresponding to the sub-pixel P of the 5th column of the 1st column pixel island 102 in the 1st partition Z.

[0107] When transistors M17, M18, M19, M20, M27, and M28 of the 17th to 28th transistors M28 are turned on and the remaining transistors are turned off, the operational amplifier 104 corresponding to the first sub-pixel P of the first column of the first column of the pixel island 102 in the first partition Z (i.e., OP1) is reused as the operational amplifier 104 corresponding to the first sub-pixel P of the first column of the pixel island 102 in the 9th partition Z (i.e., OP1'), and the operational amplifier 104 corresponding to the fifth sub-pixel P of the first column of the pixel island 102 in the first partition Z (i.e., OP5) is reused as the operational amplifier 104 corresponding to the fifth sub-pixel P of the first column of the pixel island 102 in the 9th partition Z (i.e., OP5'). When transistors 22 (M22), 23 (M23), 24 (M24), 25 (M25), 27 (M27), and 28 (M28) of the 17th to 28th transistors M17, are turned on and the remaining transistors are turned off, the operational amplifier 104 corresponding to the first sub-pixel P of the first column of the first column of the pixel island 102 in the 9th partition Z (i.e., OP1') is reused as the operational amplifier 104 corresponding to the first sub-pixel P of the first column of the pixel island 102 in the first partition Z (i.e., OP1), and the operational amplifier 104 corresponding to the fifth sub-pixel P of the first column of the pixel island 102 in the 9th partition Z (i.e., OP5') is reused as the operational amplifier 104 corresponding to the fifth sub-pixel P of the first column of the pixel island 102 in the first partition Z (i.e., OP5).

[0108] Of the 17th transistor M17 to the 28th transistor M28, the 17th transistor M17, the 18th transistor M18, the 19th transistor M19, the 20th transistor M20, the 22nd transistor M22, the 23rd transistor M23, the 24th transistor M24, and the 25th transistor M25 turn on, and the remaining transistors turn off, corresponding to the first column subpixel P of the first column pixel island 102 in the first partition Z. The operational amplifier 104 (i.e., OP1), the operational amplifier 104 corresponding to the subpixel P in the 5th column of the pixel island 102 in the 1st column of the first partition Z (i.e., OP5), the operational amplifier 104 corresponding to the subpixel P in the 1st column of the pixel island 102 in the 9th partition Z (i.e., OP1'), and the operational amplifier 104 corresponding to the subpixel P in the 5th column of the pixel island 102 in the 9th partition Z (i.e., OP5') are not reused.

[0109] [Table 5-1]

[0110] [Table 5-2]

[0111] In the embodiments of the present invention, each transistor may be a top-gate transistor or a bottom-gate transistor, but should be noted that it is not limited to these. Optionally, each transistor may be a field-effect transistor, a low-temperature polysilicon transistor, an amorphous silicon transistor, an oxide transistor, or the like. The first and second electrodes of each transistor are the drain electrode and source electrode, respectively, and are not distinguished in this context.

[0112] In some embodiments, the display board provided by embodiments of the present invention may include a source driver chip (Source IC) located in the frame region BB, and multiple gate circuits 106, multiple multiplexing circuits 105, and multiple operational amplifiers 104 can be integrated into the source driver chip, reducing data signal loss (RC loading) on ​​the transmission path from the source driver chip to the sub-pixel P. When the operational amplifiers 104 are reused between partitions Z, the wiring distance between the two operational amplifiers 104 between partitions Z is longer compared to when the operational amplifiers 104 are reused within the pixel island 102, so it is preferable to integrate the gate circuits 106, multiplexing circuits 105, and operational amplifiers 104 into the source driver chip. When the operational amplifiers 104 are reused within the pixel island 102, the wiring distance between the two operational amplifiers 104 is relatively short, so the gate circuits 106, multiplexing circuits 105, and operational amplifiers 104 can be integrated into the source driver chip, and the gate circuits 106, multiplexing circuits 105, and operational amplifiers 104 can be fabricated on the display board, and are not particularly limited thereto.

[0113] Based on the same inventive concept, embodiments of the present invention provide a method for driving the above-mentioned display board. However, since the principle for solving the problem of this driving method is similar to the principle for solving the problem of the above-mentioned display board, when implementing the driving method provided by embodiments of the present invention, one can refer to the implementation of the above-mentioned display board provided by embodiments of the present invention, and no further explanation will be repeated.

[0114] Specifically, an embodiment of the present invention provides a method for driving the above-described display board, which includes the following steps, as shown in Figure 17.

[0115] S1701, in multiplexing mode, the pre-multiplexing circuit is controlled to conduct to one of the data lines electrically connected to it and disconnect from the other data line electrically connected to it, in order to provide data signals output from at least two operational amplifiers to subpixels in the same column that are electrically connected to the data lines via a conductive multiplexing circuit and data lines.

[0116] S1702, in non-multiplexing mode, the multiplexing circuit is controlled to disconnect from all data lines electrically connected to it in order to provide the data signals output from each operational amplifier to the subpixels in each column electrically connected to each operational amplifier in a one-to-one correspondence.

[0117] Based on the same inventive concept, embodiments of the present invention provide a display device including the display board described above, as provided by embodiments of the present invention. Since the principle for solving the problems of the display device is similar to the principle for solving the problems of the display board described above, the implementation of the display device provided by embodiments of the present invention will be described in the same way as the description of the implementation of the display board described above, as provided by embodiments of the present invention, and no further explanation will be repeated.

[0118] In some embodiments, the display devices provided by embodiments of the present invention may be mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, navigators, smartwatches, fitness wristbands, personal digital assistants, or other products or components with display capabilities. Such display devices may include, but are not limited to, components such as radio frequency units, network modules, audio output and input units, sensors, display units, user input units, interface units, memory, processors, and power supplies. Furthermore, those skilled in the art will understand that the above structures do not limit the display devices provided by embodiments of the present invention. In other words, the display devices provided by embodiments of the present invention may include more or fewer of the above components, or specific combinations of components, or different arrangements of components.

[0119] Those skilled in the art will see that various modifications and variations are possible without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations in the embodiments of the present invention fall within the claims of the present invention and equivalent technical scope, the present invention is intended to include these modifications and variations. [Explanation of Symbols]

[0120] 101 Base board 102-pixel island 103 data lines 104 Operational Amplifier (OP) 105 Multiplexing circuit 106 Gate Circuits

Claims

1. A base substrate including a display area and a frame area located on at least one side of the display area, Multiple pixel islands arranged in an array within the aforementioned display area, In the aforementioned display area, a plurality of data lines extending along the column direction and arranged along the row direction, Multiple operational amplifiers located in the aforementioned frame region, It includes a plurality of multiplexing circuits located in the frame region, Each of the aforementioned pixel islands has subpixels arranged in an array, The data line is electrically connected to the subpixel, Each operational amplifier is electrically connected to a row of subpixels via the data lines, Each of the multiplexing circuits is connected to at least two of the operational amplifiers, and the subpixels electrically connected to each of the multiplexing circuits via the data lines are arranged in at least two rows. In the row direction, one partition is formed for every two adjacent columns of the pixel island, The multiplexing circuit includes a first submultiplexing circuit, and the subpixels electrically connected to each of the first submultiplexing circuits are located in at least two of the partitions. Each of the first submultiplexing circuits is connected between two operational amplifiers and the data lines electrically connected to the two operational amplifiers, and the subpixels electrically connected to each of the first submultiplexing circuits are located in the two partitions. There are 2n partitions in the row direction, where n is a positive integer, the first to n consecutive partitions are the gaze region, the (n+1) to 2n consecutive partitions are the non-gaze region, the gaze region is the region adapted to the visual requirements of human eyes in 3D display, the non-gaze region is the remaining region other than the gaze region, the refresh rate of the gaze region is higher than the refresh rate of the non-gaze region, and the division of the gaze region and the non-gaze region is determined by the arrangement order of the partitions. Each of the subpixels electrically connected to the first submultiplexing circuit is located in the m-th and (m+n)-th partitions, where m is an integer between 1 and n, The m-th partition is located in the gaze region, and the (m+n)-th partition is located in the non-gaze region. The first submultiplexing circuit is configured such that, when the non-gaze region is not refreshed and the gaze region is refreshed, it multiplexes the operational amplifier corresponding to the (m+n)-th partition in the non-gaze region to the m-th partition in the gaze region, and the operational amplifiers corresponding to the two partitions simultaneously supply data signals to the subpixels in the m-th partition. Each partition includes the pixel island of column i, where i is an integer greater than or equal to 2. Each of the subpixels electrically connected to the first submultiplexing circuit is located in the pixel island of the j-th column of the m-th partition and in the pixel island of the j-th column of the (m+n)-th partition, where j is an integer between 1 and i. k subpixels are arranged in a single row of each pixel island, where k is an even number. The display board is electrically connected to each of the first submultiplexing circuits, and the subpixels are at least a portion of the subpixels in the h-th column of the pixel island in the j-th column of the m-th partition, and at least a portion of the subpixels in the h-th column of the pixel island in the j-th column of the (m+n)-th partition, where h is an integer between 1 and k.

2. The display board according to claim 1, wherein one data line is connected between one operational amplifier and one row of subpixels.

3. The display board according to claim 2, wherein the subpixels electrically connected to each of the first submultiplexing circuits are the subpixel in the h-th column of the pixel island in the j-th column of the m-th partition, and the subpixel in the h-th column of the pixel island in the j-th column of the (m+n)-th partition.

4. The multiplexing circuit further includes a second submultiplexing circuit, The display board according to claim 3, wherein each of the second submultiplexing circuits is connected between two rows of subpixels in the pixel island within the same row and two of the first submultiplexing circuits corresponding to the two rows of subpixels.

5. k is a multiple of 4, and h is an integer between 1 and k / 4, and an integer between (1 + k / 4) and (k - 4), The display board according to claim 4, wherein each of the second submultiplexing circuits is electrically connected to the h-th column subpixel and the (h+k / 4)-th column subpixel of the pixel island in the same row, respectively.

6. The first submultiplexing circuit connecting the subpixel in the h-th column of the pixel island in the j-th column of the m-th partition and the subpixel in the h-th column of the pixel island in the j-th column of the (m+n)-th partition includes a first transistor, a second transistor and a third transistor, The first submultiplexing circuit connecting the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the m-th partition and the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the (m+n)-th partition includes a fourth transistor, a fifth transistor and a sixth transistor, The second submultiplexing circuit connecting the subpixel in the h-th column and the subpixel in the (h+k / 4)-th column of the pixel island in the j-th column within the m-th partition includes a seventh transistor, an eighth transistor and a ninth transistor, The second submultiplexing circuit connecting the h-th column subpixel and the (h+k / 4)-th column subpixel of the pixel island in the j-th column within the (m+n)-th partition includes a tenth transistor, an eleventh transistor and a twelfth transistor, where, The gate electrode of the first transistor is electrically connected to a first control signal terminal, the first electrode of the first transistor is electrically connected to the operational amplifier corresponding to the subpixel in the h-th column of the pixel island in the j-th column of the (m+n)-th partition, and the second electrode of the first transistor is electrically connected to the operational amplifier corresponding to the subpixel in the h-th column of the pixel island in the j-th column of the m-th partition. The gate electrode of the second transistor is electrically connected to the second control signal terminal, the first electrode of the second transistor is electrically connected to the second electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the first electrode of the seventh transistor. The gate electrode of the third transistor is electrically connected to the third control signal terminal, the first electrode of the third transistor is electrically connected to the first electrode of the first transistor, and the second electrode of the third transistor is electrically connected to the first electrode of the tenth transistor. The gate electrode of the fourth transistor is electrically connected to the fourth control signal terminal, the first electrode of the fourth transistor is electrically connected to the operational amplifier corresponding to the subpixel in the (h+k / 4)th column of the pixel island in the jth column of the (m+n)th partition, and the second electrode of the fourth transistor is electrically connected to the operational amplifier corresponding to the subpixel in the (h+k / 4)th column of the pixel island in the jth column of the mth partition. The gate electrode of the fifth transistor is electrically connected to the fifth control signal terminal, the first electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is electrically connected to the first electrode of the eighth transistor. The gate electrode of the sixth transistor is electrically connected to the sixth control signal terminal, the second electrode of the sixth transistor is electrically connected to the second electrode of the eleventh transistor, and the first electrode of the sixth transistor is electrically connected to the first electrode of the fourth transistor. The gate electrode of the seventh transistor is electrically connected to the seventh control signal terminal, and the second electrode of the seventh transistor is electrically connected to the data line corresponding to the h-th subpixel of the pixel island in the j-th column of the m-th partition. The gate electrode of the eighth transistor is electrically connected to the eighth control signal terminal, and the second electrode of the eighth transistor is electrically connected to the data line corresponding to the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the mth partition, The gate electrode of the ninth transistor is electrically connected to the ninth control signal terminal, the first electrode of the ninth transistor is electrically connected to the second electrode of the fifth transistor, and the second electrode of the ninth transistor is electrically connected to the second electrode of the second transistor. The gate electrode of the 10th transistor is electrically connected to the 10th control signal terminal, and the second electrode of the 10th transistor is electrically connected to the data line corresponding to the h-th subpixel of the pixel island in the j-th column of the (m+n)-th partition. The gate electrode of the 11th transistor is electrically connected to the 11th control signal terminal, and the second electrode of the 11th transistor is electrically connected to the data line corresponding to the subpixel in the (h+k / 4)th column of the pixel island in the jth column of the (m+n)th partition, The display board according to claim 5, wherein the gate electrode of the 12th transistor is electrically connected to the 12th control signal terminal, the first electrode of the 12th transistor is electrically connected to the second electrode of the 6th transistor, and the second electrode of the 12th transistor is electrically connected to the second electrode of the 3rd transistor.

7. The display board according to claim 1, wherein the two data lines are connected between one operational amplifier and one row of subpixels, one of the two data lines is connected to the subpixels in an odd-numbered row of the row, and the other is connected to the subpixels in an even-numbered row of the row.

8. The display board according to claim 7, wherein the subpixels electrically connected to each of the first submultiplexing circuits are the subpixels in the even-numbered rows of the h-th column of the pixel island in the j-th column of the m-th partition, and the subpixels in the even-numbered rows of the h-th column of the pixel island in the j-th column of the (m+n)-th partition.

9. The first submultiplexing circuit includes a thirteenth transistor and a fourteenth transistor, where, The gate electrode of the 13th transistor is electrically connected to the 13th control signal terminal, the first electrode of the 13th transistor is electrically connected to the operational amplifier corresponding to the subpixel in the h-th column of the pixel island in the j-th column of the m-th partition, and the second electrode of the 13th transistor is electrically connected to the data line corresponding to the subpixel in the even-numbered row of the h-th column of the pixel island in the j-th column of the (m+n)-th partition. The display board according to claim 8, wherein the gate electrode of the 14th transistor is electrically connected to the 14th control signal terminal, the first electrode of the 14th transistor is electrically connected to the operational amplifier corresponding to the subpixel in the h-th column of the pixel island in the j-th column of the (m+n)-th partition, and the second electrode of the 14th transistor is electrically connected to the data line corresponding to the subpixel in the even-numbered row of the h-th column of the pixel island in the j-th column of the m-th partition.

10. The aforementioned frame region further includes a plurality of gate circuits located within it. The display board according to any one of claims 7 to 9, wherein each gate circuit is connected between one operational amplifier and two data lines corresponding to the operational amplifier.

11. The gate circuit includes a 15th transistor and a 16th transistor, where, The gate electrode of the 15th transistor is electrically connected to the 15th control signal terminal, the first electrode of the 15th transistor is electrically connected to one of the operational amplifiers, and the second electrode of the 15th transistor is electrically connected to one of the two data lines. The display board according to claim 10, wherein the gate electrode of the 16th transistor is electrically connected to the 16th control signal terminal, the first electrode of the 16th transistor is electrically connected to one of the operational amplifiers, and the second electrode of the 16th transistor is electrically connected to the other of the two data lines.

12. The display board according to claim 10 or 11, further comprising a source driver chip located in the frame region, wherein the source driver chip includes the plurality of gate circuits, the plurality of multiplexing circuits, and the plurality of operational amplifiers.

13. k subpixels are arranged in a single row of each pixel island, where k is a multiple of 4. The display board according to claim 1, wherein the multiplexing circuit includes a third submultiplexing circuit, and the subpixels electrically connected to the third submultiplexing circuit are the subpixel in the h-th column and the subpixel in the (h+k / 4)-th column of the pixel island in the same row, where h is an integer between 1 and k / 4, and an integer between (1+k / 4) and (k-4).

14. In the row direction, one partition is formed for each of the i adjacent pixel islands, and there are 2n partitions in the row direction, where i is an integer greater than or equal to 2, and n is a positive integer. The display board according to claim 13, wherein the multiplexing circuit further includes a fourth submultiplexing circuit, the fourth submultiplexing circuit connecting the m-th partition and the same sequence of subpixels of the same sequence of pixel islands in the (m+n)-th partition, where m is an integer between 1 and n.

15. A third submultiplexing circuit connecting the subpixel in column h of the pixel island in column j of the m-th partition to the subpixel in column (h + k / 4) includes a 17th transistor, a 18th transistor, a 19th transistor, a 20th transistor, and a 21st transistor, where j is an integer between 1 and i. The third submultiplexing circuit connecting the subpixel in column h of the pixel island in column j of the (m+n)-th partition to the subpixel in column (h+k / 4) includes a 22nd transistor, a 23rd transistor, a 24th transistor, a 25th transistor, and a 26th transistor, The fourth submultiplexing circuit, which connects the subpixel of the h-th column of the pixel island in the j-th column within the m-th partition to the subpixel of the h-th column of the pixel island in the j-th column within the (m+n)-th partition, includes a 27th transistor, The fourth submultiplexing circuit connecting the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the m-th partition and the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the (m+n)-th partition includes a 28th transistor, where, The gate electrode of the 17th transistor is electrically connected to the 17th control signal terminal, the first electrode of the 17th transistor is electrically connected to the second electrode of the 18th transistor, and the second electrode of the 17th transistor is electrically connected to the data line corresponding to the subpixel of the h-th column of the pixel island in the j-th column of the m-th partition. The gate electrode of the 18th transistor is electrically connected to the 18th control signal terminal, and the first electrode of the 18th transistor is electrically connected to the operational amplifier corresponding to the h-th subpixel of the pixel island in the j-th column of the m-th partition, The gate electrode of the 19th transistor is electrically connected to the 19th control signal terminal, the first electrode of the 19th transistor is electrically connected to the second electrode of the 20th transistor, and the second electrode of the 19th transistor is electrically connected to the data line corresponding to the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the mth partition. The gate electrode of the 20th transistor is electrically connected to the 20th control signal terminal, and the first electrode of the 20th transistor is electrically connected to the operational amplifier corresponding to the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the mth partition, The gate electrode of the 21st transistor is electrically connected to the 21st control signal terminal, the first electrode of the 21st transistor is electrically connected to the second electrode of the 20th transistor, and the second electrode of the 21st transistor is electrically connected to the second electrode of the 18th transistor. The gate electrode of the 22nd transistor is electrically connected to the 22nd control signal terminal, the first electrode of the 22nd transistor is electrically connected to the second electrode of the 23rd transistor, and the second electrode of the 22nd transistor is electrically connected to the data line corresponding to the h-th subpixel of the pixel island in the j-th column of the (m+n)th partition. The gate electrode of the 23rd transistor is electrically connected to the 23rd control signal terminal, and the first electrode of the 23rd transistor is electrically connected to the operational amplifier corresponding to the h-th subpixel of the pixel island in the j-th column of the m-th partition, The gate electrode of the 24th transistor is electrically connected to the 24th control signal terminal, the first electrode of the 24th transistor is electrically connected to the second electrode of the 25th transistor, and the second electrode of the 24th transistor is electrically connected to the data line corresponding to the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the mth partition. The gate electrode of the 25th transistor is electrically connected to the 25th control signal terminal, and the first electrode of the 25th transistor is electrically connected to the operational amplifier corresponding to the subpixel of the (h+k / 4)th column of the pixel island in the jth column of the mth partition, The gate electrode of the 26th transistor is electrically connected to the 26th control signal terminal, the first electrode of the 26th transistor is electrically connected to the second electrode of the 25th transistor, and the second electrode of the 26th transistor is electrically connected to the second electrode of the 23rd transistor. The gate electrode of the 27th transistor is electrically connected to the control signal terminal of the 27th transistor, the first electrode of the 27th transistor is electrically connected to the operational amplifier corresponding to the subpixel of the h-th column of the pixel island in the j-th column of the (m+n)th partition, and the second electrode of the 27th transistor is electrically connected to the operational amplifier corresponding to the subpixel of the h-th column of the pixel island in the j-th column of the m-th partition, The display board according to claim 14, wherein the gate electrode of the 28th transistor is electrically connected to the control signal terminal of the 28th transistor, the first electrode of the 28th transistor is electrically connected to the operational amplifier corresponding to the subpixel in the (h+k / 4)th column of the pixel island in the jth column of the (m+n)th partition, and the second electrode of the 28th transistor is electrically connected to the operational amplifier corresponding to the subpixel in the (h+k / 4)th column of the pixel island in the jth column of the mth partition.

16. A method for driving a display board according to any one of claims 1 to 15, In multiplexing mode, to provide data signals output from at least two operational amplifiers to the subpixels in the same row electrically connected to the data lines via a conductive multiplexing circuit and the data lines, the steps include controlling the multiplexing circuit to conduct to one of the electrically connected data lines and disconnect from the other electrically connected data lines, A method for driving a display board, comprising the step of controlling a multiplexing circuit to disconnect from all electrically connected data lines in order to provide the data signals output from each operational amplifier to the subpixels of each row electrically connected to each operational amplifier in a one-to-one correspondence.

17. A display device comprising a display substrate according to any one of claims 1 to 15.

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