Bayesian decomposition of performance discrepancies in semiconductor devices

Abstract

Bayesian inference and modeling techniques may be used in conjunction with model decomposition to improve performance discrepancies of semiconductor processing devices by identifying causes of internal and external variations in performance. A network of causal relationships between processes and hardware in the semiconductor processing device may be accessed, and a first Bayesian model may be generated for a first semiconductor processing device using the causal relationships and performance data in the network. A second Bayesian model may be generated for a second semiconductor processing device using the performance data associated with the causal relationships in the network. Response distributions generated by the first and second Bayesian models may be compared to determine whether the performance of the first semiconductor processing device matches the performance of the second semiconductor processing device by decomposing the model transfer function to identify the influence of internal / external variables.

Description

Technical Field

[0001]

[0001] This disclosure generally describes identifying and correcting performance mismatches between semiconductor processing devices. More specifically, this disclosure describes a method that uses Bayesian modeling and decomposition to identify intrinsic / extrinsic variations and adjust device operating parameters to obtain optimal results.

Background Art

[0002]

[0002] Complex engineering systems can potentially cause failures in countless different ways. As engineering systems become more complex, the number of system functions that can have a causal impact on failures continues to increase. When a failure occurs, it is often difficult to identify the exact function that caused the failure. However, despite this difficulty, accurately identifying the risk factors that cause engineering failures can be very important for preventing such failures from occurring continuously in the future. The current state-of-the-art is to semi-quantitatively rank the risk of each input using language scale criteria. For example, this ranking may be performed by a team of subject experts using a numerical scale (e.g., a scale of 1 to 5). Although numerical ranking systems are used in this methodology, these ranks are often assigned based on user intuition and personal experience, and thus these rankings remain subject to cognitive bias. Therefore, a human-based ranking system takes longer to identify the root causes of engineering failures in complex systems.

Summary of the Invention

[0003]

[0003] In some embodiments, a method for identifying performance discrepancies between semiconductor processing devices may include accessing a network of causal relationships between processes and hardware within a semiconductor processing device; generating a first Bayesian model of a first semiconductor processing device using the causal relationships in the network and first performance data; generating a second Bayesian model of a second semiconductor processing device using the causal relationships in the network and second performance data; and comparing the response distributions generated by the first Bayesian model and the second Bayesian model to determine whether the performance of the first semiconductor processing device matches that of the second semiconductor processing device.

[0004]

[0004] In some embodiments, the system may include one or more processors and one or more memory devices that store instructions, when executed by the one or more processors, cause the one or more processors to perform a plurality of operations. The plurality of operations may include accessing a network of causal relationships between processes and hardware in a semiconductor processing device; generating a first Bayesian model of a first semiconductor processing device using the causal relationships in the network and first performance data; generating a second Bayesian model of a second semiconductor processing device using the causal relationships in the network and second performance data; and comparing the response distributions generated by the first Bayesian model and the second Bayesian model to determine whether the performance of the first semiconductor processing device matches that of the second semiconductor processing device.

[0005]

[0005] In some embodiments, one or more non-temporary computer-readable media may include instructions that, when executed by one or more processors, cause one or more processors to perform operations including: accessing a network of causal relationships between processes and hardware in a semiconductor processing device; generating a first Bayesian model of a first semiconductor processing device using the causal relationships in the network and first performance data; generating a second Bayesian model of a second semiconductor processing device using the causal relationships in the network and second performance data; and comparing the response distributions generated by the first Bayesian model and the second Bayesian model to determine whether the performance of the first semiconductor processing device matches that of the second semiconductor processing device.

[0006]

[0006] In any embodiment, any or all of the following features may be implemented in any combination, without limitation. The method / operation may also include identifying variations in extrinsic variables in the first and second Bayes models that indicate the sensitivity of the response distribution to hardware components in the first and second semiconductor processing devices. The method / operation may also include identifying variations in intrinsic variables in the first and second Bayes models that indicate the sensitivity of the response distribution to connections between hardware components in the first and second semiconductor processing devices. The first Bayes model may be represented using a transfer function. The transfer function may represent main effects, nonlinear effects, and interaction effects of the first semiconductor processing device that affect the response distribution of the first Bayes model. This method / operation may also include performing a first decomposition of the transfer function by subtracting a second Bayesian model from a first Bayesian model to generate variations in a separate external variable over the operating range of the separate external variable, and / or performing a second decomposition of the transfer function by aggregating each factor of the transfer function into variations in coefficients representing the internal variable with respect to the separate external variable. The system may be implemented on a controller of a semiconductor processing chamber. The system may be implemented on a central platform that communicates with controllers of multiple semiconductor processing chambers within a facility. The system may be implemented on a remote server that communicates with multiple different semiconductor processing facilities, each of which operates multiple semiconductor processing chambers. Determining whether the performance of the first semiconductor processing device matches that of the second semiconductor processing device may involve calculating the JS divergence between the response distributions generated by the first Bayesian model and the second Bayesian model, and / or determining whether the similarity between the response distributions generated by the first Bayesian model and the second Bayesian model falls within the threshold of the effective equivalence region (ROPE).The method / operation may also include performing a sensitivity analysis on an external variable to identify at least one external variable causing a performance discrepancy between a first semiconductor processing device and a second semiconductor processing device. Non-transient computer-readable media, processors, and / or memory devices may be distributed between the semiconductor processing chamber controller and a remote server. The method / operation may also include identifying the cause of the performance discrepancy between the first semiconductor processing device and the second semiconductor processing device. The method / operation may further include using the causal network to identify hardware devices. The operating parameters of the hardware devices may be adjusted to correct the performance discrepancy between the first semiconductor processing device and the second semiconductor processing device. The causal network may include node layers representing on-wafer effects, node layers representing functional requirements, and node layers representing hardware components. This method / operation may also include accessing a system function map containing a data structure that associates the requirements of a first semiconductor processing device with the functional requirements of components within the first semiconductor processing device, then with technical components, and then with on-wafer effects, and automatically generating a network from the function map.

[0007]

[0007] A further understanding of the properties and advantages of various embodiments can be achieved by referring to the remainder of this specification and the drawings. In the drawings, similar reference numbers are used across several drawings to refer to similar components. In some cases, a sub-label is associated with the reference number to indicate one of several similar components. When a reference number is referred to without specifying an existing sub-label, it is intended to refer to all such several similar components. [Brief explanation of the drawing]

[0008] [Figure 1]

[0008] A simplified diagram of a system for running an SAE software application according to several embodiments is shown. [Figure 2]

[0009] A flowchart of a method for detecting performance discrepancies between semiconductor processes, according to several embodiments, is shown. [Figure 3]

[0010] This document illustrates a mapping between product requirements and functional requirements that can be used to generate a causal interconnection network, according to several embodiments. [Figure 4]

[0011] A flowchart of the process for building one or more models based on Bayesian inference, according to several embodiments, is shown. [Figure 5]

[0012] This section demonstrates how the aforementioned prior knowledge can be incorporated with experimental data to design a model of a semiconductor processing system. [Figure 6A]

[0013] To compare the performance of the chambers according to several embodiments, we show models used for two different chambers. [Figure 6B]

[0014] Examples of how the matching process described above can be performed using a deposition chamber are shown in several embodiments. [Figure 6C]

[0015] The performance response between matching and mismatched thickness positions is shown for several embodiments. [Figure 7]

[0016] The results of sensitivity analysis of predicted responses in several embodiments are shown. [Figure 8]

[0017] The following illustrates internal variations at two locations on the substrate according to several embodiments. [Figure 9]

[0018] This document demonstrates how causal relationships described in a network structure can be used to modify the operating parameters of a process, according to several embodiments. [Figure 10]

[0019] This illustrates an exemplary computer system in which various embodiments can be implemented. [Modes for carrying out the invention]

[0009]

[0020] This specification describes embodiments for providing an unbiased, physics-based, probabilistic approach to identifying performance discrepancies in semiconductor processing systems. This methodology is based primarily on probability mathematics, physical simulations, physical experiments, and quantitative analysis, eliminating cognitive biases that have plagued the implementation of systematic failure analysis. The system combines physics-based cause-and-effect relationships to generate a Bayesian network that links functional causes to failure outputs. The Bayesian network can be generated directly from functional mappings, device requirements, and design / technical requirements. The Bayesian network can then be validated using statistical testing, where probabilities for each node in the network can be set using discrete grouping of sensor data and / or simulated data. The Bayesian network can then represent known causal and probabilistic relationships between operational requirements, technical functions, and design / technical components.

[0010]

[0021] The network can be used to represent causally interconnected processes in semiconductor processing devices, such as substrate processing chambers. This network can capture the energy flow of a system across a set of interconnected processes and hardware elements to represent causal relationships in a real system. After verification, for example through structured physical experiments, these causal relationships within the network can be used to construct models. These models can then be used to simulate the system performance response in the form of a system transfer function. This transfer function can be decomposed and used to analyze individual external and / or internal process characteristics. The results can be used to compare two different processes, whether on the same machine with different substrates or on different machines with different substrates. For example, the system can determine, based on the model output, whether the resulting substrate characteristics (e.g., film thickness) are consistent between these two different systems. The process can then identify and measure external variations representing the contribution of tolerances or degradation of architectural elements (e.g., knobs and hardware) and their interaction with system performance. The process can also identify and measure internal variations representing the contribution of the interconnection strength of the system's architectural elements under specific operating conditions. The identified external and / or internal variations can then be used to identify possible causes of potential discrepancies and update the system's operating parameters to produce consistent results.

[0011]

[0022] The process of generating a network of causal relationships, modeling a system, using the model to compare different device responses, identifying external and / or internal variations, and tuning device operating parameters can be performed entirely or partially by a software process. For example, an automated statistical engineering (SAE) software application may run on one or more computing systems to perform the operations described herein. These computing systems may be distributed across various facilities involved in the semiconductor manufacturing process.

[0012]

[0023] Figure 1 shows a simplified diagram of a system 100 for operating an SAE software application 108 according to some embodiments. The semiconductor processing facility 102 can include many different semiconductor processing devices 106. The semiconductor processing devices 106 can include semiconductor processing stations such as etching chambers, deposition chambers, polishing chambers, cleaning chambers, measurement chambers, lithography chambers, and / or any other type of semiconductor processing chamber. Some of the semiconductor processing devices 106 can include a controller 107 that is integrated with or communicates with the semiconductor processing device 106. For example, a controller 107-1 can be integrated with a semiconductor processing device 106-1 to execute a recipe and control the operating parameters and environment within the semiconductor processing device 106-1. Alternatively, the controller 107-1 can be communicatively coupled to the semiconductor processing device 106-1 through wired or wireless communication (such as an EtherCAT connection).

[0013]

[0024] The controller 107 may include any type of computing system. For example, the controller 107 may include one or more processors and one or more memory devices. One or more memory devices may contain instructions that cause one or more processors to perform operations related to the SAE software application 108. For example, the instructions may be stored on one or more non-temporary computer-readable media so that they are executed by one or more processors. In the configuration depicted in Figure 1, the controller 107 can run an instance of the SAE software application 108 on the semiconductor processing device 106. This allows the operator of the semiconductor processing device 106 to directly perform the analysis and optimization operations detailed below on the semiconductor processing device 106 itself. For example, the controller 107 may include a display device and I / O devices (e.g., a keyboard, mouse, etc.) that the operator can use to interact with the SAE software application 108. Examples of hardware / software that may be used to implement the controller 107 are described in detail below in relation to Figure 10.

[0014]

[0025] Alternatively or additionally, the semiconductor processing facility 102 may include a central platform 110 that communicates with some or all of the controller 107 and / or semiconductor processing devices 106. The central platform 110 may include a server capable of performing operations such as monitoring the performance of the semiconductor processing devices 106, updating the software of the controller 107, collecting and storing data measured from semiconductor substrates or data recorded during the semiconductor process, and / or other data monitoring operations. In some embodiments, the central platform 110 may also include an instance of the SAE software application 108. This may enable the operator of the central platform 110 to use the SAE software application 108 to analyze data from different semiconductor processing devices 106 and compare the performance of these devices. For example, the central platform 110 may collect data from various semiconductor processing devices 106 within the semiconductor processing facility 102, generate and validate models based on the collected data and domain knowledge, and simulate the performance of the semiconductor processing devices 106 over a range of operating parameters. Next, the operator of the central platform 110 can analyze the simulation results to identify internal and / or external factors that may cause performance discrepancies between various devices within the semiconductor processing facility 102.

[0015]

[0026] In some configurations, the remote monitoring facility 104 may include a server that also communicates with the semiconductor processing facility 102. For example, a remote server 112 located at a different facility may communicate with either the central platform 110 and / or individual controllers 107 to collect and aggregate performance data. The remote server 112 may also include an instance of the SAE software application 108 such that data collection, analysis, and optimization can be performed remotely. Although not shown in FIG. 1, the remote monitoring facility 104 may communicate with a number of semiconductor processing facilities. Thus, in addition to the semiconductor processing facility 102 depicted in FIG. 1, the remote monitoring facility 104 may include a data store 114 that collects operational data from semiconductor processing devices 106 across multiple different processing facilities. This enables the remote server 112 to compare the performance of semiconductor processing devices 106 operating in different facilities. For example, the remote monitoring facility 104 may be owned / operated by at least some of the manufacturers of the semiconductor processing devices 106. If the semiconductor processing devices 106 are sold or distributed to different semiconductor processing facilities, the remote monitoring facility 104 may continue to monitor and collect data from these facilities so as to be analyzed by the SAE software application 108. As a result, the results calculated by the SAE software application 108 (e.g., the cause of performance discrepancies) may be used not only to be adjusted immediately at the semiconductor processing facility 102 for improvement, but also by the semiconductor processing device manufacturers to improve the design of the semiconductor processing devices 106.

[0016]

[0027] An existing technical problem in semiconductor manufacturing arises when different results are obtained despite performing the same semiconductor manufacturing process with the same or similar equipment; this is referred to herein as a “mismatch.” For example, a single semiconductor processing chamber may repeatedly execute a recipe for performing a specific process on a batch of semiconductor substrates. The “recipe” may include a set of operating parameters (e.g., current level, timing sequence, power level, gas flow rate, etc.) executed by the semiconductor processing chamber. However, even if the same recipe and chamber are used for the entire batch, the same results will not be obtained for all semiconductor substrates in the batch. For example, the thickness of the deposited film may vary between individual substrates or between locations on the same substrate. Embodiments described herein provide a method for identifying when such mismatches occur, identifying likely causes, and identifying specific actions that can be taken to achieve better results.

[0017]

[0028] In another example, two different semiconductor processing stations may operate on separate semiconductor substrates. For instance, two etching chambers of the same type (same manufacturer, recipe, operating parameters, etc.) may be configured to operate identically and run the same recipe on the same type of substrate. However, the substrates obtained from the process in both etching chambers may not yield exactly the same results. Furthermore, embodiments described herein provide a method for identifying when discrepancies occur between different semiconductor processing devices of the same type and can be used to identify likely causes and specific actions that may be taken to obtain better results.

[0018]

[0029] Figure 2 shows a flowchart 200 of a method for identifying performance discrepancies between semiconductor processing devices according to several embodiments. The semiconductor process may include the same process performed by the same processing chamber or by different chambers, as described above. The method may be performed using any of the computer systems described herein, including the controller, server, or central platform shown in Figure 1. Each step of the flowchart 200 is described in detail in Figures 3 to 9, which will be referenced when describing each step. Furthermore, the method is not particularly limited to semiconductor processing chambers. Semiconductor processing devices may also include parts, modules, or components. For example, discrepancies may be detected between different parts, and the method may be used to identify potential causes of performance discrepancies.

[0019]

[0030] This method may include accessing an interconnected network of causal relationships between processes and hardware within a semiconductor processing device (202). This network may begin with performance definitions and product specifications for customer-specified results, which then flow into process specifications, and further into specific hardware configurations and devices. This network may include components of the semiconductor processing system and represent the flow of energy and information through the system. In some cases, a system performing this method may begin by importing a system function map and / or component function maps. These functional mappings may be maintained in dedicated software that tracks these relationships between functions, components, and results. That software may provide this method with data structures representing these functional mappings. Thus, this method step may include generating an interconnected network of causal relationships using these functional mappings.

[0020]

[0031] Figure 3 shows a mapping between product requirements and functional requirements that can be used to generate a causal interconnection network in several embodiments. For example, some embodiments may include a chemical vapor deposition (CVD) chamber for depositing films on a semiconductor substrate. The operation and data generated by this CVD chamber are used as examples only and are not intended to be limiting. Any other type of semiconductor processing device may be used in a similar manner.

[0021]

[0032] Product requirements 302 may represent the requirements imposed for the system to function properly. “Product” can be the product of a chamber, such as a semiconductor wafer on which a film is deposited. These product requirements 302 may be set by the customer and may specify performance metrics for the chamber or characteristics of the resulting wafer. Product requirements may include measurable outputs such as deposition rate, film thickness, resistance, layer impurities, throughput, processing time, and / or other results of the semiconductor manufacturing process. Product requirements may be expressed at the system level, and component requirements may be expressed at the component level.

[0022]

[0033] A set of functional requirements 304 can be directly derived from product requirements 302. For example, product requirements 302 can be mapped to a set of functional requirements 304 that may be causally related to product requirements 302. Based on product requirements 302, a set of functional requirements 304 can be selected to be incorporated into the processing chamber to produce those product requirements. For example, film thickness can be directly mapped to the controlled wafer temperature, controlled precursor dose, and / or other functional requirements 304. This mapping may mean that the performance of functional requirements 304 may influence product requirements 302.

[0023]

[0034] The mapping can be generated in a user interface where a subject expert can provide a matrix relationship between a specific product requirement 302 and a specific functional requirement 304, as shown in Figure 3. For example, known relationships between product requirements and functional requirements may be represented. The user may provide an estimate of the strength of the relationship between the product requirement and the functional requirement. This may be characterized using a numerical requirement (e.g., 5.00). Thus, this step may involve contributions of domain knowledge provided by the operator to form these relationships.

[0024]

[0035] Multiple levels of mapping can be represented by different data structures. For example, in some embodiments, functional requirements 304 can also be mapped to design requirements 306. Design requirements can represent different operations performed by technology or components in a system. Functional requirements 304, such as controlling pressure or wafer temperature, can be related to technology requirements 306, such as controlling pedestal temperature, controlling the flow of various gases or other reactants (e.g., NH3), controlling chamber pressure, and / or other requirements that may be imposed on different technology components. Similarly, design requirements 306 can be mapped to a set of hardware requirements 308, which represent specific hardware devices or components present within a semiconductor processing device.

[0025]

[0036] To generate the network structure 300, the structure may contain multiple nodes. Each individual node represents an entry for one of the requirements 302, 304, 306, and 308 described above. Edges between these nodes in the data structure may represent relationships between nodes. These relationships may be causal relationships between functions, components, and / or requirements represented by the nodes. For example, a relationship or edge between two nodes in the data structure may indicate a causal relationship between a function in the parent node and an outcome in the child node.

[0026]

[0037] In some embodiments, the system may automatically import data structures representing requirements 302, 304, 306, and 308 in order to establish relationships with nodes shown in the network structure 300. Note that in some embodiments, it is not necessary to establish relationships between all nodes represented in the data structures. For example, the strength of a relationship (e.g., a numerical score) may be subject to a threshold. If the strength of a relationship is below the threshold, the relationship does not need to be represented in the network structure 300. In other embodiments, all relationships may be represented. The method may proceed automatically by creating nodes for every function, requirement, component, etc., which has at least one relationship with another function, requirement, component, etc., which has a sufficient numerical score or a user-assigned qualitative relationship. The method may then generate relationships between nodes based on the relationships specified in the imported data structures.

[0027]

[0038] In the example in Figure 3, different requirement levels can be mapped to layers of nodes within the network structure 300. For example, the topmost node in the network structure 300 may represent hardware requirement 308. Nodes in the next higher layer may represent design requirement 306, and so on. Collectively, nodes (along with any other internal layers not shown in detail in Figure 3) can be referred to as component functions. For example, controlling gas flow may be a functional requirement, corresponding to a component function such as a gas valve that controls gas flow. Similarly, the partial pressure of gas at a specific location on the wafer may also be included as a component function, as this relates to requirements for gas control components. The bottommost node in the network structure 300 may represent a measurable on-wafer effect and represent product requirement 302. Thus, the bottommost node represents an on-wafer effect, and all nodes on which the on-wafer effect depends can be broadly referred to as component functions or hardware devices. The relationships in the network can represent the causal dependencies between various component functions and the resulting on-wafer effects.

[0028]

[0039] Returning briefly to Figure 2, after developing a causal interconnection network, the method may also include generating models of semiconductor processing devices using relational and Bayesian inference (204). When performing matching comparisons, this step may include generating models of each semiconductor processing device. In some embodiments, Bayesian models may be used. For example, when comparing the performance of two chambers, the process may include generating a first Bayesian model for a first semiconductor processing device using causal relationships in the network, and also generating a second Bayesian model for a second semiconductor processing device using causal relationships in the network. As will be discussed later, the Bayesian models of both semiconductor processing devices may use performance data from structured experiments (e.g., first performance data and second performance data, respectively) to estimate the coefficients used within the Bayesian models.

[0029]

[0040] Figure 4 shows a flowchart 400 of the process for building one or more models based on Bayesian inference, according to several embodiments. One input may include data from structured experiments 404. Generally, the scope of data from structured experiments 404 may be limited because performing a large number of marathon experiments on semiconductor substrates is too costly. Instead, the system may be adapted to use a smaller number of experiments (e.g., 15-30 substrates). Data may be collected from semiconductor processing chambers in the form of unstructured observations of the responses of these chambers. Alternatively, structured experiments can also be performed. For example, data from structured experiments 404 may be collected as measurement data from a measurement station.

[0030]

[0041] In contrast to existing methods, these methods do not need to rely solely on data. Instead, domain knowledge 406 can be used to supplement the data. Domain knowledge may include the aforementioned network structure 300, which contains the physical relationships between different variables in the system. In addition to architectural design information 402, the data may be supplemented with acquired data 408 received before the model is built. Acquired data 408 may also be received after the model is created and used to improve that model. Acquired data may include field tests, reliability data, observational data, marathon tests, iterative designs, laboratory tests, and / or other sources of additional data about the process being modeled.

[0031]

[0042] Domain knowledge 406 and acquired data 408 may be referred to as “prior information” 410 when constructing a model using Bayes’ law. Additional prior information may include past model definitions or engineering knowledge. For example, network structure 300 and / or engineering knowledge may show that temperature and pressure are related and follow a particular distribution. A specific model structure 412 may be selected and combined with the prior information 410 using Bayes’ law 414 to generate a model 416.

[0032]

[0043] Figure 5 illustrates how the aforementioned prior knowledge can be incorporated with experimental data to design a model of a semiconductor processing system. Specifically, Bayes' theorem provides a method for updating or generating a model using prior knowledge as it becomes available regarding the physical operation of the system. For example, architecture design 520 may include the physical architecture of a semiconductor processing device. This architecture design 520 may include the components listed in the network structure 300 described above, which show the causal relationships in the functionality of architecture design 520. This becomes the initial starting point for the model. However, a judgment still needs to be made as to whether the initial design is accurate and valid. In terms of Bayes' law, this question regarding the feasibility of the initial architecture design can be called p(design), that is, the probability that the design is correct.

[0033]

[0044] Next, experimental data 522 resulting from experiments conducted using semiconductor processing devices may be collected. This experimental data 522 may be used to verify or confirm the architecture design 520, including the validity of causal relationships between hardware, functionality, and design requirements. In terms of Bayesian terminology, this step may be normalized and formulated as follows: TIFF0007897956000001.tif15170

[0034]

[0045] Finally, Bayes's law can be used to combine a pre-design or initial design with experimental results to generate a posterior design that shows the probability of the design after the experimental results occurred. TIFF0007897956000002.tif15170

[0035]

[0046] The resulting model can be represented by a transfer function 500. The transfer function 500 generates an output (Y) 502 representing the system performance response. The output 502 is expressed by the transfer function 500 as a function of external variables (X) and internal variables (β). External variables may represent variations due to tolerances or degradation of architectural elements (hardware components, knobs, etc.) and their interactions. In contrast, internal variables may represent variations due to the interconnection strength of architectural elements within the system. These internal variables measure the contribution of the system's sensitivity to the operating window of the operating parameters. For example, an example of a transfer function and its estimated coefficients relating to the thickness of a film formed in a deposition chamber is as follows: TIFF0007897956000003.tif139170

[0036]

[0047] With respect to the transfer function 500, the X term, representing external variables, can correspond to physical characteristics such as pressure, temperature, plasma power, gas flow, and pedestal spacing. The β term, representing internal variables, can be coefficients of the transfer function 500. To create an accurate transfer function 500, it may include fundamental signals 504, main effects 506, nonlinear effects 508, interaction effects 510, noise 512, and / or other terms. In other words, the X term can represent hardware components, and the β term represents how those components are connected. i Term and β i Note that the number of terms can be large (e.g., 10 or more), and each may involve aggregation / integration, making the calculation complex. Note that the transfer function 500 does not represent a single value, but rather a distribution of values ​​for each variable within the function. As mentioned above, the validity of the transfer function 500 can be verified based on the measured values ​​and system response, ensuring the accuracy of the model.

[0037]

[0048] Returning briefly to Figure 2, the method may additionally include comparing the semiconductor processing device responses using a model (206). The structure of the model may be similar for each semiconductor processing device, but different X i Term and β i Each term can be different. Processes performed by semiconductor processing devices can ideally produce identical substrates. However, as mentioned above, processes involving different substrates processed by the same device, or different substrates processed by different devices of the same type, can be different, resulting in a consequence called "mismatch." For example, when comparing the performance of two different semiconductor processing devices, in order to determine whether the performance of the first semiconductor processing device matches that of the second semiconductor processing device, this comparison may involve comparing the response distributions generated by the first Bayesian model and the second Bayesian model.

[0038]

[0049] Figure 6A shows models used for comparing the performance of two different chambers according to several embodiments. These chamber models use transfer functions in the form of the equations derived earlier in Figure 5. Equation 602 may represent the first chamber, and equation 604 may represent the second chamber. These chambers may be the same type of chambers processing different substrates that are expected to have similar results. In other embodiments, these equations 602, 604 may represent other aspects of the semiconductor process, such as different device or substrate locations. Using the output Y to represent the measured performance of each chamber or device, a comparison may be made between the two chambers to determine if there is a performance discrepancy. Specifically, equation 606 may be derived by calculating the difference between equation 602 for the first chamber and equation 604 for the second chamber. If the performance of the chambers is identical, the resulting TIFF0007897956000004.tif5170 should be almost zero. However, the result obtained Because it deviates from TIFF0007897956000005.tif51700, this may indicate a performance discrepancy between the first chamber and the second chamber.

[0039]

[0050] Equation 606 can also represent the first level of a Bayesian two-level decomposition of a response. When comparing two semiconductor processing devices, Equation 606 may represent an example of performing a first decomposition of a transfer function by subtracting a second Bayesian model from a first Bayesian model to generate variations in a distinct external variable over the operating range of the distinct external variable. For example, Equation 606 uses stochastic sensitivity analysis to recognize and measure the external variation, as described above, to determine the response variation over the entire range of its value (e.g., X low From X high X (up to) i It can be decomposed into separate measurable variations of X within the set.

[0040]

[0051] Equation 610, as described above, may represent a second level of Bayesian two-level decomposition, which uses aggregated difference analysis to decompose response variations into measurable variations of the coefficients (β) of distinct X in the optimal setting, in order to recognize and measure external variations. For example, Equation 610 may represent performing a second decomposition of the transfer function by aggregating each factor of the transfer function into variations of coefficients representing the internal variables with respect to distinct external variables. The result of Equation 610 may yield a distribution of response values ​​for individual X in its optimal setting.

[0041]

[0052] Many different methods can be used to determine whether the responses of the first and second chambers match or represent a performance mismatch. These methods may employ Bayesian matching techniques that consider the entire distribution of values ​​rather than just a single value (such as the mean or standard deviation). In some embodiments, the difference between the distributions of the first and second chambers may be compared to a criterion. For example, a substantial equivalence region (ROPE) may be used to determine how much of the distribution of results for each chamber falls within a specified practical range. In some embodiments, a high density interval (HDI) method may also be used to summarize the range of the most reliable values ​​of the measurements within a limited range. This range may be determined by practical operating conditions or recipes used within the chamber, rather than spanning the entire range of possible values. In some embodiments, matching techniques such as JS divergence may also be used to calculate a measure of similarity between two distributions. For example, when comparing two semiconductor processing devices, the process may calculate the JS divergence between the response distributions generated by a first Bayesian model and the response distributions generated by a second Bayesian model.

[0042]

[0053] Figure 6B shows examples of how the matching process described above can be performed using a deposition chamber according to several embodiments. The first and second chambers described above may represent homogeneous deposition chambers processing different substrates. Alternatively, the method may be used to identify performance discrepancies within the same physical chamber and / or on the same substrate. In this example, contour plot 600 represents the thickness of the deposited film on the semiconductor substrate. The substrate thickness at positions 642 and 646 is approximately the same based on contour plot 600. However, the substrate thickness at position 640 may differ significantly from that at position 644. The model describing the process described above may be used to identify this performance discrepancy and indicate possible causes of the performance discrepancy.

[0043]

[0054] Figure 6C shows the performance response between a matching thickness location and a mismatched thickness location for several embodiments. The performance response matches if the matching response distributions for all possible design variable settings consistently match within the specifications. In this example, a threshold of 5% or less may be used. A performance mismatch can be identified if any of the response distributions for any of the design variable settings deviate from the 5% match between these two points. Therefore, when comparing the performance of two semiconductor processing devices, this step may include determining whether the similarity between the response distributions generated by the first Bayesian model and the second Bayesian model falls within the ROPE threshold.

[0044]

[0055] In this example, the results of various experiments (DOEs) are judged in the table shown in Figure 6C. Table 620 shows the matching results of the predicted responses of positions 642 and 646 across a range of inputs represented by various DOEs. Matching responses are judged to be 95% or more within the ROPE and match across the entire design space (i.e., the recorded “cutoff” value is less than the acceptable 5% variation). Plots 633 and 635 show the performance of these matching thicknesses when 100% of the 95% HDI is within the ROPE at DOE-3.

[0045]

[0056] In comparison, the different predicted response distributions for comparing the responses at positions 640 and 646 show the number of variable settings (e.g., DOE-) where the predicted responses do not match, even when other predicted responses in Table 622 are within 95% of the ROPE range. Plots 637 and 639 show the performance of these matching thicknesses when 0% of the 95% HDI is within the ROPE of DOE-3.

[0046]

[0057] These distributions and responses can be calculated using the Bayesian method described above. A Bayesian model may be used based on DOE data points to detect whether the thickness values ​​between different locations functionally match. In this example, these data may show that within the same chamber, location 642 matches location 646, while a mismatch occurs between locations 640 and 644.

[0047]

[0058] Returning briefly to Figure 2, the method may also include identifying external variations (208). External variations can be identified using the Bayesian decomposition described above, for example, by performing a probabilistic sensitivity analysis of the external variables over the operating range. For example, when comparing the performance of two different devices, this process may include identifying variations in the external variables in the first Bayesian model and the second Bayesian model. These variations in the external variables may indicate the sensitivity of the response distribution to hardware components in the first and second semiconductor processing devices.

[0048]

[0059] Continuing this example, the transfer function described above could be used to identify external variations between positions 640 and 644 that could be causing discrepancies in detected thickness. For example, external variations represented by the X variable of the transfer function could be used to perform a sensitivity analysis of these variable settings. In other words, a stochastic sensitivity analysis could reveal that changes in each setting of the X variable across the entire range of values ​​cause performance discrepancies. TIFF0007897956000006.tif5170 It is possible to determine the extent of the contribution. When comparing the performance of two semiconductor processing devices, this step may include performing a sensitivity analysis on an external variable to identify at least one external variable that causes a performance mismatch between the first and second semiconductor processing devices.

[0049]

[0060] Figure 7 shows the results of sensitivity analysis of the predicted response in several embodiments. Graph 700 shows how much variation in each variable X affects the resulting thickness at each location. Bar graph 702 represents the sensitivity of the X variable at location 640, bar graph 704 represents the sensitivity of the X variable at location 644, and bar graph 706 represents the difference between these predicted responses at each location. Bar graph 706 shows the main factors influencing the thickness discrepancy of the deposited layer. Specifically, approximately 77% of the thickness discrepancy on the substrate can be attributed to PDMAT dose flow (27.74%), NH3 dose flow (18.73%), PDMAT purge Ar flow (18.52%), and chamber pressure (12.55%).

[0050]

[0061] This information can be used to highlight the main causes of performance discrepancies on the substrate due to external factors. In this example, adjusting the PDMAT dose flow rate can have the greatest impact on the discrepancy between the two locations. Adjustments can be made to each of these parameters to bring the discrepancy performance within the ROPE range.

[0051]

[0062] However, adjusting for external factors alone may not be sufficient to eliminate all performance inconsistencies on the substrate. Some embodiments may also include evaluating internal variations at these two positions in the optimal recipe settings. It will be recognized that, in order to determine how much it affects TIFF0007897956000007.tif9170 (for example, the optimal setting determined from external variation adjustments), the internal variable (β) represented by the transfer function can be analyzed using Bayesian decomposition.

[0052]

[0063] Returning briefly to Figure 2, the method may also include identifying internal variations (210). These internal variations can be identified using the Bayesian decomposition described above. When comparing two different semiconductor processing devices, identifying variations in internal variables in the first and second Bayesian models may indicate the sensitivity of the response distribution to the connections between the hardware components of the first and second semiconductor processing devices.

[0053]

[0064] Figure 8 shows internal variations at two locations on the substrate according to several embodiments. The set of optimal settings can be determined as described above using adjustments for external variations. In this example, the optimal settings may include values ​​for each variable X illustrated in Figure 7 (e.g., chamber pressure = 5 kPa, NH3 dose flow rate = 158804 sccm). These values ​​can be used. Then, To generate the distribution for TIFF0007897956000008.tif9170, a set of 800 response graphs may be generated to show the distribution of responses.

[0054]

[0065] When the distribution is very narrow, it may indicate that these particular internal variables do not significantly affect the variation in the response. For example, Graphs 808 and 810 show very narrow distributions that indicate that variations in NH3 purge air flow rate and NH3 purge time do not significantly affect the response. However, larger distributions, such as those shown in Graphs 802 and 804, may indicate that variations in the corresponding internal variables (such as internal characteristics that cause variations in chamber pressure and NH3 dose flow rate) significantly affect the variation in the response distribution. To illustrate the data in another way, Table 801 shows how large the distribution and / or mean values ​​of the chamber pressure, dose flow rate, and pedestal temperature distributions are compared to other internal variables. These values ​​can be compared to thresholds to identify whether these internal variables are significant.

[0055]

[0066] Returning briefly to Figure 2, the method may also include tuning device parameters to compensate for internal and / or external variations (212). How this step is carried out may vary depending on the type of discrepancy identified. As described above, discrepancies may be identified between semiconductor substrates, between locations on semiconductor substrates, between different semiconductor substrates within the same chamber, between different semiconductor substrates in different chambers, etc. Depending on the particular embodiment, internal / external variations may be mapped to physical or engineering knowledge for purposes such as tuning the operation of the semiconductor chamber, tuning the design of the semiconductor device, and determining the optimal performance settings for the semiconductor device. For example, this step may include using a network of causal relationships to identify a hardware device, where the operating parameters of the hardware device may be tuned to correct a performance discrepancy between a first semiconductor processing device and a second semiconductor processing device.

[0056]

[0067] To make adjustments based on these internal fluctuations, the network structure 300 described above can be used to identify the causes of the internal fluctuations. Figure 9 shows how the causal relationships described in the network structure 300 can be used to make changes to the operating parameters of the process in several embodiments. For example, the data in Figure 8 showed that the pedestal temperature 904 and the NH3 dose flow rate 910 were related to internal fluctuations. The causal relationships identified in the network structure 300 can identify specific hardware elements that can be controlled to adjust these internal fluctuations. For example, the heater 902 can be adjusted to compensate for the internal fluctuations observed in the pedestal temperature 904. The mass flow controller 908 for NH3 can be adjusted to control the internal fluctuations observed in the NH3 dose flow rate 910. These adjustments can ultimately affect the thickness 906 of the semiconductor substrate.

[0057]

[0068] For example, when the optimal chamber settings are applied, the thickness 906 is sensitive to the NH3 dose flow rate 910 and pedestal temperature 904, which affect the total reactant concentration in the chamber, and should therefore be investigated to identify the cause of the thickness mismatch. Utilizing this causal relationship of the network structure 300, the operator can focus their investigation on the NH3 mass flow controller 908 and heater 902. Focus can be placed not only on the direct interpretation of these parameters, but also on the inherent variability in the design and installation of these devices in the chamber. For example, the heater 902 may be susceptible to asymmetric heater installation steps, thermocouple offset steps, PID tuning steps, and recipe setting steps. The mass flow controller 908 for NH3 may have variations in delay time, correction factor, inlet pressure, etc., depending on the installation location.

[0058]

[0069] It should be noted that the examples of performance discrepancies in substrates within chambers described above are provided for illustrative purposes only and are not intended as limitations. Other applications of the Bayesian modeling process described above can be used in a variety of situations. For example, the same technique may be used to identify performance discrepancies between semiconductor chambers tested in a laboratory and semiconductor chambers operating at a customer's facility. For example, the same technique may be used to determine whether the thickness or other properties of semiconductor substrates match between two chambers or chamber types. For example, the same analysis used above may be used to determine that temperature is the primary variable causing variations in thickness or other properties. Temperature can be identified as having variability that strongly contributes to thickness discrepancies between two chambers, even at different temperature setting levels (e.g., low, medium, high, optimal, etc.). The model can then be used to simulate and identify a recipe that minimizes the difference or discrepancy between the two chambers. The customer may then choose to use the proposed recipe to minimize the thickness variation. Hardware components that affect temperature (e.g., lamp heads, pyrometers, reflector plates, etc.) are also identified, and adjustments may be made to those hardware components.

[0059]

[0070] Each of the methods described herein can be implemented by a computer system. Each step of these methods can be performed automatically by the computer system and / or provided with user-involved inputs / outputs. For example, a user can provide inputs for each step in the method, each of which may be in response to a particular output requesting such input, and the output may be generated by the computer system. Each input may be received in response to a corresponding requested output. Furthermore, inputs may be received from a user, received as a data stream from another computer system, retrieved from a memory location, retrieved over a network, requested from a web service, etc. Similarly, outputs may be provided to a user, provided as a data stream to another computer system, stored in a memory location, sent over a network, provided to a web service, etc. In short, each step of the methods described herein can be performed by a computer system and may involve any number of inputs, outputs, and / or requests to and from the computer system, which may or may not involve a user. Steps that do not involve a user can be said to be performed automatically by the computer system without human intervention. Accordingly, in light of this disclosure, it will be understood that each step of each method described herein may be modified to include inputs and outputs to and from a user, or may be performed automatically by a computer system without human intervention, where any decisions are made by a processor. Furthermore, some embodiments of each of the methods described herein may be implemented as a set of instructions stored in a tangible, non-temporary storage medium to form a tangible software product.

[0060]

[0071] Figure 10 shows an exemplary computer system 1000 in which various embodiments can be implemented. System 1000 can be used to implement any of the computer systems described above. As shown in the figure, computer system 1000 includes a processing unit 1004 that communicates with several peripheral subsystems via a bus subsystem 1002. These peripheral subsystems may include a processing acceleration unit 1006, an I / O subsystem 1008, a storage subsystem 1018, and a communication subsystem 1024. The storage subsystem 1018 includes a tangible computer-readable storage medium 1022 and system memory 1010.

[0061]

[0072] The bus subsystem 1002 provides a mechanism for various components and subsystems of the computer system 1000 to communicate with each other as intended. Although the bus subsystem 1002 is schematically shown as a single bus, alternative embodiments of the bus subsystem may utilize multiple buses. The bus subsystem 1002 may be one of several types of bus structures, including a memory bus or memory controller, a peripheral bus, and a local bus using one of various bus architectures. For example, such architectures may include an Industry Standard Architecture (ISA) bus, a Microchannel Architecture (MCA) bus, an Extended ISA (EISA) bus, a Video Electronics Standards Institute (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus, which may be implemented as a mezzanine bus manufactured to the IEEE P1386.1 standard.

[0062]

[0073] The processing unit 1004, which can be implemented as one or more integrated circuits (for example, conventional microprocessors or microcontrollers), controls the operation of the computer system 1000. One or more processors may be included in the processing unit 1004. These processors may include single-core processors or multi-core processors. In some embodiments, the processing unit 1004 is implemented as one or more independent processing units 1032 and / or 1034, each processing unit may include a single or multi-core processor. In other embodiments, the processing unit 1004 may also be implemented as a quad-core processing unit formed by integrating two dual-core processors onto a single chip.

[0063]

[0074] In various embodiments, the processing unit 1004 can execute various programs in response to program code and can maintain multiple programs or processes running simultaneously. At a given time, some or all of the program code to be executed may reside in one or more processors 1004 and / or in the storage subsystem 1018. Through suitable programming, one or more processors 1004 can provide the various functions described above. The computer system 1000 may further include a processing acceleration unit 1006, which may include a digital signal processor (DSP), a dedicated processor, and the like.

[0064]

[0075] The I / O subsystem 1008 may include user interface input devices and user interface output devices. User interface input devices may include pointing devices such as keyboards, mice or trackballs, touchpads or touchscreens integrated into displays, scroll wheels, click wheels, dials, buttons, switches, keypads, audio input devices with voice command recognition systems, microphones, and other types of input devices. User interface input devices may also include motion detection and / or gesture recognition devices, such as the Microsoft Kinect® motion sensor, which enable a user to control and interact with an input device, such as a Microsoft Xbox® 360 game controller, through a natural user interface using gestures and spoken commands. User interface input devices may also include eye gesture recognition devices, such as the Google Glass® blink detector, which detects eye activity from the user (e.g., blinking while taking a picture and / or making a menu selection) and translates eye gestures as input to an input device (e.g., Google Glass®). Furthermore, the user interface input device may include a voice recognition detection device that enables the user to interact with a voice recognition system (e.g., Siri® Navigator) through voice commands.

[0065]

[0076] User interface input devices may also include, but are not limited to, three-dimensional (3D) mice, joysticks or pointing sticks, gamepads and graphics tablets, audio / visual devices such as speakers, digital cameras, digital camcorders, portable media players, webcams, image scanners, fingerprint scanners, barcode readers, 3D scanners, 3D printers, laser rangefinders, and eye-tracking devices. Furthermore, user interface input devices may also include medical imaging input devices, such as computed tomography, magnetic resonance imaging, positional emission tomography, and medical ultrasound imaging devices. User interface input devices may also include audio input devices, such as MIDI keyboards and digital musical instruments.

[0066]

[0077] User interface output devices may include non-visual displays such as display subsystems, indicator lights, or audio output devices. Display subsystems may include flat panel devices such as cathode ray tubes (CRTs), liquid crystal displays (LCDs), or plasma displays, projection devices, and touchscreens. In general, the use of the term “output device” shall include all conceivable types of devices and mechanisms for outputting information from computer system 1000 to a user or another computer. For example, user interface output devices may include, but are not limited to, a variety of display devices that visually convey text, graphics, and audio / video information, such as monitors, printers, speakers, headphones, car navigation systems, plotters, audio output devices, and modems.

[0067]

[0078] The computer system 1000 may include a storage subsystem 1018 which contains software elements that are currently located in the system memory 1010. The system memory 1010 may store program instructions that can be loaded and executed on the processing unit 1004, as well as data generated during the execution of these programs.

[0068]

[0079] Depending on the configuration and type of the computer system 1000, the system memory 1010 may be volatile (such as random access memory (RAM)) and / or non-volatile (such as read-only memory (ROM), flash memory, etc.). RAM typically contains data and / or program modules that are readily accessible to the processing unit 1004 and / or currently being operated and executed by the processing unit 1004. In some implementations, the system memory 1010 may contain several different types of memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM). In some implementations, a basic input / output system (BIOS), which contains basic routines that help transfer information between elements within the computer system 1000, such as during startup, may be stored in ROM. As an example, but not an limitation, the system memory 1010 may also include application programs 1012, program data 1014, and the operating system 1016, which may include client applications, web browsers, intermediate-tier applications, relational database management systems (RDBMS), etc. For example, Operating System 1016 may include various versions of Microsoft Windows®, Apple Macintosh®, and / or Linux operating systems, various commercially available UNIX® or UNIX-like operating systems (including, but not limited to, various GNU / Linux operating systems, Google Chrome® OS, etc.), and / or mobile operating systems such as iOS, Windows® Phone, Android® OS, BlackBerry® 10 OS, and Palm® OS.

[0069]

[0080] The storage subsystem 1018 may also provide a tangible, computer-readable storage medium for storing basic programming and data structures that provide the functionality of several embodiments. Software (programs, code modules, instructions) that, when executed by the processor, provides the functionality described above, may be stored in the storage subsystem 1018. These software modules or instructions may be executed by the processing unit 1004. The storage subsystem 1018 may also provide a repository for storing data used according to several embodiments.

[0070]

[0081] The storage subsystem 1000 may also include a computer-readable storage medium reader 1020, which may be further connected to the computer-readable storage medium 1022. Together with the system memory 1010, and optionally in combination with the system memory 1010, the computer-readable storage medium 1022 may comprehensively represent remote, local, fixed, and / or removable storage devices and storage media for storing, transmitting, and retrieving computer-readable information, both temporarily and / or more permanently.

[0071]

[0082] The computer-readable storage medium 1022, which includes code or a portion of code, may also include any suitable medium, including storage and communication media, such as volatile and non-volatile, removable and non-removable media, which are implemented in any method or technique for storing and / or transmitting information. This may include tangible computer-readable storage media or other tangible computer-readable media, such as RAM, ROM, electronically erasable programmable ROM (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD), or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices. This may also include non-tangible computer-readable media, such as any other medium which may be used to transmit data signals, data transmission, or desired information and which may be accessed by the computing system 1000.

[0072]

[0083] For example, computer-readable storage media 1022 may include hard disk drives that read from or write to non-removable non-volatile magnetic media, magnetic disk drives that read from or write to removable non-volatile magnetic disks, and optical disk drives that read from or write to removable non-volatile optical disks, such as CD-ROMs, DVDs, and Blu-ray® discs, or other optical media. Computer-readable storage media 1022 may also include, but are not limited to, Zip® drives, flash memory cards, Universal Serial Bus (USB) flash drives, Secure Digital (SD) cards, DVD discs, digital videotapes, and the like. The computer-readable storage medium 1022 may also include non-volatile memory-based SSDs such as flash memory-based solid drives (SSDs), enterprise flash drives, and solid ROMs, volatile memory-based SSDs such as solid RAM, dynamic RAM, static RAM, DRAM-based SSDs, and magnetoresistive RAM (MRAM) SSDs, and hybrid SSDs that use a combination of DRAM-based SSDs and flash memory-based SSDs. The disk drives and their associated computer-readable media may provide non-volatile storage for computer-readable instructions, data structures, program modules, and other data for the computer system 1000.

[0073]

[0084] The communication subsystem 1024 provides interfaces to other computer systems and networks. It acts as an interface for receiving data from other systems to computer system 1000 and for transmitting data from computer system 1000 to other systems. For example, the communication subsystem 1024 may enable computer system 1000 to connect to one or more devices via the Internet. In some embodiments, the communication subsystem 1024 may include radio frequency (RF) transceiver components for accessing wireless voice and / or data networks (e.g., using cellular telephone technology, 3G, 4G, or advanced data network technologies such as EDGE (Global Evolutionary High Speed ​​Data Rate), WiFi (IEEE 802.11 family standards), or other mobile communication technologies, or any combination thereof), a Global Positioning System (GPS) receiver component, and / or other components. In some embodiments, the communication subsystem 1024 may provide wired network connectivity (e.g., Ethernet) in addition to or instead of the wireless interface.

[0074]

[0085] In some embodiments, the communication subsystem 1024 may also receive input communications in the form of structured and / or unstructured data feeds 1026, event streams 1028, event updates 1030, etc., for one or more users who may use the computer system 1000.

[0075]

[0086] As an example, the communication subsystem 1024 may be configured to receive data feeds 1026 in real time from users of social networks and / or other communication services, such as web feeds including Twitter® feeds, Facebook® updates, Rich Site Summary (RSS) feeds, and / or real-time updates from one or more third-party information sources.

[0076]

[0087] Furthermore, the communication subsystem 1024 may also be configured to receive data in the form of a continuous data stream. This data may include an event stream 1028 of real-time events and / or event updates 1030, which may have no explicit end and be substantially continuous or infinite. Examples of applications that generate continuous data may include, for example, sensor data applications, financial tickers, network performance measurement tools (e.g., network monitoring and traffic management applications), clickstream analysis tools, and automotive traffic monitoring.

[0077]

[0088] The communication subsystem 1024 may also be configured to output structured and / or unstructured data feeds 1026, event streams 1028, event updates 1030, etc., to one or more databases that can communicate with one or more streaming data source computers coupled to the computer system 1000.

[0078]

[0089] Computer system 1000 can be one of various types, including handheld portable devices (e.g., iPhone® cellular phone, iPad® computing tablet, PDA), wearable devices (e.g., Google Glass® head-mounted display), PCs, workstations, mainframes, kiosks, server racks, or any other data processing systems.

[0079]

[0090] Due to the ever-changing nature of computers and networks, the description of computer system 1000 shown in the figure is merely an example. Many other configurations are possible, having more or fewer components than the system shown in the figure. For example, customized hardware may also be used, and / or certain elements may be implemented in hardware, firmware, software (including applets), or a combination thereof. Furthermore, connectivity to other computing devices, such as network input / output devices, may be employed. Based on the disclosures and teachings provided herein, other ways and / or methods for implementing various embodiments should be apparent.

[0080]

[0091] As used herein, the terms “about,” “approximately,” or “substantially” should be interpreted as being within the range expected by those skilled in the art in light of this specification.

[0081]

[0092] In the above description, for the sake of clarity, numerous specific details have been included to provide a complete understanding of various embodiments. However, it will be apparent that some embodiments can be practiced without some of these specific details. In other cases, well-known structures and devices are shown in the form of block diagrams.

[0082]

[0093] The above description provides illustrative embodiments only and does not limit the scope, applicability, or configuration of this disclosure. Rather, the above description of various embodiments provides possible disclosures for implementing at least one embodiment. It should be understood that various modifications may be made in the function and arrangement of elements without departing from the spirit and scope of some of the embodiments described in the appended claims.

[0083]

[0094] Specific details are given in the above description to provide a complete understanding of the embodiments. However, it should be understood that embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in the form of block diagrams to avoid obscuring the embodiments with unnecessary details. In other cases, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary details to avoid obscuring the embodiments.

[0084]

[0095] Furthermore, note that individual embodiments have been described as processes, shown as flowcharts, flow diagrams, data flow diagrams, structural diagrams, or block diagrams. While flowcharts may describe operations as a continuous process, many operations can be performed in parallel and simultaneously. Moreover, the order of operations can be rearranged. A process terminates when its operations are complete, but it may have additional steps not shown in the diagram. A process can correspond to a method, function, procedure, subroutine, subprogram, etc. If a process corresponds to a function, its termination may correspond to the function's return to the calling function or main function.

[0085]

[0096] The term “computer-readable medium” includes, but is not limited to, portable or fixed-storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying one or more instructions and / or data. A code segment or machine-executable instruction may represent a procedure, function, subprogram, program, routine, subroutine, module, software package, class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or hardware circuit by passing and / or receiving information, data, arguments, parameters, or memory content. Information, arguments, parameters, data, etc., may be passed, forwarded, or transmitted via any preferred means, including memory sharing, message passing, token passing, network transmission, etc.

[0086]

[0097] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description language, or any combination thereof. When implemented by software, firmware, middleware, or microcode, program code or code segments for performing the required tasks may be stored in a machine-readable medium. One or more processors may perform the required tasks.

[0087]

[0098] While the features are described in the above specification with reference to specific embodiments, it should be noted that not all embodiments are limited thereto. Various features and aspects of several embodiments may be used individually or in combination. Furthermore, embodiments may be used in any number of environments and applications other than those described herein without departing from the broader spirit and scope of this specification. Accordingly, this specification and the drawings should be considered illustrative rather than restrictive.

[0088]

[0099] Furthermore, for explanatory purposes, the method has been described in a specific order. It should be understood that in alternative embodiments, the method may be carried out in a different order than that described. Also, it should be understood that the method described above may be carried out by hardware components, or by a sequence of machine-executable instructions used to cause a machine, such as a general-purpose or dedicated processor or a logic circuit programmed with instructions, to carry out the method. These machine-executable instructions may be stored on one or more machine-readable media, such as a CD-ROM or other type of optical disk, a floppy diskette, ROM, RAM, EPROM, EEPROM, a magnetic or optical card, flash memory, or other types of machine-readable media suitable for storing electronic instructions. Alternatively, the method may be carried out by a combination of hardware and software.

Claims

1. A method for identifying performance discrepancies between semiconductor processing devices, comprising causing one or more processors to perform an operation, the operation being: Accessing the causal network between processes and hardware within semiconductor processing devices, Using the causal relationships within the network and the first performance data, a first Bayesian model of the first semiconductor processing device is generated. Using the causal relationships within the network and the second performance data, a second Bayesian model of the second semiconductor processing device is generated. In order to determine whether the performance of the first semiconductor processing device matches the performance of the second semiconductor processing device, the response distributions generated by the first Bayesian model and the second Bayesian model are compared. Methods that include...

2. The operation is to identify variations in the first Bayesian model and the second Bayesian model that indicate the sensitivity of the response distribution to hardware components in the first semiconductor processing device and the second semiconductor processing device. The method according to claim 1, further comprising:

3. The operation involves identifying variations in internal variables in the first Bayesian model and the second Bayesian model that indicate the sensitivity of the response distribution to connections between hardware components within the first semiconductor processing device and the second semiconductor processing device. The method according to claim 1, further comprising:

4. The method according to claim 1, wherein the first Bayesian model is represented using a transfer function.

5. The method according to claim 4, wherein the transfer function represents the main effects, nonlinear effects, and interaction effects of the first semiconductor processing device that affect the response distribution of the first Bayesian model.

6. The operation is to perform a first decomposition of the transfer function by subtracting the second Bayesian model from the first Bayesian model in order to generate variations of the separate external variables over the operating range of the separate external variables. The method according to claim 4, further comprising:

7. The operation performs a second decomposition of the transfer function by consolidating each factor of the transfer function into variations in coefficients representing the internal variables with respect to the separate external variables. The method according to claim 6, further comprising:

8. One or more processors, One or more memory devices and The memory device, when executed by the one or more processors, provides to the one or more processors, Accessing the causal network between processes and hardware within semiconductor processing devices, Using the causal relationships within the network and the first performance data, a first Bayesian model of the first semiconductor processing device is generated. Using the causal relationships within the network and the second performance data, a second Bayesian model of the second semiconductor processing device is generated. In order to determine whether the performance of the first semiconductor processing device matches the performance of the second semiconductor processing device, the response distributions generated by the first Bayesian model and the second Bayesian model are compared. A system that includes instructions to perform an action that involves such an action.

9. The system according to claim 8, wherein the system is mounted on a controller of a semiconductor processing chamber.

10. The system according to claim 8, wherein the system is implemented on a central platform that communicates with controllers of multiple semiconductor processing chambers within the facility.

11. The system according to claim 8, wherein the system is implemented on a remote server that communicates with a plurality of different semiconductor processing facilities, and each of the plurality of different semiconductor processing facilities operates a plurality of semiconductor processing chambers.

12. Determining whether the performance of the first semiconductor processing device matches the performance of the second semiconductor processing device is: Calculate the J-S divergence between the response distributions generated by the first Bayesian model and the second Bayesian model. The system according to claim 8, including the above.

13. Determining whether the performance of the first semiconductor processing device matches the performance of the second semiconductor processing device is: To determine whether the similarity between the response distributions generated by the first Bayesian model and the second Bayesian model falls within the threshold of the effective equivalence region (ROPE). The system according to claim 8, including the above.

14. The system according to claim 8, wherein the operation further comprises performing a sensitivity analysis on an external variable to identify at least one external variable that causes the discrepancy in performance between the first semiconductor processing device and the second semiconductor processing device.

15. One or more non-temporary computer-readable media, which, when executed by one or more processors, to the one or more processors, Accessing the causal network between processes and hardware within semiconductor processing devices, Using the causal relationships within the network and the first performance data, a first Bayesian model of the first semiconductor processing device is generated. Using the causal relationships within the network and the second performance data, a second Bayesian model of the second semiconductor processing device is generated. In order to determine whether the performance of the first semiconductor processing device matches the performance of the second semiconductor processing device, the response distributions generated by the first Bayesian model and the second Bayesian model are compared. One or more non-temporary computer-readable media containing instructions that cause an action to be performed.

16. The one or more non-temporary computer-readable media according to claim 15, wherein the one or more non-temporary computer-readable media are distributed between the controller of the semiconductor processing chamber and the remote server.

17. The operation further comprises identifying the cause of the performance discrepancy between the first semiconductor processing device and the second semiconductor processing device, one or more non-transient computer-readable media according to claim 15.

18. The operation further comprises using the causal network to identify a hardware device, wherein the operating parameters of the hardware device are adjusted to correct the discrepancy in performance between the first semiconductor processing device and the second semiconductor processing device, one or more non-temporary computer-readable media according to claim 17.

19. The causal network comprises a node layer representing on-wafer effects, a node layer representing functional requirements, and a node layer representing hardware components, one or more non-temporary computer-readable media according to claim 15.

20. The aforementioned operation is, Accessing a system function map that includes a data structure relating the requirements of the first semiconductor processing device to the functional requirements of the components within the first semiconductor processing device, then to the technical components, and then to the on-wafer effects, The network is automatically generated from the aforementioned function map. One or more non-temporary computer-readable media according to claim 15, further comprising:

Images