Silicon photonics apparatus and manufacturing method for LIDAR sensors

Abstract

To provide a silicon photonics device for LIDAR.SOLUTION: A structure of a silicon photonics device for LIDAR includes a first insulating structure and a second insulating structure that are disposed above one or more etched silicon structures overlying a substrate member. A metal layer is disposed above the first insulating structure without a prior deposition of a diffusion barrier and an adhesion layer. A thin insulating structure is disposed above the second insulating structure. A first configuration of the metal layer, the first insulating structure and the one or more etched silicon structures forms a free-space coupler. A second configuration of the thin insulating structure above the second insulating structure forms an edge coupler.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure generally relates to silicon photonics devices, specifically, silicon photonics devices for light detection and ranging (LIDAR) applications and methods of manufacturing the same.

Background Art

[0002] LIDAR, also known as radar, is used in various applications including imaging and collision avoidance. Various components used in LIDAR systems, such as modulators, optical filters, optical switches, optical waveguides, photodiodes, phase shifters, wavelength converters, etc., are implemented on complementary metal oxide semiconductor (CMOS) compatible silicon photonics chips such as the silicon-on-insulator (SOI) platform. One of the main challenges facing the development of LIDAR systems is the inadequacies related to the coupling efficiency, wavelength sensitivity, reliability, and link budget performance of various components.

Summary of the Invention

[0003] According to one embodiment, this disclosure describes the structure of a silicon photonics apparatus for LIDAR. The silicon photonics apparatus includes a substrate member, an antenna formed on the substrate member, and a photodiode formed on the substrate member and coupled to the antenna. The antenna is a one-dimensional lattice coupler. The antenna includes primary formation of a first lattice structure on the upper part of the substrate member, secondary formation of a first metal layer on the upper part of the first lattice structure, and tertiary formation of a diffusion barrier and adhesive layer on the upper part of the first metal layer, wherein the diffusion barrier and adhesive layer and the first metal layer form a reflective mirror structure. For example, the first metal layer is an MT0 (Metal0) layer. For example, the first metal layer is any of the group consisting of aluminum, gold, silver, and copper. The antenna includes a first dielectric structure coupled to the first lattice structure. For example, the first dielectric structure is any of the group consisting of silicon nitride and silicon. The antenna includes a second lattice structure coupled to the substrate member and a first metal layer coupled to the second lattice structure. The antenna includes intermediate formation of an oxide layer between the substrate member and the first formation of the first lattice structure, and between the first formation of the first lattice structure and the second formation of the first metal layer. The silicon photonics device further includes a second dielectric structure coupled to a third dielectric structure, and the second and third dielectric structures form an edge coupler. For example, the first and third dielectric structures are coplanar. For example, the diffusion barrier and adhesive layer are one of the group consisting of tantalum nitride, indium oxide, copper silide, tungsten nitride, and titanium nitride. For example, the first distance between the lower end of the first dielectric structure and the upper end of the first lattice structure is in the range of 100 nanometers to 500 nanometers, the second distance between the lower end of the first metal layer and the upper end of the first lattice structure is in the range of 800 nanometers to 1200 nanometers, and the third distance between the upper end of the first dielectric structure and the lower end of the first metal layer is in the range of 500 nanometers to 1600 nanometers. For example, the fourth distance between the lower end of the second dielectric structure and the upper end of the third dielectric structure is approximately 450 nanometers. For example, the first dielectric structure and the third dielectric structure have the same height. For example, the height of the second dielectric structure is approximately three times or less the height of the third dielectric structure. For example, the height of the first metal layer is twice the height of the diffusion barrier and adhesive layer.This disclosure describes a LiDAR sensor including a silicon photonics device as described herein. This disclosure also describes an autonomous vehicle control system including a silicon photonics device as described herein.

[0004] According to one embodiment, the present disclosure describes the structure of a silicon photonics apparatus. The silicon photonics apparatus includes a substrate member and a first antenna formed on the substrate member. The first antenna includes a first lattice structure coupled to the substrate member, a first dielectric structure coupled to the first lattice structure, and a first metal layer coupled to the first dielectric structure. The silicon photonics apparatus further includes a second antenna formed on the substrate member. The second antenna includes a second lattice structure coupled to the substrate member, and the first metal layer is coupled to the second lattice structure. The silicon photonics apparatus further includes a photodiode formed on the substrate member and coupled to the second antenna. The first antenna further includes a diffusion barrier and an adhesive layer on top of the first metal layer, and the diffusion barrier, adhesive layer and first metal layer form a reflective mirror structure. The first antenna further includes an intermediate oxide layer between the first lattice structure and the first dielectric structure, and between the first dielectric structure and the first metal layer. For example, the first antenna is a one-dimensional lattice coupler. For example, the first metal layer is an MT0 (Metal0) layer. For example, the first metal layer is one of the group consisting of aluminum, gold, silver, and copper. For example, the first dielectric structure and the second dielectric structure are coplanar. For example, the first dielectric structure, the second dielectric structure, and the third dielectric structure are formed using either silicon nitride or silicon. For example, the diffusion barrier and adhesive layer are one of the group consisting of tantalum nitride, indium oxide, copper silicide, tungsten nitride, and titanium nitride. For example, the first distance between the lower end of the first dielectric structure and the upper end of the first lattice structure is in the range of 100 nanometers to 500 nanometers, the second distance between the lower end of the first metal layer and the upper end of the first lattice structure is in the range of 800 nanometers to 1200 nanometers, and the third distance between the upper end of the first dielectric structure and the lower end of the first metal layer is in the range of 500 nanometers to 1600 nanometers. For example, the fourth distance between the upper end of the second dielectric structure and the lower end of the third dielectric structure is approximately 450 nanometers. For example, the first and second dielectric structures have the same height. For example, the height of the third dielectric structure is approximately three times or less the height of the second dielectric structure. For example, the height of the first metal layer is twice the height of the diffusion barrier and adhesive layer.This disclosure describes a LiDAR sensor including a silicon photonics device as described herein. This disclosure also describes an autonomous vehicle control system including a silicon photonics device as described herein.

[0005] According to one embodiment, the present disclosure describes a method for manufacturing a silicon photonics apparatus for LIDAR. The method includes the steps of: obtaining a substrate material and forming a silicon structure on the substrate material; forming a first dielectric structure and a second dielectric structure on the silicon structure; placing a first oxide layer on the first dielectric structure and the second dielectric structure; forming a third dielectric structure on the first oxide layer and the second dielectric structure; forming a metal layer on the first oxide layer and the first dielectric structure; and forming a diffusion barrier and an adhesive layer on the metal layer. For example, the silicon structure is a lattice. For example, the diffusion barrier and adhesive layer on the metal layer form a reflective mirror structure. For example, the diffusion barrier and adhesive layer are any of the group consisting of tantalum nitride, indium oxide, copper silide, tungsten nitride, and titanium nitride. For example, the metal layer is any of the group consisting of aluminum, gold, silver, and copper. For example, the first dielectric structure and the second dielectric structure are coplanar with each other. The method further includes the step of forming a first dielectric structure by arranging a first layer of an insulating compound on a silicon structure and etching the first layer of the insulating compound to form a first dielectric structure. The method further includes the step of arranging a second layer of the insulating compound on the lower surface of a substrate member before etching the first layer of the insulating compound, and the step of removing the second layer of the insulating compound arranged on the lower surface of the substrate member after the first dielectric structure has been formed. For example, the first and second layers of the insulating compound are any of the group consisting of silicon nitride (Si3N4) and silicon. For example, the method of arranging a first layer of the insulating compound on a silicon structure and a second layer of the insulating compound on the lower surface of a substrate member is carried out by any of the group consisting of a low-pressure chemical vapor deposition (LPCVD) process and a plasma-enhanced chemical vapor deposition (PECVD) process. The method further includes the step of arranging a film of a resistive metal alloy heater on a silicon structure. The method further includes the step of forming a third dielectric structure by placing a second oxide layer on a metal layer, etching an opening in the second oxide layer on the second dielectric structure, and forming a third dielectric structure on the second dielectric structure within the opening.The method further includes the steps of forming a second silicon structure on a substrate material, doping a portion of the second silicon structure to form a photodiode, and forming a metal contact for the photodiode on the doped portion of the second silicon structure. The method further includes the steps of forming a second silicon structure on a substrate material, forming a second diffusion barrier and adhesive layer on the second silicon structure, forming a second metal layer on the second diffusion barrier and adhesive layer and the second silicon structure, and forming a third diffusion barrier and adhesive layer on the second metal layer. This disclosure describes a silicon photonics apparatus manufactured by the method described herein. This disclosure also describes a LIDAR sensor system including a silicon photonics apparatus manufactured by the method described herein.

[0006] According to one embodiment, the present disclosure describes a method for manufacturing a silicon photonics device for vehicles. The method includes the steps of: obtaining a substrate member and forming a first silicon structure bonded to the substrate member; forming a first oxide layer on the first silicon structure; forming a metal layer on the first oxide layer and the first silicon structure; and forming an adhesive layer on the metal layer configured to act as a diffusion barrier and adhere to the metal layer. The method further includes the steps of: forming a first dielectric structure on the first oxide layer and the first silicon structure; and forming a second oxide layer on the first dielectric structure, the second oxide layer being formed between the first oxide layer and the metal layer. The method further includes the steps of: performing chemical mechanical polishing of the first oxide layer; and forming a spacer between the first silicon structure and the first dielectric structure. The method further includes the steps of: forming a second silicon structure on the first oxide layer, the second oxide layer being formed on the second silicon structure; and forming a third silicon structure on the second silicon structure and the second oxide layer. For example, the first dielectric structure and the second silicon structure are coplanar with each other. The method further includes the steps of forming a first dielectric structure on a first oxide layer and etching the first layer of the insulating compound down to the first oxide layer to form a first dielectric structure on a first silicon structure. The method further includes forming a second layer of the insulating compound on the lower surface of a substrate member before etching the first layer of the insulating compound, and removing the second layer of the insulating compound formed on the lower surface of the substrate member after forming the first dielectric structure. The method further includes forming a third silicon structure on a second silicon structure and a second oxide layer by etching an opening in a second oxide layer formed on a second silicon structure and forming a third silicon structure within the opening. The method further includes forming a fourth silicon structure on a substrate member, doping one or more specific portions of the fourth silicon structure to form a photodiode, and forming one or more metal contacts for the photodiode on portions of the fourth silicon structure.For example, the first and second layers of the insulating compound include either silicon nitride (Si3N4) or silicon. For example, a method for forming a first layer of the insulating compound on a first oxide layer and a second layer of the insulating compound on the lower surface of a substrate member is carried out by either low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). For example, the first silicon structure is a lattice structure. For example, the metal layer includes either aluminum, gold, silver, or copper. For example, the adhesive layer includes either tantalum nitride, indium oxide, copper silicide, tungsten nitride, or titanium nitride. This disclosure describes a silicon photonics apparatus manufactured by the method described herein. This disclosure also describes a LIDAR sensor system including a silicon photonics apparatus manufactured by the method described herein.

[0007] Those skilled in the art will understand that this abstract is for illustrative purposes only and is not intended to limit in any way. Any feature described herein may be used in conjunction with any other feature, and any subset of such features may be used in combination depending on the various embodiments. Other aspects, original features, and advantages of the apparatus and / or process described herein, as defined solely by the claims, will become apparent from the detailed description presented herein together with the accompanying drawings. Furthermore, the language used in this disclosure has been chosen, in principle, for readability and explanatory purposes and does not limit the scope of the subject matter disclosed herein. [Brief explanation of the drawing]

[0008] Embodiments are shown as examples, not limitations, in the figures of the attached drawings where similar reference numbers refer to similar elements, hereby,

[0009] [Figure 1a] This is a block diagram showing an example of a hardware and software environment for an autonomous vehicle according to one embodiment.

[0010] [Figure 1b] This is a high-level schematic diagram of a silicon photonics apparatus for a coherent LIDAR system according to one embodiment.

[0011] [Figure 2] Figure 1b shows a schematic cross-sectional view illustrating the structure of a silicon photonics apparatus according to one embodiment.

[0012] [Figure 3] A schematic cross-sectional view illustrating a method for manufacturing the silicon photonics apparatus shown in Figure 1b according to one embodiment is shown. [Figure 4] A schematic cross-sectional view illustrating a method for manufacturing the silicon photonics apparatus shown in Figure 1b according to one embodiment is shown. [Figure 5] A schematic cross-sectional view illustrating a method for manufacturing the silicon photonics apparatus shown in Figure 1b according to one embodiment is shown. [Figure 6] A schematic cross-sectional view illustrating a method for manufacturing the silicon photonics apparatus shown in Figure 1b according to one embodiment is shown. [Figure 7] A schematic cross-sectional view illustrating a method for manufacturing the silicon photonics apparatus shown in Figure 1b according to one embodiment is shown. [Figure 8] A schematic cross-sectional view illustrating a method for manufacturing the silicon photonics apparatus shown in Figure 1b according to one embodiment is shown. [Figure 9] A schematic cross-sectional view illustrating a method for manufacturing the silicon photonics apparatus shown in Figure 1b according to one embodiment is shown. [Figure 10] A schematic cross-sectional view illustrating a method for manufacturing the silicon photonics apparatus shown in Figure 1b according to one embodiment is shown. [Figure 11] A schematic cross-sectional view illustrating a method for manufacturing the silicon photonics apparatus shown in Figure 1b according to one embodiment is shown. [Figure 12] A schematic cross-sectional view illustrating a method for manufacturing the silicon photonics apparatus shown in Figure 1b according to one embodiment is shown. [Figure 13] A schematic cross-sectional view is shown that illustrates a method of manufacturing a silicon photonics device shown in FIG. 1b according to one embodiment. [Figure 14] A schematic cross-sectional view is shown that illustrates a method of manufacturing a silicon photonics device shown in FIG. 1b according to one embodiment. [Figure 15] A schematic cross-sectional view is shown that illustrates a method of manufacturing a silicon photonics device shown in FIG. 1b according to one embodiment. [Figure 16] A schematic cross-sectional view is shown that illustrates a method of manufacturing a silicon photonics device shown in FIG. 1b according to one embodiment. [Figure 17] A schematic cross-sectional view is shown that illustrates a method of manufacturing a silicon photonics device shown in FIG. 1b according to one embodiment.

[0013] It should be understood that alternative embodiments of the structures and methods described herein can be employed without departing from the principles described herein.

Best Mode for Carrying Out the Invention

[0014] In the following description, numerous specific details are presented for the purpose of providing a thorough understanding of various aspects of the various exemplary embodiments. It should be noted that any particular exemplary embodiment can be implemented without all of the specific details and / or with variations, substitutions, and combinations of the various features and elements described herein. Hereinafter, embodiments of the present disclosure will be referred to in detail, and examples thereof are shown in the accompanying drawings. Wherever possible, the same reference numbers used in the drawings and the description refer to the same or similar components.

[0015] Furthermore, relative terms such as “bottom,” “bottom,” “rear,” or “down,” and “top,” “top,” or “front,” or “up,” can be used to describe the relationship between one element and other elements, as shown in the drawings. It will be understood that relative terms are intended to include various orientations of the apparatus in addition to the orientation shown in the drawings. For example, if the apparatus is inverted in one of the drawings, an element described as being on the “bottom” side of another element would face the “top” side of the other element. Thus, the exemplary term “bottom” may include both “bottom” and “top” directions, depending on the particular orientation of the drawing. Similarly, if the apparatus is inverted in one of the drawings, an element described as being on the “bottom” or “bottom” of another element would face the “top” of the other element. Thus, the exemplary term “bottom” or “bottom” may include both up and down directions.

[0016] Referring to the drawings, the same numbers indicate the same parts across several figures, and Figure 1a shows an exemplary hardware and software environment for an autonomous vehicle 100 in which various technologies disclosed herein can be implemented. For example, the vehicle 100 may include not only a powertrain 102 including a prime mover 104 that is driven by an energy source 106 and can power the drivetrain 108, but also a control system 110 including directional control 112, powertrain control 114, and brake control 116. The vehicle 100 can be implemented in any number of different types of vehicles, including vehicles that can transport people and / or cargo and can travel on land routes, and it should be understood that the aforementioned components 102-116 may vary considerably depending on the type of vehicle in which these components are utilized.

[0017] For simplicity, the embodiments discussed below focus on wheeled land vehicles such as passenger cars, vans, trucks, buses, etc. In such embodiments, the prime mover 104 may include one or more electric motors and / or internal combustion engines (among other things). The energy source 106 may include, for example, a fuel system (providing, for example, gasoline, diesel, hydrogen, etc.), a battery system, a solar panel or other renewable energy source, and / or a fuel cell system. The drive train 108 includes a transmission suitable for converting the output of the prime mover 104 into vehicle motion and / or any other mechanical drive components, as well as one or more brakes configured to stop or decelerate the vehicle 100 so that it can be controlled, and a direction or steering component suitable for controlling the trajectory of the vehicle 100 (e.g., a rack and pinion steering linkage that generally allows one or more wheels of the vehicle 100 to pivot about a vertical axis to change the angle of the wheel's plane of rotation relative to the longitudinal axis of the vehicle). In one embodiment, a combination of a power train and an energy source can be used (e.g., in the case of an electric / gas hybrid vehicle), and in other embodiments, multiple electric motors (e.g., dedicated to individual wheels or axles) can be used as the prime mover 104. In the case of a hydrogen fuel cell implementation, the prime mover 104 may include one or more electric motors, and the energy source 106 may include a fuel cell system driven by hydrogen fuel.

[0018] Direction control 112 may include one or more actuators and / or sensors for controlling and receiving feedback from direction or steering components so that the vehicle 100 can follow a desired trajectory. Powertrain control 114 controls the speed and / or direction of the vehicle 100 by being configured to control the output of the powertrain 102, for example, by controlling the output power of the prime mover 104 and controlling the gears of the transmission of the drivetrain 108. Brake control device 116 may be configured to control one or more brakes that slow down or stop the vehicle 100, for example, disc or drum brakes coupled to the wheels of the vehicle.

[0019] Other vehicle types, including but not limited to all-terrain vehicles, tracked vehicles, and construction machinery, may utilize a variety of powertrains, drivetrains, energy sources, directional control, powertrain control, and brake control. Furthermore, in one embodiment, some components may be combined, but for example, vehicle directional control is primarily handled by changing the output of one or more prime movers. Therefore, the embodiments disclosed herein are not limited to specific applications of the technologies described herein in autonomous land vehicles.

[0020] In the illustrated embodiment, full or semi-autonomous control of the vehicle 100 is performed by a vehicle control system 120, which may include one or more processors 122 and one or more memories 124, each processor 122 configured to execute program code instructions 126 stored in the memory 124. The multiple processors may include, for example, multiple graphics processing units ("GPUs") and / or multiple central processing units ("CPUs").

[0021] Sensor 130 may include a variety of sensors suitable for collecting information from the surrounding environment of the vehicle for use in controlling the operation of the vehicle 100. For example, sensor 130 may include one or more detection and distance measuring sensors (e.g., RADAR sensor 134, LIDAR sensor 136, or both), a 3D positioning sensor 138, and satellite navigation systems such as GPS (Global Positioning System), GLONASS (Globalnaya Navigazionnaya Sputnikovaya Sistema, or Global Navigation Satellite System), BeiDou Navigation Satellite System (BDS), Galileo, Compass, etc. The 3D positioning sensor 138 can be used to determine the vehicle's position on Earth using satellite signals. Sensor 130 may selectively include a camera 140 and / or an IMU (Inertial Measurement Unit) 142. Camera 140 may be a monographic or stereographic camera and may record still and / or video images. The IMU 142 may include a multi-gyroscope and accelerometer capable of detecting linear and rotational motion of the vehicle 100 from three directions. One or more encoders 144, such as wheel encoders, can be used to monitor the rotation of one or more wheels of the vehicle 100. In one embodiment, the LIDAR sensor 136 may include a silicon photonic device structure for a coherent LIDAR system, as described in detail below.

[0022] The output of sensor 130 may be provided to a set of control subsystems 150, including a position estimation subsystem 152, a perception subsystem 154, a planning subsystem 156, and a control subsystem 158. The position estimation subsystem 152 is primarily responsible for accurately determining the position and orientation (sometimes also called "attitude" or "attitude estimation") of vehicle 100, mainly within its surrounding environment and generally within some reference frame. The perception subsystem 154 is primarily responsible for detecting, tracking, and / or identifying objects in the surrounding environment of vehicle 100. A machine learning model according to one embodiment may be used to track objects. The planning subsystem 156 is primarily responsible for planning the trajectory or travel path of vehicle 100 over some time frame, given a desired destination as well as static and moving objects in the environment. A machine learning model according to one embodiment may be used to plan the vehicle trajectory. The control subsystem 158 is primarily responsible for generating appropriate control signals to control various controls of the vehicle control system 120 in order to implement the planned trajectory of vehicle 100. Similarly, a machine learning model can be used to generate one or more signals to control the autonomous vehicle 100 in order to execute a planned trajectory.

[0023] It should be understood that the set of components for the vehicle control system 12 shown in Figure 1a is merely one example. In one embodiment, individual sensors may be omitted. Additionally or alternatively, in one embodiment, multiple sensors of the same type shown in Figure 1a may be used redundantly and / or to cover various areas around the vehicle. There may also be other types of additional sensors other than those described above to provide actual sensor data related to the operation and environment of the wheeled land vehicle. Similarly, various types and / or combinations of control subsystems may be used in other embodiments. Also, although subsystems 152-158 are illustrated as separate from the processor 122 and memory 124, in one embodiment, some or all of the functions of subsystems 152-158 may reside in one or more memories 124 and be implemented as program code instructions 126 executed by one or more processors 122, and these subsystems 152-158 may, in some cases, be implemented using the same processor and / or memory. The subsystems can be implemented, at least partially, using various dedicated circuit logic, various processors, various field-programmable gate arrays ("FPGAs"), various application-specific integrated circuits ("ASICs"), various real-time controllers, and, as mentioned above, multiple subsystems may utilize circuits, processors, sensors, and / or other components. Furthermore, the various components of the vehicle control system 120 can be networked in various ways.

[0024] In one embodiment, the vehicle 100 may also include a secondary vehicle control system (not shown) that can be used as a redundant or backup control system for the vehicle 100. In one embodiment, the secondary vehicle control system may be able to fully operate the autonomous vehicle 100 in the event of an adverse event occurring in the vehicle control system 120, while in other embodiments, the secondary vehicle control system may have only limited functions, such as performing a controlled stop of the vehicle 100 in response to an adverse event detected by the main vehicle control system 120. In yet other embodiments, the secondary vehicle control system may be omitted.

[0025] Generally, various architectures, including various combinations of software, hardware, circuit logic, sensors, and networks, can be used to implement the various components shown in Figure 1a. Each processor can be implemented as, for example, a microprocessor, and each memory can include not only a random access memory ("RAM") device including main storage, but also any supplemental level of memory, such as cache memory, non-volatile or backup memory (e.g., programmable or flash memory), read-only memory, etc. Also, each memory can be considered to include memory storage physically located elsewhere in the vehicle 100, such as any cache memory within the processor, but also any storage capacity used as virtual memory to be stored, for example, in a mass storage device or other computer controller. One or more processors 122 shown in Figure 1a, or entirely separate processors, can be used to implement additional functions within the vehicle 100 other than for autonomous control purposes, such as entertainment system control, doors, lighting, and convenience functions.

[0026] Furthermore, for additional storage, the vehicle 100 may include one or more high-capacity storage devices, such as removable disk drives, hard disk drives, direct access storage devices ("DASD"), optical drives (e.g., CD drives, DVD drives, etc.), solid-state storage drives ("SSD"), network-attached storage, storage area networks, and / or tape drives.

[0027] Furthermore, the vehicle 100 may include a user interface 118 that enables the vehicle 100 to receive multiple inputs from a user or operator and generate outputs therefor, such as one or more displays, touchscreens, voice and / or gesture interfaces, buttons and haptic controls, etc. Otherwise, user input may be received via other computers or electronic devices, such as apps or web interfaces on mobile devices.

[0028] Furthermore, the vehicle 100 may include one or more network interfaces (e.g., network interface 162) suitable for communicating with one or more networks 176 to enable communication of information with other computers or electronic devices, including, for example, central services such as cloud services, thereby enabling it to receive information including machine learning models and other data learned for use in autonomous control. One or more networks 176 may be, for example, communication networks and may include one or more local area networks ("LANs") such as the Internet, Wi-Fi LANs, mesh networks, and one or more bus subsystems. One or more networks 176 may selectively utilize one or more standard communication technologies, protocols, and / or inter-process communication technologies. In one embodiment, data collected by one or more sensors 130 can be uploaded to a computing system 172 via the network 176 for additional processing.

[0029] In the illustrated embodiment, the vehicle 100 can communicate with a computing system 172 via a network 176 and signal lines 178. In one embodiment, the computing system 172 is a cloud-based computing device. A machine learning engine 166, which can operate on the computing system 172, generates machine learning models based on simulated scenarios and simulated sensor data for use in the autonomous control of the vehicle 100. The machine learning models are transmitted from the computing system 172 to the vehicle 100 and can be used by control subsystems 152-158 suitable for performing that function.

[0030] Not only the processors shown in Figure 1a, but also the various additional controllers and subsystems disclosed herein generally operate under the control of an operating system and execute or depend on various computer software applications, components, programs, objects, modules, data structures, etc., as described in detail below. Furthermore, various applications, components, programs, objects, modules, etc., may be executed on one or more processors of other computers (e.g., computing system 172) connected to the vehicle 100 via network 176, for example, in a distributed, cloud-based, or client-server computing environment, where the processing required to perform the functions of the computer program is assigned to multiple computers and / or services via the network.

[0031] Generally, routines performed to implement the various embodiments described herein, whether implemented as part of an operating system or as a specific application, component, program, object, module, or instruction sequence, or a subset thereof, are referred to herein as “program code.” Program code generally consists of one or more instructions residing in various memory and storage devices for various periods of time, which, when read and executed by one or more processors, perform the steps necessary to perform the steps or elements necessary to implement the various embodiments of this disclosure. While embodiments are described in the context of fully functional computers and systems, it should be understood that the various embodiments described herein can be distributed as various forms of program products, and such embodiments can be implemented regardless of the specific type of computer-readable medium used to actually carry out the distribution.

[0032] Examples of computer-readable media include non-temporary media such as volatile and non-volatile memory devices, floppy disks and other removable disks, solid-state drives, hard disk drives, magnetic tapes, and optical discs (e.g., CD-ROMs, DVDs, etc.).

[0033] Furthermore, the various program codes described below can be identified based on the application in which they are implemented in a particular embodiment. However, it should be understood that the specific program naming conventions used thereafter are merely for convenience, and therefore this disclosure should not be limited to use only in any particular application identified and / or implied by such naming conventions. Moreover, given that the ways in which a computer program can consist of routines, procedures, methods, modules, objects, etc., are generally limitless, and considering the various ways in which program functions are assigned to various software layers residing within a typical computer (e.g., operating systems, libraries, APIs, applications, applets, etc.), it should be understood that this disclosure is not limited to the specific structures and assignments of program functions described herein.

[0034] The exemplary environment shown in Figure 1a is not intended to limit the embodiments disclosed herein. In fact, other alternative hardware and / or software environments can be used without departing from the scope of the embodiments disclosed herein.

[0035] Figure 1b is an exemplary high-level schematic diagram of a silicon photonics apparatus 105 for a coherent LIDAR system according to one embodiment. The silicon photonics apparatus 105 includes a photodiode (PD) 125, a lattice coupler 145, an edge coupler 165, and a 2×2 mixer 180. In one embodiment, PD 125 may be a germanium (Ge) PD. In other embodiments, PD 125 may be a silicon PD, an indium gallium arsenide PD, a cadmium mercury telluride PD, a lead(II) sulfide PD, a molybdenum disulfide PD, a graphene PD, and / or a combination thereof. The lattice coupler 145 can be used to couple light to and from the silicon photonics apparatus 105. The operation of the lattice coupler 145 is related to refractive index changes caused by etching or deposition on a silicon-on-insulator (SOI) wafer during the manufacturing process. In one embodiment, the lattice coupler 145 may be a one-dimensional lattice coupler. For example, if the refractive index of the lattice coupler 145 changes in only one direction, it is a one-dimensional lattice coupler, and the light is coupled in the direction of the refractive index change. In another embodiment, the lattice coupler 145 may be a two-dimensional lattice coupler. The lattice couplers 145a, 145b, and 145c may be free-space couplers. The lattice couplers 145a and 145b are associated with the receiver antenna, and the lattice coupler 145c is associated with the transmitter antenna. Each 2x2 mixer 180 is a frequency mixer that receives as input one of the local oscillator (LO) signals (e.g., LOS and LOP) and the signal received via one of the lattice couplers (e.g., 145a and 145b) associated with the receiver antenna. The output signal from the mixer 180 is then directed to the photodiode 125 for detection and sensing. The edge coupler 165 is coupled to the amplifier 170, which is a light source for the silicon photonics device 105. For example, the amplifier 170 generates light that is coupled to the silicon photonics device 105 via the edge coupler 165.The transmit (TX) port, connected to the grid coupler 145c associated with the transmitter antenna, is connected directly or indirectly to the edge coupler 165.

[0036] Figure 2 shows a schematic cross-sectional view illustrating the structure of a silicon photonics apparatus 200 for a coherent LIDAR system according to one embodiment. The structure of the silicon photonics apparatus 200 is fabricated using an SOI wafer. As shown in Figure 3, the SOI wafer 300 may include an SOI layer 202, a buried oxide (BOX) layer 206, and a bulk silicon substrate member 204 that provides support for the SOI wafer. The BOX layer 206 is located between the SOI layer 202 and the bulk silicon substrate member 204. The SOI layer 202 can be etched and patterned with one or more silicon structures 402, 404, 406, and 408 bonded to the bulk silicon substrate member 204. For example, the SOI layer 202 may be a crystalline silicon (c-Si) layer. The portion of the c-Si layer placed on the BOX layer 206 can be selectively and partially etched to pattern one or more silicon structures 402, 404, 406, and 408. The silicon structures 402, 404, 406, and 408 may include one or more of the following: island structures, rib structures, grat structures, and slab structures. The silicon structures may include one or more heterogeneous lattice structures that form optical waveguides used for optical input and output. In addition to optical waveguides, other optical device structures such as lasers, optical modulators, photodetectors, and optical switches can also be fabricated on the SOI layer 202. The depth of the edges of the silicon structures partially etched on the SOI layer 202 may range from about 50 nm to about 300 nm. The thickness of the BOX layer 206 is, for example, about 3000 nm, but may range from about 1500 nm to about 3500 nm. Dielectric material or insulating compound layers can be placed on and etched onto the silicon structures to pattern one or more insulating or dielectric structures, as will be described in detail below. For example, the first insulating structure 702 is patterned and etched into an insulating compound layer to bond with the separated silicon structure 404. In this embodiment, the first insulating structure 702 lies coplanar with the second insulating structure 704. The thickness or height of the insulating structures 702 and 704 is approximately 400 nm in Figure 2, but may range from approximately 300 nm to approximately 600 nm.In some embodiments, the insulating composite layer may be a dielectric material with a higher refractive index than the cladding material it contacts. For example, the insulating compound layer may be a silicon nitride (Si3N4) layer. One advantage of using a Si3N4 layer in a silicon photonics chip for coherent LIDAR systems is its ability to handle higher optical power. In other examples, the insulating compound layer may be an amorphous silicon (a-Si) layer, a crystalline silicon (c-Si) layer, and so on. The distance between the bottom surface of the first insulating structure 702 and the top of the silicon structure is, for example, about 240 nm, but can range from about 100 nm to about 500 nm. The germanium (Ge) photodiode 125 can be fabricated on the silicon structure via doping.

[0037] The structure of the silicon photonics apparatus 200 may include a plurality of metal routing layers for forming interconnections: a metal 1 (MT1) layer 1002, a metal 2 (MT2) layer 1402, and a metal 3 (MT3) layer 1404. After the formation of the MT1 layer 1002, a metal 0 (MT0) layer 1108 may be bonded to the first insulating structure 702. In one embodiment, a diffusion barrier and adhesive layer 1106 may be bonded to the metal layer 1104. The diffusion barrier and adhesive layer 1106 may be located on top of or on the top of the metal layer 1104. The MT0 layer 1108, consisting of the metal layer 1104 and the diffusion barrier and adhesive layer 1106, may form a reflective mirror structure bonded to the first insulating structure 702. In other embodiments, the diffusion barrier and adhesive layer 1106, which has excellent optical properties such as reflectivity, may be located on top of and below the metal layer 1104. The diffusion barrier and adhesive layer 1106 may be tantalum nitride, indium oxide, copper silide, tungsten nitride, titanium nitride, and / or a combination thereof. An oxide layer or cladding 1408 is present, filling the spaces between the different structures formed on the silicon photonics apparatus 200. The distance separating the upper end of the first insulating structure 702 from the lower end of the MT0 layer 1108 is, for example, about 900 nm, but may range between about 500 nm and about 1600 nm. The distance separating the lower end of the MT0 layer 1108 from the upper end of the silicon structure 404 is about 1140 nm, but may range between about 800 nm and about 1200 nm. In one embodiment, the thickness of the metal layer 1104 may be twice the thickness of the diffusion barrier and adhesive layer 1106. For example, the thickness of the metal layer 1104 may be about 100 nm, and the thickness of the diffusion barrier and adhesive layer 1106 may be about 50 nm. Furthermore, a thin insulating structure 1302 made of the same insulating material as the first insulating structure 702 and the second insulating structure 704 may be bonded to the second insulating structure 704. For example, the thin insulating structure 1302 may be placed on top of the second insulating structure 704. In one embodiment, the thickness of the thin insulating structure 1302 may be about 3.6 times or less the thickness of the second insulating structure 704. For example, if the thickness of the second insulating structure 704 is about 400 nm, the thickness of the thin insulating structure 1302 is about 110 nm. The distance between the lower end of the thin insulating structure 1302 and the upper end of the second insulating structure 704 may be about 450 nm.

[0038] In Figure 2, one or more of the MT0 layer 1108, the first insulating structure 702, and the partially etched silicon structures 402, 404 form a lattice coupler 145 for coupling to free space. For example, the MT0 layer 1108 and the silicon structure 402 form a lattice coupler 145 associated with the receiver antenna of the silicon photonics device 200 for a coherent LiDAR system. In another example, the MT0 layer 1108, the first insulating structure 702, and the silicon structure 404 form a lattice coupler 145 associated with the transmitter antenna of the silicon photonics device 200 for a coherent LiDAR system. The MT0 layer 1108 functions as a silicon photonics chip-free space interface. The BOX layer 206 functions as a low optical refractive index cladding material. The oxide layer cladding 1408 also functions as a low optical refractive index cladding material. The cladding can be one or more layers of lower refractive index material in contact with a core material with a higher refractive index, such as silicon structures 402, 404 and insulating structures 702, 704. A thin insulating structure 1302, positioned on top of and overlapping the second insulating structure 704, forms an edge coupler 165 for coupling to other semiconductor devices or silicon photonics devices, such as an amplifier 170. The coupling of the thin insulating structure 1302 and the second insulating structure 704 functions as an amplifier-silicon photonics chip interface. Figure 2 shows the thin insulating structure 1302 and the second insulating structure 704 overlapping edge to edge, although it should be understood that there may be an offset in these overlaps. In one embodiment, the edge coupler 165 can be manufactured from a single insulating structure. An edge coupler 165 made from a double insulating structure 704 and 1302 configuration provides higher coupling efficiency (CE) than a single insulating structure configuration and better matches the optical modes of a coherent LIDAR system. In other embodiments, the structure of the edge coupler 165 can be patterned on the crystalline silicon (c-Si) layer itself, without the need to use an insulating compound such as Si3N4.

[0039] In one embodiment, the structure of the grid coupler 145 may be constructed using another upper insulating structure (not shown in Figure 2) on top of the first insulating structure 702. This upper insulating structure may consist of the same insulating material as the first insulating structure 702. The upper insulating structure or the first insulating structure 702 beneath it may be etched and patterned to form a plurality of isolated bars of the insulating structure, which are then coupled with the MT0 layer 1108 to form the grid coupler 145. For example, if a plurality of isolated bars of the insulating structure are patterned on the upper insulating structure, these isolated bars together with the MT0 layer 1108 may form a grid coupler associated with a receiver antenna. In another example, if a plurality of isolated bars of the insulating structure are patterned on the first insulating structure 702, these isolated bars together with the upper insulating structure and the MT0 layer 1108 may form a grid coupler associated with a transmitter antenna. In other embodiments, isolated bars of the silicon structures 402, 404 and the insulating structure patterned on the upper insulating structure or first insulating structure 702 may be mixed and matched with the MT0 layer 1108 to form a grid coupler 145.

[0040] The advantage of the etched and patterned grating coupler 145 structure on the silicon photonics apparatus 200 in Figure 2 is that it helps meet the link budget requirements for use in automotive-grade LIDAR systems. For example, the grating coupler 145 structure can reduce insertion loss at the interface between the silicon photonics apparatus 200 for coherent LIDAR and free space in both the transmit and receive paths, resulting in an improvement of approximately 2 dB to 6 dB in the overall link budget. The optical loss of a transmitter or output type grating coupler is calculated twice in the link budget because light leaves such a coupler, reflects from the target, and returns to the grating coupler. The grating coupler 145 structure can easily achieve a coupling loss of approximately 0.25 dB if there are no lithography constraints. With lithography constraints, the grating coupler 145 structure can facilitate the achievement of a coupling loss of approximately 0.5 dB to approximately 1.0 dB.

[0041] Figures 3 to 17 show schematic cross-sectional views illustrating a method for manufacturing a silicon photonics device according to one embodiment.

[0042] As shown in Figure 3, an SOI wafer 300 is provided. In one embodiment, the SOI wafer 300 may be a three-layer wafer comprising a bulk silicon substrate member 204 which is the first layer or base layer, an embedded oxide (BOX) layer 206 of an electrical insulating material such as silicon dioxide (SiO2) having a thickness of about 3000 nm as the second layer or intermediate layer, and an active crystalline silicon (c-Si) SOI layer 202 having a thickness of about 220 nm as the third layer or top layer.

[0043] As shown in Figure 4, the c-Si layer or SOI layer 202 shown in Figure 3 can be precisely patterned and etched to form heterogeneous silicon structures such as grats 402, ribs 404, islands 406, and slabs 408 placed on the BOX layer 206. The remainder of the SOI layer 202 shown in Figure 3 can be etched down to the BOX layer 206. The grats 402 silicon structure is etched to a depth of approximately 70 nm, and the slabs 408 silicon structure is etched to a depth of approximately 130 nm from the top. The ribs 404 structure is patterned and etched into isolated full-thickness (e.g., 220 nm) bars of silicon structure.

[0044] As shown in Figure 5, the oxide layer or cladding 502 is deposited on the silicon structures 402, 404, 406, and 408 to a height of approximately 240 nm from the top edge of the silicon structures 402, 404, 406, and 408. After oxide deposition, the top of the SOI wafer 300 undergoes a CMP (Chemical Mechanical Polishing) or planarization process. Such oxide layer deposition and planarization processes are performed to form spacers between the silicon structures 402, 404, 406, and 408 and the insulating compound or material that will be subsequently deposited on the top of the SOI wafer 300.

[0045] As shown in Figure 6, the first layer 602 and the second layer 604 of an insulating compound or material such as silicon nitride (Si3N4) are deposited on the upper part of the oxide layer 502 and on the lower part of the substrate member 204. Such deposition can be achieved using chemical vapor deposition. The thickness of the first layer 602 deposited on the upper part of the SOI wafer 300 is approximately 400 nm. In one embodiment, the chemical vapor deposition method used may be low-pressure chemical vapor deposition (LPCVD). In the LPCVD method, Si3N4 is deposited on both sides (upper and lower) of the SOI wafer 300. The LPCVD method can deform the SOI wafer 300 by applying strong tensile stress. Such double-sided deposition of Si3N4 is performed to eliminate the effects of tensile stress and prevent warping of the SOI wafer 300 structure. In one embodiment, plasma-enhanced chemical vapor deposition (PECVD) can be used as a method for depositing an insulating compound layer on the upper part of the SOI wafer 300. In the PECVD method, double-sided deposition of the insulating compound may not be necessary. In one embodiment, amorphous silicon (a-Si) can be used as the insulating compound.

[0046] As shown in Figure 7, the layer 602 deposited on top of the oxide layer 502 in Figure 6 is patterned and etched to form two coplanar insulating structures or dielectric elements 702 and 704 placed on top of the oxide layer 502. The insulating structure 702 may overlap and bond with the silicon structure 404. The remaining portion of the deposited layer 602 on top of the oxide layer 502 is etched down to the oxide layer 502. The thickness of the two coplanar insulating structures 702 and 704 is, for example, about 400 nm. After the deposited layer 602 on top of the SOI wafer 300 is patterned and etched, the SOI wafer 300 can be cleaned to remove all photoresist.

[0047] As shown in Figure 8, the layer 604 deposited on the lower part of the substrate member 204 in Figure 7 is removed after forming two coplanar insulating structures 702, 704. The tensile stress applied to the upper part of the SOI wafer 300 is released by patterning and etching the deposited layer 604 on the upper part of the SOI wafer 300 in Figure 6. To balance the tensile stress applied to the lower part of the SOI wafer 300, the layer 604 deposited on the lower part of the SOI wafer 300 in Figure 7 is removed. After the layer 604 deposited on the lower part of the SOI wafer 300 is removed, the upper edge of the SOI wafer 300 can be deeply cleaned to remove any contaminants that may have been transferred to the upper part of the SOI wafer 300.

[0048] As shown in Figure 9, an etched silicon structure 406 placed on the BOX layer 206 is doped to form a photodiode 125. For example, germanium can be used as a material to form the photodiode 125 in Figure 9. It should be understood that other materials such as silicon, indium gallium arsenide, lead(II) sulfide, cadmium mercury telluride, or combinations thereof can also be used to form their respective photodiodes. Following the formation of the photodiode 125, another oxide layer 902 is deposited on top of the SOI wafer 300.

[0049] As shown in Figure 10, three conductive vias are formed on the MT1 layer 1002 and the terminals of the photodiode 125. The MT1 layer 1002 and the conductive vias are formed by first depositing and patterning a first diffusion barrier and adhesive layer 1004a. Then, metal 1001 is deposited and patterned in the center. Finally, a second diffusion barrier and adhesive layer 1004b is deposited and patterned. That is, metal 1001 is sandwiched between two thin diffusion barriers and adhesive layers 1004a and 1004b. In one embodiment, metal 1001 can be deposited using one or more of aluminum, copper, gold, silver, or a combination thereof. In one embodiment, the diffusion barrier and adhesive layers 1004a and 1004b can be deposited using tantalum nitride (TaN). The thickness of the diffusion barrier and adhesive layers 1004a and 1004b is about 50 nm. The thickness of the metal 1001 deposited to form the MT1 layer 1002 is about 750 nm. The distance between the MT1 layer 1002 and the top of the silicon structure 402 is approximately 740 nm.

[0050] As shown in Figure 11, an MT0 layer 1108 is formed. The purpose of this new MT0 layer 1108 is to form a highly reflective mirror structure on the silicon photonics apparatus 105. After the formation of the MT1 layer 1102 shown in Figure 10, an oxide layer 1102 with a thickness of approximately 300 nm is deposited on top of the SOI wafer 300 as shown in Figure 11. A metal layer 1104 is deposited and patterned on top of the first insulating structure 702. The thickness of this deposited metal layer 1104 is approximately 100 nm. A diffusion barrier and adhesive layer 1106 can be deposited and patterned on top of the metal layer 1104 to improve adhesion. The thickness of this upper diffusion barrier and adhesive layer 1106 is approximately 50 nm. Thus, the deposited metal layer 1104 and the diffusion barrier and adhesive layer 1106 form the MT0 layer 1108 as shown in Figure 11. The formation of the MT0 layer 1108 differs in that the base diffusion barrier and adhesive layer are not deposited before the metal layer 1104. That is, the metal layer 1104 is deposited first without a diffusion barrier and adhesive layer beneath it. For example, tantalum nitride (TaN) material diffusion barriers and adhesive layers have low reflectivity. If the TaN diffusion barrier and adhesive layer are deposited before the metal layer 1104, this may negatively affect the reflectivity of the MT0 layer 1108 for forming a highly reflective mirror structure. In other embodiments, a material with excellent optical properties in terms of reflectivity can be used as the diffusion barrier and adhesive layer beneath the metal layer 1106. Between the subsequent formation of the MT1 layer 1002 and the MT0 layer 1108, there is a deliberate omission of the CMP (Chemical Mechanical Polishing) process for planarizing the SOI wafer 300. The CMP process can introduce uncertainty into the oxide spacing between the two different layers. Such a deliberate omission of the CMP process is done to minimize changes in oxide spacing. In one embodiment, the SOI wafer 300 may undergo a CMP process between the subsequent formation of the MT1 layer 1002 and the MT0 layer 1108. The openings can be etched within the oxide spacing to a desired depth to which the MT0 layer 1108 can be patterned. The configuration of the MT0 layer 1108, the insulating structure 702, and the silicon structures 402, 404 forms one or more grid couplers 145 as described herein.The distance between the bottom of the MT0 layer 1108 and the top of the silicon structure 404 is approximately 1140 nm. The distance between the bottom of the MT0 layer 1108 and the top of the insulating structure 702 is approximately 900 nm. The distance between the bottom of the first insulating structure 702 and the top of the silicon structure 404 is approximately 240 nm.

[0051] As shown in Figure 12, an MT1 layer 1002, an MT0 layer 1108, an oxide layer 1102, and another oxide layer 1202 are deposited on top of the other upper structures. After oxide deposition, the upper part of the SOI wafer 300 undergoes a CMP (Chemical Mechanical Polishing) or planarization process.

[0052] As shown in Figure 13, openings can be etched into the oxide layer 1202 on top of the second insulating structure 704. A thin layer of an insulating compound such as Si3N4 is deposited on the openings and patterned to form a thin insulating structure 1302 on top of the second insulating structure 704. The thickness of the thin insulating structure 1302 is approximately 110 nm. The distance between the bottom of the thin insulating structure 1302 and the top of the second insulating structure 704 is approximately 450 nm. The configuration of the thin insulating structure 1302 on top of the second insulating structure 704 forms an edge coupler 165 as described herein.

[0053] As shown in Figure 14, the backend of the line manufacturing steps is performed. This includes the formation of MT2 layer 1402 and MT3 layer 1404, the addition of conductive vias connecting the different metal layers, the deposition of more oxide layers 1408, the deposition of heater HTR 1406, and the execution of CMP processing steps. The thickness of the metal deposited on MT3 layer 1404 is approximately twice that of the metal deposited on MT2 layer 1402. For example, the thickness of the metal deposited on MT2 layer 1402 is approximately 1000 nm, and the thickness of the metal deposited on MT3 layer 1404 is approximately 2000 nm. Thin coatings of diffusion barriers and adhesive layers are deposited on the top and bottom of the deposited metal on MT2 layer 1402 and MT3 layer 1404. A thin film of a resistive metal alloy is deposited as heater HTR 1406 on the silicon structure etched from the SOI layer. An example of a resistive metal alloy is titanium nitride (TiN). HTR 1406 can be used to heat silicon photonics device chips. The heater HTR1406 can also be used to change the refractive index of waveguide structures useful for the operation of phase shifters and optical switches. The distance between the top of the MT2 layer 1402 and the bottom of the MT3 layer 1404 is approximately 800 nm. To form a contact on the silicon photonics device chip, an opening can be etched to a depth of approximately 200 nm in the oxide layer 1408 directly above the MT3 layer 1404.

[0054] As shown in Figure 15, a shallow trench DT_OX1502 is formed in the BOX layer 206 and a deep trench DT_SI1504 is formed in the substrate member 204. The formation of the shallow trench DT_OX1502 involves removing the oxide layer 1408 and the BOX layer 206 down to the substrate member 204. The depth of DT_SI1504 is approximately 150 μm.

[0055] As shown in Figure 16, undercut etching is performed to release the suspension structure.

[0056] As shown in Figure 17, the back surface of the SOI wafer 300 is polished to optical quality. The thickness of the substrate material or handle 204 is approximately 600 μm after back surface polishing of the SOI wafer 300.

[0057] The schematic diagram above is part of an integrated circuit chip design. The chip design is generated in a graphical computer programming language and stored in a computer-readable storage medium (e.g., disk, tape, physical hard drive, or virtual hard drive such as a storage access network). If the designer does not manufacture the chip or produce the photolithography mask used for chip manufacturing, the designer transmits the resulting design directly or indirectly to such an entity by physical means (e.g., providing a copy of the computer-readable storage medium containing the design) or electronically (e.g., via the internet). The stored design is generally converted into a suitable format (e.g., GDSII) for the production of a photolithography mask containing several copies of the chip design to be formed on a wafer. The photolithography mask is used to define the areas of the wafer (and / or layers on it) to be etched or processed.

[0058] The aforementioned detailed descriptions of this disclosure are presented for illustrative and explanatory purposes only. They are not intended to exhaustively or restrict the disclosure in the exact form it is disclosed. Many modifications and variations are possible in light of the foregoing teachings. The embodiments described are selected to best illustrate the principles of this disclosure and their practical application, thereby allowing those skilled in the art to best utilize this disclosure in various implementations and modifications suited to their specific intended uses. The scope of this disclosure is intended to be defined by the claims appended herein. While one embodiment of this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and variations can be made herein without departing from the idea and scope of this disclosure as defined by the appended claims. For example, it will be readily apparent to those skilled in the art that many of the features, functions, processes, and materials described herein can be modified within the scope of this disclosure. Furthermore, the scope of this disclosure is not intended to be limited to specific implementations of the processes, machines, manufactures, material compositions, means, methods, and steps described herein. Those skilled in the art will readily understand from the description in this disclosure a process, machine, fabrication, composition of a substance, means, method, or step that currently exists or will be developed in the future, performing substantially the same function. Furthermore, achieving substantially the same results as the corresponding implementations described herein can be utilized in this disclosure. Accordingly, the appended claims are intended to include within their scope such a process, machine, fabrication, composition of a substance, means, method, or step. This disclosure includes the following embodiments. (Embodiment 1) A method for manufacturing a silicon photonics device, The steps include obtaining a substrate material and forming a silicon structure on the substrate material, The steps include forming a first dielectric structure and a second dielectric structure on the silicon structure, The steps include arranging a first oxide layer on the first dielectric structure and the second dielectric structure, The steps include forming a third dielectric structure on the first oxide layer and the second dielectric structure, The steps include forming a metal layer on the first oxide layer and the first dielectric structure, A method comprising the steps of forming a diffusion barrier and an adhesive layer on the metal layer. (Embodiment 2) The silicon structure is a lattice, as described in Embodiment 1. (Embodiment 3) The step of forming the dielectric structure is The steps include: placing a first layer of insulating compound on the silicon structure; The method according to Embodiment 1, further comprising the step of etching the first layer of the insulating compound to form a first dielectric structure. (Embodiment 4) Before etching the first layer of the insulating compound, the step is to place a second layer of the insulating compound on the lower surface of the substrate member, The method according to Embodiment 3, further comprising the step of removing the second layer of the insulating compound disposed on the lower surface of the substrate member after forming the first dielectric structure. (Embodiment 5) The first and second layers of the insulating compound are silicon nitride (Si 3 N 4 The method according to Embodiment 4, which is any of the group consisting of ) and silicon. (Embodiment 6) The method according to Embodiment 4, wherein the steps of arranging a first layer of the insulating compound on a silicon structure and arranging a second layer of the insulating compound on the lower surface of the substrate member are carried out by one of the group consisting of low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD). (Embodiment 7) The method according to Embodiment 1, wherein the diffusion barrier and adhesive layer on the metal layer form a reflective mirror structure. (Embodiment 8) The method according to Embodiment 7, wherein the first dielectric structure and the second dielectric structure are located on the same plane as each other. (Embodiment 9) The third step of forming the dielectric structure is: The steps include placing a second oxide layer on the metal layer, The steps include etching an opening in the second oxide layer on the second dielectric structure layer, The method of Embodiment 7, comprising the step of forming the third dielectric structure on the second dielectric structure within the opening. (Embodiment 10) The method according to Embodiment 1, wherein the metal layer is any of the group consisting of aluminum, gold, silver, and copper. (Embodiment 11) The method according to Embodiment 1, wherein the diffusion barrier and adhesive layer are any of the group consisting of tantalum nitride, indium oxide, copper silicide, tungsten nitride, and titanium nitride. (Embodiment 12) The steps include forming a second silicon structure on the substrate member, The steps include doping a portion of the second silicon structure to form a photodiode, The method according to Embodiment 1, further comprising the step of forming a metal contact for a photodiode on the doped portion of the second silicon structure. (Embodiment 13) The steps include forming a second silicon structure on the substrate member, The steps include forming a second diffusion barrier and an adhesive layer on the second silicon structure, The steps include forming a second metal layer on the second diffusion barrier and adhesive layer and the second silicon structure, The method according to Embodiment 1, further comprising the step of forming a third diffusion barrier and an adhesive layer on the second metal layer. (Embodiment 14) The method according to Embodiment 1, further comprising the step of arranging a film of a resistive metal alloy heater on the silicon structure. (Embodiment 15) A silicon photonics apparatus manufactured by a process according to any one of Embodiments 1 to 14.

Claims

1. Substrate material and The antenna is formed on the substrate member, and the antenna is The first forming portion of the first lattice structure on the upper part of the substrate member, The second forming portion of the first metal layer is horizontally arranged at the upper part of the first lattice structure, and an oxide cladding layer is sandwiched between the first forming portion of the first lattice structure and the second forming portion of the first metal layer, The antenna includes a third forming portion of an adhesive layer horizontally positioned on the upper part of the first metal layer, the adhesive layer being configured to act as a diffusion barrier, and the adhesive layer and the first metal layer forming a reflective mirror structure and a silicon photonics device-free space interface. A photodiode formed on the substrate member and coupled to the antenna, A silicon photonics device equipped with the following features.

2. The silicon photonics apparatus according to claim 1, wherein the antenna is a one-dimensional lattice coupler.

3. The silicon photonics apparatus according to claim 1, wherein the antenna further comprises a first dielectric structure coupled to the first lattice structure.

4. The silicon photonics apparatus according to claim 3, further comprising a second dielectric structure coupled to a third dielectric structure, wherein the second dielectric structure and the third dielectric structure form an edge coupler.

5. The silicon photonics apparatus according to claim 4, wherein the first dielectric structure and the third dielectric structure are located on the same plane.

6. The silicon photonics apparatus according to claim 3, wherein the antenna includes an intermediate oxide layer forming portion between the substrate member and the first forming portion of the first lattice structure.

7. The aforementioned antenna is A second lattice structure bonded to the substrate member, The first metal layer bonded to the second lattice structure, The silicon photonics apparatus according to claim 3, further comprising:

8. The silicon photonics apparatus according to claim 3, wherein the first dielectric structure is any one of the group consisting of silicon nitride and silicon.

9. The silicon photonics apparatus according to claim 3, wherein the first metal layer combined with the adhesive layer is a layer bonded to the first dielectric structure.

10. The silicon photonics apparatus according to claim 3, wherein the first metal layer is any one of the group consisting of aluminum, gold, silver, and copper.

11. The silicon photonics apparatus according to claim 1, wherein the adhesive layer is any of the group consisting of tantalum nitride, indium oxide, copper silicide, tungsten nitride, and titanium nitride.

12. The silicon photonics apparatus according to claim 4, wherein the first distance between the lower end of the first dielectric structure and the upper end of the first lattice structure is in the range of 100 nanometers to 500 nanometers, the second distance between the lower end of the first metal layer and the upper end of the first lattice structure is in the range of 800 nanometers to 1200 nanometers, and the third distance between the upper end of the first dielectric structure and the lower end of the first metal layer is in the range of 500 nanometers to 1600 nanometers.

13. The silicon photonics apparatus according to claim 4, wherein the fourth distance between the lower end of the second dielectric structure and the upper end of the third dielectric structure is about 450 nanometers.

14. The silicon photonics apparatus according to claim 4, wherein the first dielectric structure and the third dielectric structure have the same height.

15. The silicon photonics apparatus according to claim 4, wherein the height of the second dielectric structure is approximately three times or less the height of the third dielectric structure.

16. The silicon photonics apparatus according to claim 1, wherein the height of the first metal layer is twice the height of the adhesive layer.

17. A LIDAR sensor equipped with a silicon photonics device, The aforementioned silicon photonics apparatus, Substrate material and The antenna is formed on the substrate member, and the antenna is The first forming portion of the first lattice structure on the upper part of the substrate member, The second forming portion of the first metal layer is horizontally arranged at the upper part of the first lattice structure, and an oxide cladding layer is sandwiched between the first forming portion of the first lattice structure and the second forming portion of the first metal layer, The antenna includes a third forming portion of an adhesive layer horizontally positioned on the upper part of the first metal layer, the adhesive layer being configured to act as a diffusion barrier, and the adhesive layer and the first metal layer forming a reflective mirror structure and a silicon photonics device-free space interface. A photodiode formed on the substrate member and coupled to the antenna, A LIDAR sensor equipped with [feature].

18. The antenna in the silicon photonics apparatus is The LIDAR sensor according to claim 17, further comprising a first dielectric structure coupled to the first lattice structure.

19. The aforementioned silicon photonics device is The LIDAR sensor according to claim 18, further comprising a second dielectric structure coupled to a third dielectric structure, wherein the second dielectric structure and the third dielectric structure form an edge coupler.

20. An autonomous vehicle control system equipped with a silicon photonics device, The aforementioned silicon photonics apparatus, Substrate material and The antenna is formed on the substrate member, and the antenna is The first forming portion of the first lattice structure on the upper part of the substrate member, The second forming portion of the first metal layer is horizontally arranged at the upper part of the first lattice structure, and an oxide cladding layer is sandwiched between the first forming portion of the first lattice structure and the second forming portion of the first metal layer, The antenna includes a third forming portion of an adhesive layer horizontally positioned on the upper part of the first metal layer, the adhesive layer being configured to act as a diffusion barrier, and the adhesive layer and the first metal layer forming a reflective mirror structure and a silicon photonics device-free space interface. A photodiode formed on the substrate member and coupled to the antenna, An autonomous vehicle control system equipped with the following features.

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