Multi-line programming behavior in artificial neural network arrays

Abstract

Numerous examples of programming multiple rows in an array of artificial neural networks as part of a single programming operation are disclosed. In one example, a method includes ramping up an output of a high voltage generator to a first voltage level, programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator while maintaining the output of the high voltage generator at the first voltage level, where K>1, and ramping down the output of the high voltage generator to a second voltage level after the programming step.

Description

[Technical Field]

[0001] (Claiming priority) This application claims priority to U.S. Patent Application No. 18 / 076,129, entitled "Multiple Row Programming Operation in Artificial Neural Network Array," filed on 6 December 2022, and to U.S. Provisional Patent Application No. 63 / 409,177, entitled "Multiple Row Programming Operation in Artificial Neural Network Array," filed on 22 September 2022.

[0002] (Field of Invention) Numerous examples of programming multiple lines in a single programming operation on an array of artificial neural networks are disclosed. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (such as the central nervous system of animals, particularly the brain), can rely on a large number of inputs, and are generally used to estimate or approximate unknown functions. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange messages with one another.

[0004] Figure 1 illustrates an artificial neural network, where circles represent inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to inputs and learn. Typically, a neural network contains multiple input layers. Typically, there are one or more hidden layers of neurons and an output layer of neurons that provides the output of the neural network. Neurons at each level make decisions individually or collectively based on the data they receive from synapses.

[0005] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of suitable hardware technology. In fact, practical neural networks rely on a very large number of synapses, which enables high connectivity between neurons and thus very high levels of parallel processing. In principle, such complexity can be achieved with digital supercomputers or dedicated graphics processing unit clusters. However, in addition to their high cost, these approaches also suffer from poor energy efficiency compared to biological networks, which consume far less energy because they primarily perform low-precision analog calculations. While CMOS analog circuits have been used for artificial neural networks, the synapses in most CMOS implementations are too large considering the large number of neurons and synapses.

[0006] The applicant previously disclosed, in U.S. Patent Application Publication No. 2017 / 0337466(A1), incorporated by reference, an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses. The non-volatile memory arrays operate as analog neural memory and comprise non-volatile memory cells arranged in rows and columns. The neural network includes a first plurality of synapses configured to receive a first plurality of inputs and therefrom produce a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses comprises a plurality of memory cells, each of which comprises spaced source and drain regions formed in a semiconductor substrate, with a channel region extending between them, a floating gate insulated and disposed above a first portion of the channel region, and a non-floating gate insulated and disposed above a second portion of the channel region. Each of the plurality of memory cells stores weight values ​​corresponding to the number of electrons in the floating gate. The plurality of memory cells generate a first plurality of outputs by multiplying the first plurality of inputs by the stored weight values. <Non-volatile skin cell>

[0007] Non-volatile memory is well known. For example, U.S. Patent No. 5,029,130 ​​("'130"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, a type of flash memory cell. Such a memory cell 210 is shown in Figure 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed insulated above a first portion of the channel region 18 (and controlling the conductivity of the first portion of the channel region 18) and extends above a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed insulated above a second portion of the channel region 18 (and controlling the conductivity of the second portion of the channel region 18) and a second portion extending upward above the floating gate 20. The floating gate 20 and word line terminal 22 are insulated from the substrate 12 by the gate oxide. The bit line 24 is coupled to the drain region 16.

[0008] By applying a positive high voltage to the word line terminal 22, the memory cell 210 is erased (electrons are removed from the floating gate), causing the electrons in the floating gate 20 to pass through the insulator between them to the word line terminal 22 via a Fowler-Nordheim (FN) tunnel.

[0009] The memory cell 210 is programmed by source-side injection (SSI) of hot electrons by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14 (electrons are added to the floating gate). The electron flow flows from the drain region 16 towards the source region 14. The electrons are accelerated and generate heat when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 via the gate oxide due to the electrostatic attraction from the floating gate 20.

[0010] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and the word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 becomes positively charged (i.e., electrons are erased), the portion of the channel region 18 below the floating gate 20 also becomes turned on, and current flows through the channel region 18, which is detected as the erased state, i.e., the "1" state. When the floating gate 20 becomes negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 becomes almost or completely turned off, and current does not flow (or hardly flows) through the channel region 18, which is detected as the programmed state, i.e., the "0" state.

[0011] Table 1 shows the typical voltage / current ranges that can be applied to the terminals of the memory cell 210 to perform read, erase, and program operations. Table 1: Operations of the flash memory cell 210 in FIG. 2 [Table 1]

[0012] Other split-gate memory cell configurations are also known, which are other types of flash memory cells. For example, FIG. 3 shows a four-gate memory cell 310 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent No. 6,747,310, which is hereby incorporated by reference for all purposes. Here, all gates are non-floating gates except for the floating gate 20, that is, they are electrically connected or connectable to a voltage source. Programming is performed by injecting hot electrons themselves from the channel region 18 into the floating gate 20. Erasure is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0013] Table 2 shows typical voltage / current ranges that can be applied to the terminals of the memory cell 310 to perform read, erase, and program operations. Table 2: Operations of the Flash Memory Cell 310 in FIG. 3 [Table 2]

[0014] FIG. 4 shows a three-gate memory cell 410, which is another type of flash memory cell. The memory cell 410 is the same as the memory cell 310 in FIG. 3 except that the memory cell 410 does not have a separate control gate. (Erasure occurs through the use of an erase gate) The erase operation and the read operation are the same as those in FIG. 3 except that no control gate bias is applied. Since the programming operation is also performed without a control gate bias, as a result, a higher voltage is applied to the source line during the programming operation to compensate for the lack of control gate bias.

[0015] Table 3 shows typical voltage / current ranges that may be applied to the terminals of the memory cell 410 to perform read, erase, and program operations. Table 3: Operation of flash memory cell 410 in Figure 4 [Table 3]

[0016] Figure 5 shows a different type of flash memory cell, a stacked gate memory cell 510. Memory cell 510 is similar to memory cell 210 in Figure 2, except that the floating gate 20 extends above the entire channel region 18, and the control gate 22 (where coupled to the word line) extends above the floating gate 20, separated by an insulating layer (not shown). Erase is performed by FN tunneling of electrons from the FG to the substrate, programming is performed by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, and read operations are performed by electrons flowing from the source region 14 to the drain region 16, similar to the read operation of memory cell 210, which has a higher control gate voltage.

[0017] Table 4 shows typical voltage ranges that can be applied to the terminals of the memory cell 510 and the circuit board 12 for performing read, erase, and program operations. Table 4: Operation of flash memory cell 510 in Figure 5 [Table 4]

[0018] The methods and means described herein may be applied to other non-volatile memory technologies, including but not limited to FINFET split-gate flash or stack-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive random-access memory), PCM (phase change memory), MRAM (magnetic random-access memory), FeRAM (ferroelectric random-access memory), CT (charge trap) memory, CN (carbon-tube) memory, OTP (one-time programmable, bi-level or multi-level), and CeRAM (correlated electron random-access memory).

[0019] Two modifications are made to utilize a memory array containing one of the non-volatile memory cell types in the artificial neural network described above. First, lines are configured to allow each memory cell to be programmed, erased, and read individually without adversely affecting the memory state of other memory cells in the array, as will be further described below. Second, sequential (analog) programming of the memory cells is provided.

[0020] Specifically, the memory state of each memory cell in the array (i.e., the charge on the floating gate) can be changed independently and continuously, with minimal disturbance to other memory cells, from a completely erased state to a fully programmed state, and vice versa. This means that cell memory is essentially analog, or can store at least one of a number of discontinuous values ​​(such as 16 or 64 different values), making every memory cell in the memory array highly precise and individually tunable, and making the memory array ideal for memory and fine-tuning of synaptic weights in neural networks. <Neural networks using memory cell arrays>

[0021] Figure 6 conceptually illustrates an unrestricted example of a neural network utilizing a non-volatile memory array in this example. While this example uses a non-volatile memory array neural network for a facial recognition application, it is also possible to implement other suitable applications using a non-volatile memory array-based neural network.

[0022] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). The synapse CB1, going from input layer S0 to layer C1, scans the input image with a 3x3 pixel overlapping filter (kernel), applying different weight sets to some instances and shared weights to others, and shifts the filter by one pixel (or more than two pixels depending on the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., referred to as the filter or kernel) are provided to synapse CB1, where these nine input values ​​are multiplied by appropriate weights, and after adding the outputs of the multiplications, a single output value is determined, which is then given by the first synapse of CB1 to generate one of the pixels in the feature map of layer C1. The 3x3 filter is then shifted one pixel to the right within the input layer S0 (i.e., a column of 3 pixels is added to the right and a column of 3 pixels is dropped to the left), thereby providing the 9 pixel values ​​of this newly positioned filter to synapse CB1, where they are multiplied by the same weights as above, determining a second single output value by the associated synapse. This process continues until the 3x3 filter has scanned the entire 32x32 pixel image of the input layer S0 for all three colors and all bits (precision values). The process is then repeated with different weight sets to generate different feature maps of layer C1 until all feature maps of layer C1 have been computed.

[0023] In this example, layer C1 contains 16 feature maps, each having 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel; therefore, each feature map is a two-dimensional array, and thus in this example, layer C1 constitutes 16 layers of two-dimensional arrays (note that the layers and arrays referred to herein are logical relationships, not necessarily physical relationships; i.e., arrays are not necessarily oriented to physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of 16 different synaptic weight sets applied to the filtered scan. All C1 feature maps can target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first weight set shared across all scans used to generate this first map) can identify circular edges, a second map (generated using a second weight set different from the first) can identify rectangular edges or the aspect ratio of a particular feature, and so on.

[0024] Before moving from layer C1 to layer S1, an activation function P1 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions within each feature map. The purpose of the pooling function P1 is to average neighbor positions (or use the max function), for example, to reduce dependence on edge positions, and to reduce the data size before moving to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays, each 15x15 pixels). Synapse CB2, moving from layer S1 to layer C2, scans the maps in layer S1 with a 4x4 filter, shifting by 1 pixel. In layer C2, there are 22 12x12 feature maps. Before moving from layer C2 to layer S2, an activation function P2 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions within each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3, which goes from layer S2 to layer C3, an activation function (pooling) is applied, where all neurons in layer C3 are connected to all maps in layer S2 via each synapse of CB3. There are 64 neurons in layer C3. Synapse CB4, which goes from layer C3 to output layer S3, completely connects C3 to S3; that is, all neurons in layer C3 are connected to all neurons in layer S3. The output in S3 contains 10 neurons, where the neuron with the highest output determines the class. This output can, for example, indicate the identification or classification (classification) of the content of the original image.

[0025] Each layer of a synapse is implemented using an array or a portion of an array of non-volatile memory cells.

[0026] Figure 7 is a block diagram of an array that can be used for that purpose. The vector-by-matrix multiplication (VMM) array 32 contains non-volatile memory cells and is used as synapses between one layer and the next (e.g., CB1, CB2, CB3, and CB4 in Figure 6). Specifically, the VMM array 32 includes an array of non-volatile memory cells 33, erase gate and word line gate decoders 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, each of which decodes its respective input to the non-volatile memory cell array 33. Input to the VMM array 32 can be from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the non-volatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the non-volatile memory cell array 33.

[0027] The non-volatile memory cell array 33 serves two purposes. Firstly, it stores the weights used by the VMM array 32. Secondly, the non-volatile memory cell array 33 effectively multiplies the weights stored in the non-volatile memory cell array 33 by the inputs, adds them up for each output line (source line or bit line) to generate an output, which becomes the input to the next layer or the last layer. By having the non-volatile memory cell array 33 perform the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated, and the calculations are more power-efficient due to being performed in memory.

[0028] The output of the non-volatile memory cell array 33 is fed to a differential adder (such as an adding operational amplifier or an adding current mirror) 38, which adds the outputs of the non-volatile memory cell array 33 to create a single value for its convolution. The differential adder 38 is configured to perform the summation of positive and negative weights.

[0029] The summed output values ​​of the differential adder 38 are then fed to an activation function block 39, which normalizes the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The normalized output values ​​of the activation function block 39 become elements of a feature map as the next layer (e.g., C1 in Figure 6), and are then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes multiple synapses (receiving input from the previous layer of the neuron or from an input layer such as an image database), and the summing operational amplifier 38 and activation function block 39 constitute multiple neurons.

[0030] The inputs to the VMM array 32 in Figure 7 (WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog level), and the outputs can be analog level, binary level, or digital bits (in which case an output ADC is provided to convert the output analog level to digital bits).

[0031] Figure 8 is a block diagram showing the use of multiple layers of the VMM array 32, labeled in the figure as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in Figure 8, the input (indicated as Inputx) is converted from digital to analog by the digital-to-analog converter 31 and provided to the input VMM array 32a. The converted analog input can be voltage or current. Input D / A conversion of the first layer can be performed by using a function or LUT (look-up table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM array 32a. Input conversion can also be performed by an analog-to-analog (A / A) converter to convert an external analog input to the mapped analog input to the input VMM array 32a.

[0032] The output generated by input VMM array 32a is provided as input to the next VMM array (hidden level 1) 32b, the next VMM array (hidden level 1) 32b generates an output that is provided as input to the next input VMM array (hidden level 2) 32c, and so on. The various layers of VMM array 32 function as the synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a standalone physical non-volatile memory array, or multiple VMM arrays can utilize different parts of the same physical non-volatile memory array, or multiple VMM arrays can utilize overlapping parts of the same physical non-volatile memory array. The example shown in Figure 8 includes five layers (32a, 32b, 32c, 32d, 32e), namely one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will understand that this is merely an example and that a system may instead include more than two hidden layers and more than two fully connected layers. <Vector × Matrix Multiplication (VMM) Array>

[0033] Figure 9 shows a neuron VMM array 900, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (located at the top of the array). Alternatively, another reference array may be located at the bottom.

[0034] In the VMM array 900, control gate lines such as control gate line 903 extend vertically (thus the row-direction reference array 902 is perpendicular to the control gate line 903), and erase gate lines such as erase gate line 904 extend horizontally. Here, inputs to the VMM array 900 are provided to the control gate lines (CG0, CG1, CG2, CG3), and outputs of the VMM array 900 appear on the source lines (SL0, SL1). In one example, only even rows are used, and in another example, only odd rows are used. The current on each source line (SL0, SL1, respectively) performs the function of summing all the currents from the memory cells connected to that particular source line.

[0035] As described herein with respect to neural networks, the non-volatile memory cells of the VMM array 900, i.e., the memory cells 310 of the VMM array 900, may be configured to operate in a region below a threshold.

[0036] The non-volatile reference memory cells and non-volatile memory cells described herein are biased with weak inversion (in the region below the threshold) as follows: Ids = Io × e (Vg-Vth) / nVt =w × Io × e (Vg) / nVt , In the formula, w=e (-Vth) / nVt And, Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, Vt is the thermal voltage = k × T / q, where k is Boltzmann's constant, T is the Kelvin temperature, q is the electron charge, n is the gradient coefficient = 1 + (Cdep / Cox), where Cdep is the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is (Wt / L) × u ​​× Cox × (n-1) × Vt 2 It is proportional to , where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0037] When using an IV logarithmic converter that converts input current to input voltage using a memory cell (such as a reference memory cell or peripheral memory cell) or transistor: Vg = n × Vt × log[Ids / wp × Io] In the formula, wp is the w of the reference or peripheral memory cell.

[0038] For a memory array used as a vector × matrix multiplier VMM array with current input, the output current is as follows: Iout=wa×Io×e (Vg) / nVt That is to say Iout = (wa / wp) × Iin = W × Iin W=e (Vthp-Vtha) / nVt Here, wa = w of each memory cell in the memory array. Vthp is the effective threshold voltage of the peripheral memory cell, and Vtha is the effective threshold voltage of the main (data) memory cell. Note that the threshold voltage of a transistor is a function of the substrate bias voltage, and the substrate bias voltage, denoted as Vsb, can be modulated to compensate for various conditions at such temperatures. The threshold voltage Vth can be expressed as follows: Vth=Vth0+gamma(SQRT|Vsb-2×φF)-SQRT|2×φF|) In the formula, Vth0 is the threshold voltage with zero substrate bias, φF is the surface potential, and gamma is the body effect parameter.

[0039] Word lines or control gates can be used as inputs to memory cells for input voltage.

[0040] Alternatively, the flash memory cells of the VMM array described herein can be configured to operate in a linear region. Ids=beta×(Vgs-Vth)×Vds, beta=u×Cox×Wt / L W=α(Vgs-Vth) In other words, the weight W in the linear region is proportional to (Vgs - Vth).

[0041] A word line, a control gate, a bit line, or a source line can be used as an input to a memory cell operating in a linear region. A bit line or a source line can be used as an output of a memory cell.

[0042] For an I-V linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor operating in a linear region can be used to linearly convert an input / output current into an input / output voltage.

[0043] Alternatively, the memory cells of the VMM array described herein can be configured to operate in a saturation region. Ids = 1 / 2×beta×(Vgs - Vth) 2 , where beta = u×Cox×Wt / L Wα(Vgs - Vth) 2 , that is, the weight W is proportional to (Vgs - Vth) 2

[0044] A word line, a control gate, or an erase gate can be used as an input to a memory cell operating in a saturation region. A bit line or a source line can be used as an output of an output neuron.

[0045] Alternatively, the memory cells of the VMM array described herein can be used in all regions or combinations thereof (below threshold, linear, or saturation) for each layer or multiple layers of a neural network.

[0046] Another example for the VMM array 32 of FIG. 7 is described in U.S. Patent No. 10,748,630, which is incorporated herein by reference. As described in the above application, a source line or a bit line can be used as a neuron output (current sum output).

[0047] ​Figure 10 shows a neuron VMM array 1000, particularly suited to the memory cell 210 shown in Figure 2 and used as a synapse between the input layer and the next layer. The VMM array 1000 includes a memory array 1003 of non-volatile memory cells, a reference array 1001 of first non-volatile reference memory cells, and a reference array 1002 of second non-volatile reference memory cells. The reference arrays 1001 and 1002, arranged in the column direction of the array, function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1014 (partially shown) with current inputs flowing in. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference miniarray matrix (not shown).

[0048] The memory array 1003 serves two purposes. First, it stores the weights used by the VMM array 1000 in each memory cell. Second, the memory array 1003 effectively multiplies the weights stored in it by the inputs (i.e., the current inputs supplied to terminals BLR0, BLR1, BLR2, and BLR3, which are converted into input voltages by the reference arrays 1001 and 1002 and supplied to word lines WL0, WL1, WL2, and WL3), then adds all the results (memory cell currents) to generate the outputs of each bit line (BL0~BLN), which become inputs to the next layer or the last layer. By performing multiplication and addition functions, the memory array 1003 eliminates the need for separate multiplication and addition logic circuits and is also power efficient. Here, voltage inputs are supplied to word lines WL0, WL1, WL2, and WL3, and outputs appear on the respective bit lines BL0 to BLN during the read (inference) operation. Each current in bit lines BL0 to BLN performs the function of summing the currents from all non-volatile memory cells connected to that particular bit line.

[0049] Table 5 shows the operating voltages and currents of the VMM array 1000. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 5: Operation of VMM Array 1000 in Figure 10 [Table 5]

[0050] Figure 11 shows a neuron VMM array 1100, which is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1100 includes a memory array 1103 of non-volatile memory cells, a reference array 1101 of a first non-volatile reference memory cell, and a reference array 1102 of a second non-volatile reference memory cell. The reference arrays 1101 and 1102 extend in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that the word lines in the VMM array 1100 extend vertically. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on the source lines (SL0, SL1) during read operations. The current on each source line performs the function of summing all the currents from the memory cells connected to that particular source line.

[0051] Table 6 shows the operating voltages and currents of the VMM array 1100. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 6: Operation of VMM Array 1100 in Figure 11 [Table 6]

[0052] Figure 12 shows a neuron VMM array 1200, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of a first nonvolatile reference memory cell, and a reference array 1202 of a second nonvolatile reference memory cell. The reference arrays 1201 and 1202 function to convert the current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second nonvolatile reference memory cells are diode-connected through a multiplexer 1212 (partially shown) with current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Each multiplexer 1212 includes a separate multiplexer 1205 and a cascoding transistor 1204 to ensure that the respective bit lines (such as BLR0) of the first and second non-volatile reference memory cells maintain a constant voltage during read operations. The reference cells are tuned to a target reference level.

[0053] The memory array 1203 serves two purposes. First, it stores the weights used by the VMM array 1200. Second, the memory array 1203 effectively multiplies the weights stored in the memory array by the inputs (current inputs supplied to terminals BLR0, BLR1, BLR2, and BLR3, which are converted into input voltages by the reference arrays 1201 and 1202 and supplied to the control gates (CG0, CG1, CG2, and CG3)), then adds all the results (cell currents) to produce an output, which appears in BL0~BLN and becomes the input to the next layer or the last layer. By having the memory array perform the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated, and power efficiency is also improved. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3), and the output appears in the bit lines (BL0~BLN) during read operations. The current in each bit line performs the function of adding up all the currents from the memory cells connected to that particular bit line.

[0054] The VMM array 1200 performs one-way tuning of the non-volatile memory cells in the memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is applied to the floating gate (resulting in an incorrect value being stored in the cell), the cell is erased and the series of partial programming operations is restarted from the beginning. As shown, two rows sharing the same erase gate (such as EG0 or EG1) are erased together (known as page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0055] Table 7 shows the operating voltages and currents of the VMM array 1200. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, control gates of selected cells, control gates of unselected cells in the same sector as the selected cell, control gates of unselected cells in a different sector than the selected cell, erase gates of selected cells, erase gates of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 7: Operation of VMM Array 1200 in Figure 12 [Table 7]

[0056] Figure 13 shows a neuron VMM array 1300, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1300 comprises a memory array 1303 of nonvolatile memory cells, a reference array 1301 or a first nonvolatile reference memory cell, and a reference array 1302 of a second nonvolatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 extend vertically, and the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1300 is similar to the VMM array 1400 except that the VMM array 1300 performs bidirectional tuning, and each individual cell can be completely erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate by using individual EG lines. As shown, reference arrays 1301 and 1302 convert the input currents at terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1314), and these voltages are applied to memory cells in the row direction. Current outputs (neurons) are located in the bit lines BL0~BLN, and each bit line sums all the currents from the non-volatile memory cells connected to that particular bit line.

[0057] Table 8 shows the operating voltages and currents of the VMM array 1300. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, control gates of selected cells, control gates of unselected cells in the same sector as the selected cell, control gates of unselected cells in a different sector than the selected cell, erase gates of selected cells, erase gates of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 8: Operation of VMM Array 1300 in Figure 13 [Table 8]

[0058] Figure 22 shows a neuron VMM array 2200 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapse and neuron between the input layer and the next layer. In the VMM array 2200, the input 0. ..., INPUT N These are bit lines BL0, ..., BL, respectively. N The signal is received, and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0059] Figure 23 shows a neuron VMM array 2300 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapse and neuron between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received by source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method].

[0060] Figure 24 shows a neuron VMM array 2400 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are the word lines WL0, ..., WL, respectively. M Received by, output OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method].

[0061] Figure 25 shows a neuron VMM array 2500 that is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are the word lines WL0, ..., WL, respectively. M Received by, output OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method].

[0062] Figure 26 shows a neuron VMM array 2600 that is particularly suitable for the memory cell 410 shown in Figure 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT n However, each of them is a vertical control gate line CG0, ..., CG N The signal is received, and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0063] Figure 27 shows a neuron VMM array 2700 that is particularly suitable for the memory cell 410 shown in Figure 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the inputs are INPUT0, ..., INPUT N These are bit lines BL0, ..., BL, respectively. N The bit line control gates 2701-1, 2701-2, ..., 2701-(N-1) and 2701-N, which are coupled to the bit line control gates, are received by the gates. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0064] Figure 28 shows a neuron VMM array 2800, which is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are the word lines WL0, ..., WL, respectively.M Received by, output OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N It is generated in [location].

[0065] Figure 29 shows a neuron VMM array 2900 that is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are control gate lines CG0, ..., CG M It is received as follows. Output OUTPUT0, ..., OUTPUT N These are the vertical source lines SL0, ..., SL, respectively. N It is generated in each source line SL i It is coupled to the source lines of all memory cells in column i.

[0066] Figure 30 shows a neuron VMM array 3000, which is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are control gate lines CG0, ..., CG M It is received as follows. Output OUTPUT0, ..., OUTPUT N These are the vertical bit lines BL0, ..., BL N Generated in each bit line BL i It is coupled to the bit lines of all memory cells in column i. <Long-term and short-term memory>

[0067] Prior art includes the concept known as long short-term memory (LSTM). LSTM units are often used within neural networks. LSTMs allow neural networks to store information for a predetermined period and use that information in subsequent operations. A conventional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell, and the duration for which information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0068] Figure 14 shows an exemplary LSTM1400. In this example, the LSTM1400 includes cells 1401, 1402, 1403, and 1404. Cell 1401 receives the input vector x0 and generates the output vector h0 and the cell state vector c0. Cell 1402 receives the input vector x1 and the output vector (hidden state) h0 from cell 1401. 、 Cell 1401 receives the cell state c0 from cell 1401 and generates the output vector h1 and the cell state vector c1. Cell 1403 receives the input vector x2, the output vector (hidden state) h1 from cell 1402, and the cell state c1 from cell 1402 and generates the output vector h2 and the cell state vector c2. Cell 1404 receives the input vector x3, the output vector (hidden state) h2 from cell 1403, and the cell state c2 from cell 1403 and generates the output vector h3. Additional cells are also available, and an LSTM with four cells is just an example.

[0069] Figure 15 shows an exemplary implementation of LSTM cell 1500 that can be used for cells 1401, 1402, 1403, and 1404 in Figure 14. LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from a preceding cell, and an output vector h(t-1) from a preceding cell, and generates the cell state vector c(t) and output vector h(t).

[0070] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors, and an adder device 1509 for adding two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or accessed for other purposes.

[0071] Figure 16 shows an LSTM cell 1600, which is an example implementation of LSTM cell 1500. For the reader's convenience, the same numbering method used in LSTM cell 1500 is used in LSTM cell 1600. Sigmoid function devices 1501, 1502, and 1503, and tanh device 1504 each contain multiple VMM arrays 1601 and activation function blocks 1602. Thus, VMM arrays are found to be particularly useful in LSTM cells used in certain neural network systems. Multiplier devices 1506, 1507, and 1508, and adder device 1509 are implemented in a digital or analog manner. Activation function block 1602 can be implemented in a digital or analog manner.

[0072] Figure 17 shows an alternative example of LSTM cell 1600 (and another example of an implementation of LSTM cell 1500). In Figure 17, sigmoid function devices 1501, 1502, and 1503, and tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-division multiplexed manner. The LSTM cell 1700 also includes a multiplier device 1703 for multiplying two vectors, an adder device 1708 for adding two vectors, a tanh device 1505 (including an activation function block 1702), a register 1707 for storing the value i(t) when i(t) is output from the sigmoid function block 1702, a register 1704 for storing the value f(t) × c(t-1) when its value is output from the multiplier device 1703 via the multiplexer 1710, a register 1705 for storing the value i(t) × u(t) when its value is output from the multiplier device 1703 via the multiplexer 1710, a register 1706 for storing the value o(t) × c~(t) when its value is output from the multiplier device 1703 via the multiplexer 1710, and a multiplexer 1709.

[0073] While an LSTM cell 1600 contains multiple sets of VMM arrays 1601 and their respective activation function blocks 1602, an LSTM cell 1700 contains only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in the example of an LSTM cell 1700. Compared to an LSTM cell 1600, an LSTM cell 1700 requires only one-quarter the space for the VMMs and activation function blocks, thus requiring less space than an LSTM cell 1600.

[0074] It can be further understood that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a considerable amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the examples described below reduce the circuitry required outside the VMM array itself.

[0075] <Gated recurrent unit> Analog VMM implementations can be used in GRU (gated recurrent unit) systems. A GRU is a gate mechanism within a recurrent neural network. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0076] Figure 18 shows an exemplary GRU1800. In this example, the GRU1800 includes cells 1801, 1802, 1803, and 1804. Cell 1801 receives input vector x0 and produces output vector h0. Cell 1802 receives input vector x1 and output vector h0 from cell 1801 and produces output vector h1. Cell 1803 receives input vector x2 and output vector (hidden state) h1 from cell 1802 and produces output vector h2. Cell 1804 receives input vector x3 and output vector (hidden state) h2 from cell 1803 and produces output vector h3. Additional cells are also available, and a GRU with four cells is just an example.

[0077] Figure 19 shows an exemplary implementation of a GRU cell 1900 that may be used in cells 1801, 1802, 1803, and 1804 of Figure 18. The GRU cell 1900 takes an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and produces an output vector h(t). The GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to the components from the output vector h(t-1) and the input vector x(t). The GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, multiple multiplier devices 1904, 1905, and 1906 for multiplying two vectors, an adder device 1907 for adding two vectors, and a complementary device 1908 for subtracting the input from 1 to produce an output.

[0078] Figure 20 shows GRU cell 2000, an example implementation of GRU cell 1900. For the reader's convenience, the same numbering method used in GRU cell 1900 is used in GRU cell 2000. As can be seen from Figure 20, the sigmoid function devices 1901 and 1902, and the tanh device 1903, each contain multiple VMM arrays 2001 and activation function blocks 2002. Thus, it can be seen that VMM arrays are used in particular in GRU cells used in specific neural network systems. The multiplier devices 1904, 1905, 1906, the adder device 1907, and the complementary device 1908 are implemented in a digital or analog manner. The activation function block 2002 can be implemented in a digital or analog manner.

[0079] Figure 21 shows an alternative example of the GRU cell 2000 (and another example of an implementation of the GRU cell 1900). In Figure 21, the GRU cell 2100 utilizes the VMM array 2101 and the activation function block 2102, which, when configured as a sigmoid function, applies a number between 0 and 1 to control the extent to which each component of the input vector contributes to the output vector. In Figure 21, the sigmoid function devices 1901 and 1902, and the tanh device 1903, share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-division multiplexed manner. The GRU cell 2100 also includes a multiplier device 2103 for multiplying two vectors, an adder device 2105 for adding two vectors, a complementary device 2109 for subtracting an input from 1 to produce an output, a multiplexer 2104, a register 2106 for holding the value h(t-1)×r(t) when that value is output from the multiplier device 2103 via the multiplexer 2104, a register 2107 for holding the value h(t-1)×z(t) when that value is output from the multiplier device 2103 via the multiplexer 2104, and a register 2108 for holding the value h^(t)×(1-z(t)) when that value is output from the multiplier device 2103 via the multiplexer 2104.

[0080] While GRU cell 2000 contains multiple sets of VMM array 2001 and activation function block 2002, GRU cell 2100 contains only one set of VMM array 2101 and activation function block 2102, which is used to represent multiple layers in the example of GRU cell 2100. GRU cell 2100 requires 1 / 3 the space for the VMM and activation function block compared to GRU cell 2000, so GRU cell 2100 requires less space than GRU cell 2000.

[0081] It can be further understood that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a considerable amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the examples described below reduce the circuitry required outside the VMM array itself.

[0082] The input to the VMM array may be analog level, binary level, pulse, time-modulated pulse, or digital bit (in which case a DAC is required to convert the digital bit to an appropriate input analog level), and the output may be analog level, binary level, timing pulse, pulse, or digital bit (in which case an output ADC is required to convert the output analog level to a digital bit).

[0083] Typically, for each memory cell in a VMM array, each weight W can be provided by a single memory cell, a differential cell, or two blended memory cells (the average of two cells). In the case of a differential cell, two memory cells are required to provide the weight W as a differential weight (W = W+-W-). In the case of two blended memory cells, two memory cells are required to provide the weight W as the average of two cells.

[0084] Figure 31 shows the VMM system 3100. In some examples, the weights W stored in the VMM array are stored as differential pairs, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). In the VMM system 3100, half of the multiple bit lines are designated as W+ lines, i.e., bit lines that will connect to memory cells that will store the positive weight W+, and the other half of the multiple bit lines are designated as W- lines, i.e., bit lines that will connect to memory cells that will give the negative weight W-. The W- lines are interspersed alternately between the W+ lines. Subtraction operations are performed by adders, such as adders 3101 and 3102, which receive current from the W+ and W- lines. The outputs of the W+ lines and the W- lines are combined to effectively give W = W+ - W- for each pair of (W+, W-) cells in all pairs of (W+, W-) lines. Up to this point, we have described W- lines that are alternately scattered between W+ lines, but in other examples, W+ and W- lines can be arbitrarily placed anywhere within the array.

[0085] Figure 32 shows another example. In the VMM system 3210, positive weights W+ are given in the first array 3211, and negative weights W- are given in the second array 3212, which is separate from the first array, and the resulting weights are appropriately combined by the adder circuit 3213.

[0086] Figure 33 shows the VMM system 3300. The weights W stored in the VMM array are stored as differential pairs, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). The VMM system 3300 comprises arrays 3301 and 3302. Half of the multiple bit lines in each of arrays 3301 and 3302 are designated as W+ lines, i.e., bit lines connected to memory cells that store the positive weights W+, and the other half of the multiple bit lines in each of arrays 3301 and 3302 are designated as W- lines, i.e., bit lines connected to memory cells that give the negative weights W-. The W- lines are interspersed alternately between the W+ lines. Subtraction operations are performed by adders, such as adders 3303, 3304, 3305 and 3306, which receive current from the W+ and W- lines. The outputs of the W+ line and the W- line from each array 3301 and 3302 are combined together to effectively give W=W+-W- for each pair of (W+, W-) cells in all pairs of (W+, W-) lines. In addition, the W values ​​from each array 3301 and 3302 can be further combined via adders 3307 and 3308, such that each W value is the result of subtracting the W value from array 3302 from the W value from array 3301, meaning that the final result from adders 3307 and 3308 is the difference of one of the two difference values.

[0087] Each non-volatile memory cell used in an analog neural memory system is erased and programmed to hold a very specific and precise amount of charge, i.e., the number of electrons, within its floating gate. For example, each floating gate should hold one of N distinct values, where N is the number of different weights that each cell can represent. Examples of N include 16, 32, 64, 128, and 256.

[0088] To increase the overall operating speed of artificial neural networks, it is desirable to reduce latency in programming operations. [Overview of the project]

[0089] Numerous examples are disclosed of programming multiple lines in an array of artificial neural networks as part of a single programming operation.

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[0132] [Brief explanation of the drawing]

[0133] [Figure 1] This is a diagram illustrating an artificial neural network. [Figure 2] This shows a prior art split-gate flash memory cell. [Figure 3] This shows another prior art split-gate flash memory cell. [Figure 4]This shows another prior art split-gate flash memory cell. [Figure 5] This shows another prior art split-gate flash memory cell. [Figure 6] This diagram illustrates various levels of exemplary artificial neural networks that utilize one or more non-volatile memory arrays. [Figure 7] This is a block diagram illustrating a VMM system. [Figure 8] This block diagram illustrates an exemplary artificial neural network utilizing one or more VMM systems. [Figure 9] Here is another example of a VMM system. [Figure 10] Here is another example of a VMM system. [Figure 11] Here is another example of a VMM system. [Figure 12] Here is another example of a VMM system. [Figure 13] Here is another example of a VMM system. [Figure 14] This demonstrates prior art long- and short-term memory systems. [Figure 15] This shows an example cell used in long- and short-term memory systems. [Figure 16] Figure 15 shows an exemplary embodiment of the cell. [Figure 17] Another exemplary embodiment of the cell shown in Figure 15 is presented. [Figure 18] This shows a prior art gated regression unit system. [Figure 19] An exemplary cell for use in a gated regressive unit system is shown. [Figure 20] Figure 19 shows an exemplary embodiment of the cell. [Figure 21] Another exemplary embodiment of the cell shown in Figure 19 is presented. [Figure 22] Here is another example of a VMM system. [Figure 23] Here is another example of a VMM system. [Figure 24]Here is another example of a VMM system. [Figure 25] Here is another example of a VMM system. [Figure 26] Here is another example of a VMM system. [Figure 27] Here is another example of a VMM system. [Figure 28] Here is another example of a VMM system. [Figure 29] Here is another example of a VMM system. [Figure 30] Here is another example of a VMM system. [Figure 31] Here is another example of a VMM system. [Figure 32] Here is another example of a VMM system. [Figure 33] Here is another example of a VMM system. [Figure 34] Here is another example of a VMM system. [Figure 35] An example of a programming waveform from prior art is shown. [Figure 36A] An example programming waveform for consecutive lines is shown. [Figure 36B] An example programming waveform for consecutive lines is shown. [Figure 36C] An example programming waveform for consecutive lines is shown. [Figure 36D] An example programming waveform for consecutive lines is shown. [Figure 37] A block diagram of a VMM system for programming consecutive rows is shown. [Figure 38] This shows the lamp control circuit. [Figure 39] This shows the lamp control circuit. [Figure 40] This shows the lamp control circuit. [Figure 41] This shows the lamp control circuit. [Figure 42] This shows a high-voltage level shifter and inverter. [Figure 43] A ramp-up control circuit and its exemplary waveform are shown. [Figure 44] A lamp-down control circuit and its exemplary waveforms are shown.

Embodiments for Carrying Out the Invention

[0134] <Structure of the VMM System> FIG. 34 shows a block diagram of a VMM system 3400. The VMM system 3400 includes a VMM array 3401, a row decoder 3402, a high-voltage row decoder 3403, a column decoder 3404, a bit-line driver 3405, an input circuit 3406, an output circuit 3407, control logic 3408, and a bias generator 3409. The VMM system 3400 further includes a high-voltage generation block 3410 including a charge pump 3411, a charge-pump regulator 3412, and a high-voltage level generator 3413. The VMM system 3400 further includes a (program / erase, or weight tuning) algorithm controller 3414, an analog circuit 3415, a control engine 3416 (which may include special functions such as, but not limited to, arithmetic functions, activation functions, embedded microcontroller logic, etc.), test control logic 3417, and a static random access memory (SRAM) block 3418 for storing intermediate data or data for programming, such as input data for the entire row or multiple rows, input data for the input circuit (e.g., activation data) or output data for the output circuit (neuron output data).

[0135] The input circuit 3406 may include circuits such as a DAC (digital to analog converter), DPC (digital to pulses converter, digital to time modulated pulse converter), AAC (analog to analog converter, such as a current-to-voltage converter or logarithmic converter), PAC (pulse to analog level converter), or any other type of converter. The input circuit 3406 may implement one or more of the following: normalization, linear or nonlinear up / downscaling functions, or arithmetic functions. The input circuit 3406 may implement a temperature compensation function for the input level. The input circuit 3406 may implement an activation function such as ReLU or sigmoid.

[0136] The output circuit 3407 may include circuits such as an ADC (analog to digital converter, an analog-to-digital converter for converting the analog output of a neuron into digital bits), an AAC (analog to analog converter, such as a current-to-voltage converter or logarithmic converter), an APC (analog to pulse converter, analog to time-modulated pulse converter), or any other type of converter. The output circuit 3407 may implement an activation function such as a rectified linear activation function (ReLU) or a sigmoid. The output circuit 3407 may implement one or more of the following functions of the neuron output: statistical normalization, regularization, up / downscaling / gain function, statistical rounding, or arithmetic function (e.g., addition, subtraction, division, multiplication, shift, logarithm). The output circuit 3407 may implement a temperature compensation function for the neuron output or array output (such as a bit line output) in order to keep the power consumption of the array nearly constant, or to improve the accuracy of the array (neuron) output by keeping the IV gradient nearly the same.

[0137] Figure 35 shows the timing waveforms of the prior art programming operation 3500. Shown here are exemplary signals of HVSUP (high voltage power supply generated by the high voltage generation block 3410 in Figure 34), which includes a charge pump 3411 and is specifically generated by a high voltage level generator 3413 and supplied to the control gate line, source line, and / or bit line of the selected cell during the programming operation. In particular, Figure 35 shows CG (voltage applied to the control gate line coupled to the selected cell during the programming operation), SL (voltage applied to the source line coupled to the selected cell during the programming operation), EG (voltage applied to the erase gate line coupled to the selected cell during the programming operation), and IPROG (voltage generated by the bias generator 3409 or analog circuit 3415 and applied to the bit line coupled to the selected cell during the programming operation). These voltages are selected, for example, according to Tables 1 to 8 described above for the programming operation, but are not limited to these. As can be understood, the HVSUP has a significant ramp-up time t1 and ramp-down time t2 due to its peak high voltage and the actions involved in generating that voltage, such as capacitance. The ramp-up time is affected, for example, by the charge pumping action of the charge pump 3411, which takes time. The ramp-down time is affected by the time required to discharge the high voltage of all devices coupled to the high voltage, including, for example, a large capacitive load that slows down the ramp-down time. The ramp-up time t3 of the CG is short, and the ramp-down time t4 of the CG is short.

[0138] Typical values ​​for t1, t2, t3, t4, and t5 (described below) are 20–60 μs, 5–20 μs, 0.1–1 μs, 0.1–1 μs, and 0.1 μs, respectively. In contrast, once the voltage is applied, the time required to program a single cell is only 1 μs. As a result, in the prior art, it is common to program an entire row of multiple cells in a single high-voltage cycle of the HVSUP so that only a single ramp-up period and a single ramp-down period of the HVSUP are called for programming the entire row. For example, a row may contain 2048 cells, and each word may contain 128 bits, meaning that each row contains 16 words. Therefore, in the example in Figure 35, Word0, ..., Word15 (a total of 16 words) are programmed during a single cycle of the HVSUP such that a single ramp-up at t1 and a ramp-down at t2 occur for programming each set of 16 words. Further delays in t5 occur while programming cells in different rows.

[0139] Figure 36A shows the timing waveforms for programming operation 3600. Here again, the waveforms are shown for HVSUP, CG, SL, EG, and IPROG. Here, K consecutive rows of cells are programmed for each cycle of HVSUP, where K > 1. For example, K = 2, K = 3, or K = 4.

[0140] Firstly, the ramp-up period t1 results from the charge pumping action of the charge pump 3411 and from charging up all capacitive loads of all devices coupled to the high voltage generation block 3410. After the high voltage (HVSUP) stabilizes, the HVSUP is then switched to one or more lines coupled to the array terminals (CG, WL, SL, BL, and / or EG). For example, according to Tables 1 to 8, the HVSUP may be applied to the CG line, SL line, or EG line, and other voltages (lower than the HVSUP) may be applied to the remaining lines. The high voltages applied to CG, SL, EG, and BL can be optionally four different voltages. The low voltages applied to CG, SL, EG, and BL can be optionally four different voltages, the same voltage (e.g., ground), or any variation between them. Secondly, the program current (IPROG) is enabled for tPROG (e.g., 0.5 to 1 μs) for each word of 16 words in a row, as an example. Instead of the HVSUP ramping down after each row of programming, the HVSUP remains high for the next row of programming, and instead, the circuit switches CG, SL, and EG off and then back on. Switching CG, SL, and EG off and then back on requires a period equal to t4 + t3 + t5, where t4 is the required ramp-down time for the slowest of CG, SL, and EG, t3 is the ramp-up period for the slowest of CG, SL, and EG, and t5 is a gap to ensure that the ramp-up circuit does not mistakenly start ramping up CG, SL, and EG before it has completed its ramp-down. In particular, t3 is much smaller than t1 and t4 is much smaller than t2. Thirdly, the second row of the cell is programmed without the HVSUP ramping down. Fourthly, a ramp-down period of t2 occurs. For example, typical figures are: t1~10-60μs, t3~0.1-1μs, t4~0.1-1μs, t5 < 0.1 μs, t2 ≈ 10 μs Therefore, using this same sequence, row K is programmed for every constant high period of HVSUP, where K > 1. In the illustrated example, the ramp-up and ramp-down slopes of CG, SL, and EG are steeper than the ramp-up and ramp-down slopes of HVSUP, respectively.

[0141] Figure 36B shows the timing waveform for programming operation 3620, which is similar to programming operation 3600 in Figure 36A, except that t5 is absent. There is no delay between the end of the ramp-down period at t4 and the ramp-up period at t3, meaning the CG signal is switched from the first CG line of the first row to the second CG line of the second row without delay. This reduces the programming time compared to programming operation 3600.

[0142] Figure 36C shows the timing waveform of programming operation 3640, which is similar to programming operation 3600 in Figure 36A, except that t4 and t3 overlap. This means that during the ramp-down period at t4, the CG signal is switched from the first CG line of the first row to the second CG line of the second row. This reduces the programming time compared to programming operation 3620, but increases the risk that the CG ramp-down will not progress to a point considered "low" before ramping up again.

[0143] Figure 36D shows the timing waveform of programming operation 3660, which is similar to programming operation 3600 in Figure 36A, except that t3 starts before t4 ends, meaning that the CG signal applied to the second CG line of the second row ramps up before or simultaneously with the CG signal applied to the first CG line of the first row ramps down. This reduces programming time compared to programming operation 3640, at the expense of not having the option to use changes in the state of CG to trigger any action.

[0144] Therefore, programming operations 3600, 3620, 3640, and 3660 are faster than programming operation 3500 for programming two or more consecutive lines. This can be of significant importance as it represents an improvement of approximately 3 to 10 times in programming time.

[0145] Figures 37 to 41 show the circuits for performing programming operations 3600, 3620, 3640, and 3660.

[0146] Figure 37 shows a VMM system 3700, similar to Figure 34, which includes a VMM array 3401, a row decoder 3402, a high-voltage row decoder 3403, and a high-voltage generation block 3410. The VMM system 3700 further includes a high-voltage pre-decoder 3701 that performs the CG, SL, and EG sequences and switch-offs described with respect to Figure 36 and receives HVSUP as a voltage input.

[0147] The ramp-up and ramp-down functions of the HVSUP, as shown in Figures 36A to 36D, can be implemented in the HV generation block 3410, the HV pre-decoder 3701, or the row decoder 3402. Figures 38 to 41 show circuits that may be used to implement the ramp-up and ramp-down functions.

[0148] Figure 38 shows a ramp control circuit 3800-i, a bias circuit 3810, a bias circuit 3820, and a decoder 3830, where i ranges from 0 to N, and there are N+1 rows of cells in array 3401. The ramp control circuit 3800-i includes a PMOS transistor 3801 and an NMOS transistor 3802, which can ramp up the signal Vout (e.g., CG, EG, SL array terminals, pre-decoded high-voltage signal) from ground towards HVSUP or ramp down to ground. The first terminal of the PMOS transistor 3801 receives HVSUP, the gate of the PMOS transistor 3801 receives a first control signal PBIAS[N:0] (optionally a current control signal), and the second terminal of the PMOS transistor 3801 is the Vout node. The first terminal of the NMOS transistor 3802 is connected to the Vout node, the gate of the NMOS transistor 3802 receives a second control signal NBIAS[N:0] (which is optionally a current control signal), and the second terminal of the NMOS transistor 3802 is connected to ground.

[0149] Instantiations of the ramp control circuit 3800-i are coupled to the respective control gate lines, source lines, and erase gate lines to perform the switch-in and switch-off operations of the programming operations 3600, 3620, 3640, and 3660. In the illustrated example, the suffix [N:0] indicates that there are N+1 different instantiations. The instantiations of the ramp control circuit 3800 are coupled to each other in a decoding current mirror configuration.

[0150] The decoder 3830 receives the row address and generates the complements of the enable signal EN[N:0] and the enable signal ENB[N:0] such that N+1 EN signals and N+1 ENB signals are generated one for each instantiation of the lamp control circuit 3800.

[0151] The bias circuit 3810 includes a primary circuit 3815 and N+1 instances of subcircuit 3816-i, where i ranges from 0 to N. The primary circuit 3815 includes a current source 3811 and an NMOS transistor 3812, with the current i mirrored to generate NBIAS[N:0]. N Each subcircuit 3816-i includes a switch 3813 controlled by EN[N:0] from decoder 3830 and a switch 3814[N:0] controlled by ENB from decoder 3830.

[0152] The bias circuit 3820 includes a primary circuit 3825 and N+1 instances of subcircuit 3826-i, where i ranges from 0 to N. The primary circuit 3825 includes a current source 3821 and a PMOS transistor 3822, with the current i mirrored to generate PBIAS[N:0]. P Each subcircuit 3826-i includes a switch 3823 controlled by EN[N:0] from decoder 3830 and a switch 3824[N:0] controlled by ENB from decoder 3830.

[0153] In the ramp control circuit 3800-i, a high voltage in NBIAS[N:0] causes a ramp down, and a low voltage in PBIAS[N:0] causes a ramp up. When PBIAS is asserted to switch PMOS transistor 3801 on and NBIAS is deasserted, Vout is pulled up to HVSUP, thereby performing the switch-on function. When NBIAS is asserted to switch NMOS transistor 3802 on and PBIAS is deasserted, Vout is pulled down to ground, thereby performing the switch-off function. The ramp control circuit 3800 here is shown with respect to Vout, which may be used to provide the CG, SL, or EG voltages in Figures 36A to 36D. Due to the use of current mirrors in bias circuits 3810 and 3820, all N+1 instantiations receive the same current in PBIAS[N:0] and the same current in NBIAS[N:0] when the corresponding row is enabled by the row address provided to decoder 3830.

[0154] Figure 39 shows the ramp control circuit 3900-i, where i ranges from 0 to N, and there are N+1 rows of cells in array 3401. The ramp control circuit 3900-i includes PMOS transistors 3901 and 3902 and NMOS transistors 3903 and 3904. Instantiations of the ramp control circuit 3900-i are coupled to each control gate line, source line, and erase gate line to perform the switch-in and switch-off operations of the programming operation 3600. In the illustrated example, the suffix [N:0] indicates that there are N+1 different instantiations. High voltages in NBIAS[N:0] and NCASCODE cause ramp-down, and low voltages in PBIAS[N:0] and PCASCODE cause ramp-up.

[0155] The first terminal of PMOS transistor 3901 receives HVSUP, and the gate of PMOS transistor 3901 receives the first control signal PBIAS[N:0] (which is optionally a current control signal). The first terminal of PMOS transistor 3902 is coupled to the second terminal of PMOS transistor 3901, and the gate of PMOS transistor 3902 receives the second control signal PCASCODE, and the second terminal of PMOS transistor 3902 is coupled to the Vout node (e.g., CG, EG, SL array terminals, pre-decoded high-voltage signals). The first terminal of NMOS transistor 3903 is coupled to the Vout node, and the gate of NMOS transistor 3903 receives the third control signal NCASCODE. The first terminal of NMOS transistor 3904 is coupled to the second terminal of NMOS transistor 3903, and the gate of NMOS transistor 3904 receives the fourth control signal NBIAS[N:0] (which is optionally a current control signal), and the second terminal of NMOS transistor 3904 is coupled to ground.

[0156] PMOS transistor 3902 and NMOS transistor 3903 perform a cascoding function to isolate PMOS transistor 3901 and NMOS transistor 3904 from Vout. When PCASCODE and PBIAS of row N are asserted, PMOS transistors 3901 and 3902 are turned on, and when NCASCODE and NBIAS of row N are deasserted, Vout is pulled up to HVSUP, thereby performing a switch-on function. When NCASCODE and NBIAS of row N are asserted, NMOS transistors 3903 and 3904 are turned on, and when PCASCODE and PBIAS of row N are deasserted, Vout is pulled down to ground, thereby performing a switch-off function. The ramp control circuit 3900 here is shown for Vout, which may be used to provide the CG, SL, or EG voltages in Figures 36A to 36D. Optionally, the PBIAS[N:0] signal for the N+1 instances of the lamp control circuit 3900-I may be provided by the bias circuit 3820 in Figure 38 so that all N+1 instances receive the same current of PBIAS[N:0], and the NBIAS[N:0] signal for the N+1 instances of the lamp control circuit may be provided by the bias circuit 3810 in Figure 38 so that all N+1 instances receive the same current of NBIAS[N:0]. Optionally, the decoder 3830 in Figure 38 may also be used in these configurations to provide EN[N:0] and EN[N:B].

[0157] Figure 40 shows a ramp control circuit 4000-i, where i ranges from 0 to N. The ramp control circuit 4000-i includes PMOS transistors 4001 and 4002, an NMOS transistor 4003, and current bias sources 4004 and 4005. The current bias source 4005 includes a first terminal coupled to a high-voltage generation block. The PMOS transistor 4001 includes a first terminal coupled to a second terminal of the current bias source 4005, a second terminal, and a gate that receives a first control signal PBIAS[N:0] (optionally being a current control signal). The PMOS transistor 4002 includes a first terminal coupled to a second terminal of the PMOS transistor 4001, a second terminal coupled to a Vout node (e.g., CG, EG, SL array terminals, pre-decoded high-voltage signals), and a gate that receives a second control signal GP[N:0]. The NMOS transistor 4003 includes a first terminal connected to the Vout node, a second terminal, and a gate that receives a third control signal NBIAS[N:0] (optionally being a current control signal). A current bias source 4004 is connected between the second terminal of the NMOS transistor 4004 and ground.

[0158] Instantiations of the ramp control circuit 4000 are coupled to the respective control gate line, source line, and erase gate line to perform the switch-in and switch-off operations of the programming operations 3600, 3620, 3640, and 3660. In the illustrated example, the suffix [N:0] indicates that there are N+1 different instantiations. A high voltage in NBIAS[N:0] causes ramp-down, and low voltages in PBIAS[N:0] and GP[N:0] cause ramp-up. When PBIAS and GP in row N are asserted, PMOS transistors 4001 and 4002 are turned on, and when NBIAS in row N is deasserted, Vout is pulled up to HVSUP, where the ramp gradient may be controlled by the amount of current provided by the current bias source 4005, thereby performing the switch-on function. When NBIAS is asserted, the NMOS transistor 4003 is turned on, and when PBIAS and GP of row N are deasserted, Vout is pulled down to ground, where the slope of the ramp down can be controlled by the amount of current provided by the current bias source 4004, thereby performing a switch-off function. The ramp control circuit 4000 here is shown for Vout, which can be used for the CG, SL, or EG voltages in Figures 36A to 36D.

[0159] Optionally, the PBIAS[N:0] signal for the N+1 instances of the lamp control circuit 3900-I may be provided by the bias circuit 3820 in Figure 38 so that all N+1 instances receive the same current of PBIAS[N:0], and the NBIAS[N:0] signal for the N+1 instances of the lamp control circuit may be provided by the bias circuit 3810 in Figure 38 so that all N+1 instances receive the same current of NBIAS[N:0]. Optionally, the decoder 3830 in Figure 38 may also be used in these configurations to provide EN[N:0] and EN[N:B].

[0160] Figure 41 shows the ramp control circuit 4100-i, where i ranges from 0 to N. The ramp control circuit 4100-i includes PMOS transistors 4101, 4102, and 4103, NMOS transistors 4104 and 4105, and current bias sources 4106 and 4107. Instantiation of the ramp control circuit 4100-i is coupled to each control gate line, source line, and erase gate line to perform the switch-in and switch-off operations of the programming operation 3600.

[0161] The current bias source 4107 includes a first terminal connected to HVSUP. The PMOS transistor 4101 includes a first terminal connected to the second terminal of the current bias source 4107, a second terminal, and a gate that receives a first control signal GPIAS[N:0] (optionally being a current control signal). The PMOS transistor 4102 includes a first terminal connected to the second terminal of the PMOS transistor 4101, a second terminal, and a gate that receives a second control signal GP[N:0]. The PMOS transistor 4103 includes a first terminal connected to the second terminal of the PMOS transistor 4103, a second terminal connected to the Vout node, and a gate that receives a third control signal PCASCODE. The NMOS transistor 4104 includes a first terminal connected to the Vout node, a second terminal, and a gate that receives a fourth control signal NCASCODE. The NMOS transistor 4105 includes a first terminal coupled to the second terminal of the NMOS transistor 4104, a second terminal, and a gate that receives a fifth control signal NBIAS[N:0] (optionally being a current control signal). The current bias source 4106 is coupled between the second terminal of the NMOS transistor 4105 and ground.

[0162] In the illustrated example, the suffix [N:0] indicates that there are N+1 different instantiations. A high voltage in NBIAS[N:0] causes a ramp-down, while low voltages in PBIAS[N:0] and GP[N:0] cause a ramp-up. PMOS transistors 4103 and 4104 perform the cacoding function. GP[N:0] performs another pre-decoded signal function. When GPIAS, GP, and PCASCODE of row N are asserted, PMOS transistors 4101, 4102, and 4103 are turned on, and when NBIAS and NCASCODE of row N are deasserted, Vout is pulled up to CGSUP, where the ramp gradient may be controlled by the amount of current provided by the current bias source 4107, thereby performing the switch-on function. When NBIAS and NCASCODE are asserted, NMOS transistors 4104 and 4105 are turned on, and when PBIAS, GP, and PCASCODE of row N are deasserted, Vout is pulled down to ground accelerated by current bias source 4107, where the slope of the ramp down can be controlled by the amount of current provided by current bias source 4106, thereby performing a switch-off function. The ramp control circuit 4100 here is shown for Vout which can be used for CG, SL, or EG in Figures 36A to 36D.

[0163] Optionally, the PBIAS[N:0] signal for the N+1 instances of the lamp control circuit 3900-I may be provided by the bias circuit 3820 in Figure 38 so that all N+1 instances receive the same current of PBIAS[N:0], and the NBIAS[N:0] signal for the N+1 instances of the lamp control circuit may be provided by the bias circuit 3810 in Figure 38 so that all N+1 instances receive the same current of NBIAS[N:0]. Optionally, the decoder 3830 in Figure 38 may also be used in these configurations to provide EN[N:0] and EN[N:B].

[0164] Figure 42 shows a high-voltage level shifter and inverter 4200, which includes a current bias source 4201, PMOS transistors 4202 and 4204, NMOS transistors 4203, 4205, 4207, and 4208, and a current bias source 4206. Inputs IN and INB (logic voltage levels, where INB is the reciprocal of IN) are received, and the output (high voltage level) OUT is generated at the drain of NMOS transistor 4208. A low value of IN results in a high value of OUT, and a high value of IN results in a low value of OUT, where the high values ​​of IN and OUT are different voltage levels.

[0165] In some details, when IN is high, NMOS transistor 4208 is on, pulling OUT to ground, PMOS transistor 4204 is off, and NMOS transistor 4205 is on, which pulls OUT low by NMOS transistor 4205 (resulting in PMOS transistor 4202 being turned on, NMOS transistor 4203 being turned off, and the high-voltage level shifter being latched).

[0166] When IN is low, INB is high, PMOS transistor 4204 is on and NMOS transistor 4205 is off, and OUT is pulled high up to HVSUP, which in turn turns off PMOS transistor 4202 and NMOS transistor 4203 on. Current bias sources 4201 and 4206 control the ramping slope of the output voltage, respectively.

[0167] Figure 43 shows a ramp-up control circuit 4300, which includes NMOS transistors 4301, 4302, and 4305, a capacitor 4303 with capacitance Cap, and a current bias 4304 that pulls in current Ibias. The ramp-up control circuit 4300 provides ramp-up control to VHV (e.g., HVSUP, CG, EG, SL array terminals, pre-decoded high-voltage signals). The ramp-up control circuit 4300 can be applied to an HV generation block 3410, an HV pre-decoder 3701, or a row decoder 3402. VHV is a ramp-controlled high-voltage node. NMOS transistor 4301 is always on based on VDD applied to its gate. VNCTRLU is a control bias signal that turns on transistor 4302, which sinks current from HVSUP to control the ramp rate of VHV. NMOS transistor 4305 pulls VNCTRLU down to ground, so ENB is high when VNCTRLU is desired to be low. When VNCTRLU is low, NMOS transistor 4302 is turned off. ENB is turned low when it is desired that VHV ramp up to the termination voltage. When ENB is low, NMOS transistor 4305 is turned off. Charge begins to accumulate on the lower plate of capacitor 4303 to generate a voltage across VNCTRLU to control the ramp rate of VHV. The ramp-up rate is equal to Cap × VHV / Ibias. Figure 4310 shows the waveform of ramp-up control circuit 4300. The voltage at node VHV is initially maintained at a low voltage level before ramping (circuit not shown).

[0168] Figure 44 shows a ramp-down control circuit 4400, which includes NMOS transistors 4403, 4404, 4405, 4406, and 4407, a current bias source 4402 that draws in current Ibias, and a capacitor 4408 with capacitance Cap. The ramp-down control circuit 4400 is switchably coupled to the CG, SL, or EG line of a selected row during programming operation (where it switches from a first selected row to a second selected row during operation). The ramp-down control circuit 4400 can be implemented in an HV generation block 3410, an HV predecoder 3701, or a row decoder 3402. VHV is a controlled ramp-down high-voltage node (e.g., HVSUP, CG, EG, SL array terminals, predecoded high-voltage signals). NMOS transistors 4403 and 4407 are always on based on VDD applied to their respective gates. When EN is high, ENB is low, NMOS transistor 4404 is turned on, and NMOS transistor 4405 is turned off. In this state, VCNTRLD becomes the bias voltage to control the ramp-down rate of VHV. When EN is low, ENB is high, transistor 4405 is turned on, and VCNTRLD is pulled to ground. The ramp-down rate is equal to Cap × VHV / Ibias. Figure 4410 shows the waveform of the ramp-down control circuit 4400.

[0169] It should be noted that, as used herein, the terms “over” and “on” both encompass “directly” (without intermediate material, element, or gap between them) and “indirectly to” (with intermediate material, element, or gap between them). Similarly, the term “adjacent” includes “directly adjacent” (without intermediate material, element, or gap between them) and “indirectly adjacent” (with intermediate material, element, or gap between them); “attached” includes “directly attached” (without intermediate material, element, or gap between them) and “indirectly attached to” (with intermediate material, element, or gap between them); and “electrically coupled” includes “directly electrically coupled” (without intermediate material or element between them electrically connecting the elements together) and “indirectly electrically coupled to” (with intermediate material or element between them electrically connecting the elements together). For example, forming an element "on top of a substrate" may include forming the element directly on the substrate without any intermediate materials / elements between them, and forming the element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. It is a method, The steps include ramping up the output of the high-voltage generator to a first voltage level, A step of programming multiple words of K rows of memory cells in an array of memory cells using the output of the high-voltage generator, while maintaining the output of the high-voltage generator at the first voltage level, wherein K > 1. After the programming step, the step of ramping down the output of the high-voltage generator to a second voltage level, For one or more of the aforementioned K rows, the steps include ramping up the control gate line voltage to a third voltage level before programming the row, and ramping down the control gate line voltage to a fourth voltage level after programming the row. For one or more of the aforementioned K rows, the steps include ramping up the control gate line voltage to a third voltage level before programming the row, and ramping down the control gate line voltage to a fifth voltage level between the fourth voltage level and the third voltage level after programming the row. Methods that include...

2. The method according to claim 1, wherein the fourth voltage level is equal to the second voltage level.

3. The method according to claim 1, further comprising the steps of ramping up the source line voltage to a fifth voltage level before programming one or more of the K rows, and ramping down the source line voltage to a sixth voltage level after programming the row.

4. The method according to claim 3, further comprising the step of ramping up the erase control gate line voltage to a seventh voltage level before programming one or more of the K rows, and ramping down the erase control gate line voltage to an eighth voltage level after programming the row.

5. The method according to claim 1, wherein the fourth voltage level is equal to the second voltage level.

6. The method according to claim 1, wherein the ramp-up of the control gate line voltage is controlled by ramp rate.

7. The method according to claim 6, wherein the ramp rate of the ramp-up of the control gate line voltage is faster than the ramp rate of the output of the high-voltage generator.

8. A system, An array of memory cells arranged in rows and columns, (i) a first ramp-up voltage before a programming operation of multiple words in the memory cells of row K in the array, wherein K > 1; (ii) a high voltage during the programming operation of the memory cells of row K in the array; and (iii) a first ramp-down voltage after the programming operation of the memory cells of row K in the array; (i) generating a second ramp-up voltage steeper than the first ramp-up voltage before programming one of the K rows of memory cells; (ii) applying the high voltage to the control gate line of the row of the memory cell array to program one of the K rows of memory cells; and (iii) generating a second ramp-down voltage steeper than the first ramp-down voltage after programming one of the K rows of memory cells. The aforementioned lamp control circuit is A first current bias source including a first terminal coupled to the high voltage generation block, A first PMOS transistor including a first terminal coupled to the second terminal of the first current source, a second terminal, and a gate that receives a first control signal, A second PMOS transistor including a first terminal coupled to the second terminal of the first PMOS transistor, a second terminal coupled to the control gate line, and a gate that receives a second control signal, An NMOS transistor including a first terminal connected to the control gate line, a second terminal, and a gate that receives a third control signal, A system comprising a second current bias source coupled between the second terminal of the NMOS transistor and ground.

9. A system, An array of memory cells arranged in rows and columns, (i) a first ramp-up voltage before a programming operation of multiple words in the memory cells of row K in the array, wherein K > 1; (ii) a high voltage during the programming operation of the memory cells of row K in the array; and (iii) a first ramp-down voltage after the programming operation of the memory cells of row K in the array; (i) generating a second ramp-up voltage steeper than the first ramp-up voltage before programming one of the K rows of memory cells; (ii) applying the high voltage to the control gate line of the row of the memory cell array to program one of the K rows of memory cells; and (iii) generating a second ramp-down voltage steeper than the first ramp-down voltage after programming one of the K rows of memory cells. The aforementioned lamp control circuit is A first current bias source including a first terminal coupled to the high voltage generation block, A first PMOS transistor including a first terminal coupled to the second terminal of the first current source, a second terminal, and a gate that receives a first control signal, A second PMOS transistor including a first terminal coupled to the second terminal of the first PMOS transistor, a second terminal, and a gate for receiving a second control signal, A third PMOS transistor including a first terminal coupled to the second terminal of the second PMOS transistor, a second terminal coupled to the control gate line, and a gate that receives a third control signal, A first NMOS transistor including a first terminal connected to the control gate line, a second terminal, and a gate for receiving a fourth control signal, A second NMOS transistor including a first terminal coupled to the second terminal of the first NMOS transistor, a second terminal, and a gate for receiving a fifth control signal, A system comprising a second current bias source coupled between the second terminal of the second NMOS transistor and ground.

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