Output circuit for artificial neural network array

Abstract

Numerous examples of output circuits and related methods in artificial neural networks are disclosed. In one example, a system includes an array of non-volatile memory cells arranged in rows and columns, an output block for converting current from a column of the array to a first digital output during a first time period and to a second digital output during a second time period, a first output register for storing the first digital output during the first time period and outputting the stored first digital output during the second time period, and a second output register for storing the second digital output during the second time period and outputting the stored second digital output during a third time period.

Description

[Technical Field]

[0001] (Claiming priority) This application claims priority to U.S. Patent Application No. 18 / 077,993, entitled "Output Circuit for Artificial Neural Network Array," filed on 8 December 2022, and to U.S. Provisional Patent Application No. 63 / 409140, entitled "Input Circuit and Output Circuit for Concurrent and Pipelined Operations in Artificial Neural Network Array," filed on 22 September 2022.

[0002] (Field of invention) Numerous examples of output circuits and related methods for implementing parallel and pipelining operations in artificial neural networks are disclosed. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (such as the central nervous system of animals, particularly the brain), can rely on a large number of inputs, and are generally used to estimate or approximate unknown functions. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange messages with one another.

[0004] Figure 1 illustrates an artificial neural network, where circles represent inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to inputs and learn. Typically, a neural network contains multiple input layers. Typically, there are one or more hidden layers of neurons and an output layer of neurons that provides the output of the neural network. Neurons at each level make decisions individually or collectively based on the data they receive from synapses.

[0005] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of suitable hardware technology. In fact, practical neural networks rely on a very large number of synapses, which enables high connectivity between neurons and thus very high levels of parallel processing. In principle, such complexity can be achieved with digital supercomputers or dedicated graphics processing unit clusters. However, in addition to their high cost, these approaches also suffer from poor energy efficiency compared to biological networks, which consume far less energy because they primarily perform low-precision analog calculations. While CMOS analog circuits have been used for artificial neural networks, the synapses in most CMOS implementations are too large considering the large number of neurons and synapses.

[0006] The applicant previously disclosed, in U.S. Patent Application Publication No. 2017 / 0337466(A1), incorporated by reference, an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses. The non-volatile memory arrays operate as analog neural memory and comprise non-volatile memory cells arranged in rows and columns. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and therefrom produce a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses comprises a plurality of memory cells, each of which comprises spaced source and drain regions formed in a semiconductor substrate, with a channel region extending between them, a floating gate insulated and disposed above a first portion of the channel region, and a non-floating gate insulated and disposed above a second portion of the channel region. Each of the plurality of memory cells stores weight values ​​corresponding to the number of electrons in the floating gate. The plurality of memory cells generate a first plurality of outputs by multiplying the first plurality of inputs by the stored weight values. <Non-volatile skin cell>

[0007] Non-volatile memory is well known. For example, U.S. Patent No. 5,029,130 ​​("'130"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, a type of flash memory cell. Such a memory cell 210 is shown in Figure 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed insulated above a first portion of the channel region 18 (and controlling the conductivity of the first portion of the channel region 18) and extends above a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed insulated above a second portion of the channel region 18 (and controlling the conductivity of the second portion of the channel region 18) and a second portion extending upward above the floating gate 20. The floating gate 20 and word line terminal 22 are insulated from the substrate 12 by the gate oxide. The bit line 24 is coupled to the drain region 16.

[0008] By applying a positive high voltage to the word line terminal 22, the memory cell 210 is erased (electrons are removed from the floating gate), causing the electrons in the floating gate 20 to pass through the insulator between them to the word line terminal 22 via a Fowler-Nordheim (FN) tunnel.

[0009] The memory cell 210 is programmed (electrons are applied to the floating gate) by performing source side injection (SSI) of hot electrons by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. The electron flow is from the drain region 16 towards the source region 14. The electrons are accelerated and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. A portion of the heated electrons is injected through the gate oxide into the floating gate 20 due to the electrostatic attraction from the floating gate 20.

[0010] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and the word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., electrons are erased), the portion of the channel region 18 below the floating gate 20 is also turned on, and current flows through the channel region 18, which is detected as the erased state, i.e., the "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is almost or completely turned off, and current does not flow (or hardly flows) through the channel region 18, which is detected as the programmed state, i.e., the "0" state.

[0011] Table 1 shows the typical voltage / current ranges that can be applied to the terminals of the memory cell 210 to perform read, erase, and program operations. Table 1: Operation of the flash memory cell 210 in FIG. 2

Table 1

[0012] Other split-gate memory cell configurations are also known, which are other types of flash memory cells. For example, FIG. 3 shows a four-gate memory cell 310 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent No. 6,747,310, which is hereby incorporated by reference for all purposes. Here, all gates are non-floating gates except for the floating gate 20, that is, they are electrically connected or connectable to a voltage source. Programming is performed by injecting hot electrons themselves from the channel region 18 into the floating gate 20. Erasure is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0013] Table 2 shows typical voltage / current ranges that can be applied to the terminals of the memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the Flash Memory Cell 310 in FIG. 3 [Table 2]

[0014] FIG. 4 shows a three-gate memory cell 410, which is another type of flash memory cell. The memory cell 410 is identical to the memory cell 310 in FIG. 3 except that the memory cell 410 does not have a separate control gate. (Erasure occurs through the use of an erase gate) The erase operation and the read operation are the same as those in FIG. 3 except that no control gate bias is applied. Since the programming operation is also performed without a control gate bias, as a result, a higher voltage is applied to the source line during the programming operation to compensate for the lack of control gate bias.

[0015] Table 3 shows typical voltage / current ranges that may be applied to the terminals of the memory cell 410 to perform read, erase, and program operations. Table 3: Operation of flash memory cell 410 in Figure 4 [Table 3]

[0016] Figure 5 shows a different type of flash memory cell, a stacked gate memory cell 510. Memory cell 510 is similar to memory cell 210 in Figure 2, except that the floating gate 20 extends above the entire channel region 18, and the control gate 22 (where coupled to the word line) extends above the floating gate 20, separated by an insulating layer (not shown). Erase is performed by FN tunneling of electrons from the FG to the substrate, programming is performed by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, and read operations are performed by electrons flowing from the source region 14 to the drain region 16, similar to the read operation of memory cell 210, which has a higher control gate voltage.

[0017] Table 4 shows typical voltage ranges that can be applied to the terminals of the memory cell 510 and the circuit board 12 for performing read, erase, and program operations. Table 4: Operation of flash memory cell 510 in Figure 5 [Table 4]

[0018] The methods and means described herein may be applied to other non-volatile memory technologies, including but not limited to FINFET split-gate flash or stack-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive random-access memory), PCM (phase change memory), MRAM (magnetic random-access memory), FeRAM (ferroelectric random-access memory), CT (charge trap) memory, CN (carbon-tube) memory, OTP (one-time programmable, bi-level or multi-level), and CeRAM (correlated electron random-access memory).

[0019] Two modifications are made to utilize a memory array containing one of the non-volatile memory cell types in the artificial neural network described above. First, lines are configured to allow each memory cell to be programmed, erased, and read individually without adversely affecting the memory state of other memory cells in the array, as will be further described below. Second, sequential (analog) programming of the memory cells is provided.

[0020] Specifically, the memory state of each memory cell in the array (i.e., the charge on the floating gate) can be changed independently and continuously, with minimal disturbance to other memory cells, from a completely erased state to a fully programmed state, and vice versa. This means that cell memory is essentially analog, or can store at least one of a number of discontinuous values ​​(such as 16 or 64 different values), making every memory cell in the memory array highly precise and individually tunable, and making the memory array ideal for memory and fine-tuning of synaptic weights in neural networks. <Neural networks using non-volatile memory cell arrays>

[0021] Figure 6 conceptually illustrates an unrestricted example of a neural network utilizing a non-volatile memory array in this example. While this example uses a non-volatile memory array neural network for a facial recognition application, it is also possible to implement other suitable applications using a non-volatile memory array-based neural network.

[0022] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). The synapse CB1, going from input layer S0 to layer C1, scans the input image with a 3x3 pixel overlapping filter (kernel), applying different weight sets to some instances and shared weights to others, and shifts the filter by one pixel (or more than two pixels depending on the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., referred to as the filter or kernel) are provided to synapse CB1, where these nine input values ​​are multiplied by appropriate weights, and after adding the outputs of the multiplications, a single output value is determined, which is then given by the first synapse of CB1 to generate one of the pixels in the feature map of layer C1. The 3x3 filter is then shifted one pixel to the right within the input layer S0 (i.e., a column of 3 pixels is added to the right and a column of 3 pixels is dropped to the left), thereby providing the 9 pixel values ​​of this newly positioned filter to synapse CB1, where they are multiplied by the same weights as above, determining a second single output value by the associated synapse. This process continues until the 3x3 filter has scanned the entire 32x32 pixel image of the input layer S0 for all three colors and all bits (precision values). The process is then repeated with different weight sets to generate different feature maps of layer C1 until all feature maps of layer C1 have been computed.

[0023] In this example, layer C1 contains 16 feature maps, each having 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel; therefore, each feature map is a two-dimensional array, and thus in this example, layer C1 constitutes 16 layers of two-dimensional arrays (note that the layers and arrays referred to herein are logical relationships, not necessarily physical relationships; i.e., arrays are not necessarily oriented to physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of 16 different synaptic weight sets applied to the filtered scan. All C1 feature maps can target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first weight set shared across all scans used to generate this first map) can identify circular edges, a second map (generated using a second weight set different from the first) can identify rectangular edges or the aspect ratio of a particular feature, and so on.

[0024] Before moving from layer C1 to layer S1, an activation function P1 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions within each feature map. The purpose of the pooling function P1 is to average neighbor positions (or use the max function), for example, to reduce dependence on edge positions, and to reduce the data size before moving to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays, each 15x15 pixels). Synapse CB2, moving from layer S1 to layer C2, scans the maps in layer S1 with a 4x4 filter, shifting by 1 pixel. In layer C2, there are 22 12x12 feature maps. Before moving from layer C2 to layer S2, an activation function P2 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions within each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3, which goes from layer S2 to layer C3, an activation function (pooling) is applied, where all neurons in layer C3 are connected to all maps in layer S2 via each synapse of CB3. There are 64 neurons in layer C3. Synapse CB4, which goes from layer C3 to output layer S3, completely connects C3 to S3; that is, all neurons in layer C3 are connected to all neurons in layer S3. The output in S3 contains 10 neurons, where the neuron with the highest output determines the class. This output can, for example, indicate the identification or classification (classification) of the content of the original image.

[0025] Each layer of a synapse is implemented using an array or a portion of an array of non-volatile memory cells.

[0026] Figure 7 is a block diagram of an array that can be used for that purpose. The vector-by-matrix multiplication (VMM) array 32 contains non-volatile memory cells and is used as synapses between one layer and the next (e.g., CB1, CB2, CB3, and CB4 in Figure 6). Specifically, the VMM array 32 includes an array of non-volatile memory cells 33, erase gate and word line gate decoders 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, each of which decodes its respective input to the non-volatile memory cell array 33. Input to the VMM array 32 can be from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the non-volatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the non-volatile memory cell array 33.

[0027] The non-volatile memory cell array 33 serves two purposes. First, it stores the weights used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the weights stored in it by the inputs, adds them up for each output line (source line or bit line) to generate an output, which becomes the input to the next layer or the last layer. By having the non-volatile memory cell array 33 perform the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated, and the calculations are more power-efficient due to being performed in memory.

[0028] The output of the non-volatile memory cell array 33 is fed to a differential adder (such as an adding operational amplifier or an adding current mirror) 38, which adds the outputs of the non-volatile memory cell array 33 to create a single value for its convolution. The differential adder 38 is configured to perform the summation of positive and negative weights.

[0029] The summed output values ​​of the differential adder 38 are then fed to an activation function block 39, which normalizes the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The normalized output values ​​of the activation function block 39 become elements of a feature map as the next layer (e.g., C1 in Figure 6), and are then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes multiple synapses (receiving input from the previous layer of the neuron or from an input layer such as an image database), and the summing operational amplifier 38 and activation function block 39 constitute multiple neurons.

[0030] The inputs to the VMM array 32 in Figure 7 (WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog level), and the outputs can be analog level, binary level, or digital bits (in which case an output ADC is provided to convert the output analog level to digital bits).

[0031] Figure 8 is a block diagram showing the use of multiple layers of the VMM array 32, labeled in the figure as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in Figure 8, the input (indicated as Inputx) is converted from digital to analog by the digital-to-analog converter 31 and provided to the input VMM array 32a. The converted analog input can be voltage or current. Input D / A conversion of the first layer can be performed by using a function or LUT (look-up table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM array 32a. Input conversion can also be performed by an analog-to-analog (A / A) converter to convert an external analog input to the mapped analog input to the input VMM array 32a.

[0032] The output generated by input VMM array 32a is provided as input to the next VMM array (hidden level 1) 32b, the next VMM array (hidden level 1) 32b generates an output that is provided as input to the next input VMM array (hidden level 2) 32c, and so on. The various layers of VMM array 32 function as the synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a standalone physical non-volatile memory array, or multiple VMM arrays can utilize different parts of the same physical non-volatile memory array, or multiple VMM arrays can utilize overlapping parts of the same physical non-volatile memory array. The example shown in Figure 8 includes five layers (32a, 32b, 32c, 32d, 32e), namely one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will understand that this is merely an example and that a system may instead include more than two hidden layers and more than two fully connected layers. <Vector × Matrix Multiplication (VMM) Array>

[0033] Figure 9 shows a neuron VMM array 900, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (located at the top of the array). Alternatively, another reference array may be located at the bottom.

[0034] In the VMM array 900, control gate lines such as control gate line 903 extend vertically (thus the row-direction reference array 902 is perpendicular to the control gate line 903), and erase gate lines such as erase gate line 904 extend horizontally. Here, inputs to the VMM array 900 are provided to the control gate lines (CG0, CG1, CG2, CG3), and outputs of the VMM array 900 appear on the source lines (SL0, SL1). In one example, only even rows are used, and in another example, only odd rows are used. The current on each source line (SL0, SL1, respectively) performs the function of summing all the currents from the memory cells connected to that particular source line.

[0035] As described herein with respect to neural networks, the non-volatile memory cells of the VMM array 900, i.e., the memory cells 310 of the VMM array 900, may be configured to operate arbitrarily in a region below a threshold.

[0036] The non-volatile reference memory cells and non-volatile memory cells described herein are biased with weak inversion (in the region below the threshold) as follows: Ids = Io × e (Vg-Vth) / nVt =w × Io × e (Vg) / nVt , In the formula, w=e (-Vth) / nVt And, Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, Vt is the thermal voltage = k × T / q, where k is Boltzmann's constant, T is the Kelvin temperature, q is the electron charge, n is the gradient coefficient = 1 + (Cdep / Cox), where Cdep is the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is (Wt / L) × u ​​× Cox × (n-1) × Vt 2 It is proportional to , where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0037] When using an IV logarithmic converter that converts input current to input voltage using a memory cell (such as a reference memory cell or peripheral memory cell) or transistor: Vg = n × Vt × log[Ids / wp × Io] In the formula, wp is the w of the reference or peripheral memory cell.

[0038] For a memory array used as a vector × matrix multiplier VMM array with current input, the output current is as follows: Iout=wa×Io×e (Vg) / nVt That is to say Iout = (wa / wp) × Iin = W × Iin W=e (Vthp-Vtha) / nVt Here, wa = w of each memory cell in the memory array. Vthp is the effective threshold voltage of the peripheral memory cell, and Vtha is the effective threshold voltage of the main (data) memory cell. Note that the threshold voltage of a transistor is a function of the substrate bias voltage, and the substrate bias voltage, denoted as Vsb, can be modulated to compensate for various conditions at such temperatures. The threshold voltage Vth can be expressed as follows: Vth = Vth0 + gamma(SQRT|Vsb-2) * φF)-SQRT|2 * φF|) In the formula, Vth0 is the threshold voltage with zero substrate bias, φF is the surface potential, and gamma is the body effect parameter.

[0039] Word lines or control gates can be used as inputs to memory cells for input voltage.

[0040] Alternatively, the flash memory cells of the VMM array described herein can be configured to operate in a linear region. Ids=beta×(Vgs-Vth)×Vds, beta=u×Cox×Wt / L W=α(Vgs-Vth) That is, the weight W in the linear region is proportional to (Vgs - Vth).

[0041] The word line or control gate or bit line or source line can be used as an input to a memory cell operating within the linear region. The bit line or source line can be used as an output of the memory cell.

[0042] For an I-V linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor operating in the linear region can be used to linearly convert an input / output current to an input / output voltage.

[0043] Alternatively, the memory cells of the VMM array described herein can be configured to operate in the saturation region. Ids = 1 / 2 × beta × (Vgs - Vth) 2 , beta = u × Cox × Wt / L W α (Vgs - Vth) 2 , that is, the weight W is (Vgs - Vth) 2 proportional to.

[0044] The word line, control gate, or erase gate can be used as an input to a memory cell operating within the saturation region. The bit line or source line can be used as an output of the output neuron.

[0045] Alternatively, the memory cells of the VMM array described herein can be used in all regions or combinations thereof (below threshold, linear, or saturation) for each layer or multiple layers of a neural network.

[0046] Another example for the VMM array 32 of FIG. 7 is described in U.S. Patent No. 10,748,630, which is incorporated herein by reference. As described in the above application, the source line or bit line can be used as a neuron output (sum of currents output).

[0047] Figure 10 shows a neuron VMM array 1000, particularly suited to the memory cell 210 shown in Figure 2 and used as a synapse between the input layer and the next layer. The VMM array 1000 includes a memory array 1003 of non-volatile memory cells, a reference array 1001 of first non-volatile reference memory cells, and a reference array 1002 of second non-volatile reference memory cells. The reference arrays 1001 and 1002, arranged in the column direction of the array, function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1014 (partially shown) with current inputs flowing in. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference miniarray matrix (not shown).

[0048] The memory array 1003 serves two purposes. First, it stores the weights used by the VMM array 1000 in each memory cell. Second, the memory array 1003 effectively multiplies the weights stored in it by the inputs (i.e., the current inputs supplied to terminals BLR0, BLR1, BLR2, and BLR3, which are converted into input voltages by the reference arrays 1001 and 1002 and supplied to word lines WL0, WL1, WL2, and WL3), then adds all the results (memory cell currents) to generate the outputs of each bit line (BL0~BLN), which become inputs to the next layer or the last layer. By performing multiplication and addition functions, the memory array 1003 eliminates the need for separate multiplication and addition logic circuits and is also power efficient. Here, voltage inputs are supplied to word lines WL0, WL1, WL2, and WL3, and outputs appear on the respective bit lines BL0 to BLN during the read (inference) operation. Each current in bit lines BL0 to BLN performs the function of summing the currents from all non-volatile memory cells connected to that particular bit line.

[0049] Table 5 shows the operating voltages and currents of the VMM array 1000. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 5: Operation of VMM Array 1000 in Figure 10 [Table 5]

[0050] Figure 11 shows a neuron VMM array 1100, which is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1100 includes a memory array 1103 of non-volatile memory cells, a reference array 1101 of a first non-volatile reference memory cell, and a reference array 1102 of a second non-volatile reference memory cell. The reference arrays 1101 and 1102 extend in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that the word lines in the VMM array 1100 extend vertically. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on the source lines (SL0, SL1) during read operations. The current on each source line performs the function of summing all the currents from the memory cells connected to that particular source line.

[0051] Table 6 shows the operating voltages and currents of the VMM array 1100. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 6: Operation of VMM Array 1100 in Figure 11 [Table 6]

[0052] Figure 12 shows a neuron VMM array 1200, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of a first nonvolatile reference memory cell, and a reference array 1202 of a second nonvolatile reference memory cell. The reference arrays 1201 and 1202 function to convert the current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second nonvolatile reference memory cells are diode-connected through a multiplexer 1212 (partially shown) with current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Each multiplexer 1212 includes a separate multiplexer 1205 and a cascoding transistor 1204 to ensure that the respective bit lines (such as BLR0) of the first and second non-volatile reference memory cells maintain a constant voltage during read operations. The reference cells are tuned to a target reference level.

[0053] The memory array 1203 serves two purposes. First, it stores the weights used by the VMM array 1200. Second, the memory array 1203 effectively multiplies the weights stored in the memory array by the inputs (current inputs supplied to terminals BLR0, BLR1, BLR2, and BLR3, which are converted into input voltages by the reference arrays 1201 and 1202 and supplied to the control gates (CG0, CG1, CG2, and CG3)), then adds all the results (cell currents) to produce an output, which appears in BL0~BLN and becomes the input to the next layer or the last layer. By having the memory array perform the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated, and power efficiency is also improved. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3), and the output appears in the bit lines (BL0~BLN) during read operations. The current in each bit line performs the function of adding up all the currents from the memory cells connected to that particular bit line.

[0054] The VMM array 1200 performs one-way tuning of the non-volatile memory cells in the memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is applied to the floating gate (resulting in an incorrect value being stored in the cell), the cell is erased and the series of partial programming operations is restarted from the beginning. As shown, two rows sharing the same erase gate (such as EG0 or EG1) are erased together (known as page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0055] Table 7 shows the operating voltages and currents of the VMM array 1200. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, control gates of selected cells, control gates of unselected cells in the same sector as the selected cell, control gates of unselected cells in a different sector than the selected cell, erase gates of selected cells, erase gates of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 7: Operation of VMM Array 1200 in Figure 12 [Table 7]

[0056] Figure 13 shows a neuron VMM array 1300, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1300 comprises a memory array 1303 of nonvolatile memory cells, a reference array 1301 or a first nonvolatile reference memory cell, and a reference array 1302 of a second nonvolatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 extend vertically, and the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1300 is similar to the VMM array 1400 except that the VMM array 1300 performs bidirectional tuning, and each individual cell can be completely erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate by using individual EG lines. As shown, reference arrays 1301 and 1302 convert the input currents at terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1314), and these voltages are applied to memory cells in the row direction. Current outputs (neurons) are located in the bit lines BL0~BLN, and each bit line sums all the currents from the non-volatile memory cells connected to that particular bit line.

[0057] Table 8 shows the operating voltages and currents of the VMM array 1300. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, control gates of selected cells, control gates of unselected cells in the same sector as the selected cell, control gates of unselected cells in a different sector than the selected cell, erase gates of selected cells, erase gates of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 8: Operation of VMM Array 1300 in Figure 13 [Table 8]

[0058] Figure 22 shows a neuron VMM array 2200 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapse and neuron between the input layer and the next layer. In the VMM array 2200, inputs INPUT0...., INPUT N These are bit lines BL0, ...BL, respectively. N The signal is received, and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0059] Figure 23 shows a neuron VMM array 2300 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received by source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ...OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method].

[0060] Figure 24 shows a neuron VMM array 2400 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are the word lines WL0, ..., WL, respectively. M Received by, output OUTPUT0, ...OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method].

[0061] Figure 25 shows a neuron VMM array 2500 that is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUTM These are the word lines WL0, ..., WL, respectively. M Received by, output OUTPUT0, ...OUTPUT N These are bit lines BL0, ..., BL N It is generated by [this method].

[0062] Figure 26 shows a neuron VMM array 2600 that is particularly suitable for the memory cell 410 shown in Figure 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT n However, each of them is a vertical control gate line CG0, ..., CG N The signal is received, and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0063] Figure 27 shows a neuron VMM array 2700 that is particularly suitable for the memory cell 410 shown in Figure 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the inputs are INPUT0, ..., INPUT N These are bit lines BL0, ..., BL, respectively. N The bit line control gates 2701-1, 2701-2, ..., 2701-(N-1) and 2701-N, which are coupled to the bit line control gates, are received by the gates. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0064] Figure 28 shows a neuron VMM array 2800, which is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are the word lines WL0, ..., WL, respectively. M Received by, output OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N It is generated in [location].

[0065] Figure 29 shows a neuron VMM array 2900 that is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are control gate lines CG0, ..., CG M It is received as follows. Output OUTPUT0, ..., OUTPUT N These are the vertical source lines SL0, ..., SL, respectively. N It is generated in each source line SL i It is coupled to the source lines of all memory cells in column i.

[0066] Figure 30 shows a neuron VMM array 3000, which is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are control gate lines CG0, ..., CG M It is received as follows. Output OUTPUT0, ..., OUTPUT N These are the vertical bit lines BL0, ..., BL N Generated in each bit line BL i It is coupled to the bit lines of all memory cells in column i. <Long-term and short-term memory>

[0067] Prior art includes the concept known as long short-term memory (LSTM). LSTM units are often used within neural networks. LSTMs allow neural networks to store information for a predetermined period and use that information in subsequent operations. A conventional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell, and the duration for which information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0068] Figure 14 shows an exemplary LSTM1400. In this example, the LSTM1400 includes cells 1401, 1402, 1403, and 1404. Cell 1401 receives the input vector x0 and generates the output vector h0 and the cell state vector c0. Cell 1402 receives the input vector x1 and the output vector (hidden state) h0 from cell 1401. 、 Cell 1401 receives the cell state c0 from cell 1401 and generates the output vector h1 and the cell state vector c1. Cell 1403 receives the input vector x2, the output vector (hidden state) h1 from cell 1402, and the cell state c1 from cell 1402 and generates the output vector h2 and the cell state vector c2. Cell 1404 receives the input vector x3, the output vector (hidden state) h2 from cell 1403, and the cell state c2 from cell 1403 and generates the output vector h3. Additional cells are also available, and an LSTM with four cells is just an example.

[0069] Figure 15 shows an exemplary implementation of LSTM cell 1500 that can be used for cells 1401, 1402, 1403, and 1404 in Figure 14. LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from a preceding cell, and an output vector h(t-1) from a preceding cell, and generates the cell state vector c(t) and output vector h(t).

[0070] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors, and an adder device 1509 for adding two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or accessed for other purposes.

[0071] Figure 16 shows an LSTM cell 1600, which is an example implementation of LSTM cell 1500. For the reader's convenience, the same numbering method used in LSTM cell 1500 is used in LSTM cell 1600. Sigmoid function devices 1501, 1502, and 1503, and tanh device 1504 each contain multiple VMM arrays 1601 and activation function blocks 1602. Thus, VMM arrays are found to be particularly useful in LSTM cells used in certain neural network systems. Multiplier devices 1506, 1507, and 1508, and adder device 1509 are implemented in a digital or analog manner. Activation function block 1602 can be implemented in a digital or analog manner.

[0072] Figure 17 shows an alternative example of LSTM cell 1600 (and another example of an implementation of LSTM cell 1500). In Figure 17, sigmoid function devices 1501, 1502, and 1503, and tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-division multiplexed manner. The LSTM cell 1700 also includes a multiplier device 1703 for multiplying two vectors, an adder device 1708 for adding two vectors, a tanh device 1505 (including an activation function block 1702), a register 1707 for storing the value i(t) when i(t) is output from the sigmoid function block 1702, a register 1704 for storing the value f(t) × c(t-1) when its value is output from the multiplier device 1703 via the multiplexer 1710, a register 1705 for storing the value i(t) × u(t) when its value is output from the multiplier device 1703 via the multiplexer 1710, a register 1706 for storing the value o(t) × c(t) when its value is output from the multiplier device 1703 via the multiplexer 1710, and a multiplexer 1709.

[0073] While an LSTM cell 1600 contains multiple sets of VMM arrays 1601 and their respective activation function blocks 1602, an LSTM cell 1700 contains only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in the example of an LSTM cell 1700. Compared to an LSTM cell 1600, an LSTM cell 1700 requires only one-quarter the space for the VMMs and activation function blocks, thus requiring less space than an LSTM cell 1600.

[0074] It can be further understood that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a considerable amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the examples described below reduce the circuitry required outside the VMM array itself. <Gated recurrent unit>

[0075] Analog VMM implementations can be used in GRU (gated recurrent unit) systems. A GRU is a gate mechanism within a recurrent neural network. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0076] Figure 18 shows an exemplary GRU1800. In this example, the GRU1800 includes cells 1801, 1802, 1803, and 1804. Cell 1801 receives input vector x0 and produces output vector h0. Cell 1802 receives input vector x1 and output vector h0 from cell 1801 and produces output vector h1. Cell 1803 receives input vector x2 and output vector (hidden state) h1 from cell 1802 and produces output vector h2. Cell 1804 receives input vector x3 and output vector (hidden state) h2 from cell 1803 and produces output vector h3. Additional cells are also available, and a GRU with four cells is just an example.

[0077] Figure 19 shows an exemplary implementation of a GRU cell 1900 that may be used in cells 1801, 1802, 1803, and 1804 of Figure 18. The GRU cell 1900 takes an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and produces an output vector h(t). The GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to the components from the output vector h(t-1) and the input vector x(t). The GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, multiple multiplier devices 1904, 1905, and 1906 for multiplying two vectors, an adder device 1907 for adding two vectors, and a complementary device 1908 for subtracting the input from 1 to produce an output.

[0078] Figure 20 shows GRU cell 2000, an example implementation of GRU cell 1900. For the reader's convenience, the same numbering method used in GRU cell 1900 is used in GRU cell 2000. As can be seen from Figure 20, the sigmoid function devices 1901 and 1902, and the tanh device 1903, each contain multiple VMM arrays 2001 and activation function blocks 2002. Thus, it can be seen that VMM arrays are used in particular in GRU cells used in specific neural network systems. The multiplier devices 1904, 1905, 1906, the adder device 1907, and the complementary device 1908 are implemented in a digital or analog manner. The activation function block 2002 can be implemented in a digital or analog manner.

[0079] Figure 21 shows an alternative example of the GRU cell 2000 (and another example of an implementation of the GRU cell 1900). In Figure 21, the GRU cell 2100 utilizes the VMM array 2101 and the activation function block 2102, which, when configured as a sigmoid function, applies a number between 0 and 1 to control the extent to which each component of the input vector contributes to the output vector. In Figure 21, the sigmoid function devices 1901 and 1902, and the tanh device 1903, share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-division multiplexed manner. The GRU cell 2100 also includes a multiplier device 2103 for multiplying two vectors, an adder device 2105 for adding two vectors, a complementary device 2109 for subtracting an input from 1 to produce an output, a multiplexer 2104, a register 2106 for holding the value h(t-1)×r(t) when that value is output from the multiplier device 2103 via the multiplexer 2104, a register 2107 for holding the value h(t-1)×z(t) when that value is output from the multiplier device 2103 via the multiplexer 2104, and a register 2108 for holding the value h^(t)×(1-z(t)) when that value is output from the multiplier device 2103 via the multiplexer 2104.

[0080] While GRU cell 2000 contains multiple sets of VMM array 2001 and activation function block 2002, GRU cell 2100 contains only one set of VMM array 2101 and activation function block 2102, which is used to represent multiple layers in the example of GRU cell 2100. GRU cell 2100 requires 1 / 3 the space for the VMM and activation function block compared to GRU cell 2000, so GRU cell 2100 requires less space than GRU cell 2000.

[0081] It can be further understood that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a considerable amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the examples described below reduce the circuitry required outside the VMM array itself.

[0082] The input to the VMM array may be analog level, binary level, pulse, time-modulated pulse, or digital bit (in which case a DAC is required to convert the digital bit to an appropriate input analog level), and the output may be analog level, binary level, timing pulse, pulse, or digital bit (in which case an output ADC is required to convert the output analog level to a digital bit).

[0083] Typically, for each memory cell in a VMM array, each weight W can be provided by a single memory cell, a differential cell, or two blended memory cells (the average of two cells). In the case of a differential cell, two memory cells are required to provide the weight W as a differential weight (W = W+-W-). In the case of two blended memory cells, two memory cells are required to provide the weight W as the average of two cells.

[0084] Figure 31 shows the VMM system 3100. In some examples, the weights W stored in the VMM array are stored as differential pairs, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). In the VMM system 3100, half of the multiple bit lines are designated as W+ lines, i.e., bit lines that will connect to memory cells that will store the positive weight W+, and the other half of the multiple bit lines are designated as W- lines, i.e., bit lines that will connect to memory cells that will give the negative weight W-. The W- lines are interspersed alternately between the W+ lines. Subtraction operations are performed by adders, such as adders 3101 and 3102, which receive current from the W+ and W- lines. The outputs of the W+ lines and the W- lines are combined to effectively give W = W+ - W- for each pair of (W+, W-) cells in all pairs of (W+, W-) lines. Up to this point, we have described W- lines that are alternately scattered between W+ lines, but in other examples, W+ and W- lines can be arbitrarily placed anywhere within the array.

[0085] Figure 32 shows another example. In the VMM system 3210, positive weights W+ are given in the first array 3211, and negative weights W- are given in the second array 3212, which is separate from the first array, and the resulting weights are appropriately combined by the adder circuit 3213.

[0086] Figure 33 shows the VMM system 3300. The weights W stored in the VMM array are stored as differential pairs, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). The VMM system 3300 comprises arrays 3301 and 3302. Half of the multiple bit lines in each of arrays 3301 and 3302 are designated as W+ lines, i.e., bit lines connected to memory cells that store the positive weights W+, and the other half of the multiple bit lines in each of arrays 3301 and 3302 are designated as W- lines, i.e., bit lines connected to memory cells that give the negative weights W-. The W- lines are interspersed alternately between the W+ lines. Subtraction operations are performed by adders, such as adders 3303, 3304, 3305 and 3306, which receive current from the W+ and W- lines. The outputs of the W+ line and the W- line from each array 3301 and 3302 are combined together to effectively give W=W+-W- for each pair of (W+, W-) cells in all pairs of (W+, W-) lines. In addition, the W values ​​from each array 3301 and 3302 can be further combined via adders 3307 and 3308, such that each W value is the result of subtracting the W value from array 3302 from the W value from array 3301, meaning that the final result from adders 3307 and 3308 is the difference of one of the two difference values.

[0087] Each non-volatile memory cell used in an analog neural memory system is erased and programmed to hold a very specific and precise amount of charge, i.e., the number of electrons, within its floating gate. For example, each floating gate should hold one of N distinct values, where N is the number of different weights that each cell can represent. Examples of N include 16, 32, 64, 128, and 256.

[0088] Prior-generation VMM systems require considerable space and involve significant latency in both the input and output phases. In the input phase, multiple clock cycles are required to load activation data into the row registers before programming operations can begin. For example, in the case of 8-bit I / O, 8 bits of activation data are required for each row, which is typically 1024 rows or more. This requires 1 clock cycle per row, or 1024 clock cycles if there are 1024 rows, resulting in a latency of 10ns to 10μs. In the output phase, shifting out neuron output data also involves latency. For example, in the case of a 128ADC, 128 clock cycles are required for an 8-bit output.

[0089] To increase the overall operating speed of an artificial neural network, it is desirable to reduce latency in both the input and output phases. [Overview of the Initiative]

[0090] Numerous examples of output circuits and related methods for implementing parallel and pipelining operations in artificial neural networks are disclosed.

[0091]

[0092]

[0093]

[0094]

[0095]

[0096]

[0097]

[0098]

[0099]

[0100]

[0101]

[0102]

[0103]

[0104]

[0105]

[0106]

[0107]

[0108]

[0109]

[0110]

[0111]

[0112]

[0113]

[0114]

[0115]

[0116]

[0117]

[0118]

[0119]

[0120]

[0121]

[0122]

[0123]

[0124]

[0125]

[0126]

[0127]

[0128]

[0129]

[0130]

[0131]

[0132]

[0133]

[0134]

[0135]

[0136]

[0137]

[0138]

[0139]

[0140]

[0141] [Brief explanation of the drawing]

[0142] [Figure 1] This is a diagram illustrating an artificial neural network. [Figure 2] This shows a prior art split-gate flash memory cell. [Figure 3] This shows another prior art split-gate flash memory cell. [Figure 4] This shows another prior art split-gate flash memory cell. [Figure 5] This shows another prior art split-gate flash memory cell. [Figure 6] This diagram illustrates various levels of exemplary artificial neural networks that utilize one or more non-volatile memory arrays. [Figure 7]This is a block diagram illustrating a VMM system. [Figure 8] This block diagram illustrates an exemplary artificial neural network utilizing one or more VMM systems. [Figure 9] Here is another example of a VMM system. [Figure 10] Here is another example of a VMM system. [Figure 11] Here is another example of a VMM system. [Figure 12] Here is another example of a VMM system. [Figure 13] Here is another example of a VMM system. [Figure 14] This demonstrates prior art long- and short-term memory systems. [Figure 15] This shows an example cell used in long- and short-term memory systems. [Figure 16] Figure 15 shows an exemplary embodiment of the cell. [Figure 17] Another exemplary embodiment of the cell shown in Figure 15 is presented. [Figure 18] This shows a prior art gated regression unit system. [Figure 19] An exemplary cell for use in a gated regressive unit system is shown. [Figure 20] Figure 19 shows an exemplary embodiment of the cell. [Figure 21] Another exemplary embodiment of the cell shown in Figure 19 is presented. [Figure 22] Here is another example of a VMM system. [Figure 23] Here is another example of a VMM system. [Figure 24] Here is another example of a VMM system. [Figure 25] Here is another example of a VMM system. [Figure 26] Here is another example of a VMM system. [Figure 27] Here is another example of a VMM system. [Figure 28] Here is another example of a VMM system. [Figure 29] Here is another example of a VMM system. [Figure 30] Here is another example of a VMM system. [Figure 31] Here is another example of a VMM system. [Figure 32] Here is another example of a VMM system. [Figure 33] Here is another example of a VMM system. [Figure 34] Here is another example of a VMM system. [Figure 35A] The input block for the VMM system is shown. [Figure 35B] The input block for the VMM system is shown. [Figure 36] The input block for the VMM system is shown. [Figure 37A] This shows the signals associated with the input operation for the VMM array. [Figure 37B] This shows the signals associated with the input operation for the VMM array. [Figure 38A] The input block for the VMM system is shown. [Figure 38B] This shows how to input the information. [Figure 39A] The input block for the VMM system is shown. [Figure 39B] The input block for the VMM system is shown. [Figure 39C] The input block for the VMM system is shown. [Figure 39D] The input block for the VMM system is shown. [Figure 40A] This shows the output block for the VMM system. [Figure 40B] This shows the output block for the VMM system. [Figure 40C] This shows the output block for the VMM system. [Figure 41] Waveforms for the VMM system are shown. [Figure 42] Waveforms for the VMM system are shown. [Figure 43]Shows waveforms for the VMM system. [Figure 44] Shows waveforms for the VMM system. [Figure 45] Shows the neural read operation method. [Figure 46] Shows the neural read operation method. [Figure 47] Shows the neural read operation method. [Figure 48] Shows the neural read operation method. [Figure 49] Shows the neural read operation method.

Mode for Carrying Out the Invention

[0143] <Structure of the VMM System> FIG. 34 shows a block diagram of a VMM system 3400. The VMM system 3400 includes a VMM array 3401, a row decoder 3402, a high-voltage decoder 3403, a column decoder 3404, a bit-line driver 3405 (such as a bit-line control circuit for programming), an input circuit 3406, an output circuit 3407, a control logic 3408, and a bias generator 3409. The VMM system 3400 further includes a high-voltage generation block 3410 including a charge pump 3411, a charge pump regulator 3412, and a high-voltage level generator 3413. The VMM system 3400 further includes a (program / erase, or weight tuning) algorithm controller 3414, an analog circuit 3415, a control engine 3416 (which may include, but is not limited to, special functions such as arithmetic functions, activation functions, embedded microcontroller logic, etc.), a test control logic 3417, and a static random access memory (SRAM) block 3418 for storing intermediate data such as for the input circuit (e.g., activation data) or the output circuit (neuron output data, partial sum output neuron data), or data input for programming (data input for the entire row or multiple rows, etc.).

[0144] The input circuit 3406 may include circuits such as a DAC (digital-to-analog converter), DPC (digital-to-pulses converter, digital-to-time modulated pulse converter), AAC (analog-to-analog converter, such as a current-to-voltage converter or logarithmic converter), PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 3406 may implement one or more of the following: normalization, linear or nonlinear up / downscaling functions, or arithmetic functions. The input circuit 3406 may implement a temperature compensation function for the input level. The input circuit 3406 may implement an activation function such as ReLU or sigmoid. The input circuit 3406 can store digital activation data that is applied as an input signal during program or read operation, or combined with an input signal. The digital activation data can be stored in a register. The input circuit 3406 may include a sample-and-hold circuit and a buffer, and may also include a circuit for driving array terminals such as CG lines, WL lines, EG lines, and SL lines. A DAC can be used to convert digital activation data into analog input voltages applied to the array.

[0145] The output circuit 3407 may include circuits such as an ITV (current-to-voltage circuit), an ADC (analog-to-digital converter for converting the analog output of a neuron into digital bits), an AAC (analog-to-analog converter, such as a logarithmic converter), an APC (analog-to-pulse converter, analog-to-time modulated pulse converter), or any other type of converter. The output circuit 3407 can convert the array output into activation data. The output circuit 3407 may implement an activation function such as a rectified linear activation function (ReLU) or a sigmoid. The output circuit 3407 may implement one or more of the following functions of the neuron output: statistical normalization, regularization, up / down scaling / gain function, statistical rounding, or arithmetic function (e.g., addition, subtraction, division, multiplication, shift, logarithm). The output circuit 3407 may implement a temperature compensation function for the neuron output or array output (such as a bit line output) in order to keep the power consumption of the array nearly constant, or to improve the accuracy of the array (neuron) output by keeping the IV gradient nearly the same with respect to temperature changes. The output circuit 3407 may also include a register for storing the output data.

[0146] Figure 35A shows an input block 3500 used to provide input to the VMM array 3401. The input block 3500 includes a global digital-to-analog converter (DAC) 3501, row registers 3502-0 to 3502-n, each corresponding to one of the numbered rows 0 to n in the array, digital comparator blocks 3503-0 to 3503-n, each corresponding to one of the numbered rows 0 to n in the array, row sample-and-hold buffers 3504-0 to 3504-n, each corresponding to one of the numbered rows 0 to n in the array, and output signals 3505-0 to 3505-n, each corresponding to one of the numbered rows 0 to n in the array, and denoted as CGIN0, CGIN1, ..., CGINn-1, and CGINn, respectively. The signal GDACsup is the global DAC signal supplied by the global DAC3501. Signals CGIN0 through CGINn are coupled to the respective row inputs of the array 3401. CLKDAC is the input clock of the GDAC to provide analog output values. In one example, these analog output values ​​correspond to the count of the CLKDAC clock.

[0147] The digital comparator block 3503 compares the value stored in the associated row register 3502 with the signal CLKCOUNTx. CLKCOUNTx is the result of a counter that counts the clock signal over a predetermined interval. If they match, the corresponding row S / H 3504 is enabled by its respective digital comparator block 3503 to sample a value from the global DAC 3501 into its respective row S / H buffer. This technique is referred to as global row DAC sampling. As described above, each row in the VMM array 3401 has a corresponding row register 3502, a digital comparator block 3503, and a row S / H 3504.

[0148] During operation, row registers 3502-0 to 3502-n are loaded with the digital input bits DINx (where x is the number of bits, such as 8 or 16 bits) for that particular row and receive the clock signal CLK. The CLK signal is used to load the data from the digital input bits DINx into the respective row registers 3502-x. The global DAC 3501 is shared by all rows and performs digital-to-analog conversion on the digital bits DINx stored in the specific row registers 3502 in a time-division multiplexing scheme. The conversion is performed by each digital comparator block 3503 by comparing the digital input bits of the particular row with the signal CLKCOUNTx, which is a digital count value. When the digital count value of the signal CLKCOUNTx matches the contents of the respective row register 3502, the corresponding row sample-and-hold buffer 3504 for that row samples the analog output from the global DAC 3501, holds the value, and applies that value as the output signal 3505 for that particular row. The output signal 3504 can be applied, for example, to a control gate line, word line, or erase gate during programming operations in that particular row, in the manner described above with respect to other figures.

[0149] Alternatively, the row sample-and-hold buffer 3504 may be shared among two or more rows by time-division multiplexing the row sample-and-hold buffer.

[0150] Figure 35B shows the input block 3550 used to provide input to the VMM array 3401. The input block 3550 includes a global digital-to-analog converter (DAC) 3551, row registers 3552-0 to 3552-n, each corresponding to one of the numbered rows 0 to n in the VMM array 3401, digital mux blocks 3553-0 to 3553-n, each corresponding to one of the numbered rows 0 to n, row sample-and-hold (S / H) buffers 3554-0 to 3554-n, each corresponding to one of the numbered rows 0 to n, and output signals 3555-0 to 3555-n, denoted as CGIN0, CGIN1..., CGINn-1, and CGINn, each corresponding to one of the numbered rows 0 to n. The digital mux block 3553 is used to multiplex the data from the row register 3552 to the bus GDAC_DINx, which is then applied as input to the global DAC 3551. The corresponding row S / H buffer 3554 samples the value from the global DAC into the local S / H buffer 3554. Each row has its own row register 3552, S / H buffer 3554, and output signal 3555.

[0151] During operation, row registers 3552-0 to 3552-n are loaded with the digital input bits DINx (where x is the number of bits, such as 8 or 16 bits) for that particular row and receive the clock signal CLK. The CLK signal is used to load the data from the digital input bits DINx into the respective row registers 3552. The global digital-to-analog converter 3551 is shared by all rows and performs digital-to-analog conversion on the digital bits DINx stored in the particular row registers 3552 using a time-division multiplexing scheme. The conversion is performed by multiplexing the row register data to the data input (bus GDAC_DINx) of the global DAC 3551. The multiplexing of row register data to the data input bus GDAC_DINx is enabled by the respective enable signals EN-x 3557-x for each row. The corresponding row sample-and-hold buffer 3554 samples the analog output from the global DAC 3551, holds its value, and applies that value as the output signal 3555 for that particular row. The output signal 3555 can be applied, for example, to a control gate line or word line during programming operations in that particular row, in the manner described above with respect to other figures.

[0152] Alternatively, the row sample-and-hold buffer 3554 can be shared among multiple rows by time-division multiplexing the row sample-and-hold buffer.

[0153] Figure 36 shows the input block 3600 used to provide input to the VMM array 3401. The input block 3600 includes two global DACs 3601-0 and 3601-1, row registers 3602-0 to 3602-n, each corresponding to one of the numbered rows 0 to n in the VMM array 3401, digital comparator blocks 3603 to 3603-n, each corresponding to one of the numbered rows 0 to n in the VMM array 3401, row sample-and-hold buffers 3604-0 to 3604-n, each corresponding to one of the numbered rows 0 to n in the VMM array 3401, and output signals 3605-0 to 3605-n, denoted as CGIN0, CGIN1..., CGINn-1 and CGINn, each corresponding to one of the numbered rows 0 to n. The digital comparator block 3603 compares the value stored in each row register 3602 with the signal CLKCOUNTx, which is the result of a counter that counts the clock signal over a predetermined interval. When the digital count value of the signal CLKCOUNTx matches the contents of each row register 3602, each row S / H buffer 3604 is made capable of sampling a value from the global DAC 3601 into its respective S / H buffer 3604. Each row has its own row register 3602, digital comparator block 3603, and row S / H buffer 3604.

[0154] During operation, row registers 3602-0 to 3602-n are loaded with the digital input bits DINx of the associated row (where x is the number of bits, such as 8 or 16 bits) and receive the clock signal CLK. The CLK signal is used to load data from the digital input bits DINx into row registers 3602-x. The global DAC3601 (consisting of multiple global DACs such as 3601-0 and 3601-1) is shared by all rows. For example, global DAC3601-0 operates on even rows, and global DAC3601-1 operates on odd rows. The global DAC3601 receives the clock signal CLKDAC and outputs an analog value corresponding to the count of the CLKDAC clock. The global DAC3601 performs digital-to-analog conversion on the digital bits DINx stored in the associated row register 3602 (via the GDAC_DINx bus). The row sample-and-hold buffer 3604 corresponding to that row samples the analog output from the global digital-to-analog converter 3601, holds the value, and applies that value as the output signal 3605 for that particular row. The output signal 3605 can be applied to a control gate line or word line during programming operations in that particular row(s), for example, in the manner described above with respect to other figures.

[0155] Figure 37A shows waveform 3700 illustrating exemplary voltage levels of outputs CGIN0 and CGIN1 after the respective sample-and-hold operation on each GDACsup3701 using row sample-and-hold buffer 3504 in Figure 35A, row sample-and-hold buffer 3554 in Figure 35B, or row sample-and-hold buffer 3604 in Figure 36. The signal GDACsup3701 is the voltage supplied from global DACs such as global DAC3501 in Figure 35A, global DAC3551 in Figure 35B, and global DAC3601-0 and 3601-1 in Figure 36. GDACsup3701 is a linear DAC voltage curve, meaning that the global DAC output represents a linear conversion of the digital input value to an analog value. Such a linear conversion is suitable for memory cells operating in the linear domain. For example, signal 3702 indicates the sampled voltage value (level) of row 0 (CGIN0), and signal 3703 indicates the sampled voltage value (level) of row 1 (CGIN1). Signal DAC_sampling_en3704 is a control signal that enables the sampling and hold operation. Four examples of sampling are shown in edges 3705, 3706, 3707, and 3708, corresponding to different voltages being sampled.

[0156] Figure 37B shows waveform 3720 illustrating the exemplary logarithmic voltage levels of outputs CGIN0 and CGIN1 after each sample-and-hold operation for each GDACsup3721 using row sample-and-hold buffer 3504 in Figure 35A, row sample-and-hold buffer 3554 in Figure 35B, or row sample-and-hold buffer 3604 in Figure 36. The use of logarithmic conversion of digital input values ​​to analog values ​​is suitable for memory cells operating in the subthreshold region. Alternatively, it can be used for memory cells operating in the saturation region. Signal GDACsup3721 is the voltage supplied from global DACs such as global DAC3501 in Figure 35A, global DAC3551 in Figure 35B, and global DAC3601-0 and 3601-1 in Figure 36. GDACsup3721 is the logarithmic DAC curve. For example, signal 3722 indicates the sampled voltage value (level) of row 0 (CGIN0), and signal 3723 indicates the sampled voltage value (level) of row 1 (CGIN1). Signal DAC_sampling_en3724 is a control signal that enables the sampling and hold operation. Four examples of sampling are shown in edges 3725, 3726, 3727, and 3728, corresponding to different voltages being sampled.

[0157] The intelligent DAC sampling method is as follows: As shown in Figures 37A and 37B, enabling sampling is performed only in row registers used for specific input operations, meaning that sampling is enabled at the first minimum value of the row register and terminates at the maximum value of the row register. This is to reduce the sampling time to what is required based only on the range of input values ​​of the row register (i.e., the activation input values).

[0158] Furthermore, if the maximum number of rows are enabled for sampling at once, for example, up to 128 rows are enabled, and therefore, for example, if there are 180 rows enabled for the same input value, sampling will occur twice, i.e., the first time for 128 rows and the second time for 62 rows, or the first time for 90 rows and the second time for 90 rows. This is to reduce the load on the sampling circuit when a large load could cause undesirable setup times.

[0159] Figure 38 illustrates the input block 3800 used in the VMM array 3401. The input block 3800 comprises a subblock 3810, an SRAM 3418, registers 3801-0, 3801-1, ..., 3801-n, and address decoders 3804-0, 3804-1, ..., 3804-n. The subblock 3810 may optionally comprise one of the input blocks 3500, 3550, and 3600 from Figures 35A, 35B, and 36, respectively. The subblock 3810 comprises registers 3802-0, 3802-1, ..., 3802-n, row sample-and-hold buffers 3803-0, 3803-1, ..., 3803-n, and optionally intermediate circuits from Figures 35A, 35B, and 36. In the example where subblock 3810 contains input block 3500, register 3802 contains row register 3502, and row sample-and-hold buffer 3803 contains row sample-and-hold buffer 3504. In the example where subblock 3810 contains input block 3550, register 3802 contains row register 3552, and row sample-and-hold buffer 3803 contains row sample-and-hold buffer 3554. In the example where subblock 3810 contains input block 3600, register 3802 contains row register 3602, and row sample-and-hold buffer 3803 contains row sample-and-hold buffer 3604.

[0160] The address decoder 3804 receives an address for a data input load operation to load data into register 3802 or register 3801. The data is activation data or input data, such as objects or images to be classified or recognized in a neural network application. It outputs a signal to enable register 3801 or register 3802, indicating which register is asserted for the data during the load operation. The data input (not shown) typically varies from 8 to 256 bits.

[0161] The address decoder 3804 also receives an address for read-verification or program operation and outputs a signal to register 3801 or register 3802 indicating which row is asserted for read-verification or program operation. Read-verification is a read operation used in weight tuning, in which a cell is programmed for a target current representing the target weight in the neural network, and then the cell current is verified to ensure that it approximates the target current during the weight tuning algorithm.

[0162] Register 3802 enables the row sample-hold buffer 3803 using the activation data stored in each such register. In an exemplary implementation, there may be 1024 rows and 1024 instances of register 3802, where 8 bits of activation data are stored in each register 3802.

[0163] The number of clock cycles R required to load data for register 3802 is calculated by dividing R = number of rows × 8 (for 8-bit activation data) by the data width, for example, 16-bit data (e.g., R = 1024 × 8 / 16 = 512).

[0164] Each register 3801 is coupled to each register 3802 and contains one associated register. Each register 3801 is loaded with activation data for its associated register 3802, which may be performed sequentially over R clock cycles. Then, during the first clock cycle, the data from each register 3801 is loaded in parallel into its associated register 3802. Thus, registers 3802 are loaded in parallel from each register 3801 in a single time period, rather than being loaded serially over R clock cycles. This significantly speeds up the timing of the data in the loading operation.

[0165] Optionally, the SRAM3418 can be used as a background operation to sequentially load all registers 3802 over R clock cycles.

[0166] Optionally, SRAM3418 is used to sequentially load its data into register 3801. Figure 38B shows an input method 3850 that can be performed using the input block 3800 in Figure 38A. The first operation is to output multiple row enable signals in response to an address using multiple address decoders (3851). The next operation is to sequentially store activation data in response to the multiple row enable signals using the first multiple registers (3852). The sequential storage step includes the step of receiving the activation data from static random access memory using the first multiple registers, at any discretion. The next operation is to store the activation data received from the first multiple registers in parallel using a second multiple register (3853). The next operation is to drive rows of an array of nonvolatile memory cells during read neuron operation using multiple row sample-hold buffers in response to the activation data received from the second multiple registers (3854).

[0167] Figure 39A shows input block 3900. Input block 3900 comprises subblock 3910, VMM array 3401, and address decoders 3904-0, 3904-1, ..., 3904-n. Subblock 3910 may optionally comprise one of input blocks 3500, 3550, and 3600 from Figures 35A, 35B, and 36, respectively. Subblock 3910 comprises registers 3902-0, 3902-1, ..., 3902-n, row sample-and-hold buffers 3903-0, 3903-1, ..., 3903-n, and optionally intermediate circuits from Figures 35A, 35B, and 36. In the example where subblock 3910 contains input block 3500, row register 3902 contains row register 3502, and row sample-and-hold buffer 3803 contains row sample-and-hold buffer 3504. In the example where subblock 3910 contains input block 3550, row register 3902 contains row register 3552, and row sample-and-hold buffer 3903 contains row sample-and-hold buffer 3554. In the example where subblock 3910 contains input block 3600, row register 3902 contains row register 3602, and row sample-and-hold buffer 3903 contains row sample-and-hold buffer 3604.

[0168] The address decoder 3904 receives an address for a data input load operation to load data (not shown) into register 3902. The data is activation data or input data, such as objects or images to be classified or recognized in a neural network application. It outputs a signal that enables row register 3902, indicating which register is asserted for the data during the load operation. The data input (not shown) typically varies from 8 to 256 bits.

[0169] The address decoder 3904 may also receive an address for read verification or program operation and output a signal to the row register 3902 indicating which row is asserted for read verification or program operation. In this example, each row register stores activation data (e.g., 8-bit activation data) and one or more tag bits, for example, one for row enable and another for row DAC sampling. For example, row register 3902-0 contains tag bit 3905-0, row register 3902-1 contains tag bit 3905-1, row register 3902-n contains tag bit 3905-n, and so on. The tag bit (row enable tag bit) 3905 is used for row enable, which disables the activation input data stored in the row register, regardless of whether the row has been selected by the address decoder 3904. For example, if the tag bit 3905-0 for row 0 has a specific value (e.g., the value "1"), the activation data in row register 3902-0 is output. If tag bits 3905-0 have a different value (e.g., a value of "0"), no activation data is output in row register 3902-0, and row S / H buffer 3903-0 receives the Z state from row register 3902-0. Another tag bit (row S / H tag bit) is used for row DAC sampling to enable or disable sampling of global DAC values ​​to the local row S / H buffer 3903.

[0170] Figure 39B shows input block 3920. Input block 3920 is similar to input block 3900, except that it contains a second set of row registers (shadow registers) 3906-0, 3906-1, ..., 3906-n, each containing its respective tag bits 3907-0, 3907-1, ..., 3907-n. Each row can toggle between row register 3902 and row register 3906. For example, during one operation, address decoder 3904 provides an output to row register 3902, and during another operation, address decoder 3904 provides an output to row register 3906. For example, during one operation, row register 3902-0 outputs data if tag bit 3905 is enabled, and during another operation, row register 3906 outputs data if tag bit 3907 is enabled. This toggle can be implemented by a multiplexer (not shown) or other control logic. In this way, activation data can be loaded into one set of row registers 3902 or 3906, while the other set is used to actively output its activation data according to a signal from address decoder 3904.

[0171] Figure 39C shows input block 3940. Input block 3940 is similar to input block 3900, except that it contains a second set of row registers 3908-0, 3908-1, ..., 3908-n, each containing its respective tag bits 3909-0, 3909-1, ..., 3909-n. Each row can toggle between row register 3902 and row register 3908. For example, during one operation, address decoder 3904 provides an output to row register 3902, and during another operation, address decoder 3904 provides an output to row register 3908. For example, during one operation, row register 3902 outputs data if tag bit 3905 is enabled, and during another operation, row register 3908 outputs data if tag bit 3909 is enabled. This toggle can be implemented by a multiplexer (not shown) or other control logic. In this way, activation data can be loaded into one set of row registers 3902 or 3908, while the other set of row registers is used to actively output its activation data according to a signal from address decoder 3904.

[0172] Figure 39D shows input block 3960. Input block 3960 is similar to input block 3940, except that it includes a second set of row sample-and-hold buffers 3911-0, 3911-1, ..., 3911-n for the same array input (e.g., CGINx). Each row can toggle between row register 3902 and row register 3908. For example, during one operation, address decoder 3904 provides an output to row register 3902, and during another operation, address decoder 3904 provides an output to row register 3908. Similarly, during one operation, row register 3902 outputs data according to tag bit 3905, and during another operation, row register 3908 outputs data according to tag bit 3909. Each row can toggle between row S / H buffer 3903 and row S / H buffer 3911 (using control signals (not shown)). This toggle can be implemented by a multiplexer (not shown) or other control logic. In this way, activation data can be loaded into one set of row registers 3902 or 3908, while the other set is used to actively output its activation data according to a signal from address decoder 3904.

[0173] In one example, the first activation data and the first tag bit are loaded into row register 3902, and the second activation data and the second tag bit are loaded into row register 3908. The first and second activation data may be the same or different, and the first and second tag bits may be the same or different.

[0174] Figure 40A shows the input block 4000. The output block 4000 receives output current from the VMM array 3401 (not shown), typically from the bit lines or source lines of the VMM array 3401. The output block 4000 comprises a current-to-voltage converter 4001, an analog-to-digital converter 4002, an output register 4003, and an output register 4004. The current-to-voltage converter 4001 converts the current received from the VMM array 3401 into corresponding voltages, the values ​​of which reflect the current values ​​received from the VMM array 3401. The analog-to-digital converter 4002 converts each of these voltages into bits representing the voltage values ​​received from the respective current-to-voltage converters 4001, which thus reflect the current values ​​received from the VMM array 3401. The bits are then stored in the output register 4003 or output register 4004. The output operation can be toggled between the output register 4003 and the output register 4004. For example, during a first operation in a first time period (e.g., one or more clock cycles), output data is loaded into output register 4003. During a second operation in a second time period (e.g., one or more clock cycles) after the first time period, the data is read from output register 4003 by another device in the system, and new output data is loaded into output register 4004. During a third operation in a third time period (e.g., one or more clock cycles) after the second time period, the new output data can be read from output register 4004 by another device in the system and optionally loaded into output register 4003, and the sequence repeats. This reduces the amount of latency associated with output operations because data can be read from the first output register by an external device while other data can be loaded into other output registers simultaneously.

[0175] Optionally, the output block 4000 optionally includes column tag bits 4005 for enabling the current-to-voltage converter 4001 and the analog-to-digital converter 4002. The column tag bits 4005 may be included in either the current-to-voltage converter 4001 or the analog-to-digital converter 4002. The column tag bits 4005 may include column tag bits for each column in the VMM array 3401. Loading the column tag bits 4005 is similar to loading the row tag bits as described above with reference to Figures 39A to 39D. The function of the column tag bits is similar to the function of the row tag bits as described above with reference to Figures 39A to 39D. For example, the current-to-voltage converter 4001 and the analog-to-digital converter 4002 can be configured to output data for a column when the column tag bit 4005 for a given column has a first value, and not output data when the column tag bit has a second value, depending on which column tag bit 4005 is included in.

[0176] Figure 40B shows the input block 4020. The output block 4020 is the same as the output block 4000, but with the addition of an accumulator 4021. The accumulator 4021 can sum the values ​​received from the current-to-voltage converter 4001, the analog-to-digital converter 4002, the output register 4003, and the output register 4004 over a certain time period. This can be useful, for example, when neural readout operations are performed on the VMM array 3401 in a time-division manner, by reading half of a row in a first time period and the other half of a row in a second time period. The output from the first time period can be received by the output register 4003, the output from the second time period can be received by the output register 4004, and the accumulator can sum the values ​​received from the output registers 4003 and 4004.

[0177] The output block 4000 optionally includes column tag bits 4005 for enabling the current-to-voltage converter 4001 and the analog-to-digital converter 4002. The column tag bits 4005 may be included in either the current-to-voltage converter 4001 or the analog-to-digital converter 4002. The column tag bits 4005 may include column tag bits for each column in the VMM array 3401. Loading the column tag bits 4005 is similar to loading the row tag bits as described above with reference to Figures 39A to 39D. The function of the column tag bits is similar to the function of the row tag bits as described above with reference to Figures 39A to 39D. For example, the current-to-voltage converter 4001 and the analog-to-digital converter 4002 can be configured to output data for a column when the column tag bit 4005 for that column has a first value, and not output data when the column tag bit has a second value, depending on which of the two the column tag bits 4005 is included in.

[0178] Figure 40C provides an exemplary circuit for an output accumulator 4021. The output accumulator receives data from the current-to-voltage converter 4001, the analog-to-digital converter 4002, the output register 4003, and the output register 4004. The data is received by a shifter 4042 that performs a shift function in response to EN_SHIFT. The output D1 of the shifter 4042 is provided to an adder 4043, which adds D1 to D2, and the adder 4043 also receives D2, which is enabled by EN_ADD.

[0179] The output of adder 4043 is provided to one or more accumulator registers 4044, which store the output of adder 4043 and return it to adder 4043 as D2 for the next addition operation. In one configuration with three or more accumulator registers 4044, one shifter 4042, and one adder 4043, the shifter 4042 and adder 4043 are shared between different outputs of ITV 4001 and ADC 4002, or output register 4003 or 4004. Each accumulator register is used for operation on each output of ITV 4001 and ADC 4002, or output register 4003 or 4004. In this way, the outputs of current-to-voltage converter 4001, analog-to-digital converter 4002, output register 4003, and output register 4004 can be added over a period of time.

[0180] The shifter 4042 is used, for example, in serial input (DAC) mode, in which one bit of the activation input is read at a time, and the amount of bit shift in the output depends on the binary position of the input bit. For example, the LSB (least significant bit) of the input bit results in no shift in the output, the (LSB+1) input bit results in a 1-bit left shift, the (LSB+2) input bit results in a 2-bit left shift, and so on. This read operation is performed 8 times for an 8-bit activation input. The final output from the accumulator register 4044 is the result of the entire 8-bit activation input.

[0181] Figure 41 shows waveforms 4100 for the first phase 4101 in which activation data is loaded into the row registers, and the second phase 4102 in which a neural readout operation is performed using that activation data.

[0182] Figure 42 shows the waveform 4200 of the random access read operation 4201.

[0183] Figure 43 shows the waveform 4300 of the burst read operation 4301.

[0184] Figure 44 shows the waveform 4400 of the neural readout operation 4401.

[0185] Figure 45 shows neural readout operation 4500. Neural readout operation 4500 begins (4501). Activation data is loaded into the row register (4502). Next, a group of N rows is enabled (4503). Next, a column address is input (4504). A readout operation is performed (4505), which involves DAC sampling as shown in Figures 37A and 37B (using the circuits shown in Figures 35A-35B, 36, 38, and 39A-39D) and (bit line) output circuit 3407 in Figure 34 (using an ITV to convert current to voltage and an ADC to convert voltage to a digital output), where the output data is the digital output from the ADC. The data is loaded into the output register (4506). The system determines whether another column address needs to be read. If yes, it returns to operation 4504. Otherwise, the system determines whether another group of N rows needs to be read (4508). If yes, it returns to operation 4503. If no, a neural read operation is performed (4509), at which point the data output is optionally shifted out (4510), or the neural read operation ends. For each neural read operation, the neural read time for a group of rows with column switching is the DAC latency for one row + the ITV+DAC latency for N columns with multiplexing. For example, if the DAC latency is 2 μs and the ITV+ADC latency is 1 μs, the time to read the entire row is 1 × (DAC latency) + 16 × (ITV+ADC latency) = 18 μs. Essentially, for the next column neural read, the DAC latency does not contribute any additional time.

[0186] Figure 46 shows the neural read operation 4600. Neural read operation 4600 begins (4601). Activation data is loaded into the first set of row registers (4603). Then, the activation data is loaded into the second set of row registers (4602). Simultaneously with this event, the column address or row group is modified (4604). The read operation is performed (4605). Output data is loaded into the output register (4606). If no read operation is performed (4607), the process returns to operation 4604. If a read operation is performed, the system (using a logic controller (not shown)) determines whether data needs to be loaded from the second set of row registers to the first set of row registers (4608). If no, the neural read operation is performed (4611). If yes, the data is loaded from the second set of row registers to the first set of row registers (4609). The system then determines whether to perform a neural read operation (4610). If yes, the neural read operation is performed (4611). Otherwise, it returns to operation 4604.

[0187] Figure 47 shows the neural read operation 4700. First, the activation data is loaded into the first set of row registers (4701). Next, the activation data is loaded into the second set of row registers (4702). Simultaneously with this event, the column address or row group is changed (4703). The read operation is performed (4704). The data is loaded into the output register (4705). If the read operation is performed (4706), the system proceeds to operation 4707. Otherwise, the system returns to operation 4703. In operation 4707, the system determines whether the second set of row registers and their corresponding row S / H buffers are enabled. If yes, the operation is performed (4708). Otherwise, the second set of row registers and their corresponding row S / H buffers are enabled, and the system returns to operation 4703 and continues the neural read operation.

[0188] Figure 48 shows read operation 4800. Previously, digital output data has been loaded into output register 1 or output register 2. Then, the output data is shifted out from output register 1 or output register 2 (4801).

[0189] Figure 49 shows the neural read operation 4900. First, activation data is loaded into the row register (4901). Next, the data is shifted out from output register 1 or output register 2 (4902). Simultaneously with this event, the column address or row group is changed (4903). The neural read operation is performed (4904). The data is loaded into output register 1 or output register 2 (4905). If the neural read operation is to be performed (4906), the operation is performed (4907). Otherwise, the system returns to operation 4903 and continues the neural read operation.

[0190] It should be noted that, as used herein, the terms “over” and “on” both encompass “directly” (without intermediate material, element, or gap between them) and “indirectly to” (with intermediate material, element, or gap between them). Similarly, the term “adjacent” includes “directly adjacent” (without intermediate material, element, or gap between them) and “indirectly adjacent” (with intermediate material, element, or gap between them); “attached” includes “directly attached” (without intermediate material, element, or gap between them) and “indirectly attached to” (with intermediate material, element, or gap between them); and “electrically coupled” includes “directly electrically coupled” (without intermediate material or element between them electrically connecting the elements together) and “indirectly electrically coupled to” (with intermediate material or element between them electrically connecting the elements together). For example, forming an element "on top of a substrate" may include forming the element directly on the substrate without any intermediate materials / elements between them, and forming the element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. It is a system, An array of non-volatile memory cells arranged in rows and columns, An output block including a current-to-voltage converter for converting current from a column of the array into a voltage, and an analog-to-digital converter for converting the voltage into a digital output, The output block generates a first digital output during a first time period and a second digital output during a second time period. The current-voltage converter and the analog-digital converter include a plurality of column tag bits, Each column tag bit is associated with a column in the array, The current-voltage converter and the analog-digital converter are configured such that, for a given column in the array, output data is included in the digital output when the column tag bit associated with that column has a first value, and output data is not included in the digital output of that column when the column tag bit associated with that column has a second value, A first output register for storing the first digital output during the first time period and for outputting the stored first digital output during the second time period, A system comprising: a second output register for storing the second digital output during the second time period and for outputting the stored second digital output during the third time period.

2. The system according to claim 1, further comprising an accumulator for summing data received from one or more of the output block, the first output register, and the second output register.

3. The aforementioned cumulative counter is A shifter for receiving data from one or more of the output block, the first output register, and the second output register, and generating a first output, An adder for receiving the first output and the second output, summing them up, and generating a third output, The system according to claim 2, further comprising: an accumulator register for receiving and storing the third output and providing the third output to the adder as the second output.

4. It is a method, During the first period, The output block converts the current from a column of an array of non-volatile memory cells associated with a column tag bit having a first value into a first digital output, and does not convert the current from a column of the array associated with a column tag bit having a second value. The steps include storing the first digital output in a first output register, During the second period, The output block converts the current from a column of an array of non-volatile memory cells associated with a column tag bit having a first value into a second digital output, and does not convert the current from a column of the array associated with a column tag bit having a second value. The steps include storing the second digital output in the second output register, A method comprising the step of outputting the stored first digital output from the first output register.

5. During the third period, The output block converts the current from a column of an array of non-volatile memory cells associated with a column tag bit having a first value into a third digital output, and does not convert the current from a column of the array associated with a column tag bit having a second value. The steps include storing the third digital output in the first output register, The method according to claim 4, comprising the step of outputting the stored second digital output from the second output register.

6. The method according to claim 5, further comprising the step of summing the data received from one or more of the output block, the first output register, and the second output register by an accumulator.

7. The method according to claim 6, wherein the output block comprises a current-to-voltage converter for converting the current from the column of the array into a voltage, and an analog-to-digital converter for converting the voltage into a first digital output.

8. The aforementioned cumulative counter is A shifter for receiving data from one or more of the output block, the first output register, and the second output register, and generating a first output, An adder for receiving the first output and the second output, summing them up, and generating a third output, The method according to claim 6, further comprising: an accumulator register for receiving and storing the third output and providing the third output to the adder as a second output.

9. The method according to claim 6, wherein the output block comprises a current-to-voltage converter for converting the current from the column of the array into a voltage, and an analog-to-digital converter for converting the voltage into a first digital output.

10. The method according to claim 4, wherein the output block comprises a current-to-voltage converter for converting the current from the column of the array into a voltage, and an analog-to-digital converter for converting the voltage into a first digital output.

Images