Bonding layer and its manufacturing process

Abstract

A process for forming a semiconductor package is disclosed. The process includes providing a first substrate including a first dielectric layer. The process includes overlaying a first bonding layer including aluminum on a first surface of the first dielectric layer. The process includes providing a second substrate including a second dielectric layer. The process includes overlaying a second bonding layer including an alkoxysiloxide on a second surface of the second dielectric layer. The process includes forming a third bonding layer by bonding the first bonding layer and the second bonding layer to bond the first substrate to the second substrate.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims priority to U.S. Provisional Patent Application No. 63 / 240,312, filed September 2, 2021, entitled "Bonding Layer and Process of Making", the entire content of which is incorporated herein by reference for all purposes.

[0002] This disclosure relates to microelectronic devices including semiconductor devices, transistors, and integrated circuits, and also includes microfabrication methods.

Background Art

[0003] The semiconductor industry has grown rapidly, driven by the continuous improvement of the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density has been achieved by repeatedly reducing the minimum feature size to enable more components to be integrated in a given area. As the requirements for miniaturization, high speed, wide bandwidth, and reduction of power consumption and latency have increased in recent years, the need for smaller and more creative packaging technologies for semiconductor dies has been growing.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Wafer - to - wafer and chip - to - chip bonding is being carried out to continue the power - performance - area - cost (PPAC) scaling of complex circuits such as those implemented in system - on - chip (SOC). Many bonding techniques utilize oxide - to - oxide bonding adhesion to form an interconnected structure integrated through a hybrid bonding technique that forms interconnects at the bonding interface between two wafers or dies. However, in current technologies, typically, a permanent electrical connection is formed between each of the interconnected structures of the bonded wafers / dies. In other words, the existing interconnected structures of the bonded wafers / dies cannot switch between a connected state and a non - connected state.

Means for Solving the Problems

[0005] This disclosure provides various embodiments of interconnection structures for each of two wafers (or dies) that can be electrically connected to each other via the bonding of two selectively grown bonding layers. For example, the first wafer may include a first substrate on which a first dielectric layer (e.g., having an oxide surface) is formed, and the second wafer may include a second substrate on which a second dielectric layer (e.g., also having an oxide surface) is formed. A number of first interconnection structures are formed within the first dielectric layer, and a number of second interconnection structures are formed within the second dielectric layer. One of the oxide surfaces, but not both, is treated to selectively form a first bonding layer containing aluminum. The other oxide surface is treated to selectively form a second bonding layer containing silicon alkoxide. Based on the bonding of the first and second bonding layers, the first substrate can be bonded to the second substrate such that each of the first interconnection structures is in physical contact with a corresponding one of the second interconnection structures.

[0006] One aspect of this disclosure may be directed to a structure (e.g., a semiconductor package). The structure may include a first substrate, a second substrate, and a bonding layer containing AlSiO that bonds the first substrate to the second substrate.

[0007] The first substrate includes a first dielectric layer disposed on the first substrate and a first interconnection structure embedded in the first dielectric layer and having a first upper surface over which the first dielectric layer is not superimposed. The second substrate includes a second dielectric layer disposed on the second substrate and a second interconnection structure embedded in the second dielectric layer and having a second upper surface over which the second dielectric layer is not superimposed.

[0008] The first interconnection structure is in contact with the second interconnection structure with its first and second upper surfaces in contact with each other. The junction layer surrounds a portion of the combined sidewalls of the contacting first and second interconnection structures. The junction layer extends only between the first dielectric layer and the second dielectric layer. The first substrate contains a first device structure with the first dielectric layer superimposed, and the first device structure is electrically coupled to the first interconnection structure. The second substrate contains a second device structure with the second dielectric layer superimposed, and the second device structure is electrically coupled to the second interconnection structure. The thickness of the junction layer is less than approximately 4 nanometers.

[0009] Another aspect of this disclosure may be directed to a process for forming a semiconductor package. The process may include preparing a first substrate including a first dielectric layer. The process includes superimposing a first surface of the first dielectric layer with a first bonding layer containing aluminum. The process includes preparing a second substrate including a second dielectric layer. The process includes superimposing a second bonding layer containing an alkoxysiloxide onto a second surface of the second dielectric layer. The process includes forming a third bonding layer by bonding the first bonding layer and the second bonding layer in order to bond the first substrate to the second substrate.

[0010] The process further includes applying a gaseous or liquid phase of trimethylaluminum to the second surface in order to form a second bonding layer.

[0011] The process further includes applying a gaseous or liquid phase of dimethylaluminum isopropoxide to the second surface in order to form a second bonding layer.

[0012] The process further includes applying a gas or liquid phase of tris(tert-pentoxy)silicon(dimethylamide) to the second surface in order to form a second bonding layer.

[0013] The process further includes physically contacting the first bonding layer with the second bonding layer, and annealing at least the contacted first and second bonding layers at an elevated temperature to form a third bonding layer. The elevated temperature is less than approximately 500 degrees Celsius. By annealing at least the contacted first and second bonding layers, the aluminum in the first bonding layer catalyzes the rearrangement of the alkoxide ligands in the second bonding layer via a beta-desorption process.

[0014] The thickness of each of the first and second bonding layers is less than approximately 2 nanometers.

[0015] The first dielectric layer embeds a first interconnection structure on its first upper surface, which is not superimposed with the first dielectric layer or the first bonding layer, and the second dielectric layer embeds a second interconnection structure on its second upper surface, which is not superimposed with the second dielectric layer or the second bonding layer. Simultaneously with forming the third bonding layer, the process further includes physically bringing the first upper surface of the first interconnection structure into contact with the second upper surface of the second interconnection structure.

[0016] Further embodiments of this disclosure may be directed to a process for forming a semiconductor package. This process may include forming a first dielectric layer on a first substrate so that the first dielectric layer embeds a first interconnection structure, and superimposing a first junction layer containing aluminum on a first surface of the first dielectric layer; forming a second dielectric layer on a second substrate so that the second dielectric layer embeds a second interconnection structure; superimposing a second junction layer containing an alkoxysiloxide on a second surface of the second dielectric layer; and connecting the first interconnection structure to the second interconnection structure based on the coupling of the first and second junction layers.

[0017] Bonding the first bonding layer and the second bonding layer further includes physically contacting the first bonding layer with the second bonding layer, and annealing at least the contacted first and second bonding layers at an elevated temperature to form a third bonding layer containing AlSiO.

[0018] The temperature increase was less than approximately 500 degrees Celsius.

[0019] The above-mentioned and other embodiments and examples are described in detail below. The above-mentioned information and the following detailed descriptions include illustrated examples of various embodiments and examples and provide an overview or framework for understanding the nature and features of the embodiments and examples described in the claims. The drawings illustrate various embodiments and examples to enable further understanding and are incorporated into and form part of this specification. Multiple embodiments can be combined, and it will be readily apparent that features described in the context of one embodiment of the invention can be combined with a number of other embodiments. Multiple embodiments can be implemented in any convenient form. As used herein and in the claims, the singular forms "a," "an," and "the" include multiple references unless otherwise explicitly stated in the context.

[0020] Some non-limiting embodiments of this disclosure are described by example with reference to the accompanying drawings, which are schematic and not intended to be drawn to a fixed scale. Unless otherwise indicated as representing the background art, the drawings represent aspects of this disclosure. For clarity, not all elements are necessarily labeled in all drawings. [Brief explanation of the drawing]

[0021] [Figure 1] A flowchart shows an exemplary method for manufacturing a semiconductor package according to several embodiments. [Figure 2] These are cross-sectional views of semiconductor packages at various processing stages, manufactured by the method shown in Figure 1, according to several embodiments. [Figure 3] These are cross-sectional views of semiconductor packages at various processing stages, manufactured by the method shown in Figure 1, according to several embodiments. [Figure 4] These are cross-sectional views of semiconductor packages at various processing stages, manufactured by the method shown in Figure 1, according to several embodiments. [Figure 5]Cross-sectional views of semiconductor packages at various processing stages, manufactured by the method of FIG. 1, according to some embodiments. [Figure 6] Cross-sectional views of semiconductor packages at various processing stages, manufactured by the method of FIG. 1, according to some embodiments. [Figure 7] A flowchart of another exemplary method of manufacturing a semiconductor package, according to some embodiments, is shown.

BEST MODE FOR CARRYING OUT THE INVENTION

[0022] Hereinafter, referring to the exemplary embodiments depicted in the drawings, the embodiments will be described using specific terms. However, it should be understood that this does not limit the claims or the scope of the present disclosure in any way. Changes and further modifications to the features of the invention illustrated herein, as well as further applications of the principles of the subject matter illustrated herein that may occur to those skilled in the art who own the present disclosure, are intended to be included within the scope of the subject matter disclosed herein. The use of other alternative embodiments and / or other changes may be made without departing from the spirit or scope of the present disclosure. The exemplary embodiments described in the detailed description do not limit the subject matter presented.

[0023] According to one example, since the bonding layer is formed using chemical bonding technology, each substrate is treated with a precursor that can be selectively applied only to the dielectric region. During bonding, these precursors chemically react with each other to form a bonding / adhesive layer between the substrates. By using a chemically driven process for bond formation, the temperature can be reduced compared to some conventional bonding techniques. The use of chemical surface treatment can be selectively formed on an oxide or other insulating layer so as not to inhibit the metal-to-metal contact used for the wiring of the substrate.

[0024] According to one process, a carrier wafer (or die) having an oxide surface on a semiconductor can be bonded to a series of elements or a substrate wafer (or die) having an oxide surface on its surface. One oxide surface, rather than both the carrier oxide and the substrate oxide, is treated to form a thin layer containing Al on its surface. The other oxide surface is treated to form a thin surface layer containing Si alkoxide on its surface. As some examples, the thickness of the Al-containing layer (preferably Al oxide) may be 1 to 2 nanometers (nm), and the alkoxysiloxide may be about 2 nm or less because it self-saturates in 1 to 2 single layers. However, the thickness of each of these layers may be less than 1 nm. The substrate and the carrier are then bonded by annealing the substrate and carrier by physically bringing the oxide layers into contact under pressure. During the execution of the annealing step under pressure, the Al on the first oxide surface catalyzes the rearrangement of alkoxide ligands via a beta-desorption process to form Si-O-Si and Si-O-Al junctions in a process similar to sol-gel silica formation, which is well understood by those skilled in the art. This process can be carried out at relatively low temperatures, for example, below approximately 400-500°C.

[0025] Figure 1 shows a flowchart of an exemplary method 100 for forming a semiconductor package having at least two bonded (e.g., bonded) wafers, dies, or substrates based on two different bonding layers originally formed by stacking two substrates. Note that method 100 is merely an example and is not intended to limit the disclosure. Therefore, understand that additional operations may be performed before, during, and after method 100 in Figure 1, and that some other operations may only be briefly described herein.

[0026] In various embodiments, the operation of Method 100 may be associated with cross-sectional views of examples of semiconductor packages 200 at various processing stages, as shown in Figures 3-6, which will be described in more detail below. It should be understood that the semiconductor elements 200 shown in Figures 3-6 may include a number of other elements, such as inductors, fuses, capacitors, and coils, without departing from the scope of this disclosure.

[0027] Corresponding to operation 102 in Figure 1, Figure 2 is a cross-sectional view of a semiconductor package 200 in which a certain number of first interconnection structures 210A, 210B, 210C, and 210D are prepared on the first substrate 202 in one of various processing stages according to various embodiments.

[0028] The first substrate 202 is a semiconductor substrate such as a bulk semiconductor or an insulator-on-infrared (SOI) substrate, which may or may not be doped (for example, with a p-type or n-type dopant). The first substrate 202 may be a wafer such as a silicon wafer. Generally, an SOI substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulating layer is typically provided on a substrate which is a silicon substrate or a glass substrate. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used. In some embodiments, the semiconductor material of the first substrate 202 may include compound semiconductors containing silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors containing SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof.

[0029] In some embodiments, the first substrate 202 includes a number of element features / structures 203 (e.g., transistors, diodes, resistors, etc., not shown for clarity) formed along the (e.g., front) surface of the first substrate 202, and a number of interconnection structures (e.g., metal wires, metal vias, etc., not shown for clarity) formed on the element structures. The interconnection structures are configured to electrically connect the element structures to each other in order to form an integrated circuit capable of functioning as logic elements, memory elements, input / output elements, etc. These interconnection structures (e.g., formed of conductive materials such as Cu, Al, W, Ti, TiN, Ta, TaN, etc., or a number of layers or combinations thereof) may be embedded in one or more dielectric layers (e.g., formed of low dielectric materials such as SiO2), which may sometimes be referred to as, for example, metallization layers 204. In other words, each metallization layer 204 may include a number of metal wires and a number of metal vias embedded therein. Multiple such metallized layers 204 can be formed on the surface (e.g., the front side) of the first substrate 202.

[0030] Furthermore, a surface dielectric layer 206 is formed on top of the multiple metallized layers. In some embodiments, a number of first interconnection structures 210A to 210D are arranged on the surface dielectric layer 206, which is made of one or more low dielectric materials such as SiO2. The first interconnection structures 210A to 210D are formed using a damascene process, in which the blanket dielectric material of the surface dielectric layer 206 is deposited on top of a workpiece (e.g., the top metallized layer), and the dielectric material is patterned using lithography. The patterned dielectric material is filled with a conductive material, and any excess conductive material is removed from the top surface of the dielectric material using a chemical mechanical polishing (CMP) process, an etching process, or a combination thereof. In several other embodiments, the conductive material may be deposited and patterned using lithography, and the dielectric material of the surface dielectric layer 206 is formed on top of the conductive material using a subtractive etching process to form the first interconnection structures 210A to 210D. Next, excess dielectric material is removed from the first interconnection structures 210A-210D using a CMP process, an etching process, or a combination thereof.

[0031] Corresponding to operation 104 in Figure 1, Figure 3 is a cross-sectional view of a semiconductor package 200 in which the first bonding layer 302 is selectively formed on the surface dielectric layer 206 in one of various processing steps according to various embodiments.

[0032] Following the formation of the first interconnection structures 210A to 210D, at least one deposition process is performed to selectively form the first bonding layer 302 on top of the surface dielectric layer 206. As shown in the figure, the first bonding layer 302 may be formed only in the region where the surface dielectric layer 206 is present. In other words, the first bonding layer 302 may not be formed on any exposed surface of the first interconnection structures 210A to 210D. In various embodiments, the first bonding layer 302 containing an alkoxysiloxide is formed on the surface dielectric layer 206 using a gas-phase or liquid-phase surface treatment. For example, tris(tert-pentoxy)silicon(dimethylamide) or a similar compound / composite material can selectively react with OH groups on one or more surfaces of the surface dielectric layer 206 (e.g., portions of the surface of the surface dielectric layer 206 laterally adjacent to the exposed surfaces of the first interconnection structures 210A to 210D). In various embodiments, the first bonding layer 302 may have a thickness of about 2 nanometers or less due to self-saturation in one or two single layers.

[0033] Corresponding to operation 106 in Figure 1, Figure 4 is a cross-sectional view of a semiconductor package 200 in which a number of second interconnection structures 410A, 410B, 410C, and 410D are provided on the second substrate 402 in one of the various processing stages according to various embodiments.

[0034] The second substrate 402 is a semiconductor substrate such as a bulk semiconductor or an insulator-on-infrared (SOI) substrate, which may or may not be doped (for example, with a p-type or n-type dopant). The second substrate 402 may be a wafer such as a silicon wafer. Generally, an SOI substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulating layer is typically provided on a substrate which is a silicon substrate or a glass substrate. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used. In some embodiments, the semiconductor material of the second substrate 402 may include compound semiconductors containing silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors containing SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof.

[0035] In some embodiments, the second substrate 402 includes a number of element features / structures 403 (e.g., transistors, diodes, resistors, etc., not shown for clarity) formed along the (e.g., front) surface of the second substrate 402, and a number of interconnection structures (e.g., metal wires, metal vias, etc., not shown for clarity) formed on the element structures. The interconnection structures are configured to electrically connect the element structures to each other in order to form an integrated circuit capable of functioning as logic elements, memory elements, input / output elements, etc. These interconnection structures (e.g., formed from conductive materials such as Cu, Al, W, Ti, TiN, Ta, TaN, etc., or a number of layers or combinations thereof) may be embedded in one or more dielectric layers (e.g., formed from low dielectric materials such as SiO2), which may sometimes be referred to as, for example, metallization layers 404. In other words, each metallization layer 404 may include a number of metal wires and a number of metal vias embedded therein. Multiple such metallized layers 404 can be formed on the surface (e.g., the front side) of the second substrate 402.

[0036] Furthermore, a surface dielectric layer 406 is formed on top of the multiple metallized layers. In some embodiments, a number of second interconnection structures 410A to 410D are arranged on the surface dielectric layer 406, which is made of one or more low dielectric materials such as SiO2. The second interconnection structures 410A to 410D are formed using a damascene process, in which the blanket dielectric material of the surface dielectric layer 406 is deposited on top of a workpiece (e.g., the top metallized layer), and the dielectric material is patterned using lithography. The patterned dielectric material is filled with a conductive material, and any excess conductive material is removed from the top surface of the dielectric material using a chemical mechanical polishing (CMP) process, an etching process, or a combination thereof. In several other embodiments, the conductive material may be deposited and patterned using lithography, and the dielectric material of the surface dielectric layer 406 is formed on top of the conductive material using a subtractive etching process to form the second interconnection structures 410A to 410D. Next, excess dielectric material is removed from the second interconnection structures 410A-410D using a CMP process, an etching process, or a combination thereof.

[0037] Corresponding to operation 108 in Figure 1, Figure 5 is a cross-sectional view of a semiconductor package 200 in which a second bonding layer 502 is selectively formed on the surface dielectric layer 406 in one of various processing steps according to various embodiments.

[0038] Following the formation of the second interconnection structures 410A to 410D, at least one deposition process is performed to selectively form the second junction layer 502 on top of the surface dielectric layer 406. As shown in the figure, the second junction layer 502 may be formed only in the region where the surface dielectric layer 406 is present. In other words, the second junction layer 502 may not be formed on any exposed surface of the second interconnection structures 410A to 410D. In various embodiments, the second junction layer 502 containing aluminum (Al) is formed by treating one or more surfaces of the surface dielectric layer 406 (e.g., portions of the surface of the surface dielectric layer 406 laterally adjacent to the exposed surfaces of the second interconnection structures 410A to 410D) with a liquid-phase or gas-phase Al precursor. For example, trimethylaluminum or dimethylaluminum isopropoxide may be used as the precursor. In various embodiments, the thickness of the second junction layer 502 may be about 1 nanometer to about 2 nanometers.

[0039] Corresponding to operation 110 in Figure 1, Figure 6 is a cross-sectional view of a semiconductor package 200 in which a first substrate 202 (first semiconductor die) is bonded to a second substrate 402 (or second semiconductor die) in one of the various processing stages according to various embodiments.

[0040] In some embodiments, the first semiconductor die and the second semiconductor die are joined to each other using a hybrid bonding process by bonding the top surface of the first semiconductor die (e.g., the top surface of the first bonding layer 302) to the top surface of the second semiconductor die (e.g., the top surface of the second bonding layer 502). For example, the second semiconductor die is inverted, i.e., rotated 180 degrees, from the state shown in Figure 6. Next, the first interconnection structures 210A to 210D of the first semiconductor die are aligned with the second interconnection structures 410A to 410D of the second semiconductor die, respectively. The alignment of the first and second semiconductor dies may be achieved, for example, using optical sensing. The top surface of the portion of the first bonding layer 302 (higher than the top surface of the first interconnection structures 210A to 210D) is also aligned with the top surface of the portion of the second bonding layer 502 (higher than the top surface of the second interconnection structures 410A to 410D).

[0041] Following the alignment process of the first and second semiconductor dies, the first and second semiconductor dies are hybrid-bonded to each other by applying pressure and heat. In various embodiments, the Al of the second bonding layer 502 catalytically acts on the alkoxysiloxide of the first bonding layer 302 via beta-H desorption, thereby forming a third bonding layer 602 (e.g., containing AlSiO) sandwiched and bonded between the substrates. Since the first bonding layer 302 and the second bonding layer 502 are each formed to a thickness of less than 2 nanometers, the thickness of the third bonding layer 602 can be less than about 4 nm in some embodiments. The applied pressure may include a pressure of less than about 30 MPa, and the applied heat may include, as several examples, an annealing process at a temperature of about 100 to 500°C, but alternatively, other levels of pressure and heat may be used in the hybrid bonding process. The hybrid bonding process may be carried out in an N2 environment, an Ar environment, a He environment, an (approximately 4-10% H2) / (approximately 90-96% inert gas or N2) environment, an inert gas mixture environment, a combination thereof, or other types of environments.

[0042] In the hybrid bonding process, a third bonding layer 602 is formed between the surface dielectric layers 206 and 406, with the first interconnection structures 210A to 210D connected to the second interconnection structures 410A to 410D, respectively. That is, a certain number of non-metallic junctions are formed between portions of the surface dielectric layers 206 and 406 (via the third bonding layer 602), and a certain number of intermetallic junctions are formed between the first interconnection structures 210A to 210D and the second interconnection structures 410A to 410D, respectively. Part of the hybrid bonding process may include a fusion process to form non-metallic junctions, and part of the hybrid bonding process may include, for example, an inter-copper bonding process to form intermetallic junctions. The term "hybrid" refers to forming two different types of junctions using a single bonding process, rather than forming only one type of junction, as is done in other types of wafer-to-wafer bonding or die-to-die bonding processes.

[0043] Figure 7 shows a flowchart of another exemplary method 700 for forming a semiconductor package having at least two bonded (e.g., bonded) wafers, dies, or substrates based on two originally different bonding layers formed on two substrates. Note that method 700 is substantially similar to method 100 in Figure 1, except that method 700 may not include a hybrid bonding process. Therefore, the operation of method 700 in Figure 7 may be described only briefly below.

[0044] For example, Method 700 begins with operation 702, which prepares a first substrate. A first dielectric layer, formed of one or more low-dielectric materials such as SiO2, may be superimposed on the first substrate. Method 700 proceeds to operation 704, in which a first junction layer is formed superimposed on the first substrate (e.g., in contact with the first dielectric layer). The first junction layer, containing an alkoxysiloxide, is formed on the first dielectric layer using a gas-phase or liquid-phase surface treatment. For example, tris(tert-pentoxy)silicon(dimethylamide) or a similar compound / composite material may selectively react with the OH groups on the top surface of the first dielectric layer. Method 700 proceeds to operation 706, in which a second substrate is prepared. A second dielectric layer, formed of one or more low-dielectric materials such as SiO2, may also be superimposed on the second substrate. Method 700 proceeds to operation 708, in which a second junction layer is formed superimposed on the second substrate (e.g., in contact with the second dielectric layer). The second bonding layer containing aluminum (Al) is formed by treating the top surface of the second dielectric layer with a liquid-phase or gas-phase Al precursor. For example, trimethylaluminum or dimethylaluminum isopropoxide may be used as the precursor. Method 700 then proceeds to operation 710, which bonds the first substrate to the second substrate based on bonding the first bonding layer to the second bonding layer. The bonded bonding layer (e.g., a single bonding layer) may contain AlSiO according to various embodiments.

[0045] In the above description, specific details have been disclosed, such as the specific geometric shape of the processing system, and descriptions of the various elements and processes used therein. However, it will be understood that the technology of this specification may be implemented in multiple other embodiments that deviate from these specific details, and that such details are for illustrative purposes only and not limiting. Multiple embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for illustrative purposes, certain numbers, materials, and configurations have been indicated to enhance understanding. However, multiple embodiments can be implemented without such specific details. Elements having substantially the same functional structure are indicated by the same reference numeral, and thus all redundant descriptions can be omitted.

[0046] To aid in understanding various embodiments, various techniques have been described as multiple separate operations. The order of the descriptions should not be interpreted as meaning that these operations necessarily depend on their order. In fact, these operations do not have to be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed, and / or described operations may be omitted in additional embodiments.

[0047] As used herein, “substrate” or “substrate to be processed” generally refers to an object to be processed according to the present invention. A substrate may include any material portion or structure of an element, in particular a semiconductor or other electronic element, and may include, for example, a base substrate structure such as a semiconductor wafer or reticle, or a layer prepared on or superimposed on a base substrate structure such as a thin film. Accordingly, a substrate is not limited to any particular base structure, underlayer or upper layer, whether patterned or not, and includes any such layer or base structure, as well as any combination of layers and / or base structures. Certain types of substrates may be referred to herein, but only for illustrative purposes.

[0048] Those skilled in the art will understand that many modifications are possible to the operation of the techniques described above while achieving the same objectives of the present invention. Such modifications are intended to be within the scope of this disclosure. Thus, the above description of multiple embodiments of the present invention is not intended to be limiting. Rather, limitations of multiple embodiments of the present invention are set out in the following claims.

Claims

1. The first substrate and The second circuit board, A bonding layer containing AlSiO that bonds the first substrate to the second substrate, It has, The bonding layer has a structure having a thickness of less than approximately 4 nanometers.

2. The first substrate is, A first dielectric layer disposed on the first substrate described above, A first interconnection structure embedded in a first dielectric layer, wherein the first upper surface is not covered by the first dielectric layer, It has, The second substrate is A second dielectric layer disposed on the second substrate, A second interconnection structure embedded in a second dielectric layer, wherein the upper surface of the second interconnection structure is not covered by the second dielectric layer, The structure according to claim 1, having the following characteristics.

3. The structure according to claim 2, wherein the first interconnection structure is in contact with the second interconnection structure, and the upper surface of the first and the upper surface of the second are in contact with each other.

4. The structure according to claim 3, wherein the bonding layer surrounds a portion of the collective sidewall of the contacting first and second interconnection structures.

5. The structure according to claim 2, wherein the bonding layer extends only between the first dielectric layer and the second dielectric layer.

6. The first substrate includes a first element structure covered with the first dielectric layer, and the first element structure is electrically coupled to the first interconnection structure. The structure according to claim 2, wherein the second substrate includes a second element structure covered with the second dielectric layer, and the second element structure is electrically coupled to the second interconnection structure.

7. The steps include providing a first substrate including a first dielectric layer, The steps include: covering the first surface of the first dielectric layer with a first bonding layer containing aluminum; The steps include providing a second substrate including a second dielectric layer, The steps include: covering the second surface of the second dielectric layer with a second junction layer containing an alkoxysiloxide; The first bonding layer and the second bonding layer are combined to form a third bonding layer, and the first substrate is bonded to the second substrate. A process that has

8. The process according to claim 7, wherein the step of covering the first surface of the first dielectric layer with a first bonding layer containing aluminum comprises the step of providing a gas phase or liquid phase of trimethylaluminum as a precursor on the first surface to form the first bonding layer.

9. The process according to claim 7, wherein the step of covering the first surface of the first dielectric layer with a first bonding layer containing aluminum comprises the step of providing a gas or liquid phase of dimethylaluminum isopropoxide as a precursor on the first surface to form the first bonding layer.

10. The process according to claim 7, further comprising the step of providing a gas or liquid phase of tris(tert-pentoxy)silicon (dimethylamide) on the second surface to form the second bonding layer.

11. moreover, The steps include physically bringing the first bonding layer into contact with the second bonding layer, The steps include: heat-treating at least the first and second bonding layers that are in contact at an elevated temperature to form the third bonding layer; The process according to claim 7, wherein the process is further comprising:

12. The process according to claim 11, wherein the increased temperature is approximately 100°C or more and less than approximately 500°C.

13. The process according to claim 11, wherein by the step of heat-treating at least the contacted first and second bonding layers, the aluminum in the first bonding layer catalytically affects the rearrangement of the alkoxide ligand in the second bonding layer via a beta-desorption process.

14. The process according to claim 7, wherein each of the first bonding layer and the second bonding layer has a thickness less than about 2 nanometers (nm).

15. The first dielectric layer embeds the first interconnection structure, but the first upper surface of the first interconnection structure is not covered by the first dielectric layer or the first bonding layer. The process according to claim 7, wherein the second dielectric layer embeds the second interconnection structure, but the second upper surface of the second interconnection structure is not covered with the second dielectric layer or the second junction layer.

16. Furthermore, the process according to claim 15, comprising the step of bringing the first upper surface of the first interconnection structure into physical contact with the second upper surface of the second interconnection structure at the same time as the step of forming the third bonding layer.

17. The steps include forming a first dielectric layer on a first substrate, wherein the first dielectric layer embeds a first interconnection structure, The steps include: covering the first surface of the first dielectric layer with a first bonding layer containing aluminum; The steps include forming a second dielectric layer on a second substrate, wherein the second dielectric layer embeds a second interconnection structure, The steps include: covering the second surface of the second dielectric layer with a second junction layer containing an alkoxysiloxide; Based on the step of combining the first bonding layer and the second bonding layer, the first interconnection structure is connected to the second interconnection structure, A process that has

18. The step of combining the first bonding layer and the second bonding layer is further, The steps include physically bringing the first bonding layer into contact with the second bonding layer, At least the first and second bonding layers that are in contact are heat-treated at an elevated temperature. The steps include forming a third bonding layer containing AlSiO, The process according to claim 17, comprising:

19. The process according to claim 18, wherein the increased temperature is approximately 100°C or more and less than approximately 500°C.

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