User-configurable SLC memory size

Abstract

To provide devices and methods for, in storage systems with dynamic single-level cell (SLC) buffers, enabling a user to adjust sizes of the SLC buffers at runtime without interfering with operation of a file system.SOLUTION: An electronic storage system has: one or more substrates; and a controller coupled to the one or more substrates and including logic. The logic is configured to: control 21 access to a NAND-based storage medium 12 that includes a first cell region with a first number of levels and a second region with a second number of levels that is different from the first number of levels; determine 22 logical block address (LBA) locations that correspond to a user-configurable capacity placeholder; and adjust 23 respective sizes of the first cell region and the second cell region at runtime based on the LBA locations.SELECTED DRAWING: Figure 3

Description

Background Art

[0001] [Cross-reference to Related Applications] This application claims the benefit of U.S. Patent Application No. 17 / 231,893, filed Apr. 15, 2021, which is hereby incorporated by reference in its entirety.

[0002] A single-level cell (SLC) buffer may include a NAND flash memory (NAND memory) composed of a plurality of cells, and each cell includes 1-bit of data. A triple-level cell (TLC) memory may include a NAND memory composed of a plurality of cells, and each cell includes 3 bits of data. A quad-level cell (QLC) memory may include a NAND memory composed of a plurality of cells, and each cell includes 4 bits of data. The number of bits per cell may generally depend on how many distinct voltage levels are used during a programming operation associated with writing to the cell, reading from the cell, and / or erasing the cell. Thus, in the case of TLC memory, to support 3 bits per cell, 8 voltage levels are used to distinguish 8 possible combinations of 1s and 0s (e.g., 000, 001, 010, 011, 100, 101, 110, 111) that can be written to the cell.

[0003] Some storage systems include techniques for determining a programmable erasure rate associated with a storage device and converting a portion of an SLC region within the storage device to a multi-level cell (MLC) region according to the programmable erasure rate. Examples of MLCs may include TLC (e.g., 3-bit or 8-level MLC), QLC (e.g., 4-bit or 16-level MLC), etc. For example, the amount of the portion converted to the MLC region gradually changes according to the percentage capacity satisfied in the storage device.

[0004] Some storage systems may include dynamic SLC memory controller technology. For example, the controller can determine the amount of active data in the dynamic portion of the SLC area at runtime and adjust the size of the dynamic portion of the SLC area at runtime based on the determined amount of active data in the dynamic portion of the SLC area.

[0005] Some storage systems may include multi-level memory repurposing techniques. For example, a memory controller can reprovision persistent storage media in response to requests to change the configuration of the persistent storage media. [Brief explanation of the drawing]

[0006] The subject matter described herein is illustrated as an example, not as an extension of the attached drawings. For the sake of brevity and clarity, the elements depicted in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Furthermore, where appropriate, reference numerals are repeated throughout the drawings to indicate corresponding or similar elements. The drawings are as follows:

[0007] [Figure 1] This is a block diagram relating to an example of an electronic storage system according to one embodiment.

[0008] [Figure 2] This is a block diagram relating to an example of an electronic device according to one embodiment.

[0009] [Figure 3] This is a flowchart illustrating an example of a storage control method according to one embodiment.

[0010] [Figure 4] This is an explanatory diagram illustrating an example of a process flow according to one embodiment.

[0011] [Figure 5] This is an explanatory diagram illustrating another example of a process flow according to one embodiment.

[0012] [Figure 6] This is a block diagram relating to an example of a storage system according to one embodiment.

[0013] [Figure 7] This is a block diagram relating to another example of a computing system according to one embodiment.

[0014] [Figure 8] This is a block diagram relating to an example of a solid-state drive (SSD) device according to one embodiment. [Modes for carrying out the invention]

[0015] Referring to the accompanying drawings, one or more embodiments or implementations are described herein. Specific configurations and arrangements are described, but it should be understood that these are for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of this specification. Those skilled in the art will also see that the methods and / or arrangements described herein may be used in a variety of other systems and applications not described herein.

[0016] The following description includes various implementation examples that may be explicitly shown in architectures such as a system-on-a-chip (SoC) architecture, but the implementation of the methods and / or arrangements described herein is not limited to any particular architecture and / or computing system, and may be implemented in any architecture and / or computing system for similar purposes. For example, the methods and / or arrangements described herein may be implemented in various architectures using multiple integrated circuit (IC) chips and / or packages, and / or in various computing devices and / or consumer electronic (CE) devices such as set-top boxes and smartphones. Furthermore, the following description may include numerous specific details, such as examples of logic implementations, types and interrelationships of system components, and choices of logic partitioning / integration, but the claimed subject matter can be implemented without such specific details. In other examples, some subject matter, such as control structures and complete software instruction sequences, may not be shown in detail in order to avoid obscuring the subject matter disclosed herein.

[0017] The subject matter disclosed herein may be implemented in hardware, firmware, software, or any combination thereof. The subject matter disclosed herein may also be implemented as instructions stored in a machine-readable medium which one or more processors can read and execute. A machine-readable medium may include any medium and / or mechanism for storing or transmitting information in a format readable by a machine (e.g., a computing device). For example, machine-readable media may include read-only memory (ROM); random-access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; propagating signals in electrical, optical, acoustic, or other forms (e.g., carrier waves, infrared signals, digital signals, etc.), and others.

[0018] References in this specification such as “one implementation example,” “one implementation example,” and “an exemplary implementation example” indicate that the implementation example described may include certain features, structures, or characteristics, but not all embodiments necessarily include such specific features, structures, or characteristics. Furthermore, such language does not necessarily refer to the same implementation example. Moreover, if a certain feature, structure, or characteristic is described in relation to one embodiment, it is stated that such features, structures, or characteristics may be obtained in relation to other implementation examples, whether or not they are explicitly described herein, as being within the knowledge of those skilled in the art.

[0019] Various embodiments described herein may include memory components and / or interfaces to memory components. Such memory components may include volatile and / or non-volatile (NV) memory. Volatile memory may be a storage medium that requires power to maintain the state of data stored in it. Non-limiting examples of volatile memory may include various types of RAM, such as dynamic RAM (DRAM) or static RAM (SRAM). Certain types of DRAM may be used in memory modules, such as synchronous dynamic RAM (SDRAM). NV memory (NVM) may be a storage medium that does not require power to maintain the state of data stored in it. In one embodiment, a memory device may include a block-addressable memory device, for example, one based on NAND technology. In one embodiment, a memory device may include, or may not include, a memory device using NAND flash memory or other memory with multiple threshold levels. A memory device may refer to the die itself and / or a packaged memory product.

[0020] Referring to Figure 1, one embodiment of the electronic storage system 10 may include a NAND-based storage medium 12 containing a first cell area 12a having a first number of levels and a second area 12b having a second number of levels different from the first number, and a controller 11 communicatively connected to the NAND-based storage medium 12. The controller 11 may include logic 13 which determines logical block address (LBA) locations corresponding to user-configurable capacity placeholders and adjusts the sizes of the first cell area 12a and the second cell area 12b at runtime based on the LBA locations. In some embodiments, the logic 13 may further be configured to enable the user-configuration of the size of the first cell area 12a in response to a command. For example, the logic 13 may be configured to reserve a range of LBAs to manage capacity conversion between the first cell area 12a and the second cell area 12b.

[0021] In some embodiments, logic 13 may be further configured to store user data in the NAND-based storage medium 12 when this function is enabled. For example, logic 13 may be configured to convert blocks in the second cell area 12b to blocks in the first cell area 12a and move the data from the second cell area 12b to the converted blocks in the first cell area 12a. In any of these embodiments, the controller 11 and the NAND-based storage medium 12 may be incorporated into a solid-state drive (SSD).

[0022] Embodiments regarding each of the system components such as the above-described controller 11, NAND-based storage medium 12, logic 13, etc. may be implemented in hardware, software, or any suitable combination thereof. For example, hardware implementation examples may include configurable logic such as a programmable logic array (PLA), a field programmable gate array (FPGA), a complex programmable logic device (CPLD) by way of example, or fixed-function logic hardware using circuit technologies such as an application specific integrated circuit (ASIC), complementary metal oxide semiconductor (CMOS), or transistor-transistor logic (TTL) technology by way of example, or any combination thereof. Embodiments of the controller 11 may include a general-purpose controller, a special-purpose controller, a memory controller, a storage controller, a microcontroller, a general-purpose processor, a special-purpose processor, a central processing unit (CPU), an execution unit, and the like. In some embodiments, the NAND-based storage medium 12, the logic 13, and / or other system memories may be disposed within various components including the controller 11, or may be disposed in the same location (e.g., on the same die) as it.

[0023] Alternatively, or additionally, all or part of these components may be implemented in one or more modules as a set of logic instructions stored in a machine-readable or computer-readable storage medium (e.g., RAM, ROM, programmable ROM (PROM), firmware, flash memory, etc.) executed by a processor or computing device. For example, computer program code for performing the operations of the components may be written in any combination of one or more programming languages ​​applicable to the operating system (OS), including object-oriented programming languages ​​such as Python®, Perl, Java®, Smalltalk®, C++, C#, and traditional procedural programming languages ​​such as the C programming language or similar languages. For example, a NAND-based storage medium 12, another NAND-based storage medium, or another system memory can store an instruction set, which, when executed by the controller 11, causes the system 10 to implement one or more components, features, or aspects of the system 10 (for example, logic 13, which determines LBA locations corresponding to user-configurable capacity placeholders, and adjusts the sizes of the first cell area 12a and the second cell area 12b at runtime based on the LBA locations).

[0024] Referring now to FIG. 2, one embodiment of the electronic device 14 may include one or more substrates 15 and a controller 16 coupled to the one or more substrates 15. The controller 16 may include logic 17 that controls access to a NAND-based storage medium including a first cell region having a first level number and a second region having a second level number different from the first level number, determines LBA positions corresponding to user-configurable capacity holders, and adjusts the respective sizes of the first cell region and the second cell region at runtime based on the LBA positions. In some embodiments, the logic 17 may further be configured to enable a function of user-configuring the size of the first cell region in response to a command. For example, the logic 17 may be configured to reserve a range of LBAs to manage capacity conversion between the first cell region and the second cell region.

[0025] In some embodiments, the logic 17 may further be configured to store user data in the NAND-based storage medium when this function is enabled. For example, the logic 17 may be configured to convert blocks of the second cell region into blocks of the first cell region and move data of the second cell region to the converted blocks of the first cell region. In any of the embodiments herein, the controller 16 and the NAND-based storage medium may be incorporated into an SSD.

[0026] Embodiments of logic 17 may be implemented in systems, apparatus, computers, devices, etc., as described herein. More specifically, hardware implementations of logic 17 may include configurable logic such as PLA, FPGA, CPLD, etc., or fixed-function logic hardware using circuit technology such as ASIC, CMOS, or TTL technology, etc., or any combination thereof. Alternatively or additionally, logic 17 may be implemented in one or more modules as a set of logic instructions executed by a processor or computing device, stored in a machine-readable or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc. For example, computer program code for performing the operation of the component may be written in any combination of one or more programming languages ​​applicable to the OS, including object-oriented programming languages ​​such as Python®, Perl, Java®, Smalltalk®, C++, C#, and conventional procedural programming languages ​​such as the C programming language or similar programming languages.

[0027] For example, logic 17 may be mounted on a semiconductor device, which may include one or more substrates 15, to which logic 17 is coupled. In some embodiments, logic 17 may be at least partially mounted on a semiconductor substrate (e.g., silicon, sapphire, gallium arsenide, etc.) in one or more of the configurable logic and fixed-function hardware logic. For example, logic 17 may include a transistor array and / or other integrated circuit components coupled to the substrate 15, having channel regions of transistors arranged within the substrate 15. The interface between logic 17 and the substrate 15 does not have to be a step junction. Logic 17 may be considered to include an epitaxial layer grown on the initial wafer of the substrate 15.

[0028] Referring now to Figure 3, one embodiment of the storage control method 20 may include the steps of: controlling access to a NAND-based storage medium in block 21, which includes a first cell area having a first number of levels and a second area having a second number of levels different from the first number; determining an LBA location in block 22 that corresponds to a user-configurable capacity placeholder; and adjusting the sizes of the first cell area and the second cell area at runtime based on the LBA location in block 23. In some embodiments of method 20, the step of enabling a user-configurable function for the size of the first cell area in response to a command in block 24 may further include. For example, method 20 may include the step of reserving a range of LBAs in block 25 to manage capacity conversion between the first cell area and the second cell area.

[0029] In some embodiments, Method 20 may further include the step of saving user data to a NAND-based storage medium in block 26 when this function is enabled. For example, Method 20 may include the steps of converting blocks of a second cell area to blocks of a first cell area in block 27, and moving data from the second cell area to the converted blocks of the first cell area in block 28. In any of these embodiments, the NAND-based storage medium may be incorporated into an SSD in block 29.

[0030] Embodiments of Method 20 may be implemented, for example, in systems, apparatus, computers, devices, etc., as described herein. More specifically, hardware implementation examples of Method 20 may include configurable logic such as PLA, FPGA, CPLD, or coarse-grained reconfigurable fabric (CGRA), or fixed-function logic hardware using circuit technology such as ASIC, CMOS, or TTL technology, or any combination thereof. Alternatively or additionally, Method 20 may be implemented in one or more modules as a set of logic instructions executed by a processor or computing device, stored in a machine-readable or computer-readable storage medium such as RAM, ROM, PROM, firmware, or flash memory. For example, computer program code for performing the operation of the components may be written in any combination of one or more OS-applicable / appropriate programming languages, including object-oriented programming languages ​​such as Python®, Perl, Java®, Smalltalk®, C++, C#, and conventional procedural programming languages ​​such as the C programming language or similar programming languages.

[0031] For example, Method 20 may be implemented in a computer-readable medium as described in relation to Examples 22-28 below. Embodiments or parts of Method 20 may be implemented in firmware, an application (e.g., through an application programming interface (API)), or driver software running in an operating system (OS). Furthermore, logic instructions may include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, state setting data, configuration data for integrated circuits, and state information that personalizes other structural components specific to electronic circuits and / or hardware (e.g., host processor, central processing unit / CPU, microcontroller, etc.).

[0032] In some embodiments, it is advantageous to provide a technique that enables user-configurable SLC buffer / cache size while storing user data for NAND storage devices. Typically, when provisioning a NAND storage device with multiple bits per cell, an SLC cache or buffer may be provisioned to improve device performance. However, since each cell dedicated to the SLC buffer has only one bit, the overall drive capacity is reduced. File systems and partition systems arrange a portion of their data structure based on the drive capacity. Because the overall device capacity is determined based on the size of the SLC buffer, users cannot resize the amount of SLC to their own needs without risking data loss and file system corruption. User choices regarding the trade-off between performance (e.g., SLC size) and overall capacity (e.g., QLC size, TLC size, etc.) can be made at the time of provisioning. To change the trade-off chosen by the user, the contents of the drive must be erased.

[0033] In storage systems with dynamic SLC buffers, the size of the SLC buffer can be adjusted at runtime. However, this adjustment is not user-configurable. Users cannot choose how the drive trades performance and capacity, nor can they guarantee a certain amount of SLC on the drive. In storage systems with multi-level memory repurposing techniques (e.g., just-in-time block repurposing), the storage medium may be reconfigurable based on user requests, but this generally requires taking the drive offline and changing the drive's reported capacity, which disrupts file system operation. Some embodiments are advantageous because they provide techniques to overcome one or more of the aforementioned problems.

[0034] In some embodiments, a host software component, such as a storage driver, can be used to create a file in the storage device's file system. The created file will not contain any data. After the created file and its associated LBA location are communicated to the SSD firmware, the SSD can increase its SLC buffer by a corresponding amount based on the NAND erase block (EB) characteristics of the individual device. In SLC-QLC devices, for example, this increase would correspond to a 4:1 ratio.

[0035] It is advantageous for users to have control over the configurability of SLC. For example, if a user has a QLC-based SSD and is aware that the application will only use less than a quarter of the SSD's capacity, in some embodiments, the user can configure the storage system to be 100% SLC without losing any user data already on the drive. Later, if the user needs more capacity, they can, as needed, reverse this operation or provision a drive with a different ratio, again without losing or corrupting any data currently on the device.

[0036] Reclaimed SLC can be used for any useful storage needs. For example, one application may utilize the freed SLC for an intelligent caching solution (not just as a write buffer). It is advantageous that SSD devices can ship with the ability to utilize their maximum capacity (e.g., the corresponding preferred cost / gigabyte (GB) value). Users can readjust the performance-to-capacity trade-off at runtime as needed while storing user data during deployment.

[0037] In some embodiments, host software drivers and file systems can be used to provide a mechanism that allows users to make seamless trade-offs between capacity and performance. For example, capacity placeholders or padding files can be created to make the LBA range of a particular SSD inaccessible to the rest of the system (e.g., the OS, other applications, etc.) and instead reserve them for firmware (FW) management of capacity conversion between QLC and SLC, thereby achieving the desired trade-off. For example, since SLC access offers better performance than QLC, the user may choose the trade-off of increasing SLC capacity.

[0038] In some embodiments, a padding file is created if the corresponding function is enabled. For example, the LBA range may be sent to the SSD via a vendor-specific command, and the padding file is then opened for reserved exclusive access by some daemon service each time the OS is initialized. After the SSD's firmware receives the LBA range and determines how many new SLC blocks need to be created, the firmware creates additional SLCs by moving data from the current QLC blocks to the new SLC blocks as needed. The padding file will exist if the corresponding function is enabled.

[0039] Referring to Figure 4, one embodiment of process flow 40 shows how a user can reconfigure a 1 terabyte (TB) drive. Before enabling the user-configurable SLC capacity feature, the entire 1 TB of the drive may be available to the OS and file system. After the user enables this feature and requests the maximum SLC capacity, 100% of the drive is converted to SLC storage. For a QLC drive, this results in 256 GB of SLC capacity (e.g., a 4:1 capacity reduction from 1024 GB of a drive converted from QLC to SLC), with much better read and write access performance. A 768 GB padding file is created as a capacity placeholder, occupying the remaining portion of the original 1 TB. The padding file is advantageous because it makes the drive appear to the OS and file system as if the SSD had not changed. Even though the drive has been reconfigured, hardware reprovisioning is not required to account for the physical change in capacity, and the system can continue to function normally.

[0040] Referring to Figure 5, one embodiment of process flow 50 shows another example of how a user can reconfigure a 1TB drive. Before enabling the user-configurable SLC capacity feature, the entire 1TB of the drive may be available to the OS and filesystem. After the user enables this feature and requests 50% SLC capacity, 50% of the drive is converted to SLC storage. For a QLC drive, this results in 128GB of SLC capacity (e.g., a 4:1 capacity reduction from the original 512GB of the drive converted from QLC to SLC), with much better read and write access performance. A 384GB padding file is created as a capacity placeholder to occupy the remaining portion of the original 512GB that has been converted to SLC. The padding file is advantageous because it makes the drive appear to the OS and filesystem as if the SSD had not changed. Even though the drive has been reconfigured, hardware reprovisioning is not required to account for the physical change in capacity, and the system can continue to operate normally.

[0041] In some embodiments, the actual division of a specified ratio may be set by the user via a graphical user interface (GUI). For example, this interface may allow querying specific NAND cell characteristics of the drive. This interface may also determine and communicate capacity trade-offs to the user. As illustrated in Figures 4 and 5, in QLC SSDs, this function requires reserving 4 bits for each bit of reclaimed SLC. In NAND SSDs that support multiple formats in addition to SLC and QLC, embodiments of this function may be configured to perform conversions between other supported formats (e.g., 2-level cell (MLC), TLC, etc.).

[0042] Referring to Figure 6, one embodiment of the storage system 60 may include a file system with multiple files. The file system creates files that are converted to LBA locations. The LBA locations are then converted to NAND cell locations by the SSD's firmware using a logical-to-physical (L2P) table. The SSD may include some SLC that is used as a buffer / cache by the SSD's firmware. In some embodiments, when user-configurable features are enabled, the SSD's firmware creates locations in L2P that do not map to physical NAND locations (e.g., identified as reclaimed LBAs in Figure 6). Since these locations are assigned to padding files, the SSD's firmware is aware that these locations cannot be mapped to valid data. Therefore, the SSD's firmware can create more SLC (e.g., identified as reclaimed SLCs in Figure 6) to improve the performance of the storage device. For example, if the SSD has enough QLC blocks for 1TB, but 512GB of that space is reserved when the user enables user-configurable features, the SSD's firmware can safely use the equivalent of that 512GB of QLC capacity for 128GB of SLC blocks. In these embodiments, the SSD's L2P indirect table is used to indicate the location of the padding file, so padding file fragmentation is not a problem.

[0043] In some embodiments, when using a padding file as a capacity placeholder to reserve space in this way, there is a certain degree of risk that the LBA locations assigned to the padding file will be changed. In some embodiments, changes to the LBA locations assigned to the padding can be detected by the SSD's firmware itself via a fail-safe function, which can automatically roll back the function. In some embodiments, the fail-safe function refers to detecting a write that has occurred to a reserved LBA and then correcting the mapping back of SLC to QLC. If the SSD's firmware receives a write (or, for example, TRIM) request to any LBA within the reserved LBA range, the SSD's firmware can immediately cancel this function internally (for example, by disabling the user-configured function), convert any valid SLC data within that range to QLC, and revert to a NAND configuration that does not use any reclaimed SLC (for example, the configuration before the user enabled this function, or the original configuration). Note that since the SSD can return zero (for example, as the SSD does when reading a trimmed location), it is possible to safely issue reads to the padding file on the host system.

[0044] For example, if a file system is mounted as a data drive on an OS that does not recognize this feature, and the firmware (FW) erases or overwrites LBAs that were previously reserved, write requests to LBAs within the reserved range may occur. Another possibility that triggers the failsafe function is file system corruption. The process of reversing this function may involve the SSD's NAND garbage collection process, which converts SLC back to QLC, resulting in a temporary performance degradation but no data loss. For example, this conversion process can be carried out by utilizing the appropriate operation codes (e.g., opcodes) or function sets that can make the entire NAND die into the desired format (e.g., SLC, MLC, TLC, QLC, etc.). The SSD's FW identifies the target block and target format. The SSD's FW first converts the NAND die to the target format and issues specific operations (e.g., erase, program, or read) to the target block. The conversion process can be performed block by block, and the SSD's FW maintains the target format for each block.

[0045] In addition to enabling and disabling user-configured features, the relevant host software can take on the role of minimizing the situations that trigger failsafes and recovering from them when they do occur. To facilitate this, padding files should be assigned to the most restrictive filesystem access properties to prevent the most problematic programs or users from triggering failsafes. Host filesystem features that may interfere with user-configured features, such as filesystem compression, should be disabled, and problematic operations such as writing, moving, creating, or deleting files should be caught and handled by appropriate host filesystem filters.

[0046] For the system to function correctly, the LBA location of the padding file in the file system must match the one specified as reclaimed in the SSD firmware's L2P. To ensure this, at power-up, the host software manually requests this information from the SSD and checks for any discrepancies. If the SSD firmware detects a mismatch, it notifies the host driver.

[0047] Based on the mismatch notification, the host driver can either completely disable this feature or attempt to correct the mismatch. Correction of the mismatch is only possible if there is still sufficient free space to create a padding file of the desired size. For example, on a system without a protective host SW for this feature, if a user deletes a 512GB padding file and then fills the SSD to less than 512GB of free space, it will not be possible to create a 512GB padding file. In this case, the feature will simply be disabled.

[0048] Some embodiments do not require pre-OS or Unified Extensible Firmware Interface (UEFI) driver components because there is no need to access padding files before the OS boots up and starts operating (for example, host SW components for user-configurable functions are not needed until OS initialization).

[0049] In alternative embodiments, a separate padding partition may be used instead of a padding file as a capacity placeholder for the claimed portion of the SSD's capacity. Using a padding partition as a capacity placeholder may be similar to using a padding file, except when the user wants to consume capacity to create more SLCs. In this situation, the original data partition may have its files spread across a larger LBA space, and there may not be enough free space at the beginning or end of the partition to sufficiently shrink the data partition. Certain files, such as paging files, may not even be able to be moved during runtime. Therefore, an "offline" environment, such as UEFI, may be required to move these types of protected files. In either embodiment, the data layout of the SSD's LBA space is used to reserve space that the SSD can recognize as unused and unmapped, so that it can allocate SLCs faster than those configured by the user.

[0050] The technologies described herein may be provided to a variety of computing systems, including non-portable computing devices such as desktops, workstations, servers, and rack systems; portable computing devices such as smartphones, tablets, ultra-portable personal computers (UMPCs), laptop computers, Ultrabook computing devices, smartwatches, smart glasses, and smart bracelets; and / or client / edge devices such as Internet of Things (IoT) devices (e.g., sensors, cameras, etc.).

[0051] Referring here to Figure 7, one embodiment of the computing system 100 may include one or more processors 102-1 to 102-N (hereinafter generally referred to as “multiple processors 102” or “processor 102”). The multiple processors 102 can communicate with each other via an interconnection or bus 104. Each processor 102 may include various components, and for clarity only some of them will be described with reference to processor 102-1. Thus, each of the remaining processors 102-2 to 102-N may include the same or similar components as described with reference to processor 102-1.

[0052] In some embodiments, the processor 102-1 may include one or more processor cores 106-1 to 106-M (referred to here as “multiple cores 106” or more commonly as “core 106”), a cache 108 (which may be a shared cache or a private cache in various embodiments), and / or a router 110. The processor cores 106 may be implemented on a single integrated circuit (IC) chip. Furthermore, the chip may include one or more shared caches and / or private caches (such as cache 108), a bus or interconnect (such as bus or interconnect 112), logic 170, a memory controller, or other components.

[0053] In some embodiments, routers 110 may be used to communicate between various components of the processor 102-1 and / or the system 100. Furthermore, the processor 102-1 may include more than one router 110. In addition, multiple routers 110 may communicate to enable data routing between various components inside or outside the processor 102-1.

[0054] Cache 108 may store data (e.g., instructions) used by one or more components of processor 102-1 (such as core 106). For example, cache 108 may locally cache data stored in memory 114 for faster access by components of processor 102. As shown in Figure 7, memory 114 can communicate with processor 102 via interconnect 104. In some embodiments, cache 108 (which may be shared) may have various levels; for example, cache 108 may be an intermediate-level cache and / or a last-level cache (LLC). Also, each of core 106 may include a level 1 (L1) cache (116-1) (commonly referred to here as "L1 cache 116"). Various components of processor 102-1 can communicate directly with cache 108 through a bus (e.g., bus 112) and / or a memory controller or hub.

[0055] As shown in Figure 7, the memory 114 may be connected to other components of the system 100 through a memory controller 120. The memory 114 may include volatile memory and may be referred to without distinction as main memory or system memory. Although the memory controller 120 is shown as being connected between the interconnect 104 and the memory 114, the memory controller 120 may be located elsewhere in the system 100. For example, in some embodiments, the memory controller 120 or a part of it may be located on one of the multiple processors 102.

[0056] System 100 can communicate with other devices / systems / networks via a network interface 128 (for example, communicating with a computer network and / or cloud 129 via a wired or wireless interface). For example, the network interface 128 may include an antenna (not shown) for communicating wirelessly with the network / cloud 129 (for example, via an IEEE 802.11 interface (including IEEE 802.11a / b / g / n / ac, etc.), a cellular interface, 3G, 4G, LTE, Bluetooth®, etc.).

[0057] System 100 may also include storage devices such as SSDs 130 connected to interconnect 104 via SSD controller logic 125. Thus, logic 125 can control access to SSDs 130 by various components of System 100. Furthermore, even though Figure 7 shows logic 125 directly connected to interconnect 104, logic 125 can alternatively communicate with one or more other components of System 100 via storage buses / interconnections (e.g., SATA (Serial Advanced Technology Attachment) bus, Peripheral Component Interconnect (PCI) (or PCI Express (PCIe) interface), NVM Express (NVMe), etc.) (for example, if the storage bus is connected to interconnect 104 via some other logic such as a bus bridge, chipset, etc.). Furthermore, the logic 125 may be incorporated into memory controller logic (for example, as described with reference to Figure 8), or it may be provided on the same integrated circuit (IC) device (for example, on the same circuit board device as the SSD 130, or in the same enclosure as the SSD 130) in various embodiments.

[0058] Furthermore, the logic 125 and / or SSD 130 may be coupled to one or more sensors (not shown) to receive information (e.g., in the form of one or more bits or signals) indicating the status or value of a value detected by one or more sensors. These sensors may be located in close proximity to components of system 100 (or other computing systems described herein), including the core 106, interconnect 104 or 112, components outside the processor 102, SSD 130, SSD bus, SATA bus, logic 125, logic 160, logic 170, etc., to detect variations in various factors affecting the power / thermal behavior of the system / platform, such as temperature, operating frequency, operating voltage, power consumption, and / or inter-core communication activity.

[0059] Figure 8 illustrates a block diagram of various components of the SSD 130 according to one embodiment. As shown in Figure 8, the logic 160 may be located in various places, such as inside the SSD 130 or the controller 382, ​​and may include similar techniques to those described in relation to Figure 7. The SSD 130 includes a controller 382 (and further including one or more processor cores or processors 384 and memory controller logic 386), a cache 138, RAM 388, firmware storage 390, and one or more memory devices 392-1 to 392-N (collectively memory 392, which may include NAND media or other types of non-volatile memory). The memory 392 is coupled to the memory controller logic 386 via one or more memory channels or buses. The SSD 130 also communicates with the logic 125 via an interface (such as SATA, SAS, PCIe, NVMe, etc.). The processor 384 and / or controller 382 can compress / decompress data written to or read from memory devices 392-1 to 392-N.

[0060] As illustrated in Figures 7 and 8, the SSD 130 may include logic 160, which may be located in the same enclosure as the SSD 130 and / or fully integrated on the printed circuit board (PCB) of the SSD 130. The system 100 may further include logic 170 located outside the SSD 130. One or more of the features / aspects / operations described with reference to Figures 1 to 6 may be performed by one or more of the components in Figures 7 and / or 8. Also, one or more of the features / aspects / operations in Figures 1 to 6 may be programmed into the firmware 390. Furthermore, the SSD controller logic 125 may also include logic 160. Advantageously, logic 160 and / or logic 170 may include techniques for implementing one or more embodiments of any of the systems 10 (Figure 1), apparatus 14 (Figure 2), method 20 (Figure 3), process flow 40 (Figure 4), process flow 50 (Figure 5), storage system 60 (Figure 6), and / or functions described herein. For example, logic 170 may include techniques for implementing embodiments relating to host devices / computer systems / agents of various embodiments described herein, and logic 160 may include techniques for implementing embodiments relating to storage devices of various embodiments described herein.

[0061] For example, the memory 392 may include a NAND-based storage medium containing a first cell region (e.g., SLC) having a first number of levels, and a second region (e.g., QLC) having a second number of levels different from the first number. Logic 160 in the controller 382 may be configured to determine LBA locations corresponding to user-configurable capacity placeholders (e.g., padding files, padding partitions, etc.) and to adjust the sizes of the first and second cell regions at runtime based on the LBA locations. In some embodiments, logic 160 may further be configured to enable user-configuration of the size of the first cell region in response to a command (e.g., a vendor-specific command). For example, logic 160 may be configured to reserve a range of LBAs to manage capacity conversion between the first and second cell regions.

[0062] In some embodiments, logic 160 may be further configured to store user data in memory 392 when this function is enabled. For example, logic 160 may be configured to convert blocks in a second cell region to blocks in a first cell region and move data from the second cell region to the converted blocks in the first cell region.

[0063] In other embodiments, the SSD 130 may be replaced with any suitable storage / memory / technology / medium. In some embodiments, the logic 160 / 170 may be coupled to one or more substrates (e.g., silicon, sapphire, gallium arsenide, printed circuit board (PCB), etc.) and may include channel areas of transistors located on one or more substrates. In other embodiments, the SSD 130 may include two or more types of storage media. For example, the majority of the storage may be NAND, and may further include some faster, finer-grained (e.g., byte-addressable) NVM. The SSD 130 may optionally or additionally include persistent volatile memory (e.g., DRAM or SRAM with power backed up by a battery or capacitor). For example, the SSD 130 may include power loss protection (PLI) technology with energy storage capacitors. The energy storage capacitors can supply enough energy (power) to ensure that any ongoing commands are completed and that any data in the DRAM / SRAM is recorded to the non-volatile NAND medium. The capacitor can function as a backup battery for persistent volatile memory. As shown in Figures 7 and 8, the functions or aspects of logic 160 and / or logic 170 may be distributed throughout the system 100 and / or located in the same place as / integrated with various components of the system 100.

[0064] [Additional points to note and examples]

[0065] Embodiment 1 includes an electronic device comprising one or more substrates and a controller connected to one or more substrates, wherein the controller includes logic, the logic controlling access to a NAND-based storage medium comprising a first cell area having a first number of levels and a second area having a second number of levels different from the first number, determining a logical block address location corresponding to a user-configurable capacity placeholder, and adjusting the respective sizes of the first cell area and the second cell area at runtime based on the logical block address location.

[0066] Example 2 includes the apparatus described in Example 1, and the logic further enables a function to user-configure the size of the first cell area in response to a command.

[0067] Example 3 includes the apparatus described in Example 2, and the logic further reserves a range of logical block addresses to manage capacity conversion between the first cell area and the second cell area.

[0068] Example 4 includes the apparatus described in any of Examples 2 to 3, and the logic further stores user data on a NAND-based storage medium when this function is enabled.

[0069] Example 5 includes the apparatus described in Example 4, and the logic further converts blocks of the second cell region into blocks of the first cell region.

[0070] Example 6 includes the apparatus described in Example 5, and the logic further moves the data from the second cell region to the transformed block in the first cell region.

[0071] Example 7 includes the apparatus described in any of Examples 1 to 6, wherein the controller and NAND-based storage medium are incorporated into a solid-state drive.

[0072] Embodiment 8 includes an electronic storage system comprising a NAND-based storage medium including a first cell area having a first number of levels and a second area having a second number of levels different from the first number of levels, and a controller communicatively connected to the NAND-based storage medium, wherein the controller includes logic that determines a logical block address location corresponding to a user-configurable capacity placeholder and adjusts the size of the first cell area and the second cell area at runtime based on the logical block address location.

[0073] Example 9 includes the system described in Example 8, and the logic further enables the ability to user-configure the size of the first cell area in response to a command.

[0074] Example 10 includes the system described in Example 9, and the logic further reserves a range of logical block addresses to manage capacity conversion between the first cell area and the second cell area.

[0075] Example 11 includes the system described in any of Examples 9 to 10, and the logic further stores user data on a NAND-based storage medium when this function is enabled.

[0076] Example 12 includes the system described in Example 11, and the logic further converts blocks in the second cell region into blocks in the first cell region.

[0077] Example 13 includes the system described in Example 12, and the logic further moves the data from the second cell region to the transformed block in the first cell region.

[0078] Example 14 includes the system described in any of Examples 8 to 13, wherein the controller and NAND-based storage medium are incorporated into a solid-state drive.

[0079] Embodiment 15 includes a method for controlling storage, the method comprising the steps of: controlling access to a NAND-based storage medium including a first cell area having a first number of levels and a second area having a second number of levels different from the first number of levels; determining a logical block address location corresponding to a user-configurable capacity placeholder; and adjusting the respective sizes of the first cell area and the second cell area at runtime based on the logical block address location.

[0080] Example 16 includes the method described in Example 15, and further comprises the step of enabling a function to user-configure the size of the first cell area in response to a command.

[0081] Example 17 includes the method described in Example 16, and further comprises the step of reserving a range of logical block addresses in order to manage capacity conversion between a first cell region and a second cell region.

[0082] Example 18 includes the method described in any of Examples 16 to 17, and further comprises the step of saving user data to a NAND-based storage medium when this function is enabled.

[0083] Example 19 includes the method described in Example 18, and further comprises the step of converting a block of a second cell region into a block of a first cell region.

[0084] Example 20 includes the method described in Example 19, and further comprises the step of moving data from a second cell region to a transformed block in a first cell region.

[0085] Example 21 includes the method described in any of Examples 15 to 20, wherein the NAND-based storage medium is incorporated into a solid-state drive.

[0086] Embodiment 22 includes at least one non-temporary machine-readable medium, the medium comprising a plurality of instructions, which, in response to being executed by a computing device, cause the computing device to control access to a NAND-based storage medium comprising a first cell area having a first number of levels and a second area having a second number of levels different from the first number, to determine a logical block address location corresponding to a user-configurable capacity placeholder, and to adjust the sizes of the first cell area and the second cell area, respectively, at runtime based on the logical block address location.

[0087] Embodiment 23 includes at least one non-temporary machine-readable medium as described in Embodiment 22, and comprises a number of further instructions that, in response to being executed on a computing device, cause the computing device to enable the ability to user-configure the size of a first cell area in response to a command.

[0088] Embodiment 24 includes at least one non-temporary machine-readable medium as described in Embodiment 23 and further comprises a number of instructions that, in response to being executed on a computing device, cause the computing device to reserve a range of logical block addresses in order to manage capacity conversion between a first cell area and a second cell area.

[0089] Example 25 includes at least one non-temporary machine-readable medium as described in any of Examples 23 to 24, and further includes a number of instructions that cause the computing device to store user data in a NAND-based storage medium when this function is enabled, in response to being executed on the computing device.

[0090] Embodiment 26 includes at least one non-temporary machine-readable medium as described in Embodiment 25, and further comprises a number of instructions that, in response to being executed on a computing device, cause the computing device to convert blocks in a second cell region into blocks in a first cell region.

[0091] Embodiment 27 includes at least one non-temporary machine-readable medium as described in Embodiment 26, and comprises a plurality of further instructions that, in response to being executed on the computing device, cause the computing device to move data from a second cell region to a converted block in a first cell region.

[0092] Example 28 includes at least one non-temporary machine-readable medium described in any of Examples 22 to 27, wherein the NAND-based storage medium is incorporated into a solid-state drive.

[0093] Embodiment 29 includes a storage controller device, which comprises means for controlling access to a NAND-based storage medium including a first cell area having a first number of levels and a second area having a second number of levels different from the first number of levels; means for determining a logical block address location corresponding to a user-configurable capacity placeholder; and means for adjusting the respective sizes of the first cell area and the second cell area at runtime based on the logical block address location.

[0094] Example 30 includes the apparatus described in Example 29, and further comprises means for enabling a user-configurable function to set the size of the first cell area in response to a command.

[0095] Example 31 includes the apparatus described in Example 30, and further comprises means for securing a range of logical block addresses in order to manage capacity conversion between the first cell area and the second cell area.

[0096] Example 32 includes the apparatus described in any of Examples 30 to 31, and further comprises means for storing user data on a NAND-based storage medium when this function is enabled.

[0097] Example 33 includes the apparatus described in Example 32, and further comprises means for converting blocks of the second cell region into blocks of the first cell region.

[0098] Example 34 includes the apparatus described in Example 33, and further comprises means for moving data from a second cell region to a converted block in a first cell region.

[0099] Example 35 includes the apparatus described in any of Examples 29 to 34, wherein the NAND-based storage medium is incorporated into a solid-state drive.

[0100] The term “connected” may be used herein to refer to any kind of direct or indirect relationship between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical, or other connections. Furthermore, terms such as “first,” “second,” etc., may be used herein solely for the sake of clarity and, unless otherwise indicated, do not have any specific temporal or chronological meaning.

[0101] In this application and claims, a series of items leading to the term “one or more of ~” may mean any combination of the terms described. For example, the phrase “one or more of A, B, and C” and the phrase “one or more of A, B, or C” may both mean A; B; C; A and B; A and C; B and C; or A, B, and C. Various components of the system described herein may be implemented by software, firmware, and / or hardware, and / or any combination thereof. For example, various components of the system or device described herein may be provided at least in part by hardware such as a computing SoC, which may be found in a computing system such as a smartphone. A person skilled in the art will recognize that the system described herein may include additional components not shown in the corresponding figures. For example, the system described herein may include additional components such as a bitstream multiplexer or demultiplexer module, which are not shown for clarity.

[0102] The implementation of the exemplary processes described herein may include performing all operations shown in the illustrated order, but the disclosure is not limited thereto. In various examples, the implementation of the exemplary processes herein may include only a subset of the operations shown, operations performed in a different order than illustrated, or additional operations.

[0103] Furthermore, one or more of the operations described herein may be performed in response to instructions provided by one or more computer program products. Such program products may include, for example, a signal-carrying medium that provides instructions that, when executed by a processor, can produce the functions described herein. The computer program products may be provided in one or more machine-readable media of any form. Thus, for example, a processor including one or more image processing devices or processor cores may execute one or more of the exemplary process blocks described herein in response to program code and / or instructions or instruction sets sent to the processor by one or more machine-readable media. Generally, machine-readable media can carry software in the form of program code and / or instructions or instruction sets that can enable at least some of the operations described herein and / or any part of the devices, systems, or any module or component described herein to be implemented in any of the devices and / or systems described herein.

[0104] In any implementation described herein, the term “module” means any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. Software may be embodied as software packages, code, and / or instruction sets or instructions, and in any implementation described herein, “hardware” may include, for example, hardwired circuitry, programmable circuitry, state machine circuitry, fixed-function circuitry, execution unit circuitry, and / or firmware storing instructions executed by programmable circuitry, either alone or in any combination. These modules may be embodied together or individually as circuitry that forms part of a larger system (e.g., integrated circuits (ICs) and system-on-a-chip (SoCs)).

[0105] Various embodiments may be implemented using hardware elements, software elements, or a combination of both. Examples of hardware elements include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, and inductors), integrated circuits, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), logic gates, registers, semiconductor devices, chips, microchips, and chipsets. Examples of software include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application programming interfaces (APIs), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. The determination of whether an embodiment is implemented using hardware and / or software elements may depend on any number of factors, such as the desired computation rate, power level, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints.

[0106] One or more aspects of at least one embodiment may be implemented by representative instructions, stored in a machine-readable medium, that represent various logics within a processor, which, when read by a machine, cause the machine to create logic for performing the techniques described herein. Such representations are known as IP cores and may be stored in a tangible machine-readable medium and supplied to various customers or manufacturing facilities for loading into manufacturing machines that actually produce the logic or processor.

[0107] While certain features described herein have been explained with reference to various implementation examples, this explanation is not intended to be constrained. Therefore, various modifications of the implementation examples described herein and other implementation examples, though obvious to those skilled in the art to whom this disclosure relates, are considered to be within the spirit and scope of this disclosure.

[0108] These embodiments are not limited to those described herein, but it will be recognized that they may be implemented with modifications and alterations without departing from the scope of the attached claims. For example, the embodiments may include certain combinations of features. However, the embodiments are not limited in this respect, and in various implementations, the embodiments may include the implementation of only a subset of such features, the implementation of such features in different orders, the implementation of such features in different combinations, and / or the implementation of additional features beyond those explicitly described. Accordingly, the scope of these embodiments should be determined by referring to the attached claims together with the entire scope of the equivalents to which such claims are entitled. Furthermore, this embodiment includes the following items. (Item 1) An electronic device, One or more substrates; and A controller connected to one or more of the aforementioned boards, wherein the controller includes logic, Controlling access to a NAND-based storage medium including a first cell region having a first number of levels and a second cell region having a second number of levels different from the first number of levels, Determine the logical block address location corresponding to the user-configurable capacity placeholder, The sizes of the first and second cell regions are adjusted at runtime based on the aforementioned logical block address positions. A device equipped with the following features. (Item 2) The aforementioned logic further, The device described in item 1, which enables the ability to user-configure the size of the first cell area in response to a command. (Item 3) The aforementioned logic further, The device described in item 2, which reserves a range of logical block addresses in order to manage capacity conversion between the first cell area and the second cell area. (Item 4) The aforementioned logic further, The apparatus described in item 2, which saves user data to the NAND-based storage medium when the aforementioned function is enabled. (Item 5) The aforementioned logic further, The apparatus described in item 4, which converts a block of the second cell region to a block of the first cell region. (Item 6) The aforementioned logic further, The apparatus according to item 5, which moves the data of the second cell region to the converted block of the first cell region. (Item 7) The apparatus according to item 1, wherein the controller and the NAND-based storage medium are incorporated into a solid-state drive. (Item 8) It is an electronic storage system, A NAND-based storage medium comprising a first cell region having a first number of levels and a second cell region having a second number of levels different from the first number of levels; and A controller communicatively connected to the NAND-based storage medium, wherein the controller includes logic, and the logic includes Determine the logical block address location corresponding to the user-configurable capacity placeholder, The sizes of the first and second cell regions are adjusted at runtime based on the aforementioned logical block address positions. A system equipped with these features. (Item 9) The aforementioned logic further, The system described in item 8 enables the ability to user-configure the size of the first cell area in response to a command. (Item 10) The aforementioned logic further, The system described in item 9, which reserves a range of logical block addresses to manage capacity conversion between the first cell area and the second cell area. (Item 11) The aforementioned logic further, The system according to item 9, which saves user data to the NAND-based storage medium when the aforementioned function is enabled. (Item 12) The aforementioned logic further, The system according to item 11, which converts a block of the second cell region to a block of the first cell region. (Item 13) The aforementioned logic further, The system according to item 12, which moves the data of the second cell region to the converted block of the first cell region. (Item 14) The system according to item 8, wherein the controller and the NAND-based storage medium are incorporated into a solid-state drive. (Item 15) A storage control method, A step of controlling access to a NAND-based storage medium that includes a first cell region having a first number of levels and a second cell region having a second number of levels different from the first number of levels; The step of determining the logical block address location corresponding to a user-configurable capacity placeholder, and A step of adjusting the size of the first cell region and the second cell region at runtime based on the logical block address position. A method for providing this. (Item 16) moreover, The method of item 15, further comprising a step of enabling a function to user-configure the size of the first cell area in response to a command. (Item 17) moreover, The method of item 16, further comprising the step of reserving a range of logical block addresses in order to manage capacity conversion between the first cell area and the second cell area. (Item 18) moreover, The method according to item 16, further comprising the step of saving user data to the NAND-based storage medium when the aforementioned function is enabled. (Item 19) moreover, The method of item 18, further comprising the step of converting a block of the second cell region into a block of the first cell region. (Item 20) moreover, The method according to item 19, further comprising the step of moving the data of the second cell region to the converted block of the first cell region.

Claims

1. An electronic device, A NAND-based storage medium including a first cell region having a first number of levels and a second cell region having a second number of levels different from the first number of levels, The system comprises a controller connected to the aforementioned NAND-based storage medium, The controller comprises at least, Determine the logical block address location corresponding to the capacity placeholder, The sizes of the first cell region and the second cell region are adjusted based on the logical block address position. It is structured in such a way. Device.

2. The aforementioned controller further, The apparatus according to claim 1, configured to enable a function that allows the user to set the size of the first cell area in response to a command.

3. The aforementioned controller further, The apparatus according to claim 2, configured to reserve a range of logical block addresses in order to manage capacity conversion between the first cell region and the second cell region.

4. The aforementioned controller further, The apparatus according to claim 2, configured to store user data in the NAND-based storage medium when the aforementioned function is enabled.

5. The aforementioned controller further, The apparatus according to claim 4, configured to convert the blocks of the second cell region into conversion blocks of the first cell region.

6. The aforementioned controller further, The apparatus according to claim 5, configured to move data from the second cell region to the conversion block in the first cell region.

7. The apparatus according to claim 1, wherein the controller and the NAND-based storage medium are incorporated into a solid-state drive.

8. It is an electronic storage system, A non-volatile storage medium including a first cell region having a first number of levels and a second cell region having a second number of levels different from the first number of levels, The system comprises a controller connected to the non-volatile storage medium, The controller comprises at least, Determine the logical block address location corresponding to the capacity placeholder, The sizes of the first cell region and the second cell region are adjusted based on the logical block address position. It is structured in such a way. system.

9. The aforementioned controller further, The system according to claim 8, configured to enable a function that allows the user to set the size of the first cell area in response to a command.

10. The aforementioned controller further, The system according to claim 9, configured to reserve a range of logical block addresses in order to manage capacity conversion between the first cell region and the second cell region.

11. The aforementioned controller further, The system according to claim 9, configured to store user data in the non-volatile storage medium when the aforementioned function is enabled.

12. The aforementioned controller further, The system according to claim 11, configured to convert blocks of the second cell region into blocks of the first cell region.

13. The aforementioned controller further, The system according to claim 12, configured to move data from the second cell region to the converted block in the first cell region.

14. The system according to claim 8, wherein the controller and the non-volatile storage medium are incorporated into a solid-state drive.

15. A storage control method, The step of determining the logical block address location corresponding to the capacity placeholder, A step of adjusting the size of the first cell area and the second cell area based on the logical block address position. Equipped with, The first cell region and the second cell region are contained in a non-volatile storage medium, the first cell region has a first number of levels, and the second cell region has a second number of levels different from the first number of levels. method.

16. The method according to claim 15, further comprising the step of enabling a function to user-configure the size of the first cell area in response to a command.

17. The method according to claim 16, further comprising the step of reserving a range of logical block addresses in order to manage capacity conversion between the first cell area and the second cell area.

18. The method according to claim 16, further comprising the step of saving user data to the non-volatile storage medium when the above function is enabled.

19. The method according to claim 18, further comprising the step of converting a block of the second cell region into a block of the first cell region.

20. The method according to claim 19, further comprising the step of moving data from the second cell region to the converted block in the first cell region.

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