Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide a technique capable of appropriately increasing the junction area of a pn junction.SOLUTION: A semiconductor device includes a semiconductor substrate having a first main surface and a second main surface, and a polysilicon element provided on the first main surface via a first insulating film. The polysilicon element includes a first region of a first conductivity type and a second region of a second conductivity type provided on the first insulating film, and a third region of the second conductivity type provided between the first region and second region and having a lower impurity concentration than the second region. The width of the first region in a cross-sectional view varies in a direction directed from the second main surface to the first main surface.SELECTED DRAWING: Figure 18

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] In recent years, a configuration has been proposed in which a temperature sense diode for measuring the temperature of a semiconductor device is provided on a semiconductor substrate (for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2015-211087 [Overview of the project] [Problems that the invention aims to solve]

[0004] In conventional technology, multiple impurity regions in a temperature sense diode are provided in the vertical direction (i.e., the thickness direction) when viewed in cross-section, and the boundary of the pn junction extends without tilting in the vertical direction. To increase the junction area of ​​the pn junction of such a temperature sense diode and reduce the forward voltage, two configurations can be considered: one that increases the area of ​​the temperature sense diode in a plan view, and another that increases the thickness of the multiple impurity regions in a cross-sectional view. However, the configuration that increases the area of ​​the temperature sense diode in a plan view has the problem of reducing the effective area, such as the current-carrying area of ​​the semiconductor device. Also, the configuration that increases the thickness of the impurity regions in a cross-sectional view has the problem of increasing the time for impurity diffusion.

[0005] Therefore, this disclosure has been made in view of the above-mentioned problems, and aims to provide a technology that can appropriately increase the bonding area of ​​a pn junction. [Means for solving the problem]

[0006] The semiconductor device according to this disclosure comprises a semiconductor substrate having a first main surface and a second main surface, and a polysilicon element provided on the first main surface via a first insulating film, wherein the semiconductor substrate includes a current-carrying region on the first main surface side and a second electrode on the second main surface side, and the polysilicon element includes a first region of a first conductivity type and a second region of a second conductivity type provided on the first insulating film, and a third region of a second conductivity type provided between the first region and the second region and having a lower impurity concentration than the second region, wherein the width of the first region in cross-sectional view changes in the direction from the second main surface to the first main surface Furthermore, as the width of the first region in cross-sectional view changes with respect to the direction, the first region has a tapered shape. do. [Effects of the Invention]

[0007] According to this disclosure, the width of the first region in a cross-sectional view changes with respect to the direction from the second principal surface to the first principal surface. With such a configuration, the bonding area of ​​the pn joint can be appropriately increased. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view showing the configuration of a semiconductor device according to Embodiment 1. [Figure 2] This is a plan view showing another configuration of the semiconductor device according to Embodiment 1. [Figure 3] This is a partially enlarged plan view showing the configuration of the IGBT region of the semiconductor device according to Embodiment 1. [Figure 4] This is a cross-sectional view showing the configuration of the IGBT region of the semiconductor device according to Embodiment 1. [Figure 5] This is a cross-sectional view showing the configuration of the IGBT region of the semiconductor device according to Embodiment 1. [Figure 6] This is a partially enlarged plan view showing the configuration of the diode region of the semiconductor device according to Embodiment 1. [Figure 7] This is a cross-sectional view showing the configuration of the diode region of the semiconductor device according to Embodiment 1. [Figure 8]This is a cross-sectional view showing the configuration of the diode region of the semiconductor device according to Embodiment 1. [Figure 9] This is a cross-sectional view showing the configuration of the boundary region between the IGBT region and the diode region of the semiconductor device according to Embodiment 1. [Figure 10] This is a cross-sectional view showing the configuration of the termination region of a semiconductor device according to Embodiment 1. [Figure 11] This is a cross-sectional view showing the configuration of the termination region of a semiconductor device according to Embodiment 1. [Figure 12] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 13] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 14] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 15] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 16] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 17] This is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 18] This is a plan view showing the configuration of a semiconductor device according to Embodiment 1. [Figure 19] This is a flowchart showing the method for manufacturing a semiconductor device according to Embodiment 1. [Figure 20] This is a plan view illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 21] This is a plan view illustrating the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 22] This is a plan view showing the configuration of a semiconductor device according to a modified example. [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the attached drawings. The features described in each of the embodiments below are illustrative, and not all features are necessarily required. In addition, in the descriptions below, the same or similar reference numerals are used for similar components in multiple embodiments, and the different components are mainly described. Also, in the descriptions below, specific positions and directions such as "top," "bottom," "left," "right," "front," or "back" do not necessarily have to coincide with the positions and directions in actual implementation.

[0010] Furthermore, a higher concentration in one part than in another means, for example, that the average concentration in one part is higher than the average concentration in the other part. Conversely, a lower concentration in one part than in another means, for example, that the average concentration in one part is lower than the average concentration in the other part. Also, in the following explanation, we will assume that the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. - This indicates that the impurity concentration is lower than n, and n + This indicates that the impurity concentration is higher than n. Similarly, p - This indicates that the impurity concentration is lower than p, and p + This indicates that the impurity concentration is higher than p.

[0011] <Embodiment 1> Figure 1 is a plan view showing a semiconductor device equipped with an RC-IGBT (Reverse Conducting IGBT). Figure 2 is a plan view showing an alternative configuration of the semiconductor device equipped with an RC-IGBT according to this first embodiment.

[0012] As will be described later, the semiconductor device according to this embodiment 1 includes not only RC-IGBTs but also polysilicon elements. Below, the configuration of the RC-IGBTs in the semiconductor device will be described, followed by the configuration of the polysilicon elements. Note that in the description of RC-IGBTs, the RC-IGBTs and semiconductor devices may not be distinguished.

[0013] The semiconductor device 100 shown in Figure 1 has IGBT regions 10 and diode regions 20 arranged in a stripe pattern, and in the following description it may simply be referred to as the "stripe type". The semiconductor device 100 shown in Figure 2 has multiple diode regions 20 arranged in the vertical and horizontal directions, with IGBT regions 10 arranged around the diode regions 20, and in the following description it may simply be referred to as the "island type". Note that the semiconductor device only needs to have at least one of the stripe type structure in Figure 1 and the island type structure in Figure 2. Note that in this specification, for example, at least one of A, B, C, ..., and Z means any one of all combinations obtained by selecting one or more from the groups A, B, C, ..., and Z.

[0014] <Striped overall planar structure> In Figure 1, the semiconductor device 100 includes an IGBT region 10 and a diode region 20 within a single semiconductor device. Each of the IGBT region 10 and the diode region 20 extends from one end to the other of the semiconductor device 100, and is arranged alternately in stripes in a direction perpendicular to the extension direction of the IGBT region 10 and the diode region 20. In Figure 1, three IGBT regions 10 and two diode regions 20 are shown, and a configuration is shown in which all diode regions 20 are sandwiched between IGBT regions 10. However, the number of IGBT regions 10 and diode regions 20 is not limited to this; the number of IGBT regions 10 may be three or more or three or less, and the number of diode regions 20 may be two or more or two or less. Furthermore, the positions of the IGBT regions 10 and diode regions 20 in Figure 1 may be swapped, and a configuration in which all IGBT regions 10 are sandwiched between diode regions 20 may also be possible. In addition, a configuration in which one IGBT region 10 and one diode region 20 are provided adjacent to each other may also be possible.

[0015] As shown in Figure 1, a pad region 40 is provided adjacent to the IGBT region 10 on the lower side of the paper. The pad region 40 is the region where control pads 41 for controlling the semiconductor device 100 are provided. In the following description, the IGBT region 10 and the diode region 20 together may be referred to as the cell region. A termination region 30 is provided around the combined region of the cell region and the pad region 40 to maintain the breakdown voltage of the semiconductor device 100. A well-known breakdown voltage maintenance structure may be appropriately provided in the termination region 30. For example, the breakdown voltage maintenance structure may include an FLR (Field Limiting Ring) on ​​the front side of the semiconductor device 100, where the cell region is surrounded by a p-type termination well layer of a p-type semiconductor, or a VLD (Variation of Lateral Doping) where the cell region is surrounded by a p-type well layer with a concentration gradient. The number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected according to the breakdown voltage design of the semiconductor device 100. Furthermore, a p-type termination well layer may be provided over almost the entire area of ​​the pad region 40, and IGBT cells or diode cells may be provided in the pad region 40.

[0016] The control pad 41 includes, for example, at least one of a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sense diode pads 41d, 41e.

[0017] The current sense pad 41a is a control pad for detecting the current flowing through the cell region of the semiconductor device 100. The current sense pad 41a is electrically connected to the cell region of the semiconductor device 100 so that when current flows through the cell region, a fraction of the current flowing through the entire cell region, ranging from one-tenth to one-tens-thousandth of the current, flows through a portion of the IGBT cells or diode cells within that cell region.

[0018] The Kelvin emitter pad 41b and gate pad 41c are control pads to which a gate drive voltage is applied for on / off control of the semiconductor device 100. The Kelvin emitter pad 41b is electrically connected to the p-type base layer of the IGBT cell. The gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer are p + They may be electrically connected via a contact layer. The temperature sense diode pads 41d and 41e are control pads electrically connected to the anode and cathode of a temperature sense diode provided on the semiconductor device 100. The voltage between the anode and cathode of a temperature sense diode (not shown) provided in the cell region is measured via the temperature sense diode pads 41d and 41e, and the temperature of the semiconductor device 100 is measured based on this voltage.

[0019] <Island-type overall floor plan> In Figure 2, the semiconductor device 100 includes an IGBT region 10 and a diode region 20 within a single semiconductor device. Multiple diode regions 20 are arranged in a row in both the vertical and horizontal directions within the semiconductor device 100, and each diode region 20 is surrounded by the IGBT region 10. In other words, multiple diode regions 20 are provided in an island-like manner within the IGBT region 10. In Figure 2, the diode regions 20 are shown arranged in a matrix with 4 columns in the horizontal direction and 2 rows in the vertical direction of the paper. However, the number and arrangement of diode regions 20 are not limited to this, and it is acceptable as long as one or more diode regions 20 are scattered within the IGBT region 10, and each diode region 20 is surrounded by the IGBT region 10.

[0020] As shown in Figure 2, a pad region 40 is provided adjacent to the lower side of the IGBT region 10. The pad region 40 is the region where control pads 41 for controlling the semiconductor device 100 are provided. In this explanation, the IGBT region 10 and the diode region 20 together are referred to as the cell region. A termination region 30 is provided around the combined region of the cell region and pad region 40 to maintain the breakdown voltage of the semiconductor device 100. A well-known breakdown voltage maintenance structure may be appropriately provided in the termination region 30. For example, the breakdown voltage maintenance structure may include an FLR (Flat Layer Ring) on ​​the front side of the semiconductor device 100, where the combined region of the cell region and pad region 40 is surrounded by a p-type termination well layer of a p-type semiconductor, or a VLD (Very Wide Layer) where the cell region is surrounded by a p-type well layer with a density gradient. The number of ring-shaped p-type termination well layers used in the FLR and the density distribution used in the VLD should be appropriately selected according to the breakdown voltage design of the semiconductor device 100. Furthermore, a p-type termination well layer may be provided over almost the entire area of ​​the pad region 40, and IGBT cells or diode cells may be provided in the pad region 40.

[0021] The control pad 41 includes, for example, at least one of a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sense diode pads 41d, 41e.

[0022] The current sense pad 41a is a control pad for detecting the current flowing through the cell region of the semiconductor device 100. The current sense pad 41a is electrically connected to the cell region of the semiconductor device 100 so that when current flows through the cell region, a fraction of the current flowing through the entire cell region, ranging from one-tenth to one-tens-thousandth of the current, flows through a portion of the IGBT cells or diode cells within that cell region.

[0023] The Kelvin emitter pad 41b and gate pad 41c are control pads to which a gate drive voltage is applied for on / off control of the semiconductor device 100. The Kelvin emitter pad 41b is the p-type base layer and n-type base layer of the IGBT cell. +It is electrically connected to the p-type source layer. The gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer may be electrically connected via a p + type contact layer. The temperature sense diode pads 41d, 41e are control pads electrically connected to the anode and cathode of a temperature sense diode provided in the semiconductor device 100. The voltage between the anode and cathode of a temperature sense diode (not shown) provided in the cell region is measured via the temperature sense diode pads 41d, 41e, and the temperature of the semiconductor device 100 is measured based on the voltage.

[0024] <IGBT region 10> FIG. 3 is a partially enlarged plan view showing the configuration of the IGBT region 10 of a semiconductor device that is an RC-IGBT. Specifically, FIG. 3 is a view showing an enlarged view of the region surrounded by the dashed line 82 in the semiconductor device 100 shown in FIGS. 1 and 2.

[0025] Also, FIGS. 4 and 5 are cross-sectional views showing the configuration of the IGBT region 10 of a semiconductor device that is an RC-IGBT. Specifically, FIG. 4 is a cross-sectional view taken along the dashed-dotted line A-A of the semiconductor device 100 shown in FIG. 3, and FIG. 5 is a cross-sectional view taken along the dashed-dotted line B-B of the semiconductor device 100 shown in FIG. 3.

[0026] As shown in FIG. 3, in the IGBT region 10, active trench gates 11 and dummy trench gates 12 are provided in a stripe shape. In the semiconductor device 100 of FIG. 1, the active trench gates 11 and the dummy trench gates 12 extend in the longitudinal direction of the IGBT region 10, and the longitudinal direction of the IGBT region 10 corresponds to the longitudinal direction of the active trench gates 11 and the dummy trench gates 12. On the other hand, in the semiconductor device 100 of FIG. 2, there is no particular distinction between the longitudinal direction and the lateral direction in the IGBT region 10. For this reason, the left-right direction of the paper surface may correspond to the longitudinal direction of the active trench gates 11 and the dummy trench gates 12, or the up-down direction of the paper surface may correspond to the longitudinal direction of the active trench gates 11 and the dummy trench gates 12.

[0027] The active trench gate 11 is configured such that a gate trench electrode 11a is provided in a trench formed in a semiconductor substrate via a gate trench insulating film 11b. The dummy trench gate 12 is configured such that a dummy trench electrode 12a is provided in a trench formed in a semiconductor substrate via a dummy trench insulating film 12b. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c in FIGS. 1 and 2. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode provided on the front surface of the semiconductor device 100.

[0028] As shown in FIG. 3, an n + -type source layer 13 is provided on both sides in the width direction of the active trench gate 11 in contact with the gate trench insulating film 11b. The n + -type source layer 13 is also called an n + -type emitter layer in some semiconductor devices. The n + -type source layer 13 is a semiconductor layer containing, for example, arsenic (As) or phosphorus (P) as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0E+17 / cm 3 ~1.0E+20 / cm 3 . The n + -type source layer 13 is provided alternately with a p + -type contact layer 14 along the extending direction of the active trench gate 11. Also, the p + -type contact layer 14 is provided in contact with the dummy trench insulating film 12b between two adjacent dummy trench gates 12. The p + -type contact layer 14 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+15 / cm 3 ~1.0E+20 / cm 3 .

[0029] As shown in Figure 3, in the IGBT region 10 of the semiconductor device 100, three active trench gates 11 are arranged side by side, and next to them are three dummy trench gates 12. Next to these three dummy trench gates 12 are three other active trench gates 11. The IGBT region 10 is thus configured with alternating sets of active trench gates 11 and sets of dummy trench gates 12. In Figure 3, the number of active trench gates 11 in one set of active trench gates 11 is set to 3, but it is acceptable to have 1 or more. Similarly, the number of dummy trench gates 12 in one set of dummy trench gates 12 may be 1 or more, or the number of dummy trench gates 12 may be 0. In other words, all of the trench gates provided in the IGBT region 10 may be active trench gates 11.

[0030] Figure 4 is a cross-sectional view of the semiconductor device 100 along the dashed line AA in Figure 3, and is a cross-sectional view of the IGBT region 10. The semiconductor device 100 is made of n - It has a type drift layer 1. - The n-type drift layer 1 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0E+12 / cm³. 3 ~1.0E+15 / cm 3 That is the case. Furthermore, the above-mentioned n + The concentration of n-type impurities in the n-type source layer 13 is n - The concentration of n-type impurities is higher than that of type drift layer 1.

[0031] In Figure 4, the range of the semiconductor substrate is n + Type source layer 13 and p + This range extends from the p-type contact layer 14 to the p-type collector layer 16. The p-type collector layer 16 is also called the p-type drain layer depending on the semiconductor device. In Figure 4, n + Type source layer 13 and p +The upper edge of the paper of the p-type contact layer 14 is called the front surface, which is the first main surface of the semiconductor substrate, and the lower edge of the paper of the p-type collector layer 16 is called the back surface, which is the second main surface of the semiconductor substrate. In the IGBT region 10 of the cell region of the semiconductor device 100, there is an n- - It has a type drift layer 1. The semiconductor substrate may be composed of, for example, at least one of a wafer and an epitaxial growth layer. The semiconductor substrate may also include a wide bandgap semiconductor (silicon carbide (SiC), gallium nitride (GaN), diamond) that can operate stably at high temperatures.

[0032] As shown in Figure 4, in the IGBT region 10, n - On the front side of the drift layer 1, n - An n-type carrier storage layer 2 is provided, which has a higher concentration of n-type impurities than the n-type drift layer 1. The n-type carrier storage layer 2 is a semiconductor layer having, for example, arsenic or phosphorus as n-type impurities, and its concentration of n-type impurities is, for example, 1.0E+13 / cm³. 3 ~1.0E+17 / cm 3 Furthermore, the semiconductor device 100 does not have an n-type carrier storage layer 2, and even in the region of the n-type carrier storage layer 2 shown in Figure 4, n - A configuration in which an n-type drift layer 1 is provided is also possible. By providing an n-type carrier storage layer 2, the current loss when current flows through the IGBT region 10 can be reduced. n-type carrier storage layer 2 and n - The drift layer 1 and this layer together can be called the drift layer.

[0033] n-type carrier storage layer 2 is n - n-type impurities are ion-implanted into the semiconductor substrate constituting the n-type drift layer 1, and then the implanted n-type impurities are removed by annealing. - It is formed by diffusion into the semiconductor substrate, which is the drift layer 1.

[0034] A p-type base layer 15 is provided on the front side of the n-type carrier storage layer 2. The p-type base layer 15 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+12 / cm³. 3 ~1.0E+19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11.

[0035] In a portion of the front surface of the p-type base layer 15, n is in contact with the gate trench insulating film 11b of the active trench gate 11. + A p-type source layer 13 is provided, and the remaining area on the front side of the p-type base layer 15 is p + A type contact layer 14 is selectively provided. + Type source layer 13 and p + The type contact layer 14 constitutes the front surface of the semiconductor substrate. + The p-type contact layer 14 is a region where the concentration of p-type impurities is higher than that of the p-type base layer 15. + If it is necessary to distinguish between the type contact layer 14 and the p-type base layer 15, they may be referred to separately, or if there is no need to distinguish between them, they may be referred to as p-type. + The p-type contact layer 14 and the p-type base layer 15 can together be called the p-type base layer.

[0036] Also, n of semiconductor device 100 - On the back side of the drift layer 1, n - An n-type buffer layer 3 is provided, which has a higher concentration of n-type impurities than the n-type drift layer 1. The n-type buffer layer 3 is provided to suppress punch-through of the depletion layer extending from the p-type base layer 15 to the back side when the semiconductor device 100 is in the off state. The n-type buffer layer 3 contains, for example, phosphorus (P) or protons (H). + ) may be injected to form phosphorus (P) and proton (H + Both of the above may be injected to form the layer. The concentration of n-type impurities in the n-type buffer layer 3 is, for example, 1.0E+12 / cm³. 3 ~1.0E+18 / cm 3Furthermore, the semiconductor device 100 does not have an n-type buffer layer 3, and the region of the n-type buffer layer 3 shown in Figure 4 is n - A configuration may also be provided with an n-type drift layer 1. - The drift layer 1 and this layer together can be called the drift layer.

[0037] A p-type collector layer 16 is provided on the back side of the n-type buffer layer 3 of the semiconductor device 100. That is, the p-type collector layer 16 is n - It is provided between the p-type drift layer 1 and the back surface of the semiconductor substrate. The p-type collector layer 16 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+16 / cm³. 3 ~1.0E+20 / cm 3 The p-type collector layer 16 constitutes the back surface of the semiconductor substrate. The p-type collector layer 16 may be provided not only in the IGBT region 10 but also in the termination region 30. As will be described later, the portion of the p-type collector layer 16 provided in the termination region 30 constitutes the p-type termination collector layer 16a. Furthermore, a portion of the p-type collector layer 16 may extend from the IGBT region 10 into the diode region 20.

[0038] As shown in Figure 4, the IGBT region 10 of the semiconductor device 100 penetrates the p-type base layer 15 from the front surface of the semiconductor substrate, and n - A trench reaching the drift layer 1 is provided. An active trench gate 11 is formed by providing gate trench electrodes 11a in several trenches via a gate trench insulating film 11b. The gate trench electrodes 11a are provided via the gate trench insulating film 11b - It faces the drift layer 1. Furthermore, the dummy trench gate 12 is formed by providing dummy trench electrodes 12a in several trenches via a dummy trench insulating film 12b. The dummy trench electrodes 12a are connected via the dummy trench insulating film 12b. - It is facing the drift layer 1.

[0039] The gate trench insulating film 11b of the active trench gate 11 consists of a p-type base layer 15 and n + It is in contact with the type source layer 13. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 that is in contact with the gate trench insulating film 11b of the active trench gate 11.

[0040] As shown in Figure 4, an interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is provided on the region of the front surface of the semiconductor substrate where the interlayer insulating film 4 is not provided, and on the interlayer insulating film 4. The barrier metal 5 may be a conductor containing titanium (Ti), for example, titanium nitride, or TiSi, which is an alloy of titanium and silicon (Si). As shown in Figure 4, the barrier metal 5 is n + Type source layer 13, p + The type contact layer 14 and the dummy trench electrode 12a make ohmic contact, n + Type source layer 13, p + The type contact layer 14 and the dummy trench electrode 12a are electrically connected. On the other hand, the barrier metal 5 is electrically insulated from the gate trench electrode 11a by the interlayer insulating film 4.

[0041] An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 may be formed from an aluminum alloy such as an aluminum-silicon alloy (Al-Si alloy), or it may be an electrode consisting of multiple layers of metal films formed by electroless plating or electrolytic plating on an electrode made of an aluminum alloy. The plating film formed by electroless plating or electrolytic plating may be, for example, a nickel (Ni) plating film. If there are fine regions such as between adjacent interlayer insulating films 4 where good embedding cannot be obtained with the emitter electrode 6, a tungsten film with better embedding properties than the emitter electrode 6 may be placed in the fine region, and the emitter electrode 6 may be provided on the tungsten film. Note that if the barrier metal 5 is not provided, n + Type source layer 13, p +An emitter electrode 6 may be provided on the type contact layer 14 and the dummy trench electrode 12a. + The barrier metal 5 may be provided only on an n-type semiconductor layer such as the source layer 13. The barrier metal 5 and the emitter electrode 6 together may be called the emitter electrode.

[0042] In Figure 4, a configuration is shown in which the interlayer insulating film 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12. However, in the cross-sectional portion of Figure 4, the interlayer insulating film 4 may be provided on the dummy trench electrode 12a of the dummy trench gate 12. If the interlayer insulating film 4 is provided on the dummy trench electrode 12a of the dummy trench gate 12 in the cross-sectional portion of Figure 4, then the emitter electrode 6 and the dummy trench electrode 12a only need to be electrically connected in another cross-sectional portion.

[0043] A collector electrode 7 is provided on the back side of the p-type collector layer 16. The collector electrode 7, like the emitter electrode 6, may be composed of multiple layers of aluminum alloy or aluminum alloy and a plating film. The collector electrode 7 may have a different configuration from the emitter electrode 6. The collector electrode 7 makes ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0044] Figure 5 is a cross-sectional view of the semiconductor device 100 along the dashed line BB in Figure 3, and is a cross-sectional view of the IGBT region 10. Unlike the cross-sectional portion along the dashed line AA shown in Figure 4, the cross-sectional portion along the dashed line BB in Figure 5 is in contact with the active trench gate 11 and is provided on the front side of the semiconductor substrate. + The source layer 13 is missing. In other words, n shown in Figure 3 + The p-type source layer 13 is selectively provided on the front side of the p-type base layer. The p-type base layer referred to here is the p-type base layer 15 and p + It includes a contact layer 14.

[0045] <Diode region 20> Figure 6 is a partially enlarged plan view showing the configuration of the diode region 20 of a semiconductor device that is an RC-IGBT. Specifically, Figure 6 is an enlarged view of the region enclosed by the dashed line 83 in the semiconductor device 100 shown in Figures 1 and 2.

[0046] Furthermore, Figures 7 and 8 are cross-sectional views showing the configuration of the diode region 20 of a semiconductor device that is an RC-IGBT. Specifically, Figure 7 is a cross-sectional view of the semiconductor device 100 shown in Figure 6 along the dashed line CC, and Figure 8 is a cross-sectional view of the semiconductor device 100 shown in Figure 6 along the dashed line DD.

[0047] The diode trench gate 21 extends along the front surface of the semiconductor device 100 from one end of the diode region 20 in the cell region toward the opposite other end. The diode trench gate 21 is configured such that a diode trench electrode 21a is provided in a trench provided in the diode region 20 via a diode trench insulating film 21b. The diode trench electrode 21a is provided via the diode trench insulating film 21b - It is facing the drift layer 1.

[0048] Between the two adjacent diode trench gates 21, p + A p-type contact layer 24 and a p-type anode layer 25 with a lower concentration of p-type impurities are provided. + The p-type contact layer 24 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+15 / cm³. 3 ~1.0E+20 / cm 3 The p-type anode layer 25 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+12 / cm³. 3 ~1.0E+19 / cm 3 p + The p-type contact layer 24 and the p-type anode layer 25 are alternately arranged in the longitudinal direction of the diode trench gate 21.

[0049] FIG. 7 is a cross-sectional view taken along the chain-dotted line C-C in FIG. 6 of the semiconductor device 100 and is a cross-sectional view of the diode region 20. The semiconductor device 100 also has an n-type drift layer 1 made of a semiconductor substrate in the diode region 20, just like in the IGBT region 10. - The n-type drift layer 1 of the diode region 20 and the n-type drift layer 1 of the IGBT region 10 are continuously and integrally formed and are formed on the same semiconductor substrate. - -

[0050] In FIG. 7, the range of the semiconductor substrate is from the p-type contact layer 24 to the n-type cathode layer 26. In FIG. 7, the upper end of the p-type contact layer 24 on the paper surface is referred to as the front surface of the semiconductor substrate, and the lower end of the n-type cathode layer 26 on the paper surface is referred to as the back surface of the semiconductor substrate. The front surface of the diode region 20 and the front surface of the IGBT region 10 are included in the same plane, and the back surface of the diode region 20 and the back surface of the IGBT region 10 are included in the same plane. + + + + [[ID=1十八]]

[0051] As shown in FIG. 7, in the diode region 20 as well as in the IGBT region 10, an n-type carrier accumulation layer 2 is provided on the front surface side of the n-type drift layer 1, and an n-type buffer layer 3 is provided on the back surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the diode region 20 may have the same configuration as the n-type carrier accumulation layer 2 and the n-type buffer layer 3 provided in the IGBT region 10. Note that the n-type carrier accumulation layer 2 does not necessarily have to be provided in the IGBT region 10 and the diode region 20. For example, the n-type carrier accumulation layer 2 may be provided in the IGBT region 10 but not in the diode region 20. Also, similar to the IGBT region 10, the n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 may be collectively referred to as a drift layer. - - -

[0052] ​​​​​​​​On the front surface side of the n-type carrier accumulation layer 2, a p-type anode layer 25 is provided. The p-type anode layer 25 is provided between the n - -type drift layer 1 and the front surface. The concentration of the p-type impurity in the p-type anode layer 25 may be the same as the concentration of the p-type impurity in the p-type base layer 15 of the IGBT region 10, and the p-type anode layer 25 and the p-type base layer 15 may be formed simultaneously. Also, the concentration of the p-type impurity in the p-type anode layer 25 may be made lower than the concentration of the p-type impurity in the p-type base layer 15 of the IGBT region 10 so as to reduce the amount of holes injected into the diode region 20 during diode operation. By reducing the amount of holes injected during diode operation, the recovery loss during diode operation can be reduced.

[0053] On the front surface side of the p-type anode layer 25, a p + -type contact layer 24 is provided. + The concentration of the p-type impurity in the p-type contact layer 24 may be the same as or different from the concentration of the p-type impurity in the p + -type contact layer 14 of the IGBT region 10. The p + -type contact layer 24 constitutes the front surface of the semiconductor substrate. Note that the p + -type contact layer 24 is a region with a higher concentration of p-type impurity than the p-type anode layer 25. When it is necessary to distinguish the p + -type contact layer 24 and the p-type anode layer 25, they may be individually referred to, and when there is no need to distinguish them, the p + -type contact layer 24 and the p-type anode layer 25 may be collectively referred to as the p-type anode layer.

[0054] On the back surface side of the n-type buffer layer 3 of the semiconductor device 100, an n + -type cathode layer 26 is provided. That is, the n + -type cathode layer 26 is provided between the n - -type drift layer 1 and the back surface. The n + -type cathode layer 26 is a semiconductor layer having, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0E+16 / cm 3 ~1.0E+21 / cm3 n + The cathode layer 26 is provided in part or all of the diode region 20. + The cathode layer 26 forms the back surface of the semiconductor substrate. Although not shown in the figure, n + In addition, a p-type impurity may be selectively implanted into a portion of the region where the p-type cathode layer 26 is formed, thereby providing a p-type cathode layer that is a p-type semiconductor.

[0055] Although not shown in Figure 7, n + Type cathode layer 26 and p + The n-type cathode layer and the n-type buffer layer 3 may be provided on the back side of the buffer layer 3 and arranged alternately along the in-plane direction of the semiconductor substrate. A diode configured in this way is called an RFC (Relaxed Field of Cathode) diode.

[0056] As shown in Figure 7, the diode region 20 of the semiconductor device 100 penetrates the p-type anode layer 25 from the front surface of the semiconductor substrate, and n - A trench reaching the drift layer 1 is provided. The diode trench gate 21 is formed by providing a diode trench electrode 21a within the trench of the diode region 20 via a diode trench insulating film 21b. The diode trench electrode 21a is provided via the diode trench insulating film 21b - It is facing the drift layer 1.

[0057] As shown in Figure 7, the diode trench electrode 21a and p + A barrier metal 5 is provided on the type contact layer 24. The barrier metal 5 is provided on the diode trench electrodes 21a and p + The type contact layer 24 and the diode trench electrodes 21a and p make ohmic contact. + It is electrically connected to the contact layer 24. The barrier metal 5 may have the same configuration as the barrier metal 5 of the IGBT region 10.

[0058] An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is configured to be continuous with the emitter electrode 6 provided in the IGBT region 10. In addition, as in the case of the IGBT region 10, if the barrier metal 5 is not provided, the diode trench electrodes 21a and p + The type contact layer 24 and the emitter electrode 6 may be in ohmic contact.

[0059] Although Figure 7 shows a configuration in which the interlayer insulating film 4, as shown in Figure 4, is not provided on the diode trench electrode 21a of the diode trench gate 21, the interlayer insulating film 4 may be provided on the diode trench electrode 21a in the cross-sectional portion of Figure 7. If the interlayer insulating film 4 is provided on the diode trench electrode 21a of the diode trench gate 21 in the cross-sectional portion of Figure 7, then the emitter electrode 6 and the diode trench electrode 21a only need to be electrically connected in another cross-sectional portion.

[0060] n + A collector electrode 7 is provided on the back side of the cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is configured to be continuous with the collector electrode 7 provided in the IGBT region 10. The collector electrode 7 is n + Ohmic contact is made with the type cathode layer 26, n + It is electrically connected to the cathode layer 26.

[0061] Figure 8 is a cross-sectional view of the semiconductor device 100 along the dashed line DD in Figure 6, and is a cross-sectional view of the diode region 20. Unlike the cross-sectional view along the dashed line CC shown in Figure 7, in the cross-sectional view along the dashed line DD in Figure 8, there is a p between the p-type anode layer 25 and the barrier metal 5. + The p-type contact layer 24 is not provided, and the p-type anode layer 25 is the front surface of the semiconductor substrate. In other words, as shown in Figure 7, + The type contact layer 24 is selectively provided on the front side of the p-type anode layer 25.

[0062] <Boundary Region between IGBT Region 10 and Diode Region 20> FIG. 9 is a cross-sectional view showing the configuration of the boundary region between the IGBT region 10 and the diode region 20 of a semiconductor device that is an RC-IGBT. Specifically, FIG. 9 is a cross-sectional view taken along the dashed line E-E in the semiconductor device 100 shown in FIGS. 1 and 2.

[0063] As shown in FIG. 9, the p-type collector layer 16 provided on the back side of the IGBT region 10 and the n + -type cathode layer 26 provided on the back side of the diode region 20 are adjacent to each other in the in-plane direction of the semiconductor substrate. And the p-type collector layer 16 is provided so as to protrude toward the diode region 20 by a distance U1 from the boundary between the IGBT region 10 and the diode region 20.

[0064] Thus, by providing the p-type collector layer 16 to protrude into the diode region 20, the distance between the n + -type cathode layer 26 of the diode region 20 and the active trench gate 11 can be increased. Therefore, even when a gate drive voltage is applied to the gate trench electrode 11a during the reverse recovery diode operation, current flowing from the channel formed adjacent to the active trench gate 11 of the IGBT region 10 to the n + [[ID=X]]-type cathode layer 26 can be suppressed. The distance U1 may be, for example, 100 μm. Depending on the application of the semiconductor device 100 that is an RC-IGBT, the distance U1 may be zero or a distance smaller than 100 μm.

[0065] <Terminal Region 30> FIGS. 10 and 11 are cross-sectional views showing the configuration of the terminal region of the semiconductor device 100 that is an RC-IGBT. Specifically, FIG. 10 is a cross-sectional view taken along the dashed line F-F shown in FIGS. 1 and 2, and is a cross-sectional view from the IGBT region 10 to the terminal region 30. Also, FIG. 11 is a cross-sectional view taken along the dashed line G-G shown in FIG. 1, and is a cross-sectional view from the diode region 20 to the terminal region 30.

[0066] As shown in Figures 10 and 11, the termination region 30 of the semiconductor device 100 is between the front and back surfaces of the semiconductor substrate n - It has a type drift layer 1. The front and back surfaces of the termination region 30 are included in the same plane as the front and back surfaces of the IGBT region 10 and the diode region 20, respectively. Also, the n of the termination region 30 - The drift layer 1 consists of n n regions of the IGBT region 10 and the diode region 20. - It has the same configuration as drift layer 1 and is constructed as a continuous, integrated unit.

[0067] n - On the front side of the drift layer 1, that is, the front side of the semiconductor substrate and n - A p-type termination well layer 31 is selectively provided between the p-type drift layer 1 and the other layer. The p-type termination well layer 31 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+14 / cm³. 3 ~1.0E+19 / cm 3 The p-type termination well layer 31 is provided surrounding the cell region which includes the IGBT region 10 and the diode region 20. The p-type termination well layer 31 is provided in multiple ring shapes, and the number of p-type termination well layers 31 is appropriately selected according to the breakdown voltage design of the semiconductor device 100. Furthermore, on the outer edge side of the p-type termination well layer 31 there is n + A channel stopper layer 32 is provided, n + The p-type channel stopper layer 32 surrounds the p-type terminal well layer 31 in a plan view.

[0068] n of the terminal region 30 - A p-type termination collector layer 16a is provided between the p-type drift layer 1 and the back surface of the semiconductor substrate. The p-type termination collector layer 16a is integrally formed with the p-type collector layer 16 provided in the IGBT region 10 of the cell region. Therefore, the p-type termination collector layer 16a may also be referred to as the p-type collector layer.

[0069] In a configuration where the diode region 20 is provided adjacent to the termination region 30 as in the semiconductor device 100 shown in FIG. 1, as shown in FIG. 11, the p-type termination collector layer 16a is provided such that the end on the diode region 20 side protrudes into the diode region 20 by a distance U2. According to such a configuration, the distance between the n + -type cathode layer 26 of the diode region 20 and the p-type termination well layer 31 can be increased. Therefore, it is possible to suppress the p-type termination well layer 31 from operating as the anode of the diode. The distance U2 may be, for example, 100 μm.

[0070] A collector electrode 7 is provided on the back surface of the semiconductor substrate. The collector electrode 7 is continuously and integrally formed from the cell region including the IGBT region 10 and the diode region 20 to the termination region 30.

[0071] On the front surface of the semiconductor substrate in the termination region 30, an emitter electrode 6 continuous from the cell region and a termination electrode 6a structurally separated from the emitter electrode 6 are provided. The emitter electrode 6 and the termination electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may be, for example, sinSiN (semi-insulating Silicon Nitride). The termination electrode 6a and each of the p-type termination well layer 31 and the n + -type channel stopper layer 32 are electrically connected via contact holes of the interlayer insulating film 4 provided on the front surface of the termination region 30. Further, in the termination region 30, a termination protective film 34 covering the emitter electrode 6, the termination electrode 6a, and the semi-insulating film 33 is provided. The termination protective film 34 is, for example, polyimide.

[0072] <Manufacturing Method of RC-IGBT> FIGS. 12 to 17 are cross-sectional views showing a manufacturing method of a semiconductor device that is an RC-IGBT. FIGS. 12 to 15 are diagrams showing steps mainly for forming the front surface side of the boundary region of FIG. 9 of the semiconductor device 100, and FIGS. 16 and 17 are diagrams showing steps mainly for forming the back surface side of the boundary region of FIG. 9 of the semiconductor device 100.

[0073] First, as shown in Figure 12(a), n - Prepare the semiconductor substrate that constitutes the n-type drift layer 1. The semiconductor substrate may be, for example, an FZ wafer fabricated by the FZ (Floating Zone) method, or an MCZ wafer fabricated by the MCZ (Magnetic field applied CZochralski) method, or an n-type wafer containing n-type impurities. The concentration of n-type impurities contained in the semiconductor substrate is appropriately selected depending on the breakdown voltage of the semiconductor device to be fabricated. For example, in a semiconductor device with a breakdown voltage of 1200V, the n-type impurities constituting the semiconductor substrate are selected. - The concentration of n-type impurities is adjusted so that the resistivity of the n-type drift layer 1 is approximately 40 to 120 Ω·cm. As shown in Figure 12(a), in the process of preparing the semiconductor substrate, the entire semiconductor substrate is n - This is a type drift layer 1. P-type or n-type impurity ions are implanted from the front side (first main surface) or the back side (second main surface) of the semiconductor substrate, and then diffused into the semiconductor substrate by heat treatment or the like, thereby forming a p-type or n-type semiconductor layer as appropriate, and the semiconductor device 100 is manufactured.

[0074] As shown in Figure 12(a), n - The semiconductor substrate constituting the p-type drift layer 1 has regions that will become IGBT regions 10 and diode regions 20. Although not shown in Figure 12(a), the substrate also has regions that will become termination regions 30, etc., surrounding the regions that will become IGBT regions 10 and diode regions 20. The following mainly describes the manufacturing method for the IGBT regions 10 and diode regions 20 of the semiconductor device 100, but the termination regions 30 of the semiconductor device 100 may be manufactured by known manufacturing methods. For example, when forming an FLR having a p-type termination well layer 31 as a voltage-resistant holding structure in the termination region 30, the p-type impurity ions may be implanted before processing the IGBT regions 10 and diode regions 20 of the semiconductor device 100 to form the FLR. Alternatively, the p-type impurity ions may be implanted simultaneously when ion-implanting p-type impurities into the IGBT regions 10 or diode regions 20 of the semiconductor device 100 to form the FLR.

[0075] Next, as shown in Figure 12(b), n-type impurities such as phosphorus (P) are implanted from the front side of the semiconductor substrate to form an n-type carrier storage layer 2. Additionally, p-type impurities such as boron (B) are implanted from the front side of the semiconductor substrate to form a p-type base layer 15 and a p-type anode layer 25. The n-type carrier storage layer 2, p-type base layer 15, and p-type anode layer 25 are formed by implanting impurity ions into the semiconductor substrate and then diffusing the impurity ions through heat treatment. Since the ion implantation of n-type and p-type impurities is performed after masking the front surface of the semiconductor substrate, the various layers are selectively formed on the front side of the semiconductor substrate. The n-type carrier storage layer 2, p-type base layer 15, and p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20, and are connected to the p-type termination well layer 31 in the termination region 30. An n-type carrier storage layer 2, a p-type base layer 15, and a p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20, and are connected to a p-type termination well layer 31 in the termination region 30. Masking is a process in which a resist is applied to a semiconductor substrate, an opening is formed in a predetermined area of ​​the resist using photolithography technology, and a mask is formed on the semiconductor substrate in order to perform ion implantation or etching on a predetermined area of ​​the semiconductor substrate through the opening.

[0076] The p-type impurities in the p-type base layer 15 and the p-type anode layer 25 may be ion-implanted simultaneously. In this case, the depth and p-type impurity concentration of the p-type base layer 15 and the p-type anode layer 25 will be the same. Alternatively, the p-type impurities in the p-type base layer 15 and the p-type anode layer 25 may be ion-implanted separately by masking, thereby causing the depth and p-type impurity concentration of the p-type base layer 15 and the p-type anode layer 25 to be different.

[0077] The p-type impurities in the p-type terminal well layer 31 and the p-type anode layer 25 of the terminal region 30, which are not shown in Figure 12(b), may be ion-implanted simultaneously. In this case, the depth and p-type impurity concentration of the p-type terminal well layer 31 and the p-type anode layer 25 will be the same. Alternatively, by using masks with different aperture ratios, the p-type impurities in the p-type terminal well layer 31 and the p-type anode layer 25 can be ion-implanted simultaneously, thereby making the p-type impurity concentrations of the p-type terminal well layer 31 and the p-type anode layer 25 different. In this case, one or both of the masks can be made into mesh masks with different aperture ratios.

[0078] Furthermore, by masking, the p-type impurities in the p-type terminal well layer 31 and the p-type anode layer 25 may be ion-implanted separately, thereby making the depth and p-type impurity concentration of the p-type terminal well layer 31 and the p-type anode layer 25 different from each other. Similarly, by using masks with different aperture ratios, the p-type impurities in the p-type terminal well layer 31, the p-type base layer 15, and the p-type anode layer 25 may be ion-implanted simultaneously.

[0079] Next, as shown in Figure 13(a), n-type impurities are selectively injected into the front side of the p-type base layer 15 of the IGBT region 10 by masking. + A p-type source layer 13 is formed. The n-type impurity to be implanted may be, for example, arsenic (As) or phosphorus (P). Alternatively, by masking, a p-type impurity can be selectively implanted into the front side of the p-type base layer 15 of the IGBT region 10. + A type contact layer 14 is formed, and p-type impurities are selectively injected into the front side of the p-type anode layer 25 of the diode region 20. + A p-type contact layer 24 is formed. The p-type impurity to be injected may be, for example, boron (B) or aluminum (Al).

[0080] Next, as shown in Figure 13(b), the p-type base layer 15 and the p-type anode layer 25 are penetrated from the front side of the semiconductor substrate, n - A trench 8 is formed that reaches the drift layer 1. In the IGBT region 10, n +The side walls of the trench 8 that penetrates the mold source layer 13 are n + Includes a portion of the type source layer 13. In the IGBT region 10, p + The side walls of the trench 8 penetrating the type contact layer 14 are p + Includes a portion of the type contact layer 14. In the diode region 20, p + The side walls of the trench 8 that penetrates the type contact layer 24 are p + Includes a portion of the type contact layer 24.

[0081] For example, the trench 8 is formed by depositing an oxide film such as SiO2 on a semiconductor substrate, then creating openings in the oxide film in the area where the trench 8 will be formed by a masking process, and finally etching the semiconductor substrate using the oxide film with the openings as a mask. In Figure 13(b), the pitch of the trenches 8 is the same in the IGBT region 10 and the diode region 20, but the pitch of the trenches 8 may be different in the IGBT region 10 and the diode region 20. The pitch of the trenches 8 and the pattern in plan view can be appropriately changed by the mask pattern of the masking process.

[0082] Next, as shown in Figure 14(a), the semiconductor substrate is heated in an oxygen-containing atmosphere to form an oxide film 9 on the inner wall of the trench 8 and on the surface of the semiconductor substrate. The oxide film 9 formed in the trench 8 of the IGBT region 10 becomes the gate trench insulating film 11b of the active trench gate 11 and the dummy trench insulating film 12b of the dummy trench gate 12. The oxide film 9 formed in the trench 8 of the diode region 20 becomes the diode trench insulating film 21b. The oxide film 9 formed on the surface of the semiconductor substrate is removed in a later process, except for the portion formed in the trench 8.

[0083] Next, as shown in Figure 14(b), polysilicon doped with n-type or p-type impurities is deposited on the oxide film 9 in the trench 8 by CVD (chemical vapor deposition) or the like to form the gate trench electrode 11a, the dummy trench electrode 12a, and the diode trench electrode 21a.

[0084] Next, as shown in Figure 15(a), an interlayer insulating film 4 is formed on the gate trench electrode 11a of the active trench gate 11 of the IGBT region 10. The interlayer insulating film 4 may be, for example, SiO2. The interlayer insulating film 4 shown in Figure 15(a) is formed by masking to create contact holes in the insulating film that will become the deposited interlayer insulating film 4 and to remove the oxide film 9 formed on the surface of the semiconductor substrate. The contact holes in the interlayer insulating film 4 are n + On type source layer 13, p + On the type contact layer 14, p + It is formed on the type contact layer 24, on the dummy trench electrode 12a, and on the diode trench electrode 21a.

[0085] Next, as shown in Figure 15(b), a barrier metal 5 is formed on the front surface of the semiconductor substrate and on the interlayer insulating film 4, and then an emitter electrode 6 is formed on the barrier metal 5. The barrier metal 5 is formed by depositing titanium nitride using PVD (physical vapor deposition) or CVD.

[0086] The emitter electrode 6 may be formed by depositing an aluminum-silicon alloy (Al-Si alloy) onto the barrier metal 5, for example, by PVD such as sputtering or vapor deposition. Alternatively, a nickel alloy (Ni alloy) may be further formed on the formed aluminum-silicon alloy by electroless plating or electrolytic plating to form the emitter electrode 6. Forming the emitter electrode 6 by plating allows for the easy formation of a thick metal film, thereby increasing the heat capacity of the emitter electrode 6 and improving its heat resistance. When forming the emitter electrode 6 from an aluminum-silicon alloy by PVD and then further forming a nickel alloy by plating, the plating process for forming the nickel alloy may be performed after processing the back side of the semiconductor substrate.

[0087] Next, as shown in Figure 16(a), the back side of the semiconductor substrate is ground to thin it to the predetermined thickness. The thickness of the semiconductor substrate after grinding may be, for example, 80 μm to 200 μm.

[0088] Next, as shown in Figure 16(b), n-type impurities are implanted from the back side of the semiconductor substrate to form an n-type buffer layer 3. Furthermore, p-type impurities are implanted from the back side of the semiconductor substrate to form a p-type collector layer 16. The n-type buffer layer 3 may be formed in the IGBT region 10, the diode region 20, and the termination region 30, or it may be formed only in the IGBT region 10 or the diode region 20. The n-type buffer layer 3 may be formed, for example, by implanting phosphorus (P) ions, or protons (H + The n-type buffer layer 3 may be formed by injecting phosphorus, or by injecting both protons and phosphorus. Protons can be injected deep into the back surface of the semiconductor substrate with relatively low acceleration energy. Furthermore, the depth to which protons are injected can be changed relatively easily by changing the acceleration energy. For this reason, when forming the n-type buffer layer 3 with protons, if multiple injections are performed while changing the acceleration energy, it is possible to form an n-type buffer layer 3 that is thicker in the thickness direction of the semiconductor substrate than when formed with phosphorus.

[0089] Furthermore, since phosphorus can have a higher activation rate as an n-type impurity compared to protons, forming an n-type buffer layer 3 with phosphorus can suppress punch-through of the depletion layer even in thin semiconductor substrates. To further thin the semiconductor substrate, it is preferable to form an n-type buffer layer 3 by implanting both protons and phosphorus, in which case the protons are implanted at a deeper position from the back surface than the phosphorus.

[0090] The p-type collector layer 16 may be formed, for example, by implanting boron (B). The p-type collector layer 16 is also formed in the termination region 30, and the p-type collector layer 16 in the termination region 30 becomes the p-type termination collector layer 16a. By irradiating the ion-implanted back surface of the semiconductor substrate with a laser and performing laser annealing, the implanted ions are activated and the p-type collector layer 16 is formed.

[0091] If phosphorus is implanted at a relatively shallow position on the back surface of the semiconductor substrate, the phosphorus will also be activated by laser annealing. Since protons are activated at relatively low annealing temperatures of 350°C to 500°C, when protons are implanted, care must be taken to ensure that the entire semiconductor substrate does not exceed 350°C to 500°C in any subsequent process other than the proton activation process. Laser annealing can raise the temperature only near the back surface of the semiconductor substrate, so it can be used to activate n-type and p-type impurities even after protons have been implanted.

[0092] Next, as shown in Figure 17(a), n + A type cathode layer 26 is formed. + The p-type cathode layer 26 may be formed by, for example, injecting phosphorus (P). As shown in Figure 17(a), a p-type collector layer 16 and n-type cathode layer 26 are formed at a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20. + n-type impurities are selectively injected from the back side by masking so that they are located at the boundary with the type cathode layer 26. + The amount of n-type impurities injected to form the n-type cathode layer 26 is greater than the amount of p-type impurities injected to form the p-type collector layer 16. + The depth of the p-type cathode layer 26 is greater than or equal to the depth of the p-type collector layer 16. + The region where the n-type cathode layer 26 is formed requires the injection of n-type impurities into the region where p-type impurities have been implanted to create an n-type semiconductor. Therefore, n + In all regions where the type cathode layer 26 is formed, the concentration of n-type impurities is higher than the concentration of p-type impurities.

[0093] Next, as shown in Figure 17(b), a collector electrode 7 is formed on the back surface of the semiconductor substrate. The collector electrode 7 is formed over the entire surface of the back surface, including the IGBT region 10, the diode region 20, and the termination region 30. Alternatively, the collector electrode 7 may be formed over the entire surface of the back surface of the n-type wafer, which is the semiconductor substrate. The collector electrode 7 may be formed by depositing aluminum-silicon alloy (Ai-Si alloy) or titanium (Ti) by PVD such as sputtering or vapor deposition, or by layering multiple metals such as aluminum-silicon alloy, titanium, nickel, or gold. Furthermore, the collector electrode 7 may be formed by further forming a metal film on a metal film formed by PVD using electroless plating or electrolytic plating.

[0094] The semiconductor device 100 is manufactured through the process described above. Typically, multiple semiconductor devices 100 are manufactured as a matrix integrated on a single semiconductor substrate, such as an n-type wafer. For this reason, the semiconductor devices 100 are individually cut by laser dicing or blade dicing.

[0095] <Polysilicon element> Figure 18 is a cross-sectional view showing the configuration of a semiconductor device according to this first embodiment. The semiconductor device according to this first embodiment comprises the RC-IGBT described above and the polysilicon element described below.

[0096] The semiconductor device shown in Figure 18 comprises a semiconductor substrate 51, a lower insulating film 52 which is a first insulating film, a polysilicon element 53, an upper insulating film 54 which is a second insulating film, a cathode electrode 55, and an anode electrode 56.

[0097] The semiconductor substrate 51 is the semiconductor substrate described in the RC-IGBT configuration, and has a first main surface, the front surface 51a, and a second main surface, the back surface 51b, and includes an energizing region. A first electrode is provided on the front surface 51a side of the energizing region, and a second electrode is provided on the back surface 51b side of the energizing region. In this embodiment 1, the energizing region is the IGBT region 10 and diode region 20 in Figure 9 through which the main current of the RC-IGBT is supplied, the first electrode is the emitter electrode 6 in Figure 9, and the second electrode is the collector electrode 7 in Figure 9. For convenience, the energizing region, the first electrode and the second electrode are described here as components of Figure 9, but they may be components of Figures 4, 5, 7, 8, etc.

[0098] The polysilicon element 53 is provided on the front surface 51a of the semiconductor substrate 51 via a lower insulating film 52. For example, the polysilicon element 53 is provided in regions other than the IGBT region 10 and the diode region 20, i.e., in regions such as the termination region 30 and the pad region 40 in Figures 1 and 2. The lower insulating film 52 may be, for example, a CVD film or a thermal oxide film.

[0099] The polysilicon element 53 is the first region of the first conductivity type n + The cathode region 53a of type 2 and the second region of type 2, p + The anode region 53b of the type and the third region of the second conductivity type, p - Includes the type drift region 53c. + Type cathode region 53a, p + Type anode region 53b, and p - The mold drift region 53c is provided on the lower insulating film 52.

[0100] n + The impurity concentration in the type cathode region 53a is shown in Figure 9, n + The impurity concentration may be the same as that of the type source layer 13, or p + The impurity concentration in the type anode region 53b is shown in Figure 9, p + The impurity concentration may be the same as that of the contact layer 14. - The impurity concentration in the drift region 53c is p +Lower than the impurity concentration in the type anode region 53b, p - The drift region 53c is n + Type cathode region 53a and p + It is located between the type anode region 53b and the other part.

[0101] The upper insulating film 54 covers at least the upper part of the polysilicon element 53, and in this embodiment 1, it covers the part of the polysilicon element 53 other than the lower part. Also in this embodiment 1, the thickness of the lower insulating film 52 described above is less than or equal to the thickness of the upper insulating film 54. The upper insulating film 54 may be a CVD film such as SiO2. The upper insulating film 54 is n + A contact hole that exposes the type cathode region 53a, and p + It has a contact hole that exposes the type anode region 53b.

[0102] The cathode electrode 55 is n + n + It is electrically connected to the type cathode region 53a. The anode electrode 56 is p + In the contact hole exposing the type anode region 53b, p + It is electrically connected to the type anode region 53b.

[0103] In the configuration described above, the polysilicon element 53 functions as a diode capable of conducting current in the in-plane direction. The polysilicon element 53 may be a temperature-sensing diode or a Zener diode.

[0104] Here, as shown in Figure 18, n in cross-sectional view + The width of the cathode region 53a, that is, its length in the in-plane direction, changes with respect to the upward direction, which is the direction from the back surface 51b of the semiconductor substrate 51 toward the front surface 51a. In the example in Figure 18, the n in cross-sectional view + The width of the cathode region 53a increases monotonically and continuously with respect to the upward direction, n + The cathode region 53a has a tapered shape that narrows downwards.

[0105] <Manufacturing method for polysilicon elements> Figure 19 is a flowchart showing a method for manufacturing a polysilicon element 53 according to this embodiment 1. The manufacturing method in Figure 19 is performed after preparing a semiconductor substrate 51 having a front surface 51a and a back surface 51b. Note that the RC-IGBT does not need to be completed on the semiconductor substrate 51 when the manufacturing method in Figure 19 is started, and the manufacturing of the polysilicon element 53 and the manufacturing of the RC-IGBT may be carried out in parallel.

[0106] In step S1, a lower insulating film 52 is formed on the front surface 51a of the semiconductor substrate 51. In step S2, a polysilicon film is uniformly formed on the lower insulating film 52. The thickness of the polysilicon film may be, for example, 700 nm or less, or 500 nm or less.

[0107] In step S3, p-type impurities are ion-implanted into the polysilicon film. The p-type impurities are, for example, boron (B) or aluminum (Al). In step S4, the polysilicon film is etched to match the shape of the polysilicon element 53 in Figure 18. In step S5, an annealing treatment is performed to diffuse the p-type impurities implanted into the polysilicon film. This results in a polysilicon element with substantially the same external shape as the polysilicon element 53. - The process of forming the molded polysilicon film on the lower insulating film 52 is completed.

[0108] In step S6, n-type impurities are ion-implanted into the first end of the polysilicon film. The n-type impurities are, for example, arsenic (As) or phosphorus (P). In this embodiment 1, a resist mask is used for ion implantation in step S6, in which the aperture ratio increases from the center of the polysilicon film toward the first end. As a result, as shown in Figures 20 and 21, for example, the proportion of the area of ​​the region 61a in which n-type impurities are ion-implanted increases from the center of the polysilicon film 61 toward the first end.

[0109] In step S7, p-type impurities are ion-implanted into the first end and the second end opposite to it of the polysilicon film. This completes the process of implanting n-conductivity impurities and p-type impurities into the separated first and second ends of the polysilicon film 61.

[0110] In step S8, an upper insulating film 54 is formed to cover the polysilicon film 61. In step S9, an annealing treatment is performed to flatten the upper insulating film 54 and diffuse impurities from the polysilicon film 61, thereby annealing the polysilicon film 61. + Type cathode region 53a, p + Type anode region 53b, and p - A type drift region 53c is formed. In step S6, the proportion of the area of ​​the region 61a where n-type impurities are ion-implanted increases towards the first end, so in cross-sectional view, n + The width of the cathode region 53a changes with respect to the upward direction, as shown in Figure 18.

[0111] The temperature of the annealing process in step S9 is, for example, 700°C to 1100°C, or 800°C to 900°C, and the annealing time is, for example, 60 minutes. The annealing process in step S9 is carried out in an atmosphere of, for example, at least one of N2, O2, or H2. When the n-type buffer layer 3 in Figure 16(b) is formed by proton ion implantation, it is preferable that the annealing process in step S9 is carried out before the formation of the n-type buffer layer 3.

[0112] In step S10, a contact hole is formed in the upper insulating film 54 to form the cathode electrode 55 and the anode electrode 56.

[0113] <Summary of Embodiment 1> According to the semiconductor device of this embodiment 1 described above, n in cross-sectional view +The width of the cathode region 53a changes with respect to the upward direction, which is the direction from the back surface 51b of the semiconductor substrate 51 toward the front surface 51a. With this configuration, the junction area of ​​the pn junction can be increased compared to a configuration in which the boundary of the pn junction in cross-sectional view extends without tilting in the vertical direction. As a result, if the polysilicon element 53 is a temperature sense diode, the forward voltage of the temperature sense diode can be reduced, and if the polysilicon element 53 is a Zener diode, the breakdown voltage of the Zener diode can be increased.

[0114] Furthermore, with the above configuration, the junction area of ​​the pn junction can be increased without increasing the area of ​​the polysilicon element 53 in plan view or increasing the thickness of the polysilicon element 53. For this reason, the junction area of ​​the pn junction can be increased without reducing the effective area, such as at least one of the IGBT region 10 and the diode region 20, or increasing the time for impurity diffusion.

[0115] Furthermore, in this embodiment 1, the thickness of the lower insulating film 52 is less than or equal to the thickness of the upper insulating film 54. With this configuration, for example, if the polysilicon element 53 is a temperature sense diode, the temperature sense diode is close to the semiconductor substrate 51, so the temperature of the element in the current-carrying region can be accurately detected.

[0116] In this embodiment 1, the upper insulating film 54 is flattened by annealing, and the polysilicon film 61 is n + Type cathode region 53a, p + Type anode region 53b, and p - This forms a type drift region 53c. With this configuration, n + Since a dedicated annealing process for impurity diffusion to form the cathode region 53a and other areas is not required, a reduction in manufacturing costs can be expected.

[0117] Furthermore, in this embodiment 1, the thickness of the polysilicon film 61 is 500 nm or less. With this configuration, the film formation time of the polysilicon film 61, n+ Since the annealing time and annealing temperature required for impurity diffusion to form the cathode region 53a and other areas can be reduced, a reduction in manufacturing costs can be expected.

[0118] <Variation> In Embodiment 1, for ion implantation in step S6, a resist mask was used in which the aperture ratio increases from the center of the polysilicon film toward the first edge, thereby increasing the area-to-unit ratio of the ion-implanted region 61a, as shown in Figures 20 and 21. However, the width changes in cross-sectional view n + The formation of the n-type cathode region 53a is not limited to this. For example, in step S6, n-type impurities may be implanted into the first end using a resist mask that opens the entire first end of the polysilicon film and oblique ion implantation. In this case as well, the width of the n-type impurities changes when viewed in cross-section. + A type cathode region 53a can be formed. Furthermore, by adjusting the temperature or time of the heat treatment for impurity diffusion in step S6, even if ions are implanted in a generally vertical direction, the width in cross-sectional view will not change. + A type cathode region 53a can be formed.

[0119] Furthermore, in Embodiment 1, n in cross-sectional view + The width of the cathode region 53a increases monotonically and continuously with respect to the upward direction, n + The cathode region 53a had a tapered shape that narrowed downwards, but the change in width was not limited to this. For example, in cross-sectional view, n + The width of the cathode region 53a may change in a stepped manner with respect to the upward direction. With such a configuration, the bonding area of ​​the pn junction can be further increased.

[0120] Also, for example, n in cross-sectional view + The width of the cathode region 53a may decrease rather than increase in the upward direction. Also, by combining, for example, oblique ion implantation, the n in cross-sectional view can be +The width of the cathode region 53a may decrease and then increase in the upward direction, or increase and then decrease.

[0121] Also, n + The impurity concentration in the cathode region 53a may have a gradient with respect to the upward direction. For example, in the configuration shown in Figure 18 of Embodiment 1, n + The impurity concentration in the cathode region 53a may be higher in the upward direction. With this configuration, the angle at which the boundary of the pn junction is inclined in the vertical direction can be increased, and as a result, the junction area of ​​the pn junction can be further increased.

[0122] Furthermore, p in cross-sectional view + The width of the type anode region 53b is n + Similar to the width of the cathode region 53a, it may vary with respect to the upward direction. With such a configuration, p - Since the width of the type drift region 53c can be substantially widened, the adjustment range of the output characteristics of the polysilicon element 53 can be expanded.

[0123] Furthermore, in the configuration shown in Figure 19, n + Type cathode regions 53a and p + The type anode region 53b is provided at the first and second ends of the polysilicon film 61, respectively, but is not limited to this. For example, as shown in Figure 22, in a plan view, p + The type anode region 53b is p - n via the drift region 53c + The cathode region 53a may also be enclosed.

[0124] Furthermore, in Embodiment 1, an RC-IGBT having an IGBT region 10 and a diode region 20 was provided in the energizing region, but this is not the only option. For example, the energizing region may consist of either the IGBT region 10 or the diode region 20, or it may consist of at least one of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), an SBD (Schottky Barrier Diode), or a PND (PN junction diode).

[0125] The details of the embodiment can be modified or omitted as appropriate.

[0126] The various aspects of this disclosure are summarized below as an appendix.

[0127] (Note 1) A semiconductor substrate having a first main surface and a second main surface, A polysilicon element provided on the first main surface via a first insulating film and Equipped with, The aforementioned semiconductor substrate is The current-carrying region includes a first electrode provided on the first main surface side and a second electrode provided on the second main surface side, The aforementioned polysilicon element is A first region of a first conductivity type and a second region of a second conductivity type are provided on the first insulating film, A third region of second conductivity type is provided between the first region and the second region, and the impurity concentration is lower than that of the second region. Includes, A semiconductor device in which the width of the first region in a cross-sectional view changes with respect to the direction from the second main surface to the first main surface.

[0128] (Note 2) The semiconductor device according to Appendix 1, wherein the width of the first region in a cross-sectional view changes with respect to the direction, so that the first region has a tapered shape.

[0129] (Note 3) The semiconductor device according to Appendix 1, wherein the width of the first region in a cross-sectional view changes in a step-like manner with respect to the direction.

[0130] (Note 4) The semiconductor device according to any one of the appendices 1 to 3, wherein the impurity concentration in the first region has a gradient with respect to the direction.

[0131] (Note 5) The semiconductor device according to any one of the appendices 1 to 4, wherein the polysilicon element is a temperature-sensing diode or a Zener diode.

[0132] (Note 6) The semiconductor device according to any one of the appendices 1 to 5, wherein the energized region is at least one of an IGBT region and a diode region.

[0133] (Note 7) The polysilicon element further comprises a second insulating film that covers at least the upper part of the polysilicon element, The semiconductor device according to any one of the appendices 1 to 6, wherein the thickness of the first insulating film is less than or equal to the thickness of the second insulating film.

[0134] (Note 8) A semiconductor device according to any one of the appendices 1 to 7, wherein the width of the second region in a cross-sectional view varies with respect to the direction.

[0135] (Note 9) A step of preparing a semiconductor substrate having a first main surface and a second main surface, A step of forming a first insulating film on the first main surface, A step of forming a second conductivity type polysilicon film on the first insulating film, The process involves injecting a first conductivity type impurity and a second conductivity type impurity into the separated portions of the polysilicon film, A step of forming a second insulating film that covers at least the upper part of the polysilicon film, The process includes a step of planarizing the second insulating film by annealing, and forming a first region of a first conductivity type, a second region of a second conductivity type, and a third region of a second conductivity type provided between the first and second regions and having a lower impurity concentration than the second region, A method for manufacturing a semiconductor device, wherein the width of the first region in a cross-sectional view changes in the direction from the second main surface toward the first main surface.

[0136] (Note 10) The method for manufacturing a semiconductor device according to Appendix 9, wherein the thickness of the polysilicon film is 500 nm or less. [Explanation of Symbols]

[0137] 6 Emitter electrode, 7 Collector electrode, 10 IGBT region, 20 Diode region, 51 Semiconductor substrate, 51a Front side, 51b Back side, 52 Lower insulating film, 53 Polysilicon element, 53a n + Type cathode region, 53b p + Type anode region, 53c p - Type drift region, 54 upper insulating film, 61 polysilicon film.

Claims

1. A semiconductor substrate having a first main surface and a second main surface, A polysilicon element provided on the first main surface via a first insulating film and Equipped with, The aforementioned semiconductor substrate is The current-carrying region includes a first electrode provided on the first main surface side and a second electrode provided on the second main surface side, The aforementioned polysilicon element is A first region of a first conductivity type and a second region of a second conductivity type are provided on the first insulating film, A third region of second conductivity type is provided between the first region and the second region, and the impurity concentration is lower than that of the second region. Includes, The width of the first region in the cross-sectional view changes with respect to the direction from the second principal surface to the first principal surface. A semiconductor device wherein the width of the first region in a cross-sectional view changes with respect to the direction, so that the first region has a tapered shape.

2. A semiconductor substrate having a first main surface and a second main surface, A polysilicon element provided on the first main surface via a first insulating film and Equipped with, The aforementioned semiconductor substrate is The current-carrying region includes a first electrode provided on the first main surface side and a second electrode provided on the second main surface side, The aforementioned polysilicon element is A first region of a first conductivity type and a second region of a second conductivity type are provided on the first insulating film, A third region of second conductivity type is provided between the first region and the second region, and the impurity concentration is lower than that of the second region. Includes, The width of the first region in the cross-sectional view changes with respect to the direction from the second principal surface to the first principal surface. A semiconductor device in which the width of the first region in a cross-sectional view changes in a step-like manner with respect to the direction.

3. A semiconductor device according to claim 1 or claim 2, A semiconductor device in which the impurity concentration in the first region has a gradient with respect to the direction.

4. A semiconductor device according to claim 1 or claim 2, The aforementioned polysilicon element is a temperature-sensing diode or a Zener diode, wherein the semiconductor device is a semiconductor device.

5. A semiconductor device according to claim 1 or claim 2, The current-carrying region is at least one of an IGBT region and a diode region, in a semiconductor device.

6. A semiconductor device according to claim 1 or claim 2, The polysilicon element further comprises a second insulating film that covers at least the upper part of the polysilicon element, A semiconductor device in which the thickness of the first insulating film is less than or equal to the thickness of the second insulating film.

7. A semiconductor device according to claim 1 or claim 2, A semiconductor device in which the width of the second region in a cross-sectional view changes with respect to the direction.

8. A step of preparing a semiconductor substrate having a first main surface and a second main surface, A step of forming a first insulating film on the first main surface, A step of forming a second conductivity type polysilicon film on the first insulating film, The process involves injecting a first conductivity type impurity and a second conductivity type impurity into the separated portions of the polysilicon film, A step of forming a second insulating film that covers at least the upper part of the polysilicon film, The process includes a step of planarizing the second insulating film by annealing, and forming a first region of a first conductivity type, a second region of a second conductivity type, and a third region of a second conductivity type provided between the first and second regions and having a lower impurity concentration than the second region, The width of the first region in a cross-sectional view changes with respect to the direction from the second main surface toward the first main surface. A method for manufacturing a semiconductor device, wherein the thickness of the polysilicon film is 500 nm or less.

9. A step of preparing a semiconductor substrate having a first main surface and a second main surface, A step of forming a first insulating film on the first main surface, A step of forming a second conductivity type polysilicon film on the first insulating film, The process involves injecting a first conductivity type impurity and a second conductivity type impurity into the separated portions of the polysilicon film, A step of forming a second insulating film that covers at least the upper part of the polysilicon film, The process includes a step of planarizing the second insulating film by annealing, and forming a first region of a first conductivity type, a second region of a second conductivity type, and a third region of a second conductivity type provided between the first and second regions and having a lower impurity concentration than the second region, The width of the first region in a cross-sectional view changes with respect to the direction from the second main surface toward the first main surface. The width of the first region in a cross-sectional view changes with respect to the direction, so that the first region has a tapered shape, or A method for manufacturing a semiconductor device, wherein the width of the first region in a cross-sectional view changes in a step-like manner with respect to the direction.

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