Method for manufacturing semiconductor devices and semiconductor manufacturing apparatus

Abstract

To provide a method for manufacturing a semiconductor device capable of easily and correctly sorting nondefective semiconductor chips and defective semiconductor chips.SOLUTION: A data acquisition step acquires the test results of an electric test conducted for a plurality of semiconductor chips. The test results are associated with arrangement information of the plurality of semiconductor chips. A cutting step cuts a semiconductor wafer with reference to a reference point set in the semiconductor wafer. An identification step identifies whether semiconductor chips having been subjected to a cutting process are nondefective or defective on the basis of appearance information of the semiconductor wafer having been subjected to a cutting process and the test results of semiconductor wafers before the cutting process. The semiconductor wafer having been subjected to the cutting process includes two or more semiconductor chips. The appearance information is an image in a region including a reference point.SELECTED DRAWING: Figure 1

Description

Technical Field

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[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor manufacturing apparatus.

Background Art

[0002] In order to correctly select good semiconductor chips and defective semiconductor chips, it is important to accurately match the position information of the semiconductor chips in the map data output as a result of the electrical test of the semiconductor elements with the position information of a large number of semiconductor chips actually formed on the semiconductor wafer. Patent Document 1 proposes a technique for preparing a reference pellet having an ink mark in a non-formation region where no semiconductor element is formed and inspecting good and defective pellets based on the coordinates based on the reference pellet.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] <​​​​​​​​​​​The method for manufacturing a semiconductor device according to this disclosure includes a data acquisition step, a cutting step, and an identification step. The data acquisition step acquires the test results of electrical tests performed on a plurality of semiconductor chips formed on a semiconductor wafer. The test results are associated with the arrangement information of the plurality of semiconductor chips. The cutting step cuts the semiconductor wafer with respect to a base point set within the semiconductor wafer to form a cut semiconductor wafer. The identification step identifies at least one of good semiconductor chips and defective semiconductor chips in the cut semiconductor wafer based on the appearance information of the cut semiconductor wafer and the test results of the semiconductor wafer before cutting. The cut semiconductor wafer contains two or more semiconductor chips. The appearance information is an image of the region including the base point. [Effects of the Invention]

[0007] According to this disclosure, a method for manufacturing a semiconductor device is provided that makes it possible to easily and correctly sort good semiconductor chips from defective semiconductor chips.

[0008] The purpose, features, aspects, and advantages of this disclosure will become clearer from the following detailed description and accompanying drawings. [Brief explanation of the drawing]

[0009] [Figure 1] This figure shows the configuration of the semiconductor manufacturing apparatus in Embodiment 1. [Figure 2] This diagram shows the configuration of the semiconductor wafer under test. [Figure 3] This figure shows the configuration of the cut semiconductor wafer in Embodiment 1. [Figure 4] This is a flowchart showing the method for manufacturing a semiconductor device in Embodiment 1. [Figure 5] This figure shows an example of a matrix search. [Figure 6] This figure shows the configuration of the cut semiconductor wafer in Embodiment 2. [Figure 7] This figure shows the configuration of the cut semiconductor wafer in Embodiment 3. [Figure 8] This figure shows the configuration of the cut semiconductor wafer in Embodiment 4. [Figure 9] This figure shows the configuration of the cut semiconductor wafer in Embodiment 5. [Modes for carrying out the invention]

[0010] <Embodiment 1> Figure 1 shows the configuration of the semiconductor manufacturing apparatus 100 in Embodiment 1. Figure 2 shows the configuration of the semiconductor wafer 10 in Embodiment 1. The semiconductor manufacturing apparatus 100 performs electrical testing on a plurality of semiconductor chips 1 formed on the semiconductor wafer 10.

[0011] Multiple semiconductor chips 1 are arranged in a matrix along a first direction and a second direction on the surface of a semiconductor wafer 10. The second direction is perpendicular to the first direction. Dicing lines 2 are defined between the multiple semiconductor chips 1, extending in the first and second directions. In the dicing process described later, the multiple semiconductor chips 1 are separated from each other along the dicing lines 2. The planar shape of each semiconductor chip 1 is rectangular. The semiconductor wafer 10 includes an effective region 3 and an ineffective region 4. The effective region 3 corresponds to the area where the semiconductor chips 1 are formed. The ineffective region 4 is located outside the effective region 3 and corresponds to the area where semiconductor chips 1 are not formed.

[0012] The semiconductor chip 1 is formed from a semiconductor such as Si. Preferably, the semiconductor chip 1 is formed from a so-called wide-bandgap semiconductor such as SiC, GaN, Ga2O3, or diamond. The semiconductor chip 1 includes a diode element or a switching element as a semiconductor element (not shown). The diode element is, for example, a Schottky barrier diode. The switching element is an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0013] The semiconductor manufacturing apparatus 100 includes a wafer testing unit 20, a data acquisition unit 30, a transfer unit 40, a setting unit 50, a cutting unit 60, and an identification unit 70.

[0014] The wafer test unit 20 includes a test prober 21. The wafer test unit 20 applies current or voltage to each of the multiple semiconductor chips 1 and evaluates the electrical characteristics of those semiconductor chips 1 to perform an electrical test. The current or voltage is applied via a probe (not shown) of the test prober 21. The wafer test unit 20 outputs the evaluation results as the test results of the electrical test of the semiconductor chips 1.

[0015] The test results are associated with the placement information of multiple semiconductor chips 1. For example, the test results are wafer map data. The wafer map data includes the position information on the semiconductor wafer 10 for at least one of the good semiconductor chips and the defective semiconductor chips. In other words, the test results include the determination information and position information for at least one of the good semiconductor chips and the defective semiconductor chips. The determination information for a defective semiconductor chip is indicated, for example, by "×" in the wafer map data. Furthermore, the test results store not only the position information of good or defective semiconductor chips, but also the placement information of multiple semiconductor chips 1, i.e., the overall placement information. The position information and placement information are, for example, the coordinate data of the semiconductor chip 1.

[0016] The data acquisition unit 30 acquires the test results of electrical tests performed on a plurality of semiconductor chips 1 formed on the semiconductor wafer 10.

[0017] The transfer unit 40 includes, for example, a carrier that holds the semiconductor wafer 10 and a moving stage that transports the carrier with high precision. The transfer unit 40 moves between the wafer test unit 20 and the cutting unit 60.

[0018] The setting unit 50 sets a reference point 5, which serves as a reference when cutting the semiconductor wafer 10 in a cutting process described later, within the semiconductor wafer 10. The reference point 5 is a reference for the cutting section. The reference point 5 is set, for example, on the dicing line 2. Alternatively, the reference point 5 may be set on a line connecting a plurality of alignment marks used for alignment during photolithography (photoprinting). The reference point 5 corresponds to the point where those lines intersect. The reference point 5 is preferably set at the corner of a semiconductor chip formed on the outer peripheral side of the semiconductor wafer 10 among the plurality of semiconductor chips 1 formed within the effective region 3. The reference point 5 is preferably set at the corner of the outermost semiconductor chip formed in the effective region 3. By setting the reference point 5 at such a position, the good semiconductor chips within the effective region 3 are not cut in the cutting process. Also, the cutting section is set to a minimum. Even when the semiconductor wafer 10 has a large diameter size such as 8 inches or 12 inches, the cutting section is minimized.

[0019] The cutting unit 60 performs a cutting process and a fragmentation process. In the cutting process, the cutting unit 60 cuts the semiconductor wafer 10 with reference to a base point 5 set within the semiconductor wafer 10. The cut semiconductor wafer 10 is hereinafter referred to as a cut semiconductor wafer. Figure 3 is a diagram showing the configuration of a cut semiconductor wafer 11 in Embodiment 1. The cut semiconductor wafer 11 contains two or more semiconductor chips 1. Preferably, the cut semiconductor wafer 11 contains all of the multiple semiconductor chips 1 that were formed on the semiconductor wafer 10 before cutting. Also, in Embodiment 1, the cutting unit 60 cuts from the base point 5 to the edge of the semiconductor wafer 10. The cut surface of the cut semiconductor wafer 11 is formed in a first direction and a second direction from the base point 5. In Embodiment 1, the cutting direction is preferably along the first direction and the second direction, which are the arrangement directions of the semiconductor chips 1, but the cutting direction is not limited to these. In the dicing process, the cutting unit 60 dices the cut semiconductor wafer 11 to separate the multiple semiconductor chips 1 from each other.

[0020] The cutting unit 60 includes a laser oscillator 61 and a camera 62. The laser oscillator 61 cuts the semiconductor wafer 10 or the cut semiconductor wafer 11 with a laser as described above. The laser oscillator 61 is, for example, a YAG laser. The cutting unit 60 may also include a blade (not shown). The semiconductor wafer 10 may be cut by the blade. However, cutting with a blade has limitations on the cutting width. This limitation is due to the size of the diamond particles contained in the blade and the mechanical strength of the blade. Also, because the blade directly touches the semiconductor wafer 10, chipping may occur in the semiconductor chip 1 due to vibration and shock during cutting. For this reason, laser cutting, which can cut without contact and minimize the cutting width, is preferred. The camera 62 captures an image including the base point 5 in the cut semiconductor wafer 11. For example, the camera 62 captures an image including at least one semiconductor chip 1 around the base point 5 and the cut section 6 cut with respect to the base point 5. In this case, the camera 62 may automatically recognize the cut section 6 and photograph the area including the base point 5 and the semiconductor chip 1, or it may acquire information about the base point 5 from the setting unit 50 and photograph the area including the base point 5 and the semiconductor chip 1.

[0021] The identification unit 70 identifies at least one of good semiconductor chips and defective semiconductor chips in the cut semiconductor wafer 11 based on the appearance information of the cut semiconductor wafer 11 and the test results of the semiconductor wafer 10 before cutting. The appearance information is the image shown above. The identification unit 70 in Embodiment 1 includes a first identification unit 71 and a second identification unit 72.

[0022] The first identification unit 71 compares the presence or absence of semiconductor chips 1 in a predetermined range around the base point 5 based on the above image, which is the visual information, and the arrangement information of the multiple semiconductor chips 1 in the test results. The predetermined range is an arbitrary range and can be changed. The determination of the presence or absence of semiconductor chips 1 in the image is performed by image analysis. The image analysis is performed based on, for example, the shape information, area information, dicing sheet, and color information of the semiconductor chip 1. The identification unit 70 then identifies a reference chip 7 in the predetermined range. The reference chip 7 may be a semiconductor chip 1 or a chip in the invalid region 4. The chip in the invalid region 4 corresponds to the area defined by the multiple dicing lines 2 extending into the invalid region 4.

[0023] The second identification unit 72 identifies the location of at least one of the good semiconductor chips and defective semiconductor chips on the cut semiconductor wafer 11, using its reference chip 7 as a reference.

[0024] The functions of the data acquisition unit 30, the setting unit 50, the first identification unit 71, and the second identification unit 72 are realized by a processing circuit (not shown) provided in the semiconductor manufacturing apparatus 100. The processing circuit includes, for example, a processor and memory. The functions of the data acquisition unit 30, the setting unit 50, the first identification unit 71, and the second identification unit 72 are realized by the processor executing a program stored in memory.

[0025] Figure 4 is a flowchart showing the method for manufacturing a semiconductor device in Embodiment 1.

[0026] Step S1 is a formation process. In step S1, a plurality of semiconductor chips 1 are formed on a semiconductor wafer 10. The semiconductor chips 1 are arranged in a matrix along a first direction and a second direction.

[0027] Step S2 is the inspection process. The wafer test unit 20 performs an electrical test on each of the multiple semiconductor chips 1 formed on the semiconductor wafer 10. During this process, current or voltage is applied to each semiconductor chip 1 via the probe of the test prober 21. The wafer test unit 20 detects good semiconductor chips and defective semiconductor chips.

[0028] Step S3 is the data acquisition process. The data acquisition unit 30 acquires the test results of the electrical test. These test results are associated with the placement information of multiple semiconductor chips 1. The test results are wafer map data. The wafer map data includes determination information and location information of defective semiconductor chips. The wafer map data also stores the placement information of multiple semiconductor chips 1.

[0029] Step S4 is a setting step. The setting unit 50 sets a reference point 5 within the semiconductor wafer 10, which will serve as the reference point when cutting the semiconductor wafer 10 in the next cutting step. In Embodiment 1, the reference point 5 is set at the point where the two dicing lines 2 intersect. As shown in Figure 2, the reference point 5 is set at the corner of a semiconductor chip formed on the outer periphery of the semiconductor wafer 10, among the multiple semiconductor chips 1 within the effective region 3.

[0030] Step S5 is the cutting process. The cutting unit 60 cuts the semiconductor wafer 10 with respect to a base point 5 set within the semiconductor wafer 10 to form a cut semiconductor wafer 11. The cut semiconductor wafer 11 contains two or more semiconductor chips 1. In Embodiment 1, as shown in Figure 3, the cutting unit 60 cuts from the base point 5 to the edge of the semiconductor wafer 10. At that time, the cutting unit 60 cuts the semiconductor wafer 10 along a first direction and a second direction. The semiconductor wafer 10 is cut by, for example, a YAG laser. The cut surface is formed from the base point 5 in the first direction and the second direction. Through this cutting process, a cut section 6, which is a part of the semiconductor wafer 10, is separated, and a cut semiconductor wafer 11 is formed.

[0031] Step S6 is the mounting process. The cut semiconductor wafer 11 is mounted on a dicing sheet (not shown). A tape (not shown) supported by a ring frame (not shown) is attached to one main surface of the cut semiconductor wafer 11.

[0032] Step S7 is the first identification step. The camera 62 captures an image including at least one semiconductor chip 1 around the base point 5 on the cut semiconductor wafer 11 and the cut section 6 cut relative to the base point 5.

[0033] The first identification unit 71 compares the image with the arrangement information of the semiconductor chip 1 to determine whether or not the semiconductor chip 1 is present in a predetermined range around the base point 5. Based on the comparison result, the first identification unit 71 identifies a reference chip 7 in the predetermined range. An example of the first identification step is described below.

[0034] The first identification unit 71 performs a matrix search on a predetermined range around the base point 5. Figure 5 shows an example of a matrix search. As an example, the predetermined range is the same size as the area where three semiconductor chips 1 are arranged horizontally and vertically. In this case, the first identification unit 71 designates a semiconductor chip 1 adjacent to the base point 5 as a provisional reference chip 7A. The first identification unit 71 sets a predetermined range centered on the provisional reference chip 7A and performs a matrix search. Specifically, the first identification unit 71 obtains information regarding the presence or absence of semiconductor chips 1 in that range by image analysis. As shown in Figure 5, semiconductor chips 1 are not provided on the upper and upper right sides of the central part of that range. Semiconductor chips 1 are provided in the other areas. In addition, the wafer map data obtained by the first identification unit 71 as a test result stores arrangement information of multiple semiconductor chips 1 during electrical testing. The first identification unit 71 compares the results of the matrix search with the arrangement information. If the results of the matrix search match the placement information, the provisional reference chip 7A at the center of the search range is identified as the reference chip 7.

[0035] Step S8 is the second identification step. The second identification unit 72 identifies the location of good semiconductor chips on the cut semiconductor wafer 11, using its reference chip 7 as a reference. For example, the second identification unit 72 overlays the location of the reference chip 7 with the placement information in the wafer map data to identify semiconductor chips 1 other than defective semiconductor chips and to determine their locations.

[0036] Step S9 is a dicing process. The cutting unit 60 dices the cut semiconductor wafer 11 to separate the multiple semiconductor chips 1 from each other.

[0037] Step S10 is the pickup process. Based on the position information of good semiconductor chips, good semiconductor chips are accurately picked up from multiple semiconductor chips 1. Defective semiconductor chips are discarded during this pickup process.

[0038] According to the above semiconductor device manufacturing method, it becomes possible to easily and correctly separate good semiconductor chips from defective semiconductor chips without using ink.

[0039] In the above manufacturing method, the data acquisition unit 30 acquires information on defective semiconductor chips, and the second identification unit 72 identifies good semiconductor chips based on the information on the defective semiconductor chips. The test results acquired by the data acquisition unit 30 may be information on good semiconductor chips, or information on both defective and good semiconductor chips. Furthermore, the semiconductor chip 1 identified by the second identification unit 72 may be a defective semiconductor chip, or both defective and good semiconductor chips.

[0040] The first and second identification steps are performed between the mounting step and the individualization step, but may also be performed after the individualization step. In that case, the identification steps are performed on multiple individualized semiconductor chips 1. Even in this case, good semiconductor chips are accurately picked from the multiple semiconductor chips 1.

[0041] Furthermore, the first and second identification steps are examples of functions and operations performed by the identification unit 70 and are not limited to those described above. The identification unit 70 identifies at least one of good semiconductor chips and defective semiconductor chips based on the appearance information of the cut semiconductor wafer 11 and the test results of the semiconductor wafer 10 before cutting. The appearance information may be an image of the region including the base point 5, preferably an image including the semiconductor chips 1 around the base point 5 and the cut section 6. By analyzing the image, the identification unit 70 can compare the positional information of the semiconductor chips 1 in the image with the arrangement information during the test. Based on the comparison result, the position of the good semiconductor chip or the defective semiconductor chip is identified.

[0042] In summary, the semiconductor device manufacturing method in Embodiment 1 includes a data acquisition step, a cutting step, and an identification step. The data acquisition step acquires the test results of electrical tests performed on a plurality of semiconductor chips 1 formed on a semiconductor wafer 10. These test results are associated with the arrangement information of the plurality of semiconductor chips 1. The cutting step cuts the semiconductor wafer 10 with respect to a base point 5 set within the semiconductor wafer 10 to form a cut semiconductor wafer 11. The identification step identifies at least one of good semiconductor chips and defective semiconductor chips in the cut semiconductor wafer 11 based on the appearance information of the cut semiconductor wafer 11 and the test results of the semiconductor wafer 10 before cutting. The cut semiconductor wafer 11 contains two or more semiconductor chips 1. The appearance information is an image of the region including the base point 5.

[0043] This method of manufacturing semiconductor devices makes it possible to easily and correctly separate good semiconductor chips from defective semiconductor chips.

[0044] Since the sorting process between good and defective semiconductor chips is made inkless, ink management becomes unnecessary. For example, the ink drying process is eliminated, and the problem of ink peeling during dicing does not occur. In addition, the work of selecting new ink when the production of the old ink ends is also unnecessary. As semiconductor wafers 10 are becoming larger in diameter and semiconductor chips 1 are becoming smaller, the number of semiconductor chips 1 formed on one semiconductor wafer 10 is increasing. According to the manufacturing method of Embodiment 1, the process of applying ink to the reference chip 7 or defective semiconductor chips is unnecessary, thus reducing the load on the prober. In addition, the situation of ink flowing to adjacent semiconductor chips 1 does not occur.

[0045] During the mounting process, when mounting the semiconductor wafer 10 onto the dicing sheet, the dicing sheet expands. The outer edge of the semiconductor wafer 10 is more prone to stretching than the center due to the expansion. This can unintentionally cause center misalignment and θ misalignment of the semiconductor wafer 10. This results in a discrepancy between the pre-registered position information of the semiconductor chip 1 and its actual position information. Such discrepancies affect the accuracy of sorting between good and defective semiconductor chips. However, in the manufacturing method of Embodiment 1, the accuracy of recognizing the position of the semiconductor chip 1 on the dicing sheet is improved, making it possible to easily and correctly sort between good and defective semiconductor chips. Therefore, productivity in the semiconductor device manufacturing process is improved.

[0046] <Embodiment 2> In Embodiment 2, components similar to those in Embodiment 1 are given the same reference numerals, and their detailed descriptions are omitted.

[0047] Figure 6 shows the configuration of the cut semiconductor wafer 12 in Embodiment 2. The semiconductor wafer 10 is a rimmed semiconductor wafer. The rimmed semiconductor wafer includes a rim portion 10A and a central portion 10B. The rim portion 10A is provided along the outer circumference of the rimmed semiconductor wafer. The central portion 10B is provided inward from the rim portion 10A. The thickness of the rim portion 10A is greater than the thickness of the central portion 10B.

[0048] The cutting process in Embodiment 2 includes a cutting section formation process and a rim cutting process. In the cutting section formation process, the cutting section 60 cuts out a cutting section 6, which is located in the central section 10B and adjacent to the base point 5. The base point 5 is set in the setting process, as in Embodiment 1. Preferably, the cutting section 6 is located in the inactive region 4, which is provided outside the active region 3 on which the semiconductor chip 1 is formed. The cutting section 6 may also be cut along the dicing line 2 and have the same chip shape as the semiconductor chip 1. In the rim cutting process, the cutting section 60 cuts the rim section 10A. The other processes are the same as in Embodiment 1.

[0049] In a semiconductor wafer with a rim, the thickness of the rim portion 10A is greater than that of the central portion 10B. Therefore, it is difficult for the cutting portion 60 to cut from the base point 5 to the edge of the semiconductor wafer 10. According to the semiconductor device manufacturing method of Embodiment 2, the reference chip 7 is identified in the same way as in Embodiment 1 by cutting out the cutting section 6 around the base point 5. This prevents discrepancies between wafer map data and actual location information when identifying defective semiconductor chips. Therefore, productivity in the semiconductor device manufacturing process is improved.

[0050] <Embodiment 3> In Embodiment 3, components similar to those in Embodiment 1 or 2 are given the same reference numerals, and their detailed descriptions are omitted.

[0051] Figure 7 shows the configuration of the cut semiconductor wafer 13 in Embodiment 3. In the cutting process, the cutting portion 60 cuts at the boundary between the effective region 3 and the ineffective region 4 based on the base point 5. In other words, in the cutting process, all of the ineffective region 4 on which the semiconductor chip 1 is not formed is cut out.

[0052] According to the semiconductor device manufacturing method of Embodiment 3, the phenomenon of chips in the invalid region 4 being picked up during the pickup process cannot occur. The outflow of chips in the invalid region 4 is prevented. In this manufacturing method, it is impossible to set chips outside the effective region 3, i.e., chips in the invalid region 4, as the reference chip 7. The reference chip 7 is specified in the effective region 3. Therefore, when picking up good semiconductor chips in the pickup process, it is preferable that the reference chip 7 is picked up last.

[0053] <Embodiment 4> In Embodiment 4, components similar to those in Embodiments 1 to 3 are given the same reference numerals, and their detailed descriptions are omitted.

[0054] Figure 8 shows the configuration of the cut semiconductor wafer 14 in Embodiment 4. The semiconductor wafer 10 includes an effective region 3 and an ineffective region 4.

[0055] The boundary between the effective region 3 and the inactive region 4 includes a first boundary portion 8A extending in a first direction and a second boundary portion 8B extending in a second direction. The first boundary portion 8A is located between the inactive region 4 and the semiconductor chip 1 that is closest to the outer edge of the semiconductor wafer 10 in the second direction. The second boundary portion 8B is located between the inactive region 4 and the semiconductor chip 1 that is closest to the outer edge of the semiconductor wafer 10 in the first direction.

[0056] In Embodiment 4, the base point 5 is set at the intersection of a first virtual line 9A, which is a virtual extension of the first boundary 8A, and a second virtual line 9B, which is a virtual extension of the second boundary 8B.

[0057] In the setting process, the setting unit 50 may detect the first boundary 8A and the second boundary 8B based on the image of the semiconductor wafer 10 captured by the camera 62, and automatically set the intersection of the first virtual line 9A and the second virtual line 9B as the base point 5.

[0058] In the cutting process, the cutting unit 60 cuts the semiconductor wafer 10 along the first virtual line 9A and the second virtual line 9B. The cutting process includes a first cutting process and a second cutting process. In the first cutting process, the cutting unit 60 cuts the semiconductor wafer 10 along the first virtual line 9A with respect to the base point 5. This separates the first cutting section 6A, which is the edge of the semiconductor wafer 10. In the second cutting process, the semiconductor wafer 10 is cut along the second virtual line 9B. This separates the second cutting section 6B, which is the edge of the semiconductor wafer 10.

[0059] In the first identification step, the first identification unit 71 identifies the reference chip 7 based on an image of external information that includes the first cutting section 6A, the second cutting section 6B, and the surrounding semiconductor chip 1 centered on the base point 5. At this time, the first identification unit 71 identifies the reference chip 7 within a predetermined range based on the result of matching the wafer map data with the image, similar to Embodiment 1. Alternatively, in Embodiment 4, the first identification unit 71 may identify the semiconductor chip 1 located within a predetermined distance from the base point 5 as the reference chip 7. This method simplifies the identification of the reference chip 7 and improves productivity in the semiconductor device manufacturing process.

[0060] This semiconductor device manufacturing method does not require complex cutting paths. A pre-cut semiconductor wafer 14 is realized in two cutting steps. The first boundary 8A and the second boundary 8B have long straight lines within the boundaries. Since the coordinate system is recognized from such long straight lines, the position of good or defective semiconductor chips can be recognized with higher accuracy.

[0061] <Embodiment 5> In Embodiment 5, components similar to those in any of Embodiments 1 to 4 are given the same reference numerals, and their detailed descriptions are omitted.

[0062] Figure 9 shows the configuration of the cut semiconductor wafer 15 in Embodiment 5. In the cutting process, the cutting unit 60 cuts only at least one defective semiconductor chip 1A based on the test results. More specifically, the cutting unit 60 cuts out the defective semiconductor chip 1A that was determined to be defective in the inspection process and marked with an "×" or the like in the wafer map data. At this time, the cutting unit 60 identifies the defective semiconductor chip 1A by overlaying and comparing the pre-registered wafer information with the wafer map acquired in the data acquisition process.

[0063] Even if the reference chip 7 is misaligned after the mounting process, the defective semiconductor chip 1A has already been cut out. There is no risk of the defective semiconductor chip 1A being picked up during the pickup process, thus preventing its outflow.

[0064] This disclosure allows for the free combination of each embodiment, and enables the modification or omission of each embodiment as appropriate.

[0065] The various aspects of this disclosure are summarized below as an appendix.

[0066] (Note 1) A data acquisition step involves acquiring test results of electrical tests performed on multiple semiconductor chips formed on a semiconductor wafer, wherein the test results are associated with the arrangement information of the multiple semiconductor chips. A cutting step in which the semiconductor wafer is cut with reference to a base point set within the semiconductor wafer to form a cut semiconductor wafer, The system includes an identification step that identifies at least one of good semiconductor chips and defective semiconductor chips in the cut semiconductor wafer based on the appearance information of the cut semiconductor wafer and the test results of the semiconductor wafer before cutting, The aforementioned cut semiconductor wafer includes two or more semiconductor chips, A method for manufacturing a semiconductor device, wherein the aforementioned appearance information is an image of the region including the base point.

[0067] (Note 2) The above image shows a semiconductor device manufacturing method according to Appendix 1, which includes a semiconductor chip around the base point in the cut semiconductor wafer and a cut section cut with respect to the base point.

[0068] (Note 3) The plurality of semiconductor chips are arranged in a matrix along a first direction and a second direction orthogonal to the first direction on the surface of the semiconductor wafer. A method for manufacturing a semiconductor device according to Appendix 1 or Appendix 2, wherein the cut surface of the cut semiconductor wafer is formed in the first direction and the second direction from the base point.

[0069] (Note 4) The method for manufacturing a semiconductor device according to any one of the appendices 1 to 3, wherein the cutting step includes cutting from the base point to the edge of the semiconductor wafer.

[0070] (Note 5) The semiconductor wafer is a rimmed semiconductor wafer, The rimmed semiconductor wafer includes a rim portion provided along the outer circumference of the rimmed semiconductor wafer and a central portion provided inside the rim portion. The thickness of the rim portion is greater than the thickness of the central portion. The aforementioned cutting process is, A cutting section formation step involves cutting out a cutting section which is a region located within the central part and adjacent to the base point, A method for manufacturing a semiconductor device according to any one of the appendices 1 to 4, comprising a rim cutting step of cutting the rim portion.

[0071] (Note 6) The method for manufacturing a semiconductor device according to any one of Appendix 1 to Appendix 5, wherein the cutting step includes cutting at the boundary between an effective region on which the plurality of semiconductor chips are formed and an inactive region on which the plurality of semiconductor chips are not formed, based on the reference point.

[0072] (Note 7) The reference point is set at the intersection of a first virtual line, which is a virtual extension of the first boundary portion extending in the first direction, and a second virtual line, which is a virtual extension of the second boundary portion extending in the second direction, of the boundary between the effective region where the plurality of semiconductor chips are formed and the inactive region where the plurality of semiconductor chips are not formed. The first boundary portion included in the first virtual line is located between the semiconductor chip closest to the outer edge of the semiconductor wafer in the second direction and the invalid region among the plurality of semiconductor chips, The second boundary portion included in the second virtual line is located between the semiconductor chip closest to the outer edge of the semiconductor wafer in the first direction and the invalid region among the plurality of semiconductor chips, The method for manufacturing a semiconductor device according to Appendix 3, wherein the cutting step includes cutting the semiconductor wafer along the first virtual line and the second virtual line.

[0073] (Note 8) The method for manufacturing a semiconductor device according to any one of Appendix 1 to Appendix 7, wherein the cutting step includes cutting only the defective semiconductor chips based on the test results.

[0074] (Note 9) A mounting step of mounting the cut semiconductor wafer onto a dicing sheet, The process further comprises a dicing step, after the mounting step, in which the cut semiconductor wafer is diced to separate the plurality of semiconductor chips from each other. The method for manufacturing a semiconductor device according to any one of the appendices 1 to 8, wherein the identification step is performed between the mounting step and the individualization step, or after the individualization step.

[0075] (Note 10) The aforementioned identification step is, A first identification step involves comparing the presence or absence of semiconductor chips in a predetermined range around the base point based on the aforementioned image and the arrangement information of the plurality of semiconductor chips in the test results, and identifying a reference chip in the predetermined range. A method for manufacturing a semiconductor device according to any one of the appendices 1 to 9, comprising: a second identification step of identifying the position of at least one of the good semiconductor chips and the defective semiconductor chips on the cut semiconductor wafer with reference to the aforementioned reference chip.

[0076] (Note 11) The method for manufacturing a semiconductor device according to any one of the appendices 1 to 10, wherein the test results include wafer map data having positional information on the semiconductor wafer for at least one of the good semiconductor chips and the defective semiconductor chips.

[0077] (Note 12) A data acquisition unit that acquires test results of electrical tests performed on multiple semiconductor chips formed on a semiconductor wafer, the test results being associated with the arrangement information of the multiple semiconductor chips, A cutting unit that cuts the semiconductor wafer with respect to a base point set within the semiconductor wafer to form a cut semiconductor wafer, The system includes an identification unit that identifies at least one of good semiconductor chips and defective semiconductor chips in the cut semiconductor wafer based on the appearance information of the cut semiconductor wafer and the test results of the semiconductor wafer before cutting, The aforementioned cut semiconductor wafer includes two or more semiconductor chips, The aforementioned external information is an image of the region including the base point, in a semiconductor manufacturing apparatus.

[0078] (Note 13) The aforementioned image shows the semiconductor manufacturing apparatus according to Appendix 12, which includes semiconductor chips around the base point in the cut semiconductor wafer and a cut section cut with respect to the base point.

[0079] (Note 14) The plurality of semiconductor chips are arranged in a matrix along a first direction and a second direction orthogonal to the first direction on the surface of the semiconductor wafer. The semiconductor manufacturing apparatus according to Appendix 12 or Appendix 13, wherein the cut surface of the cut semiconductor wafer is formed in the first direction and the second direction from the base point.

[0080] (Note 15) The aforementioned identification unit is A first identification unit that, based on the aforementioned image and the arrangement information of the plurality of semiconductor chips in the test results, checks for the presence or absence of semiconductor chips in a predetermined range around the base point and identifies a reference chip in the predetermined range, A semiconductor manufacturing apparatus according to any one of the appendices 12 to 14, comprising: a second identification unit that identifies the position of at least one of the good semiconductor chips and the defective semiconductor chips on the cut semiconductor wafer with respect to the aforementioned reference chip.

[0081] (Note 16) The semiconductor manufacturing apparatus according to any one of Appendix 12 to Appendix 15, wherein the test results include wafer map data having positional information on the semiconductor wafer for at least one of the good semiconductor chips and the defective semiconductor chips.

[0082] (Note 17) A wafer test unit that includes a probe and performs the electrical test by applying current or voltage to each of the plurality of semiconductor chips via the probe to evaluate their electrical characteristics, The system further comprises a transfer unit for moving the semiconductor wafer between the wafer test unit and the cutting unit, The aforementioned cut portion is A YAG laser for cutting the aforementioned semiconductor wafer, A semiconductor manufacturing apparatus according to any one of the appendices 12 to 16, comprising, as the aforementioned external information, a camera for taking the aforementioned image. [Explanation of symbols]

[0083] 1 Semiconductor chip, 1A Defective semiconductor chip, 2 Dicing line, 3 Effective area, 4 Ineffective area, 5 Base point, 6 Cutting section, 6A First cutting section, 6B Second cutting section, 7 Reference chip, 7A Provisional reference chip, 8A First boundary, 8B Second boundary, 9A First virtual line, 9B Second virtual line, 10 Semiconductor wafer, 10A Rim, 10B Center, 11-15 Cut and processed semiconductor wafer, 20 Wafer test section, 21 Test prober, 30 Data acquisition section, 40 Transfer section, 50 Setting section, 60 Cutting section, 61 Laser oscillator, 62 Camera, 70 Identification section, 71 First identification section, 72 Second identification section, 100 Semiconductor manufacturing equipment.

Claims

1. A data acquisition step involves obtaining test results of electrical tests performed on multiple semiconductor chips formed on a semiconductor wafer, wherein the test results are associated with the arrangement information of the multiple semiconductor chips. A cutting step in which the semiconductor wafer is cut with reference to a base point set within the semiconductor wafer to form a cut semiconductor wafer, The system includes an identification step that identifies at least one of good semiconductor chips and defective semiconductor chips in the cut semiconductor wafer based on the appearance information of the cut semiconductor wafer and the test results of the semiconductor wafer before cutting, The aforementioned cut semiconductor wafer includes two or more semiconductor chips. A method for manufacturing a semiconductor device, wherein the aforementioned appearance information is an image of the region including the base point.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the image above includes a semiconductor chip around the base point in the cut semiconductor wafer and a cut section cut with respect to the base point.

3. The plurality of semiconductor chips are arranged in a matrix along a first direction and a second direction orthogonal to the first direction on the surface of the semiconductor wafer. The method for manufacturing a semiconductor device according to claim 1, wherein the cut surface of the cut semiconductor wafer is formed in the first direction and the second direction from the base point.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the cutting step includes cutting from the base point to the edge of the semiconductor wafer.

5. The semiconductor wafer is a rimmed semiconductor wafer, The rimmed semiconductor wafer includes a rim portion provided along the outer circumference of the rimmed semiconductor wafer and a central portion provided inside the rim portion. The thickness of the rim portion is greater than the thickness of the central portion. The aforementioned cutting process is, A cutting section formation step involves cutting out a cutting section which is a region located within the central part and adjacent to the base point, A method for manufacturing a semiconductor device according to claim 1, comprising a rim cutting step of cutting the rim portion.

6. The method for manufacturing a semiconductor device according to claim 1, wherein the cutting step includes cutting at the boundary between an effective region on which the plurality of semiconductor chips are formed and an inactive region on which the plurality of semiconductor chips are not formed, based on the reference point.

7. The reference point is set at the intersection of a first virtual line, which is a virtual extension of the first boundary portion extending in the first direction, and a second virtual line, which is a virtual extension of the second boundary portion extending in the second direction, of the boundary between the effective region where the plurality of semiconductor chips are formed and the inactive region where the plurality of semiconductor chips are not formed. The first boundary portion included in the first virtual line is located between the semiconductor chip closest to the outer edge of the semiconductor wafer in the second direction and the invalid region among the plurality of semiconductor chips, The second boundary portion included in the second virtual line is located between the semiconductor chip closest to the outer edge of the semiconductor wafer in the first direction and the invalid region among the plurality of semiconductor chips, The method for manufacturing a semiconductor device according to claim 3, wherein the cutting step includes cutting the semiconductor wafer along the first virtual line and the second virtual line.

8. The method for manufacturing a semiconductor device according to claim 1, wherein the cutting step includes cutting only the defective semiconductor chips based on the test results.

9. A mounting step of mounting the cut semiconductor wafer onto a dicing sheet, The process further comprises a dicing step, after the mounting step, in which the cut semiconductor wafer is diced to separate the plurality of semiconductor chips from each other. The method for manufacturing a semiconductor device according to claim 1, wherein the identification step is performed between the mounting step and the individualization step, or after the individualization step.

10. The aforementioned identification step is, A first identification step involves comparing the presence or absence of semiconductor chips in a predetermined range around the base point based on the aforementioned image and the arrangement information of the plurality of semiconductor chips in the test results, and identifying a reference chip in the predetermined range. A method for manufacturing a semiconductor device according to claim 1, comprising a second identification step of identifying the position of at least one of the good semiconductor chips and the defective semiconductor chips on the cut semiconductor wafer, with reference to the reference chip.

11. The method for manufacturing a semiconductor device according to claim 1, wherein the test results include wafer map data having positional information on the semiconductor wafer for at least one of the good semiconductor chips and the defective semiconductor chips.

12. A data acquisition unit that acquires test results of electrical tests performed on multiple semiconductor chips formed on a semiconductor wafer, the test results being associated with the arrangement information of the multiple semiconductor chips, A cutting unit that cuts the semiconductor wafer with respect to a base point set within the semiconductor wafer to form a cut semiconductor wafer, The system includes an identification unit that identifies at least one of good semiconductor chips and defective semiconductor chips in the cut semiconductor wafer based on the appearance information of the cut semiconductor wafer and the test results of the semiconductor wafer before cutting, The aforementioned cut semiconductor wafer includes two or more semiconductor chips. The aforementioned external information is an image of the region including the base point, in a semiconductor manufacturing apparatus.

13. The semiconductor manufacturing apparatus according to claim 12, wherein the image includes semiconductor chips around the base point in the cut semiconductor wafer and a cut section cut with respect to the base point.

14. The plurality of semiconductor chips are arranged in a matrix along a first direction and a second direction orthogonal to the first direction on the surface of the semiconductor wafer. The semiconductor manufacturing apparatus according to claim 12, wherein the cut surface of the cut semiconductor wafer is formed in the first direction and the second direction from the base point.

15. The aforementioned identification unit is A first identification unit that, based on the aforementioned image and the arrangement information of the plurality of semiconductor chips in the test results, checks for the presence or absence of semiconductor chips in a predetermined range around the base point and identifies a reference chip in the predetermined range, The semiconductor manufacturing apparatus according to claim 12, further comprising: a second identification unit that identifies the position of at least one of the good semiconductor chips and the defective semiconductor chips on the cut semiconductor wafer, with reference to the aforementioned reference chip.

16. The semiconductor manufacturing apparatus according to claim 12, wherein the test results include wafer map data having positional information on the semiconductor wafer for at least one of the good semiconductor chips and the defective semiconductor chips.

17. A wafer test unit that includes a probe and performs the electrical test by applying current or voltage to each of the plurality of semiconductor chips via the probe to evaluate their electrical characteristics, The system further comprises a transfer unit for moving the semiconductor wafer between the wafer test unit and the cutting unit, The aforementioned cut portion is A YAG laser for cutting the aforementioned semiconductor wafer, The semiconductor manufacturing apparatus according to claim 12, further comprising a camera for capturing the image as the aforementioned external information.

Images