Manufacturing method for semiconductor devices

Abstract

To provide a technology capable of suppressing peeling of a coating film while reducing an ineffective area.SOLUTION: A semiconductor device manufacturing method includes a preparation step of preparing a semiconductor structure and a dicing step of dicing a dicing line region. The thickness of a side monitor electrode is smaller than the thickness of a coating film, and the relationship of 15>b>1.15×d+6.88 is satisfied between a distance b [μm] between the coating film and the side monitor electrode and a length d [mm] of the side monitor electrode in an extension direction of the dicing line region in a plan view.SELECTED DRAWING: Figure 3

Description

Technical Field

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[0001] The present disclosure relates to a method for manufacturing a semiconductor device.

Background Art

[0002] A semiconductor chip provided with a coating film in a terminal region has been proposed. In such a semiconductor chip, there is a problem that when the developing solution stays in the recess adjacent to the coating film after forming the coating film with the developing solution, the coating film peels off due to the developing solution. In contrast, Patent Document 1 proposes a technique for suppressing the peeling of the coating film by covering the recess with the coating film and suppressing the retention of the developing solution.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a coating film is provided near the dicing line, there is a possibility that the coating film is bitten during dicing using a blade. Therefore, the coating film needs to be provided at a certain distance from the dicing line. However, when an opening is provided as in the technique of Patent Document 1, it is necessary to make the distance between the coating film and the dicing line larger than the above-mentioned certain distance. As a result, there is a problem that the ineffective area on the semiconductor substrate becomes large and the manufacturing cost of the semiconductor device increases. In addition, when a side monitor electrode for monitoring the electrical characteristics of the semiconductor chip during the manufacturing process is provided, there is a problem that the ineffective area on the semiconductor substrate becomes large and the manufacturing cost of the semiconductor device increases.

[0005] Therefore, this disclosure has been made in view of the above-mentioned problems, and aims to provide a technology that can suppress peeling of the coating film while reducing the ineffective area. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor device according to the present disclosure comprises a preparation step of preparing a semiconductor structure in which a terminal region of a semiconductor chip and a dicing line region adjacent to the terminal region in a plan view are defined, and a dicing step of performing dicing on the dicing line region, wherein the semiconductor structure includes a semiconductor substrate in which the terminal region and the dicing line region are defined, a side monitor electrode provided on the semiconductor substrate in the dicing line region, a passivation film provided extending from the upper part of the semiconductor substrate in the terminal region to the upper part of the side monitor electrode, and a coating film provided on the passivation film in the terminal region, wherein the thickness of the side monitor electrode is smaller than the thickness of the coating film, and the relationship 15>b>1.15×d+6.88 holds between the distance b[μm] between the coating film and the side monitor electrode and the length d[mm] of the side monitor electrode in the extending direction of the dicing line region in a plan view. [Effects of the Invention]

[0007] According to this disclosure, the thickness of the side monitor electrode is smaller than the thickness of the coating film, and the relationship 15 > b > 1.15 × d + 6.88 holds between the distance b [μm] between the coating film and the side monitor electrode and the length d [mm] of the side monitor electrode in the direction of extension of the dicing line region in a plan view. With such a configuration, peeling of the coating film can be suppressed while reducing the ineffective region. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view showing the configuration of a semiconductor structure according to Embodiment 1. [Figure 2] This is a plan view showing the configuration of a semiconductor structure according to Embodiment 1. [Figure 3]This is a cross-sectional view showing the configuration of a semiconductor structure according to Embodiment 1. [Figure 4] This figure shows the experimental results for the semiconductor structure according to Embodiment 1. [Figure 5] This is a cross-sectional view showing the configuration of a semiconductor structure according to Embodiment 2. [Figure 6] This is a plan view showing the configuration of a semiconductor structure according to Embodiment 2. [Figure 7] This is a plan view showing the configuration of a semiconductor structure according to a modified example of Embodiment 2. [Figure 8] This is a cross-sectional view showing the configuration of a semiconductor structure according to a modified example of Embodiment 2. [Figure 9] This is a cross-sectional view showing the configuration of a semiconductor structure according to a modified example of Embodiment 2. [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the attached drawings. The features described in each of the embodiments below are illustrative, and not all features are necessarily required. In addition, in the descriptions below, the same or similar reference numerals are used for similar components in multiple embodiments, and the different components are mainly described. Also, in the descriptions below, specific positions and directions such as "top," "bottom," "left," "right," "front," or "back" do not necessarily have to coincide with the positions and directions in actual implementation.

[0010] <Embodiment 1> Figure 1 is a plan view showing the configuration of a semiconductor structure according to this embodiment 1. The semiconductor structure is prepared in the semiconductor structure preparation process during the semiconductor device manufacturing process. The semiconductor structure includes a cell structure region 11a and a termination region 11b of the semiconductor chip 11, and a dicing line region 12.

[0011] A semiconductor element is provided in the cell structure region 11a. The semiconductor element includes, for example, at least one of MOSFET (Metal Oxide Semiconductor Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), RC-IGBT (Reverse Conducting - IGBT), SBD (Schottky Barrier Diode), and PND (PN junction diode). In this specification, for example, at least one of A, B, C, ..., and Z means any one of all combinations obtained by selecting one or more from the groups A, B, C, ..., and Z.

[0012] The terminal region 11b is the region that surrounds the cell structure region 11a in a plan view, and is the region that maintains the pressure resistance of the cell structure region 11a.

[0013] The dicing line region 12 is located between adjacent semiconductor chips 11 in a plan view and is adjacent to the terminal region 11b of each semiconductor chip 11. The semiconductor chips 11 are separated and individualized by the dicing process, which involves dicing the semiconductor structure in the dicing line region 12. The width of the dicing line region 12 is often, for example, 80 to 120 μm to ensure sufficient width for a dicing blade, such as a grinding blade, to pass through.

[0014] Figure 2 is a magnified plan view of the area enclosed by the dashed line in Figure 1, and Figure 3 is a cross-sectional view along the line A-A' in Figure 2. As shown in Figures 2 and 3, the semiconductor structure includes a semiconductor substrate 1, a side monitor electrode 2, a passivation film 3, and a coating film 4.

[0015] The semiconductor substrate 1 in FIG. 3 is made of, for example, silicon (Si) or a wide bandgap semiconductor, and includes at least one of a normal semiconductor wafer and an epitaxial growth layer. The wide bandgap semiconductor includes, for example, silicon carbide (SiC), gallium nitride (GaN), diamond, and the like. When the semiconductor substrate 1 is composed of a wide bandgap semiconductor, stable operation of the semiconductor device at high temperatures and high voltages and an increase in the switching speed are possible. However, since the price of the semiconductor substrate 1 made of SiC is high, from the viewpoint of reducing the cost of the semiconductor device, it is required to reduce the ineffective region in the semiconductor substrate 1 as much as possible. On the other hand, according to the first embodiment described below, it is possible to reduce the ineffective region in the semiconductor substrate 1.

[0016] The semiconductor chip 11 in FIG. 1 is provided on the semiconductor substrate 1, and a cell structure region 11a, a terminal region 11b, and a dicing line region 12 are defined. A surface electrode of the semiconductor chip 11 is formed on the surface of the semiconductor substrate 1, and a back surface electrode of the semiconductor chip 11 is formed on the back surface of the semiconductor substrate 1. Note that the back surface of the semiconductor substrate 1 may be polished before forming the back surface electrode.

[0017] As shown in FIG. 3, the side monitor electrode 2 is provided on the semiconductor substrate 1 in the dicing line region 12. The side monitor electrode 2 is provided to detect an abnormality during the manufacturing process of the semiconductor device. For example, a diffusion layer is provided in the semiconductor substrate 1 under the side monitor electrode 2, and the diffusion layer is formed simultaneously with the cell diffusion layer that constitutes the semiconductor element in the cell structure region 11a. Before dicing, an operator can electrically connect a probe and the side monitor electrode 2 and measure the resistance of the diffusion layer under the side monitor electrode 2 to detect an abnormality during the manufacturing process at a relatively early stage. Also, in the unlikely event that an operator discovers a characteristic defect in the semiconductor chip 11, the abnormal process can be identified retrospectively by analyzing the measured value of the side monitor electrode 2. In addition, an operator can also achieve line management by comparing the transition of the characteristic values obtained from the side monitor electrode 2.

[0018] The side monitor electrode 2 is provided at least at one location in the dicing line region 12 within the exposure shot. Although it depends on the size of the semiconductor chip 11, it is preferable that a plurality of side monitor electrodes 2 are provided in a size that fits within one side of the semiconductor chip 11. Since marks for alignment during the exposure process are often provided at the intersections where the dicing line regions 12 intersect, it is preferable not to provide the side monitor electrode 2 at such intersections. The side monitor electrode 2 is made of, for example, AlSi.

[0019] The passivation film 3 is provided from the upper part of the semiconductor substrate 1 in the terminal region 11b to the upper part of the side monitor electrode 2. The passivation film 3 provided as an insulating film on the semiconductor substrate 1 in the terminal region 11b has a function of suppressing the surface discharge of the semiconductor chip 11, similar to the coating film 4 described later. An opening is provided in the passivation film 3 to partially expose the upper part of the side monitor electrode 2 that is electrically connected to the probe. For example, after an oxide film or nitride film of silicon is deposited on the upper surface of the semiconductor substrate 1, the pattern of the passivation film 3 is formed by etching through the resist in a photolithography process.

[0020] The coating film 4 is provided on the passivation film 3 in the terminal region 11b. If the coating film 4 is bitten by the grinding blade during dicing, it may become clogged, reducing productivity, or chipping may occur, causing a notch at the end of the semiconductor chip 11. Therefore, as shown in FIGS. 2 and 3, the coating film 4 exposes the passivation film 3 in the dicing line region 12.

[0021] The coating film 4 is made of, for example, photosensitive polyimide. The pattern of the coating film 4 is formed by a developing process included in the preparation process of the semiconductor structure. For example, the coating film 4 is formed by applying a photosensitive polyimide precursor solution onto a semiconductor substrate 1 on which a passivation film 3 is provided, pre-baking, forming an arbitrary pattern in a photogravure process, and then performing a final bake. If photosensitive polyimide is applied to a wafer and then selectively exposed using a mask, the exposed portion is dissolved in the developing solution, so that the coating film 4 can be formed in any pattern.

[0022] The coating film 4, provided as an insulating film on the passivation film 3 of the terminal region 11b, has the function of suppressing creepage discharge of the semiconductor chip 11. Furthermore, because the coating film 4, made of polyimide, is flexible, it has the function of protecting the structure of the terminal region 11b of the semiconductor chip 11 from stress caused by the expansion and contraction of external encapsulating materials, etc. Note that if the back surface of the semiconductor substrate 1 is ground so that the thickness of the semiconductor substrate 1 is, for example, about 100 μm or less, the warping of the semiconductor substrate 1 after the grinding process becomes large, making it difficult to form the passivation film 3 or the coating film 4. For this reason, it is preferable to form the passivation film 3 or the coating film 4 before the grinding process of the semiconductor substrate 1.

[0023] With the above configuration, since the side monitor electrode 2 is provided on the dicing line region 12, a region dedicated to the side monitor electrode 2 is not required. Therefore, the inactive region in the semiconductor substrate 1 can be reduced. However, as shown in Figure 3, a recess is formed between the side monitor electrode 2 and the coating film 4, and the developing solution used to form the coating film 4 may accumulate in this recess, potentially causing the coating film 4 to peel off. Therefore, the inventors conducted experiments to investigate a configuration in which the coating film 4 would not peel off.

[0024] Figure 4 shows the experimental results. In this experiment, when the thickness c of the side monitor electrode 2 was smaller than the thickness a of the coating film 4, the distance between the coating film 4 and the side monitor electrode 2 was set to b [μm], and the length of the side monitor electrode in the extending direction of the dicing line region 12 in a plan view was set to d [mm]. Note that the distance b is shown in Figure 3, and the length d is shown in Figure 2.

[0025] As shown in Figure 4, when 15[μm]>b>1.15×d+6.88, preferably 10[μm]b>1.15×d+6.88, peeling of the coating film 4 is suppressed. Therefore, the semiconductor structure according to this embodiment 1 is configured such that 15[μm]>b>1.15×d+6.88 holds true. Furthermore, if this equation holds true, peeling of the coating film 4 is suppressed even when the length d is greater than 100μm.

[0026] <Summary of Embodiment 1> In the semiconductor device manufacturing method according to this embodiment 1 described above, a semiconductor structure is used in which the side monitor electrode 2 is provided on the dicing line region 12. With this configuration, the inactive region in the semiconductor substrate 1 can be reduced. In this embodiment 1, the relationship 15>b>1.15×d+6.88 holds between the distance b[μm] between the coating film 4 and the side monitor electrode 2 in a plan view and the length d[mm] of the side monitor electrode 2 in the extending direction of the dicing line region 12 in a plan view. With this configuration, it is possible to suppress the accumulation of developer solution in the recess between the side monitor electrode 2 and the coating film 4, and to suppress the peeling of the coating film 4. As a result, deterioration of the reliability of the semiconductor device and the occurrence of appearance abnormalities can be suppressed.

[0027] Furthermore, if the passivation film 3 is, for example, a glass coating film containing silicon nitride (SiN), the adhesion between the passivation film 3 and the coating film 4 can be improved more than the adhesion between the semiconductor substrate 1 and the coating film 4. Therefore, even if developer solution remains in the recesses, the peeling of the coating film 4 can be suppressed by the penetration of the developer solution between the passivation film 3 and the coating film 4.

[0028] Furthermore, if the semiconductor substrate 1 is made of SiC, the inactive area can be reduced in the expensive semiconductor substrate 1, thereby reducing the cost of the semiconductor device.

[0029] <Embodiment 2> Figure 5 is a cross-sectional view showing the configuration of the semiconductor structure according to this second embodiment, and is a cross-sectional view corresponding to Figure 3. In the semiconductor structure according to this second embodiment, a surplus region 13 is defined between the termination region 11b and the dicing line region 12. The surplus region 13 is the region outside the depletion layer at the edge of the semiconductor chip 11. The semiconductor substrate 1, passivation film 3, and coating film 4 are provided in the surplus region 13 as well as the termination region 11b.

[0030] The semiconductor structure includes one or more insulating films 5 in addition to the configuration shown in Figure 3. Figure 6 is a plan view showing the configuration of the excess region 13. The insulating film 5 is provided only in the excess region 13 and between the passivation film 3 and the semiconductor substrate 1. As a result, as shown in Figure 5, in the excess region 13 only, and in the passivation film 3 and the coating film 4, there are irregularities 6 that fit together in cross-sectional view and correspond to the shape of the insulating film 5. There may be one irregularity 6, or multiple irregularities 6 may be provided at intervals. The insulating film 5 is made of, for example, TEOS (tetra ethoxy silane).

[0031] <Summary of Embodiment 2> In the semiconductor device manufacturing method according to this second embodiment described above, the passivation film 3 and the coating film 4 are provided with irregularities 6 that fit together in cross-sectional view and correspond to the shape of the insulating film 5. With this configuration, the surface area of ​​the interface between the passivation film 3 and the coating film 4 can be increased, thereby improving their adhesion to each other. As a result, even if developer solution remains in the recesses, it is possible to suppress the peeling of the coating film 4 by the penetration of the developer solution between the passivation film 3 and the coating film 4.

[0032] Furthermore, in this second embodiment, the irregularities 6 are provided only in the excess region 13. With this configuration, the excess region 13 can be effectively utilized.

[0033] <Variation> In Figures 5 and 6, multiple insulating films 5 are arranged in a direction from the terminal region 11b toward the dicing line region 12, but this is not the only arrangement. For example, as shown in Figure 7, multiple insulating films 5 may be arranged in both the direction from the terminal region 11b toward the dicing line region 12 and perpendicular to that direction. Alternatively, for example, the insulating films 5 may be arranged continuously or intermittently around the excess region 13. The number, size, and arrangement of the insulating films 5 are not limited to the above description.

[0034] Furthermore, in Figure 5, the side surface of the insulating film 5 was perpendicular to the bottom surface of the insulating film 5. However, as shown in Figure 8, the tapered angle of the insulating film 5 may be less than 90°, so that in cross-sectional view, the insulating film 5 has a tapered shape that narrows towards the top. With such a configuration, the shape of the irregularities 6 between the passivation film 3 and the coating film 4 becomes smoother, and air bubbles are less likely to form between the passivation film 3 and the coating film 4, thereby improving the adhesion between the passivation film 3 and the coating film 4.

[0035] Furthermore, in Embodiment 2, the irregularities 6 were provided only in the excess region 13. However, if there is no need to effectively utilize the excess region 13, the irregularities 6 may be provided in the terminal region 11b. Also, as shown in Figure 9, by providing the surface electrode 11c of the semiconductor chip 11 instead of the insulating film 5, the passivation film 3 and the coating film 4 may be fitted together in cross-sectional view and have irregularities 6 corresponding to the shape of the surface electrode 11c. In this case as well, the same effects as in Embodiment 2 can be obtained.

[0036] Furthermore, it is possible to freely combine each embodiment and each variation, and to modify or omit each embodiment and each variation as appropriate.

[0037] The various aspects of this disclosure are summarized below as an appendix.

[0038] (Note 1) A preparation step for preparing a semiconductor structure in which a termination region of a semiconductor chip and a dicing line region adjacent to the termination region in a plan view are defined, A dicing step in which dicing is performed in the dicing line region. Equipped with, The aforementioned semiconductor structure is A semiconductor substrate having defined termination region and dicing line region, A side monitor electrode provided on the semiconductor substrate in the dicing line region, A passivation film is provided extending from the upper part of the semiconductor substrate in the termination region to the upper part of the side monitor electrode, The coating film provided on the passivation film in the terminal region and Includes, The thickness of the side monitor electrode is less than the thickness of the coating film. A method for manufacturing a semiconductor device, wherein the distance b [μm] between the coating film and the side monitor electrode and the length d [mm] of the side monitor electrode in the extending direction of the dicing line region in a plan view satisfy the condition 15 > b > 1.15 × d + 6.88.

[0039] (Note 2) A method for manufacturing a semiconductor device as described in Appendix 1, A method for manufacturing a semiconductor device, wherein the distance b is 7 μm or more, and the length d is greater than 100 μm.

[0040] (Note 3) A method for manufacturing a semiconductor device as described in Appendix 1 or Appendix 2, The semiconductor structure further includes one or more insulating films provided between the passivation film and the semiconductor substrate, A method for manufacturing a semiconductor device, wherein the passivation film and the coating film are provided with irregularities that fit together in cross-sectional view and correspond to the shape of the insulating film.

[0041] (Note 4) A method for manufacturing a semiconductor device as described in Appendix 1 or Appendix 2, The semiconductor structure further includes an excess region defined between the termination region and the dicing line region. The semiconductor substrate, the passivation film, and the coating film are provided in the excess region. The semiconductor structure further includes one or more insulating films provided between the passivation film and the semiconductor substrate, A method for manufacturing a semiconductor device, wherein only in the aforementioned surplus region, the passivation film and the coating film are provided with irregularities that fit together in cross-sectional view and correspond to the shape of the insulating film.

[0042] (Note 5) A method for manufacturing a semiconductor device as described in Appendix 3 or Appendix 4, A method for manufacturing a semiconductor device, wherein the taper angle of the insulating film is less than 90°.

[0043] (Note 6) A method for manufacturing a semiconductor device as described in any one of the appendices 1 to 5, The semiconductor structure further includes one or more surface electrodes provided between the passivation film and the semiconductor substrate, A method for manufacturing a semiconductor device, wherein the passivation film and the coating film in a cross-sectional view are provided with irregularities that fit together in a cross-sectional view and correspond to the shape of the surface electrode.

[0044] (Note 7) A method for manufacturing a semiconductor device as described in any one of the appendices 1 to 6, A method for manufacturing a semiconductor device, wherein the semiconductor substrate is made of SiC.

[0045] (Note 8) A method for manufacturing a semiconductor device as described in any one of the appendices 1 to 7, A method for manufacturing a semiconductor device, wherein the preparation step includes a developing step for forming a pattern on the coating film. [Explanation of Symbols]

[0046] 1 Semiconductor substrate, 2 Side monitor electrode, 3 Passivation film, 4 Coating film, 5 Insulating film, 6 Surface texture, 11 Semiconductor chip, 11b Termination region, 11c Surface electrode, 12 Dicing line region, 13 Excess region.

Claims

1. A preparation step for preparing a semiconductor structure in which a termination region of a semiconductor chip and a dicing line region adjacent to the termination region in a plan view are defined, A dicing step in which dicing is performed in the dicing line region. Equipped with, The aforementioned semiconductor structure is A semiconductor substrate having defined termination region and dicing line region, A side monitor electrode provided on the semiconductor substrate in the dicing line region, A passivation film is provided extending from the upper part of the semiconductor substrate in the termination region to the upper part of the side monitor electrode, The coating film provided on the passivation film in the terminal region and Includes, The thickness of the side monitor electrode is less than the thickness of the coating film. A method for manufacturing a semiconductor device, wherein the distance b [μm] between the coating film and the side monitor electrode and the length d [mm] of the side monitor electrode in the extending direction of the dicing line region in a plan view satisfy the relationship 15 > b > 1.15 × d + 6.

88.

2. A method for manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, wherein the distance b is 7 μm or more, and the length d is greater than 100 μm.

3. A method for manufacturing a semiconductor device according to claim 1 or claim 2, The semiconductor structure further includes one or more insulating films provided between the passivation film and the semiconductor substrate, A method for manufacturing a semiconductor device, wherein the passivation film and the coating film are provided with irregularities that fit together in cross-sectional view and correspond to the shape of the insulating film.

4. A method for manufacturing a semiconductor device according to claim 1 or claim 2, The semiconductor structure further includes an excess region defined between the termination region and the dicing line region. The semiconductor substrate, the passivation film, and the coating film are provided in the excess region. The semiconductor structure further includes one or more insulating films provided between the passivation film and the semiconductor substrate, A method for manufacturing a semiconductor device, wherein only in the aforementioned surplus region, the passivation film and the coating film are provided with irregularities that fit together in cross-sectional view and correspond to the shape of the insulating film.

5. A method for manufacturing a semiconductor device according to claim 3, A method for manufacturing a semiconductor device, wherein the taper angle of the insulating film is less than 90°.

6. A method for manufacturing a semiconductor device according to claim 1 or claim 2, The semiconductor structure further includes one or more surface electrodes provided between the passivation film and the semiconductor substrate, A method for manufacturing a semiconductor device, wherein the passivation film and the coating film in a cross-sectional view are provided with irregularities that fit together in a cross-sectional view and correspond to the shape of the surface electrode.

7. A method for manufacturing a semiconductor device according to claim 1 or claim 2, A method for manufacturing a semiconductor device, wherein the semiconductor substrate is made of SiC.

8. A method for manufacturing a semiconductor device according to claim 1 or claim 2, A method for manufacturing a semiconductor device, wherein the preparation step includes a developing step for forming a pattern on the coating film.

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