Photodetector, method for manufacturing a photodetector, and electronic device

Abstract

The present invention provides a light detection device in which a desired through electrode is formed. A light detection device according to the present invention comprises: a first semiconductor layer which has a photoelectric conversion region, one surface of which is a first surface, and the other surface of which is a second surface serving as a light entry surface; a second semiconductor layer one surface of which is a third surface and the other surface of which is a fourth surface; a second wiring layer which is superimposed on the third surface of the second semiconductor layer; a third wiring layer which is superimposed on the fourth surface of the second semiconductor layer; a first wiring layer one surface of which is superimposed on the first surface of the first semiconductor layer and the other surface of which is superimposed on one of the second wiring layer and the third wiring layer; a first conductor which has a first width, which is composed of a first material, and through which the second semiconductor layer penetrates in the thickness direction; and a second conductor which has a second width smaller than the first width, which is composed of a second material different from the first material, and through which the second semiconductor layer penetrates in the thickness direction.

Description

Technical Field

[0001] The present technology (the technology according to the present disclosure) relates to a photodetection device, a method for manufacturing a photodetection device, and an electronic device, and particularly to a photodetection device having a conductor penetrating a semiconductor layer, a method for manufacturing a photodetection device, and an electronic device.

Background Art

[0002] For a stacked image sensor, a conductor penetrating a semiconductor layer may be provided. Patent Documents 1, Patent Document 2, and Patent Document 3 describe examples of through electrodes that are conductors penetrating a semiconductor layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] For example, since it is desirable that a through electrode used as a power line has low resistance, it is desirable to increase the diameter in a plan view and to form it with a low-resistance material. On the other hand, when the area where the through electrode is provided is narrow, it is desirable to form a through electrode having a small diameter and a high aspect ratio.

[0005] An object of the present technology is to provide a photodetection device in which a desired through electrode is formed, a method for manufacturing a photodetection device, and an electronic device.

Means for Solving the Problems

[0006] A photodetector according to one aspect of this technology comprises: a first semiconductor layer having a photoelectric conversion region, one of which is a first surface and the other surface is a second surface which is an incident light surface; a second semiconductor layer having one of which is a third surface and the other surface which is a fourth surface; a second wiring layer superimposed on the third surface of the second semiconductor layer; a third wiring layer superimposed on the fourth surface of the second semiconductor layer; a first wiring layer having one surface superimposed on the first surface of the first semiconductor layer and the other surface superimposed on one of the wiring layers of the second wiring layer and the third wiring layer; a first conductor having a first width, made of a first material, and penetrating the second semiconductor layer along the thickness direction; and a second conductor having a second width smaller than the first width, made of a second material different from the first material, and penetrating the second semiconductor layer along the thickness direction.

[0007] Another aspect of the present technology provides a photodetector comprising: a first semiconductor layer having a photoelectric conversion region, one of which is a first surface and the other surface is a second surface which is an incident light surface; a second semiconductor layer having one of which is a third surface and the other surface which is a fourth surface; a second wiring layer superimposed on the third surface of the second semiconductor layer; a third wiring layer superimposed on the fourth surface of the second semiconductor layer; a first wiring layer having one surface superimposed on the first surface of the first semiconductor layer and the other surface superimposed on one of the wiring layers of the second wiring layer and the third wiring layer; a first conductor made of a first material and penetrating the second semiconductor layer along the thickness direction; and a second conductor made of a second material different from the first material and penetrating the second semiconductor layer along the thickness direction.

[0008] A method for manufacturing a photodetector according to one aspect of this technology involves forming a conductor that penetrates itself in a semiconductor layer, laminating an insulating film so as to cover one end of the first conductor, forming another conductor from the insulating film side so as to penetrate the semiconductor layer, which is made of a material different from the material constituting the first conductor and has a diameter larger than the diameter of the first conductor, and forming wiring connected to the first conductor and wiring connected to the other conductor from the insulating film side.

[0009] An electronic device according to one aspect of this technology comprises the above-mentioned light detection device and an optical system for forming an image of light from an object on the above-mentioned light detection device.

[0010] Another aspect of the present technology provides a photodetector comprising: a first semiconductor layer having a photoelectric conversion region, one of which is a first surface and the other surface is a second surface which is an incident light surface; a second semiconductor layer having one of which is a third surface and the other surface which is a fourth surface; a second wiring layer superimposed on the third surface of the second semiconductor layer; a third wiring layer superimposed on the fourth surface of the second semiconductor layer; a first wiring layer having one surface superimposed on the first surface of the first semiconductor layer and the other surface superimposed on one of the wiring layers of the second wiring layer and the third wiring layer; a first conductor having a first width and penetrating the second semiconductor layer along the thickness direction; and a second conductor having a second width smaller than the first width and penetrating the second semiconductor layer along the thickness direction. [Brief explanation of the drawing]

[0011] [Figure 1] This is a chip layout diagram showing an example configuration of a photodetector according to the first embodiment of this technology. [Figure 2] This is a block diagram showing an example configuration of a light detection device according to the first embodiment of this technology. [Figure 3] This is an equivalent circuit diagram of a pixel in a photodetector according to the first embodiment of this technology. [Figure 4A] This is a longitudinal cross-sectional view of a photodetector according to the first embodiment of this technology. [Figure 4B] This is a magnified view of the main part of Figure 4A. [Figure 4C] This is a longitudinal cross-sectional view of a photodetector according to a modified example 4 of the first embodiment of this technology. [Figure 5A] This is a cross-sectional view showing a process for manufacturing a photodetector according to the first embodiment of this technology. [Figure 5B] This is a cross-sectional view of the process following Figure 5A. [Figure 5C] This is a cross-sectional view of the process, following Figure 5B. [Figure 5D] It is a process cross-sectional view following FIG. 5C. [Figure 5E] It is a process cross-sectional view following FIG. 5D. [Figure 5F] It is a process cross-sectional view following FIG. 5E. [Figure 5G] It is a process cross-sectional view following FIG. 5F. [Figure 5H] It is a process cross-sectional view following FIG. 5G. [Figure 5I] It is a process cross-sectional view following FIG. 5H. [Figure 5J] It is a process cross-sectional view following FIG. 5I. [Figure 5K] It is a process cross-sectional view following FIG. 5J. [Figure 5L] It is a process cross-sectional view following FIG. 5K. [Figure 5M] It is a process cross-sectional view following FIG. 5L. [Figure 5N] It is a process cross-sectional view following FIG. 5M. [Figure 5O] It is a process cross-sectional view following FIG. 5N. [Figure 5P] It is a process cross-sectional view following FIG. 5O. [Figure 5Q] It is a process cross-sectional view following FIG. 5P. [Figure 5R] It is a process cross-sectional view following FIG. 5Q. [Figure 5S] It is a process cross-sectional view following FIG. 5R. [Figure 5T] It is a process cross-sectional view following FIG. 5S. [Figure 5U] It is a process cross-sectional view following FIG. 5T. [Figure 5V] It is a process cross-sectional view following FIG. 5U. [Figure 5W] It is a process cross-sectional view showing a method of manufacturing a photodetection device according to Modification 4 of the first embodiment of the present technology. [Figure 5X] It is a process cross-sectional view following FIG. 5W. [Figure 6] It is a longitudinal sectional view of a photodetection device according to Modification 1 of the first embodiment of the present technology. [Figure 7]This is a partially enlarged view showing an enlarged portion of the main part of the longitudinal cross-section of a photodetector according to a modified example 2 of the first embodiment of this technology. [Figure 8A] This is a cross-sectional view showing a process for manufacturing a photodetector according to a modified example 2 of the first embodiment of this technology. [Figure 8B] This is a cross-sectional view of the process following Figure 8A. [Figure 9] This is a partially enlarged view showing an enlarged section of the main part of the longitudinal cross-section of a photodetector according to Modification 3 of the first embodiment of this technology. [Figure 10] This is a partially enlarged view showing an enlarged section of the main part of the longitudinal cross-section of a photodetector according to another embodiment of the first embodiment of this technology, Modification 3. [Figure 11] This is a longitudinal cross-sectional view showing the main part of the photodetector according to the second embodiment of this technology. [Figure 12A] This is a perspective view of a transistor in a photodetector according to a second embodiment of this technology. [Figure 12B] Figure 12A is a longitudinal cross-sectional view of the transistor shown. [Figure 12C] Figure 12A is a cross-sectional view showing the cross-sectional structure when viewed along the AA cutting line. [Figure 12D] Figure 12A is a cross-sectional view showing the cross-sectional structure when viewed along the BB cutting line. [Figure 13A] This is a cross-sectional view showing a process for manufacturing a photodetector according to a second embodiment of this technology. [Figure 13B] This is a cross-sectional view of the process, following Figure 13A. [Figure 13C] This is a cross-sectional view of the process, following Figure 13B. [Figure 13D] This is a cross-sectional view of the process, following Figure 13C. [Figure 13E] This is a cross-sectional view of the process, following Figure 13D. [Figure 14A] This is a longitudinal cross-sectional view of a transistor in a photodetector according to Modification 1-1 of the second embodiment of this technology. [Figure 14B] This is a longitudinal cross-sectional view of a transistor in a photodetector according to a modified example 1-2 of the second embodiment of this technology. [Figure 14C]This is a longitudinal cross-sectional view of a transistor in a photodetector according to Modification 1-3 of the second embodiment of this technology. [Figure 14D] This is a longitudinal cross-sectional view of a transistor in a photodetector according to Modification 1-4 of the second embodiment of this technology. [Figure 14E] This is a longitudinal cross-sectional view of a transistor in a photodetector according to Modification 1-5 of the second embodiment of this technology. [Figure 14F] This is a longitudinal cross-sectional view of a transistor in a photodetector according to Modification 1-6 of the second embodiment of this technology. [Figure 15A] This is a cross-sectional view showing a process for manufacturing a photodetector according to a modified example 2 of the second embodiment of this technology. [Figure 15B] This is a cross-sectional view of the process, following Figure 15A. [Figure 15C] This is a cross-sectional view of the process, following Figure 15B. [Figure 16A] This is a cross-sectional view showing a process for manufacturing a photodetector according to a modified example 3 of the second embodiment of this technology. [Figure 16B] This is a cross-sectional view of the process, following Figure 16A. [Figure 17] This is a longitudinal cross-sectional view showing the main part of a photodetector according to a modified example 4 of the second embodiment of this technology. [Figure 18A] This is a perspective view of a transistor in a photodetector according to Modification 4-1 of the second embodiment of this technology. [Figure 18B] Figure 18A is a longitudinal cross-sectional view of the transistor shown. [Figure 18C] Figure 18B is a cross-sectional view showing the cross-sectional structure when viewed along the AA cutting line. [Figure 19A] This is a perspective view of a transistor in a photodetector according to Modification 4-2 of the second embodiment of this technology. [Figure 19B] Figure 19A is a longitudinal cross-sectional view of the transistor shown. [Figure 19C] Figure 19B is a cross-sectional view showing the cross-sectional structure when viewed along the AA cutting line. [Figure 20]This is a perspective view of a transistor in a photodetector according to Modification 4-3 of the second embodiment of this technology. [Figure 21] This is a longitudinal cross-sectional view showing the main part of a photodetector according to a modified example 5 of the second embodiment of this technology. [Figure 22A] This is a longitudinal cross-sectional view of a transistor in a photodetector according to Modification 5-1 of the second embodiment of this technology. [Figure 22B] This is a cross-sectional view showing the cross-sectional structure when viewed along the AA cutting line in Figure 22A. [Figure 22C] Figure 22A is a cross-sectional view showing the cross-sectional structure when viewed along the CC cutting line. [Figure 22D] Figure 22A is a cross-sectional view showing the cross-sectional structure when viewed along the BB cutting line. [Figure 23A] This is a longitudinal cross-sectional view of a transistor in a photodetector according to modification 5-2 of the second embodiment of this technology. [Figure 23B] Figure 23A is a cross-sectional view showing the cross-sectional structure when viewed along the CC cutting line. [Figure 24A] This is a longitudinal cross-sectional view of a transistor in a photodetector according to modification 5-3 of the second embodiment of this technology. [Figure 24B] Figure 24A is a cross-sectional view showing the cross-sectional structure when viewed along the BB cutting line. [Figure 25] This is a longitudinal cross-sectional view of a transistor in a photodetector according to modification 5-4 of the second embodiment of this technology. [Figure 26] This is a longitudinal cross-sectional view of a transistor in a photodetector according to Modification 5-5 of the second embodiment of this technology. [Figure 27] This is a longitudinal cross-sectional view showing the main part of a photodetector according to a modified example 6 of the second embodiment of this technology. [Figure 28A] This figure shows the element layout of the first semiconductor layer in the photodetector according to the second embodiment of this technology. [Figure 28B] This figure shows the element layout of the second semiconductor layer in the photodetector according to the second embodiment of this technology. [Figure 29]This is a longitudinal cross-sectional view showing the main part of the photodetector according to the third embodiment of this technology. [Figure 30A] This is a schematic explanatory diagram showing the longitudinal cross-sectional structure of the second conductor in the photodetector according to the third embodiment of this technology. [Figure 30B] Figure 30A is a cross-sectional view showing the cross-sectional structure when viewed along the DD cutting line. [Figure 31A] This is a cross-sectional view showing a process for manufacturing a second conductor according to a third embodiment of this technology. [Figure 31B] This is a cross-sectional view of the process following Figure 31A. [Figure 31C] This is a cross-sectional view of the process, following Figure 31B. [Figure 31D] This is a cross-sectional view of the process, following Figure 31C. [Figure 31E] This is a cross-sectional view of the process, following Figure 31D. [Figure 32A] This is a schematic explanatory diagram showing the longitudinal cross-sectional structure of the second conductor in a photodetector according to Modification 1 of the third embodiment of this technology. [Figure 32B] Figure 32A is a cross-sectional view showing the cross-sectional structure when viewed along the DD cutting line. [Figure 33A] This is a cross-sectional view showing a process for manufacturing a second conductor according to a modified example 1 of the third embodiment of this technology. [Figure 33B] This is a cross-sectional view of the process following Figure 33A. [Figure 34] This is a longitudinal cross-sectional view showing the main part of a semiconductor device according to a modified example 2 of the third embodiment of this technology. [Figure 35] This is a longitudinal cross-sectional view showing the main part of the photodetector according to the fourth embodiment of this technology. [Figure 36A] This is a cross-sectional view showing a process for manufacturing a photodetector according to a fourth embodiment of this technology. [Figure 36B] This is a cross-sectional view of the process, following Figure 36A. [Figure 36C] This is a cross-sectional view of the process, following Figure 36B. [Figure 36D] This is a cross-sectional view of the process, following Figure 36C. [Figure 36E]This is a cross-sectional view of the process, following Figure 36D. [Figure 36F] This is a cross-sectional view of the process, following Figure 36E. [Figure 37] This is a longitudinal cross-sectional view showing the main part of a photodetector according to a modified example 1 of the fourth embodiment of this technology. [Figure 38] This is a longitudinal cross-sectional view showing the main part of a photodetector according to a modified example 2 of the fourth embodiment of this technology. [Figure 39] This is a longitudinal cross-sectional view showing the main part of a photodetector according to a modified example 3 of the fourth embodiment of this technology. [Figure 40] This is a longitudinal cross-sectional view showing the main part of a photodetector according to a modified example 4 of the fourth embodiment of this technology. [Figure 41] This is a longitudinal cross-sectional view showing the main part of a photodetector according to a modified example 5 of the fourth embodiment of this technology. [Figure 42A] This is a cross-sectional view showing a process for manufacturing a photodetector according to a modified example 5 of the fourth embodiment of this technology. [Figure 42B] This is a cross-sectional view of the process following Figure 42A. [Figure 42C] This is a cross-sectional view of the process, following Figure 42B. [Figure 43] This is a longitudinal cross-sectional view showing the main part of the photodetector according to the fifth embodiment of this technology. [Figure 44A] This is a cross-sectional view showing a process for manufacturing a photodetector according to the fifth embodiment of this technology. [Figure 44B] This is a cross-sectional view of the process following Figure 44A. [Figure 44C] This is a cross-sectional view of the process, following Figure 44B. [Figure 44D] This is a cross-sectional view of the process, following Figure 44C. [Figure 44E] This is a cross-sectional view of the process, following Figure 44D. [Figure 44F] This is a cross-sectional view of the process, following Figure 44E. [Figure 44G] This is a cross-sectional view of the process, following Figure 44F. [Figure 45A] This is a longitudinal cross-sectional view showing the main components of a conventional photodetector. [Figure 45B]This is a longitudinal cross-sectional view showing the main components of a conventional photodetector. [Figure 46] This is a longitudinal cross-sectional view showing the main part of a photodetector according to a modified example 1 of the fifth embodiment of this technology. [Figure 47A] This is a cross-sectional view showing a process for manufacturing a photodetector according to a modified example 1 of the fifth embodiment of this technology. [Figure 47B] This is a cross-sectional view of the process following Figure 47A. [Figure 48A] This is a chip layout diagram showing one example configuration of a photodetector according to a modified example 2 of the fifth embodiment of this technology. [Figure 48B] This is a longitudinal cross-sectional view showing the main part of a photodetector according to a modified example 2 of the fifth embodiment of this technology. [Figure 49] This is a schematic explanatory diagram showing the longitudinal cross-sectional structure of a plurality of second conductors in a photodetector according to the sixth embodiment of this technology. [Figure 50A] This is a cross-sectional view showing a process for manufacturing a second conductor according to the sixth embodiment of this technology. [Figure 50B] This is a cross-sectional view of the process, following Figure 50A. [Figure 50C] This is a cross-sectional view of the process, following Figure 50B. [Figure 50D] This is a cross-sectional view of the process, following Figure 50C. [Figure 50E] This is a cross-sectional view of the process, following Figure 50D. [Figure 50F] This is a cross-sectional view of the process, following Figure 50E. [Figure 50G] This is a cross-sectional view of the process, following Figure 50F. [Figure 50H] This is a cross-sectional view of the process, following Figure 50G. [Figure 51A] This is a cross-sectional view showing a process for manufacturing multiple second conductors in a conventional photodetector. [Figure 51B] This is a cross-sectional view of the process following Figure 51A. [Figure 51C] This is a cross-sectional view of the process, following Figure 51B. [Figure 52] This is a schematic explanatory diagram showing the longitudinal cross-sectional structure of a plurality of second conductors in a photodetector according to Modification 1 of the sixth embodiment of this technology. [Figure 53A] This is a cross-sectional view showing a process for manufacturing a second conductor according to a modified example 1 of the sixth embodiment of this technology. [Figure 53B] This is a cross-sectional view of the process following Figure 53A. [Figure 53C] This is a cross-sectional view of the process, following Figure 53B. [Figure 53D] This is a cross-sectional view of the process, following Figure 53C. [Figure 54] This is a longitudinal cross-sectional view showing the main part of the photodetector according to the seventh embodiment of this technology. [Figure 55A] This is a cross-sectional view showing a process for manufacturing a photodetector according to the seventh embodiment of this technology. [Figure 55B] This is a cross-sectional view of the process, following Figure 55A. [Figure 55C] Figure 55B is a plan view taken from the protective insulating film side. [Figure 55D] This is a cross-sectional view of the process, following Figure 55B. [Figure 55E] This is a cross-sectional view of the process, following Figure 55D. [Figure 55F] This is a cross-sectional view of the process, following Figure 55E. [Figure 56] This is a longitudinal cross-sectional view showing the main part of a photodetector according to Modification 1 of the seventh embodiment of this technology. [Figure 57A] This is a cross-sectional view showing a process for manufacturing a photodetector according to a modified example 1 of the seventh embodiment of this technology. [Figure 57B] This is a cross-sectional view of the process following Figure 57A. [Figure 57C] This is a cross-sectional view of the process, following Figure 57B. [Figure 57D] This is a cross-sectional view of the process, following Figure 57C. [Figure 58] This is a longitudinal cross-sectional view showing the main part of a photodetector according to a modified example 2 of the seventh embodiment of this technology. [Figure 59A] This is a cross-sectional view showing a process for manufacturing a photodetector according to a modified example 2 of the seventh embodiment of this technology. [Figure 59B] This is a cross-sectional view of the process following Figure 59A. [Figure 59C]This is a cross-sectional view of the process, following Figure 59B. [Figure 59D] This is a cross-sectional view of the process, following Figure 59C. [Figure 60] This is a longitudinal cross-sectional view showing the main part of the photodetector according to the eighth embodiment of this technology. [Figure 61A] This is a planar diagram illustrating the region where the amount of signal charge increases or decreases. [Figure 61B] This is a plan view illustrating the arrangement of the second and third conductors. [Figure 61C] This is a planar diagram illustrating the concept of canceling out increases and decreases in the amount of signal charge. [Figure 62] This is a plan view showing the arrangement of one second conductor and multiple third conductors. [Figure 63A] This is a cross-sectional view showing a process for manufacturing a photodetector according to the eighth embodiment of this technology. [Figure 63B] This is a cross-sectional view of the process following Figure 63A. [Figure 64] This is a longitudinal cross-sectional view showing the main part of a photodetector according to Modification 1 of the eighth embodiment of this technology. [Figure 65] This is a plan view showing the arrangement of one second conductor and multiple third conductors in a photodetector according to a modified example 2 of the eighth embodiment of this technology. [Figure 66] This is a plan view showing the arrangement of one second conductor and multiple third conductors in a photodetector according to a modified example 3 of the eighth embodiment of this technology. [Figure 67] This is a longitudinal cross-sectional view showing the main part of a photodetector according to a modified example 4 of the eighth embodiment of this technology. [Figure 68] This is a cross-sectional view showing a process for manufacturing a photodetector according to a modified example 4 of the eighth embodiment of this technology. [Figure 69] This is a longitudinal cross-sectional view showing the main part of a photodetector according to Modification 5 of the eighth embodiment of this technology. [Figure 70] This is a plan view showing the arrangement of the second conductor and the third conductor in a photodetector according to modification 5 of the eighth embodiment of this technology. [Figure 71A] This is a cross-sectional view showing a process for manufacturing a photodetector according to a modified example 5 of the eighth embodiment of this technology. [Figure 71B] This is a cross-sectional view of the process following Figure 71A. [Figure 72] This is a longitudinal cross-sectional view showing the main part of a photodetector according to a modified example 6 of the eighth embodiment of this technology. [Figure 73A] This is a cross-sectional view showing a process for manufacturing a photodetector according to a modified example 6 of the eighth embodiment of this technology. [Figure 73B] This is a cross-sectional view of the process following Figure 73A. [Figure 74A] This is a longitudinal cross-sectional view showing the mark and the cross-sectional structure of the second conductor provided in the photodetector according to the ninth embodiment of this technology. [Figure 74B] This is a plan view of the alignment marks provided in the optical detection device according to the ninth embodiment of this technology. [Figure 74C] This is a partially enlarged plan view showing an enlarged view of area AA in Figure 74B. [Figure 75A] This is a cross-sectional view showing a process for manufacturing a photodetector according to the ninth embodiment of this technology. [Figure 75B] This is a cross-sectional view of the process, following Figure 75A. [Figure 75C] This is a cross-sectional view of the process, following Figure 75B. [Figure 75D] This is a cross-sectional view of the process, following Figure 75C. [Figure 75E] This is a cross-sectional view of the process, following Figure 75D. [Figure 76] This is a longitudinal cross-sectional view showing the mark and the cross-sectional structure of the second conductor of a conventional photodetector. [Figure 77] This is a longitudinal cross-sectional view showing the mark and the cross-sectional structure of the second conductor provided in the photodetector according to Modification 1 of the 9th embodiment of this technology. [Figure 78A] This is a cross-sectional view showing a process for manufacturing a photodetector according to a modified example 1 of the ninth embodiment of this technology. [Figure 78B] This is a cross-sectional view of the process following Figure 78A. [Figure 78C] This is a cross-sectional view of the process, following Figure 78B. [Figure 79]This is a longitudinal cross-sectional view showing the mark and the cross-sectional structure of the second conductor provided in the photodetector according to Modification 2 of the 9th embodiment of this technology. [Figure 80A] This is a cross-sectional view showing a process for manufacturing a photodetector according to a modified example 2 of the ninth embodiment of this technology. [Figure 80B] This is a cross-sectional view of the process, following Figure 80A. [Figure 80C] This is a cross-sectional view of the process, following Figure 80B. [Figure 81] This is a longitudinal cross-sectional view showing the mark and the cross-sectional structure of the second conductor provided in the photodetector according to Modification 3 of the 9th embodiment of this technology. [Figure 82] This is a partially enlarged plan view showing an enlarged view of the alignment mark area AA provided by the optical detection device according to Modification 4 of the 9th embodiment of this technology. [Figure 83] This is a partially enlarged plan view showing an enlarged view of the alignment mark area AA provided by the optical detection device according to Modification 5 of the 9th embodiment of this technology. [Figure 84] This is a plan view of the alignment marks provided in the optical detection device according to Modification 6 of the 9th embodiment of this technology. [Figure 85] This is a longitudinal cross-sectional view showing the main part of the photodetector according to the tenth embodiment of this technology. [Figure 86A] This is a cross-sectional view showing a process for manufacturing a photodetector according to the tenth embodiment of this technology. [Figure 86B] This is a cross-sectional view of the process, following Figure 86A. [Figure 86C] This is a cross-sectional view of the process, following Figure 86B. [Figure 86D] This is a cross-sectional view of the process, following Figure 86C. [Figure 86E] This is a cross-sectional view of the process, following Figure 86D. [Figure 87] This is a longitudinal cross-sectional view showing the main components of a conventional photodetector. [Figure 88] This is a longitudinal cross-sectional view showing the main part of a photodetector according to Modification 1 of the 10th embodiment of this technology. [Figure 89]This is a longitudinal cross-sectional view showing the main part of a photodetector according to a modified example 2 of the 10th embodiment of this technology. [Figure 90A] This is a longitudinal cross-sectional view showing the main part of the photodetector according to the 11th embodiment of this technology. [Figure 90B] This is a longitudinal cross-sectional view showing the main part of the photodetector according to the 11th embodiment of this technology. [Figure 90C] Figure 90A is an explanatory diagram showing the dimensional relationship at the joint position of the seventh conductor, the eighth conductor, and the insulating film when viewed from a plan perspective. [Figure 91A] This is a cross-sectional view showing a process for manufacturing a photodetector according to the 11th embodiment of this technology. [Figure 91B] This is a cross-sectional view of the process following Figure 91A. [Figure 91C] This is a cross-sectional view of the process, following Figure 91B. [Figure 91D] This is a cross-sectional view of the process, following Figure 91C. [Figure 91E] This is a cross-sectional view of the process, following Figure 91D. [Figure 91F] This is a cross-sectional view of the process, following Figure 91E. [Figure 92A] This is a cross-sectional view showing a conventional method for manufacturing a photodetector. [Figure 92B] This is a cross-sectional view of the process, following Figure 92A. [Figure 93A] This is a longitudinal cross-sectional view showing the main part of a photodetector according to Modification 1 of the 11th embodiment of this technology. [Figure 93B] This is a longitudinal cross-sectional view showing the main part of a photodetector according to Modification 1 of the 11th embodiment of the technology. [Figure 93C] Figure 93A is an explanatory diagram showing the dimensional relationship at the joint position of the seventh conductor, the eighth conductor, and the insulating film when viewed from a plan perspective. [Figure 94A] This is a longitudinal cross-sectional view showing the main part of a photodetector according to a modified example 2 of the 11th embodiment of this technology. [Figure 94B] This is a longitudinal cross-sectional view showing the main part of a photodetector according to a modified example 2 of the 11th embodiment of this technology. [Figure 94C]Figure 94A is an explanatory diagram showing the dimensional relationship at the joint position of the seventh conductor, the eighth conductor, and the insulating film when viewed from a plan perspective. [Figure 95] This is a longitudinal cross-sectional view showing the main part of a photodetector according to a modified example 3 of the 11th embodiment of this technology. [Figure 96] This figure shows a schematic configuration of an electronic device according to the twelfth embodiment of this technology. [Figure 97] This block diagram shows an example of a schematic configuration of a vehicle control system. [Figure 98] This is an explanatory diagram showing an example of the installation location of the external information detection unit and the imaging unit. [Figure 99] This figure shows an example of a schematic configuration of an endoscopic surgical system. [Figure 100] This block diagram shows an example of the functional configuration of a camera head and CCU. [Figure 101A] This is a longitudinal cross-sectional view showing the main part of the photodetector according to the 13th embodiment of this technology. [Figure 101B] This is a magnified view of a portion of Figure 101A. [Figure 101C] This is a plan view showing an example of the positional relationship between the wiring, the connection part, the first conductor, and the second conductor in a light detection device according to the 13th embodiment of this technology. [Figure 101D] This is a plan view showing an example of the positional relationship between the wiring, the first conductor, and the second conductor in a photodetector according to the 13th embodiment of this technology. [Figure 102A] This is a cross-sectional view showing a process for manufacturing a photodetector according to the 13th embodiment of this technology. [Figure 102B] This is a cross-sectional view of the process following Figure 102A. [Figure 102C] This is a cross-sectional view of the process, following Figure 102B. [Figure 102D] This is a cross-sectional view of the process, following Figure 102C. [Figure 102E] This is a cross-sectional view of the process, following Figure 102D. [Figure 102F] This is a cross-sectional view of the process, following Figure 102E. [Figure 102G]This is a cross-sectional view of the process, following Figure 102F. [Figure 102H] This is a cross-sectional view of the process, following Figure 102G. [Figure 102I] This is a cross-sectional view of the process, following Figure 102H. [Figure 102J] This is a cross-sectional view of the process, following Figure 102I. [Figure 103A] This is a longitudinal cross-sectional view showing the main part of a photodetector according to Modification 1 of the 13th embodiment of this technology. [Figure 103B] This is a plan view showing an example of the positional relationship between the wiring, the connection part, the first conductor, and the second conductor in a photodetector according to Modification 1 of the 13th embodiment of this technology. [Figure 104A] This is a longitudinal cross-sectional view showing the cross-sectional structure of the second conductor in the photodetector according to the 14th embodiment of this technology. [Figure 104B] Figure 104A is a cross-sectional view showing the cross-sectional structure when viewed along the FF cutting line. [Figure 105A] This is a cross-sectional view showing a process for manufacturing a photodetector according to the 14th embodiment of this technology. [Figure 105B] This is a cross-sectional view of the process, following Figure 105A. [Figure 105C] This is a cross-sectional view of the process, following Figure 105B. [Figure 105D] This is a cross-sectional view of the process, following Figure 105C. [Figure 105E] This is a cross-sectional view of the process, following Figure 105D. [Figure 106] This is a plan view showing the conventional arrangement of the second conductor and the transistor. [Figure 107] This is a plan view showing the arrangement of the second conductor and the transistor in the photodetector according to the 14th embodiment of this technology. [Figure 108] This is a longitudinal cross-sectional view showing the cross-sectional structure of the second conductor in a photodetector according to Modification 1 of the 14th embodiment of this technology. [Figure 109A] This is a longitudinal cross-sectional view showing the cross-sectional structure of the second conductor in a photodetector according to a modified example 2 of the 14th embodiment of this technology. [Figure 109B]Figure 109A is a cross-sectional view showing the cross-sectional structure when viewed along the FF cutting line. [Figure 110] This is a cross-sectional view showing a process for manufacturing a photodetector according to a modified example 2 of the 14th embodiment of this technology. [Figure 111A] This is a longitudinal cross-sectional view showing the cross-sectional structure of the second conductor in a photodetector according to Modification 3 of the 14th embodiment of this technology. [Figure 111B] Figure 111A is a cross-sectional view showing the cross-sectional structure when viewed along the FF cutting line. [Figure 112] This is a cross-sectional view showing a process for manufacturing a photodetector according to a modified example 3 of the 14th embodiment of this technology. [Figure 113] This is a longitudinal cross-sectional view showing the cross-sectional structure of the second conductor in the photodetector according to the 15th embodiment of this technology. [Figure 114A] This is a cross-sectional view showing a process for manufacturing a photodetector according to the 15th embodiment of this technology. [Figure 114B] This is a cross-sectional view of the process following Figure 114A. [Figure 114C] This is a cross-sectional view of the process, following Figure 114B. [Figure 114D] This is a cross-sectional view of the process, following Figure 114C. [Figure 114E] This is a cross-sectional view of the process, following Figure 114D. [Figure 114F] This is a cross-sectional view of the process, following Figure 114E. [Figure 114G] This is a cross-sectional view of the process, following Figure 114F. [Figure 114H] This is a cross-sectional view of the process, following Figure 114G. [Figure 114I] This is a cross-sectional view of the process, following Figure 114H. [Figure 115] This is a longitudinal cross-sectional view showing the cross-sectional structure of the second conductor in a photodetector according to Modification 1 of the 15th embodiment of this technology. [Figure 116] This is a cross-sectional view showing a process for manufacturing a photodetector according to a modified example 1 of the 15th embodiment of this technology. [Figure 117A]This is a cross-sectional view showing a process for manufacturing a photodetector according to a modified example 2 of the 15th embodiment of this technology. [Figure 117B] This is a cross-sectional view of the process following Figure 117A. [Figure 118] This is a longitudinal cross-sectional view showing the main part of a photodetector according to a modified example 3 of the 15th embodiment of this technology. [Figure 119A] This is a longitudinal cross-sectional view showing a portion of the pixel area of ​​a photodetector according to the 16th embodiment of this technology. [Figure 119B] This is a magnified longitudinal cross-sectional view showing a portion of the via layer in the first wiring layer of the photodetector shown in Figure 119A. [Figure 119C] This is a plan view showing a part of the planar configuration of the via layer in the first wiring layer of the photodetector shown in Figure 119A. [Figure 119D] This is a magnified longitudinal cross-sectional view showing a portion of the via layer in the second wiring layer of the photodetector shown in Figure 119A. [Figure 120A] This is a cross-sectional view showing a process for manufacturing a photodetector according to the 16th embodiment of this technology. [Figure 120B] This is a cross-sectional view of the process, following Figure 120A. [Figure 120C] This is a cross-sectional view of the process, following Figure 120B. [Figure 120D] This is a cross-sectional view of the process, following Figure 120C. [Figure 120E] This is a cross-sectional view of the process, following Figure 120D. [Figure 120F] This is a cross-sectional view of the process, following Figure 120E. [Figure 120G] This is a cross-sectional view of the process, following Figure 120F. [Figure 121A] This is a cross-sectional view showing an enlarged portion of the metal layer of the first wiring layer of a photodetector according to a modified example 2 of the 16th embodiment of this technology. [Figure 121B] This is a plan view showing a partial planar configuration of the metal layer of the first wiring layer of a photodetector according to a modified example 2 of the 16th embodiment of this technology. [Figure 122] This is a longitudinal cross-sectional view showing the cross-sectional structure of the photodetector unit according to the 17th embodiment of this technology. [Figure 123A] This is a longitudinal cross-sectional view showing a part of the pixel area of ​​a light detection device according to the 17th embodiment of this technology. [Figure 123B] This figure shows the longitudinal cross-sectional structure and planar structure of the heat collecting section of the photodetector according to the 17th embodiment of this technology. [Figure 123C] This figure shows the longitudinal cross-sectional structure and the planar structure of the heat dissipation section of the photodetector according to the 17th embodiment of this technology. [Modes for carrying out the invention]

[0012] The following describes preferred embodiments for implementing this technology with reference to the drawings. The embodiments described below are merely examples of typical embodiments of this technology and should not be interpreted as narrowing the scope of this technology.

[0013] In the following drawings, identical or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from reality. Therefore, specific thicknesses and dimensions should be determined by referring to the following explanation. Furthermore, it is also important to note that there may be differences in the relationships and ratios of dimensions between drawings.

[0014] Furthermore, the first to twelfth embodiments described below illustrate devices and methods for realizing the technical concept of this technology, and the technical concept of this technology does not specify the materials, shapes, structures, arrangements, etc., of the components as described below. The technical concept of this technology can be modified in various ways within the technical scope defined by the claims described in the patent claims.

[0015] The explanation will be given in the following order. 1. First Embodiment 2. Second Embodiment 3. Third Embodiment 4. Fourth Embodiment 5. Fifth Embodiment 6. Sixth Embodiment 7. Seventh Embodiment 8. Eighth Embodiment 9. Ninth Embodiment 10. Tenth Embodiment 11. Eleventh Embodiment 12. Twelfth Embodiment Examples of applications in electronic devices Examples of applications to mobile devices Examples of applications to endoscopic surgical systems 13. The 13th Embodiment 14. Fourteenth Embodiment 15. 15th Embodiment 16. Sixteenth Embodiment 17. Embodiment 17

[0016] [First Embodiment] This embodiment 1 describes an example in which this technology is applied to a photodetector that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor.

[0017] ≪Overall Configuration of the Light Detection Device≫ First, the overall configuration of the light detection device 1 will be described. As shown in Figure 1, the light detection device 1 according to the first embodiment of this technology is mainly composed of a semiconductor chip 2 whose two-dimensional planar shape when viewed from above is rectangular. That is, the light detection device 1 is mounted on the semiconductor chip 2. As shown in Figure 96, this light detection device 1 takes in image light (incident light 106) from the subject through an optical system (optical lens) 102, converts the amount of light of the incident light 106 that is imaged on the imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs it as a pixel signal.

[0018] As shown in Figure 1, the semiconductor chip 2 on which the photodetector 1 is mounted comprises a rectangular pixel region 2A located in the center of a two-dimensional plane including the X and Y directions which intersect with each other, and a peripheral region 2B located outside the pixel region 2A so as to surround it.

[0019] The pixel region 2A is a light-receiving surface that receives light focused by the optical system 102, for example, as shown in Figure 96. In the pixel region 2A, multiple pixels 3 are arranged in a matrix in a two-dimensional plane including the X and Y directions. In other words, the pixels 3 are repeatedly arranged in the X and Y directions that intersect each other in the two-dimensional plane. In this embodiment, for example, the X and Y directions are orthogonal. The direction that is orthogonal to both the X and Y directions is the Z direction (thickness direction).

[0020] As shown in Figure 1, multiple bonding pads 14 are arranged in the peripheral region 2B. Each of the multiple bonding pads 14 is arranged, for example, along each of the four edges in the two-dimensional plane of the semiconductor chip 2. Each of the multiple bonding pads 14 is an input / output terminal used when electrically connecting the semiconductor chip 2 to an external device.

[0021] <Logic Circuits> As shown in Figure 2, the semiconductor chip 2 includes a logic circuit 13 that includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is composed of a CMOS (Complenentary MOS) circuit having, for example, n-channel conductivity type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and p-channel conductivity type MOSFETs as field-effect transistors.

[0022] The vertical drive circuit 4 is composed of, for example, a shift register. The vertical drive circuit 4 sequentially selects the desired pixel drive line 10, supplies pulses to the selected pixel drive line 10 to drive the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 of the pixel region 2A vertically row by row, and supplies the pixel signal from each pixel 3, based on the signal charge generated by the photoelectric conversion element of each pixel 3 according to the amount of light received, to the column signal processing circuit 5 through the vertical signal line 11.

[0023] The column signal processing circuit 5 is arranged, for example, for each column of pixels 3, and performs signal processing such as noise reduction on the signal output from one row of pixels 3 for each pixel column. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog Digital) conversion to remove pixel-specific fixed pattern noise. A horizontal selection switch (not shown) is provided at the output stage of the column signal processing circuit 5, connected to the horizontal signal line 12.

[0024] The horizontal drive circuit 6 is composed of, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuit 5, thereby sequentially selecting each of the column signal processing circuits 5, and outputting the processed pixel signals from each of the column signal processing circuits 5 to the horizontal signal line 12.

[0025] The output circuit 7 processes the pixel signals supplied sequentially from each of the column signal processing circuits 5 through the horizontal signal lines 12 and outputs them. Signal processing methods that can be used include, for example, buffering, black level adjustment, column variation correction, and various digital signal processing techniques.

[0026] The control circuit 8 generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. The control circuit 8 then outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc.

[0027] <Pixel> Figure 3 is an equivalent circuit diagram showing one example configuration of pixel 3. Pixel 3 comprises a photoelectric conversion element PD, a charge storage region (floating diffusion) FD that stores (holds) the signal charge photoelectrically converted by the photoelectric conversion element PD, and a transfer transistor TR that transfers the signal charge photoelectrically converted by the photoelectric conversion element PD to the charge storage region FD. Pixel 3 also includes a readout circuit 15 electrically connected to the charge storage region FD.

[0028] A photoelectric converter (PD) generates a signal charge in accordance with the amount of light received. The PD also temporarily stores (holds) the generated signal charge. The cathode side of the PD is electrically connected to the source region of a transfer transistor (TR), and the anode side is electrically connected to a reference potential line (e.g., ground). A photodiode is used as the PD.

[0029] The drain region of the transfer transistor TR is electrically connected to the charge storage region FD. The gate electrode of the transfer transistor TR is electrically connected to the transfer transistor drive line among the pixel drive lines 10 (see Figure 2).

[0030] The charge storage region FD temporarily stores and holds the signal charge transferred from the photoelectric conversion element PD via the transfer transistor TR.

[0031] The readout circuit 15 reads the signal charge stored in the charge storage region FD and outputs a pixel signal based on the signal charge. The readout circuit 15 is not limited to but includes, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST as pixel transistors. These transistors (AMP, SEL, RST) are composed of MOSFETs having, for example, a gate insulating film made of a silicon oxide film (SiO2 film), a gate electrode, and a pair of main electrode regions that function as a source region and a drain region. Alternatively, these transistors may be MISFETs (Metal Insulator Semiconductor FETs) in which the gate insulating film is made of a silicon nitride film (Si3N4 film), or a multilayer film such as a silicon nitride film and a silicon oxide film.

[0032] The amplifying transistor AMP has its source region electrically connected to the drain region of the selection transistor SEL, and its drain region is electrically connected to the power line Vdd and the drain region of the reset transistor. The gate electrode of the amplifying transistor AMP is electrically connected to the charge storage region FD and the source region of the reset transistor RST.

[0033] The selection transistor SEL has its source region electrically connected to the vertical signal line 11 (VSL), and its drain electrically connected to the source region of the amplification transistor AMP. The gate electrode of the selection transistor SEL is electrically connected to the selection transistor drive line among the pixel drive lines 10 (see Figure 2).

[0034] The reset transistor RST has its source region electrically connected to the charge storage region FD and the gate electrode of the amplification transistor AMP, and its drain region electrically connected to the power line Vdd and the drain region of the amplification transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line among the pixel drive lines 10 (see Figure 2).

[0035] ≪Specific Configuration of the Light Detection Device≫ Next, the specific configuration of the light detection device 1 will be explained using Figures 4A and 4B.

[0036] <Laminated structure of a photodetector> As shown in Figure 4A, the photodetector 1 (semiconductor chip 2) has a stacked structure in which a light-collecting layer 90, a first semiconductor layer 20, a first wiring layer 30, a second wiring layer 40, a second semiconductor layer 50, a third wiring layer 60, a fourth wiring layer 70, and a third semiconductor layer 80 are stacked in this order.

[0037] The light-gathering layer 90 has a stacked structure in which, although not limited to this, a color filter 91 and an on-chip lens 92 are stacked in that order from the second surface S2 side of the first semiconductor layer 20. The first semiconductor layer 20 has a photoelectric conversion region described later, and one surface is the first surface S1 and the other surface is the second surface S2 which is the light incident surface. The first wiring layer 30 is superimposed on the first surface S1 of the first semiconductor layer 20. The second wiring layer 40 is superimposed on the surface of the first wiring layer 30 opposite to the surface on the first semiconductor layer 20 side. The second semiconductor layer 50 has multiple transistors, one surface is the third surface S3 and the other surface is the fourth surface S4, and the third surface S3 is superimposed on the surface of the second wiring layer 40 opposite to the surface on the first wiring layer 30 side. The third wiring layer 60 is superimposed on the fourth surface S4 of the second semiconductor layer 50. The fourth wiring layer 70 is superimposed on the side of the third wiring layer 60 opposite to the side facing the second semiconductor layer 50. The fifth side S5 of the third semiconductor layer 80 is superimposed on the side of the fourth wiring layer 70 opposite to the side facing the third wiring layer 60.

[0038] Here, the first surface S1 of the first semiconductor layer 20 is sometimes called the device formation surface or main surface, and the second surface S2 of the first semiconductor layer 20 is sometimes called the light incident surface or back surface. Also, the third surface S3 of the second semiconductor layer 50 is sometimes called the device formation surface or main surface, and the fourth surface S4 of the second semiconductor layer 50 is sometimes called the back surface. Furthermore, the fifth surface S5 of the third semiconductor layer 80 is sometimes called the device formation surface or main surface, and the surface opposite to the fifth surface S5 is sometimes called the back surface.

[0039] Furthermore, the first semiconductor layer 20 and the second semiconductor layer 50 are joined via the first wiring layer 30 and the second wiring layer 40 using the F2F (Face to Face) method, that is, so that the device formation surfaces face each other. In addition, the second semiconductor layer 50 and the third semiconductor layer 80 are joined via the third wiring layer 60 and the fourth wiring layer 70 using the B2F (Back to Face) method, that is, so that the back surface and the device formation surface face each other.

[0040] <First Semiconductor Layer> The first semiconductor layer 20 is made of a semiconductor substrate. The first semiconductor layer 20 is made of a single-crystal silicon substrate of a first conductivity type, for example, p-type. In addition, a bonding pad 14 is provided in the region of the first semiconductor layer 20 that overlaps with the peripheral region 2B in a plan view. In the region of the first semiconductor layer 20 that overlaps with the pixel region 2A in a plan view, a photoelectric conversion region 20a is provided for each pixel 3. For example, an island-shaped photoelectric conversion region 20a partitioned by a separation region 20b is provided for each pixel 3. Note that the number of pixels 3 is not limited to that shown in Figure 4A.

[0041] The photoelectric conversion region 20a, although not shown in the figure, has a well region of a first conductivity type, for example, p-type, and a semiconductor region (photoelectric conversion section) of a second conductivity type, for example, n-type, embedded inside the well region. The photoelectric conversion element PD shown in Figure 3 is composed of a photoelectric conversion region 20a that includes the well region of the first semiconductor layer 20 and the photoelectric conversion section. The photoelectric conversion region 20a may also be provided with a charge storage region (not shown), which is a semiconductor region of a second conductivity type, for example, n-type, and a transistor T1. Transistor T1 is, for example, the transfer transistor TR shown in Figure 3.

[0042] The isolation region 20b, while not limited to this, has a trench structure in which an isolation groove is formed in the first semiconductor layer 20 and an insulating film is embedded within this isolation groove. In the example shown in Figure 4A, an insulating film and a metal are embedded within the isolation groove.

[0043] <1st wiring layer> The first wiring layer 30 includes an insulating film 31, wiring 32, a first connection pad 33, and vias (contacts) 34. The wiring 32 and the first connection pad 33 are laminated via the insulating film 31 as shown in the figure. The first connection pad 33 faces the side of the first wiring layer 30 opposite to the first semiconductor layer 20. The vias 34 connect the first semiconductor layer 20 to the wiring 32, to each other, and to the wiring 32 and the first connection pad 33, etc. The wiring 32 and the first connection pad 33 are not limited to these, but may be made of copper, for example, and may be formed by the damascene process.

[0044] <Second wiring layer> The second wiring layer 40 includes an insulating film 41, wiring 42, a second connection pad 43, and vias (contacts) 44. The wiring 42 and the second connection pad 43 are laminated via the insulating film 41 as shown in the figure. The second connection pad 43 faces the side of the second wiring layer 40 opposite to the second semiconductor layer 50 and is joined to the first connection pad 33. The vias 44 connect the second semiconductor layer 50 to the wiring 42, to each other, and to the wiring 42 and the second connection pad 43, etc. The wiring 42 and the second connection pad 43 are not limited to these, but for example, they may be made of copper and formed by the damascene process.

[0045] <Second Semiconductor Layer> The second semiconductor layer 50 is made of a semiconductor substrate. The second semiconductor layer 50 is made of a single-crystal silicon substrate, although it is not limited to this. The second semiconductor layer 50 exhibits a first conductivity type, for example, p-type. Multiple transistors T2 are provided in the second semiconductor layer 50. More specifically, the transistors T2 are provided in the region of the second semiconductor layer 50 that overlaps with the pixel region 2A in a plan view. The transistors T2 are, for example, the transistors that constitute the readout circuit 15 shown in Figure 3. In order to distinguish between the region of the second semiconductor layer 50 that overlaps with the pixel region 2A in a plan view and the region that overlaps with the peripheral region 2B in a plan view, the region that overlaps with the peripheral region 2B is called the first region 50a, and the region that overlaps with the pixel region 2A is called the second region 50b.

[0046] (First conductor and second conductor) The second semiconductor layer 50 is provided with a first conductor 51 and a second conductor 52. More specifically, the first region 50a is provided with a first conductor 51 having a first width, made of a first material, and penetrating the second semiconductor layer 50 along the thickness direction. The second region 50b is provided with a second conductor 52 having a second width smaller than the first width, made of a second material different from the first material, and penetrating the second semiconductor layer 50 along the thickness direction. The first conductor 51 and the second conductor 52 are conductors (electrodes) that penetrate the semiconductor layer. In this embodiment, since the semiconductor layer is made of silicon, the first conductor 51 and the second conductor 52 are through-silicon vias (TSVs).

[0047] The first conductor 51 is not limited to this, but can be used, for example, as a power line. Therefore, it is preferable that the first conductor 51 has low electrical resistance. Accordingly, it is preferable to use a conductive material with low electrical resistivity as the first material constituting the first conductor 51. Here, copper, which is an example of such a conductive material, is used as the first material. In addition, the resistance of the first conductor 51 can be reduced by increasing the first width. The first region 50a on which the first conductor 51 is provided has a low density of elements and wiring, so the first width can be increased.

[0048] Since the second conductor 52 is provided in the second region 50b where multiple transistors T2 are provided, it may be necessary to provide the second conductor 52 in a narrow region between transistors T2. For this reason, it is necessary to reduce the second width. Reducing the second width increases the aspect ratio of the second conductor 52. The aspect ratio of the second conductor 52 is not limited to this, but may be 5 or more, for example. With such an aspect ratio, it may be difficult to embed it with the same material as the first material (here, for example, copper). Therefore, it is preferable to use a conductive material with good embedding properties for holes with a high aspect ratio as the second material constituting the second conductor 52. Examples of such conductive materials include high-melting-point metals. Examples of high-melting-point metals include tungsten (W), cobalt (Co), ruthenium (Ru), or metallic materials containing at least one of these. Here, tungsten is used as the second material.

[0049] As shown in Figure 4B, the first conductor 51 has ends 51a and 51b in the penetration direction. The penetration direction is the direction in which the first conductor 51 penetrates the second semiconductor layer 50, and is also the thickness direction of the second semiconductor layer 50. End 51a of the first conductor 51 is located within the third wiring layer 60, and end 51b is located within the second wiring layer 40. Since the first conductor 51 has a tapered shape in the penetration direction, the diameter of end 51a is larger than the diameter of end 51b. The first width described above corresponds, for example, to the larger of the two ends of the first conductor 51 in the penetration direction. More specifically, it corresponds to the larger of the dimensions (diameter here) of end 51a and the dimensions (diameter here) of end 51b, i.e., the dimension of end 51a (diameter here). Note that the diameter is the distance between the sides and is independent of the planar shape of the first conductor 51. Here, the diameter of end 51a is represented as diameter d1.

[0050] Similarly, the second conductor 52 has ends 52a and 52b in the through-direction. The through-direction is the direction in which the second conductor 52 penetrates the second semiconductor layer 50, and is also the thickness direction of the second semiconductor layer 50. End 52a of the second conductor 52 is located within the third wiring layer 60, and end 52b is located within the second wiring layer 40. Since the second conductor 52 has a tapered shape in the through-direction, the diameter of end 52b is larger than the diameter of end 52a. The second width mentioned above corresponds, for example, to the larger of the two ends of the second conductor 52 in the through-direction. More specifically, the second width mentioned above corresponds to the larger of the dimensions (diameter) of end 52a and the dimensions (diameter) of end 52b, i.e., the dimension (diameter) of end 52b. Note that the diameter is the distance between the sides and is independent of the planar shape of the second conductor 52. Furthermore, here, the diameter of end 52b is denoted as diameter d2. And the diameter d2 of end 52b is smaller than the diameter d1 of end 51a (d2 <d1)。

[0051] Furthermore, one of the ends 51a of the first conductor 51 having a first width and the end 52b of the second conductor 52 having a second width is located in the second wiring layer 40, and the other is located in the third wiring layer 60. In the example shown in Figure 4A, the end 52b is located in the second wiring layer 40, and the end 51a is located in the third wiring layer 60.

[0052] One end of the first conductor 51 and the second conductor 52 are connected to different wirings belonging to a single metal layer, which are provided in the same wiring layer as the one end. More specifically, the end 51a of the first conductor 51 on the third wiring layer 60 side (one side) and the end 52a of the second conductor 52 on the third wiring layer 60 side (one side) are connected to wirings formed by dividing a single metal film, or wirings formed by embedding a metal film in a groove and removing the excess metal film, which are provided in the third wiring layer 60 as described later. More specifically, the single metal film is the metal film M1m of the third wiring layer 60, which will be described in the manufacturing method described later. The metal film M1m is then divided to form a plurality of wirings 62 belonging to the metal layer M1. Here, the wiring to which end 51a is connected is called wiring 62a to distinguish it from other wirings, and the wiring to which end 52a is connected is called wiring 62b to distinguish it from other wirings. Furthermore, the first metal layer is the metal layer closest to the second semiconductor layer 50 in the wiring layer on the same side as one end.

[0053] The end 51b of the first conductor 51 on the side of the second wiring layer 40 (the other side), and the end 52b of the second conductor 52 on the side of the second wiring layer 40 (the other side), are connected to the wiring 42 belonging to the metal layer M1 of the second wiring layer 40.

[0054] <3rd wiring layer> As shown in Figures 4A and 4B, the third wiring layer 60 includes an insulating film 61, wiring 62, a third connection pad 63, a barrier insulating film 64, and a silicon cover film 65. The wiring 62 and the third connection pad 63 are laminated via the insulating film 61 as shown. The third connection pad 63 faces the side of the third wiring layer 60 opposite to the second semiconductor layer 50. The wiring 62 and the third connection pad 63 are not limited to being made of copper, for example, and may be formed by the damascene process.

[0055] As shown in Figure 4B, the third wiring layer 60 has a barrier insulating film 64 provided at a position overlapping with the wiring 62 belonging to the metal layer M1 in the thickness direction. The barrier insulating film 64 has the function of preventing the diffusion of metal from the side of the barrier insulating film 64 away from the second semiconductor layer 50 to the second semiconductor layer 50. More specifically, the barrier insulating film 64, although not limited to this, prevents the diffusion of metal (copper in this case) from the wiring formed on the side of the barrier insulating film 64 away from the second semiconductor layer 50 to the second semiconductor layer 50. The barrier insulating film 64 is an insulating film, and is not limited to this, but may be, for example, a film containing silicon (Si) and nitrogen (N), a film containing silicon and carbon (C), or a SiCN film containing silicon, carbon and nitrogen. Here, the explanation will assume that the barrier insulating film 64 is a SiCN film.

[0056] The silicon cover film 65 is provided to prevent light reflection from the element and is made of a high-melting-point oxide.

[0057] <4th wiring layer> As shown in Figure 4A, the fourth wiring layer 70 includes an insulating film 71, wiring 72, a fourth connection pad 73, and vias (contacts) 74. The wiring 72 and the fourth connection pad 73 are laminated via the insulating film 71 as shown. The fourth connection pad 73 faces the side of the fourth wiring layer 70 opposite to the third semiconductor layer 80 and is joined to the third connection pad 63. The vias 74 connect the third semiconductor layer 80 to the wiring 72, to each other, and to the wiring 72 and the fourth connection pad 73, etc. The wiring 72 and the fourth connection pad 73 are not limited to these, but may be made of copper, for example, and may be formed by the damascene process.

[0058] <Third Semiconductor Layer> The third semiconductor layer 80 is made of a semiconductor substrate. The third semiconductor layer 80 is made of a single-crystal silicon substrate of the first conductivity type, for example, p-type. Multiple transistors T3 are provided in the third semiconductor layer 80. More specifically, the transistors T3 are provided in the region of the third semiconductor layer 80 that overlaps with the pixel region 2A and the peripheral region 2B in a plan view. The transistors T3 are, for example, the transistors that constitute the logic circuit 13 shown in Figure 2.

[0059] ≪Manufacturing Method for Light Detection Devices≫ The manufacturing method of the photodetector 1 will be described below with reference to Figures 5A to 5V. Note that some of the components shown in Figures 5A to 5V have different scales and shapes from those shown in Figures 4A and 4B, but this is to make the manufacturing method of the photodetector 1 easier to understand. Furthermore, the cross-section of the photodetector 1 shown in Figures 5A to 5V can also be interpreted as being different from the cross-section shown in Figures 4A and 4B.

[0060] The second conductor 52 is formed using a via-middle method. First, as shown in Figure 5A, an element such as a transistor T2 is formed on the third surface S3 side of the second semiconductor layer 50w of the first conductivity type, for example, p-type. Then, a portion of the second wiring layer 40 is formed on the third surface S3. More specifically, vias 44 and an insulating film 41 covering the vias 44 are formed on the third surface S3. Then, a resist pattern R1 is formed on the exposed surface of the insulating film 41 using known lithography techniques.

[0061] Then, etching is performed using a known etching technique with the resist pattern R1 as a mask. More specifically, the portion of the resist pattern R1 exposed from the opening R1a is etched into the interior of the second semiconductor layer 50w to form a hole 53 as shown in Figure 5B. The diameter of the hole 53 is not limited to this, but for example, it is formed to a size of 40 nm to 300 nm. The second conductor 52 formed in this hole 53 is formed to be about the same size as the hole 53. Therefore, the second width is 40 nm to 300 nm. After that, the resist pattern R1 is removed. The hole 53 is not limited to this, but for example, it may be provided in a region where transistors T2 are densely arranged. The hole 53 is not limited to this, but for example, it may be provided in a narrow region in a plan view, such as between transistors T2. In such cases, it is necessary to reduce the diameter of the hole 53 and to provide a high aspect ratio.

[0062] Next, as shown in Figure 5C, the insulating film 41m and the film 52m are sequentially laminated in this order onto the exposed surface including the inner wall of the hole 53. The insulating film 41m is made of, for example, silicon oxide (SiO2). The film 52m is a second material that constitutes the second conductor 52, and in this case, it is a tungsten film. The insulating film 41m is provided to insulate between the silicon that constitutes the second semiconductor layer 50w and the tungsten, which is the second material. Also, since the aspect ratio of the hole 53 is high, it is desirable that the insulating film 41m be laminated using a highly covering film deposition method such as atomic layer deposition (ALD). The insulating film 41m is not limited to this, but is laminated with a film thickness of, for example, about 20 nm. The film 52m made of the second material is laminated by chemical vapor deposition (CVD). As already explained, tungsten has good embedding properties, so it also has good embedding properties for the hole 53 with a high aspect ratio.

[0063] Subsequently, as shown in Figure 5D, excess portions of the insulating film 41m and film 52m are removed by etch-back and CMP (Chemical Mechanical Polishing). Furthermore, the insulating film 41 is ground until the via 44 is exposed. Here, the contents embedded in the hole 53 are referred to as pillars 53a. Pillars 53a have a two-layer structure with insulating film 41m on the outside and tungsten on the inside. Then, as shown in Figure 5E, the second wiring layer 40 is completed by forming the remaining layers of the second wiring layer 40.

[0064] Next, as shown in Figure 5F, the second semiconductor layer 50w, on which the second wiring layer 40 is stacked, and the first semiconductor layer 20, on which the first wiring layer 30 is stacked, which was prepared separately, are joined using the F2F method. Then, as shown in Figure 5G, the back side of the second semiconductor layer 50w is ground by back grinding to reduce the thickness of the second semiconductor layer 50w.

[0065] Furthermore, as shown in Figure 5H, the silicon constituting the second semiconductor layer 50w is selectively etched by known dry etching, leaving the portion that will become the second semiconductor layer 50. More specifically, the difference in etching rates between the silicon constituting the second semiconductor layer 50w and the silicon oxide constituting the insulating film 41m in a selected etchant is used to selectively etch the silicon constituting the second semiconductor layer 50w. Since the outer periphery of the column 53a is composed of the insulating film 41m, which is silicon oxide, the column 53a remains unetched, and a portion of it protrudes from the fourth surface S4 of the second semiconductor layer 50. Then, the column 53a, more specifically the second material of the column 53a, becomes a conductor that penetrates the second semiconductor layer 50. That is, a conductor that penetrates itself is formed in the second semiconductor layer 50.

[0066] Subsequently, the third wiring layer 60 is formed on the fourth surface S4 of the second semiconductor layer 50. As shown in Figure 5I, the film 65m and insulating film 61m1 of the third wiring layer 60 are laminated in this order on the exposed surface and the fourth surface S4 of the column 53a. The film 65m is a film made of a high-melting-point oxide that constitutes the silicon cover film 65, and the insulating film 61m1 is a film made of silicon oxide, for example. More specifically, the film 65m and insulating film 61m1 are laminated in this order on the fourth surface S4 so as to cover the end 53b, which is one end of the column 53a. By being covered with this insulating film 61m1, the end 53b of the column 53a is no longer exposed. The one end of the column 53a is the end closer to the fourth surface S4 in the penetrating direction in which the column 53a penetrates the second semiconductor layer 50.

[0067] Then, as shown in Figure 5J, the exposed surface of the insulating film 61m1 is flattened using the CMP method. At this time, the tungsten of the column 53a may be exposed by grinding and recessing the end 53b using the CMP method. Furthermore, the portion of the film 65m that is laminated around the column 53a is removed by washing with a chemical solution. This forms the silicon cover film 65 shown in Figure 4A.

[0068] Next, as shown in Figure 5K, an insulating film 61m2 is laminated to cover the end 53b of the column 53a. By being covered with this insulating film 61m2, the end 53b of the column 53a is no longer exposed.

[0069] Then, as shown in Figure 5L, a resist pattern R2 is formed on the exposed surface of the insulating film 61m2 using a known lithography technique, and etching is performed using a known etching technique with the resist pattern R2 as a mask. More specifically, the portion of the resist pattern R2 exposed to the opening R2a is etched to form a hole 54h that penetrates the second semiconductor layer 50 through the insulating film 61m2 and reaches the second wiring layer 40.

[0070] Subsequently, as shown in Figure 5M, an insulating film 61m3, for example, made of silicon oxide, is laminated onto the inner wall of the hole 54h and the exposed surface of the insulating film 61m2. Then, as shown in Figure 5N, the insulating film at the bottom of the hole 54h is removed by etch-back until it reaches the wiring 42, thereby obtaining the hole 54. The diameter of the hole 54 is not limited to this, but is formed to be, for example, between 1 μm and 5 μm. The first conductor 51 formed in this hole 54 is formed to be approximately the same size as the hole 54. Therefore, the first width is between 1 μm and 5 μm. From this point forward, the insulating films 61m1, 61m2, and 61m3 will not be distinguished and will simply be referred to as insulating film 61m.

[0071] Next, as shown in Figure 5O, a film 51m made of the first material, namely copper, is laminated onto the exposed surface of the insulating film 61m. The film 51m is laminated so as to fill the holes 54. Since the holes 54 have a sufficiently larger diameter and a lower aspect ratio compared to the holes 53 shown in Figure 5B, copper, which has inferior filling properties than tungsten, can fill the holes 54.

[0072] Then, the excess portion of the film 51m shown in Figure 5O is removed by the CMP method. Here, since the end 53b of the column 53a is covered with the insulating film 61m, the column 53a and its end 53b are less likely to be ground by the CMP grinding method. In other words, the exposure of the cross-section of the column 53a is suppressed. This suppresses the simultaneous grinding of the copper of the film 51m and the tungsten of the column 53a. When the excess portion of the film 51m shown in Figure 5O is removed by the CMP method, the state shown in Figure 5P is obtained. Here, the contents embedded in the hole 54 are called the column 54a. In this process, the first material constituting the column 54a becomes another conductor that penetrates the second semiconductor layer 50. In other words, it forms another conductor that penetrates itself in the second semiconductor layer 50. The exposed end of the column 54a is called the end 53b. Since the aspect ratio of the hole 54 is low, the aspect ratio of the column 54a is also low.

[0073] Next, as shown in Figure 5Q, the barrier insulating film 64 and insulating film 61m4 of the third wiring layer 60 are laminated on the exposed surface of the insulating film 61m in this order. More specifically, the barrier insulating film 64 and insulating film 61m4 are laminated so as to cover one end of the column 54a, i.e., end 54b. The one end of the column 54a is the end closer to the fourth surface S4 in the penetrating direction in which the column 54a penetrates the second semiconductor layer 50. When insulating film 61m and insulating film 61m4 are not distinguished, they are simply referred to as insulating film 61.

[0074] Subsequently, as shown in Figure 5R, a resist pattern R3 is formed on the exposed surface of the insulating film 61m4 using a known lithography technique, and etching is performed using a known etching technique with the resist pattern R3 as a mask. More specifically, the insulating film 61m4 exposed from the opening R3a of the resist pattern R3 is etched until it reaches the barrier insulating film 64, thereby forming multiple openings 66 for forming the wiring 62. That is, the barrier insulating film 64 also functions as an etching stop layer. After that, the resist pattern R3 is removed.

[0075] Here, the larger the opening R3a of the resist pattern R3, the lower the aspect ratio of the opening 66 formed by etching, and the smaller the opening R3a, the higher the aspect ratio of the opening 66. Also, generally, the higher the aspect ratio of the opening 66, the slower the etching rate of the opening 66, and the lower the aspect ratio of the opening 66, the faster the etching rate of the opening 66. An opening 66a, which is formed to overlap with a column 54a in a plan view, has a lower aspect ratio than, for example, an opening 66b, which is formed to overlap with a column 53a in a plan view. Therefore, etching of opening 66a proceeds faster than etching of opening 66b. Here, in order to reset the difference in etching rate caused by the difference in the width of the openings 66, etching of all openings 66 is temporarily stopped by the barrier insulating film 64. The barrier insulating film 64, which functions as an etching stop layer, temporarily stops the etching of the opening 66a, thus preventing the copper column 54a from being etched before the opening 66b and other openings 66 reach the barrier insulating film 64. This suppresses an increase in the amount of etching on the copper column 54a. In addition, the barrier insulating film 64 plays a role in protecting the column 54a during the process of removing the resist pattern R3.

[0076] Next, as shown in Figure 5S, the exposed portion of the barrier insulating film 64, i.e., the portion that functioned as an etching stop layer, is removed by etching at all openings 66. Then, as shown in Figure 5T, the insulating film 61m is etched at all openings 66. Since all etching is temporarily stopped by the barrier insulating film 64, etching of the insulating film 61m can be started almost simultaneously at all openings 66. Furthermore, the etching shown in Figure 5T is continued until the end portion 53b of the column 53a is exposed. In addition, the portion of the barrier insulating film 64 that remains without being removed functions as a barrier insulating film.

[0077] As shown in Figure 5T, the end 53b of column 53a and the end 54b of column 54a may protrude from the bottom of the opening 66. By providing the ends 53b and 54b in this manner, the contact area with the wiring 62 embedded in the opening 66 is increased, improving the tightness with the wiring 62.

[0078] Subsequently, as shown in Figure 5U, a metal film M1m is laminated onto the inner wall of the opening 66 and the exposed surface of the insulating film 61m4. Then, as shown in Figure 5V, the excess portion of the metal film M1m is removed by the CMP method. This divides the metal film M1m and forms the wiring 62 belonging to the metal layer M1. The tungsten portion of the column 53a connected to the wiring 62b corresponds to the second conductor 52, and the column 54a connected to the wiring 62a corresponds to the first conductor 51.

[0079] Next, although not shown in the diagram, the remaining layers of the third wiring layer 60 are formed. Then, although the order of the process is not limited to this, the second semiconductor layer 50 on which the third wiring layer 60 is stacked and the third semiconductor layer 80 on which the separately prepared fourth wiring layer 70 is stacked are joined using the B2F method. Then, a light-collecting layer 90 is formed on the light incident surface side. This completes the photodetector 1. The photodetector 1 is formed in each of the multiple chip formation regions demarcated by scribe lines (dicing lines) on the semiconductor substrate. Then, by dividing these multiple chip formation regions individually along the scribe lines, a semiconductor chip 2 on which the photodetector 1 is mounted is formed.

[0080] ≪Effect≫ The operation of the light detection device 1 will now be explained. As shown in Figure 4B, the first conductor 51 electrically connects the wiring 42 provided in the second wiring layer 40 and the wiring 62a provided in the third wiring layer 60. The second conductor 52 electrically connects the wiring 42 provided in the second wiring layer 40 and the wiring 62b provided in the third wiring layer 60.

[0081] <<Main effects of the first embodiment>> The main effects of the first embodiment will be described below. Before that, galvanic corrosion will be explained. When a plurality of different metals are exposed in an electrolyte solution, the lower metal is selectively corroded. This is called galvanic corrosion. For example, when dissimilar metals are exposed in the liquid during the CMP process, the metal with a higher ionization tendency elutes due to galvanic corrosion. For example, when copper and cobalt are exposed in the liquid, cobalt elutes, so it was not possible to form a mixture of copper (noble metal) TSVs and cobalt (base metal) TSVs that penetrate a single semiconductor layer.

[0082] On the other hand, in the photodetector 1 according to the first embodiment of the present technology, one conductor that penetrates itself is formed in the second semiconductor layer 50, an insulating film 61 is laminated so as to cover one end of the one conductor, and from the insulating film 61 side, another conductor made of a material different from the material constituting the one conductor and having a diameter larger than the diameter of the one conductor is formed so as to penetrate the second semiconductor layer 50, and wirings 62b connected to the one conductor and 62a connected to the other conductor are formed from the insulating film 61 side. Therefore, since it is suppressed that both the one conductor and the other conductor are exposed in the solution, it is possible to suppress the occurrence of galvanic corrosion. Therefore, the first conductor 51 and the second conductor 52 made of different materials can be provided.

[0083] Also, in the photodetector 1 according to the first embodiment of the present technology, since the occurrence of galvanic corrosion can be suppressed, the first conductor 51 that is required to have a low resistance can be formed with a large diameter and made of copper, and the second conductor 52 provided in a narrow region can be made of a metal such as tungsten that has good embedding properties even with a fine diameter that is difficult to embed with copper.

[0084] Furthermore, in the photodetector 1 according to the first embodiment of the present technology, since the first conductor 51 having a large diameter and a low resistance is provided in the first region 50a of the second semiconductor layer 50 that overlaps the peripheral region 2B in plan view, the photodetector 1 can be made to consume less power and can be further speeded up.

[0085] In addition, in the photodetection device 1 according to the first embodiment of the present technology, since the second conductor 52 has a high aspect ratio and a fine diameter, it can be provided in a narrow region in a plan view. For example, it can be provided in a second region 50b that overlaps with the pixel region 2A in a plan view in the second semiconductor layer 50. More specifically, the second conductor 52 can be provided in the second region 50b so as to be sandwiched between the transistors T2. That is, fine TSVs can be arranged in the pixel 3. Thereby, the degree of freedom in the design of the photodetection device 1 is increased.

[0086] Furthermore, in the photodetection device 1 according to the first embodiment of the present technology, since the second conductor 52 having a high aspect ratio can be formed, even when the thickness of the second semiconductor layer 50 is relatively thick, the second conductor 52 penetrating the second semiconductor layer 50 can be provided. For example, but not limited to this, even when the thickness of the second semiconductor layer 50 exceeds 1 micron, the second conductor 52 can be formed.

[0087] In addition, in the photodetection device 1 according to the first embodiment of the present technology, since the second conductor 52 can be provided with a fine diameter, an increase in the dimensions of the photodetection device 1 and the pixel 3 can be suppressed. Further, since the second conductor 52 has a fine diameter, the influence of the second conductor 52 on the transistor T2 can be suppressed, and an increase in the keep-out distance between the second conductor 52 and the transistor T2 can be suppressed. The keep-out distance is a distance at which the influence of the second conductor 52 on the transistor T2 can be suppressed to a certain amount or less.

[0088] Furthermore, in the photodetection device 1 according to the first embodiment of the present technology, for example, the first conductor 51 used as a power supply line with a high voltage and the fine second conductor 52 are provided in different regions of the second semiconductor layer 50, that is, provided separately, so that the influence of the second conductor 52 received from the first conductor 51 can be reduced, and the reliability of the photodetection device 1 can be improved.

[0089] In the first embodiment described above, column 53a had a two-layer structure with an insulating film 41m on the outside and tungsten on the inside. However, it is not limited to this, and other layers such as a barrier metal layer may be present between the insulating film 41m and the film 52m. Also, other layers such as a barrier metal layer may be provided between column 54a and the insulating film 61. The barrier metal is not limited to this, but for example, titanium nitride (TiN) and functions as an adhesion layer that brings the insulating film and tungsten into close contact.

[0090] Furthermore, in the first embodiment described above, both the end 51b of the first conductor 51 on the second wiring layer 40 side (the other side) and the end 52b of the second conductor 52 on the second wiring layer 40 side (the other side) are connected to wiring 42 belonging to the same metal layer (metal layer M1) of the second wiring layer 40. However, the invention is not limited to this, and the wiring 42 may be connected to wiring 42 belonging to different metal layers (for example, metal layer M1 and metal layer M2).

[0091] Furthermore, the first semiconductor layer 20 may contain all the elements of the pixel 3 circuit shown in Figure 3. In that case, transistor T1 may be a transistor that constitutes the pixel 3 circuit shown in Figure 3. In addition, capacitors, analog circuits, logic circuits, memory circuits, etc., may be appropriately combined and arranged in the second semiconductor layer 50 and the third semiconductor layer 80 as signal processing circuits downstream of the circuit shown in Figure 3. In that case, transistors T2 and T3 may be transistors that constitute those circuits.

[0092] Furthermore, although the first conductor 51 was used as a power line in the first embodiment described above, it is not limited to this and may also be a signal output line to the outside of the semiconductor chip 2, a drive line for each transistor within the semiconductor chip 2, a reference potential line, or other paths. In addition, the second conductor 52 may function as a vertical signal line when the read circuit 15 is formed on the second semiconductor layer 50, or as a connection path from the circuit formed on the first semiconductor layer 20 to the circuit formed on the third semiconductor layer 80 when the read circuit 15 is formed on the first semiconductor layer 20.

[0093] The first conductor 51 and the second conductor 52 may be made of the same material, provided their dimensions (in this case, diameter) are different. Conversely, if they are made of different materials, their dimensions (in this case, diameter) may be the same.

[0094] [Modification 1 of the First Embodiment] A modification 1 of the first embodiment of this technology, shown in Figure 6, will be described below. The difference between the photodetector 1 according to this modification 1 of the first embodiment and the photodetector 1 according to the first embodiment described above lies in the method of bonding the semiconductor layers; the other configurations of the photodetector 1 are basically the same as those of the photodetector 1 according to the first embodiment described above. Components that have already been described are denoted by the same reference numerals and their descriptions are omitted.

[0095] The first semiconductor layer 20 and the second semiconductor layer 50 are joined via the first wiring layer 30 and the third wiring layer 60 using the F2B (Back to Face) method, that is, so that the device formation surface and the back surface face each other. Furthermore, the second semiconductor layer 50 and the third semiconductor layer 80 are joined via the second wiring layer 40 and the fourth wiring layer 70 using the F2F (Back to Face) method, that is, so that the device formation surfaces face each other.

[0096] <<Main effects of Modification 1 of the First Embodiment>> Even with the light detection device 1 according to this modified example 1 of the first embodiment, the same effects as the light detection device 1 according to the first embodiment described above can be obtained.

[0097] [Modification 2 of the First Embodiment] A modification 2 of the first embodiment of this technology, shown in Figure 7, will be described below. The difference between the photodetector 1 according to this modification 2 of the first embodiment and the photodetector 1 according to the first embodiment described above is that the second conductor 52 is formed using a via last method, while the other configurations of the photodetector 1 are basically the same as those of the photodetector 1 according to the first embodiment described above. Components that have already been described will be denoted by the same reference numerals and their descriptions will be omitted.

[0098] <Second conductor> Since the second conductor 52 is formed of via last, the second conductor 52 exhibits a tapered shape in the through-direction that is opposite to that of the first embodiment described above. Therefore, the diameter of end 52a is larger than the diameter of end 52b. The second width described above corresponds to, for example, the larger of the two ends of the second conductor 52 in the through-direction. More specifically, the second width described above corresponds to the larger of the dimensions (here, diameter) of end 52a and the dimensions (here, diameter) of end 52b, i.e., the dimension of end 52a (here, diameter). Note that the diameter is the distance between the sides and is independent of the planar shape of the second conductor 52. Here, the diameter of end 52a is represented as diameter d2. Both the end 51a of the first conductor 51, which has the first width, and the end 52a of the second conductor 52, which has the second width, are located in the same wiring layer of the second wiring layer 40 and the third wiring layer 60. In this case, both end 51a shown in Figure 4A and end 52a shown in Figure 7 are located in the third wiring layer 60.

[0099] ≪Manufacturing Method for Light Detection Devices≫ The manufacturing method of the photodetector 1 will be described below with reference to Figures 8A and 8B. Only the differences from the manufacturing method of the photodetector 1 described in the first embodiment above will be explained here.

[0100] In the manufacturing method of the photodetector 1 according to the modified example 2 of the first embodiment, the order of steps for forming the second conductor 52 differs from the manufacturing method of the photodetector 1 according to the first embodiment described above. Therefore, the resist pattern R1 is not formed in the step shown in Figure 5A. The second wiring layer 40 is first completed on the third surface S3 side of the second semiconductor layer 50w. After that, the second semiconductor layer 50w on which the second wiring layer 40 is laminated and the first semiconductor layer 20 on which the first wiring layer 30 is laminated, which has been prepared separately, are joined by the F2F method. Then, the second semiconductor layer 50w is ground by back grinding, leaving the portion that will become the second semiconductor layer 50.

[0101] Next, as shown in FIG. 8A, a film 65m constituting a silicon cover film 65 and an insulating film 61m5 are laminated in this order on the fourth surface S4 of the second semiconductor layer 50. Then, a hole 53h penetrating the second semiconductor layer 50 is formed from the insulating film 61m5 side. Thereafter, an insulating film 41m is laminated on the inner wall of the hole 53h and the exposed surface of the insulating film 61m5 by atomic layer deposition. At this time, the insulating film 61m5 may be laminated so that the internal space of the hole 53h is filled.

[0102] Then, as shown in FIG. 8B, a hole 53i penetrating the second semiconductor layer 50 and reaching the wiring 42 of the second wiring layer 40 is formed by a known etching technique, a combination of a lithography technique and an etching technique, or the like. Thereafter, tungsten is embedded in the hole 53i. Thereby, a second conductor 52 (one conductor) is formed. Then, an insulating film is laminated so as to cover the exposed surfaces of the second conductor 52 and the insulating film 61m5, and the steps shown in FIG. 5L and subsequent steps are performed as in the case of the first embodiment.

[0103] ≪Main effects of Modified Example 2 of the First Embodiment≫ Even in the photodetector 1 according to the modified example 2 of the first embodiment, the same effects as those of the photodetector 1 according to the above-described first embodiment can be obtained.

[0104] [Modified Example 3 of the First Embodiment] A modified example 3 of the first embodiment of the present technology shown in FIG. 9 will be described below. The photodetector 1 according to the modified example 3 of the first embodiment is different from the above-described first embodiment in that the transistor T2 is a fin-type MOSFET, and the configuration of the photodetector 1 other than that is basically the same as the configuration of the photodetector 1 of the above-described first embodiment. For the components that have already been described, the same reference numerals are given and the description thereof is omitted.

[0105] Transistor T2 is a fin-type MOSFET (hereinafter also referred to as "FinFET") and has multiple fins T2f. The fins T2f are formed in a convex shape on the third surface S3 side of the second semiconductor layer, and can form a channel. The gate electrode TG of transistor T2 is provided so as to cover the tip of the fin T2f via a gate insulating film 41G. Although not shown in the illustration, in the direction perpendicular to the plane of the paper in Figure 9, one end of the fin T2f is provided as the source region of transistor T2, and the other end is provided as the drain region of transistor T2. Therefore, the channel of transistor T2 is formed to extend in the direction perpendicular to the plane of the paper.

[0106] As shown in Figure 9, the second conductor 52 penetrates the region of the second semiconductor layer 50 between the FinFET transistors T2. The end 52b of the second conductor 52 is connected to the wiring 42M0. The wiring 42M0 is made of, but is not limited to, tungsten. The wiring 42M0 is connected to the wiring 42.

[0107] <<Main effects of Modification 3 of the First Embodiment>> Even with the photodetector 1 according to this modified example 3 of the first embodiment, the same effects as the photodetector 1 according to the first embodiment described above can be obtained.

[0108] Although the second conductor 52 described above was columnar, it is not limited to this and may be the second conductor 52L shown in Figure 10. The second conductor 52L is a wall-shaped conductor extending in the direction perpendicular to the plane of the paper in Figure 10.

[0109] Hereinafter, the thickness of the second conductor 52L represents the thickness of the wall-shaped conductor. More specifically, the thickness of the second conductor 52L is the thickness in a direction perpendicular to both the through direction and the direction perpendicular to the plane of FIG. 10. The second conductor 52L has an end portion 52La and an end portion 52Lb in the through direction. The end portion 52Lb is connected to the wiring 42M0 via the via 44V0. The through direction is the direction in which the second conductor 52L penetrates the second semiconductor layer 50, and is also the thickness direction of the second semiconductor layer 50. The end portion 52La of the second conductor 52 is located within the third wiring layer 60, and the end portion 52Lb is located within the second wiring layer 40.

[0110] And, the second width of the second conductor 52L corresponds to, for example, the larger dimension among the end portions of the second conductor 52L in the through direction. More specifically, the second width corresponds to the larger of the dimensions (here, the thickness) of the end portion 52La and the dimension (here, the thickness) of the end portion 52Lb, that is, the dimension (here, the thickness) of the end portion 52Lb. Here, the thickness of the end portion 52Lb is represented as the thickness d2. And, the thickness d2 of the end portion 52Lb is smaller than the diameter d1 of the end portion 51a of the first conductor 51 described above (d2 < d1). Also, even for such a second conductor 52L, the same effects as those of the second conductor 52 in the third modification of the first embodiment can be obtained.

[0111] [Fourth Modification of the First Embodiment] The fourth modification of the first embodiment of the present technology shown in FIG. 4C will be described below. An insulating film 61m3 is provided between the first conductor 51 and the second semiconductor layer 50 of the photodetection device 1 according to the fourth modification of the first embodiment. The configuration of the photodetection device 1 other than this is basically the same as the configuration of the photodetection device 1 of the first embodiment described above. For the components that have already been described, the same reference numerals are given and the description thereof is omitted. Also, when the insulating film 61m3 is not distinguished from the other insulating film 61, it may be referred to as the insulating film 61.

[0112] Hereinafter, with reference to Figures 5L, 5W, and 5X, a method for manufacturing a photodetector 1 according to a modified example 4 of the first embodiment of this technology will be described. First, as shown in Figure 5L, the portion of the resist pattern R2 exposed to the opening R2a is etched to form a hole 54h for embedding the first conductor 51. The hole 54h penetrates the second semiconductor layer 50. Then, as shown in Figure 5W, an insulating film 61m3 made of, for example, silicon oxide is laminated to cover the bottom surface and side walls of the hole 54h.

[0113] Here, the hole 54h is formed to be shallower than the first conductor 51 embedded in the hole 54h. More specifically, as shown in Figure 5W, an insulating film 41 remains between the bottom surface of the hole 54h and the wiring 42, and the copper wiring 42 of the second wiring layer 40 is not exposed to the bottom surface of the hole 54h. This is to suppress the etching of the copper wiring 42 and the scattering of copper during the etching process that forms the hole 54h. Furthermore, an insulating film 61m3 is deposited on the bottom surface of the hole 54h.

[0114] Next, as shown in Figure 5X, the insulating film 61m3 deposited on the bottom surface of the hole 54h and the insulating film 41 remaining on the bottom surface of the hole 54h are etched to form a hole 54 that reaches the wiring 42. This electrically connects the first conductor 51 embedded in the hole 54 to the wiring 42. The insulating film 61m3 remaining on the side wall of the hole 54 functions as a sidewall that electrically insulates the first conductor 51 from the second semiconductor layer 50. Also, since the insulating film 61m3 is laminated within the hole 54h, the insulating film 61m3 that functions as a sidewall does not reach the wiring 42. The subsequent manufacturing method is the same as in the first embodiment, so the explanation is omitted.

[0115] Even with the photodetector 1 according to this modified example 4 of the first embodiment, the same effects as the photodetector 1 according to the first embodiment described above can be obtained.

[0116] Furthermore, in the photodetector 1 according to the modified example 4 of this first embodiment, when forming the hole 54h, an insulating film 41 is left between the bottom surface of the hole 54h and the wiring 42, so that the copper constituting the wiring 42 is not exposed.

[0117] In the first embodiment described above, the barrier insulating film 64 functions as an etching stop layer when etching the insulating film 61m4(61) to form the opening 66. Therefore, the barrier insulating film 64 is made of a material whose etching rate for the selected etchant is higher than that of the material constituting the insulating film 61m4(61). In addition, the barrier insulating film 64 has the function of suppressing the diffusion of metal from the side of the barrier insulating film 64 away from the second semiconductor layer 50 to the second semiconductor layer 50 side of the barrier insulating film 64.

[0118] Furthermore, the photoelectric conversion region 20a only needs to have the function of performing photoelectric conversion on incident light in at least a portion of its region.

[0119] Furthermore, in the photodetector 1 shown in Figure 6, one side of the first wiring layer 30 is superimposed on the first surface S1 of the first semiconductor layer 20, and the other side is superimposed on the third wiring layer 60. More specifically, the other side of the first wiring layer 30 is superimposed on the side of the third wiring layer 60 opposite to the second semiconductor layer 50. The first connection pad 33 and the third connection pad 63 are then joined. Similarly, one side of the fourth wiring layer 70 is superimposed on the third semiconductor layer 80, and the other side is superimposed on the second wiring layer 40. More specifically, the other side of the fourth wiring layer 70 is superimposed on the side of the second wiring layer 40 opposite to the second semiconductor layer 50. The second connection pad 43 and the fourth connection pad 73 are then joined. The configuration of the photodetector 1 shown in Figure 6 can also be applied to the photodetectors according to the second to eleventh embodiments described below.

[0120] [Second Embodiment] A second embodiment of the present technology, shown in Figures 11 and 12A to 12D, will be described below. The difference between the photodetector 1 of this second embodiment and the photodetector 1 of the first embodiment described above is that it has a second conductor 52A instead of the second conductor 52, and the rest of the configuration of the photodetector 1 is basically the same as that of the photodetector 1 of the first embodiment described above. Components that have already been described will be denoted by the same reference numerals and their descriptions will be omitted.

[0121] <<Configuration of the light detection device>> The following describes the configuration of the photodetector 1 according to the second embodiment of this technology, focusing on the differences from the configuration of the photodetector 1 according to the first embodiment described above. Note that in the drawings illustrating this second embodiment, the same components may be depicted with different scales between drawings. Also, the barrier metal layer is omitted from the drawings illustrating this second embodiment.

[0122] <Second wiring layer> As shown in Figure 11, the wiring 42, second connection pad 43, and via 44 of the second wiring layer 40 are conductors provided in the second wiring layer 40. These conductors are connected according to the design to form an electrical path within the second wiring layer 40. The electrical path is not limited to this, but may be, for example, a path through which electricity such as signal charges flows, or a path that supplies voltage. Note that the electrical path shown in Figure 11 is just one example, and this technology is not limited to this.

[0123] <3rd wiring layer> The third wiring layer 60 includes an insulating film 61, wiring 62, a third connection pad 63, a silicon cover film 65, and vias (contacts) 67. The wiring 62, the third connection pad 63, and the vias 67 are conductors provided in the third wiring layer 60. These conductors are connected according to the design to form an electrical path within the third wiring layer 60. The electrical path is not limited to this, but may be, for example, a path through which electricity such as signal charges flows, or a path that supplies voltage. Note that the electrical path shown in Figure 11 is just one example, and this technology is not limited to this.

[0124] <Second conductor> The second conductor 52A is located in a different position from the second conductor 52 shown in Figure 4A. More specifically, the second conductor 52A is located in a position where a channel can be formed between the source and drain of transistor T2. The second conductor 52A penetrates the second semiconductor layer 50 along the Z direction and functions as the gate electrode G of transistor T2 (first transistor) on the second semiconductor layer 50. The insulating film 41m provided between the side surface of the second conductor 52A and the second semiconductor layer 50 functions as the gate insulating film of transistor T2 (first transistor). Transistor T2 turns on and off depending on the voltage value supplied to the second conductor 52A. Transistor T2 is, for example, a normally-off transistor, but it may also be a normally-on transistor. When transistor T2 is in the ON state, the portion of the second semiconductor layer 50 adjacent to the side surface of the second semiconductor layer 50 via the insulating film 41m is modulated, a channel is formed between the source S and drain D, and signal charge flows. In the following explanation, the second conductor 52A may be referred to as the gate electrode G. Transistor T2 is a planar transistor, and is, for example, a transistor that constitutes the circuit after pixel 3.

[0125] The following explanation will be given with reference to Figures 12A to 12D. In this second embodiment, the insulating film 41m may be omitted from the drawings from Figure 12A onward. Furthermore, in this second embodiment, in the drawings from Figure 12A onward, the insulating film may be shown through the insulating film to clearly explain the relationship between the source S, drain D, gate electrode G and vias, but this does not mean that the insulating film does not exist.

[0126] As shown in Figures 12A to 12D, the gate electrode G can form a channel between the source S and drain D of transistor T2. The source S and drain D are semiconductor regions (diffusion regions) of a second conductivity type, such as n-type, formed within the second semiconductor layer 50. As shown in Figures 12C and 12D, the gate electrode G is not positioned on the straight line connecting the source S and drain D, but is positioned at an offset from that line.

[0127] As shown in Figures 11 and 12D, the end 52a of the second conductor 52A (gate electrode G) on the third wiring layer 60 side is connected to via 67. This connects the gate electrode G to an electrical path provided within the third wiring layer 60. The electrical path connected to the gate electrode G is, for example, a path capable of supplying voltage to the gate electrode G. More specifically, the gate electrode G is electrically connected only to the electrical path provided within the third wiring layer 60, out of the two electrical paths provided within the second wiring layer 40. In other words, the electrical path connected to the gate electrode G includes only one of the conductors (the conductor in the third wiring layer 60) and not the other conductor (the conductor in the second wiring layer 40). Thus, the electrical path capable of supplying voltage to the second conductor 52A passes through only one of the two wiring layers superimposed on the second semiconductor layer 50, and not the other.

[0128] As shown in Figures 11, 12B, and 12C, source S is connected to one via 44. That is, source S is connected to an electrical path provided in the second wiring layer 40. Similarly, drain D is connected to another via 44. That is, drain D is connected to an electrical path provided in the second wiring layer 40. In this way, source S and drain D are electrically connected to the other conductor (the conductor provided in the second wiring layer 40) of the conductors provided in the second wiring layer 40 and the conductors provided in the third wiring layer 60, but are not connected to the other conductor (the conductor provided in the third wiring layer 60).

[0129] The second material constituting the second conductor 52A is, but is not limited to, polysilicon (Poly-Si). Furthermore, if transistor T2 is a p-type transistor, the second material may be hafnium, zirconium, titanium, tantalum, aluminum, and metal carbides containing these elements, such as titanium carbide, zirconium carbide, tantalum carbide, hafnium carbide, and aluminum carbide. If transistor T2 is an n-type transistor, the second material may be ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide and tungsten. In this embodiment, the second material is described as polysilicon.

[0130] ≪Manufacturing Method for Light Detection Devices≫ The method for manufacturing the photodetector 1 will be described below with reference to Figures 13A to 13E. Note that some components shown in Figures 13A to 13E may have different scales or shapes than those shown in Figure 11; this is to make the method for manufacturing the photodetector 1 easier to understand. Furthermore, the cross-sections of the photodetector 1 shown in Figures 13A to 13E can also be interpreted as being different from the cross-section shown in Figure 11. In addition, the method for manufacturing the photodetector 1 according to the second embodiment of this technology will be described focusing on the differences from the method for manufacturing the photodetector 1 according to the first embodiment described above.

[0131] First, as shown in Figure 13A, a second conductor 52A and an insulating film 41m are formed on the second semiconductor layer 50w, and a second wiring layer 40 is formed on the third surface S3 of the second semiconductor layer 50w. The use of polysilicon as the material constituting the second conductor 52A and the position where the second conductor 52A is provided differ from the manufacturing method described in the first embodiment above, but everything else is the same as in the first embodiment, so the explanation is omitted here. Subsequently, the second semiconductor layer 50w on which the second wiring layer 40 is laminated and the first semiconductor layer 20 on which the first wiring layer 30 is laminated, which has been prepared separately, are joined by the F2F method.

[0132] Next, as shown in Figure 13B, the back surface of the second semiconductor layer 50w is ground by back grinding and known dry etching to expose the ends of the second conductor 52A and the insulating film 41m. At this time, the insulating film 41m acts as a stopper for dry etching.

[0133] Then, as shown in Figure 13C, the film 65m of the third wiring layer 60 and the insulating film 61m1 are laminated in this order on the exposed surface of the insulating film 41m and the fourth surface S4. After that, as shown in Figure 13D, the third wiring layer 60 side is flattened using the CMP method. At this time, excess portions of the insulating film 61m1 and the second conductor 52A are removed.

[0134] Next, as shown in Figure 13E, vias 67 are formed so as to overlap the end of the second conductor 52A. After that, the third wiring layer 60 is completed. The subsequent steps are the same as those described in the first embodiment, so their explanation is omitted.

[0135] <<Main effects of the second embodiment>> The main effects of the second embodiment will be explained below, but before that, the configuration of the transistor T2 shown in Figure 4A of the first embodiment will be explained. In the transistor T2 shown in Figure 4A, the gate electrode is connected to a via 44 of the second wiring layer 40, and after the via 44, a wiring 42, a second conductor 52, and a wiring 62 of the third wiring layer 60 are connected in that order. In other words, the electrical path connected to the gate electrode of transistor T2 is first routed within the second wiring layer 40 located on the first semiconductor layer 20 side, then via the second conductor 52, and finally connected to the wiring 62 of the third wiring layer 60 located on the third semiconductor layer 80 side. In this way, the electrical path is routed to travel back and forth within the second wiring layer 40.

[0136] Furthermore, since the electrical path was routed to travel back and forth within the second wiring layer 40, it was necessary to arrange the via connected to the gate electrode and the second conductor 52 horizontally. In such a layout, it was difficult to reduce the distance between the via connected to the gate electrode and the second conductor 52.

[0137] Furthermore, the stress exerted by the second conductor 52 on the second semiconductor layer 50 could potentially cause the characteristics of transistor T2 to fluctuate.

[0138] In contrast, the transistor T2 in the photodetector 1 according to the second embodiment of this technology uses a second conductor 52A that penetrates the second semiconductor layer 50 along the thickness direction as the gate electrode G, and an insulating film provided between the side surface of the second conductor 52A and the second semiconductor layer 50 as the gate insulating film. Since the gate electrode G penetrates the second semiconductor layer 50 along the thickness direction in this way, the end 52a of the gate electrode G is exposed to the third wiring layer 60 (fourth surface S4). Therefore, the electrical path can be directly connected to the gate electrode G on the third wiring layer 60 side without having to travel back and forth within the second wiring layer 40. This suppresses the length of the electrical path and suppresses the increase in parasitic capacitance.

[0139] Furthermore, in the photodetector 1 according to the second embodiment of this technology, the transistor T2 has the second conductor 52A itself as the gate electrode G, which saves space and suppresses the increase in pixel size.

[0140] Furthermore, in the photodetector 1 according to the second embodiment of this technology, the transistor T2 has the second conductor 52A itself as the gate electrode G, which suppresses fluctuations in the characteristics of the transistor T2.

[0141] Thus, the photodetector 1 according to the second embodiment of this technology can suppress deterioration of connectivity between the first semiconductor layer 20 and the third semiconductor layer 80 by modifying the structure of the transistor T2.

[0142] <<Variations of the second embodiment>> The following describes a modified version of the second embodiment.

[0143] <Example 1> In the photodetector 1 according to the second embodiment, the transistor T2 had a gate electrode G connected to a via 67 of the third wiring layer 60, that is, connected to an electrical path provided within the third wiring layer 60. However, this technology is not limited to this. In Modification 1 of the second embodiment, if it is desired to connect the gate electrode G to an electrical path provided within the second wiring layer 40, the gate electrode G may be connected to a via 44 of the second wiring layer 40. Similarly, in the second embodiment described above, the source S and drain D were connected to a via 44 of the second wiring layer 40, that is, connected to an electrical path provided within the second wiring layer 40. However, this technology is not limited to this. In Modification 1 of the second embodiment, if it is desired to connect at least one of the source S and drain D to an electrical path provided within the third wiring layer 60, at least one of the source S and drain D may be connected to a via 67 of the third wiring layer 60. More specifically, at least one of the diffusion regions constituting the source S and the diffusion region constituting the drain D may be connected only to the conductor of the third wiring layer 60, among the conductors of the second wiring layer 40 and the conductors of the third wiring layer 60. When connected to via 67, the diffusion regions constituting the source S and the diffusion region constituting the drain D are positioned in the thickness direction of the second semiconductor layer 50 so that the signal charge can move toward the third wiring layer 60. Below, variations of the electrical path to which the gate electrode G, source S, and drain D are connected will be described.

[0144] (Extreme Variation 1-1) As shown in Figure 14A, the gate electrode G and source S are connected to via 67 of the third wiring layer 60, and the drain D is connected to via 44 of the second wiring layer 40.

[0145] (Variations 1-2) As shown in Figure 14B, the gate electrode G and drain D are connected to via 67 of the third wiring layer 60, and the source S is connected to via 44 of the second wiring layer 40.

[0146] (Variations 1-3) As shown in Figure 14C, the gate electrode G, source S, and drain D are all connected to via 67 in the third wiring layer 60.

[0147] (Variations 1-4) As shown in Figure 14D, the source S is connected to via 67 of the third wiring layer 60, and the gate electrode G and drain D are connected to via 44 of the second wiring layer 40.

[0148] (Variations 1-5) As shown in Figure 14E, the drain D is connected to via 67 of the third wiring layer 60, and the gate electrode G and source S are connected to via 44 of the second wiring layer 40.

[0149] (Extreme Variations 1-6) As shown in Figure 14F, the drain D and source S are connected to via 67 of the third wiring layer 60, and the gate electrode G is connected to via 44 of the second wiring layer 40.

[0150] (Main effects of Modification 1 of the Second Embodiment) Even with the light detection device 1 according to this modified example 1 of the second embodiment, the same effects as the light detection device 1 according to the second embodiment described above can be obtained.

[0151] Furthermore, in the photodetector 1 according to the modified example 1 of this second embodiment, the gate electrode G, source S, and drain D can be connected to vias 67 of the third wiring layer 60 or vias 44 of the second wiring layer 40, respectively, thus improving the design flexibility.

[0152] <Modification 2> In Modification 2 of the Second Embodiment, the manufacturing method of the photodetector 1 differs from that of the Second Embodiment. Hereinafter, the manufacturing method of the photodetector 1 in Modification 2 of the Second Embodiment will be described, focusing on the differences in the manufacturing method, with reference to Figures 15A to 15C.

[0153] As shown in Figure 15A, a second conductor 52A and an insulating film 41m are formed on the second semiconductor layer 50w. Then, vias 44 of the second wiring layer 40 are formed on the third surface S3 of the second semiconductor layer 50w. The formation of the second wiring layer 40 is temporarily stopped at the state shown in Figure 15A. More specifically, the formation of the second wiring layer 40 is temporarily stopped before a layer made of a metal such as copper or aluminum is formed on the second wiring layer 40.

[0154] Subsequently, as shown in Figure 15B, a support substrate 94 on which an insulating film 93 is formed is bonded to the third surface S3 side of the second semiconductor layer 50w on which the vias 44 are formed. In this way, a temporary support substrate 94 is bonded to the third surface S3 side of the second semiconductor layer 50w before the first wiring layer 30, which includes a layer made of metal such as copper or aluminum, is bonded. The wafer shown in Figure 15B does not include a layer made of metal such as copper or aluminum.

[0155] Next, the steps shown in Figures 13B to 13D, as described in the second embodiment, are performed. Then, as shown in Figure 15C, vias 67 are formed on the fourth surface S4 side of the second semiconductor layer 50. Here, heat treatment is performed in the step of forming the vias 67. At the time of this heat treatment, the wafer does not contain any layers made of metal, such as copper or aluminum. Therefore, the heat treatment temperature can be increased compared to when the wafer contains layers made of metal. After that, the third wiring layer 60 is completed.

[0156] Next, the second semiconductor layer 50, on which the third wiring layer 60 is laminated, and the third semiconductor layer 80, on which the fourth wiring layer 70 is laminated, which has been prepared separately, are joined using the B2F method. Then, the insulating film 93 and the support substrate 94 are removed. Finally, the third wiring layer 60 is completed, and the second semiconductor layer 50 and the first semiconductor layer 20 are joined using the F2F (Face to Face) method. The subsequent steps are the same as those described in the second embodiment above, so their explanation is omitted here.

[0157] Even with the light detection device 1 according to this modified example 2 of the second embodiment, the same effects as the light detection device 1 according to the second embodiment described above can be obtained.

[0158] Furthermore, in the photodetector 1 according to the modified example 2 of this second embodiment, the temperature of the heat treatment when forming the vias 67 can be increased, thereby suppressing an increase in the resistance value of the vias 67.

[0159] <Variation 3> Modification 3 of this second embodiment differs from the photodetector 1 of the second embodiment in that the wiring and connection pads of the first wiring layer 30 and the second wiring layer 40 are formed of polysilicon. Furthermore, the manufacturing method of the photodetector 1 in Modification 3 of this second embodiment differs from that of the second embodiment. Hereinafter, the manufacturing method of the photodetector 1 in Modification 3 of the second embodiment will be described with reference to Figures 16A and 16B, focusing on the parts where the manufacturing method differs.

[0160] Figure 16A shows the state before the second semiconductor layer 50 and the first semiconductor layer 20 are joined and the ends of the second conductor 52A and insulating film 41m are exposed. The wiring 32, first connection pad 33, wiring 42, and second connection pad 43 shown in Figure 16A are all made of polysilicon and not metals such as copper or aluminum.

[0161] Next, the steps shown in Figures 13B to 13D, as described in the second embodiment, are performed. Then, as shown in Figure 16B, vias 67 are formed on the fourth surface S4 side of the second semiconductor layer 50. At the time of heat treatment of the vias 67, the wafer does not contain any layers made of metal, such as copper or aluminum. Therefore, the heat treatment temperature can be increased compared to when the wafer contains layers made of metal. After that, the third wiring layer 60 is completed. The subsequent steps are the same as those described in the second embodiment above, so their explanation is omitted here.

[0162] Even with the photodetector 1 according to this modified example 3 of the second embodiment, the same effects as the photodetector 1 according to the second embodiment described above can be obtained.

[0163] Furthermore, in the photodetector 1 according to the modified example 3 of this second embodiment, the temperature of the heat treatment when forming the vias 67 can be increased, thereby suppressing an increase in the resistance value of the vias 67.

[0164] <Modification 4> The transistor T2 in the photodetector 1 according to the second embodiment was a planar transistor, but this technology is not limited to this. In modification 4 of the second embodiment, the transistor T2 is a FINFET type transistor, as shown in Figure 17. More specifically, the transistor T2 is an SOI-FINFET type transistor formed using an SOI wafer.

[0165] <Second conductor> The second conductor 52A shown in Figure 17 functions as the gate electrode G of transistor T2 (first transistor). The second conductor 52A shown in Figure 17 has multiple vertical portions that penetrate the second semiconductor layer 50 along the Z direction. Furthermore, the second conductor 52A has horizontal portions that connect the vertical portions. In the example shown in Figure 17, the second conductor 52A connects the ends of two vertical portions on the third surface S3 side. In addition, the insulating film 41m provided between the second conductor 52A and the second semiconductor layer 50 functions as a gate insulating film. The source S and drain D of transistor T2 are provided along the direction perpendicular to the plane of the paper in Figure 17. The channel of transistor T2 is formed in the portion of the second semiconductor layer 50 located between the vertical portions of the second conductor 52A, as shown in Figures 18A to 18C. That is, the channel is formed between the opposing sides of the vertical portions of the second conductor 52A. A modified example of transistor T2 will be described below.

[0166] (Variation 4-1) In the modified example 4-1 shown in Figures 18A to 18C, the gate electrode G and source S are connected to via 67 of the third wiring layer 60, and the drain D is connected to via 44 of the second wiring layer 40.

[0167] (Modification 4-2) In Modification 4-1, the second semiconductor layer 50 was provided so as to surround the vertical portion of the gate electrode G, but this technology is not limited to this. In Modification 4-2, as shown in Figures 19A to 19C, the second semiconductor layer 50 does not need to be present on the side of the vertical portion of the gate electrode G opposite to the side where the channel is formed.

[0168] Furthermore, in the transistor T2 of Modification 4-1, the vertical portion of the gate electrode G reached the fourth surface S4 of the second semiconductor layer 50, but this technology is not limited to this. As shown in Figures 19A and 19B, the vertical portion does not need to reach the fourth surface S4 of the second semiconductor layer 50. In that case, as shown in Figure 19B, the via 67 of the third wiring layer 60 is extended until it reaches the vertical portion. This allows the via 67 to be connected to the vertical portion.

[0169] (Modification 4-3) In the transistor T2 of Modification 4-2, the vertical portion did not reach the fourth surface S4 of the second semiconductor layer 50, but this technology is not limited to this. In Modification 4-3, as shown in Figure 20, the vertical portion may reach the fourth surface S4 of the second semiconductor layer 50.

[0170] (Modification 4-4) In the transistor T2 shown in Modifications 4-1 to 4-3, the gate electrode G and source S are connected to via 67 of the third wiring layer 60, and the drain D is connected to via 44 of the second wiring layer 40, but it is not limited to this. In Modification 4-4, the gate electrode G, source S, and drain D only need to be connected to either via 44 or via 67, respectively. The relationship between the gate electrode G, source S, drain D and the vias may be in the configuration shown in Figure 12B and any of Figures 14A to 14F.

[0171] (Main effects of Modification 4 of the Second Embodiment) Even with the photodetector 1 according to this modified example 4 of the second embodiment, the same effects as the photodetector 1 according to the second embodiment described above can be obtained.

[0172] <Modification 5> As shown in Figure 21, in Modification 5 of the second embodiment, transistor T2 is a GAA (Gate All Around) FET type transistor. More specifically, transistor T2 is an SOI-GAAFET type transistor formed using an SOI wafer.

[0173] <Second conductor> The second conductor 52A functions as the gate electrode G of transistor T2 (first transistor). In the example shown in Figure 21, the second conductor 52A has a horizontal portion that connects the ends of the vertical portion on the third surface S3 side and a horizontal portion that connects the ends of the vertical portion on the fourth surface S4 side. Aside from this point, it is similar in many respects to transistor T2 in the modified example 4 of the second embodiment, so a detailed explanation will be omitted. A modified example of transistor T2 will be described below.

[0174] (Variation 5-1) In the modified example 5-1 shown in Figures 22A to 22D, the multiple channels of transistor T2 are arranged along the horizontal direction (the direction perpendicular to the Z direction).

[0175] (Variation 5-2) In the modified example 5-2 shown in Figures 23A and 23B, multiple channels of transistor T2 are arranged along the Z direction. Note that the AA and BB cross-sectional views in Figure 23A are the same as those in Figures 22B and 22D.

[0176] (Modification 5-3) In the modified example 5-3 shown in Figures 24A and 24B, the multiple channels of transistor T2 are arranged along the thickness direction, similar to modified example 5-2, and the second semiconductor layer 50 is provided at a position closer to the third wiring layer 60 than the gate electrode G. The cross-sectional views AA and CC in Figure 24A are the same as those in Figures 22B and 23B.

[0177] (Modification 5-4) In the modified example 5-4 shown in Figure 25, the gate electrode G of transistor T2, and the source S and drain D have different dimensions in the thickness direction compared to the modified example 5-2. Note that the cross-sectional views AA, BB, and CC in Figure 25 are the same as those in Figures 22B, 22D, and 23B.

[0178] (Variation 5-5) In the modified example 5-5 shown in Figure 26, the gate electrode G of transistor T2, and the source S and drain D have different dimensions in the thickness direction compared to the modified example 5-1. Note that the cross-sectional views AA, BB, and CC in Figure 26 are the same as those in Figures 22B, 22D, and 22C.

[0179] (Variations 5-6) In the transistor T2 shown in Modifications 5-1 to 5-5, the gate electrode G and source S are connected to via 67 of the third wiring layer 60, and the drain D is connected to via 44 of the second wiring layer 40, but it is not limited to this. In Modification 5-6, the gate electrode G, source S, and drain D only need to be connected to either via 44 or via 67. The relationship between the gate electrode G, source S, drain D and the via may be in the configuration shown in Figure 12B and any of Figures 14A to 14F.

[0180] (Main effects of modified example 5 of the second embodiment) Even with the photodetector 1 according to this modified example 5 of the second embodiment, the same effects as the photodetector 1 according to the second embodiment described above can be obtained.

[0181] <Variation 6> In the second embodiment, the second semiconductor layer 50 and the third semiconductor layer 80 were joined by the B2F method, but this technology is not limited to this. As shown in Figure 27, the second semiconductor layer 50 and the third semiconductor layer 80 may be joined by the F2F method, and although not shown, the first semiconductor layer 20 and the second semiconductor layer 50 may be joined by the F2B method. In this case, the third wiring layer 60 corresponds to the second wiring layer, and the second wiring layer 40 corresponds to the third wiring layer.

[0182] Even with the photodetector 1 according to this modified example 6 of the second embodiment, the same effects as the photodetector 1 according to the second embodiment described above can be obtained.

[0183] Furthermore, conventionally, when the second semiconductor layer 50 and the third semiconductor layer 80 are joined by the F2F method, and the first semiconductor layer 20 and the second semiconductor layer 50 are joined by the F2B method, it was difficult to establish conductivity between the photodiode and the transistor T2. In contrast, in the photodetector 1 according to modification 6 of the second embodiment of this technology, since the gate electrode G penetrates the second semiconductor layer 50 along the thickness direction, wiring can be routed directly from the back side (fourth surface S4) of the transistor T2 to the photoelectric conversion element PD configured in the photoelectric conversion region 20a, thereby suppressing an increase in parasitic capacitance.

[0184] <Example 7> As shown in Figure 28A, the transfer gate TG of the transfer transistor TR and the charge storage region FD are arranged on the first semiconductor layer 20 in which the photoelectric conversion element PD is formed. In the first semiconductor layer 20, one charge storage region FD is shared by multiple pixels 3, for example, four pixels 3. Then, as shown in Figure 28B, the amplification transistor AMP, the selection transistors SEL0 and SEL1, and the reset transistor RST are arranged on the second semiconductor layer 50. The gate electrode G of the amplification transistor AMP is electrically connected to the charge storage region FD and the source region of the reset transistor RST.

[0185] Now, consider the case where the gate electrode G of the amplification transistor AMP is the second conductor 52A. Since the second conductor 52A penetrates the second semiconductor layer 50, it can be connected to the electrical path on the third surface S3 side and the electrical path on the fourth surface S4 side. Therefore, one end of the gate electrode G on the third surface S3 side and the other end on the fourth surface S4 side can be connected to the charge storage region FD, and the other end can be connected to the source region of the reset transistor RST.

[0186] For example, consider the case where the first semiconductor layer 20 and the second semiconductor layer 50 are joined by the F2B method, as explained in the modified example 6 above (Figure 27). By connecting the end of the gate electrode G of the amplification transistor AMP on the fourth face S4 side to the charge storage region FD, and connecting the end on the third face S3 side to the source region of the reset transistor RST, it is possible to suppress the length of the wiring from the gate electrode G to the charge storage region FD and from the gate electrode G to the source region of the reset transistor RST.

[0187] Even with the photodetector 1 according to this modified example 7 of the second embodiment, the same effects as the photodetector 1 according to the second embodiment described above can be obtained.

[0188] [Third Embodiment] A third embodiment of the present technology, shown in Figures 29, 30A, and 30B, will be described below. The difference between the photodetector 1 of this third embodiment and the photodetector 1 of the first embodiment described above is that it has a third connection pad 63A instead of the third connection pad 63. The rest of the configuration of the photodetector 1 is basically the same as that of the photodetector 1 of the first embodiment described above. Components that have already been described will be denoted by the same reference numerals and their descriptions will be omitted.

[0189] <<Configuration of the light detection device>> The configuration of the photodetector 1 according to the third embodiment of this technology will be described below, focusing on the differences from the configuration of the photodetector 1 according to the first embodiment described above. In the drawings illustrating this third embodiment, the same components may be depicted with different scales between drawings. Also, the barrier metal layer is omitted from the drawings illustrating this third embodiment. Furthermore, Figures 30A and 30B are schematic diagrams showing the third connection pad 63A shown in Figure 29.

[0190] <3rd wiring layer> As shown in Figure 29, the third wiring layer 60 has an insulating film 61 and a third connecting pad 63 provided on the insulating film 61, one of which is the bottom surface and the other is the joining surface. The end of the second conductor 52 on the fourth surface S4 side extends to the third connecting pad 63 and is connected to the third connecting pad 63. As shown in Figure 30A, the insulating film 61 includes insulating film 61a and insulating film 61b. When insulating film 61a and insulating film 61b are not distinguished, they are referred to as insulating film 61. The joining surface of the third connecting pad 63A is connected to the surface of the fourth connecting pad 73 on the third wiring layer 60 side of the fourth wiring layer 70.

[0191] <Third connection pad> As shown in Figure 30A, the third connection pad 63A is provided on the end of the second conductor 52 on the fourth surface S4 side, i.e., end 52a. The bottom surface of the third connection pad 63A is the surface on the second semiconductor layer 50 side. The bonding surface of the third connection pad 63A is the surface opposite to the bottom surface, more specifically the surface on the fourth wiring layer 70 side. The side surface of the third connection pad 63A is the surface that connects the bottom surface and the bonding surface. The third connection pad 63A is provided conformally around the second conductor 52. In other words, the third connection pad 63A is provided within an equidistant range from the second conductor 52. Also, the end 52a of the second conductor 52 on the fourth surface S4 side faces the bonding surface of the third connection pad 63A. The third connection pad 63A is made of, for example, copper, although this is not limited to it. The second conductor 52 is made of, for example, tungsten, although this is not limited to it.

[0192] Furthermore, the third connecting pad 63A is in contact with the insulating film 61a and the insulating film 61b. More specifically, the bottom surface of the third connecting pad 63A is in contact with the insulating film 61a, and the side surface of the third connecting pad 63A is in contact with the insulating film 61b. The insulating film 61a is made of a material whose etching rate for a selected etchant (selected etching conditions) is higher than that of the material constituting the insulating film 61b. Examples of combinations of materials constituting the insulating film 61a and the materials constituting the insulating film 61b include the following. Insulating film 61a / Insulating film 61b Silicon oxide / silicon nitride, Silicon oxide / silicon oxynitride (SiON), Silicon oxide of first density / silicon oxide of second density (first density < second density), Silicon oxide / Low-K insulating film with a lower dielectric constant than silicon oxide, Low-K insulating film / silicon oxide

[0193] Similarly, the insulating film 41m is composed of a material whose etching rate for the selected etchant (selected etching conditions) is higher than that of the material constituting the insulating film 61b. The material constituting the insulating film 41m may be the same as the material constituting the insulating film 61a, or it may be a different material, as long as its etching rate for the selected etchant (selected etching conditions) is higher than that of the material constituting the insulating film 61b.

[0194] ≪Manufacturing Method for Light Detection Devices≫ The manufacturing method of the light detection device 1 will be described below with reference to Figures 31A to 31E. Note that only the part related to the manufacturing method of the third connection pad 63A will be described here.

[0195] First, as shown in Figure 31A, the ends of the second conductor 52 and the insulating film 41m are exposed from the fourth surface S4 side of the second semiconductor layer 50. Then, as shown in Figure 31B, insulating films 61a and 61b are laminated in that order on the fourth surface S4 side so as to cover the exposed ends of the second conductor 52 and insulating film 41m. Note that insulating film 61a is evenly laminated on the surface of the exposed end of the second conductor 52 via insulating film 41m. After that, as shown in Figure 31C, the surface of the wafer on which insulating films 61a and insulating film 61b are laminated is ground and flattened using the CMP method. The flattened exposed surface faces insulating film 61a, insulating film 61b, the material constituting the second conductor 52, and insulating film 41m.

[0196] Next, the planarized exposed surface is etched using the selected etchant. As a result, as shown in Figure 31D, the insulating film 61a and insulating film 41m are selectively etched from among the insulating film 61a, insulating film 61b, second conductor 52, and insulating film 41m. More specifically, the materials constituting insulating film 61a and insulating film 41m have a higher etching rate to the selected etchant than the materials constituting insulating film 61b and second conductor 52, so they are selectively etched. The insulating film 61b is etched only slightly, if at all.

[0197] As a result, an annular hole 61h is formed in plan view, centered on the second conductor 52. More specifically, since the insulating film 61a is evenly laminated on the surface of the exposed end of the second conductor 52 via the insulating film 41m, removing such insulating film 61a results in a depression in an area equidistant from the second conductor 52, forming an annular hole 61h. Thus, in the third embodiment, an annular hole 61h can be formed on the second conductor 52 by self-alignment without the use of lithography techniques. Furthermore, etching stops before the bottom of the hole 61h reaches the second semiconductor layer 50. This prevents the metal to be embedded later from coming into contact with the second semiconductor layer 50.

[0198] Then, a barrier metal layer (not shown) is laminated into the hole 61h, and subsequently, as shown in Figure 31E, a metal film constituting the third connecting pad 63A is deposited by a plating method to fill the hole 61h formed by self-alignment, and then the excess portion of the deposited metal film is removed using the CMP method. This forms the third connecting pad 63A by self-alignment.

[0199] <<Main effects of the third embodiment>> The main effects of the third embodiment will be described below, but before that, a conventional photodetector and connection pad will be explained.

[0200] Generally, in order to manufacture a photodetector that connects three or more semiconductor layers, it is necessary to perform multiple hybrid bonding operations on each semiconductor layer. For example, when hybrid bonding a first semiconductor layer 20, a second semiconductor layer 50, and a third semiconductor layer 80, first the first semiconductor layer 20 and the second semiconductor layer 50 are hybrid bonded, and then the third semiconductor layer 80 is hybrid bonded to the hybrid bonded first semiconductor layer 20 and second semiconductor layer 50.

[0201] During hybrid bonding, wafers are stacked and compressed. This can sometimes cause localized distortion in the wafers. This localized distortion can cause some of the vias, such as the second conductor 52, to shift horizontally. When a portion of a via shifts, the overlapping accuracy between the shifted via and the connection pad formed in the next process can deteriorate. The holes into which the connection pad is embedded are generally formed using lithography and etching techniques. However, if the via itself shifts, even if the alignment in the lithography process is performed correctly, it can be difficult to track the shifted via. This can lead to a deterioration in the overlapping accuracy between some of the vias and the connection pad. In some cases, the dimensions of the connection pad must be set larger to account for the margin of overlapping accuracy between the via and the connection pad.

[0202] Furthermore, as mentioned above, if the dimensions of the connection pads were set considering the overlapping accuracy between the vias and connection pads, there was a possibility that when the next wafer was hybrid bonded, the larger connection pads might come into contact with connection pads on the next wafer that should not be in contact. In addition, the miniaturization of pixel dimensions reduced the tolerance for overlapping accuracy between vias and connection pads.

[0203] In contrast, in the photodetector 1 according to the third embodiment of this technology, insulating film 61a and insulating film 61b are stacked in that order around the end of the second conductor 52 exposed from the semiconductor layer, and by utilizing the etching rates of the material constituting insulating film 61a and the material constituting insulating film 61b with respect to a selected etchant, an annular hole 61h is formed in plan view with the second conductor 52 at its center, and the material constituting the third connection pad 63A is embedded in the hole 61h to form the third connection pad 63A. Thus, the third connection pad 63A can be formed without using lithography technology.

[0204] Furthermore, since the hole 61h is formed self-aligned with the second conductor 52 as its center, even if the second conductor 52 is misaligned due to localized strain in the wafer, an annular hole 61h can be formed with the misaligned second conductor 52 as its center, thereby suppressing deterioration of the overlapping accuracy between the second conductor 52 and the third connection pad 63A within the wafer surface. In this way, even if the second conductor 52 is misaligned, the third connection pad 63A can be formed by following that misalignment.

[0205] Furthermore, in the photodetector 1 according to the third embodiment of this technology, the third connection pad 63A can be formed self-aligned within an equidistant range from the second conductor 52, thus reducing the need to design the third connection pad 63A to be large in order to ensure superposition of the two. And because the size of the third connection pad 63A can be suppressed, when hybrid bonding is performed between the second semiconductor layer 50 and the third semiconductor layer 80, it is possible to suppress the third connection pad 63A from contacting a connection pad among the fourth connection pads 73 that it should not be contacting.

[0206] Although the side surface of the third connecting pad 63A shown in Figure 29 has a forward taper shape, it may also have a reverse taper shape.

[0207] <<Variation of the third embodiment>> The following describes a modified version of the third embodiment.

[0208] <Example 1> In the photodetector 1 according to the third embodiment, the end portion 52a of the second conductor 52 faced the bonding surface, which is the surface of the third connection pad 63A on the fourth wiring layer 70 side. However, this technology is not limited to this. In the first modification of the third embodiment, as shown in Figures 32A and 32B, the end portion 52a of the second conductor 52 is located inside the third connection pad 63A and does not face the bonding surface.

[0209] The manufacturing method of the photodetector 1 according to Modification 1 of the Third Embodiment will be described below with reference to Figures 33A and 33B. Only the parts that differ from the process described in the Third Embodiment will be described here.

[0210] First, as shown in Figure 31C of the third embodiment, the exposed surface of the wafer is flattened using the CMP method, and then, as shown in Figure 33A, only the second conductor 52 is etched back. More specifically, the exposed portion of the second conductor 52 is etched, and the end portion 52a of the second conductor 52 is recessed from the flattened surface.

[0211] Subsequently, a process similar to that shown in Figure 31D is performed to form the hole 61h. Then, a barrier metal layer (not shown) is laminated into the hole 61h, and as shown in Figure 33B, a metal film constituting the third connecting pad 63A is deposited by a plating method to fill the hole 61h formed by self-alignment, and then the excess portion of the deposited metal film is removed using the CMP method. In this way, the third connecting pad 63A is formed by self-alignment.

[0212] Even with the light detection device 1 according to this modified example 1 of the third embodiment, the same effects as the light detection device 1 according to the third embodiment described above can be obtained.

[0213] <Modification 2> In the third embodiment, the photodetector 1 was manufactured using the WoW (Wafer on Wafer) method, but this technology is not limited to this. For example, a semiconductor device 1A such as the photodetector 1 may be manufactured using the CoW (Chip on Wafer) method or the CoC (Chip on Chip) method. Modification 2 of the third embodiment describes a semiconductor device 1A manufactured using the CoW (Chip on Wafer) method.

[0214] (Semiconductor device) The semiconductor device 1A is a high-bandwidth memory (HBM). The semiconductor device 1A has a stacked structure in which multiple layers of chips are stacked. For example, as shown in Figure 34, the semiconductor device 1A has a stacked structure in which five layers of chips, from chip C1 to chip C5, are stacked. Each chip from chip C2 to chip C5 has a cell area DR, which is the area in which the memory cells of the DRAM (Dynamic Random Access Memory) are formed, and word lines and bit lines (not shown). Chip C1 also has a logic area LG, which is the area in which the drive logic circuits that drive the memory cells of each chip from chip C2 to chip C5 are formed.

[0215] Each chip from chip C1 to chip C5 comprises a semiconductor layer, an insulating film 61a, and an insulating film 61b. Chips C1 and C5 also have a second conductor 52 and a connection pad Pad provided at one end of the second conductor 52. Each chip from chip C2 to chip C4 also has a second conductor 52 and connection pad Pads provided at both ends of the second conductor 52. These connection pad Pads have the same configuration as the third connection pad 63A described above and are formed in the same manner as the third connection pad 63A. The connection pad Pads of the stacked chips are connected to each other, thereby connecting the second conductors 52 of chips C1 to C5 in a line along the stacking direction of the chips.

[0216] The second conductor 52, connected in a row, connects the word lines of each chip to each other, or the bit lines of each chip to each other. Furthermore, the second conductor 52, connected in a row, is connected to a drive logic circuit provided in the logic area LG of chip C1. The drive logic circuit drives the memory cells of each chip from chip C2 to chip C5 via the second conductor 52, connected in a row.

[0217] Even with the semiconductor device 1A according to this modified example 2 of the third embodiment, the same effects as the photodetector 1 according to the third embodiment described above can be obtained.

[0218] Furthermore, when manufacturing semiconductor device 1A using lithography technology, the manufacturing process is complicated because it is necessary to repeatedly perform tasks such as bonding chips together, forming resist patterns by lithography, etching, and forming connection pads. However, in this modified example 2 of the third embodiment, connection pads can be formed without using lithography technology, thus reducing the number of steps and preventing the manufacturing process from becoming complicated.

[0219] [Fourth Embodiment] A fourth embodiment of the present technology, shown in Figure 35, will be described below. The difference between the photodetector 1 of this fourth embodiment and the photodetector 1 of the first embodiment described above is that the end 51b of the first conductor 51 is connected to the wiring 42A. The rest of the configuration of the photodetector 1 is basically the same as that of the photodetector 1 of the first embodiment described above. Components that have already been described will be denoted by the same reference numerals and their descriptions will be omitted.

[0220] <<Configuration of the light detection device>> The configuration of the photodetector 1 according to the fourth embodiment of this technology will be described below, focusing on the differences from the configuration of the photodetector 1 according to the first embodiment described above. Note that in the drawings illustrating this fourth embodiment, the same components may be depicted with different scales from one drawing to the next. Also, the barrier metal layer is omitted from the drawings illustrating this fourth embodiment.

[0221] <Second wiring layer> The wiring 42 of the second wiring layer 40 is provided in the insulating film 41. Of the wiring 42 of the second wiring layer 40, the wiring 42 to which the end 51b, which is the end of the first conductor 51 on the third surface S3 side, is connected is sometimes called wiring 42A to distinguish it from the other wiring 42. Wiring 42A is a pad to which the first conductor 51 is connected, and corresponds to one wiring. The first conductor 51 penetrates the second semiconductor layer 50, and the end 51b, which is the end of the first conductor 51 on the third surface S3 side, extends to the wiring 42A of the second wiring layer 40 and is connected to wiring 42A. The end 51a, which is the end of the first conductor 51 on the fourth surface S4 side, extends to the fourth connection pad 73 of the fourth wiring layer 70 and is connected to the fourth connection pad 73, although this is not limited to the end 51a.

[0222] The wiring 42A has a laminated structure consisting of a first layer 42A1 made of a first conductive material and a second layer 42A2 made of a second conductive material that does not contain the first conductive material and is located between the first layer 42A1 and the end 51b of the first conductor 51 on the third surface S3 side. More specifically, the end 51b is connected to the second layer 42A2, and the second layer 42A2 is connected to the first layer 42A1. In other words, the end 51b and the first layer 42A1 are not directly connected, but are connected via the second layer 42A2. The first conductive material constituting the first layer 42A1 is, but is not limited to, a material containing copper. In this embodiment, an example in which the first layer 42A1 is made of copper will be described. The second conductive material constituting the second layer 42A2 is a material that does not contain the first conductive material, more specifically a material that does not contain copper. As the second conductive material constituting the second layer 42A2, a material is used that is unlikely to affect the operation of the transistor even if it is diffused into the semiconductor layer. It is preferable to use a material that has been conventionally used near the semiconductor layer as such a second conductive material. Examples of the second conductive material constituting the second layer 42A2 include tungsten, ruthenium, titanium, tantalum, tantalum nitride, aluminum, cobalt, and silicon. In this embodiment, an example in which the second layer 42A2 is made of tungsten will be described.

[0223] The second conductor 52, although not limited to this, has, for example, one end on the third surface S3 side connected to the wiring 42 and one end on the fourth surface S4 side connected to the third connection pad 63.

[0224] ≪Manufacturing Method for Light Detection Devices≫ The manufacturing method of the photodetector 1 will be described below with reference to Figures 36A to 36F. Here, only the parts related to the manufacturing method of the first conductor 51 and the wiring 42A will be described. In addition, in the following drawings, the first conductor 51 and the second conductor 52 are shown side by side in order to clearly explain the manufacturing method of the first conductor 51 and the wiring 42A. Note that in this fourth embodiment, in the drawings from Figure 36A onward, the illustration of the insulating film provided between the first conductor 51 and the second semiconductor layer 50 and the insulating film provided between the second conductor 52 and the second semiconductor layer 50, as well as their formation methods, may be omitted.

[0225] First, as shown in Figure 36A, an element such as a transistor T2 is formed on the third surface S3 side of the second semiconductor layer 50w, and an insulating film 41 is deposited on the third surface S3 side. Then, holes 44h, 53, and 42h2 are formed from the exposed surface of the insulating film 41 using known lithography and etching techniques. Hole 44h is, but is not limited to, a hole for forming a via 44 connected to the gate electrode G of transistor T2. Hole 53 is a hole for forming a second conductor 52. Hole 42h2 is a hole for forming the second layer 42A2 of wiring 42A. The depths of holes 44h, 53, and 42h2 in the thickness direction of the second semiconductor layer 50 are all different, with hole 53 being the deepest, followed by hole 44h, and then hole 42h2 being the shallowest.

[0226] Next, as shown in Figure 36B, a tungsten film is laminated onto the exposed surface of the insulating film 41 so as to fill the interiors of holes 44h, 53, and 42h2, and then the excess portion of the tungsten film is removed by CMP. This yields tungsten vias 44, a second conductor 52, and a second layer 42A2. The thickness of the second layer 42A2 thus formed is such that it is thick enough not to be penetrated by etching when holes 51h are formed by dry etching, while also being as low-resistance as possible. Furthermore, the relationship between the dimensions in the thickness direction of the vias 44, the second conductor 52, and the second semiconductor layer 42A2 of the second semiconductor layer 50 is the same as the relationship between the depths of holes 44h, 53, and 42h2.

[0227] Then, as shown in Figure 36C, an insulating film 41 is further laminated, and holes for forming wiring 42 are formed in the laminated insulating film 41 using known lithography and etching techniques. More specifically, holes 42h and 42h1 are formed. Hole 42h1 is a hole for forming the first layer 42A1, and hole 42h is a hole for forming wiring 42 other than wiring 42A.

[0228] Next, as shown in Figure 36D, copper is deposited on the exposed surface of the insulating film 41 by plating to fill the insides of holes 42h and 42h1, and then the excess copper is removed by CMP. This yields copper wiring 42 and the first layer 42A1. This also yields wiring 42A, which includes the first layer 42A1 and the second layer 42A2.

[0229] Subsequently, several steps already described in the first embodiment are performed. As these steps have been described in detail in the first embodiment, the illustrations and detailed descriptions are omitted, but the second wiring layer 40 is completed on the third surface S3 side, the second semiconductor layer 50w side and the first semiconductor layer 20 side are joined by the F2F method, the second semiconductor layer 50w is thinned by grinding from the side opposite to the third surface S3 to expose the second conductor 52, and an insulating film 61 is laminated on the fourth surface S4 of the second semiconductor layer 50.

[0230] Then, as shown in Figure 36E, holes 63h and 51h are formed from the insulating film 61 side using known lithography and etching techniques. Hole 63h is for forming a third connecting pad 63 that is connected to the second conductor 52. Hole 51h is for forming the first conductor 51. More specifically, hole 51h is for embedding the material (e.g., copper) that constitutes the first conductor 51. When forming hole 51h, first the insulating film 61 is etched, then the second semiconductor layer 50 is etched, and then the insulating film 41 is etched. The etching that forms hole 51h causes hole 51h to reach the second layer 42A2. Furthermore, it is preferable that the etching that forms hole 51h is carried out until holes 51h at different positions on the wafer surface reach the second layer 42A2. Also, depending on the position on the wafer surface, there may be differences in the progress of etching when forming hole 51h. Therefore, over-etching may be performed to suppress the occurrence of localized hole 51h opening defects within the wafer surface. For this reason, the thickness of the second layer 42A2 is set to such a size that the first layer 42A1 will not be exposed even if over-etching is performed.

[0231] Subsequently, as shown in Figure 36F, copper is deposited on the exposed surface of the insulating film 61 by plating to fill the insides of holes 63h and 51h, and then the excess copper is removed by CMP. This yields a copper third connecting pad 63 and a first conductor 51.

[0232] <<Main effects of the fourth embodiment>> The main effects of the fourth embodiment will be explained below, but before that, the prior art will be described. Conventionally, when forming the hole 51h, there was a possibility that the copper constituting the wiring 42 would be exposed. When etching plasma collided with the exposed copper, there was a possibility that the copper would scatter. In particular, in a photodetector in which pixel transistors are stacked and the semiconductor layer has a three-layer structure, the distance between the transistor T2 and the through electrode such as the first conductor 51 is small, so the scattered copper could enter the semiconductor layer and potentially affect the characteristics of the transistor T2.

[0233] Furthermore, when creating the holes 51h, etching is required that penetrates the second semiconductor layer 50, which has a thickness on the order of microns. When forming holes 51h that penetrate such a thick semiconductor layer, differences in etching progress occur between the central and edge portions of the wafer. Therefore, in order to suppress the occurrence of localized hole 51h opening defects within the wafer surface, it was necessary to continue etching until the holes 51h reached the wiring 42 in the areas where etching progressed relatively slowly within the wafer surface; in other words, over-etching was necessary.

[0234] However, when over-etching was performed, in areas of the wafer surface where etching progressed relatively quickly, the copper constituting the wiring 42 was exposed, and there was a possibility that the etching plasma would collide with the exposed copper, causing it to diffuse.

[0235] In general, a barrier metal is provided between the wiring 42 and the insulating film 41. However, compared to the second semiconductor layer 50, which has a thickness on the order of microns, the barrier metal is on the order of nanometers, and may not be thick enough to absorb the etching variations of the second semiconductor layer 50. Therefore, in areas where etching progresses relatively quickly on the wafer surface, the barrier metal may be etched and removed during over-etching, potentially exposing the copper that makes up the wiring 42. Then, the etching plasma may collide with the exposed copper, potentially causing it to diffuse.

[0236] In contrast, in the photodetector 1 according to the fourth embodiment of this technology, one wiring 42A includes a laminated structure of a first layer 42A1 made of copper and a second layer 42A2 made of a second conductive material that does not contain copper, located between the first layer 42A1 and one end 51b of the first conductor 51. Therefore, when the hole 51h reaches the wiring 42A, the second layer 42A2 made of the second conductive material that does not contain copper is exposed, and the scattering of copper can be suppressed.

[0237] Furthermore, in the photodetector 1 according to the fourth embodiment of this technology, even if over-etching occurs in a portion of the wafer surface where etching progresses relatively quickly, the etching plasma collides with the second layer 42A2 made of a second conductive material that does not contain copper, thus suppressing the scattering of copper. In this way, even if there is a difference in the progress of etching of the holes 51h depending on the position on the wafer surface, the scattering of copper can be suppressed.

[0238] Furthermore, in the photodetector 1 according to the fourth embodiment of this technology, the second conductive material constituting the second layer 42A2 is a material that is unlikely to affect the operation of the transistor even if it diffuses into a semiconductor layer such as the second semiconductor layer 50. Therefore, even if etching plasma collides with the second conductive material constituting the second layer 42A2 and the second conductive material constituting the second layer 42A2 diffuses into a semiconductor layer such as the second semiconductor layer 50, it is possible to suppress the effect on the operation of the transistor.

[0239] Furthermore, in the photodetector 1 according to the fourth embodiment of this technology, the second layer 42A2 is made of the same material as the materials constituting the vias 44 and the second conductor 52, more specifically, tungsten. Therefore, the second layer 42A2, the vias 44, and the second conductor 52 can be formed by performing tungsten film deposition and the subsequent CMP method just once each, thereby suppressing an increase in the manufacturing process.

[0240] Furthermore, in the photodetector 1 according to the fourth embodiment of this technology, in the process of forming the second layer 42A2 shown in Figure 36B, the thickness of the second layer 42A2 is formed to be as low as possible in resistance and to be the thickness remaining at the bottom of the hole 51h after the etching of the hole 51h is completed. This suppresses an increase in the resistance of the wiring 42A and prevents the first layer 42A1 from being exposed.

[0241] <<Variation of the fourth embodiment>> The following describes a modified version of the fourth embodiment.

[0242] <Example 1> In the photodetector 1 according to the fourth embodiment, the thickness dimension of the second semiconductor layer 50 of the second layer 42A2 was smaller than the thickness dimension of the second semiconductor layer 50 of the via 44, but this technology is not limited to this. In modification 1 of the fourth embodiment, as shown in Figure 37, the thickness dimension of the second semiconductor layer 50 of the second layer 42A2 is the same as the thickness dimension of the second semiconductor layer 50 of the via 44. In order to make the thickness dimensions of the via 44 and the second layer 42A2 the same, the holes 44h and 42h2 should be made to the same depth in the process shown in Figure 36A of the fourth embodiment. Note that the distance between the second layer 42A2 and the third surface S3 of the second semiconductor layer 50 is equal to the thickness of the gate electrode G.

[0243] Even with the photodetector 1 according to this modification 1 of the fourth embodiment, the same effects as the photodetector 1 according to the fourth embodiment described above can be obtained.

[0244] Furthermore, in the photodetector 1 according to the modification 1 of the fourth embodiment, in order to make the dimensions of the via 44 and the second layer 42A2 the same in the thickness direction, holes 44h and 42h are made to the same dimensions in the process shown in Figure 36A of the fourth embodiment. Therefore, holes 44h and 42h can be formed simultaneously in a single photolithography and etching process. This suppresses the increase in the number of processes.

[0245] Furthermore, in the photodetector 1 according to the modification 1 of the fourth embodiment, the thickness dimension of the second layer 42A2 is larger than that of the fourth embodiment. Therefore, the exposure of the first layer 42A1 when forming the hole 51h can be further suppressed.

[0246] <Modification 2> In the photodetector 1 according to the fourth embodiment, the width dimension (direction perpendicular to the Z direction) of the second layer 42A2 was set to the same width dimension as the first layer 42A1, but this technology is not limited to this. In the modified example 2 of the fourth embodiment, as shown in Figure 38, the width dimension of the second layer 42A2 may be smaller than the width dimension of the first layer 42A1, as long as it is equal to or greater than the width dimension (horizontal dimension) of the end 51b of the first conductor 51.

[0247] Even with the photodetector 1 according to this modified example 2 of the fourth embodiment, the same effects as the photodetector 1 according to the fourth embodiment described above can be obtained.

[0248] <Variation 3> In the photodetector 1 according to the 3rd modification of the 4th embodiment, as shown in Figure 39, the surface of the 2nd layer 42A2 on the side of the 1st conductor 51 is concave toward the 1st layer 42A1 side. This is because it was over-etched when forming the hole 51h for embedding the 1st conductor 51. In order to open the hole 51h at different positions on the wafer surface, a portion of the 2nd layer 42A2 is over-etched. Preferably, the 2nd layer 42A2 is of a thickness that does not penetrate even when over-etched.

[0249] Even with the photodetector 1 according to this modified example 3 of the fourth embodiment, the same effects as the photodetector 1 according to the fourth embodiment described above can be obtained.

[0250] <Modification 4> In the photodetector 1 according to the 4th modified embodiment, as shown in Figure 40, the surface of the second layer 42A2 on the first layer 42A1 side is provided to be recessed toward the end 51b side of the first conductor 51. This recess is formed, for example, by etching.

[0251] Even with the photodetector 1 according to this modified example 4 of the fourth embodiment, the same effects as the photodetector 1 according to the fourth embodiment described above can be obtained.

[0252] <Modification 5> In the photodetector 1 according to modification 5 of the fourth embodiment, as shown in Figure 41, an insulating film 45 is provided between the second layer 42A2 and the insulating film 41. The insulating film 45 is a different type of insulating film from the insulating film 41, for example, a silicon oxynitride film.

[0253] The insulating film 45 functions as an etching stop layer when forming holes 51h. More specifically, the insulating film 45 is made of a material whose etching rate for a selected etchant is lower than that of the material constituting the insulating film 41. The manufacturing method of the photodetector 1 according to Modification 5 of the fourth embodiment will now be described, with reference to Figures 42A to 42C, focusing on the differences from the manufacturing method described in the fourth embodiment.

[0254] As shown in Figure 42A, after holes 44h, 53, and 42h2 are formed, an insulating film 45, which functions as an etching stop layer, is laminated to cover the inner surfaces of holes 44h, 53, and 42h2. The insulating film 45 is laminated to have a thickness of, for example, about 50 nm, although this is not limited to this thickness. Then, the insulating film 45 at the bottom of the via 44 is removed, and then the same process as shown in Figures 36B to 36D is carried out.

[0255] Next, as shown in Figure 42B, holes 63h and 51h are formed. Here, the etching of hole 51h slows down when it reaches the insulating film 45, and even if the insulating film 45 is etched, only a small amount is etched. By slowing down the etching of hole 51h with the insulating film 45, it is possible to wait until the etching of the parts of the wafer surface where etching is lagging catches up, and the variation in the etching rate of holes 51h that occurred on the wafer surface can be reset. In other words, the progress of etching of holes 51h at different locations on the wafer surface is equalized by the insulating film 45.

[0256] Subsequently, as shown in Figure 42C, the etching conditions are changed to etch and remove the insulating film 45 located at the bottom of the hole 51h. Etching of the insulating film 45 is started simultaneously at holes 51h at different locations on the wafer surface. Furthermore, since the thickness of the insulating film 45 is thin, for example, about 50 nm, the etching time is short, and even if there is variation in the progress of etching on the wafer surface, it is only slight. This suppresses an increase in the amount of over-etching of the material constituting the second layer 42A2. The subsequent steps have already been described in the fourth embodiment, so they are omitted here.

[0257] Even with the photodetector 1 according to this modified example 5 of the fourth embodiment, the same effects as the photodetector 1 according to the fourth embodiment described above can be obtained.

[0258] Furthermore, in the photodetector 1 according to modification 5 of this fourth embodiment, since the insulating film 45 is provided as an etching stop layer, it is possible to reset the variation in the etching progress of holes 51h formed on the wafer surface. This makes it possible to suppress an increase in the amount of over-etching of the second layer 42A2 and to suppress an increase in the amount of material constituting the second layer 42A2 that is scattered.

[0259] [Fifth Embodiment] A fifth embodiment of the present technology, shown in Figure 43, will be described below. The difference between the photodetector 1 of this fifth embodiment and the photodetector 1 of the first embodiment described above is that it has a second conductor 52B instead of the second conductor 52. The other configurations of the photodetector 1 are basically the same as those of the photodetector 1 of the first embodiment described above. Components that have already been described will be denoted by the same reference numerals and their descriptions will be omitted.

[0260] <<Configuration of the light detection device>> The configuration of the photodetector 1 according to the fifth embodiment of this technology will be described below, focusing on the differences from the configuration of the photodetector 1 according to the first embodiment described above. In the drawings illustrating this fifth embodiment, the same components may be depicted with different scales in the drawings for the sake of clarity. Also, in the drawings illustrating this fifth embodiment, some barrier metal layers may be omitted from the illustration. Furthermore, in Figure 43, the differences in film thickness are emphasized.

[0261] As shown in Figure 43, the second conductor 52B penetrates the second semiconductor layer 50 along its thickness direction. Furthermore, the second conductor 52B is integrally formed from the same material as one of the wirings 62 of the third wiring layer 60. More specifically, the second conductor 52 and the one wiring 62 are formed simultaneously from the same material. Here, the one wiring 62 is sometimes referred to as wiring 62B to distinguish it from the other wirings 62. The second conductor 52B and wiring 62B are integrally formed in the same film deposition process. Therefore, the second conductor 52B and wiring 62B are continuously constructed from the same material, and there is no boundary between them. Moreover, there is no interface between dissimilar materials between the second conductor 52B and wiring 62B. The second conductor 52B and wiring 62B are composed of a third material. The third material is a conductive material with low resistance. Examples of the third material include tungsten, aluminum, copper, cobalt, and ruthenium. In this embodiment, the second conductor 52B and the wiring 62B are assumed to be made of copper.

[0262] Furthermore, the photodetector 1 has an insulating film 41m (separation insulating film) between the second conductor 52B and the second semiconductor layer 50. The insulating film 41m protrudes into the insulating film 61 of the third wiring layer 60. The thickness of the insulating film 41m on the third surface S3 side is greater than the thickness on the fourth surface S4 side.

[0263] Furthermore, the insulating film 41m is of higher quality than the insulating film 61 of the third wiring layer 60. More specifically, the insulating film 41m has a higher density and fewer impurities than the insulating film 61 of the third wiring layer 60. This is because, as will be explained later in the section on manufacturing methods, the temperature at which the insulating film 41m is deposited is higher than the temperature at which the insulating film 61 is deposited. Therefore, the insulating film 41m has a higher electrical withstand voltage than the insulating film 61.

[0264] The end 52b of the second conductor 52B on the third surface S3 side is connected to one of the wirings 42 of the second wiring layer 40. Here, the one wiring 42 is sometimes referred to as wiring 42B to distinguish it from the other wirings 42. The photodetector 1 also has a barrier metal layer provided to cover the metallic material. The barrier metal layer suppresses the diffusion of metals constituting the wiring, connection pads, and vias into the insulating film. In this embodiment, the barrier metal layer provided to cover the second conductor 52B and the wiring 62B is referred to as barrier metal layer 55 to distinguish it from other barrier metal layers. The barrier metal layer 55 is provided between the second conductor 52B and the insulating film 41m, between the second conductor 52B and the wiring 42B, and between the wiring 62B and the insulating film 61. The barrier metal layer 55 is composed of a film containing a high melting point metal (high melting point metal film). The barrier metal layer 55 is composed of, but is not limited to, titanium nitride (TiN), for example.

[0265] In the barrier metal layer 55, the portion provided between the second conductor 52B and the insulating film 41m has a thickness greater on the fourth surface S4 side than on the third surface S3 side. This is the opposite trend to that of the insulating film 41m.

[0266] ≪Manufacturing Method for Light Detection Devices≫ The manufacturing method of the photodetector 1 will be described below with reference to Figures 44A to 44G. Here, only the parts related to the manufacturing methods of the second conductor 52B and the wiring 62B will be described.

[0267] First, as shown in Figure 44A, an element such as a transistor T2 is formed on the third surface S3 side of the second semiconductor layer 50w, and the insulating film of the second wiring layer 40 is laminated. Then, from the third surface S3 side, a hole 53 is formed that extends into the interior of the second semiconductor layer 50w using known lithography and etching techniques. The hole 53 is provided to form the second conductor 52B.

[0268] Next, as shown in Figure 44B, the insulating film 41m and the film (sacrificial film) 56 are sequentially laminated in this order on the exposed surface, including the inner wall (inner circumferential surface and bottom surface) of the hole 53, starting from the third surface S3 side. The insulating film 41m is made of, for example, silicon oxide (SiO2). The insulating film 41m is deposited by, for example, a high-temperature, low-pressure CVD method. Since no metal wiring such as aluminum or copper has yet been formed on the third surface S3 side of the second semiconductor layer 50w shown in Figures 44A and 44B, the temperature at which the insulating film 41m is deposited is not restricted by metals such as aluminum or copper. Therefore, the temperature at which the insulating film 41m is deposited can be set higher than when metal wiring such as aluminum or copper is provided. This suppresses a decrease in the density of the insulating film 41m and an increase in impurities. Furthermore, it suppresses a decrease in the electrical breakdown voltage of the insulating film 41m. Furthermore, since Figure 44B schematically shows the insulating film 41m, the thickness of the insulating film 41m is depicted as uniform along the Z direction. However, in reality, the thickness of the insulating film 41m is thicker on the side where the film is deposited along the Z direction (the third surface S3 side) and thinner towards the bottom of the hole 53 (the fourth surface S4 side).

[0269] The film 56 is laminated as a temporary material to fill the holes 53 via the insulating film 41m. The film 56 is composed of a sacrificial material, which will be removed in a later step. More specifically, only the film 56 is removed from the insulating film 41m. Therefore, as the sacrificial material constituting the film 56, a material with a higher etching rate to the selected etchant is selected than the material constituting the insulating film 41m. In other words, the material constituting the insulating film 41m is a material with a lower etching rate to the selected etchant than the sacrificial material constituting the film 56. Examples of sacrificial materials include silicon, polysilicon, silicon nitride, and tungsten. In this embodiment, the film 56 is described as being made of polysilicon.

[0270] Next, as shown in Figure 44C, the second wiring layer 40 is completed, and the same process as shown in Figures 5F to 5H of the first embodiment is performed. More specifically, the second semiconductor layer 50 is thinned from the side opposite to the third surface S3, exposing the film 56 and insulating film 41m from the fourth surface S4. More specifically, the film 56 and insulating film 41m are made to protrude from the fourth surface S4. As a result, as shown in Figure 44D, the film 56 and insulating film 41m protruding from the fourth surface S4 are obtained. Subsequently, as shown in Figure 44E, the insulating film 61 and a film m that functions as a hard mask are deposited on the fourth surface S4 side. Then, using known lithography and etching techniques, an opening mh is formed in the film m. More specifically, the opening mh is provided in a region that overlaps with the film 56 embedded in the hole 53 in a plan view.

[0271] Since the second wiring layer 40, which has wiring 42 and the like, is already completed, the insulating film 61 is deposited at a temperature that the metal constituting the wiring, such as aluminum or copper, can withstand. Therefore, the insulating film 61 is deposited at a lower temperature than the temperature at which the insulating film 41m is deposited. The insulating film 61 is deposited by methods such as plasma CVD or spin-on-glass (SOG).

[0272] Then, as shown in Figure 44F, the film 56 is selectively removed from the insulating film 41m through the opening mh using a known etching technique. Specifically, the difference in etching rates between the sacrificial material (polysilicon) constituting the film 56 and the silicon oxide constituting the insulating film 41m at a selected etchant is used to remove only the film 56 from the insulating film 41m. As a result, the area occupied by the film 56 within the hole 53 becomes a cavity, and the insulating film 41m is exposed.

[0273] Next, as shown in Figure 44G, an opening 61j is formed in the insulating film 61 in the region that overlaps with the hole 53 in a plan view, for embedding the wiring 62B. Then, a barrier metal layer 55 is laminated on the exposed surfaces inside the hole 53 and the opening 61j. The barrier metal layer 55 is provided on the inner circumferential surface of the hole 53 via the insulating film 41m, and at the bottom of the hole 53, i.e., in the region where the hole 53 overlaps with the wiring 42B in a plan view. Also, since the insulating film 41m is laminated on the inner circumferential surface of the hole 53, the barrier metal layer 55 is deposited on the exposed surface of the insulating film 41m on the inner circumferential surface of the hole 53. Furthermore, since Figure 44G schematically shows the barrier metal layer 55, the thickness of the barrier metal layer 55 is depicted as uniform along the Z direction. However, in reality, the thickness of the barrier metal layer 55 is thicker on the side where the film is deposited along the Z direction (the fourth surface S4 side) and thinner on the wiring 42B side (the third surface S3 side). Thus, since the barrier metal layer 55 is laminated from the opposite side (the fourth surface S4 side) to the side on which the insulating film 41m is laminated (the third surface S3 side), the thickness trends of the barrier metal layer 55 and the insulating film 41m are reversed.

[0274] Subsequently, as shown in Figure 44G, a film 62m made of a conductive material (copper in this embodiment) is deposited on the exposed surface of the barrier metal layer 55 by a plating method. The film 62m is deposited so as to fill the holes 53 and the openings 61j. More specifically, the film 62m is deposited so as to fill the cavities in the holes 53 and the openings 61j. In this way, since films 62m of the same material are simultaneously filled into the holes 53 and the openings 61j in the same process, the second conductor 52B and the wiring 62B can be continuously constructed from the same material, and the formation of a boundary between them can be suppressed. More specifically, the formation of an interface between dissimilar materials can be suppressed. In other words, the second conductor 52B is formed simultaneously with the wiring 62B in the same process by utilizing the cavities in the holes 53. Subsequently, the excess portions of the barrier metal layer 55 and the film 62m are removed by the CMP method to obtain the second conductor 52B and the wiring 62B shown in Figure 43.

[0275] <<Main effects of the fifth embodiment>> The main effects of the fifth embodiment will be explained below, but before that, two conventional examples shown in Figures 45A and 45B will be described.

[0276] First, in the conventional second conductor 52 shown in Figure 45A, a hole 53 is formed from the third surface S3 side, an insulating film 41m and a barrier metal layer 55 are deposited on the inner surface of the hole 53 from the third surface S3 side, and the material constituting the second conductor 52 is embedded in the hole 53 from the third surface S3 side. Then, the wiring 62 is formed from the fourth surface S4 side. In the conventional second conductor 52 shown in Figure 45A, since the insulating film 41m is formed from the third surface S3 side before the metal wiring such as aluminum or copper is provided, it is possible to suppress a decrease in the electrical withstand voltage of the insulating film 41m. On the other hand, since the second conductor 52 is formed from, for example, tungsten from the third surface S3 side and the wiring 62 is formed from, for example, copper from the fourth surface S4 side, an interface between dissimilar materials is created between the second conductor 52 and the wiring 62. Therefore, the electrical resistance between the second conductor 52 and the wiring 62 was higher compared to the case where there was no interface between dissimilar materials. Also, the film thickness of both the conventional insulating film 41m and the barrier metal layer 55 was thicker on the side where the film was deposited along the Z direction (the third surface S3 side) and thinner towards the bottom of the hole 53 (the fourth surface S4 side). Furthermore, the barrier metal layer 55 was not provided between the second conductor 52 and the wiring 42.

[0277] Furthermore, in the conventional second conductor 52 shown in Figure 45B, a hole 53 is formed from the fourth surface S4 side, an insulating film 41m and a barrier metal layer 55 are deposited on the inner surface of the hole 53 from the fourth surface S4 side, and the materials constituting the second conductor 52 and wiring 62 are embedded in the hole 53 in a single step from the fourth surface S4 side. In the conventional example shown in Figure 45B, since the second conductor 52 and wiring 62 are formed simultaneously in the same step, there is no interface between dissimilar materials between the second conductor 52 and the wiring 62. Therefore, the electrical resistance between the second conductor 52 and the wiring 62 can be lower than that of the conventional second conductor 52 shown in Figure 45A. On the other hand, since metal wiring such as aluminum or copper is provided on the third surface S3 side of the second semiconductor layer 50 before forming the insulating film 41m, the temperature at which the insulating film 41m is deposited is limited by the metal such as aluminum or copper, and it was necessary to set it to a lower temperature than in the conventional example shown in Figure 45A. Therefore, the electrical breakdown voltage of the insulating film 41m was reduced compared to when the film was deposited at a high temperature. In addition, the film thickness of both the conventional insulating film 41m and the barrier metal layer 55 was thicker on the side where the film was deposited along the Z direction (the fourth surface S4 side) and thinner towards the bottom of the hole 53 (the third surface S3 side).

[0278] In contrast, in the photodetector 1 according to the fifth embodiment of this technology, before forming metal wiring such as aluminum or copper, a hole 53 for forming the second conductor 52B is formed from the third surface S3 side, and an insulating film 41m is laminated against the inner wall of the hole 53. Therefore, the insulating film 41m can be formed at high temperatures without being restricted by the metal wiring. As a result, a decrease in the electrical withstand voltage of the insulating film 41m can be suppressed.

[0279] Furthermore, in the photodetector 1 according to the fifth embodiment of this technology, the hole 53 is filled with a sacrificial material film 56 from the third surface S3 side. Then, from the fourth surface S4 side, the film 56 is selectively removed from the insulating film 41m, and the second conductor 52B and the wiring 62B are formed simultaneously in the same process using the cavity created by the removal of the film 56 from the fourth surface S4 side. As a result, the second conductor 52B and the wiring 62B can be continuously constructed from the same material, and the occurrence of an interface between dissimilar materials between them can be suppressed.

[0280] In the fifth embodiment described above, an opening mh was formed as shown in Figure 44E to selectively remove the film 56 from the insulating film 41m, but this technology is not limited to this. An opening 61j may be formed instead of the opening mh, and the film 56 may be selectively removed through the opening 61j.

[0281] <<Variations of the Fifth Embodiment>> The following describes a modified version of the fifth embodiment.

[0282] <Example 1> As shown in Figure 46, the photodetector 1 according to Modification 1 of the fifth embodiment includes a second conductor 52B made of a third material and a second conductor 52C made of a fourth material different from the third material. The fourth material constituting the second conductor 52C is a material that can be used as a through electrode, that is, a conductive material, from among the sacrificial materials described in the fifth embodiment. Examples of the fourth material include silicon and tungsten. In this modification, an example in which the second conductor 52C is made of silicon, more specifically polysilicon, will be described. Furthermore, regarding the second conductor 52B, an example in which the second conductor 52B is made of copper will be described, similar to the case of the fifth embodiment described above. The polysilicon second conductor 52C has a higher electrical resistance than the copper second conductor 52B.

[0283] The second conductor 52C is formed by embedding a film 56 made of the fourth material into the hole 53. Hereinafter, to distinguish between the hole 53 for the second conductor 52C and the hole 53 for the second conductor 52B, the hole for the second conductor 52C will be referred to as hole 53-1, and the hole for the second conductor 52B will be referred to as hole 53-2. Furthermore, the end 52b of the second conductor 52C on the third surface S3 side is connected to the wiring 42, and the end 52a on the fourth surface S4 side is connected to the wiring 62. The wiring 62 is made of the same material as the second conductor 52B, i.e., the third material.

[0284] The manufacturing method of the photodetector 1 will be described below with reference to Figures 47A and 47B. Here, only the parts related to the manufacturing methods of the first conductor 51B and the first conductor 51C will be described.

[0285] First, the steps shown up to Figure 44D of the fifth embodiment are performed, and then, as shown in Figure 47A, an insulating film 61 and a film m that functions as a hard mask are deposited on the fourth surface S4 side. Then, using known lithography and etching techniques, openings mh are formed in the film m. More specifically, the openings mh are provided in the region that overlaps with the film 56 embedded in hole 53-2 in a plan view. On the other hand, the openings mh are not provided in the region that overlaps with the film 56 embedded in hole 53-1 in a plan view. In this way, of the two holes 53-1 and 53-2, the openings mh are provided only in hole 53-2. As a result, in the next etching step, only the film 56 embedded in hole 53-2 is removed from the two films 56 embedded in hole 53-1. This selectively leaves the film 56 embedded in hole 53-1.

[0286] Then, as shown in Figure 47B, openings 61j are formed in both holes 53-1 and 53-2 for embedding wiring 62 and wiring 62B. Then, the steps from Figure 44G onward of the fifth embodiment are carried out.

[0287] Even with the photodetector 1 according to this modified example 1 of the fifth embodiment, the same effects as the photodetector 1 according to the fifth embodiment described above can be obtained.

[0288] Furthermore, in the photodetector 1 according to the modified example 1 of the fifth embodiment, both the second conductor 52B and the second conductor 52C, which has higher resistance than the second conductor 52B, are provided by selectively leaving the film 56 embedded in some of the holes 53 (hole 53-1) without removing it. This allows some of the second conductors to be used as high-resistance elements, thereby increasing the degree of freedom in circuit design.

[0289] More specifically, in Figure 46, via 44, wiring 42, and second conductor 52C are connected to the gate electrode G of transistor T2 in this order. By changing the resistance values ​​by changing the materials of at least some of these components, the voltage applied to the gate electrode G can be changed. In this modified example, since the material constituting the second conductor can be selectively changed, the voltage applied to the gate electrode G can be changed by selectively changing the resistance value of the second conductor. Therefore, the voltage applied to the gate electrode G can be changed not only by changing the resistance values ​​of via 44 and wiring 42, but also by changing the resistance value of the second conductor. This increases the degree of freedom in circuit design.

[0290] <Modification 2> As shown in Figures 48A and 48B, the photodetector 1 according to the modified example 2 of the fifth embodiment includes a guard ring 2C. As shown in Figure 48A, the guard ring 2C is provided in the peripheral region 2B of the semiconductor chip 2. More specifically, the guard ring 2C is provided in the peripheral region 2B at a position closer to the outer edge than the bonding pad 14. The guard ring 2C is also provided along the Z direction of the semiconductor chip 2. The guard ring 2C suppresses the semiconductor chip 2 from cracking from the outer edge when subjected to external impact. For example, when the semiconductor chip 2 is separated into individual pieces, the semiconductor chip 2 is subjected to mechanical load. The guard ring 2C suppresses the propagation of cracks that occur on the outer edge of the semiconductor chip 2 toward the bonding pad 14 and the pixel region 2A. The guard ring 2C also suppresses the entry of moisture toward the bonding pad 14 and the pixel region 2A.

[0291] Figure 48B shows the portion of the guard ring 2C provided around the second semiconductor layer 50. The guard ring 2C has a second conductor 52B that penetrates the second semiconductor layer 50 along the thickness direction. Although not shown in the figure, the guard ring 2C may have a similar structure for the first semiconductor layer 20 and the third semiconductor layer 80. More specifically, it may have a second conductor 52B that penetrates the first semiconductor layer 20 along the thickness direction and a second conductor 52B that penetrates the third semiconductor layer 80 along the thickness direction.

[0292] Even with the photodetector 1 according to this modified example 2 of the fifth embodiment, the same effects as the photodetector 1 according to the fifth embodiment described above can be obtained.

[0293] Furthermore, in the photodetector 1 according to the modified example 2 of this fifth embodiment, the portion of the guard ring 2C that penetrates a semiconductor layer such as the second semiconductor layer 50 is made of the second conductor 52B. Therefore, the portion of the guard ring 2C that penetrates the semiconductor layer can be formed simultaneously with the second conductor 52B provided in the pixel region 2A. As a result, an increase in the number of processes can be suppressed, and manufacturing costs can be suppressed.

[0294] The guard ring 2C may also include a second conductor 52C instead of a second conductor 52B. The material of the second conductor 52B or second conductor 52C in the guard ring 2C should be selected according to the strength and stress of the semiconductor chip 2.

[0295] [Sixth Embodiment] A sixth embodiment of the present technology, shown in Figure 49, will be described below. The differences between the photodetector 1 of this sixth embodiment and the photodetector 1 of the first embodiment described above are that the second semiconductor layer 50 is formed from an SOI substrate and that the height positions of the ends 52a of the second conductor 52 are aligned. The other configurations of the photodetector 1 are basically the same as those of the photodetector 1 of the first embodiment described above. Components that have already been described will be denoted by the same reference numerals and their descriptions will be omitted.

[0296] <<Configuration of the light detection device>> The configuration of the photodetector 1 according to the sixth embodiment of this technology will be described below, focusing on the differences from the configuration of the photodetector 1 according to the first embodiment described above. In the drawings illustrating this sixth embodiment, the same components may be depicted with different scales between drawings. Also, the barrier metal layer is omitted from the drawings illustrating this sixth embodiment. Furthermore, Figure 49 is a schematic diagram showing the longitudinal cross-sectional structure of the multiple second conductors 52 in the photodetector 1, and differs from the actual photodetector 1 in some respects. For example, the transistor T2, etc., is omitted from Figure 49. The same applies to the drawings from Figure 49 onward.

[0297] <Second Semiconductor Layer> The second semiconductor layer 50 is part of the semiconductor layer of the SOI (Silicon on Insulator) substrate. The second semiconductor layer 50 is formed, for example, from the semiconductor layer 50-3 shown in Figure 50A. As shown in Figure 50A, the SOI substrate 50S is a substrate in which an insulating layer 50-2 and a semiconductor layer 50-3 are superimposed in that order on one side of a base substrate 50-1 made of a semiconductor material (more specifically, silicon). The third surface S3 of the second semiconductor layer 50 corresponds to the surface of the semiconductor layer 50-3 opposite to the insulating layer 50-2 side. The insulating layer 50-2 is made of, for example, silicon oxide. The semiconductor layer 50-3 is made of, for example, silicon.

[0298] <Second conductor> The photodetector 1 has multiple second conductors 52. As shown in Figure 49, the height position of the end 52a of the second conductor 52 in the thickness direction of the second semiconductor layer 50 is the same for all of the second conductors 52. In other words, the height positions of the end 52a of the multiple second conductors 52 are aligned. The end 52a of the second conductor 52 is connected to the third connection pad 63. The end 52a is the end on the fourth surface S4 side in the thickness direction of the second semiconductor layer 50.

[0299] ≪Manufacturing Method for Light Detection Devices≫ The manufacturing method of the photodetector 1 will be described below with reference to Figures 50A to 50H. Here, the manufacturing method of the second conductor 52 will be the main focus. First, as shown in Figure 50A, an element such as a transistor T2 (not shown) is formed on the third surface S3 of the semiconductor layer 50-3. Then, a portion of the second wiring layer 40 is formed on the third surface S3. More specifically, for example, as shown in Figure 50A, an insulating film 41 is formed as a portion of the second wiring layer 40. Then, although not shown, a resist pattern is formed on the exposed surface of the insulating film 41 using a known lithography technique. Then, from the third surface S3 side, a hole 53 for embedding the second conductor 52 is formed using a known etching technique.

[0300] When forming the holes 53, the insulating layer 50-2 is used as an etching stop layer. The semiconductor layer 50-3 is etched from the third surface S3 side until the insulating layer 50-2 is reached, thereby forming the holes 53. Even if the insulating layer 50-2 is etched, only a small amount is removed. More specifically, the holes 53 at different locations on the wafer surface are etched until the holes 53 reach the insulating layer 50-2. As a result, the depth position of the bottom of the holes 53 in the thickness direction of the semiconductor layer 50-3 becomes the same for multiple holes 53. In other words, the depth positions of the bottom of multiple holes 53 are aligned.

[0301] Subsequently, as shown in Figure 50B, the insulating film 41m and the material constituting the second conductor 52 are laminated in that order from the third surface S3 side, and the excess is removed to form the second conductor 52. After that, the same process as shown in Figures 5E and 5F of the first embodiment is performed.

[0302] Next, as shown in Figure 50C, the base substrate 50-1 and the insulating layer 50-2 are ground and removed using the CMP method. The exposed surface of the semiconductor layer 50-3 after the base substrate 50-1 and the insulating layer 50-2 have been removed is flattened.

[0303] Then, as shown in Figure 50D, a portion of the semiconductor layer 50-3 is selectively etched by a known dry etching method. This leaves the portion of the semiconductor layer 50-3 that will become the second semiconductor layer 50. As a result of this process, the second conductor 52, which was embedded in the hole 53 and covered with the insulating film 41m, is exposed, and a portion of it protrudes from the fourth surface S4 of the second semiconductor layer 50. Furthermore, since the depth position of the bottom of the hole 53 is the same for all of the holes 53, the height position in the penetrating direction of the end 52a of the exposed second conductor 52 is the same for all of the second conductors 52. In other words, the height positions of the end 52a of the multiple second conductors 52 are aligned.

[0304] Then, as shown in Figure 50E, the silicon cover film 65 and the insulating film 61 are laminated in that order on the fourth surface S4 so as to cover the end portion 52a. Examples of high-melting-point oxides that make up the silicon cover film 65 include metal oxides, aluminum oxide (Al2O3), hafnium oxide (HfO2), and tantalum oxide (Ta2O5). Since the height positions of the end portions 52a of the multiple second conductors 52 are aligned, the silicon cover film 65 and the insulating film 61 can be laminated evenly.

[0305] Next, as shown in Figure 50F, the side of the wafer where the silicon cover film 65 and insulating film 61 are laminated is flattened by grinding using the CMP method, and the end portion 52a of the second conductor 52 is exposed. At this time, since the insulating film is mainly ground, the grinding conditions of the CMP method are set according to the insulating film. In addition, the insulating film 41m covering the end face of the end portion 52a is also ground and removed by this grinding. As described above, since the height positions of the multiple end portions 52a are aligned, when grinding using the CMP method, it is possible to suppress large variations in the timing of grinding the insulating film 41m covering the end face of the end portion 52a among the multiple second conductors 52. Therefore, it is possible to suppress large irregularities on the surface ground by the CMP method.

[0306] Subsequently, as shown in Figure 50G, insulating film 61c and insulating film 61 are laminated in that order on the exposed surface on the fourth surface S4 side. Insulating film 61c is a silicon carbonitride (SiCN) film. When insulating film 61c and insulating film 61 are not distinguished, it is referred to as insulating film 61.

[0307] Next, as shown in Figure 50H, a hole 63h extending to the second conductor 52 is formed on the flattened exposed surface from the insulating film 61 side using known lithography and etching techniques. Then, the material constituting the third connection pad 63 is laminated by a plating method so as to fill the inside of the hole 63h, and then the excess is removed by a CMP method to flatten the exposed surface. This gives rise to the third connection pad 63. This flattened surface is the bonding surface with the fourth wiring layer 70. Here, since the unevenness of the exposed surface before the hole 63h is formed is suppressed, the unevenness of the bonding surface with the fourth wiring layer 70 obtained after the formation of the third connection pad 63 can also be suppressed.

[0308] Then, although not shown in the diagram, the bonding surface of the third wiring layer 60 is bonded to the third semiconductor layer 80, which has a separately prepared fourth wiring layer 70 stacked on top of it.

[0309] <<Main effects of the sixth embodiment>> The main effects of the sixth embodiment will be described below, but before that, the manufacturing method of the multiple second conductors in the conventional photodetector shown in Figures 51A to 51C will be explained.

[0310] To form the second conductor 52, it is necessary to form deep holes 53 in the second semiconductor layer 50 by dry etching. When forming these deep holes 53, there was a possibility of depth fluctuations occurring within the wafer surface. If such fluctuations occurred, as shown in Figure 51A, there was a possibility of fluctuations in the height position of the exposed second conductor 52. Then, after laminating the insulating film 61 onto the exposed second conductor 52, the insulating film is ground and planarized by the CMP method. Under the conditions for grinding the insulating film 61, the metal constituting the second conductor 52 was difficult to grind, and it was sometimes difficult to eliminate the fluctuations in the height position of the exposed second conductor 52 by planarization using the CMP method. Therefore, the fluctuations in the height position of the second conductor 52 were carried over to subsequent processes. Furthermore, as shown in Figure 51B, fluctuations also occurred in the height of the third connection pad 63, and the bonding surface where the third connection pad 63 was exposed also had the potential to become uneven in accordance with the fluctuations in the height position of the second conductor 52. Furthermore, when such a joint surface is connected to the fourth wiring layer 70, a void V may occur depending on the size of the irregularities, as shown in Figure 51C. This could result in an open electrical circuit and a decrease in yield.

[0311] In contrast, in the photodetector 1 according to the sixth embodiment of this technology, when forming holes 53 from the third surface S3 side by etching, the insulating layer 50-2 of the SOI substrate 50S is used as an etching stop layer. This makes it possible to align the depth position of the bottom of the holes 53 in the thickness direction of the semiconductor layer 50-3 to be the same for multiple holes 53. As a result, the height position in the penetrating direction of the end 52a of the second conductor 52 that protrudes from the fourth surface S4 of the second semiconductor layer 50 can be aligned to be the same for multiple second conductors 52, and even after the subsequent CMP process, it is possible to suppress the increase in unevenness of the exposed surface. Furthermore, it is possible to suppress the deterioration of the flatness of the exposed surface in subsequent processes, and it is also possible to suppress the increase in unevenness of the bonding surface with the fourth wiring layer 70 obtained after forming the third connection pad 63. This makes it possible to suppress the occurrence of voids V and prevent electrical circuits from becoming open. And it is possible to suppress a decrease in yield.

[0312] <<Variation of the 6th Embodiment>> The following describes a modified version of the sixth embodiment.

[0313] <Example 1> As shown in Figure 52, the photodetector 1 according to the modified example 1 of the sixth embodiment has an insulating layer 50-2 of the SOI substrate 50S, and the end portion 52a of the second conductor 52 on the fourth surface S4 side penetrates the insulating layer 50-2.

[0314] The method for manufacturing the photodetector 1 according to Modification 1 of the Sixth Embodiment will be described below with reference to Figures 53A to 53D. Only the parts that differ from the process described in the Sixth Embodiment will be described here.

[0315] First, the same process as in Figure 50A of the sixth embodiment is performed to etch the holes 53 until they reach the insulating layer 50-2. More specifically, the holes 53 at different locations on the wafer surface are etched until they reach the insulating layer 50-2. Then, as shown in Figure 53A, the etching conditions are changed to etch the insulating layer 50-2, forming holes 53 that penetrate both the semiconductor layer 50 and the insulating layer 50-2. The etching of holes 53 at different locations on the wafer surface is aligned using the insulating layer 50-2 before etching of the insulating layer 50-2 begins. Therefore, it is possible to suppress large variations in the timing of initiating etching of the insulating layer 50-2 among multiple second conductors 52. As a result, the depth position of the bottom of the holes 53 in the thickness direction of the semiconductor layer 50-3 is the same for multiple holes 53. In other words, the depth positions of the bottom of multiple holes 53 are aligned.

[0316] Then, as shown in Figure 53B, the insulating film 41m and the material constituting the second conductor 52 are laminated in that order from the third surface S3 side, and the excess is removed to form the second conductor 52. Also, since the depth position of the bottom of the holes 53 is the same for all of the holes 53, the height position in the through direction of the end 52a of the protruding second conductor 52 is the same for all of the second conductors 52. In other words, the height positions of the end 52a of the multiple second conductors 52 are aligned.

[0317] Next, as shown in Figure 53C, the base substrate 50-1 is removed. First, the base substrate 50-1 is ground down to a certain thickness using the CMP method, and then the base substrate 50-1 is selectively etched using a known dry etching method. This exposes the second conductor 52 covered by the insulating film 41m and the insulating layer 50-2. In the modified example 1, the semiconductor layer 50-3 corresponds to the second semiconductor layer 50, and the fourth surface S4 of the second semiconductor layer 50 is the surface of the semiconductor layer 50-3 facing the insulating layer 50-2.

[0318] Subsequently, as shown in Figure 53D, insulating film 61c and insulating film 61 are laminated in that order on the fourth surface S4 so as to cover the end portion 52a of the second conductor 52. Then, similar to the process shown in Figure 50H of the sixth embodiment, a hole 63h extending to the second conductor 52 is formed, and a third connecting pad 63 is formed embedded in the hole 63h.

[0319] Even with the photodetector 1 according to this modification 1 of the sixth embodiment, the same effects as the photodetector 1 according to the sixth embodiment described above can be obtained. Furthermore, in the photodetector 1 according to modification 1 of the sixth embodiment, the insulating layer 50-2 is left intact, so the number of manufacturing steps can be reduced compared to the sixth embodiment. More specifically, the CMP process to remove the insulating layer 50-2 does not need to be performed. Also, since the insulating layer 50-2 is used as a silicon cover film 65, the process of laminating the silicon cover film 65 does not need to be performed. In addition, the process of laminating the insulating film 61 on the silicon cover film 65 and the CMP process of the laminated insulating film 61 do not need to be performed.

[0320] [Seventh Embodiment] A seventh embodiment of the present technology, shown in Figure 54, will be described below. The difference between the photodetector 1 of this seventh embodiment and the photodetector 1 of the first embodiment described above is that it is equipped with a protective insulating film 68. The other configurations of the photodetector 1 are basically the same as those of the photodetector 1 of the first embodiment described above. Components that have already been described are denoted by the same reference numerals and their descriptions are omitted.

[0321] <<Configuration of the light detection device>> The configuration of the photodetector 1 according to the seventh embodiment of this technology will be described below, focusing on the differences from the configuration of the photodetector 1 according to the first embodiment described above. Note that in the drawings illustrating this seventh embodiment, the same components may be depicted with different scales from one drawing to the next. Also, in the drawings illustrating this seventh embodiment, the barrier metal layer may be omitted from the illustration.

[0322] <3rd wiring layer> As shown in Figure 54, the third wiring layer 60 includes an insulating film 61, a third connection pad 63, a silicon cover film 65, and a protective insulating film 68. The thickness direction of the third wiring layer 60 is the Z direction.

[0323] The third connection pad 63 is laminated via an insulating film 61 and faces the side of the third wiring layer 60 opposite to the second semiconductor layer 50. The third connection pad 63 is a conductor and is made of a conductive material. The third connection pad 63 is not limited to, but may be made of copper, for example, and may be formed by the damascene process.

[0324] The silicon cover film 65 is laminated so as to cover the fourth surface S4 of the second semiconductor layer 50. On the surface of the silicon cover film 65 opposite to the fourth surface S4, an insulating film 61, a protective insulating film 68, and another insulating film 61 are laminated in that order.

[0325] The protective insulating film 68 is laminated on the fourth surface S4 side of the second semiconductor layer 50 via the insulating film 61. More specifically, the protective insulating film 68 is laminated on the fourth surface S4 side of the second semiconductor layer 50 via the silicon cover film 65 and the insulating film 61. The portion of the insulating film 61 laminated between the protective insulating film 68 and the silicon cover film 65 is sometimes called the first insulating film 61d to distinguish it from the other portion. The first insulating film 61d is a part of the insulating film 61 and is superimposed on the side of the protective insulating film 68 facing the second semiconductor layer 50. The protective insulating film 68 is not in contact with the third connection pad 63 to which the second conductor 52 is connected.

[0326] Furthermore, as shown in Figure 55C, the protective insulating film 68 is provided so as to surround the second conductor 52 in a plan view. And, as shown in Figures 54 and 55C, the protective insulating film 68 is not in contact with the second conductor 52.

[0327] The protective insulating film 68 is made of a material whose grinding speed under selected chemical mechanical polishing (CMP) conditions is slower than that of the material constituting the first insulating film 61d. Furthermore, the protective insulating film 68 is made of a material whose grinding speed under selected chemical mechanical polishing conditions is slower than that of the material constituting the second conductor 52.

[0328] The material constituting the first insulating film 61d is, but is not limited to, silicon oxide. The material constituting the second conductor 52 is, but is not limited to, tungsten. The material constituting the protective insulating film 68 is, for example, silicon nitride and silicon carbonitride. In this embodiment, the protective insulating film 68 is assumed to be made of silicon nitride.

[0329] The end portion 52a of the second conductor 52 on the fourth surface S4 side extends away from the fourth surface S4 and is connected to the third connecting pad 63 at a position that does not exceed the lamination position of the protective insulating film 68. The lamination position of the protective insulating film 68 is the lamination position of the protective insulating film 68 in the third wiring layer 60, and is a lamination position in the direction away from the fourth surface S4. More specifically, the lamination position of the protective insulating film 68 is the lamination position of the protective insulating film 68 on the side opposite to the fourth surface S4. In the example shown in Figure 54, the end portion 52a of the second conductor 52 is connected to the third connecting pad 63 at the lamination position of the protective insulating film 68 on the side opposite to the fourth surface S4.

[0330] ≪Manufacturing Method for Light Detection Devices≫ The manufacturing method of the photodetector 1 will be described below with reference to Figures 55A to 55F. Here, the manufacturing method of the second conductor 52 will be the main focus. First, as shown in Figure 5H of the first embodiment, the second conductor 52 protrudes from the fourth surface S4 of the second semiconductor layer 50. Then, as shown in Figure 55A, the silicon cover film 65, the first insulating film 61d, and the protective insulating film 68 are laminated on the fourth surface S4 in that order. Since the second conductor 52 protrudes from the fourth surface S4, the portions of the first insulating film 61d and the protective insulating film 68 that are laminated to cover the end portion 52a of the second conductor 52 protrude more than the other portions.

[0331] Then, from the state shown in Figure 55A, the exposed surface of the wafer on the protective insulating film 68 side is ground by chemical mechanical polishing under selected conditions. More specifically, the first insulating film 61d is selectively ground by chemical mechanical polishing under selected conditions. Note that pressure is applied to the portion of the protective insulating film 68 that overlaps with the edge 52a in the thickness direction (i.e., the upper end of the protrusion), so it can be ground. After the upper end of the protective insulating film 68 is ground, grinding of the first insulating film 61d is started. Then, the portion of the first insulating film 61d that protrudes more than the other parts is ground.

[0332] The grinding is then carried out until the end portion 52a is exposed and the exposed surface is flattened, as shown in Figure 55B. Therefore, while the portion of the first insulating film 61d that protrudes from the other parts is being ground, the protective insulating film 68 in the non-protruding portion is only slightly ground, and the protective insulating film 68 functions as a stop layer against grinding. Because the protective insulating film 68 functions as a stop layer against grinding, the grinding of the first insulating film 61d superimposed on the fourth surface S4 side of the protective insulating film 68 can be suppressed. Furthermore, since the grinding of the first insulating film 61d is suppressed, the grinding of the silicon cover film 65 located closer to the fourth surface S4 than the first insulating film 61d is also suppressed. Figure 55C is a plan view of Figure 55B from the side of the protective insulating film 68. As shown in Figure 55C, the protective insulating film 68 remains surrounding the end portion 52a of the second conductor 52.

[0333] Furthermore, by setting the lamination position of the protective insulating film 68 to be less than or equal to the height of the end 52a of the second conductor 52 before grinding, and more preferably less than the height of the end 52a of the second conductor 52 before grinding, the end 52a can be exposed more reliably. The lamination position of the protective insulating film 68 can be set by adjusting the film thickness of the first insulating film 61d.

[0334] Furthermore, the photodetector 1 has multiple second conductors 52, and multiple photodetectors 1 are provided on the wafer. In other words, the second conductors 52 are provided at different positions on the wafer surface. The protective insulating film 68 is laminated on the second conductors 52 provided at different positions on the wafer surface. For example, the protective insulating film 68 is laminated over the entire wafer surface. Grinding is performed at different positions on the wafer surface until the edges 52a are exposed and the exposed surfaces are flattened. Even if there are parts where grinding proceeds quickly and parts where grinding proceeds slowly at different positions on the wafer surface, the protective insulating film 68 functions as a stop layer against grinding, so that the first insulating film 61d and the silicon cover film 65 superimposed on the fourth surface S4 side of the protective insulating film 68 are suppressed from being locally exposed. In order to expose the multiple second conductors 52 provided at different positions on the wafer surface, it is preferable to set the lamination position of the protective insulating film 68 to the second conductors 52 with a smaller protrusion amount on the wafer surface.

[0335] Next, as shown in Figure 55D, an insulating film 61 is laminated onto the flattened exposed surface. Note that in Figure 55D, a portion of the hole 51h in the depth direction is omitted from the illustration. Then, as shown in Figure 55E, a hole 63h for forming the third connecting pad 63 and a hole 51h for forming the first conductor 51 are formed sequentially. The hole 63h is formed so that its bottom reaches the second conductor 52.

[0336] Then, as shown in Figure 55F, a barrier metal layer is laminated into holes 63h and 51h, the materials constituting the third connection pad 63 and the first conductor 51 are embedded, and the excess is removed by CMP to obtain the third connection pad 63 and the first conductor 51. The materials constituting the third connection pad 63 and the first conductor 51 are not limited to these, but are, for example, copper, and are deposited in holes 63h and 51h by plating. This completes the third wiring layer 60. The subsequent manufacturing methods have already been explained, so they will be omitted here.

[0337] <<Main effects of the 7th embodiment>> The main effects of the seventh embodiment will be explained below, but first, the conventional example will be described. The photodetector 1 has multiple second conductors 52, and multiple photodetectors 1 are provided on the wafer. In other words, multiple second conductors 52 are provided on the wafer surface. During the manufacturing process, the second conductors 52 protrude from the fourth surface S4, for example as shown in Figure 55A, but the amount of protrusion is not uniform for all second conductors 52 and varies within the wafer surface. Therefore, in the chemical mechanical polishing process shown in Figure 55B, the grinding amount was set taking into account the variation in the amount of protrusion of the second conductors 52. However, if the goal is to expose the second conductors 52 with small protrusions, the overall grinding amount increases. And when the overall grinding amount increases, there is a possibility that the variation in the amount of grinding within the wafer surface will increase. For example, there is a possibility that dishing will occur within the wafer surface. And there is a possibility that the amount of grinding will be excessively high locally within the wafer surface. And there is a possibility that the silicon cover film 65 will be ground down locally.

[0338] In contrast, the photodetector 1 according to the seventh embodiment of this technology is equipped with a protective insulating film 68. The protective insulating film 68 is made of a material whose grinding speed against chemical mechanical polishing under selected conditions is slower than that of the material constituting the first insulating film 61d and the material constituting the second conductor 52. Therefore, the protective insulating film 68 is difficult to grind and functions as a grinding stop layer. This suppresses excessive grinding of the first insulating film 61d and the second conductor 52. Furthermore, since excessive grinding of the first insulating film 61d is suppressed, grinding of the silicon cover film 65 is also suppressed.

[0339] Furthermore, in the photodetector 1 according to the seventh embodiment of this technology, the protective insulating film 68 is laminated on the second conductor 52 provided at different positions on the wafer surface. For example, the protective insulating film 68 is laminated over the entire wafer surface. Therefore, the protective insulating film 68 functions as a stop layer against grinding on the wafer surface. As a result, even when the total grinding amount is increased to expose the second conductor 52, which has a small protrusion on the wafer surface, it is possible to suppress excessive grinding of the first insulating film 61d surrounding the first exposed second conductor 52. As a result, excessive grinding locally on the wafer surface can be suppressed. As a result, it is possible to suppress localized grinding up to the silicon cover film 65.

[0340] Furthermore, the light detection device 1 according to the seventh embodiment described above may have a wiring 62 which is a conductor, and the second conductor 52 may be connected to the wiring 62.

[0341] Furthermore, in the photodetector 1 according to the seventh embodiment described above, as shown in Figures 54 and 55F, the end portion 52a of the second conductor 52 was connected to the third connecting pad 63 at the stacking position on the side opposite to the fourth surface S4 of the protective insulating film 68. However, it is also possible that it be connected to the third connecting pad 63 at a position closer to the second semiconductor layer 50 than the stacking position on the opposite side. Although not limited to this, for example, if over-etching is performed when forming the hole 63h shown in Figure 55E, the end portion 52a of the second conductor 52 will be connected to the third connecting pad 63 at a position closer to the third connecting pad 63 than in the case shown in Figures 54 and 55F.

[0342] The protective insulating film 68 may also be a block film made of silicon carbonitride. A block film is a film used to improve the controllability of forming holes for embedding wiring, etc.

[0343] <<Variations of the 7th Embodiment>> The following describes a modified version of the seventh embodiment.

[0344] <Example 1> In the seventh embodiment, the protective insulating film 68 was not in contact with the third connecting pad 63 to which the second conductor 52 was connected. However, in the photodetector 1 according to Modification 1 of the seventh embodiment, as shown in Figure 56, the protective insulating film 68 is in contact with the third connecting pad 63 to which the second conductor 52 is connected. Furthermore, in the photodetector 1 according to the seventh embodiment described above, the end portion 52a of the second conductor 52 was connected to the third connecting pad 63 at a stacking position on the side of the protective insulating film 68 opposite to the fourth surface S4. However, in the photodetector 1 according to Modification 1 of the seventh embodiment, the end portion 52a of the second conductor 52 was connected to the third connecting pad 63 at a position closer to the second semiconductor layer 50 than the stacking position on the opposite side.

[0345] The method for manufacturing the photodetector 1 according to Modification 1 of the 7th Embodiment will be described below with reference to Figures 57A to 57D. Only the parts that differ from the process described in the 7th Embodiment will be described here.

[0346] First, as shown in Figure 57A, after laminating up to the protective insulating film 68, a resist pattern R4 is formed to fill the recessed areas. Then, full-surface etch-back is performed, and subsequently, the resist pattern R4 is removed. This etch-back process removes the portion of the protective insulating film 68 that overlaps with the edge 52a in the thickness direction (i.e., the upper end of the protrusion), as shown in Figure 57B.

[0347] Subsequently, chemical mechanical polishing is performed in the same manner as in the seventh embodiment to obtain the state shown in Figure 57C. In this modified example 1, since the upper end of the protrusions of the protective insulating film 68 has been removed in advance, the grinding speed of the protrusions is faster than in the seventh embodiment, and the exposed portion of the second conductor 52 is ground more extensively than in the seventh embodiment, resulting in a dished state.

[0348] Then, as shown in Figure 57D, an insulating film 61 is laminated on the flattened exposed surface, and holes 63h for forming the third connection pad 63 and holes 51h for forming the first conductor 51 are sequentially formed. The holes 63h are formed so that their bottoms reach the second conductor 52. Also, the width of the holes 63h in the horizontal direction (direction perpendicular to the lamination direction (Z direction)) is the same as the opening of the protective insulating film 68. Therefore, the third connection pad 63 embedded in the holes 63h will be in contact with the protective insulating film 68. Furthermore, the bottom of the holes 63h is located closer to the second semiconductor layer 50 than in the seventh embodiment. As a result, the end 52a of the second conductor 52 is connected to the third connection pad 63 at a position closer to the second semiconductor layer 50 than the lamination position on the side of the protective insulating film 68 opposite to the fourth surface S4 side. The subsequent steps are the same as in the seventh embodiment, so the explanation is omitted.

[0349] Even with the photodetector 1 according to this seventh embodiment modification 1, the same effects as the photodetector 1 according to the seventh embodiment described above can be obtained.

[0350] <Modification 2> In Modification 1 of the 7th Embodiment, the protective insulating film 68 was in contact with the third connection pad 63 to which the second conductor 52 was connected. However, in the photodetector 1 according to Modification 2 of the 7th Embodiment, as shown in Figure 58, the protective insulating film 68 is not in contact with the third connection pad 63 to which the second conductor 52 is connected.

[0351] The method for manufacturing the photodetector 1 according to Modification 2 of the 7th Embodiment will be described below with reference to Figures 59A to 59D. Only the parts that differ from the process described in Modification 1 of the 7th Embodiment will be described here.

[0352] First, as shown in Figure 59A, after laminating up to the protective insulating film 68, a resist pattern R5 is formed to fill the recessed areas. Here, the resist pattern R5 is formed with gaps around the convex areas. Then, full-surface etch-back is performed, and after that, the resist pattern R5 is removed. As a result of this etch-back, as shown in Figure 59B, the portion of the protective insulating film 68 that overlaps with the edge 52a in the thickness direction (i.e., the upper end of the convex areas) and the recessed areas that are not covered by the resist pattern R5 are removed.

[0353] Subsequently, chemical mechanical polishing is performed to obtain the state shown in Figure 59C. In this modified example 2, the opening of the protective insulating film 68 is larger compared to modified example 1. And, similar to modified example 1, the exposed portion of the second conductor 52 is more extensively ground and dished than in the seventh embodiment.

[0354] Then, as shown in Figure 59D, an insulating film 61 is laminated onto the flattened exposed surface, and holes 63h for forming the third connection pad 63 and holes 51h for forming the first conductor 51 are sequentially formed. The width of the holes 63h in the horizontal direction (direction perpendicular to the lamination direction) is the same as in the case of Embodiment 2, and the opening of the protective insulating film 68 is larger than in the case of Embodiment 2, so the holes 63h do not come into contact with the opening of the protective insulating film 68. Therefore, the third connection pad 63 embedded in the holes 63h does not come into contact with the protective insulating film 68. The subsequent steps are the same as in the case of the seventh embodiment, so the explanation is omitted.

[0355] Even with the photodetector 1 according to this modified example 2 of the seventh embodiment, the same effects as the photodetector 1 according to the seventh embodiment described above can be obtained.

[0356] [Eighth Embodiment] The eighth embodiment of this technology, shown in Figure 60, will be described below. The difference between the photodetector 1 of this eighth embodiment and the photodetector 1 of the first embodiment described above is that it is equipped with a third conductor 57. The other configurations of the photodetector 1 are basically the same as those of the photodetector 1 of the first embodiment described above. Components that have already been described are denoted by the same reference numerals and their descriptions are omitted.

[0357] <<Configuration of the light detection device>> The configuration of the photodetector 1 according to the eighth embodiment of this technology will be described below, focusing on the differences from the configuration of the photodetector 1 according to the first embodiment described above. Note that in the drawings illustrating this eighth embodiment, the same components may be depicted with different scales between drawings. Furthermore, in the drawings illustrating this eighth embodiment and their description, the insulating film provided between the third conductor 57 and the second semiconductor layer 50, and the insulating film provided between the second conductor 52 and the second semiconductor layer 50 are omitted from the illustration. In addition, the barrier metal layer is omitted from the drawings illustrating this eighth embodiment.

[0358] <Overview> First, let's describe the outline of the eighth embodiment. Generally, when a through-conductor is formed that penetrates a semiconductor layer in the thickness direction, the semiconductor layer around the through-conductor is pulled towards the through-conductor. In other words, stress is generated in the semiconductor layer around the through-conductor. This stress in the semiconductor layer around the through-conductor can potentially affect the characteristics of the transistor. For this reason, transistors are sometimes designed to be positioned at a certain distance away from the through-conductor.

[0359] Here, we will explain the second conductor 52, which is a through-conductor that penetrates the semiconductor layer, as illustrated in Figure 61A. The arrow CH represents the channel direction. The channel direction indicates the direction in which signal charge flows in a transistor provided in the semiconductor layer. In the eighth embodiment, for convenience, we will explain assuming that the channel direction is parallel to the X direction. Also, the exposed surface (plane of the paper) of the semiconductor layer is the (100) plane.

[0360] Due to the stress described above, the semiconductor layer surrounding the second conductor 52 creates regions that would affect the performance of a transistor if it were formed. More specifically, these regions include areas where the amount of signal charge flowing through the channel increases and areas where the amount of signal charge flowing through the channel decreases. Figure 61A shows regions K1 and K2, which have a significant impact on the amount of signal charge flowing through the channel. Region K1 is the region where the amount of signal charge flowing through the channel increases if a transistor were formed, and it occurs on both sides of the second conductor 52. More specifically, region K1 occurs along the direction perpendicular to the channel direction (Y direction) on both sides of the second conductor 52. Region K2 is the region where the amount of signal charge flowing through the channel decreases if a transistor were formed, and it occurs on both sides of the second conductor 52. More specifically, region K2 occurs along the direction parallel to the channel direction (X direction) on both sides of the second conductor 52. The direction in which regions K1 (increased signal charge) and K2 (decreased signal charge) occur depends on the channel direction. Furthermore, since two regions K1 and two regions K2 are generated for each through-conductor (second conductor 52), they are sometimes called regions K1a and K1b, and regions K2a and K2b, respectively, to distinguish them from each other. In addition, the surrounding circle that encloses such regions K1 and K2 is called the Keep Out Zone (KOZ).

[0361] The presence of regions K1 and K2 can restrict the placement of transistors. Therefore, the photodetector 1 according to the eighth embodiment, as shown in Figure 61B, includes a third conductor 57 that is separate from the second conductor 52 and is arranged such that the second conductor 52 and the keep-out region KOZ overlap at a 45-degree angle with respect to the channel direction. The third conductor 57 is made of the same material and has the same diameter as the second conductor 52. Ideally, regions K1 and K2 of the third conductor 57 are the same size as regions K1 and K2 of the second conductor 52. The third conductor 57 is arranged alongside the second conductor 52 along a direction that forms a 45-degree angle with the channel direction. Because the third conductor 57 is arranged in this way, ideally, region K1b of the third conductor 57 and region K2a of the second conductor 52 can be exactly overlapped, and region K2b of the third conductor 57 and region K1a of the second conductor 52 can be exactly overlapped. Therefore, as shown in Figure 61C, ideally, the increase and decrease of signal charge can be canceled out in the region where the region K1a of the second conductor 52 and the region K2b of the third conductor 57 overlap. Similarly, ideally, the increase and decrease of signal charge can be canceled out in the region where the region K2a of the second conductor 52 and the region K1b of the third conductor 57 overlap. In this way, by overlapping regions of the same size with opposite increases and decreases in signal charge, the increases and decreases of signal charge can be canceled out. Furthermore, in regions where the increases and decreases of signal charge are canceled out, the performance of a transistor, such as transistor T2, is suppressed to be significantly affected.

[0362] Furthermore, while the keep-out region KOZ exists for both the second conductor 52 and the third conductor 57, by arranging the second conductor 52 and the third conductor 57 as shown in Figure 61C, the keep-out region KOZ can be reduced to half its size (a semicircle).

[0363] <Third conductor> The photodetector 1 includes a third conductor 57. As shown in Figure 60, the third conductor 57 is a conductor that penetrates the semiconductor layer. More specifically, the third conductor 57 penetrates the second semiconductor layer 50 and protrudes into the second wiring layer 40 and the third wiring layer 60. The third conductor 57 is formed simultaneously with the second conductor 52 and has the same length in the extending direction. The third conductor 57 is made of the same material as the second conductor 52 and has the same diameter. The third conductor 57 and the second conductor 52 are made of tungsten, for example, but are not limited to this. The third conductor 57 is provided in the second semiconductor layer 50 in the vicinity of the second conductor 52. Because the third conductor 57 is provided, the increase and decrease of signal charge in the semiconductor layer around the second conductor 52 are canceled out. Therefore, it becomes possible to provide the transistor T2 closer to the second conductor 52 than if the third conductor 57 were not provided. Therefore, the constraints on the layout design of the transistor T2 can be relaxed. The third conductor 57 is a dummy conductor provided in the semiconductor layer surrounding the second conductor 52 to cancel out increases and decreases in signal charge. Therefore, the third conductor 57 may be in a floating state or connected to a reference potential.

[0364] Figure 62 shows an example in which one second conductor 52 and multiple third conductors 57 are arranged in a line. Note that the number of third conductors 57 is not limited to the number shown in Figure 62. Also, to distinguish between multiple third conductors 57, they may be called third conductors 57-1, 57-2, 57-3, and 57-4. These conductors are arranged in the order of third conductor 57-1, third conductor 57-2, second conductor 52, third conductor 57-3, and third conductor 57-4, along a direction that forms a 45-degree angle with the channel direction, more specifically, in a line. These conductors are arranged in one dimension.

[0365] Third conductors 57-2 and 57-3 are positioned on either side of the second conductor 52. Therefore, the increase and decrease of signal charge around the second conductor 52, more specifically in the semiconductor layers on either side, cancel each other out. More specifically, the increase and decrease of signal charge in the regions K1 and K2 on the upper left side of the second conductor 52 and the regions K2 and K1 on the lower right side of the third conductor 57-2 overlap, canceling each other out. Furthermore, the increase and decrease of signal charge in the regions K2 and K1 on the lower right side of the second conductor 52 and the regions K1 and K2 on the upper left side of the third conductor 57-3 overlap, canceling each other out.

[0366] Furthermore, multiple third conductors 57 are positioned on either side of the second conductor 52. On the upper left side of the second conductor 52, the regions K1 and K2 on the upper left side of the third conductor 57-2 overlap with the regions K2 and K1 on the lower right side of the third conductor 57-1, canceling out the increase and decrease of signal charge in that region. Similarly, on the lower right side of the second conductor 52, the regions K2 and K1 on the lower right side of the third conductor 57-3 overlap with the regions K1 and K2 on the upper left side of the third conductor 57-4, canceling out the increase and decrease of signal charge in that region. In this way, by increasing the number of arranged third conductors 57, the region where the increase and decrease of signal charge around the second conductor 52 are canceled out can be expanded. Furthermore, the keep-out region KOZ can be moved to a position further away from the second conductor 52.

[0367] ≪Manufacturing Method for Light Detection Devices≫ The manufacturing method of the photodetector 1 will be described below with reference to Figures 63A and 63B. Here, the manufacturing methods of the third conductor 57 and the second conductor 52 will be described in detail. The third conductor 57 and the second conductor 52 are formed by via middles from the third surface S3 side. First, as shown in Figure 63A, a transistor T2, etc., is formed on the third surface S3 side of the second semiconductor layer 50w, and an insulating film 41 is laminated. Then, from the insulating film 41 side (third surface S3 side), a hole 57h for forming the third conductor 57, a hole 53 for forming the second conductor 52, and a hole 44h for forming the via 44 are formed. The hole 57h is formed simultaneously with the hole 53 in the same process and has the same depth.

[0368] Subsequently, as shown in Figure 63B, tungsten is simultaneously embedded in holes 57h, 53, and 44h from the insulating film 41 side (third surface S3 side) using the same process, and the excess tungsten is removed by the known CMP method. This forms the third conductor 57, the second conductor 52, and the via 44. From this point onward, the same process as in the first embodiment is carried out, causing the third conductor 57 and the second conductor 52 to protrude from the surface opposite to the third surface S3 side (fourth surface S4). In this way, the third conductor 57 is formed simultaneously with the second conductor 52 using the same process, and their lengths in the extending direction are the same. The subsequent manufacturing method has already been described, so it will be omitted here.

[0369] <<Main effects of the 8th embodiment>> The main effects of the eighth embodiment are described below. In the photodetector 1 according to the eighth embodiment, the third conductor 57 and the second conductor 52 are arranged along a direction that forms a 45-degree angle with the channel direction. As a result, regions K1 and K2 of the third conductor 57 overlap with regions K2 and K1 of the second conductor 52, and the increase and decrease in signal charge in that region can be canceled out. Therefore, the region that was originally the keep-out region KOZ of the second conductor 52 is no longer a keep-out region, making it possible to place the transistor T2 in that region. As a result, the transistor T2 can be placed in a position closer to the second conductor 52. In this way, the constraint on the placement position of the transistor T2 due to the keep-out region KOZ can be suppressed, and the constraints on the layout design of the transistor T2 can be relaxed.

[0370] Furthermore, in the photodetector 1 according to the eighth embodiment, since the third conductor 57 is arranged on both sides of the second conductor 52, the increase or decrease in signal charge can be canceled out around the second conductor 52, or more specifically, in the semiconductor layers on both sides.

[0371] Furthermore, in the photodetector 1 according to the eighth embodiment, multiple third conductors 57 are arranged on either side of the second conductor 52. By increasing the number of arranged third conductors 57, the region in which the increase and decrease of signal charge around the second conductor 52 cancel each other out can be expanded. In addition, the keep-out region KOZ can be moved to a position further away from the second conductor 52.

[0372] Furthermore, in the photodetector 1 according to the eighth embodiment, the third conductor 57 and the second conductor 52 are formed simultaneously in the same process, thus suppressing an increase in the number of processes. Therefore, an increase in manufacturing costs can be suppressed.

[0373] Note that the direction in which the second conductor 52 and the third conductor 57 are arranged is not limited to that shown in Figure 62. The direction in which the second conductor 52 and the third conductor 57 are arranged may be perpendicular to the direction shown in Figure 62. The same applies to the following modifications regarding the arrangement direction.

[0374] Furthermore, although the third surface S3 and the fourth surface S4 of the second semiconductor layer 50 were (100) surfaces, they may be other surfaces. In that case, the direction in which the second conductor 52 and the third conductor 57 are arranged may be at a different angle with respect to the channel direction, i.e., an angle other than 45 degrees.

[0375] <<Variations of the 8th Embodiment>> The following describes a modified version of the eighth embodiment.

[0376] <Example 1> In the eighth embodiment, the third conductor 57 protruded into the second wiring layer 40 and the third wiring layer 60, but the present technology is not limited to this. In the photodetector 1 according to Modification 1 of the eighth embodiment, as shown in Figure 64, the third conductor 57 does not protrude into the second wiring layer 40 and the third wiring layer 60. The third conductor 57 does not need to protrude into the wiring layer superimposed on the second semiconductor layer 50, as long as it penetrates at least the second semiconductor layer 50.

[0377] Even with the photodetector 1 according to this eighth embodiment modification 1, the same effects as the photodetector 1 according to the eighth embodiment described above can be obtained.

[0378] <Modification 2> In the eighth embodiment, the third conductor 57 was arranged one-dimensionally with respect to the second conductor 52 along a direction forming a 45-degree angle with the channel direction, but the present technology is not limited to this. As shown in Figure 65, the third conductor 57 may be arranged two-dimensionally with respect to the second conductor 52 along two directions forming a 45-degree angle with the channel direction. In Figure 65, one conductor is the second conductor 52 and the rest are the third conductors 57, but the number and placement of the second conductors 52 are not limited to the example shown in Figure 65. For example, the layout of the second conductors 52 can be considered based on the positions of the conductors in the matrix shown in Figure 65. More specifically, any third conductor 57, excluding the conductors at the four corners shown in Figure 65, can be replaced with a second conductor 52. Except for the conductors at the four corners shown in Figure 65, the increase or decrease in signal charge can be offset regardless of where the second conductors 52 are placed or whether the number of second conductors 52 is increased.

[0379] Even with the photodetector 1 according to this modified example 2 of the eighth embodiment, the same effects as the photodetector 1 according to the eighth embodiment described above can be obtained.

[0380] Furthermore, in the photodetector 1 according to the modified example 2 of this eighth embodiment, the second conductor 52 and the third conductor 57 are arranged two-dimensionally in a matrix, which makes it easier to design the placement of the second conductor 52, and in particular the placement of multiple second conductors.

[0381] <Variation 3> In the eighth embodiment, the third conductor 57 was made of the same material and had the same diameter as the second conductor 52, but the present technology is not limited thereto. As shown in Figure 66, the third conductor 57 may be made of the same material as the second conductor 52 but have a different diameter. More specifically, the third conductor 57 may have a smaller diameter than the second conductor 52.

[0382] Figure 66 shows a single second conductor 52 and multiple third conductors 57 arranged in a row. These multiple third conductors 57 are sometimes referred to as third conductors 57-5, 57-6, and 57-7 to distinguish them from one another. These conductors are arranged in a row along a direction that forms a 45-degree angle with the channel direction, in the order of second conductor 52, third conductor 57-5, third conductor 57-6, and third conductor 57-7. Furthermore, the diameter of the third conductors decreases in this order (arrangement order), starting from the second conductor 52. In other words, the diameter of the third conductors 57 decreases as they move away from the second conductor 52.

[0383] As the diameter of the third conductor 57 decreases, the stress on the surrounding semiconductor layer also decreases. And as the stress decreases, regions K1 and K2 also decrease. A third conductor 57-5, which has a smaller diameter than the second conductor 52, is positioned on the lower right side of the plane of the second conductor 52. Furthermore, regions K2 and K1 on the lower right side of the plane of the second conductor 52 overlap with regions K1 and K2 on the upper left side of the plane of the third conductor 57-5, which are smaller in size. Although regions K1 and K2 of the third conductor 57-5 are smaller than regions K2 and K1 of the second conductor 52, they overlap with parts of regions K2 and K1 of the second conductor 52, canceling out the increase and decrease in signal charge in the overlapping parts. In addition, regions K2 and K1 on the lower right side of the plane of the third conductor 57-5 overlap with regions K1 and K2 on the upper left side of the plane of the third conductor 57-6, which are smaller in size. Regions K1 and K2 of the third conductor 57-6 are smaller than regions K2 and K1 of the third conductor 57-5, but they overlap with parts of regions K2 and K1 of the third conductor 57-5, canceling out the increase and decrease in signal charge in the overlapping region. The same applies to the third conductor 57-7. In this way, by gradually reducing the diameter of the third conductor 57, the region where the increase and decrease in signal charge occurs is reduced little by little. The keep-out region KOZ remaining in the third conductor 57-7 is smaller in size than that of the second conductor 52.

[0384] Even with the photodetector 1 according to this modified example 3 of the eighth embodiment, the same effects as the photodetector 1 according to the eighth embodiment described above can be obtained.

[0385] Furthermore, in the photodetector 1 according to the 3rd modification of this 8th embodiment, the diameter of the third conductor 57 is gradually reduced, so that the region in which the signal charge increases or decreases is reduced in part, and the size of the remaining keep-out region KOZ can be reduced. Moreover, the more such third conductors 57 are increased, the smaller the size of the remaining keep-out region KOZ can be.

[0386] The number of third conductors 57 is not limited to the number shown in Figure 66. Also, in the modified example 3 of the eighth embodiment, the third conductor 57 is provided only on one side of the second conductor 52, but it may also be provided on the other side or on both sides.

[0387] <Modification 4> In the eighth embodiment, the third conductor 57 and the second conductor 52 were formed by via middles from the third surface S3 side, but the present technology is not limited thereto. As shown in Figure 67, the third conductor 57 and the second conductor 52 may be formed by via lasts from the fourth surface S4 side. In that case, the third conductor 57 and the second conductor 52 are made of the same material as the material that constitutes the first conductor 51. In the fourth modification of the eighth embodiment, although not limited thereto, for example, the third conductor 57, the second conductor 52, and the first conductor 51 are made of copper.

[0388] Next, the manufacturing method of the photodetector 1 according to this modified example will be described. As shown in Figure 68, an insulating film 61 is laminated on the fourth surface S4 side of the second semiconductor layer 50. Then, from the insulating film 61 side (fourth surface S4 side), holes 57h for forming the third conductor 57, holes 53 for forming the second conductor 52, and holes 51h for forming the first conductor 51 are formed. After that, copper is simultaneously embedded in holes 57h, holes 53, and holes 51h from the insulating film 61 side (fourth surface S4 side) using the same process, and the excess copper is removed by a known CMP method. This forms the third conductor 57, the second conductor 52, and the first conductor 51 shown in Figure 67.

[0389] Even with the photodetector 1 according to this modified example 4 of the eighth embodiment, the same effects as the photodetector 1 according to the eighth embodiment described above can be obtained.

[0390] <Modification 5> In the eighth embodiment, the third conductor 57 was made of the same material and had the same diameter as the second conductor 52, but the present technology is not limited thereto. As shown in Figures 69 and 70, the third conductor 57 may be made of a different material and have a different diameter than the second conductor 52. In this modified example, the third conductor 57 is made of copper and the second conductor 52 is made of tungsten. Also, the diameter of the third conductor 57 is smaller than the diameter of the second conductor 52.

[0391] Generally, different materials constituting a through-conductor result in different stresses on the surrounding semiconductor layer. Furthermore, the stress on the surrounding semiconductor layer can be expressed as the product of the thermal expansion coefficient and Young's modulus. For example, tungsten and copper exhibit the following differences in stress on the surrounding semiconductor layer. Note that the stress ratios described below are normalized values ​​when the stress on the surrounding semiconductor layer by tungsten is set to "1". Material / Coefficient of thermal expansion (10 -6 / K) / Young's modulus (GPa) / Stress / Stress ratio Tungsten / 4.3 / 345 / 1483.5 / 1 Copper / 16.8 / 129.8 / 2180.6 / 1.47

[0392] Thus, copper exerts more stress on the semiconductor layer than tungsten. More specifically, copper exerts approximately 1.5 times more stress on the semiconductor layer than tungsten. Therefore, if the copper third conductor 57 is provided with the same diameter as the tungsten second conductor 52, the keep-out region KOZ of the third conductor 57 is considered to be approximately 1.5 times that of the keep-out region KOZ of the second conductor 52. Here, in order to cancel out the increase and decrease in signal charge, it is ideally preferable that the stress exerted on the semiconductor layer is approximately the same for the third conductor 57 and the second conductor 52. Therefore, when the third conductor 57 is made of copper and the second conductor 52 is made of tungsten, the diameter of the third conductor 57 should be smaller than the diameter of the second conductor 52. As a result, as shown in Figure 70, the stress exerted by the third conductor 57 on the second semiconductor layer 50 can be made to be approximately the same as the stress exerted by the second conductor 52 on the second semiconductor layer 50, and the increase and decrease in signal charge can be canceled out. In other words, by making the third conductor 57 from a material that exerts a greater stress on the semiconductor layer than the material constituting the second conductor 52, the diameter of the third conductor 57 can be made smaller than that of the second conductor 52, thus saving space.

[0393] Next, the manufacturing method of the photodetector 1 according to this modified example will be described. In this modified example, the third conductor 57 is formed by via last from the fourth surface S4 side, and the second conductor 52 is formed by via middle from the third surface S3 side. First, as shown in Figure 71A, the second conductor 52 and via 44 are formed by via middle from the third surface S3 side. Then, after the process already described, as shown in Figure 71B, an insulating film 61 is laminated on the fourth surface S4 side of the second semiconductor layer 50. Then, from the insulating film 61 side (fourth surface S4 side), holes 57h for forming the third conductor 57, holes 51h for forming the first conductor 51, and holes for forming wiring layers, etc. are formed. Then, from the insulating film 61 side (fourth surface S4 side), copper is simultaneously embedded in the holes 57h and 51h, and the excess copper is removed by the known CMP method. This forms the third conductor 57, the second conductor 52, and the first conductor 51 shown in Figure 69.

[0394] Even with the photodetector 1 according to this modified example 5 of the eighth embodiment, the same effects as the photodetector 1 according to the eighth embodiment described above can be obtained.

[0395] Furthermore, in the photodetector 1 according to modification 5 of this eighth embodiment, the third conductor 57 is made of a material that exerts a greater stress on the semiconductor layer than the material constituting the second conductor 52, thereby making the diameter of the third conductor 57 smaller than that of the second conductor 52. As a result, the installation area of ​​the third conductor 57 can be reduced in a plan view, and the third conductor 57 can be installed even in narrow spaces.

[0396] Furthermore, when both the third conductor 57 and the second conductor 52 are formed by via middle from the third surface S3 side, they may be formed by covering one of the holes 57h and 53 with resist while filling the other hole 57h and 53 with material. The same applies when both the third conductor 57 and the second conductor 52 are formed by via last from the fourth surface S4 side.

[0397] <Variation 6> In Modification 6 of the 8th Embodiment, the third conductor 57 was formed by via last from the fourth surface S4 side, and the second conductor 52 was formed by via middle from the third surface S3 side. However, this technology is not limited to this. As shown in Figure 72, the third conductor 57 may be formed by via middle from the third surface S3 side, and the second conductor 52 may be formed by via last from the fourth surface S4 side. In that case, the second conductor 52 is made of the same material as the material constituting the first conductor 51. In Modification 6 of the 8th Embodiment, although not limited to this, for example, the third conductor 57 and via 44 may be made of tungsten, and the second conductor 52 and first conductor 51 may be made of copper. The second conductor 52 is made of a material that exerts a greater stress on the semiconductor layer than the material constituting the third conductor 57. For this reason, the diameter of the second conductor 52 is set to be smaller than that of the third conductor 57.

[0398] First, as shown in Figure 73A, the third conductor 57 and via 44 are formed from the third surface S3 side. Then, following the previously described process, as shown in Figure 73B, a hole 53 for forming the second conductor 52 and a hole 51h for forming the first conductor 51 are formed from the fourth surface S4 side. After that, copper is embedded in the holes 53 and 51h from the insulating film 61 side (fourth surface S4 side), and the excess copper is removed by the known CMP method. This forms the third conductor 57, the second conductor 52, and the first conductor 51 shown in Figure 72.

[0399] [Ninth Embodiment] The ninth embodiment of this technology, shown in Figures 74A to 74C, will be described below. The difference between the photodetector 1 of this ninth embodiment and the photodetector 1 of the first embodiment described above is that it includes a mark MK having a fourth conductor 58 and an etching stop layer 46, and the alignment mark AL used in the lithography process is composed of multiple marks MK. The rest of the configuration of the photodetector 1 is basically the same as that of the photodetector 1 of the first embodiment described above. Components that have already been described will be denoted by the same reference numerals and their descriptions will be omitted.

[0400] <<Configuration of the light detection device>> The configuration of the photodetector 1 according to the ninth embodiment of this technology will be described below, focusing on the differences from the configuration of the photodetector 1 according to the first embodiment described above. Note that in the drawings illustrating this ninth embodiment, the same components may be depicted with different scales from one drawing to the next. Also, the barrier metal layer is omitted from the drawings illustrating this ninth embodiment.

[0401] Figure 74B is a plan view of the entire alignment mark AL. The dimensions of the alignment mark AL are on the order of microns. Figure 74C is a partially enlarged plan view showing an enlarged area AA of Figure 74B. As shown in Figure 74C, one alignment mark AL contains multiple marks MK. Figure 74A is a longitudinal cross-sectional view, for convenience, showing the cross-sectional structure of one mark MK and one second conductor 52.

[0402] <Alignment Marks> The alignment mark AL is used in the lithography process when forming the wiring 62 connected to the end 52a of the second conductor 52 to align the wiring 62 with respect to the second conductor 52. Therefore, the alignment mark AL is formed in the process of forming the second conductor 52. Figure 74B shows an example of the shape of the alignment mark AL. The alignment mark AL may have a shape other than the cross shape shown in Figure 74B, such as a square or a circle. In addition, to improve the accuracy of the alignment, the alignment mark AL is placed inside the semiconductor chip 2 rather than inside the scribe line.

[0403] <mark> As shown in Figure 74C, one alignment mark AL is composed of multiple marks MK. More specifically, multiple marks MK are arranged in two dimensions to constitute one alignment mark AL. In this embodiment, it is assumed that the marks MK are arranged along the X and Y directions. The marks MK are densely arranged in a matrix along the X and Y directions. By arranging multiple marks MK, the contour of the alignment mark AL appears as a line. The shape of the marks MK is not limited to the shape shown in Figure 74C, and may be the shape shown in the modified example of this embodiment or other shapes. Furthermore, the combination of the shape of the marks MK and the shape of the alignment mark AL is diverse and is not limited to those shown.

[0404] As shown in Figure 74A, the mark MK is provided on the third surface S3 side of the second semiconductor layer 50. As shown in Figures 74A and 74B, the mark MK has a fourth conductor 58, an etching stop layer 46, and an insulating film 41m.

[0405] (Fourth conductor) The fourth conductor 58 has the same diameter as the second conductor 52. The diameter of the fourth conductor 58 is formed to be on the order of several hundred nanometers. Furthermore, the fourth conductor 58 is made of the same material as the material that constitutes the second conductor 52. In this embodiment, although not limited thereto, an example will be described in which the fourth conductor 58 and the second conductor 52 are made of tungsten. The positional relationship between the second conductor 52 and the fourth conductor 58 in the thickness direction of the photodetector 1 is as shown in Figure 74A. More specifically, the end 52a of the second conductor 52 on the fourth surface S4 side extends away from the fourth surface S4 and is connected to the wiring 62 of the third wiring layer 60. The end 58a of the fourth conductor 58, which is the end closer to the wiring 62, is located closer to the wiring 42 of the second wiring layer 40 than the connection point between end 52a and the wiring 62. That is, end 58a does not reach the connection point between end 52a and the wiring 62. Furthermore, an etching stop layer 46 is provided between the fourth conductor 58 and the second semiconductor layer 50.

[0406] (Etching stop layer) The etching stop layer 46, which will be described in detail in the manufacturing method described later, functions as a film that slows down the etching rate of the hole 58h for embedding the fourth conductor 58. The etching stop layer 46 consists of a single layer film and is laminated on the third surface S3 of the second semiconductor layer 50. The etching stop layer 46 is provided in a position that overlaps with the fourth conductor 58 in a plan view and is provided in a circular shape in a plan view as shown in Figure 74C. The etching stop layer 46 is made of a material whose etching rate for a selected etchant is slower than both the material constituting the insulating film 41 and the material constituting the second semiconductor layer 50 (silicon). For example, if the insulating film 41 is made of silicon oxide, the material constituting the etching stop layer 46 can be silicon nitride, metal, etc. In this embodiment, it is assumed that the insulating film 41 is made of silicon oxide and the etching stop layer 46 is made of silicon nitride.

[0407] ≪Manufacturing Method for Light Detection Devices≫ The manufacturing method of the photodetector 1 will be described below with reference to Figures 75A to 75E. Here, the manufacturing methods of the fourth conductor 58 and the second conductor 52 will be mainly described. First, as shown in Figure 75A, a transistor T2, etc., is formed on the third surface S3 side of the second semiconductor layer 50w. Then, an etching stop layer 46 is formed on the third surface S3 of the second semiconductor layer 50w. More specifically, the etching stop layer 46 is formed at the position where the mark MK is to be provided in a plan view. The etching stop layer 46 is formed using, for example, known film deposition techniques, lithography techniques, etching techniques, etc. Then, an insulating film 41 is laminated so as to cover the etching stop layer 46.

[0408] Next, as shown in Figure 75B, a hole 58h for forming the fourth conductor 58 and a hole 53 for forming the second conductor 52 are simultaneously formed from the insulating film 41 side (third surface S3 side) using known lithography and etching techniques. More specifically, a resist pattern R6 having openings R6a and R6b is formed on the exposed surface of the insulating film 41 using known lithography techniques, and the portions exposed from openings R6a and R6b are simultaneously etched using known etching techniques to obtain holes 58h and 53.

[0409] In a plan view, opening R6a is provided at the position where hole 58h is formed, and opening R6b is provided at the position where hole 53 is formed. Of these, opening R6a is provided at a position that overlaps with the etching stop layer 46 in a plan view, more specifically at a position inside the etching stop layer 46 in a plan view. This makes it possible to provide hole 58h at a position that overlaps with the etching stop layer 46 in a plan view. More specifically, the bottom of hole 58h can be provided at a position inside the etching stop layer 46 in a plan view.

[0410] When etching begins, the insulating film 41 exposed from openings R6a and R6b is etched first. Then, the portion exposed from opening R6b continues to be etched, from the insulating film 41 to the second semiconductor layer 50 and the third wiring layer 60. This forms hole 53. In contrast, the etching of the portion exposed from opening R6a slows down once hole 58h reaches the etching stop layer 46, and even if the etching stop layer 46 is etched, only a small amount is removed. In this way, hole 58h is formed. While the etching of hole 53 progresses to the second semiconductor layer 50 and the third wiring layer 60, the etching stop layer 46 exposed at the bottom of hole 58h is etched only a small amount. Since hole 58h does not penetrate the etching stop layer 46, the second semiconductor layer 50 and the third wiring layer 60 are not etched. In this way, hole 58h is formed shallower than hole 53. After that, the resist pattern R6 is removed.

[0411] Next, as shown in Figure 75C, the insulating film 41m is laminated into the holes 58h and 53 from the insulating film 41 side (third surface S3 side), and then tungsten is embedded into the holes 58h and 53. Then, the excess portions of the insulating film 41m and tungsten are removed, for example, by the CMP method. This yields the fourth conductor 58 and the second conductor 52. Since the hole 58h is formed shallower than the hole 53, the end portion 58a of the fourth conductor 58 can be positioned at a different location in the lamination direction (thickness direction) from the end portion 52a of the second conductor 52, more specifically at a shallower position. Then, the steps shown in Figures 5E to 5H of the first embodiment are performed.

[0412] Subsequently, as shown in Figure 75D, the silicon cover film 65 and the insulating film 61 are laminated in this order. Then, as shown in Figure 75E, the exposed surface of the insulating film 61 is flattened by grinding using the CMP method, exposing the end 52a of the second conductor 52. More specifically, only the second conductor 52 of the fourth conductor 58 and the second conductor 52 is exposed. Since the end 58a of the fourth conductor 58 is located within the second wiring layer 40, its exposure is suppressed by wafer flattening. Therefore, the end 58a of the fourth conductor 58 is suppressed from being ground by the CMP method. In this way, since the fourth conductor 58 of mark MK is suppressed from being ground by the CMP method, the occurrence of irregularities on the end 58a of the fourth conductor 58 is suppressed.

[0413] Next, although not shown in the diagram, an insulating film 61 is further laminated onto the flattened exposed surface to form wiring 62 and the like, completing the third wiring layer 60. Here, the process of forming the wiring 62 will be explained. To form holes for embedding the wiring 62, a resist pattern is formed using known lithography techniques. At that time, an alignment mark AL having multiple marks MK is used to align the second conductor 52 and the wiring 62. As shown in Figure 75E, the fourth conductor 58 of the marks MK is suppressed from being ground by the CMP method, and the occurrence of irregularities at the end 58a is suppressed. Therefore, the alignment light used during alignment is reflected by the end 58a of the fourth conductor 58 that has not been ground by the CMP method. This suppresses a decrease in alignment accuracy. The manufacturing method thereafter has already been explained, so it will be omitted.

[0414] <<Main effects of the 9th embodiment>> The main effects of the ninth embodiment will be described below, but first, the conventional example will be explained. As shown in Figure 76, the conventional mark MKa has a fourth conductor 58 and an insulating film 41m, and does not have an etching stop layer 46. Because the fourth conductor 58 does not have an etching stop layer 46, the hole filling the fourth conductor 58 penetrates the second semiconductor layer 50 and extends to the insulating film 61. Furthermore, the end 58a of the fourth conductor 58 was formed at the same position in the stacking direction as the end 52a of the second conductor 52. Therefore, both the end 58a and the end 52a were subjected to grinding by the CMP method. Here, when planarizing by grinding by the CMP method, the ideal is to aim for flatness, but strictly speaking, irregularities may occur. Therefore, as shown in Figure 76, irregularities occurred on the end 58a of the fourth conductor 58, and in the subsequent lithography process, there was a possibility that the alignment light would be diffusely reflected by the irregularities on the end 58a. This could lead to a decrease in alignment accuracy. Furthermore, variations in the amount of grinding of the fourth conductor 58, more specifically within the chip surface or wafer surface, could potentially reduce alignment accuracy.

[0415] In contrast, in the photodetector 1 according to the ninth embodiment of this technology, since the mark MK has an etching stop layer 46, the etching rate of the hole 58h can be slowed down midway, and the hole 58h can be formed shallower than the hole 53. As a result, the end 58a of the fourth conductor 58 can be placed at a different position in the stacking direction (thickness direction) from the end 52a of the second conductor 52, more specifically at a shallower position. In Figure 74A, the end 58a of the fourth conductor 58 is located within the second wiring layer 40. Therefore, grinding of the end 58a of the fourth conductor 58 by the CMP method is suppressed. In this way, grinding of the fourth conductor 58 of the mark MK by the CMP method is suppressed, so that irregularities occur on the end 58a of the fourth conductor 58. Therefore, diffuse reflection of alignment light due to irregularities on the end 58a can be suppressed, and a decrease in alignment accuracy can be suppressed. Furthermore, since the fourth conductor 58 of mark MK is suppressed from being ground by the CMP method, changes in the shape of mark MK within the chip surface or wafer surface can be suppressed, and a decrease in alignment accuracy can be suppressed.

[0416] The second conductor 52 may also be connected to the third connecting pad 63. Furthermore, the timing for forming the etching stop layer 46 is not limited to the timing described in the manufacturing method above. The etching stop layer 46 can be formed at any time before the insulating film 41 is laminated on the third surface S3.

[0417] <<Variations of the 9th Embodiment>> The following describes a modified version of the ninth embodiment.

[0418] <Example 1> In the ninth embodiment, the etching stop layer 46 of the mark MK was a single layer film, but the present technology is not limited to this. In the photodetector 1 according to the first modification of the ninth embodiment, as shown in Figure 77, the etching stop layer 46 of the mark MK has a laminated structure in which a third layer 46a and a fourth layer 46b are stacked in that order on the third surface S3. In addition, the hole 58h penetrates only the fourth layer 46b of the third layer 46a and the fourth layer 46b.

[0419] The third layer 46a functions as an etching stop layer under conditions for etching the second semiconductor layer 50. The third layer 46a is made of a material whose etching rate with respect to a selected etchant is slower than that of the material (silicon) constituting the second semiconductor layer 50. The third layer 46a is made of, but is not limited to, silicon oxide.

[0420] Furthermore, the fourth layer 46b functions as an etching stop layer under conditions for etching the insulating film 41. The fourth layer 46b is made of a material whose etching rate with respect to the selected etchant is slower than that of the material constituting the insulating film 41 (silicon oxide). The fourth layer 46b is made of silicon, for example, although it is not limited to this.

[0421] Thus, the fourth layer 46b functions as an etching stop layer when etching the insulating film 41 of the insulating film 41 and the second semiconductor layer 50. The third layer 46a functions as an etching stop layer when etching the second semiconductor layer 50 of the insulating film 41 and the second semiconductor layer 50.

[0422] The manufacturing method of the photodetector 1 will be described below with reference to Figures 78A to 78C. In this modified example 1, the explanation will focus on the differences from the manufacturing method described in the ninth embodiment. First, as shown in Figure 78A, the third layer 46a and the fourth layer 46b are stacked in this order on the third surface S3 of the second semiconductor layer 50w. After that, the insulating film 41 is stacked.

[0423] Next, as shown in Figure 78B, a resist pattern R6 is formed on the exposed surface of the insulating film 41, and the portions exposed from the openings R6a and R6b are simultaneously etched using a known etching technique to obtain holes 58h and 53. In the etching of hole 53, two types of materials, the insulating film 41 and the second semiconductor layer 50, are etched. Figure 78B shows the stages in which the insulating film 41 is etched. The etching of the portion exposed from the opening R6a slows down when hole 58h reaches the fourth layer 46b. Furthermore, even if the fourth layer 46b is etched, it is only slightly.

[0424] Subsequently, as shown in Figure 78C, the etching conditions are changed, and the process moves to etching the second semiconductor layer 50w (silicon). Here, the fourth layer 46b, exposed from the bottom of the hole 58h, is made of silicon, so it is etched at about the same speed as the etching of the hole 53. The etching of the portion exposed from the opening R6a slows down once the hole 58h reaches the third layer 46a. Even if the third layer 46a is etched, it is only slightly. In this way, since the hole 53 is formed across different materials, by layering etching stop layers 46 corresponding to each of the different materials, it is possible to suppress the hole 58h from penetrating the entire etching stop layer 46 even if the etching conditions change for each material. This makes it possible to form the hole 58h shallower than the hole 53. The subsequent manufacturing method has already been explained, so it will be omitted here.

[0425] Even with the photodetector 1 according to this modified example 1 of the ninth embodiment, the same effects as the photodetector 1 according to the ninth embodiment described above can be obtained.

[0426] Furthermore, in the photodetector 1 according to the modified example 1 of the ninth embodiment, even when the holes 53 for forming the second conductor 52 are formed across different materials, the etching stop layer 46 is multilayered corresponding to each of the different materials. Therefore, even if the etching conditions change for each material, it is possible to suppress the holes 58h from penetrating the entire etching stop layer 46. As a result, the holes 58h can be formed shallower than the holes 53.

[0427] <Modification 2> In the ninth embodiment, the mark MK is provided on the third surface S3 side of the second semiconductor layer 50, and the end 58a of the fourth conductor 58 is located within the second wiring layer 40; however, the present technology is not limited to this. As shown in Figure 79, the fourth conductor 58 may penetrate the second semiconductor layer 50, and the end 58a may be located within the third wiring layer 60. Furthermore, the mark MK has an etching stop layer 46c instead of the etching stop layer 46.

[0428] (Fourth conductor) The fourth conductor 58 penetrates the etching stop layer 46c and the second semiconductor layer 50, reaching into the third wiring layer 60. The end 58a of the fourth conductor 58 is located closer to the wiring 42 of the second wiring layer 40 than the connection point between the end 52a and the wiring 62. In other words, the end 58a does not reach the connection point between the end 52a and the wiring 62.

[0429] (Etching stop layer) The hole 58h penetrates the etching stop layer 46c by etching. This is achieved by changing at least one of the film thickness of the etching stop layer 46c and the material constituting the etching stop layer 46c. In this modified example 2, an example is described in which the film thickness of the etching stop layer 46c is made thinner than the film thickness of the etching stop layer 46 in the ninth embodiment.

[0430] The etching stop layer 46c is made of silicon nitride, similar to the etching stop layer 46 of the ninth embodiment, but its film thickness is thinner than that of the etching stop layer 46 of the ninth embodiment. Under conditions for etching the insulating film 41 and the second semiconductor layer 50, although the etching rate of silicon nitride is slow, it is not completely etched. Therefore, by making the film thickness thinner, the holes 58h will penetrate the etching stop layer 46c over time.

[0431] The manufacturing method of the photodetector 1 will be described below with reference to Figures 80A to 80C. In this modified example 2, the focus will be on the differences from the manufacturing method described in the ninth embodiment. First, as shown in Figure 80A, an etching stop layer 46c is formed on the third surface S3 of the second semiconductor layer 50w, thinner than the etching stop layer 46 of the ninth embodiment. Then, an insulating film 41 is laminated to cover the etching stop layer 46 to form a resist pattern R6 having openings R6a and R6b. The portions exposed from openings R6a and R6b are then etched simultaneously using known etching techniques to obtain holes 58h and 53. The etching of the portion exposed from opening R6a slows down when hole 58h reaches the etching stop layer 46, and the etching of the etching stop layer 46 proceeds slowly over time. While the etching of the etching stop layer 46 of hole 58h proceeds slowly, the etching of the portion exposed from the opening R6b, i.e., hole 53, proceeds, progressing from the etching of the insulating film 41 to the etching of the second semiconductor layer 50. Subsequently, when hole 58h penetrates the etching stop layer 46, the etching of hole 58h proceeds to the second semiconductor layer 50. However, because it took time to penetrate the etching stop layer 46, as shown in the figure, hole 58h is formed shallower than hole 53. Then, similar to the ninth embodiment, the insulating film 41m and tungsten are laminated in that order in the holes 58h and 53 from the insulating film 41 side (third surface S3 side) to obtain the fourth conductor 58 and the second conductor 52. Then, the process shown in Figures 5E to 5H of the first embodiment is performed.

[0432] Next, as shown in Figure 80B, the silicon cover film 65 and the insulating film 61 are laminated in this order to cover the fourth conductor 58 and the second conductor 52 that protrude from the fourth surface S4. Since the aforementioned hole 58h is formed shallower than the hole 53, the amount of protrusion of the fourth conductor 58 from the fourth surface S4 is smaller than the amount of protrusion of the second conductor 52.

[0433] Then, as shown in Figure 80C, the exposed surface of the insulating film 61 is flattened by grinding using the CMP method, exposing the end 52a of the second conductor 52. More specifically, only the second conductor 52 of the second conductor 52 is exposed. Although the end 58a of the fourth conductor 58 is located within the insulating film 61 of the third wiring layer 60, similar to th...

Claims

1. A single conductor is formed in the semiconductor layer that penetrates itself. An insulating film is laminated so as to cover one end of the aforementioned conductor, From the insulating film side, another conductor is formed, which is made of a material different from the material constituting the first conductor and has a diameter larger than the diameter of the first conductor, so as to penetrate the semiconductor layer. From the insulating film side, a wiring connected to the first conductor and a wiring connected to the other conductor are formed. A method for manufacturing a light detection device.

2. The material constituting the first conductor is a second material, The first method for forming the conductor is: Etching from one side of the second semiconductor layer to form a hole in the semiconductor layer, The first conductor is formed by sequentially laminating an insulating film, different from the insulating film, and the second material in this order against the inner wall of the hole. By etching the second semiconductor layer from the other side of the second semiconductor layer, one end of the first conductor protrudes from the other side of the second semiconductor layer, while leaving the portion that will become the semiconductor layer intact. including, A method for manufacturing a light detection device according to claim 1.

3. A first semiconductor layer having a photoelectric conversion region, wherein one surface is a first surface and the other surface is a second surface which is the light incident surface, A second semiconductor layer having one side as the third surface and the other side as the fourth surface, A second wiring layer superimposed on the third surface of the second semiconductor layer, A third wiring layer superimposed on the fourth surface of the second semiconductor layer, A first wiring layer having one side superimposed on the first surface of the first semiconductor layer and the other side superimposed on one of the wiring layers of the second wiring layer and the third wiring layer, A first conductor having a first width and penetrating the second semiconductor layer along the thickness direction, A second conductor having a second width smaller than the first width and penetrating the second semiconductor layer along the thickness direction, Equipped with, The second semiconductor layer has a first transistor in which the second conductor serves as the gate electrode and the insulating film provided between the side surface of the second conductor and the second semiconductor layer serves as the gate insulating film. Light detection device.

4. The photodetector according to claim 3, wherein the second conductor is connected only to the conductor provided in the third wiring layer, out of the conductor provided in the second wiring layer and the conductor provided in the third wiring layer.

5. The photodetector according to claim 4, wherein at least one of the diffusion regions constituting the source and the diffusion region constituting the drain of the first transistor is connected only to the conductor of the third wiring layer among the conductors of the second wiring layer and the conductors of the third wiring layer.

6. A first semiconductor layer having a photoelectric conversion region, wherein one surface is a first surface and the other surface is a second surface which is the light incident surface, A second semiconductor layer having one side as the third surface and the other side as the fourth surface, A second wiring layer superimposed on the third surface of the second semiconductor layer, A third wiring layer superimposed on the fourth surface of the second semiconductor layer, A first wiring layer having one side superimposed on the first surface of the first semiconductor layer and the other side superimposed on one of the wiring layers of the second wiring layer and the third wiring layer, A first conductor having a first width and penetrating the second semiconductor layer along the thickness direction, A second conductor having a second width smaller than the first width and penetrating the second semiconductor layer along the thickness direction, Equipped with, The third wiring layer comprises an insulating film and a third connecting pad provided on the insulating film, one of which is the bottom surface and the other is the bonding surface. The end of the second conductor on the fourth face side extends to the third connecting pad and is connected to the third connecting pad. The bottom surface of the third connection pad is the surface on the second semiconductor layer side, The portion of the insulating film that contacts the bottom surface of the third connecting pad is made of a material with a high etching rate for an etchant, selected from the material that constitutes the portion of the insulating film that contacts the side surface which connects the bottom surface of the third connecting pad and the bonding surface. Light detection device.

7. The photodetector according to claim 6, wherein the end of the second conductor on the fourth surface side faces the joining surface of the third connecting pad.

8. The photodetector according to claim 6, wherein the end of the second conductor on the fourth surface side is located within the third connecting pad.

9. The third semiconductor layer, A fourth wiring layer is provided, one side of which is superimposed on the third semiconductor layer, and the other side of which is superimposed on the second wiring layer and the other wiring layer of the third wiring layer. The photodetector according to claim 6, wherein the bonding surface of the third connection pad is connected to a connection pad of the wiring layer of the first wiring layer and the fourth wiring layer that is superimposed on the third wiring layer.

10. A first semiconductor layer having a photoelectric conversion region, wherein one surface is a first surface and the other surface is a second surface which is the light incident surface, A second semiconductor layer having one side as the third surface and the other side as the fourth surface, A second wiring layer superimposed on the third surface of the second semiconductor layer, A third wiring layer superimposed on the fourth surface of the second semiconductor layer, A first wiring layer having one side superimposed on the first surface of the first semiconductor layer and the other side superimposed on one of the wiring layers of the second wiring layer and the third wiring layer, A first conductor having a first width and penetrating the second semiconductor layer along the thickness direction, A second conductor having a second width smaller than the first width and penetrating the second semiconductor layer along the thickness direction, Equipped with, The second wiring layer has an insulating film and wiring provided in the insulating film, The end of the first conductor on the third side extends to one of the wirings and is connected to that wiring. The aforementioned wiring has a laminated structure comprising a first layer made of a first conductive material containing copper, and a second layer made of a second conductive material that does not contain copper, located between the first layer and the end of the first conductor on the third surface side. Light detection device.

11. The photodetector according to claim 10, wherein the second conductive material is tungsten, ruthenium, titanium, tantalum, tantalum nitride, aluminum, or silicon.

12. The photodetector according to claim 11, wherein the first conductive material is copper.

13. A first semiconductor layer having a photoelectric conversion region, wherein one surface is a first surface and the other surface is a second surface which is the light incident surface, A second semiconductor layer having one side as the third surface and the other side as the fourth surface, A second wiring layer superimposed on the third surface of the second semiconductor layer, A third wiring layer superimposed on the fourth surface of the second semiconductor layer, A first wiring layer having one side superimposed on the first surface of the first semiconductor layer and the other side superimposed on one of the wiring layers of the second wiring layer and the third wiring layer, A first conductor having a first width and penetrating the second semiconductor layer along the thickness direction, A second conductor having a second width smaller than the first width and penetrating the second semiconductor layer along the thickness direction, Equipped with, A separator insulating film is provided between the second conductor and the second semiconductor layer, The third wiring layer comprises an insulating film and wiring provided in the insulating film. The second conductor is integrally provided with one of the wirings of the third wiring layer using the same material, The isolation insulating film protrudes into the insulating film of the third wiring layer, The isolation insulating film has a higher density than the insulating film of the third wiring layer. Light detection device.

14. The photodetector according to claim 13, wherein the thickness of the separating insulating film on the third surface side is greater than the thickness on the fourth surface side.

15. A high-melting-point metal film is provided between the second conductor and the isolation insulating film. The second conductor is connected to one of the wirings of the second wiring layer, The photodetector according to claim 13, wherein the high-melting-point metal film is also provided between the second conductor and the first wiring of the second wiring layer.

16. The photodetector according to claim 15, wherein the portion of the high-melting-point metal film provided between the second conductor and the separating insulating film has a thickness on the fourth side that is greater than the thickness on the third side.

17. The photodetector according to claim 13, comprising: a second conductor made of a third material; and a second conductor made of a fourth material different from the third material.

18. A first semiconductor layer having a photoelectric conversion region, wherein one surface is a first surface and the other surface is a second surface which is the light incident surface, A second semiconductor layer having one side as the third surface and the other side as the fourth surface, A second wiring layer superimposed on the third surface of the second semiconductor layer, A third wiring layer superimposed on the fourth surface of the second semiconductor layer, A first wiring layer having one side superimposed on the first surface of the first semiconductor layer and the other side superimposed on one of the wiring layers of the second wiring layer and the third wiring layer, A first conductor having a first width and penetrating the second semiconductor layer along the thickness direction, A second conductor having a second width smaller than the first width and penetrating the second semiconductor layer along the thickness direction, Equipped with, The third wiring layer comprises an insulating film, a protective insulating film laminated on the fourth side of the second semiconductor layer via the insulating film, and a conductor. The end of the second conductor on the fourth surface side extends away from the fourth surface and is connected to the conductor at a position not exceeding the lamination position of the protective insulating film. The protective insulating film is not in contact with the second conductor. Light detection device.

19. The photodetector according to claim 18, wherein the protective insulating film is made of a material whose grinding speed for chemical mechanical polishing under selected conditions is slower than that of the material constituting the insulating film.

20. The photodetector according to claim 18, wherein the protective insulating film is made of a material whose grinding speed for chemical mechanical polishing under selected conditions is slower than that of the material constituting the second conductor.

21. The photodetector according to claim 18, wherein the protective insulating film is made of silicon nitride or silicon carbonitride.

22. A first semiconductor layer having a photoelectric conversion region, wherein one surface is a first surface and the other surface is a second surface which is the light incident surface, A second semiconductor layer having one side as the third surface and the other side as the fourth surface, A second wiring layer superimposed on the third surface of the second semiconductor layer, A third wiring layer superimposed on the fourth surface of the second semiconductor layer, A first wiring layer having one side superimposed on the first surface of the first semiconductor layer and the other side superimposed on one of the wiring layers of the second wiring layer and the third wiring layer, A first conductor having a first width and penetrating the second semiconductor layer along the thickness direction, A second conductor having a second width smaller than the first width and penetrating the second semiconductor layer along the thickness direction, Equipped with, It comprises a first fixed charge film provided to cover the outer circumferential surface of one of the second conductors, which is a fifth conductor, and a second fixed charge film provided to cover the outer circumferential surface of the other second conductor, which is a sixth conductor, The first fixed charge film and the second fixed charge film are one and the other of a negative fixed charge film and a positive fixed charge film. Light detection device.

23. The second semiconductor layer includes a third region which is a semiconductor region of a first conductivity type and is located on the fourth surface side, a fourth region which is a semiconductor region of a second conductivity type and is located on the third surface side, a fifth region which is a semiconductor region of a first conductivity type and is located on the third surface side, and a sixth region which is a semiconductor region of a second conductivity type and is located between the third region and the fifth region. The fifth conductor penetrates the third region and the fourth region, The photodetector according to claim 22, wherein the sixth conductor penetrates the third region, the sixth region, and the fifth region.

24. The second semiconductor layer includes a seventh region which is a semiconductor region of the first conductivity type and an eighth region which is a semiconductor region of the second conductivity type. The seventh region is located in a position that covers the outer surface of the first fixed charge film, The eighth region is located in a position that covers the outer surface of the second fixed charge film. The light detection device according to claim 22.

25. The photodetector according to claim 23, wherein the first fixed charge film is the negative fixed charge film when the first conductivity type is p-type, and the positive fixed charge film when the first conductivity type is n-type.

26. The first fixed charge film is the negative fixed charge film, The second fixed charge film is the positive fixed charge film, The aforementioned second semiconductor layer is a semiconductor layer formed from a p-type semiconductor substrate. The second semiconductor layer is provided with a second transistor, which is a p-channel conductive field-effect transistor, and a third transistor, which is an n-channel conductive field-effect transistor. The fifth conductor is electrically connected to any of the gate electrode, source region, and drain region of the second transistor. The photodetector according to claim 22, wherein the sixth conductor is electrically connected to any of the gate electrode, source region, and drain region of the third transistor.

27. The first fixed charge film is the positive fixed charge film, The second fixed charge film is the negative fixed charge film, The aforementioned second semiconductor layer is a semiconductor layer formed from an n-type semiconductor substrate. The second semiconductor layer is provided with a second transistor, which is an n-channel conductive field-effect transistor, and a third transistor, which is a p-channel conductive field-effect transistor. The fifth conductor is electrically connected to any of the gate electrode, source region, and drain region of the second transistor. The photodetector according to claim 22, wherein the sixth conductor is electrically connected to any of the gate electrode, source region, and drain region of the third transistor.

28. A first semiconductor layer having a photoelectric conversion region, where one surface is a first surface and the other surface is a second surface which is the light incident surface, A second semiconductor layer having one side as the third surface and the other side as the fourth surface, A second wiring layer superimposed on the third surface of the second semiconductor layer, A third wiring layer superimposed on the fourth surface of the second semiconductor layer, A first wiring layer having one side superimposed on the first surface of the first semiconductor layer and the other side superimposed on one of the wiring layers of the second wiring layer and the third wiring layer, A first conductor having a first width and penetrating the second semiconductor layer along the thickness direction, A second conductor having a second width smaller than the first width and penetrating the second semiconductor layer along the thickness direction, Equipped with, The second conductor has, in the thickness direction of the second semiconductor layer, a seventh conductor located closer to the third surface and an eighth conductor located closer to the fourth surface. The first end of the seventh conductor, which is the end closest to the fourth face, is connected to the second end of the eighth conductor, which is the end closest to the third face, within the second semiconductor layer. The diameter of the second end is different from the diameter of the first end. The second conductor and the second semiconductor layer are insulated from each other by an insulating film provided on the outer surface of the second conductor. The thickness of the portion of the insulating film provided on the outer circumferential surface of the end with the smaller diameter of the first end and the second end is greater than the thickness of the portion of the conductor having the smaller diameter of the seventh conductor and the eighth conductor that is provided on the outer circumferential surface other than the end with the smaller diameter. Light detection device.

29. The diameter of the seventh conductor gradually decreases as it approaches the first end. The photodetector according to claim 28, wherein the diameter of the eighth conductor gradually decreases as it approaches the second end.

30. The photodetector according to claim 28, wherein the diameter of the second end is greater than the diameter of the first end.

31. The photodetector according to claim 28, wherein the diameter of the eighth conductor at the position of the fourth surface in the thickness direction of the second semiconductor layer is greater than the diameter of the seventh conductor at the position of the third surface.

32. A first semiconductor layer having a photoelectric conversion region, where one surface is a first surface and the other surface is a second surface which is the light incident surface, A second semiconductor layer having one side as the third surface and the other side as the fourth surface, A second wiring layer superimposed on the third surface of the second semiconductor layer, A third wiring layer superimposed on the fourth surface of the second semiconductor layer, A first wiring layer having one side superimposed on the first surface of the first semiconductor layer and the other side superimposed on one of the wiring layers of the second wiring layer and the third wiring layer, A first conductor having a first width and penetrating the second semiconductor layer along the thickness direction, A second conductor having a second width smaller than the first width and penetrating the second semiconductor layer along the thickness direction, Equipped with, The second conductor has, in the thickness direction of the second semiconductor layer, a seventh conductor located closer to the third surface and an eighth conductor located closer to the fourth surface. The first end of the seventh conductor, which is the end closest to the fourth face, is connected to the second end of the eighth conductor, which is the end closest to the third face, within the second semiconductor layer. The seventh and eighth conductors are rectangles that are elongated in different directions when viewed from above. Light detection device.

33. A first semiconductor layer having a photoelectric conversion region, wherein one surface is a first surface and the other surface is a second surface which is the light incident surface, A second semiconductor layer having one side as the third surface and the other side as the fourth surface, A second wiring layer superimposed on the third surface of the second semiconductor layer, A third wiring layer superimposed on the fourth surface of the second semiconductor layer, A first wiring layer having one side superimposed on the first surface of the first semiconductor layer and the other side superimposed on one of the wiring layers of the second wiring layer and the third wiring layer, A first conductor having a first width and penetrating the second semiconductor layer along the thickness direction, A second conductor having a second width smaller than the first width and penetrating the second semiconductor layer along the thickness direction, Equipped with, The first conductor is made of a first material, The second conductor is made of a second material different from the first material, Each of the first conductor and the second conductor protrudes from the fourth surface into the third wiring layer. The heights of the first conductor and the second conductor that protrude into the third wiring layer are different from each other. Light detection device.

34. The photodetector according to claim 33, wherein the height of the second conductor protruding into the third wiring layer is higher than the height of the first conductor protruding into the third wiring layer.

35. The photodetector according to claim 33, wherein the height of the first conductor protruding into the third wiring layer is higher than the height of the second conductor protruding into the third wiring layer.

36. The end of the first conductor that protrudes into the third wiring layer is electrically connected to the first wiring of the third wiring layer via a connector. The photodetector according to claim 34, wherein the end of the second conductor that protrudes into the third wiring layer is directly electrically connected to a second wiring which is part of the wiring of the third wiring layer and belongs to the same metal layer as the first wiring.

37. A first semiconductor layer having a photoelectric conversion region, wherein one surface is a first surface and the other surface is a second surface which is the light incident surface, A second semiconductor layer having one side as the third surface and the other side as the fourth surface, A second wiring layer superimposed on the third surface of the second semiconductor layer, A third wiring layer superimposed on the fourth surface of the second semiconductor layer, A first wiring layer having one side superimposed on the first surface of the first semiconductor layer and the other side superimposed on one of the wiring layers of the second wiring layer and the third wiring layer, A first conductor having a first width and penetrating the second semiconductor layer along the thickness direction, A second conductor having a second width smaller than the first width and penetrating the second semiconductor layer along the thickness direction, Equipped with, The second semiconductor layer has an insulating member that penetrates it along the thickness direction, In a plan view, the second conductor is surrounded by a portion of the second semiconductor layer, and the portion of the second semiconductor layer is further surrounded by the insulating member, resulting in a triple-layer structure. Light detection device.

38. A light detection device according to any one of claims 3 to 37, and an optical system for forming an image of light from a subject on the light detection device, electronic equipment.

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