Power converter

Abstract

Provided is a power conversion device (100) comprising: a power converter (1) that is constituted of a plurality of leg circuits (8) connected in parallel, the leg circuits (8) having positive electrode-side and negative electrode-side arms (9) connected in series; and a control unit (7) that controls the power converter (1). The positive electrode-side and negative electrode-side arms (9) are constituted of one converter cell (10) or a plurality of converter cells (10) connected in series, the converter cell (10) having a series body in which a plurality of semiconductor switching elements (12U, 12L) are connected in series, and also having a capacitor (15) connected in parallel to the series body. The control unit (7) comprises: a gate signal generation unit (90) that compares an arm modulation command and a carrier wave and generates gate signals (GU, GL) for driving the semiconductor switching elements (12U, 12L); and a gate signal switching determination unit (80) that determines whether to switch the number of times that the gate signal changes between on and off during one cycle of the carrier wave.

Description

Technical Field

[0001] This application relates to a power conversion device.

Background Art

[0002] In recent years, in power conversion devices used for high-voltage applications such as power systems, the practical application of a multilevel converter configured by connecting a plurality of converter cells each provided with a capacitor in series multiple connection has been attempted. These converters are called, for example, a modular multilevel converter (hereinafter abbreviated as MMC) method or a cascade multilevel converter (hereinafter abbreviated as CMC) method, and are used for, for example, conversion from three-phase alternating current to direct current or its reverse conversion. These converters generate an output voltage using the capacitor voltages of the converter cells connected in series multiple connection.

[0003] As a switching method of MMC, there is a phase shift PWM method. This method compares a modulation command and a carrier wave, and determines a gate signal based on the magnitude relationship therebetween. Usually, it is adjusted so that a gate pulse is generated once per cycle of the carrier wave. Since the capacitor voltage in each converter cell of MMC varies due to the charge and discharge of the current flowing through the arm, when the frequency of the carrier wave is low, if the phase shift PWM method is applied to MMC and adjusted to generate a gate pulse once per cycle of the carrier wave, there is a concern that the ripple of the capacitor voltage will increase and the operation cannot be continued.

[0004] On the other hand, a configuration is known in which an MMC control device includes an illegal pulse prevention device, is adjusted to generate a gate pulse once per cycle of the carrier wave, and increases the frequency of the carrier wave when the deviation between the signal level before removing illegal pulses and the signal level after removing illegal pulses is large, thereby suppressing the ripple of the capacitor voltage and improving the followability to the output voltage (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0005] [Patent Document 1] Japanese Patent Publication No. 2021-197809 [Overview of the project] [Problems that the invention aims to solve]

[0006] In the configuration of Patent Document 1, if the deviation between the signal level before and after removing the erroneous pulse is large, the carrier frequency can be increased to improve tracking of the output voltage. However, increasing the carrier frequency increases switching losses. Therefore, although methods using multiple carrier frequencies are known, the problem of tracking of the output voltage at low carrier frequencies still remains.

[0007] This application discloses technology to solve the above-mentioned problems, and aims to provide a power converter that can continue operation without increasing the carrier frequency, even when operating at a low carrier frequency, thereby suppressing an increase in switching losses. [Means for solving the problem]

[0008] The power conversion device disclosed in this application is A power conversion device comprising a power conversion unit that performs power conversion between AC and DC, and a control unit that controls the power conversion unit, wherein multiple leg circuits are provided, each having a positive-side arm and a negative-side arm corresponding to multiple phases connected in series, and the connection point of these leg circuits is connected to each phase AC line, and these leg circuits are connected in parallel between positive and negative DC lines, and the power conversion device comprises a power conversion unit that performs power conversion between AC and DC, and a control unit that controls the power conversion unit, Each of the positive and negative electrodes has one or more converter cells connected in series, each cell having a series unit in which a plurality of semiconductor switching elements are connected in series and a capacitor connected in parallel to this series unit. The control unit, A modulation command generation unit calculates an arm modulation command for each of the multiple positive-side arms and the negative-side arms based on the voltage command values ​​output by the multiple positive-side arms and the negative-side arms, A gate signal generation unit compares the calculated arm modulation command with the carrier wave to generate a gate signal for driving a plurality of semiconductor switching elements, The system includes a gate signal switching determination unit that determines whether or not to switch the number of times the gate signal is switched on or off per cycle of the carrier wave with respect to the carrier wave frequency, The gate signal switching determination unit determines whether to switch the number of times the gate signal is turned on or off per cycle of the carrier wave if the voltage of the capacitor exceeds a preset voltage range. When the number of on / off changes of the gate signal is considered to be 2 for one pulse, the gate signal generation unit selectively performs one of the following based on the result of the gate signal switching determination unit: limit the number of gate signal pulses to 1 within one cycle of the carrier wave, or adjust it to a number greater than 1 that is below a preset allowable number. This generates the aforementioned gate signal. [Effects of the Invention]

[0009] According to the power converter described herein, operation can be continued even when the carrier frequency is low, and the increase in switching losses can be suppressed. [Brief explanation of the drawing]

[0010] [Figure 1] This is a schematic diagram showing the configuration of a power conversion system including a power conversion device according to Embodiment 1. [Figure 2A] This is a diagram showing an example of a converter cell that makes up a power conversion device. [Figure 2B] This is a diagram showing another example of a converter cell that makes up a power conversion device. [Figure 2C] This is a diagram showing another example of a converter cell that makes up a power conversion device. [Figure 3] This is a diagram illustrating the current flowing through a power converter. [Figure 4] This is a functional block diagram showing the configuration of the converter control unit according to Embodiment 1. [Figure 5] This is a block diagram showing the configuration of the total voltage control unit included in the modulation command generation unit. [Figure 6] It is a block diagram showing the configuration of a current control unit included in a modulation command generation unit. [Figure 7] It is a block diagram showing the configuration of a phase balance control unit included in a modulation command generation unit. [Figure 8] It is a block diagram showing the configuration of a positive-negative balance control unit included in a modulation command generation unit. [Figure 9] It is a block diagram showing the configuration of a gate signal switching determination unit included in a converter control unit. [Figure 10] It is a block diagram showing the configuration of a gate signal generation unit included in a converter control unit. [Figure 11] It is a diagram showing a modulation command and a carrier wave of a phase shift PWM method. [Figure 12A] It is a flowchart showing the operation in a gate signal generation unit and is a diagram showing the operation of a 1 pulse / 1 carrier wave cycle signal generation unit. [Figure 12B] It is a flowchart showing the operation in a gate signal generation unit and is a diagram showing the operation of a 1 pulse / 1 carrier wave cycle signal generation unit. [Figure 13A] It is a flowchart showing the operation in a gate signal generation unit and is a diagram showing the operation of a pulse number adjustment unit. [Figure 13B] It is a flowchart showing the operation in a gate signal generation unit and is a diagram showing the operation of a pulse number adjustment unit. [Figure 14A] It is a diagram showing a gate signal generated by a 1 pulse / 1 carrier wave cycle signal generation unit. [Figure 14B] It is a diagram showing a gate signal generated by a pulse number adjustment unit. [Figure 15] It is a functional block diagram showing the configuration of a converter control unit according to Embodiment 2. [Figure 16] It is a block diagram showing the configuration of a gate signal switching determination unit included in a converter control unit according to Embodiment 2. [Figure 17] It is a hardware configuration diagram which is an example of a converter control unit according to Embodiments 1 and 2.

Embodiments for Carrying Out the Invention

[0011] The following description of this embodiment will be made with reference to the figures. In each figure, the same reference numerals indicate the same or corresponding parts.

[0012] Embodiment 1. The power conversion device according to Embodiment 1 will be described below with reference to the figures. In this embodiment 1, the gate signal is switched based on the magnitude of the capacitor voltage of the converter cell. If the capacitor voltage of the converter cell fluctuates greatly, the limit of one gate pulse per carrier cycle is suspended, and the number of pulses is adjusted so that it is below a preset tolerance value.

[0013] <Overall configuration of the power conversion system and configuration of the power conversion device> Figure 1 is a schematic diagram showing the overall configuration of a power conversion system including a power converter according to Embodiment 1. The power converter 100 is connected between the three-phase AC power system 2 and the DC lines 6P and 6N.

[0014] The power converter 100 comprises a power conversion unit 1 and a converter control unit 7. The power conversion unit 1 has arms 9pu, 9pv, 9pw, 9nu, 9nv, and 9nw in each of the U, V, and W phases, between the AC terminals Nu, Nv, Nw connected to the interconnection transformer 3 and the positive-side DC line 6P, and between the AC terminals Nu, Nv, Nw and the negative-side DC line 6N. Hereinafter, each arm will be referred to collectively as arm 9. In addition, in each phase, arms 9pu, 9pv, and 9pw connected between the AC terminals Nu, Nv, Nw and the DC line 6P will be referred to as "positive-side arms," ​​and arms 9nu, 9nv, and 9nw connected between the AC terminals Nu, Nv, Nw and the DC line 6N will be referred to as "negative-side arms." Furthermore, arms 9pu and 9nu are connected via connection point 4u to form a U-phase leg circuit 8u, arms 9pv and 9nv are connected via connection point 4v to form a V-phase leg circuit 8v, and arms 9pw and 9nw are connected via connection point 4w to form a W-phase leg circuit 8w. Each arm 9 is composed of k converter cells 10 (k: a natural number greater than or equal to 2). In this embodiment, the power conversion unit 1 is configured as a three-phase Y-connected MMC.

[0015] Figures 2A, 2B, and 2C show examples of the configuration of the converter cell 10. As shown in Figures 2A and 2B, the converter cell 10 has a configuration in which a capacitor 15 is connected in parallel to a series of self-extinguishing switching elements 12U and 12L, and a diode element 13 is connected in antiparallel (in parallel and in the reverse bias direction) to each of the switching elements 12U and 12L. Here, the self-extinguishing semiconductor switching elements are, for example, IGBTs (Insulated-Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

[0016] Furthermore, as shown in Figure 2C, the converter cell 10 may also be a full-bridge configuration in which two series-connected semiconductor switching elements 12U and 12L, each having diode elements 13 connected in antiparallel, are connected to a capacitor 15 in parallel. Gate signals GU and GL are transmitted to the gates of the semiconductor switching elements 12U and 12L from the gate signal generation unit 90, which will be described later.

[0017] The converter cell 10 is equipped with a capacitor voltage detection unit 16 that detects the voltage of the capacitor 15, and detects the voltage Vcap of each capacitor.

[0018] In addition to the capacitor voltage detection unit 16 located in each converter cell 10, the power conversion unit 1 further includes a reactor 5 located corresponding to each arm 9, an arm current detection unit 20, a DC voltage detection unit 21 located in the positive DC line 6P, and a DC voltage detection unit 22 located in the negative DC line 6N.

[0019] The arm current detection unit 20 detects the arm currents Ipu and Inu passing through the positive side arm 9pu and the negative side arm 9nu of the U phase, respectively; the arm currents Ipv and Inv passing through the positive side arm 9pv and the negative side arm 9nv of the V phase, respectively; and the arm currents Ipw and Inw passing through the positive side arm 9pw and the negative side arm 9nw of the W phase, respectively.

[0020] The DC voltage detection unit 21 detects the DC voltage Vdcp between the positive DC line 6P and the ground. The DC voltage detection unit 22 detects the DC voltage Vdcn between the negative DC line 6N and the ground. Here, the DC voltage Vdcc is expressed by equation (1). Vdcc = (Vdcp - Vdcn) / 2 =Vdc / 2 ···(1) Furthermore, a DC voltage command value Vdcc* is predetermined as the voltage command value of the DC voltage Vdcc applied to each arm 9 of the power converter 100.

[0021] Furthermore, the AC power system 2 is equipped with an AC voltage detection unit 19 and an output current detection unit (AC current detection unit) 11. The three-phase AC system voltages Vu, Vv, Vw detected by the AC voltage detection unit 19 and the three-phase AC system currents Iu, Iv, Iw of the AC power system 2 detected by the output current detection unit 11 are input to the power converter 100.

[0022] <Current flowing through power converter 100> Here, the current flowing through the power converter 100 will be explained using Figure 3. In Figure 3, the current elements are as follows: (a) Ipu, Ipv, Ipw: Currents flowing through the U-phase positive side arm 9pu, the V-phase positive side arm 9pv, and the W-phase positive side arm 9pw. (b) Inu, Inv, Inw: Currents flowing through the U-phase negative side arm 9nu, the V-phase negative side arm 9nv, and the W-phase negative side arm 9nw. (c) Iu: This is the AC current of the U phase that passes through the AC system, and half of this AC system current Iu is divided between the U phase positive electrode side arm 9pu and the U phase negative electrode side arm 9nu. (d) Iv: This is the AC current of the V phase that passes through the AC system, and half of this AC system current Iv is divided between the V phase positive electrode side arm 9pv and the V phase negative electrode side arm 9nv. (e) Iw: This is the alternating current of the W phase that passes through the AC system. Half of this AC system current Iw is divided between the W phase positive electrode arm 9pw and the W phase negative electrode arm 9nw.

[0023] (f) Idc: This is the current that passes through the DC system detected by the current sensor 23, and 1 / 3 of Idc flows through the U-phase arm, V-phase arm, and W-phase arm, respectively. (g) Izu: This is the current component obtained by subtracting the AC system current Iu / 2 that passes through the AC system from the current Ipu and Inu flowing through the U-phase arm, and the following relationships (2) and (3) hold. Izu = Ipu + Iu / 2 ... (2) Izu = Inu - Iu / 2 ... (3) (h) Izuc: This is a circulating current component that does not pass through the AC system or DC system, but circulates between the phases of the leg circuit 8u, 8v, and 8w. If we eliminate the AC system current Iu from equations (2) and (3) above, the current component Izu becomes equation (4) below. Izu = (Ipu + Inu) / 2 ... (4) Therefore, the circulating current component Izuc is given by the following equation (5). Izuc = Izu - Idc / 3...(5)

[0024] Similarly, although not shown in the diagram, the other phases are as follows: (i) Izv: The current component obtained by subtracting the AC power system current Iv / 2 that passes through the AC power system from the current Ipv and Inv flowing through the V-phase arm. (j) Izw: The current component obtained by subtracting the AC power system current Iw / 2 that passes through the AC power system from the current Ipw and Inw flowing through the W phase arm. (k) The circulating current components Izvc and Izwc are given by equations (6) and (7) below. Izvc = Izv - Idc / 3 ... (6) Izwc = Izw - Idc / 3 ... (7)

[0025] <Configuration of Converter Control Unit 7> Next, the configuration of the converter control unit 7 will be described using FIG. 4. FIG. 4 is a functional block diagram showing the configuration of the converter control unit 7. The converter control unit 7 is roughly composed of a modulation command generation unit 70, a gate signal switching determination unit 80, and a gate signal generation unit 90.

[0026] <Configuration of Modulation Command Generation Unit 70> First, the modulation command generation unit 70 will be described. The modulation command generation unit 70 includes a PLL (Phase Locked Loop) unit 400, an all-voltage control unit 200, a current control unit 300, a phase balance control unit 500 for equalizing the capacitor voltages Vcap of each converter cell 10, a positive-negative balance control unit 600, and a voltage command value calculation unit 700.

[0027] <Operation of PLL Unit 400> The PLL unit 400 extracts a phase θ synchronized with the system voltage from the AC system voltages Vu, Vv, Vw of each phase.

[0028] <Configuration of All-Voltage Control Unit 200> FIG. 5 is a block diagram showing the configuration of the all-voltage control unit 200. The all-voltage control unit 200 receives the capacitor voltages Vcap of all (all phases and all arms) of the converter cells 10, the capacitor voltage command values Vcap* for all the converter cells 10 (hereinafter referred to as all-voltage command values Vcap*), and the DC current command value Idc*. When representing the capacitor voltage values ​​of all converter cells 10, Vcap is used as shown in Figures 2A, 2B, and 2C. When representing them individually, as shown in Figure 5, the capacitor voltage of the U-phase positive side arm is Vcappu1···Vcappuk, the capacitor voltage of the U-phase negative side arm is Vcapnu1···Vcapnuk, the capacitor voltage of the V-phase positive side arm is Vcappv1···Vcappvk, the capacitor voltage of the V-phase negative side arm is Vcapnv1···Vcapnvk, the capacitor voltage of the W-phase positive side arm is Vcappw1···Vcappwk, and the capacitor voltage of the U-phase negative side arm is Vcapnw1···Vcapnwk. Individual notation may also be Vcapxxm (xx = pu, nu, pv, nv, pw, nw, m are natural numbers from 1 to k).

[0029] In Figure 5, the first representative value calculation unit 210 of the total voltage control unit 200 calculates the average value Vcap_av of the capacitor voltage Vcap of all converter cells 10. The overall voltage control unit 200 controls the average value Vcap_av of the capacitor voltages Vcap of all converter cells 10 so that it follows a predetermined overall voltage command value Vcap*. The average value Vcap_av of the capacitor voltages Vcap of all converter cells 10 may be a filtered value to suppress sharp fluctuations. Note that the average value Vcap_av of the capacitor voltage Vcap is not limited to the average value of the capacitor voltage Vcap of all converter cells 10. For example, it could be the median, the intermediate value between the maximum and minimum values, or the average value of the capacitor voltage Vcap of any number of converter cells 10.

[0030] Since the difference between AC power and DC power in the power conversion unit 1 becomes the common active power for all converter cells 10, the capacitor voltage Vcap of all converter cells 10 is controlled by the active current Iq. That is, feedback control is performed by a controller 220 such as a PI (Proportional Integral) controller so that the difference between the average value Vcap_av of the capacitor voltage Vcap of all converter cells 10 and the total voltage command value Vcap* becomes 0. Then, the added control amount 230 is added by an adder 240 to the DC current command value Idc* or the DC current detection value Idc detected by the current sensor 23, and the added control amount is output to the current control unit 300 as the active current command value Iq*.

[0031] The average value Vcap_av calculated by the first representative value calculation unit 210 of the total voltage control unit 200 is the average value of the capacitor voltages of all phases and is used as the voltage command value in the phase balance control unit 500 that balances the voltages between phases. Therefore, the average value Vcap_av is explicitly output as the voltage command value Vcap_av* to the phase balance control unit 500 and the gate signal switching determination unit 80. Furthermore, the sum of the capacitor voltages Vcap for each arm (Vcappu, Vcapnu, Vcappv, Vcapnv, Vcappw, Vcapnw) is output to the voltage command value calculation unit 700. Here, the sum of the capacitor voltages Vcap is referred to collectively as Vcapxx.

[0032] <Configuration of the current control unit 300> Figure 6 is a block diagram showing the configuration of the current control unit 300. The current control unit 300 receives the following inputs: a phase θ synchronized with the AC system voltage output by the PLL unit 400, the AC system currents Iu, Iv, and Iw detected by the output current detection unit 11, the active current command value Iq* output from the overall voltage control unit 200, and the reactive current command value Id* determined from the operating conditions of the power conversion unit 1.

[0033] The current control unit 300 controls the power of the power conversion unit 1 by controlling the active current Iq and reactive current Id of the power conversion unit 1. The active current Iq and reactive current Id of the power conversion unit 1 are determined by the 3-phase / 2-phase converter 310 using the following equation (8), based on the AC system currents Iu, Iv, Iw, and the phase θ which is synchronized with the AC system voltage.

number

[0034] The voltage command values ​​Vd* and Vq* on the dq axis are determined by feedback control using controllers 320 and 330 so that the active current Iq follows the active current command value Iq*, and the reactive current Id follows the reactive current command value Id*. Here, controllers 320 and 330 are, for example, PI controllers, similar to controller 220.

[0035] Next, the voltage command values ​​Vd* and Vq* on the dq axis are input to the 2-phase / 3-phase converter 350, and are converted into AC voltage command values ​​Vacu*, Vacp*, and Vacw* for each phase, the U-phase, V-phase, and W-phase, respectively, according to equation (9) below, and output to the voltage command value calculation unit 700. Note that when referring to the AC voltage command values ​​Vacu*, Vacp*, and Vacw* collectively, they are written as AC voltage command value Vac*.

number

[0036] <Configuration of the phase balance control unit 500> Figure 7 is a block diagram showing the configuration of the phase balance control unit 500. The phase balance control unit 500 controls the voltages of each phase (U phase, V phase, W phase) to equalize them. The phase balance control unit 500 receives the capacitor voltage Vcap of all converter cells 10, the arm currents Ipu, Inu, Ipv, Inv, Ipw, and Inw detected by the arm current detection unit 20, the DC current Idc detected by the current sensor 23, the average value (first representative value) Vcap_av* of all capacitor voltages output from the total voltage control unit 200, and the circulating current command value Izpn* (Izpna*, Izpnb) for positive and negative balance output from the positive and negative balance control unit 600, which will be described later.

[0037] The phase balance control unit 500 controls the average values ​​of the capacitor voltages of each phase (U phase, V phase, W phase), Vcapu, Vcapv, and Vcapw, so that they follow the average value of all capacitor voltages, Vcap_av*, output from the total voltage control unit 200.

[0038] The second representative value calculation unit 510 receives the capacitor voltage Vcap of all converter cells 10 as input and calculates the average values ​​Vcapu, Vcapv, and Vcapw of the capacitor voltages of all converter cells 10 in the leg circuits 8u, 8v, and 8w of each phase (U phase, V phase, W phase).

[0039] The average values ​​of the capacitor voltages for each phase, Vcapu, Vcapv, and Vcapw, oscillate at a frequency component that is twice the system frequency. Therefore, filters 511, 512, and 513 remove the frequency component that is twice the system frequency from the average values ​​of the capacitor voltages Vcapu, Vcapv, and Vcapw. Filters 511, 512, and 513 are moving average filters or notch filters, etc., that have a frequency of twice the system frequency.

[0040] Next, the average values ​​of the capacitor voltages of each phase, Vcapu, Vcapv, and Vcapw, are passed through filters 511, 512, and 513 to obtain values ​​Vcapu-, Vcapv-, and Vcapw-. These values ​​Vcapu-, Vcapv-, and Vcapw- are then converted between three phases and two phases by the three-phase / two-phase converter 520 based on the following equation (10) to calculate the control values ​​Vcapa and Vcapb.

number

[0041] Next, controllers 521 and 522 control the system so that the average value Vcap_av* of all capacitor voltages output from the total voltage control unit 200 and the control values ​​Vcapa and Vcapb are both zero, thereby determining the circulating current command values ​​Iza* and Izb* for phase balancing. Controllers 521 and 522 are, for example, PI controllers.

[0042] Next, the circulating current command values ​​Iza* and Izb* for phase balancing are added to the circulating current command values ​​Izpna* and Izpnb* for positive and negative balancing output by the positive and negative balance control unit 600, which will be described later.

[0043] Meanwhile, the circulating current calculation unit 550 of the phase balance control unit 500 receives the arm currents Ipu, Inu, Ipv, Inv, Ipw, Inw, and DC current Idc as inputs, and calculates the circulating currents Izuc, Izvc, and Izwc using the aforementioned equations (5) to (7). The circulating currents Izuc, Izvc, and Izwc calculated by the circulating current calculation unit 550 are input to the 3-phase / 2-phase converter 560, where they are converted between 3-phase and 2-phase based on the following equation (11), and the control values ​​Iza and Izb are output.

number

[0044] Controllers 531 and 532 control the system so that the deviation between the control values ​​Iza and Izb output from the 3-phase / 2-phase converter 560 and the sum of the circulating current command values ​​Iza* and Izb* for phase balancing and the circulating current command values ​​Izpna* and Izpnb* for positive and negative balancing becomes zero, and output values ​​531a and 532a are output. Here, controllers 531 and 532 are, for example, PI controllers.

[0045] The output values ​​531a and 532a are then input to the 2-phase / 3-phase converter 540 and converted into voltage command values ​​VzU*, VzV*, and VzW* for the circulating current. The voltage command values ​​VzU*, VzV*, and VzW* for the circulating current are output to the subsequent voltage command value calculation unit 700. Here, when referring to the voltage command values ​​VzU*, VzV*, and VzW* for the circulating current collectively, they are written as voltage command value Vz* (see Figure 4).

[0046] <Configuration of the positive / negative balance control unit 600> Figure 8 is a block diagram showing the configuration of the positive / negative balance control unit 600. The positive / negative balance control unit 600 controls the voltages of the positive side arm and the negative side arm to equalize them. The positive / negative balance control unit 600 receives the capacitor voltage Vcap of all converter cells 10 as input. The positive / negative balance control unit 600 controls the phase (U phase, V phase, W phase) leg circuits 8u, 8v, 8w so that the capacitor voltage of the positive side arm and the capacitor voltage of the negative side arm are balanced.

[0047] The third representative value calculation unit 610 receives the capacitor voltage value Vcap of all converter cells 10 as input and calculates the average values ​​Vcapup_av, Vcapun_av, Vcapvp_av, Vcapvn_av, Vcapwp_av, and Vcapwn_av of the capacitor voltages of each converter cell 10 on the positive and negative sides of the arms in each phase (U phase, V phase, W phase). Then, it controls the unit so that the difference between the average values ​​Vcapup_av, Vcapvp_av, and Vcapwp_av of the positive side arms and the average values ​​Vcapun_av, Vcapvn_av, and Vcapwn_av of the negative side arms becomes zero for each phase.

[0048] Specifically, as shown in Figure 8, the difference between the average values ​​of the capacitor voltages of the positive side arm (Vcapup_av, Vcapvp_av, Vcapwp_av) and the average values ​​of the capacitor voltages of the negative side arm (Vcapun_av, Vcapvn_av, Vcapwn_av), calculated by the third representative value calculation unit 610, is multiplied by 1 / 2 using a multiplier, and the multiplied values ​​are passed through filters 621, 622, and 623. Since the average values ​​of the capacitor voltages of one side arm (one arm on the positive or negative side), calculated by the third representative value calculation unit 610, contain frequency oscillations at the same frequency as the system frequency and frequency oscillations at twice the system frequency, the values ​​are passed through either a moving average filter with the same frequency as the system frequency (filters 621, 622, and 623), or a notch filter with the same frequency as the system frequency and a notch filter with twice the frequency.

[0049] Then, the values ​​passed through filters 621, 622, and 623 (referred to as the positive and negative balance outputs for each phase) are output by controllers 631, 632, and 633, for example, using PI control. This outputs the magnitude of the current required to equalize the voltage of the positive side arm and the negative side arm of each phase. Here, in order to resolve the imbalance in capacitor voltage between the positive and negative arms, it is necessary to reverse the direction of power flowing into the capacitor (the direction of charging and discharging current) between the positive and negative arms. Since the AC voltages input and output by the power conversion unit 1 have opposite polarity between the positive and negative arms, it is necessary to flow a current of the same polarity 1f (fundamental wave) component in order to charge and discharge the capacitor between the positive and negative arms.

[0050] Specifically, the output values ​​of controllers 631, 632, and 633, which represent the magnitude of the current required to equalize the voltage of the positive and negative arms of each phase, are multiplied by multipliers 651, 652, and 653 by unit sine waves Vuunit, Vvunit, and Vwunit, which are in phase with each phase's AC voltage and have a magnitude of 1. This calculates the AC current of the 1f (fundamental wave) component for each phase, which is necessary to eliminate the imbalance in the capacitor voltage between the positive and negative arms. These AC currents of the 1f (fundamental wave) component for each phase are input to the 3-phase / 2-phase converter 660, where they are converted between 3-phase and 2-phase and output the positive / negative balance circulating current command values ​​Izpna* and Izpnb*.

[0051] On the other hand, the values ​​obtained by passing through filters 621, 622, and 623 (referred to as the positive and negative balance outputs for each phase) are used by controllers 671, 672, and 673 to output AC voltage commands VpnU*, VpnV*, and VpnW* for positive and negative balancing. Specifically, the values ​​obtained by passing through filters 621, 622, and 623 (the positive and negative balanced outputs for each phase) are added together, and then multiplied by 1 / 3 using multiplier 640 to obtain the neutral point voltage Vz. Then, the difference between the positive and negative balanced outputs for each phase and the neutral point voltage Vz is controlled, for example, by controllers 671, 672, and 673 using PI control to output the AC voltage command values ​​for positive and negative balance VpnU*, VpnV*, and VpnW*. Here, when referring to the AC voltage command values ​​for positive and negative balance VpnU*, VpnV*, and VpnW* collectively, they are written as the AC voltage command value for positive and negative balance Vpn* (see Figure 4).

[0052] The positive / negative balance control unit 600 outputs the AC component of each phase as a circulating current command value Izpn* (Izpna*, Izpnb*) and the DC component of each phase as an AC voltage command value Vpn* (VpnU*, VpnV*, VpnW*).

[0053] <Operation of the voltage command value calculation unit 700> The voltage command value calculation unit 700 receives a predetermined DC voltage command value Vdcc*, AC voltage command values ​​Vac* (Vacu*, Vacv*, Vacw*) for each phase output from the current control unit 300, voltage command values ​​Vz* (VzU*, VzV*, VzW*) for circulating current output from the phase balance control unit 500, AC voltage command value Vpn* for positive and negative balance output from the positive and negative balance control unit 600, and the total voltage values ​​Vcappu, Vcapnu, Vcappv, Vcapnv, Vcappw, Vcapnw of the capacitors 15 included in each arm output from the total voltage control unit 200, and calculates the voltage command value Vref for each arm using the following formula (12). Here, the DC voltage command value Vdcc* is a voltage command value equivalent to half the DC terminal voltage Vdc.

[0054] In other words, the voltage command values ​​Vrefpu, Vrefpv, Vrefpw, Vrefnu, Vrefnv, and Vrefnw for the U-phase positive electrode arm, V-phase positive electrode arm, W-phase positive electrode arm, U-phase negative electrode arm, V-phase negative electrode arm, and W-phase negative electrode arm are calculated using the following formula (12). Vrefpu=Vdcc*+VzU*-Vacu*-VpnU* Vrefpv=Vdcc*+VzV*-Vacv*-VpnV* Vrefpw=Vdcc*+VzW*-Vacw*-VpnW* Vrefnu=Vdcc*+VzU*+Vacu*+VpnU* Vrefnv=Vdcc*+VzV*+Vacv*+VpnV* Vrefnw=Vdcc*+VzW*+Vacw*+VpnW* ...Equation (12)

[0055] The voltage command values ​​Vrefpu, Vrefpv, Vrefpw, Vrefnu, Vrefnv, and Vrefnw of the U-phase positive side arm, V-phase positive side arm, W-phase positive side arm, U-phase negative side arm, V-phase negative side arm, and W-phase negative side arm, calculated using equation (12), are used to obtain the sum of the voltages of the capacitors 15 included in each arm, Vcappu. ,V cappv ,V cappw, Vcapnu, Vcapnv, By dividing each arm by Vcapnw, the following arm modulation commands Krefpu, Krefpv, Krefpw, Krefnu, Krefnv, and Krefnw are generated for the U-phase positive arm, V-phase positive arm, W-phase positive arm, U-phase negative arm, V-phase negative arm, and W-phase negative arm, respectively. When referring to the arm modulation commands collectively, they are written as arm modulation command Kref.

[0056] The modulation command generation unit 70 outputs the arm modulation command Kref (Krefpu, Krefpv, Krefpw, Krefnu, Krefnv, Krefnw), which is the calculation result of the voltage command value calculation unit 700, to the gate signal generation unit 90. In the gate signal generation unit 90, the gate signals GU.GL of the semiconductor switching elements of each converter cell 10 are determined by comparing the arm modulation command Kref with the carrier wave.

[0057] <Configuration and operation of the gate signal switching determination unit 80> Next, the gate signal switching determination unit 80 according to this embodiment 1 will be described. The gate signal switching determination unit 80 determines that if the capacitor voltage of at least one converter cell 10 falls outside the specified range during steady operation of the power converter 100, it will not generate a gate signal at a rate of 1 pulse per carrier period (hereinafter referred to as "1 pulse / 1 carrier period"), but will instead adjust the number of pulses within one carrier period to operate the device.

[0058] The configuration and operation of the gate signal switching determination unit 80 will be explained below with reference to the diagrams. Figure 9 is a block diagram showing the configuration of the gate signal switching determination unit 80. The gate signal switching determination unit 80 receives the AC system voltages Vu, Vv, and Vw detected by the AC voltage detection unit 19, the average value of the capacitor voltages of all converter cells 10, Vcap_av*, output from the all-voltage control unit 200, and the capacitor voltage Vcapxxm of all converter cells 10 as inputs.

[0059] Each AC system voltage Vu, Vv, and Vw is compared with a pre-set upper limit of system voltage Vacmax by comparator 81a. If it is less than the upper limit of system voltage Vacmax, comparator 81a outputs 1. Similarly, each AC system voltage Vu, Vv, and Vw are compared with a pre-set lower limit of system voltage Vacmin by comparator 81b. If each AC system voltage Vu, Vv, and Vw is greater than or equal to the lower limit of system voltage Vacmin, comparator 81b outputs 1. Therefore, if all AC system voltages Vu, Vv, and Vw are within the upper and lower limits of system voltage, the logical AND circuit (hereinafter referred to as AND circuit) 82a outputs 1. Here, for example, by setting the upper limit of system voltage Vacmax to 1.1pu and the lower limit of system voltage Vacmin to 0.9pu, it is determined that the AC system voltages Vu, Vv, and Vw are within the steady-state range.

[0060] Furthermore, the average value of the capacitor voltage Vcap_av* is compared with a pre-set upper limit of the average capacitor voltage Vcap_avmax using comparator 81c. If Vcap_av* is less than the pre-set upper limit of the average capacitor voltage Vcap_avmax, comparator 81c outputs 1. Also, comparator 81d compares the average value of the capacitor voltage Vcap_av* with a lower limit of the average capacitor voltage Vcap_avmin. If Vcap_av* is greater than or equal to the lower limit of the average capacitor voltage Vcap_avmin, comparator 81d outputs 1. Therefore, if the average values ​​of all capacitor voltages Vcap_av* are greater than or equal to the lower limit of the average capacitor voltage Vcap_avmin and less than the upper limit of the average capacitor voltage Vcap_avmax, the AND circuit 82b outputs 1. Here, for example, by setting the upper limit of the average capacitor voltage Vcap_avmax to 1.05pu and the lower limit of the average capacitor voltage Vcap_avmin to 0.95pu, it is determined that the average value of the capacitor voltage Vcap_av* is within the steady-state range and that the power converter 100 is in a state where it can output the desired voltage.

[0061] The AND circuit 82c outputs 1 when both the AC system voltages Vu, Vv, Vw and the average value of the capacitor voltage Vcap_av* are within the steady-state range. In other words, the AND circuit 82c outputs 1 when the power converter 100 is operating in a steady state.

[0062] Furthermore, when the gate signal switching determination unit 80 receives the capacitor voltages Vcap (Vcapxx1 to Vcapxxk) of all converter cells as input, the maximum and minimum value extraction unit 85 calculates the maximum value Vcapmax and the minimum value Vcapmin of the capacitor voltages of all converter cells. In Figure 9, the maximum and minimum value extraction unit 85 is referred to as the maximum / minimum value extraction unit 85.

[0063] Comparator 81e compares the maximum capacitor voltage Vcapmax and the allowable maximum Val_max (e.g., 1.2pu) of all converter cells. Comparator 81e outputs 1 if the maximum capacitor voltage Vcapmax exceeds the allowable maximum Val_max. Furthermore, comparator 81f outputs 1 if the minimum capacitor voltage Vcapmin is less than or equal to the allowable minimum Val_min (e.g., 0.8pu). The outputs of comparators 81e and 81f are input to a logical OR circuit (hereinafter referred to as OR circuit) 83, and OR circuit 83 outputs 1 if at least one capacitor voltage is outside the allowable range.

[0064] Then, when both the AND circuit 82c and the OR circuit 83 output 1, the AND circuit 82d sets the gate switching signal CarFlag to 1. In other words, the gate switching signal CarFlag is set to 1 when at least one capacitor voltage falls outside the acceptable range during steady-state operation.

[0065] <Configuration and operation of the gate signal generation unit 90> Next, the gate signal generation unit 90 will be described. The gate signal generation unit 90 selectively performs one of the following actions depending on the value of the gate switching signal CarFlag output by the gate signal switching determination unit 80: limit the number of gate signal pulses to once within one carrier period or adjust it to a value below an acceptable value exceeding one.

[0066] The configuration and operation of the gate signal generation unit 90 will be explained below with reference to the diagram. Figure 10 is a block diagram showing the configuration of the gate signal generation unit 90. The carrier wave generator 91 receives the initial value of the carrier wave phase Carθ, the carrier wave frequency Freqc, and the number SMID which identifies each converter cell, and generates a triangular wave carrier CARR corresponding to all converter cells. It also outputs Cslope, which represents the slope of the triangular wave carrier CARR, to the 1-pulse / 1-carrier period signal generation unit 99. The 1-pulse / 1-carrier period signal generation unit 99 is a signal generation unit that generates a gate signal of one square wave (pulse) during one carrier period.

[0067] In the carrier generator 91, if each arm has k transducer cells 10, then k triangular wave carriers are required, and the phase difference φcr between two adjacent carriers is given by equation (13). φcr [rad.] = 2π / k···(13)

[0068] Figure 11 shows the relationship between the arm modulation command Kref and the carrier wave in a phase-shifted PWM method. In Figure 11, the solid curve represents the arm modulation command Kref, and the dashed, short dashed, and long dashed lines represent the carrier waves of the first, second, and kth converter cells, respectively. For example, if the phase of the carrier wave of the first converter cell on the U-phase positive electrode side arm is Carθ, then the phase of the carrier wave of the second converter cell is set to Carθ+2π / k, and the phase of the carrier wave of the third converter cell is set to Carθ+2×2π / k. Carrier waves are generated and compared with the arm modulation command Kref.

[0069] Furthermore, by setting the initial phase value Carθ of the carrier wave for each arm to differ by an equal 60 degrees for each arm, all switching elements in the circuit are made to switch uniformly throughout the entire output fundamental wave period. If we set the initial value of the carrier wave phase Carθ of the U-phase positive electrode side arm to 0, The initial value of the carrier wave phase Carθ of the V-phase positive electrode side arm is 60 degrees. The initial phase value Carθ of the carrier wave on the W-phase positive electrode side arm is 120 degrees. The initial value of the carrier wave phase Carθ of the U-phase negative electrode arm is set to 180 degrees. The initial value of the carrier wave phase Carθ of the V-phase negative side arm is 240 degrees. The initial value of the carrier wave phase Carθ of the W-phase negative pole arm is set to 300 degrees.

[0070] Next, the comparator 93 compares the magnitude of the arm modulation command Kref with that of the carrier wave for each converter cell. The comparator 93 outputs 1 to G1 if Kref-CARR ≥ 0, and outputs 0 to G1 of the selector 95 if Kref-CARR < 0.

[0071] Next, the gate signals GU and GL of the switching elements 12U and 12L are determined by selecting either the 1-pulse / 1-carrier period signal generation unit 99 or the pulse number adjustment unit 97 based on the value of the gate switching signal CarFlag output from the gate signal switching determination unit 80 using the selector 95. When the gate switching signal CarFlag is 0, that is, when the capacitor voltage of all converter cells is within the acceptable range during steady-state operation, the 1-pulse / 1-carrier period signal generation unit 99 is selected.

[0072] <Operation of the 1-pulse / 1-carrier period signal generation unit 99> The operation of the 1-pulse / 1-carrier period signal generation unit 99 will be explained below using the flowcharts in Figures 12A and 12B. In Embodiment 1, a low-frequency Freqc carrier wave is used, and low-frequency Freqc is generally less than twice the system frequency. In step S101, PrevG1 is initialized to 0. PrevG1 is the value of G1 one analysis time point prior. If there is input data in step S102, proceed to step S103 (yes in step S102). If there is no input data, terminate (no in step S102).

[0073] In step S103, the G1 output from the comparator 93 and the carrier wave slope Cslope output from the carrier wave generator 91 are input. In step S104, determine whether G1 is 1 or not. If G1 is 1 (yes in step S104), proceed to step S105. In step S105, if PrevG1 is 0 and the carrier slope Cslope is negative (yes in step S105), proceed to step S106. In step S106, the value of G1 is set for the gate signal Gate, and the process proceeds to step S111.

[0074] In step S105, if PrevG1 is 1, or if the carrier slope Cslope is positive (no in step S105), proceed to step S107. In step S107, the value of PrevG1 is set to the gate signal Gate. That is, the value of G1 from one analysis time point prior is maintained, and the process proceeds to step S111.

[0075] If G1 is 0 in step S104 (no in step S104), proceed to step S108. In step S108, if PrevG1 is 1 and the carrier slope Cslope is positive (yes in step S108), proceed to step S109. In step S109, the value of G1 is set for the gate signal Gate, and the process proceeds to step S111.

[0076] In step S108, if PrevG1 is 0 or the carrier slope Cslope is negative (no in step S108), proceed to step S110. In step S110, the value of PrevG1 is set to the gate signal Gate. That is, the value of G1 from one analysis time point prior is maintained, and the process proceeds to step S111.

[0077] In step S111, the gate signals GU and GL of switching elements 12U and 12L are determined based on the gate signal Gate. Specifically, in step S111, if the value of the gate signal Gate one analysis time point prior is 0 and changes from 0 to 1, the gate signal GL of switching element 12L is set to OFF, and the gate signal GU of switching element 12U is set to ON with a delay of the dead time. On the other hand, in step S111, if the value of Gate one analysis time point prior is 1 and changes from 1 to 0, the gate signal GU of switching element 12U is set to OFF, and the gate signal GL of switching element 12L is set to ON with a delay of the dead time. Thus, the change in the gate signal Gate between 0 and 1 corresponds to the switching of the gate signals GU and GL of switching elements 12U and 12L between ON and OFF.

[0078] Then, proceed to step S112 and set PrevG1 to the current Gate value. Steps S102 to S112 are repeated to determine the gate signals GU and GL of the switching elements 12U and 12L, and then the switching elements 12U and 12L are switched.

[0079] Figure 14A shows the relationship between the arm modulation command Kref, the carrier CARR, and the gate signal Gate when the gate switching signal CarFlag is 0 and the 1-pulse / 1-carrier period signal generation unit 99 is selected, i.e., when the flow in Figures 12A and 12B is applied. In Figures 14A and 14B, the arm modulation command Kref is shown by a solid line, the carrier CARR by a dashed line, and the gate signal Gate by a dotted line. As shown in Figure 14A, within one cycle of the carrier wave CARR (each of the intervals a1 and a2), there are two instances where the gate signal Gate changes from 0 to 1 or from 1 to 0. In other words, within one cycle of the carrier wave CARR, the power converter 100 operates with one pulse (one square wave). Therefore, if the capacitor voltage Vcap of all converter cells is within the acceptable range, the gate signal can be switched once per carrier cycle, allowing for operation with low switching losses.

[0080] <Operation of pulse rate adjustment unit 97> In the selector 95, if the gate switching signal CarFlag output from the gate signal switching determination unit 80 is 1, that is, if the capacitor voltage of at least one converter cell 10 falls outside the acceptable range during steady-state operation, the pulse number adjustment unit 97 is selected. The operation of the pulse count adjustment unit 97 will be explained below using the flowcharts in Figures 13A and 13B.

[0081] In step S201, PrevG1 is initialized to 0 and PRECARR to 0. PrevG1 is the value of G1 one analysis time point prior. PRECARR is the value of the carrier CARR one analysis time point prior. If there is input data in step S202, proceed to step S203 (yes in step S202). If there is no input data, terminate (no in step S202).

[0082] In step S203, the G1 output from the comparator 93, the carrier CARR output from the carrier generator 91, and the preset gate pulse limit GCMAX are input. In step S204, if the carrier value PRECARR from one analysis time point is less than 0.5pu and the carrier CARR is 0.5pu or greater (yes in step S204), that is, immediately after the carrier value passes 0.5pu while rising, the process proceeds to step S205, and GCCount is initialized to 0. Here, GCCount is the number of times the gate signal Gate has changed. In other words, two changes in the gate signal Gate constitute one pulse. If the answer in step S204 is "no", proceed to step S206.

[0083] In step S206, determine whether G1 is 1 or not. If G1 is 1 (yes in step S206), proceed to step S207. In step S207, it is determined whether PrevG1 is 0 or not. If PrevG1 is 0 (yes in step S207), proceed to step S208.

[0084] In step S208, if the number of times the gate signal Gate has changed (GCCount) is less than or equal to twice the upper limit of the number of gate pulses (GCMAX) (yes in step S208), proceed to step S209. In step S209, the value of G1 is set for the gate signal Gate, and the process proceeds to step S210. In step S210, the number of times the gate signal Gate has changed is increased by 1, and the process proceeds to step S217.

[0085] If PrevG1 is 1 in step S207 (no in step S207), proceed to step S211. In step S211, the value of PrevG1 is set to the gate signal Gate. That is, the value of G1 from one analysis time point prior is maintained, and the process proceeds to step S217.

[0086] If G1 is 0 in step S206 (no in step S206), proceed to step S212. In step S212, it is determined whether PrevG1 is 1 or not. If PrevG1 is 1 (yes in step S212), proceed to step S213.

[0087] In step S213, if the number of times the Gate has changed (GCCount) is less than or equal to twice the upper limit of the number of gate pulses (GCMAX) (yes in step S213), proceed to step S214. In step S214, the value of G1 is set for the gate signal Gate, and the process proceeds to step S215. In step S215, the number of times the gate signal Gate has changed is increased by 1, and the process proceeds to step S217.

[0088] If PrevG1 is 0 in step S212 (no in step S212), proceed to step S216. In step S216, the value of PrevG1 is set to the gate signal Gate. That is, the value of G1 from one analysis time point prior is maintained, and the process proceeds to step S217.

[0089] Step S217In this step, the gate signals GU and GL of the switching elements 12U and 12L are determined based on the gate signal Gate. Specifically, in step S217, if the value of Gate one analysis time before was 0 and changes from 0 to 1, the gate signal GL of the switching element 12L is set to OFF, and the gate signal GU of the switching element 12U is set to ON with a delay of the dead time. On the other hand, in step S217, if the value of Gate one analysis time before was 1 and changes from 1 to 0, the gate signal GU of the switching element 12U is set to OFF, and the gate signal GL of the switching element 12L is set to ON with a delay of the dead time.

[0090] Then, proceed to step S218 and set PrevG1 to the current Gate value. Steps S202 to S218 are repeated to determine the gate signals GU and GL of the switching elements 12U and 12L, and then the switching elements 12U and 12L are switched.

[0091] Figure 14B shows the relationship between the arm modulation command Kref, carrier wave CARR, and Gate when the gate switching signal CarFlag is 1 and the pulse count adjustment unit 97 is selected, i.e., when the flow in Figures 13A and 13B is applied. As shown in Figure 14B, within one cycle of the carrier wave (section b1), there are two points where the Gate changes from 0 to 1 or from 1 to 0. In other words, within one cycle of the carrier wave CARR, the power converter 100 operates with one pulse (one square wave). On the other hand, during the subsequent carrier wave cycle (section b2), there are four points where the Gate changes from 0 to 1 or from 1 to 0. In other words, the power converter 100 operates with 2 pulses (2 square waves) within the cycle of the carrier wave CARR.

[0092] Therefore, in the pulse count adjustment unit 97, the arm modulation command Kref and Gate intersect three or more times within one cycle of the carrier wave, which increases the number of gate pulses and thus increases switching loss. However, increasing the number of gate pulses has the effect of improving the tracking of the output voltage to the arm modulation command Kref. Therefore, by limiting the number of gate signal changes by the gate pulse count upper limit GCMAX, the overall increase in switching loss can be suppressed.

[0093] In the example shown in Figure 14B, the gate signal Gate changed at most twice (2 pulses) during one period of the carrier wave CARR. However, if the rate of change of the arm modulation command Kref is similar to the rate of change of the carrier wave CARR, chattering of 3 or more pulses may occur. Therefore, to avoid increasing the number of gate pulses unnecessarily, it is best to set the upper limit of the number of gate pulses, GCMAX, to around 3 pulses (6 changes in the gate signal Gate).

[0094] When the upper limit of the gate pulse count, GCMAX, is set to 3 pulses, the number of switching cycles increases only where switching is necessary, and this number is at most 6. Therefore, operation can be continued at a lower frequency than if the carrier frequency were to be operated steadily at three times the system frequency. As a result, the frequency is suppressed, and the increase in switching losses due to frequency increases can be suppressed. Furthermore, the upper limit of the gate pulse count, GCMAX, is not limited to 3 pulses (6 gate changes). It may be determined to an optimal value depending on the capacitor capacity of the converter cell 10, the carrier frequency, etc.

[0095] As described above, according to the power converter according to this embodiment 1, in a phase-shift PWM type MMC, the control unit that drives each semiconductor switching element of a converter cell having a series unit in which a plurality of semiconductor switching elements are connected in series and a capacitor connected in parallel to this series unit comprises: a modulation command generation unit that calculates arm modulation commands for each of the plurality of positive and negative arms based on the command values ​​of the voltages output by the plurality of positive and negative arms; a gate signal generation unit that generates a gate signal for driving the plurality of semiconductor switching elements by comparing the calculated arm modulation command with the carrier wave; and a gate signal switching determination unit that determines whether or not to switch the number of on / off changes of the gate signal per cycle of the carrier wave with respect to the frequency of the carrier wave. The gate signal generation unit generates the gate signal based on the determination result of the gate signal switching determination unit. Therefore, when the result of the gate signal switching determination unit is "switch", the number of on / off changes of the gate signal increases, so there is no need to operate the power converter by steadily increasing the frequency of the carrier wave. As a result, the continuity of operation can be improved and the increase in switching loss can be suppressed.

[0096] Furthermore, during operation at the set carrier frequency, if the capacitor voltage of at least one converter cell falls outside the acceptable range, the gate signal switching determination unit selects the pulse count adjustment unit 97 to switch the semiconductor switching element at or below the gate pulse count upper limit GCMAX. This improves operational continuity and suppresses the increase in switching losses without increasing the carrier frequency.

[0097] Embodiment 2. The power conversion device according to Embodiment 2 will be described below with reference to the figures. In Embodiment 1, an example was described in which there is only one carrier wave CARR frequency for driving the switching elements 12U and 12L of the power converter 100. In Embodiment 2, an example is described in which a power converter is operated in which the switching elements are switched by switching between two or more carrier waves.

[0098] FIG. 15 is a configuration diagram of the converter control unit 7 according to Embodiment 2. The gate signal switching determination unit 80a is different from that in Embodiment 1. The other configurations are the same as those in Embodiment 1 including the power conversion system, and the description of the configuration and operation is omitted, and the description will focus on the differences.

[0099] In FIG. 15, at least two types of carrier frequencies Freqc1 and Freqc2 (Freqc1 < Freqc2) with different frequencies, the value Vcap_av* of the average value of the total capacitor voltage output from the total voltage control unit 200, and the AC system voltages Vv, Vu, and Vw are input to the gate signal switching determination unit 80a according to Embodiment 2.

[0100] <Configuration and Operation of Gate Signal Switching Determination Unit 80a> When the carrier frequency is lower than a preset frequency during the steady operation of the power conversion device 100, the gate signal switching determination unit 80a according to Embodiment 2 does not generate a gate signal with 1 pulse per carrier period, but makes a determination to switch to adjusting the number of pulses within one carrier period for operation.

[0101] Hereinafter, the configuration and operation of the gate signal switching determination unit 80a will be described with reference to the drawings. FIG. 16 is a block diagram showing the configuration of the gate signal switching determination unit 80a according to Embodiment 2. The AC system voltages Vu, Vv, and Vw detected by the AC voltage detection unit 19, the value Vcap_av* of the average value of the capacitor voltages of all converter cells output from the total voltage control unit 200, and the carrier frequencies Freqc1 and Freqc2 are input to the gate signal switching determination unit 80a.

[0102] The operation from comparator 81a to AND circuit 82c is the same as in Figure 9 of Embodiment 1. That is, each AC system voltage Vu, Vv, Vw is compared with a preset upper limit of system voltage Vacmax by comparator 81a, and if it is less than the upper limit of system voltage Vacmax, comparator 81a outputs 1. Also, each AC system voltage Vu, Vv, Vw is compared with a preset lower limit of system voltage Vacmin by comparator 81b, and if each AC system voltage Vu, Vv, Vw is greater than or equal to the lower limit of system voltage Vacmin, comparator 81b outputs 1. Therefore, if all AC system voltages Vu, Vv, Vw are within the upper and lower limits of system voltage, AND circuit 82a outputs 1. Here, for example, by setting the upper limit of system voltage Vacmax to 1.1pu and the lower limit of system voltage Vacmin to 0.9pu, it is determined that the AC system voltages Vu, Vv, Vw are within the steady-state range.

[0103] Furthermore, the average value of the capacitor voltage Vcap_av* is compared with a pre-set upper limit of the average capacitor voltage Vcap_avmax using comparator 81c. If Vcap_av* is less than the pre-set upper limit of the average capacitor voltage Vcap_avmax, comparator 81c outputs 1. Also, comparator 81d compares the average value of the capacitor voltage Vcap_av* with a lower limit of the average capacitor voltage Vcap_avmin. If Vcap_av* is greater than or equal to the lower limit of the average capacitor voltage Vcap_avmin, comparator 81d outputs 1. Therefore, if the average values ​​of all capacitor voltages Vcap_av* are greater than or equal to the lower limit of the average capacitor voltage Vcap_avmin and less than the upper limit of the average capacitor voltage Vcap_avmax, the AND circuit 82b outputs 1. Here, for example, by setting the upper limit of the average capacitor voltage Vcap_avmax to 1.05pu and the lower limit of the average capacitor voltage Vcap_avmin to 0.95pu, it is determined that the average value of the capacitor voltage Vcap_av* is within the steady-state range and that the power converter 100 is in a state where it can output the desired voltage.

[0104] The AND circuit 82c outputs 1 when both the AC system voltages Vu, Vv, Vw and the average value of the capacitor voltage Vcap_av* are within the steady-state range. In other words, the AND circuit 82c outputs 1 when the power converter 100 is operating in a steady state.

[0105] Further, two types of carrier frequencies Freqc1 and Freqc2 used for the carrier wave CARR for driving the switching elements 12U and 12L of the power conversion device 100 are input to the gate signal switching determination unit 80a, and the carrier frequency Freqc1 or the carrier frequency Freqc2 and a preset carrier frequency lower limit value Cfmin are compared by the comparator 86. When the compared carrier frequency (Freqc1 or Freqc2) is less than the carrier frequency lower limit value Cfmin, the comparator 86 outputs 1. Here, the carrier frequency lower limit value Cfmin is set to a frequency at which the operation can continue even with respect to fluctuations in the capacitor voltage, for example, if it is above this frequency. Therefore, it is a value appropriately set according to the capacitance of the capacitor and the like.

[0106] When both the AND circuit 82c and the comparator 86 output 1, the AND circuit 82d sets the gate switching signal CarFlag to 1. That is, when the carrier frequency is low during steady operation, the gate switching signal CarFlag is set to 1. The gate switching signal CarFlag output from the gate signal switching determination unit 80a is input to the selector 95 of the gate signal generation unit 90 shown in FIG. 10, and the gate signal Gate is generated based on the flowcharts shown in FIGS. 12A, 12B, FIGS. 13A, 13B.

[0107] Specifically, in the second embodiment, the frequency relationship is assumed to be Freqc1 < Cfmin ≤ Freqc2. When the power conversion device 100 is in steady operation, in the case of the carrier frequency Freqc2, since the gate switching signal CarFlag is output as 0 to the gate signal generation unit 90, in the 1 pulse / 1 carrier period signal generation unit 99, a gate signal of 1 pulse per carrier period is generated. On the other hand, in the case of the carrier frequency Freqc1, since the gate switching signal CarFlag is output as 1 to the gate signal generation unit 90, a gate signal with more than 1 pulse per carrier period and not exceeding the pulse number upper limit value GCMAX is generated by the pulse number adjustment unit 97.

[0108] The low-frequency carrier frequency Freqc1 is generally less than twice the system frequency, while the high-frequency carrier frequency Freqc2 is generally more than twice the system frequency. Therefore, the lower limit of the carrier frequency Cfmin should be set to a value close to twice the system frequency. However, it is not limited to this value, and should be set appropriately according to the operating conditions of the power converter 100 or the capacitance of the capacitor mentioned above.

[0109] Furthermore, in the case of carrier frequency Freqc1, the pulse count adjustment unit 97 generates a gate signal that is less than or equal to the upper limit of the pulse count GCMAX. However, it is desirable to set the upper limit of the pulse count GCMAX in this case so as not to exceed the number of pulses of carrier frequency Freqc2. In other words, when converted to the number of pulses per unit time, even in the case of carrier frequency Freqc1, it should be set so as not to exceed the number of pulses of carrier frequency Freqc2.

[0110] Although I have explained using two examples of carrier frequencies, it is not limited to just two. If there are three or more types, the carrier frequency should be set so that it is below the predetermined lower limit of the carrier frequency Cfmin, or the number of pulses should be set so that the lowest frequency carrier does not exceed the number of pulses per unit time of the highest frequency carrier.

[0111] As described above, according to the power converter of Embodiment 2, in a power converter that operates with two or more carrier frequencies, when operating with a low-frequency carrier below a preset lower limit of carrier frequency Cfmin, the upper limit of the number of pulses per unit time is set to GCMAX so as not to exceed the number of pulses per unit time for the highest-frequency carrier, and the gate signal is generated accordingly. This improves the continuity of operation even with low-frequency carriers and suppresses the increase in switching losses as a power converter.

[0112] Figure 17 shows an example of the hardware configuration of the converter control unit 7 in the embodiments 1 and 2 described above. As shown in Figure 17, the converter control unit 7 includes, for example, a processor 1000 and a storage device 1100 as processing circuits. The processor 1000 may include a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), an IC (Integrated Circuit), an FPGA (Field Programmable Gate Array), various logic circuits, and various signal processing circuits. Furthermore, the processor 1000 may consist of multiple processors of the same or different types, each performing a portion of the processing. The storage device 1100 may include a RAM (Random Access Memory) configured to read and write data from the processor 1000, and a ROM (Read Only Memory) configured to read data from the processor 1000. The processor 1000 executes programs input from the storage device 1100, such as the ROM.

[0113] Furthermore, if the gate signal generation unit 90 shown in Figures 4 and 15 is not provided in the converter control unit 7 but is included in each converter cell 10, the hardware configuration may be as shown in Figure 17.

[0114] <Other embodiments> (1) In Figures 2A to 2C, the switching elements 12U and 12L constituting the converter cell 10 were explained using IGBTs with diodes connected in antiparallel as an example, but as mentioned above, MOSFETs may also be used. However, IGBTs are more effective than MOSFETs.

[0115] (2) The semiconductor switching element is not limited to one composed of a Si (silicon) semiconductor, but may also be a wide-bandgap semiconductor such as SiC (silicon carbide) or GaN (gallium nitride). Wide-bandgap semiconductors are suitable for application to MMCs due to their characteristics such as enabling faster switching, high-temperature operation, and high dielectric breakdown field strength.

[0116] While this disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but are applicable individually or in various combinations to the embodiments. Accordingly, countless variations not illustrated are conceivable within the scope of the technology disclosed herein. These include, for example, modifications, additions, or omissions of at least one component, as well as the extraction of at least one component and its combination with components of other embodiments. [Explanation of Symbols]

[0117] 1: Power conversion unit, 2: AC power system, 3: Interconnection transformer, 4u, 4v, 4w: Connection point, 5: Reactor, 6P, 6N: DC line, 7: Converter control unit, 8u, 8v, 8w: Reg circuit, 9: Arm, 10 Converter cell, 11: Output current detection unit (AC current detection unit), 12U, 12L: Switching element, 13: Diode element, 15: Capacitor, 16: Voltage detection unit, 19: AC voltage detection unit, 20 Arm current detection unit, 21, 22: DC voltage detection unit, 23: Current sensor, 70: Modulation command generation unit, 80, 80a: Gate signal switching determination unit, 81a, 81b, 81c, 81d, 81e, 81f, 86, 93: Comparator, 82a, 82b, 82c, 82d: AND circuits, 83: OR circuits, 85: Maximum and minimum value extraction unit, 90: Gate signal generation unit, 91: Carrier wave generator, 95: Selector, 97: Pulse count adjustment unit, 99: 1 pulse / 1 carrier period signal generation unit, 100: Power converter, 200: Total voltage control unit, 210: First representative value calculation unit, 220, 320, 330, 521, 522, 531, 532, 631, 632, 633, 671, 672, 673: Controllers, 240: Adder, 300: Current control unit, 310, 520, 560, 660: 3-phase / 2-phase converters, 350, 540: 2-phase / 3-phase converters, 400: PLL unit, 500: Phase balance control unit, 510: Second representative value calculation unit, 511, 512, 513, 621, 622, 623: Filters, 550: Circulating current calculation unit, 600: Positive / negative balance control unit, 610: Third representative value calculation unit, 640, 651, 652, 653: Multipliers, 1000: Processor, 1100: Memory device.

Claims

1. A power conversion device comprising a power conversion unit that performs power conversion between AC and DC, and a control unit that controls the power conversion unit, wherein multiple leg circuits are provided, each having a positive-side arm and a negative-side arm corresponding to multiple phases connected in series, and the connection point of these leg circuits is connected to each phase AC line, and these leg circuits are connected in parallel between positive and negative DC lines, and the power conversion device comprises a power conversion unit that performs power conversion between AC and DC, and a control unit that controls the power conversion unit, Each of the positive and negative electrodes has one or more converter cells connected in series, each cell having a series unit in which a plurality of semiconductor switching elements are connected in series and a capacitor connected in parallel to this series unit. The control unit, A modulation command generation unit calculates an arm modulation command for each of the multiple positive-side arms and the negative-side arms based on the voltage command values ​​output by the multiple positive-side arms and the negative-side arms, A gate signal generation unit compares the calculated arm modulation command with the carrier wave to generate a gate signal for driving a plurality of semiconductor switching elements, The system includes a gate signal switching determination unit that determines whether or not to switch the number of times the gate signal is switched on or off per cycle of the carrier wave, with respect to the frequency of the carrier wave. The gate signal switching determination unit determines whether to switch the number of times the gate signal is turned on or off per cycle of the carrier wave if the voltage of the capacitor exceeds a preset voltage range. When the number of on / off changes of the gate signal is considered to be two for one pulse, the gate signal generation unit selectively performs one of the following based on the result of the gate signal switching determination unit: limit the number of gate signal pulses to once within one cycle of the carrier wave, or adjust it to a number greater than one that is below a preset allowable number. A power converter that generates the aforementioned gate signal.

2. A power conversion device comprising a power conversion unit that performs power conversion between AC and DC, wherein a plurality of leg circuits are provided in parallel between positive and negative DC lines, each having a positive-side arm and a negative-side arm corresponding to a plurality of phases connected in series, and the connection point of the leg circuits is connected to each phase AC line, and the power conversion unit that controls the power conversion unit, Each of the positive and negative electrodes has one or more converter cells connected in series, each cell having a series unit in which a plurality of semiconductor switching elements are connected in series and a capacitor connected in parallel to this series unit. The control unit, A modulation command generation unit calculates an arm modulation command for each of the multiple positive-side arms and the multiple negative-side arms based on the command values ​​of the voltages output by the multiple positive-side arms and the multiple negative-side arms, A gate signal generation unit compares the calculated arm modulation command with the carrier wave to generate a gate signal for driving a plurality of semiconductor switching elements, The system includes a gate signal switching determination unit that determines whether or not to switch the number of times the gate signal is switched on or off per cycle of the carrier wave, with respect to the frequency of the carrier wave. The carrier wave has at least two frequencies, and the gate signal switching determination unit determines whether to switch the number of times the gate signal is turned on or off per cycle of the carrier wave when the carrier wave is operating at a preset lower limit of the carrier wave frequency. When the number of times the gate signal is switched on and off is considered to be two, the gate signal generation unit adjusts the number of pulses of the gate signal to be greater than 1 and less than or equal to a preset allowable number within one cycle of the carrier wave, based on the result of the gate signal switching determination unit. A power converter that generates the aforementioned gate signal.

3. The power conversion device according to claim 2, wherein the gate signal generation unit adjusts the number of times the gate signal is switched on and off per unit time for the carrier with the lowest frequency among the carriers to be less than or equal to the number of times the gate signal is switched on and off per unit time for the carrier with the highest frequency among the carriers.

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