Semiconductor wafer inspection apparatus, semiconductor wafer inspection method, and recording medium

Abstract

The present invention provides a semiconductor wafer inspection apparatus, a semiconductor wafer inspection method, and a recording medium that can reduce the total number of contacts, thereby lowering inspection time and manufacturing costs. [Solution] The semiconductor wafer SW inspection apparatus 1 includes a contact position determination unit that determines which semiconductor chips to contact with N measurement sites among a plurality of semiconductor chips. If there are no semiconductor chips among the N semiconductor chips that have been inspected that are determined to be defective, the contact position determination unit determines that the next semiconductor chip to be contacted should be shifted by N in the first direction. If there are semiconductor chips among the N semiconductor chips that have been inspected that are determined to be defective, the contact position determination unit determines that the next semiconductor chip to be contacted should be such that the semiconductor chip located furthest to the second direction among the defective semiconductor chips makes contact with the N measurement sites located furthest to the second direction.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor wafer inspection apparatus, a semiconductor wafer inspection method, and a recording medium. [Background technology]

[0002] Conventionally, semiconductor wafer inspection equipment has been proposed that inspects (also called testing) semiconductor chips configured on a wafer by multiprobing (see, for example, Patent Document 1). For such semiconductor wafer inspection equipment, it is preferable to have a short inspection time for the semiconductor chip due to manufacturing cost considerations. Since the inspection time is proportional to the number of contacts between the probe and the electrodes of the semiconductor chip, reducing the total number of contacts is effective in reducing manufacturing costs. Therefore, semiconductor wafer inspection equipment capable of reducing the total number of contacts between the probe and the electrodes of the semiconductor chip has also been proposed (see, for example, Patent Document 2). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 6-168991 [Patent Document 2] Patent No. 7498677 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, the semiconductor wafer inspection apparatus described in Patent Documents 1 and 2 still had room for improvement in terms of reducing the total number of contacts.

[0005] This disclosure provides a semiconductor wafer inspection apparatus, a semiconductor wafer inspection method, and a recording medium that can reduce the total number of contacts and thereby reduce inspection time and manufacturing costs. [Means for solving the problem]

[0006] The semiconductor wafer inspection apparatus according to this disclosure comprises at least N measurement sites (where N is an integer of 2 or more) arranged in a specific direction, a tester that brings the N measurement sites into contact with a plurality of semiconductor chips formed on a semiconductor wafer and arranged in the specific direction, and inspects the N semiconductor chips that are in contact, and a determination means for determining which of the plurality of semiconductor chips to make contact with the N measurement sites. The determination means determines that if there are no semiconductor chips among the N inspected semiconductor chips that are determined to be defective, the next semiconductor chip to be made to contact will be shifted by N units in a first direction, which is one of the specific directions, and if there are semiconductor chips among the N inspected semiconductor chips that are determined to be defective, the determination means determines that the next semiconductor chip to be made to contact will be the one located furthest to the second direction, which is the other direction of the specific direction, among the semiconductor chips that are determined to be defective, and the one located furthest to the second direction among the N measurement sites.

[0007] The semiconductor wafer inspection method according to this disclosure comprises at least N measurement sites (where N is an integer of 2 or more) arranged in a specific direction, and a tester that brings the N measurement sites into contact with a plurality of semiconductor chips formed on the semiconductor wafer and arranged in the specific direction, and inspects the N semiconductor chips that are in contact. used A semiconductor wafer inspection method comprising a determination step of determining which semiconductor chips to contact with the N measurement sites from among a plurality of semiconductor chips, wherein in the determination step, if there are no semiconductor chips determined to be defective among the N semiconductor chips inspected, it is determined to shift the next semiconductor chip to be contacted by N units in a first direction which is one of the specific directions, and if there are semiconductor chips determined to be defective among the N semiconductor chips inspected, the next semiconductor chip to be contacted is It was determined to be a defective product. It is determined that the semiconductor chip located furthest to the second direction, which is the other direction from the specified direction, and the N measurement sites located furthest to the second direction, make contact.

[0008] The recording medium relating to this disclosure contains a test program that causes a computer to function as a semiconductor wafer testing device as described above. [Effects of the Invention]

[0009] According to this disclosure, it is possible to further reduce the total number of contacts, thereby lowering inspection time and manufacturing costs. [Brief explanation of the drawing]

[0010] [Figure 1] This is a configuration diagram showing an example of a semiconductor wafer inspection apparatus according to the first embodiment. [Figure 2] This is a configuration diagram showing the control configuration of a semiconductor wafer inspection apparatus according to the first embodiment. [Figure 3] This is a schematic diagram showing a semiconductor chip formed on a semiconductor wafer. [Figure 4] This is a schematic diagram showing a probe card. [Figure 5] This is a conceptual diagram showing the inspection sequence for semiconductor chips. [Figure 6] This is a schematic diagram showing the inspection process, including re-examination, for the comparative example, illustrating the inspection process in a specific column. (a) shows the initial inspection, and (b) shows the re-examination. [Figure 7] This is a schematic diagram illustrating the testing process, including retesting using the efficient probing method, and shows the testing process in a specific column. [Figure 8] This is a first schematic diagram showing the inspection process, including re-inspection, according to the first embodiment, and shows the first half of the inspection in a specific column, where (a) shows the first step, (b) shows the second step, (c) shows the third step, (d) shows the fourth step, (e) shows the fifth step, and (f) shows the sixth step. [Figure 9] This is a first schematic diagram showing the inspection process, including re-inspection, according to the first embodiment, and shows the latter half of the inspection in a specific column, where (a) shows the seventh step, (b) shows the eighth step, (c) shows the ninth step, (d) shows the tenth step, and (e) shows the eleventh step. [Figure 10] A chart showing the total number of contacts when the ratio of the number of semiconductor chips determined to be non-defective in the initial inspection is 95%. [Figure 11] A chart showing the total number of contacts when the ratio of the number of semiconductor chips determined to be non-defective in the initial inspection is 75%. [Figure 12] A chart showing the total number of contacts when the ratio of the number of semiconductor chips determined to be non-defective in the initial inspection is 50%. [Figure 13] A second schematic diagram showing the state of inspection including re-inspection according to the first embodiment, showing the state of inspection in a specific column, (a) shows a specific process, (b) shows the state before adjustment of the next process of the specific process, and (c) shows the state after adjustment of the next process of the specific process. [Figure 14] A third schematic diagram showing the state of inspection including re-inspection according to the first embodiment, showing the state of inspection in a specific column, (a) shows a specific process, (b) shows the state before adjustment of the next process of the specific process, and (c) shows the state after adjustment of the next process of the specific process. [Figure 15] A flowchart showing a method for inspecting a semiconductor wafer according to the first embodiment. [Figure 16] A first schematic diagram showing the state of inspection including re-inspection according to the second embodiment, showing the state of inspection in a specific column, (a) shows the state before the first adjustment, (b) shows the state after the first adjustment, (c) shows the state before the second adjustment, and (d) shows the state after the second adjustment. [Figure 17] A second schematic diagram showing the state of inspection including re-inspection according to the second embodiment, showing the state of inspection in a specific column, (a) shows the state before the first adjustment, (b) shows the state after the first adjustment, (c) shows the state before the second adjustment, and (d) shows the state after the second adjustment. [Figure 18] A flowchart showing a method for inspecting a semiconductor wafer according to the second embodiment. [Figure 19] A flowchart showing a method for inspecting a semiconductor wafer according to the third embodiment. [Figure 20]This is a flowchart showing a semiconductor wafer inspection method according to the fourth embodiment. [Figure 21] This is a schematic diagram showing a probe card for a semiconductor wafer inspection apparatus according to the fifth embodiment. [Figure 22] This is a schematic diagram showing other examples of probe cards according to the fifth embodiment, where (a) shows the first example, (b) shows the second example, (c) shows the third example, and (d) shows the fourth example. [Figure 23] This is a schematic diagram showing the inspection process, including re-inspection, according to the fifth embodiment, where (a) shows the first step, (b) shows the second step, (c) shows the third step, (d) shows the fourth step, (e) shows the fifth step, and (f) shows the sixth step. [Figure 24] This is a plan view showing the semiconductor wafer used in the simulation according to the fifth embodiment. [Figure 25] This is a diagram showing the simulation results according to the fifth embodiment. [Figure 26] This graph shows the simulation results according to the fifth embodiment. [Figure 27] This is a flowchart showing a semiconductor wafer inspection method according to the fifth embodiment. [Modes for carrying out the invention]

[0011] The present disclosure will be described below in accordance with preferred embodiments. However, the present disclosure is not limited to the embodiments shown below and may be modified as appropriate without departing from the spirit of the disclosure. Furthermore, in the embodiments shown below, some illustrations and descriptions of certain components are omitted. It goes without saying that, regarding the details of the omitted technologies, publicly known or well-known technologies are applied as appropriate, to the extent that they do not contradict the content described below.

[0012] Figure 1 is a configuration diagram showing an example of a semiconductor wafer inspection apparatus according to the first embodiment. Figure 2 is a configuration diagram showing the control configuration of the semiconductor wafer inspection apparatus according to the first embodiment.

[0013] The semiconductor wafer SW inspection apparatus 1 performs inspection on each semiconductor chip of the semiconductor wafer SW. As shown in Figure 1, the inspection apparatus 1 includes a wafer chuck 10, a moving mechanism 20, a probe card 30, a frog ring 40, a performance board 50, a test head 60, and a rotating shaft 70. The inspection apparatus 1 also includes a semiconductor tester (tester) 80, as shown in Figure 2.

[0014] The wafer chuck 10 holds the semiconductor wafer SW. The moving mechanism 20 moves and rotates the wafer chuck 10 in three dimensions. The probe card 30 has probes 31 that contact electrode pads formed on the semiconductor chip. The probe card 30 has connection terminals on its upper side that are electrically connected to the probes 31. The frog ring 40 is a connecting member for connecting the connection terminals located on the upper side of the probe card 30 to the test head 60. The test head 60 is connected to a semiconductor tester 80 and applies electrical signals from the semiconductor tester 80 to the semiconductor chip, receives a corresponding output signal from the semiconductor chip and sends it back to the semiconductor tester 80. A performance board 50 is attached to the test head 60 for connection with the frog ring 40. The test head 60 and the performance board 50 are configured to rotate around a rotation axis 70 and be detached from the rest of the device. Generally, the parts of the inspection device 1 other than the test head 60 are referred to as the prober P.

[0015] Figure 3 is a schematic diagram showing semiconductor chips formed on a semiconductor wafer SW. As shown in Figure 3, numerous semiconductor chips SC are arranged in a grid pattern on the semiconductor wafer SW. Note that there are also regions on the semiconductor wafer SW outside the effective area EA where semiconductor chips SC cannot be formed. In Figure 3, the dashed circles represent the effective area EA.

[0016] Figure 4 is a schematic diagram showing a probe card 30. The probe card 30 has N measurement sites 32 (where N is an integer greater than or equal to 2). Each measurement site 32 has a probe 31 that contacts an electrode pad formed on a semiconductor chip SC. Each measurement site 32 is formed so that each probe 31 contacts (hereinafter also referred to as contact) the corresponding electrode pad of the semiconductor chip SC. In Figure 4, there are four measurement sites 32, which are arranged in a row in a specific direction. Of these measurement sites 32, the other side of the specific direction is the first measurement site 32a, and the second measurement site 32b, third measurement site 32c, and fourth measurement site 32d are arranged in that order toward the one side of the specific direction. In the following explanation, N=4.

[0017] As shown in Figure 2, the inspection device 1 further includes a control unit 90. The control unit 90 controls the prober P and the semiconductor tester 80 and includes a contact position determination unit (determination means) 91 and a storage unit (recording medium) 92. The storage unit 92 stores the operation program and various setting values ​​for operating the inspection device 1. The storage unit 92 may also provide a temporary storage area during operation. The contact position determination unit 91 determines which of the multiple semiconductor chips SC on the semiconductor wafer SW the probes 31 of the multiple measurement sites 32 should make contact with. The prober P operates the moving mechanism 20 according to this determination to make contact between the probes 31 of the multiple measurement sites 32 and the semiconductor chips SC.

[0018] Next, the inspection method using the semiconductor wafer SW inspection apparatus 1 according to the first embodiment will be described. First, the semiconductor wafer SW is held in the wafer chuck 10. Then, the control unit 90 controls the moving mechanism 20 so that the probe 31 of each measurement site 32 makes equal and accurate contact with the electrode pads on each semiconductor chip SC.

[0019] Next, the control unit 90 brings the probe card 30 close to the semiconductor wafer SW and brings the probes 31 of each measurement site 32 into contact with the electrode pads of the semiconductor chip SC, thereby electrically coupling them. Then, the semiconductor tester 80 applies an electrical signal to each semiconductor chip SC via the test head 60, according to the control unit 90. The semiconductor tester 80 then receives the output signal from each semiconductor chip SC corresponding to the electrical signal and determines whether a predetermined output is being produced. This determines whether each semiconductor chip SC is a good product or a defective product.

[0020] After the determination, the control unit 90 inspects the next semiconductor chip SC. Specifically, the control unit 90 moves the probe card 30 away from the semiconductor wafer SW and brings the probes 31 of each measurement site 32 into contact with the electrode pads of the uninspected semiconductor chip SC. Subsequently, an electrical signal is applied, an output signal is received, and a determination is made to determine whether each semiconductor chip SC is good or defective. Thereafter, all semiconductor chip SCs on the semiconductor wafer SW are inspected in the same manner.

[0021] Figure 5 is a conceptual diagram showing the inspection sequence of semiconductor chips SC. As shown in Figure 5, the control unit 90 starts measurement from the semiconductor chip SCa at the edge of the semiconductor wafer SW. More specifically, the control unit 90 inspects the semiconductor wafer SW by sequentially moving it in a zigzag pattern from the semiconductor chip SC of the outermost row (horizontal row) shown in Figure 5 toward the other row. During this process, the control unit 90 makes contact with each semiconductor chip SC in sequence using the probe 31 and performs the inspection until it reaches the semiconductor chip SC of the outermost row. In the following description, the direction in which the multiple measurement sites 32 advance in each row is referred to as the first direction, and the direction opposite to the first direction is referred to as the second direction. The first and second directions are aligned along specific directions.

[0022] Furthermore, the control unit 90 may perform inspections in a zigzag pattern, starting from the semiconductor chip SC in the farthest column (vertical column) toward the column on the other side, from one end to the other end or from the other end to the one end.

[0023] Here, if each semiconductor chip SC formed on the semiconductor wafer SW is determined to be defective during the initial inspection (hereinafter referred to as the initial inspection), a second inspection (hereinafter referred to as the reinspection) may be performed. This is because even good semiconductor chip SCs may be judged as defective during the initial inspection for some reason. For example, if the contact between the probe 31 of the probe card 30 and the electrode pad of the semiconductor chip SC is not appropriate, even a good semiconductor chip SC may be judged as defective. Therefore, the inspection device 1 increases the number of semiconductor chip SCs judged as good by performing a reinspection of the semiconductor chip SCs that have been judged as defective, compared to when only the initial inspection is performed. Note that the reinspection may be repeated not just once, but two or more times.

[0024] Next, we will describe an inspection method including re-inspection using the inspection apparatus 1 of the semiconductor wafer SW according to the first embodiment. Prior to that, we will describe an inspection method related to a comparative example.

[0025] Figure 6 is a schematic diagram showing the inspection process, including re-examination, for the comparative example, and illustrates the inspection process in a specific column. In Figure 6, the number of semiconductor chips SC in the specific column is assumed to be 32, and each is assigned a coordinate number from 1 to 32. Furthermore, it is assumed that multiple measurement sites 32 can simultaneously contact four adjacent semiconductor chips SC.

[0026] First, the contact points of the probe card 30 with each semiconductor chip SC are predetermined. As shown in Figure 6(a), the inspection apparatus for the comparative example first performs an initial inspection on the semiconductor chip SCs at coordinates 1 to 4, and then performs initial inspections on four semiconductor chip SCs at each coordinate from 5 onwards. This results in a total of eight initial inspections. Now, suppose that in the initial inspection, the semiconductor chip SCs at coordinates 6, 9, 16, 18, 23, 24, and 29 are determined to be defective (indicated as "F" in Figure 6), and the remaining semiconductor chip SCs are determined to be good (indicated as "P" in Figure 6). In this case, a re-inspection is performed on the semiconductor chip SCs at coordinates 6, 9, 16, 18, 23, 24, and 29. Since the contact points of the probe card 30 with each semiconductor chip SC are predetermined, the re-inspection is performed as shown in Figure 6(b). In other words, re-inspection is performed on semiconductor chips SC at coordinates 5-8, 9-12, 13-16, 17-20, 21-24, and 29-32. Note that in the example in Figure 6(b), re-inspection is not performed on semiconductor chips SC at coordinates 1-4 and 25-28. Therefore, the number of re-inspections is 6.

[0027] Here, since the inspection time of a semiconductor chip SC is proportional to the number of inspections (number of contacts), reducing the total number of contacts required to inspect one semiconductor wafer SW is effective in reducing manufacturing costs. Therefore, the efficient probing method described in Patent Document 2 has been proposed. The method shown in Figure 6 will be referred to as the conventional method.

[0028] Figure 7 is a schematic diagram showing the examination process, including retesting, using the efficient probing method, and illustrates the examination process in a specific column. In the efficient probing method, the initial examination is the same as in the conventional method.

[0029] In the efficient probing method shown in Figure 7, the control unit first brings the first measurement site 32a into contact with the semiconductor chip SC at coordinate 6, which was determined to be defective, at the start of the re-examination. At this time, the fourth measurement site 32d and the semiconductor chip SC at coordinate 9, which was also determined to be defective, come into contact simultaneously. As a result, the semiconductor chip SCs at coordinates 6 and 9 are re-examined at the same time.

[0030] Next, the control unit 90 brings the first measurement site 32a into contact with the semiconductor chip SC at coordinate 16, which was determined to be defective. At this time, the third measurement site 32c and the semiconductor chip SC at coordinate 18, which was also determined to be defective, come into contact simultaneously. As a result, the semiconductor chip SCs at coordinates 16 and 18 are re-examined at the same time.

[0031] Similarly, the control unit 90 can re-examine all semiconductor chips SC that were initially identified as defective by re-examining coordinates 23-26 and 29-32. Thus, in the efficient probing method, eight contacts are made during the initial inspection and four contacts are made during the re-examination. Therefore, the total number of contacts is 12, which is two fewer than the 14 contacts required by the conventional method, allowing the efficient probing method to perform the re-examination with fewer contacts.

[0032] Next, the inspection process including re-examination according to the first embodiment will be described. Figures 8 and 9 are first schematic diagrams showing the inspection process including re-examination according to the first embodiment, and show the inspection process in a specific column. In the example shown in Figures 8 and 9, the number of re-examinations is assumed to be one. The inspection method according to the first embodiment described below will be referred to as the sequential method.

[0033] First, as shown in Figure 8(a), in the first inspection, the contact position determination unit 91 determines to make contact between the probe card 30 and the semiconductor chips SC at coordinates 1 to 4. Then, the inspection is performed. Assume that all semiconductor chips SC are judged to be good in the first inspection.

[0034] Next, as shown in Figure 8(b), in the second inspection, the contact position determination unit 91 decides to make contact between the probe card 30 and the semiconductor chips SC at coordinates 5 to 8. That is, if there are no semiconductor chips SC determined to be defective in the first inspection, the contact position determination unit 91 decides to shift the semiconductor chips SC to be made contact in the second inspection by four positions in the first direction. Then the inspection is performed. Suppose that in the second inspection, only the semiconductor chip SC at coordinate 6 is determined to be defective.

[0035] Next, as shown in Figure 8(c), in the third inspection, the contact position determination unit 91 decides to bring the probe card 30 into contact with the semiconductor chips SC at coordinates 6 to 9. That is, for the third inspection, the contact position determination unit 91 decides that the semiconductor chip SC at coordinate 6, which was determined to be defective in the second inspection, will come into contact with the first measurement site 32a. As a result, the semiconductor chip SC at coordinate 6 undergoes a re-inspection, and the semiconductor chip SC at coordinate 9 undergoes an initial inspection. Let's assume that the semiconductor chip SC at coordinate 6 is determined to be good, and the semiconductor chip SC at coordinate 9 is determined to be defective.

[0036] Next, as shown in Figure 8(d), in the fourth inspection, the contact position determination unit 91 decides to bring the probe card 30 into contact with the semiconductor chips SC at coordinates 9 to 12. That is, for the fourth inspection, the contact position determination unit 91 decides that the semiconductor chip SC at coordinate 9, which was determined to be defective in the third inspection, will come into contact with the first measurement site 32a. As a result, the semiconductor chip SC at coordinate 9 undergoes a re-inspection, and the semiconductor chip SCs at coordinates 10 to 12 undergo an initial inspection. Let's assume that the semiconductor chip SC at coordinate 9 is determined to be defective, and the semiconductor chip SCs at coordinates 10 to 12 are determined to be good.

[0037] Subsequently, as shown in Figure 8(e), in the fifth inspection, the contact position determination unit 91 decides to bring the probe card 30 into contact with the semiconductor chips SC at coordinates 13 to 16. In the examples shown in Figures 8 and 9, the number of re-inspections is one. Therefore, no further re-inspection is performed on the semiconductor chip SC at coordinate 9, which was determined to be defective. Also, in the fourth inspection, the semiconductor chips SC at coordinates 10 to 12 were determined to be good. Therefore, the contact position determination unit 91 decides to bring the probe card 30 into contact with the semiconductor chips SC at coordinates 13 to 16. Then, the inspection is performed. Assume that in the fifth inspection, only the semiconductor chip SC at coordinate 16 was determined to be defective.

[0038] Next, as shown in Figure 8(f), in the sixth inspection, the contact position determination unit 91 decides to bring the probe card 30 into contact with the semiconductor chips SC at coordinates 16 to 19. That is, the contact position determination unit 91 decides to bring the semiconductor chip SC at coordinate 16, which was determined to be defective in the fifth inspection, into contact with the first measurement site 32a. As a result, the semiconductor chip SC at coordinate 16 undergoes a re-inspection, and the semiconductor chips SC at coordinates 17 to 19 undergo their initial inspection. Let's assume that the semiconductor chip SC at coordinate 18 is determined to be defective, and the semiconductor chips SC at coordinates 16, 17, and 19 are determined to be good.

[0039] Next, as shown in Figure 9(a), in the seventh inspection, the contact position determination unit 91 decides to bring the probe card 30 into contact with the semiconductor chips SC at coordinates 18 to 21. That is, the contact position determination unit 91 decides to bring the semiconductor chip SC at coordinate 18, which was determined to be defective in the sixth inspection, into contact with the first measurement site 32a. As a result, the semiconductor chip SC at coordinate 18 is re-inspected, and the semiconductor chips SC at coordinates 20 and 21 are initially inspected. Let's assume that the semiconductor chip SC at coordinate 18 is determined to be defective, and the semiconductor chips SC at coordinates 20 and 21 are determined to be good.

[0040] Subsequently, as shown in Figure 9(b), in the eighth inspection, the contact position determination unit 91 decides to bring the probe card 30 into contact with the semiconductor chips SC at coordinates 22-25. Here, the number of re-inspections is one. Therefore, no further re-inspection is performed on the semiconductor chip SC at coordinate 18, which was determined to be defective in the seventh inspection. Also, the semiconductor chips SC at coordinates 19-21 are determined to be good. Therefore, the contact position determination unit 91 decides to bring the probe card 30 into contact with the semiconductor chips SC at coordinates 22-25. Then, the inspection is performed. Suppose that in the eighth inspection, the semiconductor chips SC at coordinates 23 and 24 are determined to be defective.

[0041] Next, as shown in Figure 9(c), in the ninth inspection, the contact position determination unit 91 decides to bring the probe card 30 into contact with the semiconductor chips SC at coordinates 23 to 26. That is, the contact position determination unit 91 decides that the semiconductor chip SC at coordinates 23 and 24, which was determined to be defective in the eighth inspection, will make contact with the first measurement site 32a. As a result, the semiconductor chip SCs at coordinates 23 and 24 will be re-inspected, and the semiconductor chip SC at coordinate 26 will undergo its initial inspection. Let's assume that all semiconductor chip SCs are then determined to be good.

[0042] Next, as shown in Figure 9(d), in the 10th inspection, the contact position determination unit 91 decides to make contact between the probe card 30 and the semiconductor chip SC at coordinates 27-30. That is, since there are no semiconductor chip SCs that were determined to be defective in the 9th inspection, the contact position determination unit 91 decides to shift the semiconductor chip SC to be made contact next by 4 units in the first direction. Then the inspection is performed. Suppose that in the 10th inspection, only the semiconductor chip SC at coordinate 29 is determined to be defective.

[0043] Subsequently, as shown in Figure 9(e), in the 11th inspection, the contact position determination unit 91 determines to bring the probe card 30 into contact with the semiconductor chips SC at coordinates 29-32. That is, the contact position determination unit 91 determines that the semiconductor chip SC at coordinate 29, which was determined to be defective in the 10th inspection, will make contact with the first measurement site 32a. Then the inspection is performed. In the 11th inspection, only the semiconductor chip SC at coordinate 29 is determined to be defective, and the inspection, including re-inspection, is completed.

[0044] Here, as shown in Figures 8 and 9, the seven semiconductor chips SC determined to be defective in the initial inspection are located at the same coordinate positions as those shown in the efficient probing method in Figure 7. However, the sequential method according to the first embodiment involves 11 contacts, including the initial inspection and one re-inspection, which is fewer than the 12 contacts in the efficient probing method.

[0045] Next, we will explain the simulation results regarding the number of contacts. Instead of calculating the number of contacts of the probe card 30 for semiconductor chips SC formed in a grid pattern on the semiconductor wafer SW, the simulation calculated the number of contacts of the probe card 30 for semiconductor chips SC present in a single row. This is because calculating the number of contacts of the probe card 30 for a single row of semiconductor chips SC makes the interpretation of the results clearer than calculating it for the entire semiconductor wafer SW, the number of contacts for the entire semiconductor wafer SW is actually the sum of the number of contacts in each row, and the number of semiconductor chips SC on the semiconductor wafer SW differs from row to row, etc.

[0046] In the simulation, the number of semiconductor chips SC in a row was set to increments of 10, ranging from 10 to 200, with three initial good quality rates: 95%, 75%, and 50%. The number of measurement sites 32 on the probe card 30 was set to 3 to 5. The measurement sites 32 were assumed to be adjacent to each other, and the total number of contacts required to test a row of semiconductor chips SC was calculated. The number of trials was set to 1000 for each condition, and the location of defective semiconductor chips SC was randomly determined according to the initial good quality rate.

[0047] Figure 10 shows the total number of contacts when 95% of semiconductor chips are judged as good during the initial inspection. Figure 10 shows the average total number of contacts when 1000 simulations are performed under each condition.

[0048] As shown in Figure 10, for example, when the number of measurement sites is "3" and the number of semiconductor chips is "10", the average total number of contacts for the conventional method was 4.47, and the average total number of contacts for the efficient probing method was 4.457. The average total number of contacts for the sequential method was 4.217. In other words, the method with the fewest total contacts was the sequential method.

[0049] Similarly, for example, when the number of measurement sites is "4" and the number of semiconductor chips is "100", the average total number of contacts for the conventional method was 29.642, while the average total number of contacts for the efficient probing method was 29.375. The average total number of contacts for the sequential method was 28.312. In this case as well, the sequential method resulted in the fewest total contacts.

[0050] Furthermore, for example, when the number of measurement sites was "5" and the number of semiconductor chips was "200", the average total number of contacts for the conventional method was 49.322, while the average total number of contacts for the efficient probing method was 48.625. The average total number of contacts for the sequential method was 46.065. In this case as well, the sequential method was found to be the method with the fewest total contacts.

[0051] Furthermore, in cases other than the three examples mentioned above, the method with the fewest total contacts was consistently the sequential method. Note that when the number of measurement sites is "5" and the number of semiconductor chips is "10," due to significant figures, the total number of contacts appears to be the same for both the efficient probing method and the sequential method; however, in reality, the sequential method resulted in fewer total contacts.

[0052] Figure 11 shows the total number of contacts when the percentage of semiconductor chips judged as good during the initial inspection is 75%. In Figure 11, the simulation was performed under the same conditions as in Figure 10 to calculate the total number of contacts (average value).

[0053] As shown in Figure 11, for example, when the number of measurement sites is "3" and the number of semiconductor chips is "200", the average total number of contacts for the conventional method was 105.555, while the average total number of contacts for the efficient probing method was 100.439. Furthermore, the average total number of contacts for the sequential method was 93.757. In other words, the sequential method resulted in the fewest total contacts.

[0054] Similarly, for example, when the number of measurement sites is "4" and the number of semiconductor chips is "10", the average total number of contacts for the conventional method was 4.804, while the average total number of contacts for the efficient probing method was 4.557. The average total number of contacts for the sequential method was 4.25. In this case as well, the sequential method resulted in the fewest total contacts.

[0055] Furthermore, for example, when the number of measurement sites was "5" and the number of semiconductor chips was "100", the average total number of contacts for the conventional method was 35.258, while the average total number of contacts for the efficient probing method was 32.673. The average total number of contacts for the sequential method was 30.595. In this case as well, the sequential method was found to be the method with the fewest total contacts.

[0056] Furthermore, in cases other than the three examples mentioned above, the sequential method consistently resulted in the fewest total contacts. Similarly, when the number of measurement sites was "5" and the number of semiconductor chips was "10," the results were the same as in Figure 10, indicating that the sequential method actually resulted in fewer total contacts.

[0057] Figure 12 shows the total number of contacts when the percentage of semiconductor chips judged as good during the initial inspection is 50%. In Figure 12, the simulation was performed under the same conditions as in Figure 10 to calculate the total number of contacts (average value).

[0058] As shown in Figure 12, for example, when the number of measurement sites is "3" and the number of semiconductor chips is "100", the average total number of contacts for the conventional method was 63.345, while the average total number of contacts for the efficient probing method was 59.223. Furthermore, the average total number of contacts for the sequential method was 56.169. In other words, the method with the fewest total contacts was the sequential method.

[0059] Similarly, for example, when the number of measurement sites is "4" and the number of semiconductor chips is "200", the average total number of contacts for the conventional method was 96.847, while the average total number of contacts for the efficient probing method was 90.189. The average total number of contacts for the sequential method was 86.325. In this case as well, the sequential method resulted in the fewest total contacts.

[0060] Furthermore, for example, when the number of measurement sites was "5" and the number of semiconductor chips was "10", the average total number of contacts using the conventional method was 3.943, while the average total number of contacts using the efficient probing method was 3.899. The average total number of contacts using the sequential method was also 3.899. In this case as well, the method with the fewest total contacts was the sequential method. Note that, due to the consideration of significant figures, the total number of contacts is shown to be the same for the efficient probing method and the sequential method, but in reality, the sequential method had fewer total contacts.

[0061] Furthermore, in cases other than the three examples mentioned above, the method with the fewest total contacts was consistently the sequential method.

[0062] As shown above, the simulation results also indicate that the total number of contacts can be reduced by using the sequential method.

[0063] In this case, the semiconductor wafer SW inspection apparatus 1 according to the first embodiment preferably performs the inspections shown in Figures 13 and 14.

[0064] Figure 13 is a second schematic diagram showing the inspection process, including re-inspection, according to the first embodiment, and shows the inspection process in a specific column. In Figure 9(e), the semiconductor chip SC at coordinate 29 was determined to be defective. Therefore, by bringing the semiconductor chip SC at coordinate 29 into contact with the first measurement site 32a, the fourth measurement site 32d comes into contact with the semiconductor chip SC at coordinate 32, which is located at the end in the first direction.

[0065] However, as shown in Figure 13(a), suppose the semiconductor chip SC at coordinate 29 is determined to be a good product. In this case, since all of the semiconductor chips SC at coordinates 27 to 30 are good products, the contact positions of the semiconductor chips SC will be shifted by the number of measurement sites, which is four, as shown in Figure 13(b). However, in this case, the number of semiconductor chips to be in contact will be less than four, and the third and fourth measurement sites 32c and 32d will not make contact with the semiconductor chips SC.

[0066] During inspection of semiconductor chips SC, a malfunction may occur if any of the measurement sites 32 contact an area outside the effective area EA or an area where semiconductor chips SC are not formed. Therefore, as shown in Figure 13(c), the contact position determination unit 91 determines that the contact position should be shifted in the second direction by the number of semiconductor chips SC (two in Figure 13) that are less than four. This helps to suppress the occurrence of malfunctions.

[0067] Figure 14 is a third schematic diagram showing the inspection process, including re-inspection, according to the first embodiment, and shows the inspection process in a specific column. Also, as shown in Figure 14(a), suppose that the semiconductor chip SC at coordinate 30 is determined to be defective. In this case, as shown in Figure 14(b), the contact position determination unit 91 determines the next contact position so that the semiconductor chip SC at coordinate 30 and the first measurement site 32a make contact. However, in this case, the number of semiconductor chips to make contact becomes less than four, and the fourth measurement site 32d does not make contact with the semiconductor chip SC. Therefore, as shown in Figure 14(c), the contact position determination unit 91 decides to shift in the second direction by the number of semiconductor chips SC that are less than four (one in Figure 14). This also helps to suppress the occurrence of defects.

[0068] Figure 15 is a flowchart showing the inspection method for a semiconductor wafer SW according to the first embodiment. Note that in Figure 15, the number of columns is n. max Each semiconductor chip SC on the semiconductor wafer SW shall be inspected.

[0069] As shown in Figure 15, first, the control unit 90 performs initial setup (S1). In this process, the control unit 90 loads a test program for performing the inspection into the semiconductor tester 80. Furthermore, the control unit 90 sets the semiconductor wafer SW in the prober P, sets the probe card 30, adjusts the position of the probe card 30, and moves the probe card 30 to its initial position. Also, the variable n is set to "1". Furthermore, the contact position determination unit 91 is set with the placement information of the multiple semiconductor chips SC to be inspected.

[0070] Next, the control unit 90 determines that there are n rows to be inspected (S2). Then, the contact position determination unit 91 determines that it will contact the four semiconductor chips SC from the second direction side of the n rows (S3). The control unit 90 then brings the four measurement sites 32 into contact with the four semiconductor chips SC at the determined positions, applies an electrical signal from the semiconductor tester 80 to each semiconductor chip SC, and observes the response. The semiconductor tester 80 then determines whether each semiconductor chip SC is good or defective (S4). The semiconductor tester 80 then notifies the contact position determination unit 91 of the determination result (S4).

[0071] Subsequently, the contact position determination unit 91 determines whether there are any defective products (S5). If there are defective products (S5: YES), the contact position determination unit 91 determines whether the number of retests has reached the maximum value (S6). If the number of retests has not reached the maximum value (S6: NO), the contact position determination unit 91 determines to make contact between the semiconductor chip SC on the second direction side of the defective product and the first measurement site 32a (S7). Then, the process proceeds to step S9.

[0072] On the other hand, if there are no defective products (S5: NO), or if the number of re-inspections has reached the maximum value (S6: YES), the contact position determination unit 91 decides to move four units in the first direction and make contact (S8). Then, the process moves to step S9.

[0073] In step S9, the control unit 90 determines whether the inspection has been completed for all n semiconductor chips SC in the n row (S9). For example, in the inspection method according to the first embodiment, if the inspection has been completed for all n semiconductor chips SC in the n row, the number of semiconductor chips SC that make contact with the four measurement sites 32 at the positions determined by the contact position determination unit 91 will be zero.

[0074] If the inspection of all n semiconductor chips SC is not completed (S9:NO), that is, if the four measurement sites 32 make contact with any of the semiconductor chips SC at the positions determined by the contact position determination unit 91, the contact position determination unit 91 determines whether any of the measurement sites 32 are protruding (S10).

[0075] For example, in the cases shown in Figure 13(b) and Figure 14(b), the contact position determination unit 91 determines that the contacts are in a protruding state (S10: YES) and adjusts the contact position (S11). That is, the contact position determination unit 91 shifts the contact position in the second direction by the number of measurement sites 32 that are in a protruding state. Then the process proceeds to step S4. Also, if the conditions are not as shown in Figure 13(b) and Figure 14(b), the contact position determination unit 91 determines that the contacts are not in a protruding state (S10: NO) and the process proceeds to step S4.

[0076] Furthermore, if the inspection of all n semiconductor chips SC is completed (S9:YES), the control unit 90 increments the variable n (S12). Then, the control unit 90 checks if the variable n is n max Determine if it exceeds (S13).

[0077] The variable n is n max If it does not exceed (S13:NO), the process proceeds to step S2. On the other hand, if the variable n is n max If the value exceeds (S13:YES), the process shown in Figure 15 terminates.

[0078] In this way, according to the semiconductor wafer SW inspection apparatus 1 and inspection method of the first embodiment, if any of the N semiconductor chips SC that have been inspected are determined to be defective, the next contact target is determined so that the semiconductor chip SC located furthest to the second direction among the defective semiconductor chip SCs makes contact with the N measurement sites 32 located furthest to the second direction. Therefore, if any semiconductor chip SCs are determined to be defective, they are immediately re-inspected. In this way, by sequentially re-inspecting semiconductor chip SCs determined to be defective, the number of contacts can be reduced compared to conventional methods and efficient probing methods. Thus, it is possible to provide a semiconductor wafer SW inspection apparatus 1 that can further reduce the total number of contacts and reduce inspection time and manufacturing costs.

[0079] Furthermore, if the number of semiconductor chips SC to be contacted by the contact position determination unit 91 is less than N, it shifts the next contact position in the second direction by the number of missing contact points. This reduces the possibility of malfunctions occurring due to the first direction side of the N measurement sites 32 not making contact with the semiconductor chips SC.

[0080] Furthermore, according to the storage unit 92 of the first embodiment, the semiconductor wafer SW inspection apparatus 1 and inspection method can be realized.

[0081] Next, the semiconductor wafer SW inspection apparatus 1 and inspection method according to the second embodiment will be described. The semiconductor wafer SW inspection apparatus 1 and inspection method according to the second embodiment are similar to those of the first embodiment, but differ in some respects. The differences from the first embodiment will be described below. In the following description, elements that are the same as or similar to those of the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0082] First, some semiconductor chips SC may contain defects that occur during the manufacturing process, such as damaging the probe 31 when the measurement site 32 makes contact, or burning out the probe 31 due to a large current flowing during inspection. Such semiconductor chips SC are referred to as prohibited chips, where contact is forbidden.

[0083] Figure 16 is a first schematic diagram showing the inspection process, including re-inspection, according to the second embodiment, and shows the inspection process in a specific column. For example, suppose the semiconductor chip SC at coordinate 15 is the prohibited chip PC. Here, as shown in Figure 16(a), suppose the contact position determination unit 91 decides to bring the semiconductor chip SC at coordinates 12 to 15 into contact with the four measurement sites 32. In this case, the fourth measurement site 32d and the prohibited chip PC come into contact.

[0084] Therefore, as shown in Figure 16(b), the contact position determination unit 91 adjusts the contact position so that the fourth measurement site 32d (the one at the end in the first direction) of the four measurement sites 32 makes contact with the semiconductor chip SC (at coordinate 14) adjacent to the prohibited chip PC in the second direction. As a result, the semiconductor chip SC at coordinate 11, which has been inspected, makes contact with the first measurement site 32a, but it is possible to inspect the semiconductor chip SCs at coordinates 12 to 14, which have not been inspected, while avoiding the prohibited chip PC.

[0085] Furthermore, as shown in Figure 16(c), suppose the contact position determination unit 91 determines that the semiconductor chip SC at coordinates 15-18 should be brought into contact with the four measurement sites 32. In this case, the first measurement site 32a and the prohibited chip PC will come into contact. In this state, the semiconductor chip SC at coordinates 1-14 can be said to have been inspected.

[0086] Therefore, as shown in Figure 16(d), the contact position determination unit 91 adjusts the contact position so that the first measurement site 32a (the one at the end in the second direction) among the four measurement sites 32 makes contact with the semiconductor chip SC (coordinate 16) adjacent to the prohibited chip PC in the first direction. In other words, since all semiconductor chips SC on the second direction side of the prohibited chip PC have already been inspected, the contact positions of the four measurement sites 32 are further advanced by one in the first direction to adjust the contact position. This makes it possible to avoid the prohibited chip PC.

[0087] Figure 17 is a second schematic diagram showing the inspection process, including re-inspection, according to the second embodiment, and shows the inspection process in a specific column. As shown in Figure 17(a), for example, if the semiconductor chip SC at coordinate 4 is a prohibited chip PC, there will be fewer than four semiconductor chip SCs located in the second direction from the prohibited chip PC. Therefore, if we try to inspect the semiconductor chip SCs at coordinates 1 to 3 while avoiding the prohibited chip PC, the first measurement site 32a will not make contact with the semiconductor chip SCs. Thus, as shown in Figure 17(b), the contact position determination unit 91 sets the prohibited chip PC and the semiconductor chip SCs at coordinates 1 to 3 in the prohibited area PA.

[0088] Next, the contact position determination unit 91 adjusts the contact position to avoid the prohibited area PA. That is, in the example shown in Figure 17(a), there are fewer than four semiconductor chips SC located in the second direction of the prohibited chip PC, so the contact position determination unit 91 shifts the contact position in the first direction, as shown in Figure 17(b). This adjusts the position so that the semiconductor chip SC adjacent to the prohibited area PA in the first direction (the one at coordinate 5) and the first measurement site 32a make contact.

[0089] Similarly, if the prohibited chip PC is located at coordinate 29, or if there are fewer than four semiconductor chips SC located in the first direction from the prohibited chip PC, the contact position determination unit 91 sets these as prohibited area PA. Then, once the inspection of semiconductor chips SC located in the second direction from coordinate 28 is completed, the inspection for the current row is finished, and the inspection of the next row is performed.

[0090] Furthermore, if the contact position is determined to avoid the prohibited chip PC, as shown in Figure 16(d), for example, it may still be possible to make contact with another prohibited chip PC, as shown in Figure 17(c). In such cases, the contact position determination unit 91 sets the two prohibited chip PCs and the semiconductor chip SC at coordinates 16 and 17 as the prohibited area PA, as shown in Figure 17(d). That is, if there are other prohibited chip PCs in the four semiconductor chip SCs located in the first or second direction of the prohibited chip PC, the two prohibited chip PCs and the semiconductor chip SC between them are set as the prohibited area PA.

[0091] The contact position determination unit 91 then shifts the contact position in the first direction. This adjusts the position so that the semiconductor chip SC (at coordinate 19) adjacent to the prohibited area PA in the first direction makes contact with the first measurement site 32a.

[0092] Figure 18 is a flowchart showing a semiconductor wafer SW inspection method according to the second embodiment.

[0093] After processing in step S7 or step S8, the contact position determination unit 91 determines whether the four measurement sites 32 make contact with the prohibited chip PC (S14). If the four measurement sites 32 do not make contact with the prohibited chip PC (S14: NO), the process proceeds to step S9.

[0094] On the other hand, if the four measurement sites 32 make contact with the prohibited chip PC (S14: YES), the contact position determination unit 91 performs processing related to the prohibited chip PC (S15). In this case, the processing described with reference to Figures 16 and 17 is performed. That is, in step S15, not only is the prohibited chip PC avoided, but if, in the process of avoiding it, other prohibited chip PCs are contacted or the four semiconductor chips SC are not contacted, a prohibited area PA is set and processing is performed to avoid the prohibited area PA as well. Then the process moves on to step S9.

[0095] In this way, the semiconductor wafer SW inspection apparatus 1, inspection method, and storage unit 92 according to the second embodiment can obtain the same effects as the first embodiment.

[0096] Furthermore, in the second embodiment, the contact position determination unit 91 adjusts the contact position so that the ends of the N measurement sites 32 make contact with the semiconductor chip SC adjacent to the prohibited chip PC, in order to avoid contact with the prohibited chip PC. As a result, it is prevented that any of the N measurement sites 32 make contact with the prohibited chip PC, thereby preventing failures caused by contact with the prohibited chip PC.

[0097] Furthermore, the contact position determination unit 91 designates areas PA as prohibited regions and prohibits contact if there are no N semiconductor chips SC between two prohibited chips PC or between a prohibited chip PC and the semiconductor chip SC at the end. This further prevents accidental contact with prohibited chips PC and helps prevent malfunctions.

[0098] Next, the semiconductor wafer SW inspection apparatus 1 and inspection method according to the third embodiment will be described. The semiconductor wafer SW inspection apparatus 1 and inspection method according to the third embodiment are similar to those of the first embodiment, but differ in some respects. The differences from the first embodiment will be described below. In the following description, elements that are the same as or similar to those of the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0099] First, it is empirically known that when re-inspecting a semiconductor chip SC that was determined to be defective during the initial inspection, contacting a different measurement site 32 than the one used during the initial inspection increases the likelihood of successful repair.

[0100] Therefore, the semiconductor wafer SW inspection apparatus 1 according to the third embodiment performs a process to make contact with a semiconductor chip SC that has been determined to be defective, using a measurement site 32 different from the measurement site 32 that was contacted last time. At this time, the contact position determination unit 91 may adjust the measurement site 32 by, for example, one unit in the second direction. In particular, it is preferable that the contact position determination unit 91 determines the number of semiconductor chip SCs that are being inspected for the first time as much as possible, even while performing re-inspection. Furthermore, if there are multiple semiconductor chip SCs to be re-inspected, it is preferable that the contact position determination unit 91 determines the number of semiconductor chip SCs to be re-inspected to contact a different measurement site 32 as much as possible.

[0101] Figure 19 is a flowchart showing a semiconductor wafer SW inspection method according to the third embodiment.

[0102] After a "NO" is determined in step S10, or after the processing in step S11, the contact position determination unit 91 determines whether there is a semiconductor chip SC that has been determined to be defective and whether the same measurement site 32 as before is making contact (S16).

[0103] If the same measurement site 32 as the previous time is not in contact (S16: NO), the process proceeds to step S4. On the other hand, if the same measurement site 32 as the previous time is in contact (S16: YES), the contact position determination unit 91 adjusts the contact position (S17). After that, the process proceeds to step S4.

[0104] In this way, the semiconductor wafer SW inspection apparatus 1, inspection method, and storage unit 92 according to the third embodiment can obtain the same effects as in the first embodiment.

[0105] Furthermore, according to the third embodiment, during re-inspection, the semiconductor chip SC determined to be defective comes into contact with a different measurement site 32. This reduces the possibility of a product being deemed defective due to a problem with the measurement site 32, thereby improving the remedy rate during re-inspection.

[0106] Next, the semiconductor wafer SW inspection apparatus 1 and inspection method according to the fourth embodiment will be described. The semiconductor wafer SW inspection apparatus 1 and inspection method according to the fourth embodiment are similar to those of the first embodiment, but differ in some respects. The differences from the first embodiment will be explained below.

[0107] The semiconductor wafer SW inspection apparatus 1 according to the fourth embodiment is capable of determining the defect mode if the semiconductor chip SC is determined to be defective during the initial inspection. The defect mode is a categorization of the defect when the semiconductor chip SC is determined to be defective during inspection.

[0108] Furthermore, the semiconductor wafer SW inspection apparatus 1 according to the fourth embodiment performs a re-inspection on a semiconductor chip SC that has been determined to be defective, according to the defect mode. That is, the inspection apparatus 1 performs a re-inspection on the semiconductor chip SC that has been determined to be defective under different inspection conditions. This makes it possible to obtain detailed data on the semiconductor chip SC that has been determined to be defective and to investigate the cause of the defect. It also becomes possible to determine whether a semiconductor chip SC has a slightly lower capability than the original semiconductor chip SC and whether it is a good product or a defective product. In this case, a semiconductor chip SC that would have been a defective product according to the original specifications can be salvaged as a good product, albeit at a lower grade, thereby improving the yield.

[0109] Figure 20 is a flowchart showing a semiconductor wafer SW inspection method according to the fourth embodiment.

[0110] After determining "NO" in step S6, the semiconductor tester 80, for example, based on instructions from the control unit 90, changes the inspection conditions for the semiconductor chip SC that was determined to be defective compared to before it was determined to be defective (S18). For example, the semiconductor tester 80 may change the electrical signal transmitted during inspection, or it may change the criteria for determining whether the output signal output from the semiconductor chip SC in response to the electrical signal is good or defective. This allows for the determination of good and defective products at a lower grade. The inspection conditions may also be changed to allow for the investigation of the cause of the defect. Then, the process moves on to step S7.

[0111] In this way, the semiconductor wafer SW inspection apparatus 1, inspection method, and storage unit 92 according to the fourth embodiment can obtain the same effects as in the first embodiment.

[0112] Furthermore, in the fourth embodiment, the inspection device 1 changes the inspection conditions for semiconductor chips SC that have been determined to be defective compared to before they were determined to be defective. This allows for investigation into the cause of the initial defect determination and enables inspections to be performed according to the lower grade, leading to an improvement in yield.

[0113] Next, the semiconductor wafer SW inspection apparatus 1 and inspection method according to the fifth embodiment will be described. The semiconductor wafer SW inspection apparatus 1 and inspection method according to the fifth embodiment are similar to those of the first embodiment, but differ in some respects. The differences from the first embodiment will be explained below.

[0114] Figure 21 is a schematic diagram showing a probe card 30 of a semiconductor wafer SW inspection apparatus 1 according to the fifth embodiment. As shown in Figure 21, in the fifth embodiment, the probe card 30 has N measurement sites 32 (for example, "2" in Figure 21) arranged in M ​​columns (M is an integer of 2 or more, for example, "2" in Figure 21) in a column direction orthogonal to a specific direction. That is, the probe guard 30 has M columns with N measurement sites 32.

[0115] In Figure 21, of the two measurement sites 32 in the first column, one is the first measurement site 32e and the other is the second measurement site 32f. Furthermore, of the two measurement sites 32 in the second column, the other is the third measurement site 32g and the other is the fourth measurement site 32h.

[0116] Figure 22 is a schematic diagram showing another example of the probe card 30 according to the fifth embodiment, where (a) shows the first example, (b) shows the second example, (c) shows the third example, and (d) shows the fourth example.

[0117] As shown in Figure 22(a), the probe guard 30 may have three measurement sites 32 arranged in three rows. Alternatively, as shown in Figure 22(b), the probe guard 30 may have two measurement sites 32 spaced apart in a specific direction (see Figure 21) rather than adjacent to each other, and two rows of measurement sites 32 spaced apart in the column direction (see Figure 21). In other words, the probe guard 30 may have two measurement sites 32 arranged in two rows with spacing in both the specific direction and the column direction.

[0118] Furthermore, as shown in Figure 22(c), the probe guard 30 may have three measurement sites 32 arranged in two rows. Also, as shown in Figure 22(d), the probe guard 30 may have three measurement sites 32 arranged adjacent to each other in a specific direction, with the measurement sites 32 spaced apart in the row direction. That is, the probe guard 30 may have three measurement sites 32 arranged in two rows with spacing only in the row direction. Note that the probe guard 30 may also have measurement sites 32 that are spaced apart only in a specific direction and adjacent in the row direction.

[0119] Figure 23 is a schematic diagram showing the inspection process, including re-examination, according to the fifth embodiment. In Figure 23, the number of semiconductor chips SC in a specific first row is assumed to be 14, and the number of semiconductor chips SC in a specific second row is assumed to be 16. Furthermore, the semiconductor chips SC shown in Figure 23 are assigned coordinate numbers 1, 2, 1 to 16 in the specific direction and column direction. In addition, multiple measurement sites 32 are assumed to be able to simultaneously contact four adjacent 2x2 semiconductor chips SC, and the number of re-examinations is assumed to be one.

[0120] First, as shown in Figure 23(a), in the first inspection, the contact position determination unit 91 decides to make contact between the probe card 30 and the semiconductor chips SC at coordinates (1,2), (2,1), and (2,2). In this case, there is no semiconductor chip SC at coordinate (1,1), and no contact is made with the first measurement site 32e. Then, the inspection is performed. Assume that all semiconductor chips SC are judged to be good in the first inspection.

[0121] Next, as shown in Figure 23(b), in the second inspection, the contact position determination unit 91 decides to make contact between the probe card 30 and the semiconductor chip SC at coordinates (1,3), (1,4), (2,3), and (2,4). That is, since there are no semiconductor chip SCs that were determined to be defective in the first inspection, the contact position determination unit 91 decides to shift the semiconductor chip SC to be made contact next by two positions in the first direction without shifting it in the column direction. Then the inspection is performed. Suppose that in the second inspection, only the semiconductor chip SC at coordinate (1,4) is determined to be defective.

[0122] Next, as shown in Figure 23(c), in the third inspection, the contact position determination unit 91 decides to bring the probe card 30 into contact with the semiconductor chips SC at coordinates (1,4), (1,5), (2,4), and (2,5). That is, the contact position determination unit 91 decides that the semiconductor chip SC at coordinate (1,4), which was determined to be defective in the second inspection, will come into contact with the measurement site 32 located furthest to the second direction (i.e., the first measurement site 32e). As a result, the semiconductor chip SC at coordinate (1,4) is re-inspected, and the semiconductor chip SCs at coordinates (1,5) and (2,5) undergo their initial inspection. Let's assume that the semiconductor chip SC at coordinate (1,4) is again determined to be defective, and the semiconductor chip SCs at coordinates (1,5) and (2,5) are determined to be good.

[0123] Subsequently, as shown in Figure 23(d), in the fourth inspection, the contact position determination unit 91 decides to bring the probe card 30 into contact with the semiconductor chips SC at coordinates (1,6), (1,7), (2,6), and (2,7). In the example shown in Figure 23, the number of re-inspections is one. Therefore, no further re-inspection is performed on the semiconductor chip SC at coordinate (1,4), which was determined to be defective in the re-inspection. Thus, in the fourth inspection, the contact position determination unit 91 decides to bring the probe card 30 into contact with the semiconductor chips SC at coordinates (1,6), (1,7), (2,6), and (2,7) by shifting it two positions in the first direction without shifting it in the column direction. Then, the inspection is performed. Suppose that in the fourth inspection, the semiconductor chip SC at coordinates (2,6) and (2,7) is determined to be defective, and the semiconductor chip SC at coordinates (1,6) and (1,7) is determined to be good.

[0124] Next, as shown in Figure 23(e), in the fifth inspection, the contact position determination unit 91 decides to bring the probe card 30 into contact with the semiconductor chips SC at coordinates (1,6), (1,7), (2,6), and (2,7). That is, the contact position determination unit 91 decides that the semiconductor chip SC at coordinates (2,6) and (2,7), which was determined to be defective in the fourth inspection, will come into contact with the measurement site 32 (i.e., the third measurement site 32g) located furthest to the second direction. At this time, the contact position determination unit 91 determines the contact position without shifting in the column direction. Then, the inspection is performed. In the fifth inspection, the semiconductor chip SC at coordinate (2,6) is determined to be good, but the semiconductor chip SC at coordinate (2,7) is determined to be defective again.

[0125] Next, as shown in Figure 23(f), in the sixth inspection, the contact position determination unit 91 decides to bring the probe card 30 into contact with the semiconductor chips SC at coordinates (1,8), (1,9), (2,8), and (2,9). In the example shown in Figure 23, the number of re-inspections is one. Therefore, although the semiconductor chip SC at coordinate (2,7) was determined to be defective in the fifth inspection, no further re-inspection is performed. Thus, in the sixth inspection, the contact position determination unit 91 decides to bring the probe card 30 into contact with the semiconductor chips SC at coordinates (1,8), (1,9), (2,8), and (2,9) by shifting it two positions in the first direction without shifting it in the column direction. The inspection is then performed. Assume that all semiconductor chips SC are determined to be good in the sixth inspection. Thereafter, the same sequential inspection method is performed on the two rows of semiconductor chips SC as described above.

[0126] Next, we will explain the simulation results regarding the number of contacts. Figure 24 is a plan view showing the semiconductor wafer SW used in the simulation according to the fifth embodiment. The simulation calculated the number of contacts of the probe card 30 when inspecting all of the semiconductor chips SC, which are formed in a grid pattern with a maximum of 34 chips in a specific direction and 42 columns in the column direction, as shown in Figure 24.

[0127] The arrangement of measurement sites 32 on the probe card 30 used in the simulation included a 2x2 configuration with a total of 4 sites as shown in Figure 21, a 3x2 configuration with a total of 6 sites as shown in Figure 22(c), a 3x3 configuration with a total of 9 sites as shown in Figure 22(a), and a 3x2 configuration with a total of 6 sites spaced apart in the column direction as shown in Figure 22(d). The configuration shown in Figure 22(d) will be referred to as an irregular 3x2 configuration.

[0128] Furthermore, the simulation used four initial inspection good chip rates: 95%, 90%, 85%, and 80%, and initially defective chips were randomly assigned. Each trial consisted of 1000 runs, with one re-inspection. The contact count was evaluated by the ratio of the reduction in the number of contacts by the fifth embodiment to the total number of contacts by the conventional method, which involves initial and re-inspection of predetermined contact positions. A higher value indicates a greater reduction in the number of contacts by the fifth embodiment.

[0129] Figure 25 is a chart showing the simulation results according to the fifth embodiment, and Figure 26 is a graph showing the simulation results according to the fifth embodiment. First, for the measurement sites 32 arranged in a 2x2 configuration, the reduction rates of the total number of contacts were 2.28%, 4.62%, 6.03%, and 6.86% for initial good product rates of 95%, 90%, 85%, and 80%, respectively.

[0130] Furthermore, for the 3x2 arrangement of measurement sites 32, the reduction rates of the total number of contacts were 6.88%, 9.85%, 11.31%, and 11.72% for initial good product rates of 95%, 90%, 85%, and 80%, respectively. For the 3x3 arrangement of measurement sites 32, the reduction rates of the total number of contacts were 9.22%, 11.80%, 12.40%, and 11.95% for initial good product rates of 95%, 90%, 85%, and 80%, respectively.

[0131] Furthermore, for measurement sites 32 arranged in an irregular 3x2 configuration, the reduction rates of the total number of contacts were 6.87%, 9.89%, 11.20%, and 11.79% for initial good product rates of 95%, 90%, 85%, and 80%, respectively.

[0132] Thus, it was found that the total number of contacts decreases in all cases of the measurement site 32. Therefore, even when N measurement sites 32 are provided in M ​​columns, the total number of contacts decreases, and it was found that inspection time and manufacturing costs can be reduced.

[0133] Figure 27 is a flowchart showing the semiconductor wafer SW inspection method according to the fifth embodiment. In Figure 27, the measurement site 32 is assumed to be 2x2. As shown in Figure 27, first the control unit 90 performs initial setup as in the first embodiment and sets the variable n to "1" (S1).

[0134] Next, the control unit 90 determines that the rows to be inspected are n to n+1 (n+M-1) rows (S19). Then, the contact position determination unit 91 determines that it will contact a maximum of N × M rows of semiconductor chips SC by bringing into contact the semiconductor chip SC furthest to the second direction among the n to n+1 rows with the measurement site 32 furthest to the second direction (S20). After that, the processes in steps S4 to S6 are executed.

[0135] If there are defective products (S5: YES) and the number of re-inspections has not reached the maximum value (S6: NO), the contact position determination unit 91 determines that the semiconductor chip SC on the second side of the defective product should make contact with the measurement site 32 on the second side (S21). In this case, the contact position determination unit 91 determines the contact position without shifting the measurement sites 32 in the column direction. Then the process moves on to step S23.

[0136] On the other hand, if there are no defective products (S5: NO), or if the number of re-inspections has reached the maximum value (S6: YES), the contact position determination unit 91 decides to move two units (N units) in the first direction to make contact (S22). In this case as well, the contact position determination unit 91 determines the contact position without shifting the measurement site 32 in the column direction.

[0137] In step S23, the control unit 90 determines whether the inspection has been completed for all semiconductor chips SC in rows n to n+1 (S23). In the inspection method according to the fifth embodiment, if the inspection has been completed for all semiconductor chips SC in row n, the number of semiconductor chips SC that make contact with the measurement site 32 at the positions determined by the contact position determination unit 91 (i.e., the positions in steps S21 and S22) will be zero.

[0138] If the inspection of all semiconductor chips SC in columns n to n+1 is not completed (S23:NO), that is, if the measurement site 32 makes contact with any semiconductor chip SC at a position determined by the contact position determination unit 91, the process proceeds to step S4.

[0139] On the other hand, if the inspection of all semiconductor chips SC in columns n to n+1 is completed (S23: YES), the control unit 90 adds "2 (i.e., M)" to the variable n (S24). Then, the control unit 90 checks if the variable n is n max Determine if it exceeds (S13).

[0140] The variable n is nmax If it does not exceed (S13: NO), the process proceeds to step S19. On the other hand, when the variable n exceeds n max (S13: YES), the control unit 90 determines whether the variable n is n max +1 (S25). When the variable n is n max +1 (S25: YES), it can be said that only the semiconductor chips SC in the n max th column are in the uninspected state. Therefore, the control unit 90 subtracts only "1" from the variable n (S26), and the process proceeds to step S19. As a result, the inspection apparatus 1 for the semiconductor wafer SW according to the fifth embodiment suppresses a situation where the measurement sites 32 protrude in the column direction. That is, the inspection apparatus 1 for the semiconductor wafer SW according to the fifth embodiment has the probe guard 30 having M columns of measurement sites 32 and inspects from one end to the other end in the column direction. In this case, when the semiconductor chips SC to be inspected in the latter half of the inspection are less than M columns, the contact position determination unit 91 determines the contact position so that the measurement site 32 at the most other end side in the column direction and the semiconductor chip SC in the most other end column in the column direction contact each other.

[0141] On the other hand, when the variable n is not n max +1 (S25: NO), since the inspection has been performed up to the semiconductor chips SC in the n max th column, the process shown in FIG. 27 ends.

[0142] In the fifth embodiment, the control unit 90 may execute the same processes as in steps S9 and S10 after the process of step S23. In this case, the control unit 90 checks whether the semiconductor chip SC on the most first direction side among the contacting semiconductor chips SC and the measurement site 32 on the most first direction side are in contact. Then, when the semiconductor chip SC on the most first direction side and the measurement site 32 on the most first direction side are not in contact, the contact position determination unit 91 shifts the contact position to the second direction side so that they are in contact.

[0143] In this way, the semiconductor wafer SW inspection apparatus 1, inspection method, and storage unit 92 according to the fifth embodiment can achieve the same effects as the first embodiment. In particular, the fifth embodiment provides a semiconductor wafer SW inspection apparatus 1 that can reduce the number of contacts even when there are N measurement sites 32 in M ​​rows, thereby reducing inspection time and manufacturing costs.

[0144] Although the present disclosure has been described above based on embodiments, the present disclosure is not limited to the above embodiments, and modifications may be made without departing from the spirit of the present disclosure, and known technologies, well-known technologies, or other technologies may be combined as appropriate to the extent possible. Furthermore, technologies from different embodiments may be combined as appropriate to the extent possible.

[0145] Furthermore, the flowcharts shown in Figures 15, 18-20, and 27 above are merely examples, and the order and content of the processing may be changed as appropriate, as long as they do not deviate from the main purpose.

[0146] Furthermore, although Figure 4 shows the probe card 30 configured to perform inspections on four consecutive semiconductor chips SC, it is not limited to four consecutive semiconductor chips SC; a configuration with gaps between some chips, resulting in discontinuity, is also possible.

[0147] Furthermore, for the inspection of semiconductor chips (SC), the zigzag motion shown in Figure 5 is not mandatory. Inspection may always be performed from a specific direction, or it may involve a mix of directions, such as performing two rows from one direction to the other, followed by one row from the other to the first. In addition, inspection may be performed while specifying any row. [Explanation of symbols]

[0148] 1: Semiconductor wafer inspection equipment 30: Probe card 31: Probe 32: Multiple measurement sites 32a, 32e: First measurement site 32b, 32f: Second measurement site 32c, 32g: Third measurement site 32d, 32h: 4th measurement site 80: Semiconductor tester (tester) 90: Control Unit 91: Contact position determination unit (determination means) 92: Memory unit (recording medium) P: Prova PA: Forbidden area PC: Prohibited chips SC: Multiple semiconductor chips SW: Semiconductor wafer

Claims

1. At least N measurement sites (where N is an integer greater than or equal to 2) arranged in a specific direction, A tester that makes N measurement sites contact multiple semiconductor chips formed on a semiconductor wafer and arranged in the specified direction, and inspects the N semiconductor chips that are in contact, The system includes a determination means for determining which semiconductor chip to contact the N measurement sites among a plurality of semiconductor chips, The aforementioned determination means is If none of the N semiconductor chips inspected are found to be defective, it is decided to shift the next semiconductor chip to be contacted by N chips in the first direction, which is one of the specified directions. If any of the N semiconductor chips inspected are determined to be defective, the next semiconductor chip to be made to contact is determined to be the one located furthest to the second direction (the other direction from the specified direction) among the defective semiconductor chips, and the one located furthest to the second direction among the N measurement sites. A semiconductor wafer inspection apparatus characterized by the following features.

2. When the determination means determines which semiconductor chips to contact next, if the number of semiconductor chips to contact is less than N, it adjusts the contact position by shifting the next N semiconductor chips to contact in the second direction by the number of chips that are missing. The semiconductor wafer inspection apparatus according to feature 1.

3. When the determination means determines which semiconductor chip to contact next, if it would accidentally contact a prohibited chip (a semiconductor chip that is prohibited from being contacted), it adjusts the contact position so that the end of the N measurement sites in the first direction makes contact with the semiconductor chip adjacent to the prohibited chip in the second direction, or so that the end of the N measurement sites in the second direction makes contact with the semiconductor chip adjacent to the prohibited chip in the first direction. The semiconductor wafer inspection apparatus according to feature 1.

4. The determination means, if the number of semiconductor chips located in the first or second direction of the prohibited chip is less than N, designates the prohibited chip and the fewer than N semiconductor chips as a prohibited area, or, if there are other prohibited chips among the N semiconductor chips located in the first or second direction of the prohibited chip, designates the two prohibited chips and the semiconductor chip between them as a prohibited area, and adjusts the contact position to avoid the prohibited area. The semiconductor wafer inspection apparatus according to feature 3.

5. The determination means, if any of the N semiconductor chips inspected are determined to be defective, adjusts the contact position so that a measurement site different from the one that contacted the defective semiconductor chip makes contact with the defective semiconductor chip. The semiconductor wafer inspection apparatus according to feature 1.

6. If any of the N semiconductor chips tested by the tester are determined to be defective, the tester changes the test conditions for the defective semiconductor chip compared to before it was determined to be defective. The semiconductor wafer inspection apparatus according to feature 1.

7. The N measurement sites are arranged in M ​​columns (where M is an integer of 2 or more) in a column direction perpendicular to the specific direction. The tester can inspect N x M semiconductor chips in contact with a plurality of semiconductor chips formed on a semiconductor wafer and arranged in the specific direction and the row direction by making contact with the M rows and N measurement sites. The aforementioned determination means is When a semiconductor chip is selected from among multiple semiconductor chips to be in contact with the M rows and N measurement sites, and N x M rows of semiconductor chips are inspected, If no semiconductor chips are found to be defective among the N x M rows of semiconductor chips that were inspected, it is decided to shift the next semiconductor chip to be made contact by N units in a first direction, which is one of the specified directions, without shifting it in the row direction. When any of the N x M rows of semiconductor chips that have been inspected are determined to be defective, the next semiconductor chip to be made to contact is determined to be the one located furthest to the second direction (the direction other than the specified direction) among the defective semiconductor chips, without shifting it in the direction of the rows, so that it makes contact with the one located furthest to the second direction among the M rows and N measurement sites. The semiconductor wafer inspection apparatus according to feature 1.

8. A method for inspecting a semiconductor wafer, comprising: N measurement sites (where N is an integer of 2 or more) arranged in at least a specific direction; and a tester that brings the N measurement sites into contact with a plurality of semiconductor chips formed on a semiconductor wafer and arranged in the specific direction, and inspects the N semiconductor chips in contact; The process includes a determination step of determining which semiconductor chip will be in contact with the N measurement sites from among a plurality of semiconductor chips. In the aforementioned decision process, If none of the N semiconductor chips inspected are found to be defective, it is decided to shift the next semiconductor chip to be contacted by N chips in the first direction, which is one of the specified directions. If any of the N semiconductor chips inspected are determined to be defective, the next semiconductor chip to be made to contact is determined to be the one located furthest to the second direction (the other direction from the specified direction) among the defective semiconductor chips, and the one located furthest to the second direction among the N measurement sites. A method for inspecting semiconductor wafers, characterized by the following features.

9. A computer-readable recording medium on which an inspection program for causing a computer to function as a semiconductor wafer inspection apparatus as described in claim 1 is recorded.

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