Semiconductor equipment

Abstract

To provide a semiconductor device to reduce time for rewriting data in memory cells.SOLUTION: A memory module 10 includes a first memory cell MC[1], a second memory cell MC[2], a selection transistor DTr, and a wiring WBL1. Each memory cell has a memory node electrically connected to either a source or a drain of a transistor WTr, a gate of a transistor RTr, and one of electrodes of a capacitive element CS. One side of the first memory cell is electrically connected to the wiring via the selection transistor, the other side of the first memory cell is electrically connected to one side of the second memory cell, and the other side of the second memory cells is electrically connected to the wiring WBL1. The memory node of the first memory cell is rewritten by a signal applied to the wiring via the selection transistor when the selection transistor is in an on state, and is rewritten by a signal applied to the wiring via the memory node of the second memory cell when it is in an off state.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to semiconductor devices and electronic equipment.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the technical field relates to a product, method, or method of manufacture. Alternatively, the present invention relates to a process , relating to machines, manufacturers, or compositions of matter In particular, one aspect of the present invention relates to a semiconductor device, a display device, a light-emitting device, an energy storage device, a memory device, and This relates to methods for driving them, or methods for manufacturing them.

[0003] In this specification, a semiconductor device is defined as an element that can function by utilizing semiconductor properties. This refers to a component, circuit, or device. Examples include semiconductor elements such as transistors and diodes. It is a semiconductor device. Another example is a circuit having semiconductor elements, which is a semiconductor device. Yes. Another example is a device equipped with a circuit having semiconductor elements, which is a semiconductor device. ru. [Background technology]

[0004] Mobile devices such as smartphones, tablets, and e-books, and personal computers Electronic devices, such as servers and other semiconductor devices, are required to handle large amounts of data. Therefore, semiconductor devices are required to have a large memory capacity and high processing speed. It is being done.

[0005] In particular, in recent years, the aforementioned electronic devices have applications that handle high-definition images, videos, and audio. As the number of operations increases, the amount of data being handled also increases. Therefore, semiconductors with large memory capacity are needed. A semiconductor device is needed. Patent document 1 describes a semiconductor device in which memory cells are stacked three-dimensionally. The location is disclosed. In addition, a large memory capacity can be achieved without changing the size of the semiconductor device chip. To realize semiconductor devices with high volume, technologies for miniaturizing the circuits contained in the semiconductor device are required. It is being done. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2008-258458 [Overview of the project] [Problems that the invention aims to solve]

[0007] Applications that run on electronic devices require an internet or network connection. This requires the ability to comfortably handle large amounts of data such as images and audio. Electronic devices, such as mobile devices, are characterized by their portability, and in order to enable long-term use, electricity Reducing power consumption is a challenge. In electronic devices, power gating and other power reduction measures are used to reduce power consumption. Power reduction technologies can be used. However, power reduction technologies such as power gating can be used. This presents a problem: it requires backing up data currently in use.

[0008] For example, in NAND flash memory, which is known as a semiconductor device, data To rewrite the data, it is also necessary to update data at addresses other than the one specified. Therefore, NAND flash memory and the like require processing time to write large amounts of data. A large amount of data is required, and there is also the challenge that power consumption increases in proportion to the amount of data.

[0009] In view of the above problems, one aspect of the present invention aims to provide a memory device with a novel configuration. Or, one aspect of the present invention aims to provide a memory device with a shortened rewrite time. Or, one aspect of the present invention aims to provide a memory device that reduces power consumption. These are regarded as one of the problems.

[0010] Note that the description of these problems does not preclude the existence of other problems. One aspect of the present invention is not required to solve all of these problems. Other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

[0011] Note that the problems of one aspect of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Other problems are those not mentioned in this section described below. Problems not mentioned in this section can be derived by those skilled in the art from the description in the specification or drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention solves at least one of the problems listed above and / or other problems.

Means for Solving the Problems

[0012] One aspect of the present invention is a semiconductor device having a memory module, and the memory module has a first memory cell, a second memory cell, a selection transistor, and a first wiring. The first memory cell has a first memory node, the second memory cell has a second memory node, and one of the first memory cells is electrically connected to the first wiring via the selection transistor. The other end of the first memory cell is electrically connected to the other end of the second memory cell, The other end of the second memory cell is electrically connected to the first wiring, and the first memory node and Memory node 2 has the function of holding voltage as a signal, and the select transistor is ON. When in this state, the first memory node receives the signal that is given to the first wiring via the selection transistor. The second memory node has the function of being rewritten by a number, and the second memory node is a selection transistor, The function is rewritten by a signal applied to the first wiring via the first memory node. And when the selection transistor is in the off state, the first memory node is the second memory node It has the function of being rewritten by a signal given to the first wiring via the second The molynode has the function of being rewritten by the signal applied to the first wiring. This is a semiconductor device with distinctive features.

[0013] In the above configuration, the memory module further comprises a second wiring, a third wiring, and a fourth The first memory cell has a wiring, and further comprises a first transistor and a first capacitive element. The second memory cell further comprises a second transistor and a second capacitive element. The first memory node has either the source or the drain of the first transistor, and the first The second memory node is formed by being electrically connected to one of the electrodes of the capacitive element, , between the source or drain of the second transistor and one of the electrodes of the second capacitive element Formed by electrical connection, one of the sources or drains of the selected transistor is The first wiring is electrically connected, and the source or drain of the select transistor is the other of the first The memory node is electrically connected, and the gate of the selected transistor is electrically connected to the fourth wiring. The source or drain of the first transistor is connected to the second memory node. Electrically connected, the gate of the first transistor is electrically connected to the second wiring, and the The source or drain of the two transistors is electrically connected to the first wiring, and the second The gate of the transistor is electrically connected to a third wire, characterized in that the semiconductor device It is preferable to place it there.

[0014] In the above configuration, the memory module further has a fifth wiring and the first memory One side of the wire is electrically connected to the fifth wire via a selection transistor, and the selection transistor When the terminal is ON, the first memory node supplies the fifth wiring via the selection transistor. It has the function of being rewritten by the signal received, and the second memory node is connected to the first wiring A semiconductor device is preferred that has the function of being rewritten by a given signal. It's nice.

[0015] In the above configuration, the first transistor, the second transistor, or the selected transistor A semiconductor device having a metal oxide in the semiconductor layer is preferred.

[0016] In the above configuration, the semiconductor layer of the first transistor is the semiconductor layer of the second transistor. A semiconductor device characterized by being formed within the same opening is preferred.

[0017] In the above configuration, the transistor having a metal oxide in the semiconductor layer is a back gate A semiconductor device having the following characteristics is preferred.

[0018] An electronic device having the semiconductor device described above and a housing is preferred. [Effects of the Invention]

[0019] One aspect of the present invention can provide a storage device with a novel configuration. Or, one aspect of the present invention One embodiment can provide a storage device with reduced rewrite time. Or, one embodiment of the present invention The embodiment can provide a storage device that reduces power consumption.

[0020] The effects of one embodiment of the present invention are not limited to those listed above. This does not preclude the existence of other effects. These other effects are described in the following section. This is an effect not mentioned in the specification. Effects not mentioned in this section can be described in the specification or by those skilled in the art. This can be derived from drawings and other descriptions, and can be extracted as appropriate from these descriptions. Furthermore, one aspect of the present invention includes, among the effects listed above and / or other effects, at least It has one effect. Therefore, one aspect of the present invention may, in some cases, be the above row It may not always have the effects mentioned. [Brief explanation of the drawing]

[0021] [Figure 1] A circuit diagram showing an example configuration of a semiconductor device. [Figure 2] A circuit diagram showing an example configuration of a semiconductor device. [Figure 3] A timing chart illustrating an example of the operation of a semiconductor device. [Figure 4] A timing chart illustrating an example of the operation of a semiconductor device. [Figure 5] A timing chart illustrating an example of the operation of a semiconductor device. [Figure 6] A circuit diagram showing an example configuration of a semiconductor device. [Figure 7] A timing chart illustrating an example of the operation of a semiconductor device. [Figure 8] A timing chart illustrating an example of the operation of a semiconductor device. [Figure 9] A block diagram showing an example of a storage device. [Figure 10] A circuit diagram showing an example configuration of a semiconductor device. [Figure 11] A circuit diagram showing an example configuration of a semiconductor device. [Figure 12] A circuit diagram showing an example configuration of a semiconductor device. [Figure 13] A top view and a cross-sectional view illustrating an example configuration of a semiconductor device. [Figure 14] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 15] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 16] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 17] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 18] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 19] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 20] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 21] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 22] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 23] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 24] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 25] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 26] A cross-sectional view illustrating an example of semiconductor device fabrication. [Figure 27] A cross-sectional diagram illustrating a semiconductor device. [Figure 28] A cross-sectional diagram illustrating a semiconductor device. [Figure 29] A cross-sectional diagram illustrating a semiconductor device. [Figure 30] A diagram illustrating the range of atomic ratios for metal oxides. [Figure 31] A block diagram explaining the CPU. [Figure 32] A perspective view showing an example of an electronic device. [Figure 33] A perspective view showing an example of an electronic device. [Modes for carrying out the invention]

[0022] (Embodiment 1) In this embodiment, a semiconductor device that shortens the rewrite time of memory cells is shown in Figures 1 to This will be explained using Figure 7.

[0023] First, the circuit configuration of the semiconductor device will be explained with reference to Figure 1(A). Figure 1(A The semiconductor device shown is a memory module 10 having n memory cells. Module 10 includes memory cells MC[1] to MC[n], a selection transistor DTr, and a distribution Line WWL_D, wiring WWL[1] to WWL[n], wiring RWL[1] to RWL[n] It has wiring WBL1, wiring RBL1, and wiring RBL2. Note that wiring WWL (wiring W WL[1] to WWL[n]) function as rewrite word lines, and wiring RWL (wiring RW L[1] to RWL[n]) function as read word lines, and wiring WBL1 is rewritten. RBL1 and RBL2 function as read bit lines, with RBL1 functioning as a bit line. n is an integer greater than or equal to 2.

[0024] Figure 1(A) shows an example where memory cells MC[1] to MC[n] are connected in series. There is. At one end of any of the series-connected memory cells MC[1] to MC[n], It is preferable that the selection transistor DTr is connected. In Figure 1(A), the selection transistor This shows an example where a DTR is connected to a memory cell MC[1].

[0025] Each memory cell consists of a transistor WTr, a transistor RTr, a capacitive element CS, It also has memory nodes. Transistor WTr is a rewrite transistor. Therefore, transistor RTr functions as a readout transistor.

[0026] A memory node consists of either the source or drain of transistor WTr and transistor R It is formed by electrically connecting the gate of the transistor (Tr) to one of the electrodes of the capacitive element (CS). The gate of transistor WTr is electrically connected to the wiring WWL, and the power of the capacitive element CS The other end of the pole is electrically connected to the wiring RWL. Transistor of memory cell MC[1] The source or drain of the WTr is connected in series with the memory cell MC[1]. It is electrically connected to the memory node of the memory cell MC[2].

[0027] Either the source or drain of the selection transistor DTr is electrically connected to wiring WBL1. The source or drain of the selection transistor DTr is the other of the memory cell MC[1] The gate of the selected transistor DTr, which is electrically connected to the memory node, is wired to WWL_D. It is electrically connected to the transistor WTr of the memory cell MC[n] The source or drain, or the other, is electrically connected to wiring WBL1. In other words, in series. One end of a series of connected memory cells is connected to the selection transistor DTr and wiring WBL1. It is electrically connected to the other end of a series of memory cells.

[0028] The source or drain of the transistor RTr in the memory cell MC[1] is Electrically connected to line RBL2, the transistor RTr of memory cell MC[1] The other of the drain or the other is the transistor of the series-connected memory cell MC[2] It is electrically connected to either the source or drain of the RTr. The source or drain of transistor RTr in [n] is connected to wiring RBL1 and electrical They are connected in series. In other words, wiring RBL1 is connected to the memory cells that are connected in series. It is electrically connected to wiring RBL2 via transistor RTr.

[0029] In the configuration of the memory module 10 described above, memory cell MC[1] to memory cell To rewrite the data in any one of the MC[n] memory cells connected in series, It can be rewritten via the transistor WTr and the memory node. However, note To rewrite the data of the nearest memory cell MC[j] from the recell MC[1], select a tracer It is preferable that data is supplied from the wiring WBL1 via the inverter DTr, and the memory To rewrite the data of memory cell MC[j] that is close to memory cell M, It is preferable that data is supplied from wiring WBL1 connected to C[n]. j is 1 or less. It is an integer less than or equal to n.

[0030] For memory module 10 with a different circuit configuration than that shown in Figure 1(A), refer to Figure 1(B). Let me explain. The transistor WTr shown in Figure 1(B) is a transistor with a small off-current. It is preferable that it be a transistor. Transistor WTr is a transistor with a small off-current. By using this method, the independence of data held in adjacent memory nodes can be ensured. Furthermore, transistor WTr may be a transistor with a back gate. By applying a voltage to the gate, the threshold of the transistor WTr can be controlled. Note that the wiring BGL shown in Figure 1(B) is connected to each of the memory cells MC[1] to M The back gate of the WTr transistor in the Morissel MC[n] is electrically connected. Furthermore, the selection transistor DTr, like the transistor WTr, has a back gate. It is preferable that they be present.

[0031] Unlike the example shown in Figure 1(B), the wiring BGL is connected to the memory cell MC[1] or memory cell. The back gates of the transistors WTr in MC[n] are each electrically connected independently. Alternatively, each component may be configured to supply a different potential.

[0032] The channel formation region of the transistor WTr has a metal oxide as described in Embodiment 3. It is preferable to use indium, element M (for example, aluminum) In the case of metal oxides selected from one or more of the following (gallium, yttrium, tin, etc.) and zinc. Because the metal oxide functions as a wide-bandgap semiconductor, the metal oxide is cha Transistors contained within the Nell-formed region have the characteristic of having a very low off-current. A transistor with low off-current characteristics is used for the WTr transistor that controls data retention. By applying this, the memory cell MC can retain data for a long time. This reduces the number of times the retained data needs to be refreshed, thus reducing the consumption of semiconductor devices. It can reduce power consumption.

[0033] Furthermore, the channel formation region of transistor RTr is the field-effect transfer of the transistor. It is preferable to use materials with a high degree of conductivity. By using such transistors, semiconductors The device can operate more quickly. For example, the channel formation region of the transistor RTr. Materials included in the region include semiconductors such as metal oxides and silicon, as described in Embodiment 3. It can have materials.

[0034] For a memory module 10 with a different circuit configuration from Figure 1(B), refer to Figure 1(C). Let me explain. In Figure 1(C), the transistor RTr also has a back gate. It is a transistor, and by applying a voltage to the back gate, the threshold of the transistor RTr is controlled. It can be controlled. Note that the wiring BGL shown in Figure 1(C) is for each memory The transistors RTr and W of memory cell MC[1] to memory cell MC[n] This shows an example of an electrical connection to the back gate of a transistor.

[0035] Using metal oxides in the channel formation region of transistors RTr and WTr As a result, the memory module 10 is formed above the transistors formed on the silicon substrate. This can be achieved. Therefore, to provide a semiconductor device with a high information density per unit area. It is possible.

[0036] Unlike the example shown in Figure 1(C), the wiring BGL is connected to the memory cell MC[1] or memory cell. The back gates of transistors RTr and WTr in MC[n] are They may be electrically connected independently, and each may supply a different potential. Figure 1 (A) Although not shown in the diagram, the circuit configuration also includes a back gate for transistor RTr. good.

[0037] The semiconductor device shown in Figure 2 has the memory module 10 shown in Figure 1(C) arranged in a row, m These are arranged in a row, and the RWL and WWL wirings are shared with the memory cell MC in the same row. The configuration is electrically connected in such a way. In other words, the semiconductor device shown in Figure 2 has n rows A semiconductor device that can be represented in two dimensions with m rows, such as memory cell MC[1,1] or memory cell MC It has [m,n]. In Figure 2, although not shown for the sake of simplicity, the depth d is By providing this, the semiconductor device creates a three-dimensional memory cell MC[1,1,1] or memory cell MC[ It can have m,n,d. In Embodiment 2, the semiconductor device is a three-dimensional memory cell. Detailed explanation of examples having memory cells MC[1,1,1] to MC[m,n,d] Do the following: m, n, or d are integers greater than or equal to 2.

[0038] The semiconductor device shown in Figure 2 has wiring WWL_D, wiring RWL[1] to wiring RWL[n], Wiring WWL[1] to WWL[n], wiring RBL1[1] to RBL1[m], Wiring RBL2[1] to Wiring RBL2[m], Wiring WBL1[1] to Wiring WBL1[m] ], and wiring BGL[1] to wiring BGL[m].

[0039] Specifically, the other electrode of the capacitive element CS of the memory cell MC[i,j] (not shown) is The transistor WTr of the memory cell MC[i,j] is electrically connected to the wiring RWL[j]. The gate is electrically connected to wiring WWL[j]. Wiring WBL1[i] is selected The source or drain of transistor DTr[i] and memory cell MC[i,n] The source or drain of transistor WTr is electrically connected to the other. Wiring RB L1[i] is the source or drain of the transistor RTr of the memory cell MC[i,n]. It is electrically connected to the other side. Wiring RBL2[i] is connected to memory cell MC[i,1] It is electrically connected to either the source or drain of the transistor RTr. i is 1 or greater than m The following integers are given, where j is an integer between 1 and n (inclusive).

[0040] The data structure stored in the memory module of the semiconductor device shown in Figure 2 is as follows: It is preferable to represent it as a bit, which is the smallest unit. For example, row 1, row 2, n-1 The operation of rewriting the data in the nth and nth rows will be explained by referring to the timing chart in Figure 3. I will reveal it.

[0041] In T11, the selection transistor DTr[1 ] or DTr[m] is turned ON. Furthermore, “H” is given to the wiring WWL[1]. As a result, the transistor WTr of the memory cell MC[1,1] or MC[m,1] It turns on. Wiring WBL1[1] to WBL1[m] is connected to the selection transistor DTr[ Data D[2] is sent to memory cells MC[1,2] to MC[m] via 1] to DTr[m]. It can be given to the memory node m,2]. At this time, the memory cell MC[1,1] The memory node to MC[m,1] is also given data D[2]. Data D is m Digital data having a data width of bits is preferred. Alternatively, data D may contain analog data. Data may be provided. Analog data is preferably controlled by voltage. If each bit can have different analog data, the data that the semiconductor device can store The amount of data can be dramatically improved.

[0042] In T12, the wire WWL[1] is given “L”, which is the memory cell MC[1,1] The transistor WTr in MC[m,1] is turned off. Therefore, the memory cell The memory nodes of MC[1,2] through MC[m,2] hold the data D[2]. Furthermore, the data D[1] given to the wiring WBL1[1] to WBL1[m] is, Memory cells MC[1,1] through the selection transistors DTr[1] to DTr[m] The data in the memory node MC[m,1] can be rewritten.

[0043] In T13, the selection transistor DTr[1 ] to DTr[m] are turned off. Therefore, memory cells MC[1,1] to MC[m The memory node owned by [1] holds the data D[1].

[0044] In T14, the wiring WWL[n-1] is given "H", which means that the memory cell MC[ The transistor WTr in [1,n-1] or MC[m,n-1] is turned ON. Furthermore, by assigning "H" to the wiring WWL[n], memory cells MC[1,n] to M The transistor WTr on C[m,n] is turned ON. Wiring WBL1[1] to W The data D[n-1] given to BL1[m] is from memory cell MC[1,n] to MC[ Memory cells MC[1,n-1] to MC[m,n-1] via memory nodes m,n] The data in the memory node can be rewritten.

[0045] In T15, the wiring WWL[n-1] is given “L”, which is how the memory cell MC[1, The transistor WTr in n-1] or MC[m,n-1] is turned off. The memory nodes of memory cells MC[1,n-1] to MC[m,n-1] have Data D[n-1] is held. Furthermore, wiring WBL1[1] to WBL1[m] is By providing the data D[n] to the memory nodes of memory cells MC[1,n] to MC[m,n] It is possible.

[0046] In T16, the memory cell MC[1,n] is created by assigning "L" to the wiring WWL[n]. The transistor WTr in MC[m,n] is turned off. Therefore, the memory cell The memory nodes of MC[1,n] through MC[m,n] hold the data D[n]. It can be done.

[0047] In NAND flash memory, memory cells are connected in series in a memory module. To update any one memory cell, update the data in all rows of the memory module. It is necessary. However, in the configuration shown in this embodiment, data can be accessed from any row of the memory module. Because the data can be rewritten, it can be rewritten at high speed.

[0048] In Figure 4, multiple memory modules of the semiconductor device are connected via wiring WWL, wiring RWL, and The structure of the data connected and stored by line WWL_D is an example with a data width of m columns. I will explain this using an example. For instance, write the data for the first, second, third, (n-1), and nth rows. The switching operation will be explained with reference to the timing chart in Figure 4.

[0049] The basic operation is the same as the operation described in Figure 3, so the explanation will be omitted. Figure 4 is different from Figure 3. Let me explain the points. As an example, Figure 4 explains how to rewrite the data in the third row. To clarify, in a memory module with multiple rows, any row to be rewritten is selected. The first row of memory cells MC, or the nth row of memory cells MC, to which the generator DTr is connected. It is preferable to access from the closer side. The memory cell rewrite time is arbitrary. This corresponds to the number of lines up to the line to be rewritten. Therefore, it is the number of lines up to any line to be rewritten. Accessing from the other side can reduce the rewrite time.

[0050] Note that in Figure 4, multiple memory cells have an m-row configuration. Therefore, rewriting The data provided is the same as the data provided to wiring WBL1[1] to WBL1[m]. It can be rewritten at times. That is, in the configuration shown in this embodiment, the semiconductor device can write any address It can be said that this is a memory device with a data width of m bits relative to the value of S.

[0051] For the operation of reading the data rewritten in Figure 3, please refer to the timing chart in Figure 5. I will explain.

[0052] In T30, the wiring RBL1[1] to RBL1[m] can be initialized to any potential. Yes, it is possible. Also, any data can be stored in the memory cell via the wiring RBL2[1] to RBL2[m]. A reference potential is given to confirm that it is stored. Any potential to initialize is Preferably, the potential is the same as the "L" value in the data, or lower than the "L" value in the data.

[0053] In T31, memory cells MC[1,1] to MC[m, connected to wiring RWL[1] The data stored in [1] can be read. Give “L” to wiring RWL[1]. The remaining wiring RWL[2] through RWL[n] are given "H". Transistor RTr Since they are connected in series, any of the memory cells MC[1,1] to MC[m,1] If the data "H" is stored, then the memory cell M that stores the "H" data A reference potential signal is output to wiring RBL1 in the target column of C.

[0054] Each memory cell MC connected to wiring RWL[2] to RWL[n] is connected to wiring R By assigning "H" to WL[2] through RWL[n], the capacitive element CS is subject to the law of conservation of charge. This allows us to apply a "H" to the gate of transistor RTr. Therefore, in the transistor RTr connected in series, transistors other than the one being read out are not read out. All RTrs are turned on. Therefore, the data of the memory cell to be read is "L". Furthermore, the reference potential applied to wiring RBL2 cannot be output to wiring RBL1. When the data of the memory cell to be read is "H", the reference potential applied to wiring RBL2 is This is output to wiring RBL1. Therefore, memory cells MC[1,1] to MC[m,1 The data stored in [ ] is output to wiring RBL1[1] to RBL1[m].

[0055] In T32, the wires RWL[1] to RWL[n] are assigned “L”, and the wire RBL1 [1] Initialize RBL1[m] to any potential. At this time, wiring RBL2[1] It is preferable that “H” is given to RBL2[m], but even if “L” is given good.

[0056] In T33, memory cells MC[1,2] to MC[m, The data held in [2] can be read. Give "L" to wiring RWL[2]. The other wirings RWL[1], RWL[3] through RWL[n] are assigned the value "H". The explanation is omitted because it is the same as the operation of reading data from wiring RWL[1].

[0057] The operation of T34 is the same as that of T32, so the explanation is omitted. From here on, wiring RWL[3] to R The data stored in the memory cell MC connected to WL[n] can be read. Therefore, data is read sequentially in the row direction of the memory cells MC. It is possible.

[0058] A semiconductor device different from the one shown in Figure 2 will be explained with reference to Figure 6. Figure 2 differs from this one in that it has wiring WBL2. For simplicity of explanation, here is an example. We will explain this using memory module 10 as an example.

[0059] Wiring WBL2 is electrically connected to either the source or drain of the select transistor DTr. Therefore, the memory module 10 has wiring WBL1 and wiring WBL2 Data can be rewritten to the memory cell MC from either one or both.

[0060] In other words, by assigning "H" to wiring WWL_D, wiring WBL2[1] becomes a selected transistor. The data of the memory node MC[1,1] of the memory cell is rewritten via the DTR. This is possible. Also, by assigning "H" to wiring WWL[n], wiring WBL1[1] becomes The data at the memory node of the memory cell MC[1,n] can be rewritten. By simultaneously applying "H" to line WWL[1] and wiring WWL[n], the memory cell MC The data of the memory nodes [1,1] and memory cell MC[1,n] can be rewritten simultaneously. It is possible.

[0061] Using a method different from that shown in Figure 3, write the data for the first, second, (n-1), and nth rows. The switching operation will be explained with reference to the timing chart in Figure 7.

[0062] In T41, the selection transistor DTr[1 ] or DTr[m] is turned ON. And, “H” is given to the wiring WWL[1]. By doing so, the transistor WTr of memory cell MC[1,1] or MC[m,1] is The state becomes [unclear]. Therefore, the data given to the wiring WBL2[1] to WBL2[m] D[2] is connected to memory cell MC[ via selection transistor DTr[1] to DTr[m] The data in 1,2] to MC[m,2] can be rewritten. Data D[2] is also given to MC[1,1] through MC[m,1].

[0063] Furthermore, when "H" is assigned to the wiring WWL[n], the memory cell MC[1,n] The transistor WTr located at MC[m,n] is turned ON. Furthermore, the wiring WWL[n When "H" is assigned to -1], the memory cell MC[1,n-1] or MC[m,n- The transistor WTr in [1] is turned ON. Therefore, the wiring WBL1[1] The data D[n-1] given to WBL1[m] is from the memory cell MC[1,n-1] The data at the memory node MC[m,n-1] can be rewritten. Data D[n-1] is also provided for Morisel MC[1,n] through MC[m,n].

[0064] Therefore, memory cells MC[1,2] to MC[m,2] and memory cells MC[1,n The memory nodes -1] through MC[m,n-1] can have their data overwritten simultaneously.

[0065] In T42, the wiring WWL[1] is given “L”, which is the memory cell MC[1,1] The transistor WTr of MC[m,1] is in the OFF state, and the wiring WWL[ When "L" is given to n-1], the memory cell MC[1,n-1] or MC[m,n- The transistor WTr in [1] turns off. Therefore, memory cell MC[1,2] The memory node that MC[m,2] possesses holds the data D[2], and also memo The memory nodes of the recell MC[1,n-1] to MC[m,n-1] contain data D [n-1] is retained.

[0066] Furthermore, the data D[1] given to the wiring WBL2[1] to WBL2[m] is selected Memory cells MC[1,1] to MC[1,1] via transistors DTr[1] to DTr[m] The data of [m,1] can be rewritten. Furthermore, the wiring WBL2[1] to WBL2 The data D[n] given to [m] is the selected transistor DTr[1] to DTr[m]. The data in memory cells MC[1,n] to MC[m,n] can be rewritten via this method. ru.

[0067] In Figure 8, multiple memory modules of the semiconductor device are connected via wiring WWL, wiring RWL, and The structure of the data connected and stored by line WWL_D is an example with a data width of m columns. I will explain this using an example. For instance, write the data for the first, second, third, (n-1), and nth rows. The switching operation will be explained with reference to the timing chart in Figure 8.

[0068] The basic operation is the same as the operation described in Figure 7, so the explanation will be omitted. Figure 8 is different from Figure 7. Let me explain the point. As an example, in T51, the data in the 2nd row and the (n-1)th row are the same. It can be overwritten at times. Also, in T52, the data in the first and nth lines can be overwritten simultaneously. .

[0069] In a memory module with n rows, for example, if two different rows are to be overwritten, select The first row of memory cells MC, or the nth row of memory cells, to which the select transistor DTr is connected. It is preferable to access each row simultaneously from either side of the MC. Because two lines can be rewritten simultaneously, the rewrite time to the memory cell is further reduced. It can be shortened. Therefore, accessing any line to be rewritten from the nearest side is possible. This allows for a reduction in rewriting time.

[0070] Note that in Figure 8, multiple memory cells have an m-row configuration. Therefore, rewriting The data that can be provided is the data given to wiring WBL1[1] to WBL1[m] and wiring W The data provided to BL2[1] through WBL2[m] is simultaneously rewritten by In other words, in the configuration shown in this embodiment, the semiconductor device has m bits for any address. It can be said that it is a storage device with a data width of [specify data width].

[0071] Figures 6 through 8 show that data is written to any row of a memory module simultaneously from different directions. Because it can be changed, data can be rewritten even faster than with the circuit configuration explained in Figure 2. It is possible to draw.

[0072] The configurations and methods shown in this embodiment can be appropriately combined with the configurations and methods shown in other embodiments. They can be used together.

[0073] (Embodiment 2) This embodiment describes a storage device having the semiconductor device described in the above embodiment. I will reveal it.

[0074] Figure 9(A) shows an example of the configuration of the storage device. The storage device 2600 is connected to peripheral circuit 2601, and has a memory cell array 2610. Peripheral circuit 2601 includes a low decoder 2621, Word line driver circuit 2622, bit line driver circuit 2630, output circuit 2640, It has a control logic circuit 2660.

[0075] The semiconductor device shown in Figure 1(A), (B), or (C) described in Embodiment 1 is a It can be applied to the Morisel array 2610.

[0076] The bit line driver circuit 2630 includes a column decoder 2631 and a pre-charge circuit 263 2. It has a sense amplifier 2633 and a programming circuit 2634. Pre-charge circuit 26 32 has the function of pre-charging the wiring RBL2 described in Embodiment 1 to a predetermined potential. The sense amplifier 2633 processes the potential output from the memory cell MC to the wiring RBL1. It has the function of acquiring the data signal and amplifying the said data signal. The signal is sent to the storage device 26 via the output circuit 2640 as a digital data signal RDATA. Output to the outside of 00.

[0077] Furthermore, the storage device 2600 receives a low power supply voltage (VSS) from an external source as the power supply voltage, and peripheral circuits. High power supply voltage (VDD) for path 2601, high power supply voltage (VI) for memory cell array 2610 L) is supplied.

[0078] Furthermore, the storage device 2600 contains control signals (CE, WE, RE) and address signals ADDR. The data signal WDATA is input from an external source. The address signal ADDR is used by the raw decoder. The data signal WDATA is input to 2621 and column decoder 2631 and is written to the writing circuit It will be entered into 2634.

[0079] The control logic circuit 2660 processes external input signals (CE, WE, RE). Then, control signals are generated for the low decoder 2621 and the column decoder 2631. , is the chip enable signal, WE is the write enable signal, and RE is the read This is the enable signal. The signal processed by the control logic circuit 2660 is this It is not limited to this; other control signals can be input as needed.

[0080] Furthermore, the aforementioned circuits and signals can be selected or omitted as needed.

[0081] Furthermore, in Figure 9(B), the memory device 2600 is a p-channel Si transistor, and as will be described later. The oxide semiconductor of the embodiment (preferably an oxide containing In, Ga, and Zn) is channeled This shows an example of a configuration using transistors included in the formation region. For example, Figure 9(B) The memory device 2600 shown is a logic layer whose peripheral circuits are composed of Si transistors. It has 1000 and a memory layer 2000. In other words, above the logic layer 1000, A memory layer 2000 formed by transistors that include a solid semiconductor in the channel formation region It is formed.

[0082] Therefore, by placing the sense amplifier 2633 below the memory layer 2000, the sense amplifier The wiring length of RBL1, which connects the 2633 module and the memory cell MC, can be shortened. Therefore, the effect of the time constant of the wiring RBL1 is reduced, and the memory cell M The speed of data read from C can be improved. By using transistors in memory cell MCs, the off-current of the memory cell MC can be reduced. This is possible because it can suppress data leakage between adjacent memory cells (MCs). This allows for long-term data storage. Furthermore, it extends the refresh interval of the memory cells. This allows for a reduction in the power consumption of the memory device 2600. Furthermore, Si transistors By using only p-channel type components, manufacturing costs can be kept low. The Si transistor may be limited to n-channel type only.

[0083] Figures 10 to 12 show the configuration of the memory cell array 2610 in Figure 9. In Figure 12, some elements have been omitted for clarity.

[0084] In Figure 10, the memory cell MC[m,n,d] is connected to wiring RBL1[m], wiring WBL1[ [m], wiring WWL[n,d], and wiring RWL[n,d] are connected. Therefore, Figure The semiconductor device shown in 10 has three-dimensionally arranged memory cells MC[1 It has ,1,1] to MC[m,n,d].

[0085] Wiring RBL1, wiring RBL2, and wiring WBL1 are arranged in rows and in the depth direction d. It is preferable to connect it to the bit line driver circuit 2630A. Therefore, memory Cells MC[1,1] through MC[m,n] are processed as data access units. This indicates that the data width has m bits. The semiconductor device of this embodiment is It can be easily applied not only to general-purpose memory but also to the frame memory of display devices.

[0086] However, wiring RBL2 may be fixed at any high potential. Also, in Figure 10, One end and the other end of the memory module 10 are connected via the selection transistor DTr and the wiring WBL1. This shows an example of how they are connected. Each memory module 10 is connected via wiring WBL1 By shortening the wiring length, variations due to wiring resistance can be reduced, thus improving the data sheet. This can shorten the changeover time.

[0087] Figure 11 shows a different configuration of the memory cell array 2610 from that in Figure 10. It further has wiring WBL2, and wiring WBL2 is memorized via the select transistor DTr. It is electrically connected to the Remodule 10. In Figure 10, wiring WBL1 is connected to the memory module The memory module 10 is connected in the vicinity of the rail 10, and the memory module 10 shares the wiring WBL1 with the bit wire drive. It is connected to the IBA circuit 2630A. In Figure 11, the memory module 10 is wired to WBL1 or This shows an example where the bit line driver circuit 2630A is connected via wiring WBL2. The wiring WBL1 or wiring WBL2 shown in Figure 11 is on the outside of the memory cell array 2610. It is preferable that it be connected to the bit line driver circuit 2630A. Therefore, the memory The Luarray 2610 improves the data density of the semiconductor device compared to the configuration shown in Figure 10. It is possible.

[0088] Figure 12 shows a different configuration of the memory cell array 2610 from that in Figure 11. Furthermore, select transistors DTr1, DTr2, wiring RWL_D1, and wiring RWL_D It has 2. Wiring RBL2 is connected to the memory module via the selection transistor DTr1. Connected to 10, wiring RBL1 is connected to the memory module via the selection transistor DTr2. It is connected to 10. Wiring RWL_D2 connects to the gate of the selected transistor DTr1 and electrical The wire RWL_D1 is connected to the gate of the selected transistor DTr2, and is electrically connected to it. The selection transistor DTr1 selects data for each memory module 10. The select transistor can be pre-charged at a predetermined potential used for reading the signal. DTr2 can select the memory module 10 from which to read the data. The readout wiring RBL1 is connected to the selected transition of the unselected memory module 10. The DTr2 can be turned off. Therefore, the unselected memory module 1 Because 0 can be disconnected, the data read from the selected memory cell to wiring RBL1 is transmitted The quality can be improved. In particular, the data held by the memory module 10 is analog In the case of data, it is preferable to have a selection transistor DTr2. As a different example... When reading data from wiring RBL2, you can control the selection transistor DTr1. Good. The selection transistors DTr1 or DTr2 may be provided as needed.

[0089] Furthermore, Figure 12 shows that one side of the memory module 10 is distributed via a selection transistor DTr. It is connected to wire WBL2. Wires WBL1 and RBL1 are bit wire driver circuits. Connected to 2630A, wiring WBL2 and wiring RBL2 are connected to bit wire driver circuit 263 It is connected to 0B. Therefore, the memory module 10 is connected to the bit line driver circuit 2. The signal supplied from 630A to wiring WBL1 and the bit line driver circuit 2630B The data can be rewritten by the signal applied to line WBL2.

[0090] <Examples of structures and manufacturing methods> The following describes the manufacturing method to help understand the structure of the semiconductor device of this embodiment. I will reveal it.

[0091] Figures 13(A) and (B) are schematic diagrams showing the semiconductor devices shown in Figures 1(A) to (C). Yes. Figure 13(A) shows a top view of the semiconductor device, and Figure 13(B) is a top view of Figure 13(A). This shows a cross-sectional view corresponding to the dashed line A1-A2.

[0092] The semiconductor device consists of wiring RWL, wiring WWL, and an insulator (hatched in Figure 13). (Area not shown) and a structure having stacked elements, and an opening is provided in the structure, A conductive material PG is formed to fill the area. Wiring ER is formed on the conductive material PG. This connects wiring ER to wiring RWL or wiring WWL, thereby electrically connecting them. It is.

[0093] In addition, the wiring RWL and wiring WWL pass through the structure in a single manner. An opening is formed, through which wiring WWL_D, wiring RWL, and wiring WWL pass. A selection transistor DTr is provided in the region DM, and a memory cell MC is provided in the region AR. Therefore, an insulator, a conductor, and a semiconductor are formed in the opening. The body functions as wiring WBL and wiring RBL, and the semiconductor is a select transistor DTr. It functions as the channel formation region of transistors WTr and RTr. (Figure 13) The region in which an insulator, a conductor, and a semiconductor are formed in the opening is defined as region HL. This is illustrated in the diagram. Furthermore, the transistors in the memory cell MC are provided with back gates. If so, the conductor in region HL is electrically connected to the back gate. It can also function as a BGL (Band Link) for wiring.

[0094] In other words, in Figure 13, the semiconductor device shown in any one of Figures 1(A), (B), or (C) is a region The semiconductor device configured in SD1, as shown in Figure 2 or Figure 6, is configured in region SD2. This indicates that.

[0095] In the following fabrication method examples 1 and 2, memory cells MC are formed in region AR. I will explain the method.

[0096] <<Example of manufacturing method 1>> Figures 14 to 18 are cross-sectional views illustrating an example of the fabrication of the semiconductor device shown in Figure 1(C). In particular, cross-sectional views of transistors WTr and RTr in the channel length direction are shown. Furthermore, in the cross-sectional views of Figures 14 to 18, some elements have been omitted for clarity. It is illustrated.

[0097] As shown in Figure 14(A), the semiconductor device in Figure 1(C) is located above the substrate (not shown). An insulator 101A is placed on the insulator 101A, and a conductor 131A is placed on the insulator 101A, and An insulator 101B placed on body 131A, and a conductor 13 placed on insulator 101B 2A, an insulator 101C placed on the conductor 132A, and a component placed on the insulator 101C A conductor 131B, an insulator 101D placed on the conductor 131B, and an insulator 101D A conductor 132B is placed on top, and an insulator 101E is placed on top of the conductor 132B. It possesses. Furthermore, from now on, a laminate having these multiple conductors and multiple insulators will be referred to as a laminate. Write 100.

[0098] For example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used as the substrate. For example, an insulating substrate can be a glass substrate, a quartz substrate, a sapphire substrate, or a stabilized substrate. These include zirconia substrates (such as yttria-stabilized zirconia substrates) and resin substrates. Examples of semiconductor substrates include silicon, germanium, and other semiconductor substrates, or carbide. Ricon, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide Examples include compound semiconductor substrates made of um. Furthermore, insulating regions exist within the aforementioned semiconductor substrates. Semiconductor substrates having a region, for example, SOI (Silicon On Insulator) There are boards and the like. Conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. There are also substrates containing metallic nitrides, substrates containing metallic oxides, and so on. Furthermore, a substrate in which a conductor or semiconductor is provided on an insulating substrate, a semiconductor substrate with a conductor or This includes substrates with an insulator, and substrates with a semiconductor or insulator provided on a conductive substrate. Alternatively, substrates on which elements are provided may be used. Examples of its offspring include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0099] Furthermore, a flexible substrate may be used as the substrate. One method for creating the transistor is to fabricate the transistor on a non-flexible substrate, and then the transistor Another method involves peeling off the substrate and transferring it to a flexible substrate. In that case, the non-flexible substrate and the substrate will be separated. It is preferable to provide a release layer between the inverter and the substrate. Furthermore, a sheet with woven fibers can be used as the substrate. A film or foil may be used. The substrate may also be stretchable. It may have the property of returning to its original shape when the bending or pulling is stopped. It may have the property of not returning to its original shape. The substrate may be, for example, 5 μm to 700 μm. More preferably 10 μm to 500 μm, and more preferably 15 μm to 300 μm. It has a region that constitutes thickness. Thinning the substrate makes semiconductor devices containing transistors lighter. This is possible. Also, by making the substrate thinner, flexibility can be improved even when using materials such as glass. In some cases, it may have the property of returning to its original shape when bending or pulling is stopped. Therefore, it is possible to mitigate the impact applied to semiconductor devices on the substrate due to drops, etc. Yes, it is possible. In other words, it is possible to provide robust semiconductor devices.

[0100] Flexible substrates include, for example, metals, alloys, resins, or glass, or their fibers. Fibers and other materials can be used. The lower the coefficient of thermal expansion of the flexible substrate, the more deformation due to the environment is suppressed. It is preferable to have it controlled. As a flexible substrate, for example, if the coefficient of thermal expansion is 1 × 10 -3 / K or less, 5 x 10 -5 / K or less, or 1 × 10 -5Materials with a temperature of / K or less should be used. For example, polyester, polyolefin, polyamide (nylon, aramid, etc.) Examples include polyimide, polycarbonate, and acrylic. In particular, aramid has a high coefficient of thermal expansion. Because of its low coefficient of friction, it is suitable as a flexible substrate.

[0101] In the manufacturing example described in this embodiment, a heat treatment is included in the process, so the substrate Therefore, it is preferable to use a material that has high heat resistance and a low coefficient of thermal expansion.

[0102] Conductor 131A (Conductor 131B) functions as wiring WWL shown in Figure 1(C), The electrical element 132A (conductor 132B) functions as the RWL wiring shown in Figure 1(C).

[0103] Examples of conductors 131A, 131B, 132A, and 132B include Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium A material containing one or more metallic elements selected from um, beryllium, indium, ruthenium, etc. Materials can be used. Also, polycrystalline silicon containing impurity elements such as phosphorus is a representative example. High-electrical-conductivity semiconductors, such as nickel silicide, may also be used. .

[0104] Furthermore, the above-mentioned conductors, in particular conductor 131A and conductor 131B, are semiconductors 1 described later. 51, included in metal oxides applicable to semiconductors 152, 153a, and 153b. Conductive materials containing the aforementioned metal elements and oxygen may also be used. Conductive materials containing nitrogen may be used. For example, titanium nitride, tantalum nitride, and other nitrogen-containing materials. Conductive materials may be used. In addition, indium tin oxide and indium oxide containing tungsten oxide may be used. Indium oxide, indium zinc oxide containing tungsten oxide, indium zinc oxide containing titanium oxide Indium tin oxide containing titanium oxide, indium zinc oxide, and silicon are added. Indium tin oxide with added nitrogen may also be used. In addition, nitrogen-containing indium gallium zinc acid may be used. Chemicals may also be used. By using such materials, water that may be mixed in from surrounding insulators, etc. It is sometimes possible to capture the raw material.

[0105] Furthermore, the above-mentioned conductor, in particular conductor 132A and conductor 132B, may be water or hydrogen, etc. It is preferable to use a conductive material that has the function of suppressing the permeation of impurities. For example, Tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide are used. It is preferable that it be present, and it can be in the form of a single layer or multiple layers.

[0106] Furthermore, multiple conductive materials formed from the above materials may be stacked and used. For example, as described above. A laminated structure may be formed by combining a material containing a metallic element with a conductive material containing oxygen. Furthermore, a laminate combining the aforementioned metal element-containing material and a nitrogen-containing conductive material is also used. It may also be used as a structure. Furthermore, a material containing the aforementioned metal element, a conductive material containing oxygen, and nitrogen A laminated structure may be formed by combining conductive materials containing an element with an insulating material. By applying an insulator having an excess oxygen region as the edge material, the region of the conductor in contact with the insulator In this process, oxygen may diffuse. This can cause materials containing metal elements and oxygen to diffuse. A laminated structure combined with a conductive material can be formed. Similarly, a conductor By applying an insulator having an excess nitrogen region as an insulator in contact with the conductor, nitrogen may diffuse in the region in contact with the insulator of the conductor. As a result, a laminated structure combined with a material containing a metal element and a conductive material containing nitrogen can be formed. In the region in contact with the conductor, nitrogen may diffuse. As a result, a laminated structure combined with a material containing a metal element and a conductive material containing nitrogen can be formed. In the region in contact with the conductor, nitrogen may diffuse. As a result, a laminated structure combined with a material containing a metal element and a conductive material containing nitrogen can be formed.

[0107] Each of the conductors 131A, 131B, 132A, and 132B may be made of the same material as each other or may be made of different materials from each other. That is, the materials applied to the conductors 131A, 131B, 132A, and 132B constituting the semiconductor device according to one aspect of the present invention can be appropriately selected and used respectively. Each of the conductors 131A, 131B, 132A, and 132B may be made of the same material as each other or may be made of different materials from each other. That is, the materials applied to the conductors 131A, 131B, 132A, and 132B constituting the semiconductor device according to one aspect of the present invention can be appropriately selected and used respectively. Each of the conductors 131A, 131B, 132A, and 132B constituting the semiconductor device according to one aspect of the present invention The materials applied to the conductors 131A, 131B, 132A, and 132B can be appropriately selected and used respectively.

[0108] As the insulators 101A to 101E, it is preferable that the insulators are materials with reduced impurity concentrations such as water or hydrogen. For example, the desorption amount of hydrogen from the insulators 101A to 101E is, in temperature-programmed desorption spectroscopy (TDS), when the surface temperature of the film is in the range of 50°C to 500°C, the desorption amount converted to hydrogen molecules is, per area of any one of the insulators 101A to 101E, 2×10 As the insulators 101A to 101E, it is preferable that the insulators are materials with reduced impurity concentrations such as water or hydrogen. For example, the desorption amount of hydrogen from the insulators 101A to 101E is, in temperature-programmed desorption spectroscopy (TDS), when the surface temperature of the film is in the range of 50°C to 500°C, the desorption amount converted to hydrogen molecules is, per area of any one of the insulators 101A to 101E, 2×10 ectroscopy)) is, when the surface temperature of the film is in the range of 50°C to 500°C, the desorption amount converted to hydrogen molecules is, per area of any one of the insulators 101A to 101E, 2×10 ectroscopy)) is, when the surface temperature of the film is in the range of 5°C to 500°C, the desorption amount converted to hydrogen molecules is, per area of any one of the insulators 101A to 101E, 2×10 ectroscopy)) is, when the surface temperature of the film is in the range of 50°C to 500°C, the desorption amount converted to hydrogen molecules is, per area of any one of the insulators 101A to 101E, 2×10 molecules / cm 15 molecules / cm 2 molecules / cm 15 molecules / cm 2 molecules / cm 14 molecules / cm 2 or less, preferably 1×10 or less, more preferably 5×10 14 molecules / cm 2 or less. Also, the insulators 101A to 101E may be formed using an insulator that releases oxygen when heated. As described above, the conductor 13 1A, conductor 131B, conductor 132A, and conductor 132B can be formed into a laminated structure by combining a material containing a metal element and a conductive material containing an oxygen element. It can be a laminated structure formed by combining a material containing a metal element and a conductive material containing an oxygen element.

[0109] As the insulators 101A to 101E, for example, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used singly or in a laminated form. Also, for example, materials containing silicon oxide or silicon oxynitride can be used. For example, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used singly or in a laminated form. Also, for example, materials containing silicon oxide or silicon oxynitride can be used. For example, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used singly or in a laminated form. Also, for example, materials containing silicon oxide or silicon oxynitride can be used. For example, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used singly or in a laminated form. Also, for example, materials containing silicon oxide or silicon oxynitride can be used. For example, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used singly or in a laminated form. Also, for example, materials containing silicon oxide or silicon oxynitride can be used.

[0110] In this specification, silicon oxynitride refers to a material with a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material with a higher nitrogen content than oxygen in its composition. Also, in this specification, aluminum oxynitride refers to a material with a higher oxygen content than nitrogen in its composition, and aluminum nitride oxide refers to a material with a higher nitrogen content than oxygen in its composition. In this specification, silicon oxynitride refers to a material with a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material with a higher nitrogen content than oxygen in its composition. Also, in this specification, aluminum oxynitride refers to a material with a higher oxygen content than nitrogen in its composition, and aluminum nitride oxide refers to a material with a higher nitrogen content than oxygen in its composition. In this specification, silicon oxynitride refers to a material with a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material with a higher nitrogen content than oxygen in its composition. Also, in this specification, aluminum oxynitride refers to a material with a higher oxygen content than nitrogen in its composition, and aluminum nitride oxide refers to a material with a higher nitrogen content than oxygen in its composition. In this specification, silicon oxynitride refers to a material with a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material with a higher nitrogen content than oxygen in its composition. Also, in this specification, aluminum oxynitride refers to a material with a higher oxygen content than nitrogen in its composition, and aluminum nitride oxide refers to a material with a higher nitrogen content than oxygen in its composition. In this specification, silicon oxynitride refers to a material with a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material with a higher nitrogen content than oxygen in its composition. Also, in this specification, aluminum oxynitride refers to a material with a higher oxygen content than nitrogen in its composition, and aluminum nitride oxide refers to a material with a higher nitrogen content than oxygen in its composition.

[0111] In the next step, as shown in FIG. 14(B), an opening 191 is formed in the laminate 100 shown in FIG. 14(A) by forming a resist mask and performing an etching process or the like. In the next step, as shown in FIG. 14(B), an opening 191 is formed in the laminate 100 shown in FIG. 14(A) by forming a resist mask and performing an etching process or the like.

[0112] The formation of the resist mask can be appropriately performed using a lithography method, a printing method, an inkjet method, or the like. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Also, for the etching process, dry etching The formation of the resist mask can be appropriately performed using a lithography method, a printing method, an inkjet method, or the like. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Also, for the etching process, dry etching The formation of the resist mask can be appropriately performed using a lithography method, a printing method, an inkjet method, or the like. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced. Also, for the etching process, dry etching Either the etching method or the wet etching method may be used, or both may be used.

[0113] Then, as shown in Figure 15(A), etching treatment is used to remove the side of the opening 191. The conductor 132A (conductor 132B) on the surface is removed, and a recess 192A is formed on the side surface. (Recess 192B) is formed. Here, the conductor 132A (conductor 132B) is In the laminate 100, the conductor 132A (conductor 132B) is selectively removed. Materials (insulators 101A to 101E, and conductors 131A (conductors 131B)) It is assumed that a material with a high etching rate is being used.

[0114] Furthermore, recess 192A (recess 192B) is part of the semiconductor device manufacturing process shown in Figure 14(A) In this stage, a sacrificial layer is provided in the region where the opening 191 and recess 192A (recess 192B) are formed. Furthermore, in the semiconductor device fabrication process shown in Figure 14(B), the opening 191 may be formed at the same time. Furthermore, when the opening 191 is formed without providing a sacrificial layer, the recess 192A (recess) is automatically formed. In some cases, 192B) can be formed.

[0115] In the next step, as shown in Figure 15(B), the side of the opening 191 shown in Figure 15(A) An insulator 102 is formed in the aforementioned recess.

[0116] As the insulator 102, an insulating material having the function of suppressing oxygen permeation is used. Preferred. For example, as the insulator 102, silicon nitride, silicon oxide nitride, silicon nitride It is preferable to use aluminum nitride, aluminum nitride oxide, etc. By forming the insulator 102, oxygen enters through the insulator 102, as will be described later. The reduction in the conductivity of the conductor 133 due to the oxidation of the conductor 133 can be prevented. .

[0117] In the next step, as shown in FIG. 16(A), on the side surface of the opening 191 shown in FIG. 15(B), and in the formed recess, the conductor 133 is formed into a film. That is, the conductor 133 is formed on the insulator 102.

[0118] As the conductor 133, the materials applicable to the above-described conductor 131A, conductor 131B, conductor 132A, and conductor 132B can be used. In particular, among these materials, it is preferable to apply a material with high conductivity to the conductor 133.

[0119] In the next step, as shown in FIG. 16(B), by forming a resist mask and performing an etching process or the like, the conductor 133 included in the opening 191 is removed so that only the above-described recess remains with the conductor 133. Thereby, the conductor 133a and the conductor 133b are formed. Incidentally, at this time, as long as the insulators 101A to 101E, the conductor 131A, and the conductor 131B are not exposed in the opening 191, a part of the insulator 102 may be removed. B is not exposed in the opening 191, a part of the insulator 102 may be removed. Yes.

[0120] Regarding the formation of the resist mask and the etching process, refer to the description of FIG. 14(B). Refer to.

[0121] By the way, the conductor 133a (conductor 133b) functions as the other electrode of the capacitor element CS shown in FIG. 1(C). That is, in the region 181A (region 181B) shown in FIG. 16(B), the capacitor element CS is formed. the capacitor element CS is formed.

[0122] In the next step, as shown in Figure 17(A), the insulator 1 located on the side of the opening 191 02. A semiconductor 151 is formed on the conductor 133a and the conductor 133b.

[0123] As the semiconductor 151, a material containing a metal oxide as described in Embodiment 3 is applied. It is preferable to do so.

[0124] By the way, if semiconductor 151 contains a metal oxide, the insulating material in contact with semiconductor 151 Body 102 has the function of suppressing the permeation of not only oxygen but also impurities such as water or hydrogen. It is preferable to use an edge material. By forming such an insulator 102, the insulator 1 Impurities such as water or hydrogen enter through O2 and react with the oxygen contained in semiconductor 151. This prevents it from turning into water. When water is generated within semiconductor 151, semiconductor 151 Oxygen deficiencies may form within the system. When impurities such as hydrogen enter these oxygen deficiencies... Therefore, in semiconductor 151, If there is a region containing a large amount of hydrogen, that region is included in the channel-forming region. Transistors tend to exhibit normally-on characteristics. To prevent this, an insulator 102 is used. An insulating material that has the function of suppressing the permeation of not only oxygen but also impurities such as water or hydrogen. It is desirable to use [this].

[0125] Furthermore, if the semiconductor 151 contains a metal oxide, the semiconductor 151 will form a region The conductivity may differ depending on the region. Figure 17(A) shows the semiconductor 151 formed therein. Of the regions, the regions in contact with the insulator 102 are shown as region 151a and region 151b, and the conductor The region in contact with 133a (conductor 133b) is shown as region 151c. In particular, region 1 51a is the region that overlaps with the side surface of the conductor 131A (conductor 131B), and region 151b This is the region that overlaps with the side surface of insulator 101A (insulator 101B to insulator 101E). Region 151c is in contact with conductor 133a (conductor 133b), therefore conductor 1 Impurities such as hydrogen or water contained in 33a (conductor 133b) diffuse into region 151c. This may occur. As mentioned above, if impurities such as water or hydrogen diffuse into semiconductor 151 Because electron carriers may be generated, region 151c is made to have low resistance. Therefore, region 151c has higher conductivity than regions 151a and 151b. It becomes a region.

[0126] Region 151a is the region that forms the channel of the transistor. When the transistor is ON, region 151a has low resistance, so it is lower than region 151b. The conductivity increases.

[0127] In the next step, as shown in Figure 17(B), semiconductor 1 located on the side of the opening 191 An insulator 103 and a semiconductor 152 are sequentially deposited on 51.

[0128] As the insulator 103, any material applicable to the insulator 102 described above can be used. In particular, if the semiconductor 151 contains a metal oxide, the insulator 103 is oxygen. Furthermore, it is an insulating material that has the function of suppressing the permeation of impurities such as water or hydrogen. It is preferable.

[0129] By the way, in region 182A (region 182B) shown in Figure 17(B), in Figure 1(C) The transistor WTr shown is configured. Specifically, region 182A (region 182B) In this, region 151a of semiconductor 151 is the channel formation region of transistor WTr Functioning, each of the two regions 151b of semiconductor 151 is the source power of transistor WTr The electrode functions as a drain electrode, and the conductor 132A acts as the gate electrode of the transistor WTr. It functions in particular when using a material containing a metal oxide as semiconductor 151. The WTr transistor is composed of an oxide semiconductor (OS) transistor.

[0130] As semiconductor 152, similar to semiconductor 151, it contains a metal oxide as described in Embodiment 3. Materials that can be used can be used. Also, as an alternative to semiconductor 152, polycrystalline silicon, Semiconductor materials such as amorphous silicon can be used.

[0131] In the next step, as shown in Figure 18(A), an insulator 104 is formed on the semiconductor 152. Then, a conductive film 134 is formed so that the remaining opening 191 is filled.

[0132] As the insulator 104, a material applicable to the insulators 102 and 103 described above is used. It is possible.

[0133] The conductor 134 is the aforementioned conductor 131A, conductor 131B, conductor 132A, Materials applicable to conductors 132B, 133a, and 133b can be used. ru.

[0134] By the way, in region 183A (region 183B) shown in Figure 18(A), in Figure 1(C) The transistor RTr shown is configured. Specifically, region 183A (region 183B) In this, the semiconductor 151 has region 151c, two regions 151b, and the conductor 133a (conductor The electrode 133b) acts as the gate electrode of the transistor RTr, and the semiconductor 152 is the transistor It functions as a channel-forming region of transistor RTr, and the conductor 134 is the channel of transistor RTr. It functions as a gate electrode. In particular, materials containing metal oxides are applied as semiconductor 152. If this is the case, then transistor RTr constitutes an OS transistor.

[0135] By performing the steps from Figure 14(A) to Figure 18(A), the semiconductor shown in Figure 1(C) is produced. Body devices can be manufactured.

[0136] One aspect of the present invention is not limited to the semiconductor device configuration example shown in Figure 18(A). One aspect of this may vary depending on the circumstances, or as needed, as shown in Figure 18(A) The conductor device can be modified as appropriate.

[0137] For example, one aspect of the present invention, as described above, is a transistor W as shown in Figure 1(A) It is also possible to create a semiconductor device in which transistors RTr do not have back gates. To manufacture the semiconductor device shown in Figure 1(A), the semiconductor device shown in Figure 1(C) is manufactured. In the process, if you perform the step shown in Figure 18(B) instead of the step shown in Figure 18(A) Good. In Figure 18(B), instead of the conductor 134 in Figure 18(A), the opening 191 is This shows the process of forming an insulator 105 so as to fill the gap. Note that the insulator 105 is, for example, A material suitable for use as the insulator 104 can be used.

[0138] Furthermore, for example, one aspect of the present invention improves the switching characteristics of a transistor WTr. Therefore, the gate electrode configuration of the transistor WTr is changed from the configuration shown in Figure 18(A). It may be modified. Figures 19(A), (B) and 20(A)(B) show the method for manufacturing the semiconductor device. This shows an example. In Figure 19(A), in Figure 14(B), the side surface of the opening 191 The conductor 131A (conductor 131B) is removed, and the recess 193A (recess 193B) This shows the process by which the conductor 131A (conductor 131B) is formed. In the laminate 100, the conductor 131A (conductor 131B) is selectively removed. Materials (conductor 132A (conductor 132B), insulator 101A to insulator 101E are more It is assumed that a material with a high tread rate is being used.

[0139] Furthermore, recess 193A (recess 193B) is part of the semiconductor device manufacturing process shown in Figure 14(A). In this stage, a sacrificial layer is applied to the region where the opening 191 and the recess 193A (recess 193B) are formed. Even if the opening 191 is formed at the same time in the semiconductor device manufacturing process shown in Figure 14(B), Good. Also, when the opening 191 is formed without providing a sacrificial layer, the recess 193A (recess) is automatically formed. In some cases, part 193B) can be formed.

[0140] In the next step, as shown in Figure 19(B), the side of the opening 191 shown in Figure 19(A) A semiconductor 153 is formed in the recess 193A (recess 193B).

[0141] As the semiconductor 153, a material containing a metal oxide as described in Embodiment 3 is applied. It shall be done.

[0142] In the next step, as shown in Figure 20(A), resist mask formation and etching processes are performed. As a result, the semiconductor 153 remains only in the aforementioned recess 193A (recess 193B), The semiconductor 153 contained in part 191 is removed, and semiconductor 153a (semiconductor 153b) is formed. This process is performed simultaneously with, or after, an etching process is carried out to improve conductivity. Body 132A (conductor 132B) is removed to form recess 192A (recess 192B).

[0143] Next, similar to the process in Figure 16(B), the semiconductor 153a( An insulator 102 is formed to cover semiconductor 153b). b) When a material containing a metal oxide is applied, semiconductor 153a (semiconductor 15 3b) By contacting the insulator 102, impurities such as hydrogen and water contained in the insulator 102 are released. It diffuses into semiconductor 153a (semiconductor 153b). Also, semiconductor 153a (semiconductor 153b ) comes into contact with conductor 133a (conductor 133b), and conductor 133a (conductor 133 Impurities such as hydrogen and water contained in b) diffuse into semiconductor 153a (semiconductor 153b). In other words, semiconductor 153a (semiconductor 153b) plays a role in collecting impurities such as hydrogen and water. It possesses. As a result, semiconductor 153a (semiconductor 153b) has low resistance, and the transistor It can function as the gate electrode of the WTr. After this, see Figures 17(A) to 18( By performing the same steps as in A), the semiconductor device shown in Figure 20(B) can be constructed. It is possible.

[0144] Furthermore, for example, in one aspect of the present invention, the first terminal of the transistor WTr shown in Figure 1(C) Alternatively, to reduce the electrical resistance between the second terminal and the gate of transistor RTr. Therefore, the configuration of the gate electrode of transistor RTr is changed from the configuration shown in Figure 18(A). This is also acceptable. Figures 21(A) and (B) show an example of a method for fabricating the semiconductor device. Figure 2 In 1(A), the conductor 132A (conductive) is located on the side surface of the opening 191 in Figure 15(A). Not only body 132B) is removed, but insulators 101A to 101E are also removed. This shows the process by which recess 194B (recess 194A, recess 194C) is formed. Here, the conductor 132A (conductor 132B) and the insulators 101A to 101E are used. In the laminate 100, the conductor 132A (conductor 132B) and the insulator 101A to Materials such that insulator 101E is selectively removed (conductor 131A (conductor 131B) It is assumed that a material with a higher etching rate is being used.

[0145] Furthermore, recess 194B (recess 194A, recess 194C) is a semiconductor device as shown in Figure 14(A). During the manufacturing process of the piece, the opening 191 and the recess 194B (recess 194A, recess 194C) A sacrificial layer is provided in the region where the aperture is formed, and in the semiconductor device fabrication process shown in Figure 14(B), It may be formed together with part 191. Also, when the opening 191 is formed without providing a sacrificial layer In some cases, recesses 194B (recesses 194A and 194C) can be formed automatically.

[0146] Furthermore, in Figure 21(A), in recess 194B (recess 194A, recess 194C), Edge body 101B, insulator 101C (insulator 101A, insulator 101D, insulator 101E) However, conductor 132A (conductor 132B) is removed more significantly, but conductor 13 Insulator 101B and insulator 101C (insulator 101A, insulator 132B) are better than 2A (conductor 132B). The edge material 101D and the insulator 101E) may be removed in larger quantities. Also, the insulator 101B , insulator 101C (insulator 101A, insulator 101D, insulator 101E), and conductor 13 2A (conductor 132B) may be formed to the same depth.

[0147] Figure 21(B) shows an example of the configuration of a semiconductor device when the process shown in Figure 21(A) is followed. After the process shown in Figure 21(A), the recess 194B (recess 194A, recess 194C) is filled. A conductive film 133 is formed in this manner, and the gate electrode of the transistor RTr is formed. Figure 2 In 1(B), the conductor 133a functions as the gate electrode of the transistor RTr, and the conductor Figures 133b and 133c are shown. Following this are Figures 17(A) through 18(A). By performing a similar process, the semiconductor device shown in Figure 21(B) can be constructed. This semiconductor device has more semiconductor 151 and conductor 1 than the semiconductor device shown in Figure 18(A). The configuration has been designed to increase the contact area with 33a (conductor 133b). When a material containing a metal oxide is applied, the semiconductor device shown in Figure 21(B) is similar to the one shown in Figure 18(A). Since region 151b shown in ) does not exist, the first terminal or the second terminal of transistor WTr This allows us to reduce the electrical resistance between the gate of transistor RTr and the other element.

[0148] <<Example of manufacturing method 2>> Here, we will describe an example of a semiconductor device in this embodiment with a structure different from that of manufacturing method example 1. This will be explained using Figures 22 to 24.

[0149] Figures 22 to 24 show the fabrication of the semiconductor device shown in Figure 1(C), similar to Figures 14 to 18. This is a cross-sectional diagram illustrating an example, specifically showing the cross-section of transistors WTr and RTr. The images show cross-sectional views along the channel length. Furthermore, the cross-sectional views in Figures 22 to 24 refer to Figures 14 to 24. Similar to Figure 18, some elements have been omitted from the diagram for clarity.

[0150] The initial steps are as described in Figures 14(A) to 15(B) in Manufacturing Method Example 1. Please refer to the description provided.

[0151] The process shown in Figure 22(A) is a continuation of the process shown in Figure 15(B). Figure 2 In 2(A), the side surface of the opening 191 shown in Figure 15(B), and the recess formed therein, A semiconductor 151 is formed. In other words, a semiconductor 151 is formed on the insulator 102.

[0152] It is preferable to use the semiconductor described in Embodiment 3 as the semiconductor 151.

[0153] In the next step, as shown in Figure 22(B), the side of the opening 191 shown in Figure 22(A) A conductive material 133 is formed in the recesses that are created.

[0154] For the conductor 133, refer to the description of the conductor 133 explained in Manufacturing Method Example 1.

[0155] In the next step, as shown in Figure 23(A), resist mask formation and etching processes are performed. As a result, the conductor included in the opening 191 remains in the aforementioned recess only, so that the conductor 133 remains in the recess. 133 is removed. This forms conductors 133a and 133b. Oh, at this time, if the insulator 102 is not exposed to the opening 191, then the semiconductor 151 It's okay if some parts are removed.

[0156] For details on the formation of the resist mask and the etching process, please refer to the explanation in Figure 14(B). To drink.

[0157] By the way, conductor 133a (conductor 133b) is, in addition to the capacitive element CS shown in Figure 1(C), It functions as an electrode. In other words, in region 181A (region 181B) shown in Figure 23(A) A capacitive element CS is formed there.

[0158] For semiconductor 151, refer to the description of semiconductor 151 explained in manufacturing method example 1. Furthermore, if semiconductor 151 contains a metal oxide, semiconductor 151 is in region 151a, region It can be divided into region 151b and region 151c. Region 151a, region 151b, region 1 For 51c, refer to regions 151a, 151b, and 151c as explained in Fabrication Method Example 1. We will take the above information into consideration.

[0159] In the next step, as shown in Figure 23(B), the conductor 1 located on the side of the opening 191 An insulator 103 is formed on 33a, the conductor 133b, and the semiconductor 151, and thereafter, A semiconductor film 152 is formed on the edge body 103.

[0160] For the insulator 103, refer to the description of the insulator 103 explained in Manufacturing Method Example 1.

[0161] For semiconductor 152, refer to the description of semiconductor 152 explained in example 1 of the manufacturing method.

[0162] By the way, in region 182A (region 182B) shown in Figure 23(B), in Figure 1(C) The transistor WTr shown is configured. Specifically, region 182A (region 182B) In this, region 151a of semiconductor 151 is the channel formation region of transistor WTr Functioning, each of the two regions 151b of semiconductor 151 is the source power of transistor WTr The electrode functions as a drain electrode, and the conductor 132A acts as the gate electrode of the transistor WTr. It functions in particular when using a material containing a metal oxide as semiconductor 151. The WTr transistor will constitute an OS transistor.

[0163] In the next step, as shown in Figure 24(A), an insulator 104 is formed on the semiconductor 152. Then, a conductive film 134 is formed so that the remaining opening 191 is filled.

[0164] For the insulator 104, refer to the description of the insulator 104 explained in Manufacturing Method Example 1.

[0165] For the conductor 134, refer to the description of the conductor 134 explained in Manufacturing Method Example 1.

[0166] By the way, in region 183A (region 183B) shown in Figure 24(A), in Figure 1(C) The transistor RTr shown is configured. Specifically, region 183A (region 183B) In this, the semiconductor 151 has region 151c, two regions 151b, and the conductor 133a (conductor The electrode 133b) acts as the gate electrode of the transistor RTr, and the semiconductor 152 is the transistor It functions as a channel-forming region of transistor RTr, and the conductor 134 is the channel of transistor RTr. It functions as a gate electrode. In particular, materials containing metal oxides are applied as semiconductor 152. If this is the case, then transistor RTr constitutes an OS transistor.

[0167] Perform the steps shown in Figures 14(A) to 15(B) and Figures 22(A) to 24(A). This allows us to fabricate the semiconductor device shown in Figure 1(C).

[0168] One aspect of the present invention is not limited to the semiconductor device configuration example shown in Figure 24(A). One aspect of this may, depending on the circumstances, or as needed, be the half shown in Figure 24(A). The conductor device can be modified as appropriate.

[0169] For example, one aspect of the present invention, as described above, is a transistor W as shown in Figure 1(A) It is also possible to create a semiconductor device in which transistors RTr do not have back gates. To manufacture the semiconductor device shown in Figure 1(A), the semiconductor device shown in Figure 1(C) is manufactured. In this process, instead of performing the steps shown in Figure 24(A), perform the steps shown in Figure 24(B). In Figure 24(B), the opening 191 is filled in place of the conductor 134 in Figure 24(A). This shows the process of forming the insulator 105 so that it forms a circle. Note that the insulator 105 is, for example, A material suitable for use as the insulator 104 can be used.

[0170] Furthermore, for example, one aspect of the present invention improves the switching characteristics of a transistor WTr. Therefore, the configuration of the gate electrode of the transistor WTr is changed from the configuration shown in Figure 24(A). It may be modified. Figure 25 shows an example of the configuration of the semiconductor device. Semiconductor device shown in Figure 25 When manufacturing, the recess 19 is as shown in the example configuration in Figure 20(B) described in Manufacturing Method Example 1. Semiconductor 153a (semiconductor 153b) is formed so that 3A (recess 193B) is filled. Furthermore, an insulating layer covers the semiconductor 153a (semiconductor 153b) with respect to the side surface of the opening 191. Body 102 is formed. After that, the same process as in Figures 22(A) to 24(A) is carried out. By doing so, the semiconductor device shown in Figure 25 can be constructed. The effects of doing so are explained in the manufacturing method example 1, as shown in Figures 19(A), (B), 20(A), ( Refer to the description in B).

[0171] Furthermore, for example, in one aspect of the present invention, the first terminal of the transistor WTr shown in Figure 1(C) Alternatively, to reduce the electrical resistance between the second terminal and the gate of transistor RTr. Therefore, the configuration of the gate electrode of transistor RTr is changed from the configuration shown in Figure 24(A). It is also possible. Figure 26 shows an example of the configuration of the semiconductor device. The semiconductor device shown in Figure 26 can be constructed. When manufacturing, the example configuration shown in Figure 21(A), as explained in Manufacturing Method Example 1, is manufactured. After that, By performing the same process as shown in Figures 22(A) to 24(A), the semiconductor shown in Figure 26 is produced. A body device can be constructed. Note that the effects of constructing Figure 26 are shown in the example of the manufacturing method. Refer to the description of Figure 21(B) explained in section 1.

[0172] A semiconductor capable of holding a large amount of data can be produced by the above-described manufacturing method example 1 or manufacturing method example 2. The device can be manufactured.

[0173] Here, in region SD2 of the semiconductor device shown in Figure 13(B), the semiconductor device shown in Figure 18(A) Figure 27 shows the structure to which the cross-sectional view of the configuration (circuit configuration in Figure 1(C)) is applied. Note that region SD1 This corresponds to the memory cell MC. As shown in Figure 27, the conductive wiring RWL and WWL are shown. The above-described example of a manufacturing method involves creating an opening in a structure in which a body and an insulator are laminated together. 1. By manufacturing as described in Example 2 of the manufacturing method, the circuit configuration shown in Figure 1(C) can be realized. It is possible.

[0174] <Example of connection with peripheral circuits> The semiconductor device shown in Manufacturing Method Example 1 or Manufacturing Method Example 2 has a readout circuit in its lower layer, Peripheral circuits of the memory cell array, such as a recharge circuit, may be formed. In this case, silico A Si transistor is formed on a substrate or the like to constitute the peripheral circuit, and then the manufacturing method If, in Example 1 or Manufacturing Method Example 2, a semiconductor device according to one aspect of the present invention is formed on the peripheral circuit, Good. Figure 28(A) shows the peripheral circuit composed of planar Si transistors, and its upper layer Figure 29(A) shows a cross-sectional view in which a semiconductor device according to one aspect of the present invention is formed. The circuit is constructed with FIN-type Si transistors, and a semiconductor device according to one aspect of the present invention is placed on top of it. This is a formed cross-sectional view. Note that the semiconductor device shown in Figures 28(A) and 29(A) is just one example. Therefore, the configuration shown in Figure 18(A) is applied.

[0175] In Figures 28(A) and 29(A), the Si transistors constituting the peripheral circuit are located on the substrate. It is formed on 1700. The element isolation layer 1701 is formed between multiple Si transistors. Conductors 1712 are formed as the source and drain of the Si transistor. The conductor 1730 is formed extending in the channel width direction, and is connected to other Si transistors, or It is connected to the conductor 1712 (not shown).

[0176] The substrate 1700 can be a single-crystal semiconductor substrate made of silicon or silicon carbide, or a polycrystalline semiconductor substrate. Conductor substrates, compound semiconductor substrates made of silicon germanium, and SOI substrates are used. It is possible.

[0177] Furthermore, the substrate 1700 can be, for example, a glass substrate, a quartz substrate, a plastic substrate, or a metal substrate. Substrates, flexible substrates, laminated films, paper containing fibrous materials, or base film, etc. Any of these may be used. Alternatively, a semiconductor element can be formed using one substrate, and then a semiconductor can be formed on another substrate. The conductive elements may be transposed. In Figures 28(A) and 29(A), as an example, substrate 170 An example using a single-crystal silicon wafer is shown in section 0.

[0178] Here, we will explain the details of Si transistors. The planar type is shown in Figure 28(A). The Si transistor shown here is a cross-sectional view in the channel length direction and is a planar type as shown in Figure 28(B). The Si transistor shown is a cross-sectional view in the channel width direction. Channel formation region 1793 provided in cellulose 1792, low-concentration impurity region 1794 and The high-concentration impurity region 1795 (these are collectively also simply called the impurity region), and the impurity region A conductive region 1796 provided in contact with the region, and a channel forming region 1793 provided A gate insulating film 1797 and a gate electrode 1790 provided on the gate insulating film 1797, The gate electrode 1790 has side wall insulating layers 1798 and 1799 provided on its side. In addition, metal silicide or the like may be used in the conductive region 1796.

[0179] Furthermore, the FIN-type Si transistor shown in Figure 29(A) has a cross-sectional view in the channel length direction. As shown, the FIN-type Si transistor shown in Figure 29(B) has a cross-sectional view in the channel width direction. The Si transistors shown in Figures 29(A) and (B) have a channel formation region 1793. The gate insulating film 1797 and gate electrode 179 have a convex shape, and along their side and top surfaces are the gate insulating film 1797 and gate electrode 179 A 0 is provided. In this embodiment, a part of the semiconductor substrate is processed to form a protrusion. Although this is shown, a semiconductor layer with a convex shape may be formed by processing the SOI substrate. The symbols shown in Figures 29(A) and (B) are the same as the symbols shown in Figures 28(A) and (B).

[0180] Furthermore, the insulators, conductors, semiconductors, etc. disclosed in this specification are subject to PVD (Physical Vapor Deposition). cal vapor deposition) method, CVD (Chemical Vapor Deposition) method, CVD (Chemical Vapor Deposition) method, It can be formed by the Deposition method. For example, the PVD method is... Sputtering method, resistance heating deposition method, electron beam deposition method, PLD (Pulsed Laminate) Examples include the plasma deposition method. Furthermore, CVD methods include plasma deposition. Examples include CVD methods and thermal CVD methods. In particular, as a thermal CVD method, MOCV is an example. D(Metal Organic Chemical Vapor Depositio Examples include the n) method and the ALD (Atomic Layer Deposition) method. ru.

[0181] Thermal CVD is a film deposition method that does not use plasma, so defects can occur due to plasma damage. It has the advantage of never being accomplished.

[0182] In the thermal CVD method, the raw material gas and oxidizer are simultaneously introduced into the chamber, and the chamber is subjected to atmospheric pressure. Alternatively, by applying reduced pressure and reacting the film near or on the substrate, the film can be deposited on the substrate. You may go.

[0183] Furthermore, the ALD method maintains atmospheric pressure or reduced pressure inside the chamber, and the raw material gas for the reaction is The gases are introduced into the chamber sequentially, and film deposition can be performed by repeating this gas introduction sequence. For example, by switching between each switching valve (also called a high-speed valve), two types or less The above raw material gases are supplied to the chamber in order, and the first is supplied in order to prevent the mixing of multiple types of raw material gases. An inert gas (such as argon or nitrogen) is introduced simultaneously with or after the raw material gas. A second raw material gas is introduced. If an inert gas is introduced at the same time, the inert gas is... It acts as a carrier gas, and also when introducing a second raw material gas, an inert gas is introduced at the same time. Good. Also, instead of introducing an inert gas, the first source gas was removed by vacuum evacuation. Later, a second raw material gas may be introduced. The first raw material gas is adsorbed onto the surface of the substrate and the first thin A thin layer is formed, and it reacts with a second raw material gas that is introduced later, so that a second thin layer is formed against the first thin layer. Thin films are formed by stacking layers. The order of gas introduction is controlled until the desired thickness is achieved. By repeating this process multiple times, a thin film with excellent step coverage can be formed. (Thickness of the thin film) This can be adjusted by the number of times the gas introduction sequence is repeated, allowing for precise film thickness control. It is possible and suitable for fabricating miniature FETs.

[0184] Thermal CVD methods such as MOCVD and ALD are disclosed in the embodiments described above. It can form various films such as metal films, semiconductor films, and inorganic insulating films, for example, In-G When forming an α-Zn-O film, trimethylindium (In(CH3)3), tri Methyl gallium (Ga(CH3)3) and dimethyl zinc (Zn(CH3)2) are used. Furthermore, the combinations are not limited to these, and triethylgallium can be substituted for trimethylgallium. It is also possible to use um(Ga(C2H5)3), and diethylzinc can be used instead of dimethylzinc. Zn(C2H5)2) can also be used.

[0185] For example, when forming a hafnium oxide film using a film deposition apparatus that utilizes ALD, the solvent and a liquid containing hafnium precursor compounds (such as hafnium alkoxide or tetrakisdimethyl Hafnium amides such as TDMAH and Hf[N(CH3)2]4) Two types of gases are used: a raw material gas that is vaporized, and ozone (O3) as an oxidizing agent. Other materials include tetrakis(ethylmethylamide)hafnium.

[0186] For example, when forming an aluminum oxide film using a film deposition apparatus that utilizes ALD, A liquid containing a medium and an aluminum precursor compound (trimethylaluminum (TMA, Al(C)) Two types of gases are used: a raw material gas obtained by vaporizing H3, etc., and H2O as an oxidizing agent. Other materials include tris(dimethylamide)aluminum and triisobutylaluminum. Luminium, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedi Examples include Honor.

[0187] For example, when forming a silicon oxide film using a film deposition apparatus that utilizes ALD, hexa Chlorodisilane is adsorbed onto the film-forming surface, and radicals of oxidizing gases (O2, nitrous oxide) are removed. It is supplied and reacted with the adsorbed material.

[0188] For example, when depositing a tungsten film using a film deposition apparatus that utilizes ALD, WF6 The initial tungsten film is formed by sequentially introducing gas and B2H6 gas, and then WF A tungsten film is formed by sequentially introducing 6 gas and H2 gas. SiH4 gas may be used instead of S.

[0189] For example, oxide semiconductor films, such as In-Ga-Zn-, can be deposited using an ALD-based film deposition system. When forming an O film, In(CH3)3 gas and O3 gas are introduced sequentially and repeatedly. - An O layer is formed, and then Ga(CH3)3 gas and O3 gas are introduced sequentially and repeatedly to form a Ga An O layer is formed, and then Zn(CH3)2 gas and O3 gas are repeatedly introduced in sequence to form a Zn layer. An O layer is formed. Note that the order of these layers is not limited to this example. Also, these gases are used This forms mixed oxide layers such as In-Ga-O layers, In-Zn-O layers, and Ga-Zn-O layers. It is permissible to do so. Furthermore, the water obtained by bubbling it with an inert gas such as Ar instead of O3 gas. While H2O gas can be used, it is preferable to use O3 gas, which does not contain H. In(C2H5)3 gas may be used instead of (CH3)3 gas. Also, Ga(CH 3) Ga(C2H5)3 gas may be used instead of 3 gas. Also, Zn(CH3)2 You may use gas.

[0190] Note that the configuration examples of the semiconductor device described in this embodiment can be combined with each other as appropriate. It can be done.

[0191] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0192] (Embodiment 3) In this embodiment, the channel formation region of the OS transistor used in the above embodiment is included This section will primarily explain metal oxides.

[0193] The metal oxide preferably contains at least indium or zinc. In particular, indium It is preferable to include aluminum and zinc. In addition to these, aluminum, gallium, It is preferable that it contains yttrium or tin, etc. Also, boron, silicon, Titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium Selected from neodymium, hafnium, tantalum, tungsten, or magnesium, etc. It may contain one or more types.

[0194] Here, the metal oxide is In-M-Zn oxide, which has indium, element M, and zinc. Let's consider the case where it is a substance. Note that element M is aluminum, gallium, yttrium or Examples include tin. Other elements that can be used for element M include boron, silicon, and titanium. Iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, Examples include odymium, hafnium, tantalum, tungsten, and magnesium. However, these are elements. In some cases, M may be a combination of multiple elements as mentioned above.

[0195] Next, using Figures 30(A), 30(B), and 30(C), the metal according to the present invention This section describes the preferred range of atomic ratios of indium, element M, and zinc in oxides. Figures 30(A), 30(B), and 30(C) show the atomic ratio of oxygen. It will not be listed. Also, the number of atoms of indium, element M, and zinc in the metal oxide. Let the terms of the ratio be [In], [M], and [Zn].

[0196] In Figures 30(A), 30(B), and 30(C), the dashed line represents [In]:[M The line where the atomic ratio of ]:[Zn]=(1+α):(1-α):1 (-1≦α≦1), [In]:[M]:[Zn]=(1+α):(1-α):2 is the line where the atomic ratio is, The line [I]:[M]:[Zn]=(1+α):(1-α):3 represents the atomic ratio. The line where the atomic ratio of n]:[M]:[Zn]=(1+α):(1-α):4, and The line represents the atomic ratio [In]:[M]:[Zn]=(1+α):(1-α):5. vinegar.

[0197] Furthermore, the dashed line represents the atomic ratio of [In]:[M]:[Zn]=5:1:β (β≧0) The line where the atomic ratio is [In]:[M]:[Zn]=2:1:β, [In [In]:[M]:[Zn] = 1:1:β is the atomic ratio line, [In]:[M]:[Zn The line where the atomic ratio of [In]:[M]:[Zn]=1:3:β The line represents the ratio of the number of atoms, and the atomic ratio is [In]:[M]:[Zn]=1:4:β. It represents a line.

[0198] Also, as shown in Figures 30(A), 30(B), and 30(C), [In]:[M]: Metal oxides with an atomic ratio of [Zn]=0:2:1, and values ​​near that, exhibit spinel-type crystal formation. It's easy to create a structure.

[0199] Furthermore, multiple phases may coexist within a metal oxide (e.g., two-phase coexistence, three-phase coexistence). Example For example, if the atomic ratio is in the vicinity of [In]:[M]:[Zn]=0:2:1, then spin Two phases, one with a crystalline structure and the other with a layered structure, tend to coexist. Also, the atomic ratio is [In]: When [M]:[Zn]=1:0:0, the crystal structure is of the Bixbyte type and layered. Two phases with the crystal structure tend to coexist. When multiple phases coexist in a metal oxide, different formations occur. Grain boundaries may form between crystal structures.

[0200] Region A shown in Figure 30(A) represents the indium, element M, and zinc present in the metal oxide. An example of a preferred range for the atomic ratio is shown.

[0201] By increasing the indium content of metal oxides, the carrier mobility of the metal oxides can be improved. The electron mobility can be increased. Therefore, metal oxides with a high indium content The material exhibits higher carrier mobility compared to metal oxides with a lower indium content.

[0202] On the other hand, when the content of indium and zinc in the metal oxide decreases, the carrier mobility decreases. It becomes lower. Therefore, the atomic ratio is [In]:[M]:[Zn]=0:1:0, and so When the value is in the vicinity of (for example, region C shown in Figure 30(C)), the insulating properties become high.

[0203] Therefore, a metal oxide according to one aspect of the present invention has high carrier mobility and grain boundaries. It tends to have a layered structure with fewer atoms, having the atomic ratio shown in region A of Figure 30(A). It is preferable.

[0204] In particular, in region B shown in Figure 30(B), within region A, CAAC(c-axis a (ligned crystalline)-OS is likely to form, and has high carrier mobility. A metal oxide is obtained.

[0205] CAAC-OS has c-axis orientation and multiple nanocrystals are linked in the ab-plane direction. It is a crystal structure that is linked and distorted. The distortion refers to the region where multiple nanocrystals are linked. In this context, the orientation of the grid arrangement between a region with aligned grid arrangements and another region with aligned grid arrangements This refers to the parts that have changed.

[0206] Nanocrystals are based on a hexagonal shape, but they are not necessarily regular hexagons; they can also be non-regular hexagonal. There are also cases where the distortion has a grid arrangement such as pentagons and heptagons. Furthermore, in CAAC-OS, even near strain, clear grain boundaries (grain bows) are present. It is not possible to confirm (also called 'ndary') crystal grains. In other words, due to the distortion of the lattice arrangement, It can be seen that the formation of the boundary is suppressed. This is because CAAC-OS is in the ab-plane direction. The oxygen atoms are not densely arranged, and the substitution of metal elements reduces the bond distance between atoms. This is thought to be because the distortion can be tolerated through changes and other processes.

[0207] CAAC-OS is a highly crystalline metal oxide. On the other hand, CAAC-OS has a clear bond. Since grain boundaries cannot be identified, a decrease in electron mobility caused by grain boundaries does not occur. It can be said that this is a problem. Also, the crystallinity of metal oxides decreases due to the inclusion of impurities and the formation of defects. Because this can occur, CAAC-OS is a metal oxide with few impurities or defects (such as oxygen deficiencies). It can also be called a substance. Therefore, metal oxides containing CAAC-OS have stable physical properties. Therefore, metal oxides containing CAAC-OS are heat-resistant and highly reliable.

[0208] Furthermore, region B is 4.1 from [In]:[M]:[Zn]=4:2:3, and its vicinity Includes adjacent values. Neighboring values ​​include, for example, [In]:[M]:[Zn]=5:3:4. Furthermore, region B is defined as [In]:[M]:[Zn]=5:1:6, and its neighboring values, and The values ​​include [In]:[M]:[Zn] = 5:1:7 and its neighbors.

[0209] Furthermore, the properties of metal oxides are not uniquely determined by the atomic ratio. Even with ratios, the properties of metal oxides can differ depending on the formation conditions. For example, metal acids When depositing a phosphate using a sputtering device, the atomic ratio deviates from the target atomic ratio. A film is formed. Also, depending on the substrate temperature during film formation, the amount of [Zn] may be greater than that of the target [Zn]. The [Zn] content of the film may decrease. Therefore, the region shown in the illustration is where the metal oxide is specific. This region exhibits an atomic ratio that tends to have the characteristics of [specific characteristics], and the boundary between region A and region C is strictly defined. There isn't one.

[0210] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0211] (Embodiment 4) In this embodiment, the CPU that can be equipped with the semiconductor device of the above embodiment is described below. explain.

[0212] Figure 31 shows an example configuration of a CPU that uses the semiconductor device described in Embodiment 1 in part. This is a block diagram.

[0213] The CPU shown in Figure 31 is an ALU1191 (ALU: Arithmetic) mounted on board 1190. tic logic unit (arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller R1195, Register 1196, Register Controller 1197, Bus Interface 1198 (Bus I / F), rewritable ROM1199, and ROM interface It has a ROM I / F (1189). The substrate 1190 is a semiconductor substrate, SOI base A plate, glass substrate, etc., is used. ROM1199 and ROM interface1189 are, It may also be provided on a separate chip. Of course, the CPU shown in Figure 31 is a simplified representation of its configuration. This is just one example; actual CPUs have a wide variety of configurations depending on their application. A configuration including the CPU or arithmetic circuit shown in Figure 31 is considered as one core, and a configuration including multiple such cores is considered as one core. Alternatively, a configuration where each core operates in parallel, such as a GPU, is also possible. Furthermore, the number of bits that a CPU can handle in its internal arithmetic circuits and data bus is, for example, 8 bits, 16 bits. It can be 1 bit, 32 bits, 64 bits, etc.

[0214] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to the decoder 1193, decoded, and then sent to the ALU controller 1192. Trap controller 1194, register controller 1197, timing controller This is entered into Ra1195.

[0215] ALU controller 1192, interrupt controller 1194, register controller The driver 1197 and timing controller 1195 perform various operations based on the decoded instructions. It performs control. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal to do so. In addition, the interrupt controller 1194 generates a signal to the CPU's program. During RAM execution, interrupt requests from external input / output devices and peripheral circuits are processed based on their priority and mass. The system determines and processes based on the state. The register controller 1197 processes the state of register 1196. It generates a dress and reads or writes to register 1196 depending on the CPU state. .

[0216] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 11 92, instruction decoder 1193, interrupt controller 1194, and It generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 generates an internal clock signal based on the reference clock signal. It is equipped with an internal clock generation unit that supplies the internal clock signal to the various circuits mentioned above.

[0217] In the CPU shown in Figure 31, a memory cell is located in register 1196. The transistor shown in the previous embodiment can be used as the memory cell of TA1196. Cut.

[0218] In the CPU shown in Figure 31, the register controller 1197 receives from ALU 1191. Following the instructions, select the hold operation in register 1196. That is, register 1 In the memory cell of 196, data is retained by a flip-flop, or Select whether to use quantitative elements for data retention. (Data retention using flip-flops) If selected, power voltage is supplied to the memory cells in register 1196. If data retention in the capacitive element is selected, the data will not be rewritten to the capacitive element. This process can be performed to stop the supply of power voltage to the memory cell in register 1196. ru.

[0219] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0220] (Embodiment 5) The storage device in the above embodiment is a memory card (e.g., an SD card), USB (Univ (Serial Bus) memory, SSD (Solid State Drive) It can be applied to various removable storage devices such as (ve). In this embodiment, Several configuration examples of movable storage devices will be explained using Figure 32.

[0221] Figure 32(A) is a schematic diagram of a USB memory device. The USB memory device 5100 is housed in enclosure 5101 It has a cap 5102, a USB connector 5103, and a circuit board 5104. Circuit board 5104 It is housed in the enclosure 5101. The circuit board 5104 contains a memory device and a drive for the memory device. A circuit is provided for this purpose. For example, the circuit board 5104 has a memory chip 5105, a controller A roller chip 5106 is attached. The memory chip 5105 is in Embodiment 2. The memory cell array 2610, word line driver circuit 2622, and raw decoder 26 described above 21. Sense amplifier 2633, pre-charge circuit 2632, column decoder 2631, etc. It is incorporated. The controller chip 5106 specifically includes the processor, work machine It incorporates a memory chip, ECC circuit, etc. Note that the memory chip 5105 and controller are also included. The circuit configurations for each of the 5106 components are not limited to those described above, and may vary depending on the situation. Depending on the circumstances, the circuit configuration may be changed as appropriate. For example, word line driver circuit 2622, Low decoder 2621, sense amplifier 2633, precharge circuit 2632, column decoder The -der 2631 was incorporated into the controller chip 5106 instead of the memory chip 5105. This configuration is also acceptable. The USB connector 5103 is an interface for connecting to external devices. It functions as a system.

[0222] Figure 32(B) is a schematic diagram of the external appearance of an SD card, and Figure 32(C) shows the internal structure of an SD card. This is a schematic diagram of the structure. The SD card 5110 consists of a housing 5111, a connector 5112, and a circuit board. It has 5113. Connector 5112 serves as an interface for connecting to an external device. It functions. The circuit board 5113 is housed in the casing 5111. The circuit board 5113 has memory storage. Circuits for driving memory chips and storage devices are provided. For example, the circuit board 5113 has memory chips The chip 5114 and controller chip 5115 are installed. Memory chip 511 4 includes the memory cell array 2610 and the word line driver circuit 26 described in Embodiment 2. 22. Low decoder 2621, sense amplifier 2633, precharge circuit 2632, color It incorporates a 2631 decoder and other components. The controller chip 5115 contains a processor It incorporates a sasser, work memory, ECC circuit, etc. Note that the memory chip 5114 and The circuit configurations for each controller chip 5115 are not limited to those described above, and may vary depending on the situation. Depending on the circumstances, the circuit configuration may be modified as appropriate. For example, the word line driver. Circuit 2622, Low Decoder 2621, Sense Amplifier 2633, Precharge Circuit 263 2. The column decoder 2631 is connected to the controller chip 511, not the memory chip 5114. It could also be configured as part of option 5.

[0223] By also providing a memory chip 5114 on the back side of the circuit board 5113, the SD card 5110 The capacity can be increased. Also, a wireless chip with wireless communication functionality can be placed on board 5113. It may be provided. This will enable wireless communication between the external device and the SD card 5110. This enables reading and writing data to the memory chip 5114.

[0224] Figure 32(D) is a schematic diagram of the external appearance of an SSD, and Figure 32(E) is a schematic diagram of the internal structure of an SSD. This is a diagram. The SSD5150 has a housing 5151, a connector 5152, and a circuit board 5153. Connector 5152 functions as an interface for connecting to an external device. The circuit board 5153 is housed in the casing 5151. The circuit board 5153 contains a storage device and a memory device. A circuit is provided to drive the device. For example, the circuit board 5153 has a memory chip 5154 Memory chip 5155 and controller chip 5156 are installed. The top 5154 includes the memory cell array 2610 described in Embodiment 2, and the word line dry Circuit 2622, Low Decoder 2621, Sense Amplifier 2633, Precharge Circuit 26 32. It incorporates a column decoder 2631, etc. There is also a memo on the back of circuit board 5153. By adding the Rechip 5154, the capacity of the SSD5150 can be increased. Chip 5155 has work memory built into it. For example, memory chip 5155 A DRAM chip can be used. The controller chip 5156 has a processor, E CC circuits and other components are incorporated. Note that memory chip 5154 and memory chip 515 The circuit configurations of 5 and the controller chip 5115 are not limited to those described above. Depending on the situation or circumstances, the circuit configuration may be changed as appropriate. For example, control The chip 5156 may also be provided with memory that functions as work memory.

[0225] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0226] (Embodiment 6) This embodiment provides an example of an electronic device to which the storage device of the above embodiment can be applied. I will explain this.

[0227] <Notebook personal computer> Figure 33(A) shows a notebook personal computer, consisting of a casing 5401 and a display unit 540 2. It has a keyboard 5403, a pointing device 5404, etc. One aspect of the present invention This storage device can be included in a notebook personal computer.

[0228] <Smartwatch> Figure 33(B) shows a smartwatch, a type of wearable device, with a housing 5901 It includes a display unit 5902, operation buttons 5903, a control element 5904, a band 5905, etc. A storage device according to one aspect of the present invention can be provided in a smartwatch. 5902 may use a display device that has the added function of a position input device. Furthermore, the function as a position input device is added by providing a touch panel on the display device. It is possible. Alternatively, the function as a position input device is a photoelectric sensor, also known as a photosensor. It can also be added by providing a conversion element in the pixel section of the display device. The 5903 has a power switch to activate the smartwatch, and the smartwatch app case... The buttons for operating the controls, volume control buttons, or the display unit 5902 can be turned on or off. It can be equipped with one of the following: a switch or the like. Also, as shown in Figure 33(B) The Towatch indicates that there are 2 operation buttons (5903), but the smartwatch has... The number of operation buttons is not limited to this. Also, the control element 5904 is a smartwatch It functions as a crown for setting the time. In addition, the control 5904 is used for functions other than time setting. It is used as an input interface for operating smartwatch applications. It may be done in this way. Note that in the smartwatch shown in Figure 33(B), the operator 590 The configuration has 4, but is not limited to this, and may also have a configuration without the operator 5904. That's fine.

[0229] <Video camera> Figure 33(C) shows a video camera, consisting of a first housing 5801, a second housing 5802, and a display unit 5 It has 803, an operation key 5804, a lens 5805, a connecting part 5806, etc. One embodiment of the present invention The video camera can be equipped with a memory device. Operation key 5804 and lens 58 05 is provided in the first housing 5801, and the display unit 5803 is provided in the second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connecting part 5806. The connection is maintained, and the angle between the first housing 5801 and the second housing 5802 is determined by the connecting part 5806. It can be changed. The video on the display unit 5803 is connected to the first housing on the connection unit 5806. The configuration may also be such that the switching occurs according to the angle between 5801 and the second housing 5802.

[0230] <Mobile phone> Figure 33(D) shows a mobile phone with information terminal functionality, consisting of a housing 5501 and a display unit 55 It has 02, a microphone 5503, a speaker 5504, and an operation button 5505. One embodiment of the present invention The storage device can be installed in a mobile phone. Also, the display unit 5502 has a position input device. A display device with added positioning functionality may be used. This functionality can be added by providing a touch panel on the display device. The function as a position input device involves a photoelectric conversion element, also called a photosensor, which is used in the display device's image. It can also be added by providing it in the base part. Furthermore, a mobile phone can be connected to the operation button 5505. Power switch for turning on the device, buttons for operating mobile phone applications, volume control buttons. The device must also include a switch to turn the display unit 5502 on or off. It is possible.

[0231] Furthermore, the mobile phone shown in Figure 33(D) has two operation buttons 5505. However, the number of control buttons on a mobile phone is not limited to this. Also, although not shown in the diagram... The mobile phone shown in Figure 33(D) is equipped with a light-emitting device for use as a flashlight or illumination. It may also be a configuration that includes a placement.

[0232] <Television equipment> Figure 33(E) is a perspective view showing a television system. The television system consists of a housing 9 000, display unit 9001, speaker 9003, operation key 9005 (power switch, or (including operating switch), connection terminal 9006, sensor 9007 (force, displacement, position, velocity, acceleration) Speed, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field It measures electric current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation. A storage device according to one aspect of the present invention is provided for use in a television device. Television equipment can have a large screen, for example, 50 inches or more, or 100 inches. It is possible to incorporate a display unit 9001 with a size of 1 inch or larger.

[0233] <Mobile> The aforementioned storage devices can also be applied to the area around the driver's seat of a mobile vehicle.

[0234] For example, Figure 33(F) is a diagram showing the area around the windshield inside a car. Figure 33(F) shows the display panel 5701 and display panel 5 mounted on the dashboard. In addition to display panel 5703 (702), a display panel 5704 mounted on the pillar is also shown. It is.

[0235] Display panels 5701 to 5703 display navigation information, speedometer - Various information such as tachometer, mileage, fuel level, gear status, air conditioning settings, etc. It can provide information. Also, the display items and layout displayed on the display panel are It can be modified as needed to suit the user's preferences, and the design can be enhanced. Display panels 5701 to 5703 can also be used as lighting devices. be.

[0236] The display panel 5704 displays images from an imaging device installed on the vehicle body. This allows for the correction of the blind spot (view obstructed by the pillars). In other words, on the outside of the car... By displaying images from the provided imaging means, blind spots are compensated for, and safety is enhanced. This is possible. Furthermore, by displaying images that fill in the gaps in the unseen areas, it becomes more natural and less jarring. Safety checks can be performed without any problems. The display panel 5704 can also be used as a lighting device. can.

[0237] A storage device according to one aspect of the present invention can be installed in a mobile device. For example, when displaying an image on display panel 5701 to display panel 5704, Frame memory for temporarily storing image data, and the system that drives the moving object. It can be used as a storage device to save programs, etc.

[0238] Additionally, although not shown in the illustrations, electronic devices are shown in Figures 33(A) to (C), (E), and (F). This configuration may include a microphone and a speaker. With this configuration, for example, as described above This allows electronic devices to be equipped with voice input functionality.

[0239] In addition, although not shown in the illustrations, electronic devices are shown in Figures 33(A), (B), (D) to (F). This configuration may include a camera.

[0240] Also, although not shown in the illustrations, the electronic devices shown in Figures 33(A) to (F) are located inside the enclosure. Sensors (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity, gradient, vibration It may also be a configuration that includes a function for measuring motion, odor, or infrared radiation. In addition, the mobile phone shown in Figure 33(D) has a tilt detection sensor such as a gyroscope and an accelerometer. By providing a detection device that has a s, the orientation of the mobile phone (the mobile phone is in the vertical direction) can be determined. The device determines the orientation of the mobile phone and displays the screen of the display unit 5502 accordingly. It can be configured to switch automatically depending on the situation.

[0241] Also, although not shown in the illustrations, the electronic devices shown in Figures 33(A) to (F) are fingerprint, vein, The configuration may include a device that acquires biological information such as iris scans or voiceprints. By using this technology, it is possible to realize electronic devices with biometric authentication capabilities.

[0242] Furthermore, the display unit of the electronic device shown in Figures 33(A) to (F) is made of a flexible substrate. It may also be used. Specifically, the display unit has a transistor and a capacitor on a flexible substrate. The configuration may include elements and display elements. By applying this configuration, This includes not only housings with flat surfaces, such as the electronic devices shown in Figures 33(A) to (F), but also curved housings. This makes it possible to realize electronic devices with enclosures that have surfaces.

[0243] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0244] (Notes regarding the descriptions in this specification, etc.) A description of each component in the above embodiment is provided below.

[0245] <Notes relating to one aspect of the present invention described in the embodiments> The configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to represent the present invention. This can be one embodiment. Furthermore, multiple configuration examples may be shown within a single embodiment. The combination allows for appropriate combinations of the configuration examples.

[0246] Furthermore, the content described in one embodiment (even a part of it) may be subject to change in implementation. Other details (even partial details) described in the form, and one or more other embodiments The content to be stated (even if only a part of it) should be applied to or combined with at least one other content. It is possible to replace or otherwise perform actions such as [doing something else].

[0247] Furthermore, the content described in each embodiment refers to the use of various figures in each embodiment. This refers to the content described or the content described using the text included in the specification.

[0248] Note that a diagram (even a part of it) described in one embodiment may be a part of that diagram. In that embodiment, another figure (even if only a part of it) and one or more other figures For at least one of the diagrams (even if only a part of it) described in the form of the installation, the combination By doing so, even more diagrams can be constructed.

[0249] <Notes regarding ordinal numbers> In this specification, the ordinal numbers "1st," "2nd," and "3rd" are used to avoid confusion of constituent elements. This was added to avoid [the problem]. Therefore, it does not limit the number of components. Furthermore, this does not limit the order of the components. Also, for example, the embodiments described herein The component referred to as "first" in one is in another embodiment or in the claims. It may also be the component referred to in "Second" in [the relevant section]. Furthermore, for example, in this specification, etc. In one embodiment, the component referred to as "first" is used in other embodiments, or It may be omitted in the claims.

[0250] <Notes regarding descriptions of drawings> The embodiments are described with reference to the drawings. However, the embodiments differ in many ways. It is possible to implement it in such a manner, without deviating from its purpose and scope, in that form. It will be easily understood by those skilled in the art that the form and details can be changed in various ways. Therefore, The invention is not to be interpreted as being limited to the contents described in the embodiments. In the structure of the invention, the same reference numerals are used for identical parts or parts having similar functions in different drawings. We will use it consistently throughout, and will omit the explanation of its repetition.

[0251] Furthermore, in this specification, phrases indicating placement such as "above" and "below" refer to the relative positions of the components. The positional relationships are used for convenience in explaining them by referring to the diagram. The positional relationships between the components are The arrangement changes appropriately depending on the direction in which each component is described. Therefore, the words indicating the arrangement are specified in the specification. The explanation provided is not the only way to express the idea; it can be appropriately rephrased depending on the situation.

[0252] Furthermore, the terms "up" and "down" refer to situations where the relative positions of the constituent elements are directly above or directly below, and directly connected. It does not limit what is being done. For example, if the expression is "electrode B on insulating layer A", It is not necessary for electrode B to be directly in contact with insulating layer A, and the insulating layer A and electrode B are not in direct contact. This does not exclude those that include other components in between.

[0253] Furthermore, in the drawings, the size, layer thickness, or area are shown at arbitrary sizes for the sake of explanation. Therefore, it is not necessarily limited to that scale. Furthermore, the drawings are made with clarity in mind. This is a schematic representation and is not limited to the shapes or values ​​shown in the drawings. For example... , variations in signals, voltages, or currents due to noise, or signals due to timing discrepancies This can include variations in voltage, current, and other parameters.

[0254] Furthermore, in drawings, in perspective views and other similar views, some structural elements are used to ensure clarity of the drawings. In some cases, the original description may be omitted.

[0255] Furthermore, in the drawings, identical elements or elements with similar functions, elements of the same material, and In some cases, elements formed simultaneously may be given the same symbol, and the explanation for this repetition is as follows: It may be omitted in some cases.

[0256] <Notes regarding paraphrasable descriptions> In this specification and other documents, when describing the connection relationships of transistors, the source and drain are referred to as one The side is referred to as "either the source or the drain" (or the first electrode, or the first terminal), and the source The other side of the source and drain is referred to as "the other side of the source or drain" (or the second electrode, or the second terminal). It is indicated that the source and drain of a transistor are related to the structure or movement of the transistor. This is because it varies depending on the operating conditions, etc. Regarding the terminology for the source and drain of a transistor... Depending on the situation, you can use appropriate terms such as source (drain) terminal or source (drain) electrode. They can be replaced. Also, in this specification, the two terminals other than the gate are referred to as the first terminal and the second terminal. These may be referred to as terminals, or as the third terminal, fourth terminal, etc. The channel formation region refers to the region where a channel is formed by applying an electric potential to the gate. This region is formed, allowing current to flow between the source and drain.

[0257] Furthermore, the source and drain functions may differ when using transistors with different polarities, or when the circuit The direction of the current may change during operation, which can cause the current to switch positions. In detailed documents, the terms "source" and "drain" may be used interchangeably. ru.

[0258] Furthermore, when the transistor described herein has two or more gates (this configuration (This is sometimes called a dual-gate structure), and these gates are called the first gate, the second gate and It can be called by name, or it can be called the front gate or back gate. In particular, "front gate" The phrases " " can be replaced with the phrase "gate". Also, The term "backgate" can be interchanged with the term "gate." The bottom gate is a region in the transistor fabrication process that is larger than the channel formation region. It refers to the terminal that is formed first, and the term "top gate" is used when manufacturing a transistor. This refers to terminals that are formed after the channel formation region.

[0259] Furthermore, in this specification, the terms "electrode" and "wiring" refer to these components functionally. It is not limited to this. For example, "electrode" can be used as part of "wiring". And the reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and This includes cases where the wiring is formed as an integrated unit.

[0260] Furthermore, in this specification, voltage and potential may be used interchangeably as appropriate. Voltage is a base This refers to the potential difference from the reference potential; for example, the reference potential is the ground potential (earth potential). If we consider it as electric potential, then voltage can be rephrased as electric potential. Ground potential is not necessarily 0V. This does not necessarily mean that. Furthermore, electric potential is relative, and depending on the reference potential, This may change the potential supplied to wiring, etc.

[0261] In this specification, the terms "membrane," "layer," etc. may be used in some cases or in some situations. Depending on the context, they can be interchanged. For example, the term "conductive layer" can be replaced with "conductive layer". In some cases, the term can be changed to "electromagnetic film." Alternatively, for example, "insulating film" could be used. In some cases, the term may be changed to "insulating layer." Or, depending on the circumstances... Alternatively, depending on the situation, you can replace terms such as "membrane" or "layer" with other terms. It is possible to use the term "conductor" instead of "conductive layer" or "conductive film". In some cases, the terminology can be changed. For example, terms such as "insulating layer" or "insulating film" can be used. In some cases, it may be possible to change the term to "insulator."

[0262] In this specification, terms such as "wiring," "signal line," and "power line" may be used as appropriate. Depending on the situation, they can be interchanged. For example, "wiring" and In some cases, it may be possible to change the term "signal line" to "signal line". Also, for example, In some cases, the term "wiring" can be changed to terms such as "power lines." Conversely, terms such as "signal line" and "power line" should be changed to the term "wiring." In some cases, this may be possible. Terms such as "power lines" may be changed to terms such as "signal lines." This is sometimes possible. Conversely, terms like "signal line" can also be used for "power line," etc. In some cases, it may be possible to change the terminology. Also, the "potential" applied to the wiring Change the terminology to a term like "signal," depending on the circumstances or situation. This is sometimes possible. Conversely, terms like "signal" can also be used in the context of "electric potential." It may be possible to change it to a different word.

[0263] <Notes regarding the definition of terms> The following explains the definitions of terms used in the above embodiment.

[0264] <<Regarding impurities in semiconductors>> Impurities in semiconductors refer to components other than the main components that make up the semiconductor layer, for example. Elements present in less than 0.1 atomic percent are considered impurities. The presence of impurities can, for example, affect semiconductors. The formation of Density of States (DOS) and carrier mobility In some cases, the quality may decrease, or the crystallinity may decrease. In the case of semiconductors, impurities that alter the properties of semiconductors include, for example, Group 1 elements and Group 2 elements. These include elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components. In particular, for example, hydrogen (also found in water), lithium, sodium, silicon, boron, ri These include hydrogen, carbon, and nitrogen. In the case of oxide semiconductors, for example, the inclusion of impurities such as hydrogen can cause problems. This can lead to the formation of oxygen vacancies. Furthermore, if the semiconductor is a silicon layer, the semiconductor properties... Impurities that alter the composition include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, and Group 1 elements. These include Group 3 elements and Group 15 elements.

[0265] <<About the switch>> In this specification, a switch refers to a conductive state (on state) or a non-conductive state (off state). This refers to a device that has the function of controlling whether or not to allow current to flow when it enters a certain state. Alternatively, it can refer to a switch. A switch is a device that has the function of selecting and switching the path through which electric current flows.

[0266] For example, an electrical switch or a mechanical switch can be used. Furthermore, any switch that can control the current will suffice, and is not limited to any particular type.

[0267] An example of an electrical switch is a transistor (for example, a bipolar transistor). MOS transistors, diodes (for example, PN diodes, PIN diodes, Schottky diode, MIM (Metal Insulator Metal) die Od, MIS (Metal Insulator Semiconductor) die Odes, diode-connected transistors, etc., or logic circuits combining these. There is.

[0268] Furthermore, when using a transistor as a switch, the "conductive state" of the transistor refers to: A state in which the source and drain electrodes of a transistor can be considered to be electrically short-circuited. Also, the "non-conductive state" of a transistor refers to the state where the source electrode and drain electrode of the transistor are connected. This refers to a state in which the poles can be considered electrically blocked. Note that a transistor is not simply a switch. When operating in this manner, the polarity (conductivity type) of the transistor is not particularly limited.

[0269] One example of a mechanical switch is a digital micromirror device (DMD). Switches using MEMS (Micro-Electro-Mechanical Systems) technology are Yes, it exists. The switch has electrodes that can be moved mechanically, and when those electrodes move... Therefore, it operates by controlling the states of conduction and non-conductivity.

[0270] <<About Connection>> In this specification, etc., when it is stated that X and Y are connected, it means that X and Y are electrically connected. When they are directly connected, when X and Y are functionally connected, and when X and Y are directly connected This includes cases where a connection is made. Therefore, a predetermined connection relationship, for example, in the diagram or This includes not only connections shown in text, but also connections other than those shown in diagrams or text. It shall be considered as such.

[0271] Here, X, Y, etc., refer to the object (e.g., device, element, circuit, wiring, electrode, terminal). (Conductive film, layer, etc.)

[0272] One example of a case where X and Y are electrically connected is when the electrical connection between X and Y is possible. Elements that perform this function (for example, switches, transistors, capacitive elements, inductors, resistive elements, etc.) One or more elements (such as ions, display elements, light-emitting elements, and loads) are connected between X and Y. This is possible. Furthermore, the switch has a function that allows it to be controlled to be on or off. In other words, A switch can be either conductive (on) or non-conductive (off), allowing current to flow. It has a function to control whether or not it is released.

[0273] One example of a functional connection between X and Y is a functional connection between X and Y. Circuits that can perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signals) Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits ( Power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc. ), voltage source, current source, switching circuit, amplification circuit (which can increase signal amplitude or current amount, etc.) Circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc., signal generation One or more circuits (such as memory circuits and control circuits) can be connected between X and Y. For example, even if another circuit is placed between X and Y, the signal output from X If the signal is transmitted to Y, then X and Y are assumed to be functionally connected.

[0274] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y are electrically connected. When connected electrically (i.e., connected with another element or circuit in between X and Y) (if such a connection exists) and (if X and Y are functionally connected) (When functionally connected with another circuit in between) and when X and Y are directly connected (That is, the case where X and Y are connected without another element or circuit in between) It shall be assumed that they are electrically connected. In other words, when explicitly stating that they are electrically connected, simply, This is equivalent to the case where it is explicitly stated that it is "continued."

[0275] For example, the source (or first terminal, etc.) of the transistor is connected via Z1 (or Without an intermediary, X is electrically connected, and the drain of the transistor (or the second terminal, etc.) is connected. If Y is electrically connected via (or without) Z2, or if the transistor's saw A part of Z1 (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. They are indirectly connected, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. When they are connected and another part of Z2 is directly connected to Y, the following table It can be expressed.

[0276] For example, "X and Y and the source (or first terminal, etc.) and drain (or the first terminal) of the transistor" Terminals 2, etc., are electrically connected to each other, and X is the source of the transistor (or The electrical components are connected in the following order: the first terminal (or the second terminal), the transistor's drain (or the second terminal), and Y. It can be expressed as "connected to the source (or the source) of the transistor." Terminal 1 (or terminal 2) is electrically connected to X, and the drain (or terminal 2) of the transistor is connected to X. (d) is electrically connected to Y, X is the source of the transistor (or the first terminal, etc.), and the transistor The drain (or second terminal, etc.) of the converter, Y, is electrically connected in this order. It can be expressed as, "X is the source (or first terminal, etc.) of the transistor." Alternatively, "X is the source (or first terminal, etc.) of the transistor." Y is electrically connected to X, and the transient is electrically connected to X via the drain (or second terminal, etc.) and the drain. The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.) It can be expressed as, "Y is provided in this connection order." Similar to these examples... By using a method of representation to specify the order of connections in a circuit configuration, the transition Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of the starter. This allows us to determine the technical scope. Note that these expressions are just examples, and this... The method of expression is not limited to these. Here, X, Y, Z1, Z2 are objects (e.g., devices, (Examples include elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.)

[0277] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even if such a combination exists, one component may possess the functions of multiple components. Yes. For example, if part of the wiring also functions as an electrode, one conductive film will function as the wiring, and It possesses the functions of both components of the electrode. Therefore, in this specification Electrically connected means that a single conductive film combines the functions of multiple components. This also falls under that category.

[0278] <<Regarding parallel and perpendicular lines>> In this specification, "parallel" means that two lines are positioned at an angle of -10° or more and 10° or less. This refers to a state in which it is in a certain condition. Therefore, it also includes cases where the angle is between -5° and 5°. Also, "abbreviated "Parallel" refers to a state where two straight lines are positioned at an angle between -30° and 30°. Furthermore, "perpendicular" refers to a state where two straight lines are positioned at an angle between 80° and 100°. This refers to the case where the angle is between 85° and 95°. Furthermore, "approximately perpendicular" means This refers to a state where two straight lines are positioned at an angle between 60° and 120°. [Explanation of Symbols]

[0279] BGL Wiring ER wiring RBL wiring RBL1 Wiring RBL2 Wiring RWL wiring WBL Wiring WBL1 Wiring WBL2 Wiring WWL wiring WWL_D Wiring 10 memory modules 100-layer structure 101A Insulator 101B Insulator 101C insulator 101D Insulator 101E Insulator 102 Insulator 103 Insulator 104 Insulator 105 Insulator 131A Conductor 131B Conductor 132A Conductor 132B Conductor 133 Conductors 133a Conductor 133b Conductor 133c conductor 134 Conductors 151 Semiconductors 151a area 151b area 151c area 152 Semiconductors 153 Semiconductors 153a Semiconductor 153b Semiconductor 181A area 181B area 182A area 182B area 183A area 183B area 191 Opening 192A Recess 192B Recess 193A Recess 193B Recess 194A Recess 194B Recess 194C recess 1000 logic layers 1189 ROM Interface 1190 circuit board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 1700 circuit boards 1701 Element Isolation Layer 1712 Conductors 1730 Conductor 1790 🙏 1792 Well 1793 Channel formation region 1794 Low concentration impurity region 1795 High concentration impurity region 1796 Conductive region 1797 Gate insulating film 1798 Sidewall insulation layer 1799 Sidewall insulation layer 2000 memory layers 2600 storage device 2601 Peripheral Circuits 2610 memory cell array 2621 Low Decoder 2622 Word Line Driver Circuit 2630 bit line driver circuit 2630A Bit Line Driver Circuit 2630B Bit Line Driver Circuit 2631 Column Decoder 2632 Precharge Circuit 2633 SenseAmp 2634 circuits 2640 Output Circuit 2660 Control Logic Circuit 5100 USB flash drive 5101 enclosure 5102 Cap 5103 USB connector 5104 circuit board 5105 memory chip 5106 Controller Chip 5110 SD card 5111 enclosure 5112 connector 5113 circuit board 5114 memory chip 5115 Controller Chip 5150 SSD 5151 enclosure 5152 Connector 5153 circuit board 5154 memory chip 5155 memory chip 5156 Controller Chip 5401 enclosure 5402 Display section 5403 Keyboard 5404 Pointing device 5501 enclosure 5502 Display section 5503 Microphone 5504 Speaker 5505 Operation Buttons 5701 Display Panel 5702 Display Panel 5703 Display Panel 5704 Display Panel 5801 enclosure 5802 enclosure 5803 Display section 5804 Operation Keys 5805 Lens 5806 Connection part 5901 enclosure 5902 Display section 5903 Operation Buttons 5904 Operator 5905 Band 9000 cabinets 9001 Display section 9003 Speaker 9005 Operation Keys 9006 Connection terminal 9007 Sensor

Claims

[Claim 1] It comprises a first to nth (where n is an integer of 2 or more) memory cell, a selection transistor, and a first wiring, The first to n memory cells are connected in series, Either the source or the drain of the selection transistor is electrically connected to the first wiring. The source or drain of the selection transistor, the other of which is electrically connected to the first terminal of the first memory cell, The second terminal of the n memory cell is electrically connected to the first wiring, The first memory cell comprises a first transistor having a first oxide semiconductor in its channel formation region, and a second transistor having a second oxide semiconductor in its channel formation region. The gate of the first transistor is electrically connected to either the source or the drain of the second transistor. The gate of the first transistor is electrically connected to the first terminal of the first memory cell. The channel formation region of the first transistor has a first region that overlaps with the second oxide semiconductor, The channel formation region of the second transistor has a second region that overlaps with the first oxide semiconductor. In the first region, the second oxide semiconductor has a concave shape, and the inside of the concave shape is in contact with a conductive layer.

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