Power converter and control device for power converter

Abstract

A control device (21) for a power converter (20) comprises: a current sensor (25); a plurality of semiconductor drive units (23); and a main control unit (22). Each of the plurality of semiconductor drive units (23) is provided to a corresponding switching element among a plurality of switching elements (S) constituting the power converter (20), and adjusts a switching speed of the corresponding switching element (S) in accordance with a corresponding drive capability adjustment signal. The main control unit (22) outputs, to each of the plurality of switching elements (S), a drive signal for controlling a switching timing on the basis of a current detection value from the current sensor (25). The main control unit (22) generates, for each semiconductor drive unit (23), a corresponding drive capability adjustment signal on the basis of a relationship between the switching timing of the corresponding switching element (S) and a timing of current detection by the current sensor (25).

Description

Technical Field

[0001] The present disclosure relates to a power conversion device and a control device for a power converter.

Background Art

[0002] In a shunt current detection type inverter device, in order to restore three-phase currents based on the current flowing through the DC bus, it is necessary to detect the current in two different switching states for each carrier period of PWM (Pulse Width Modulation). In this case, since current detection immediately after switching involves errors, the current of the DC bus is detected after a waiting time T , ,

[0005] , , ,

[0006] , , , has elapsed.

[0003] Japanese Patent Application Laid-Open No. 11-4594 (Patent Document 1) discloses a countermeasure when at least one of the two components of the output voltage vector Vs is less than the waiting time T MIN is less than. Specifically, the inverter device of this document has means for calculating two vectors Vs' and Vs" in which each of the two components is at least equal to the waiting time T MIN so that the vector average of these vectors Vs' and Vs" is equal to the output voltage vector Vs.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the method of Patent Document 1 described above, when the original output voltage command is in the overmodulation region, it may not be possible to generate the vectors Vs' and Vs" such that the vector average of the vectors Vs' and Vs" is equal to the output voltage vector Vs.

[0006] This disclosure has been made in consideration of the above-mentioned problems, and one of its objectives is to provide a control device for a power converter that can perform current detection with the shortest possible waiting time from switching. [Means for solving the problem]

[0007] A control device for a power converter according to one embodiment is provided. The power converter includes a plurality of switching elements and performs power conversion by switching the plurality of switching elements. The control device comprises a current sensor, a plurality of semiconductor drive units, and a main control unit. The current sensor is provided to detect the current flowing through the plurality of switching elements. Each of the semiconductor drive units is provided for a corresponding switching element among the plurality of switching elements and adjusts the switching speed of the corresponding switching element according to a corresponding drive capability adjustment signal. The main control unit outputs a drive signal to each of the plurality of switching elements to control the switching timing based on the current detection value from the current sensor. For each semiconductor drive unit, the main control unit generates a corresponding drive capability adjustment signal based on the relationship between the switching timing of the corresponding switching element and the timing of current detection from the current sensor. [Effects of the Invention]

[0008] According to the above embodiment, for each semiconductor drive unit, a corresponding drive capability adjustment signal is generated based on the relationship between the switching timing of the corresponding switching element and the timing of current detection by the current sensor, thereby adjusting the switching speed of the corresponding switching element. This makes it possible to perform current detection with the shortest possible waiting time from switching. [Brief explanation of the drawing]

[0009] [Figure 1] This is a circuit diagram showing an example configuration of a power conversion device according to Embodiment 1. [Figure 2] Figure 1 is a block diagram showing an example of the configuration of the main control unit. [Figure 3] This figure shows an example of the configuration of the semiconductor drive unit shown in Figure 1. [Figure 4] This figure shows an example of how the switching waveform changes with and without drive capability adjustment. [Figure 5] Figure 2 is a timing diagram showing an example of the operation of the main control unit. [Figure 6] This figure illustrates the switching state of the main circuit corresponding to the drive signal in Figure 5. [Figure 7] Figure 2 is a timing diagram showing another example of the operation of the main control unit. [Figure 8] This is a timing diagram showing the control operation of a comparative example. [Figure 9] This is a timing diagram showing an example of the operation of the main control unit in the power conversion device of Embodiment 2. [Figure 10] This is a flowchart showing the operation of the drive capability adjustment unit in the power converter of Embodiment 2. [Figure 11] This is a block diagram showing an example of the configuration of the main control unit in an inverter device as a power conversion device according to Embodiment 3. [Figure 12] Figure 11 is a timing diagram showing an example of the operation of the main control unit. [Figure 13] This flowchart shows the operation of the drive capability adjustment unit and the drive signal generation unit in the power conversion device of Embodiment 3. [Modes for carrying out the invention]

[0010] Each embodiment will be described in detail below with reference to the drawings. In the following description, a single-shunt current detection inverter device will be used as an example, but the power conversion device of this disclosure is not limited to an inverter device, and the current detection method is not limited to a single-shunt method but may be a triple-shunt method or other current detection method. The same or corresponding parts will be denoted by the same reference numerals and their descriptions will not be repeated.

[0011] Embodiment 1. [Overall configuration of the power converter] Figure 1 is a circuit diagram showing an example configuration of a power conversion device according to Embodiment 1. In Figure 1, an inverter device 10 that drives a three-phase motor 13 is shown as an example of a power conversion device.

[0012] Furthermore, Figure 1 shows an example configuration for supplying a DC voltage Vdc to the inverter device 10, which includes an AC power supply 11 representing an AC power system and a converter circuit 12. The converter circuit 12 converts AC power received from the AC power system into DC power. A high-potential DC bus 33 is connected to the high-potential output node 31 of the converter circuit 12, and a low-potential DC bus 34 is connected to the low-potential output node 32 of the converter circuit 12.

[0013] Instead of the AC power supply 11 and converter circuit 12 described above, a DC power supply such as a storage battery or solar cell may be used. Furthermore, a DC / DC converter may be provided between the DC power supply and the inverter device 10.

[0014] The inverter device 10, as a power conversion device, comprises a main circuit 20 and a control device 21 that controls the main circuit 20. In this disclosure, the main circuit 20 is also referred to as a power converter or inverter circuit.

[0015] The main circuit 20 converts the DC power supplied via DC buses 33 and 34 into AC power by switching multiple switching elements Sup, Svp, Swp, Sun, Svn, and Swn (collectively referred to as switching element S). The main circuit 20 drives the motor 13 by supplying the converted AC power to the motor 13.

[0016] More specifically, the main circuit 20 includes a switching element Sup on the upper U-phase arm, a switching element Sun on the lower U-phase arm, a switching element Svp on the upper V-phase arm, a switching element Svn on the lower V-phase arm, a switching element Swp on the upper W-phase arm, and a switching element Swn on the low-potential side of the lower W-phase arm. Switching element Sup is connected between the high-potential DC bus 33 and the U-phase output node 35. Switching element Sun is connected between the low-potential DC bus 34 and the U-phase output node 35. Switching element Svp is connected between the high-potential DC bus 33 and the V-phase output node 36. Switching element Svn is connected between the low-potential DC bus 34 and the V-phase output node 36. Switching element Swp is connected between the high-potential DC bus 33 and the W-phase output node 37. The U-phase current iu, V-phase current iv, and W-phase current iw are output to the motor 13 from the U-phase output node 35, the V-phase output node 36, and the W-phase output node 37, respectively.

[0017] In Figure 1, an IGBT (Insulated Gate Bipolar Transistor) is shown as an example of the switching element S, but it is not limited to this. For example, a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) or a bipolar power transistor may be used as the switching element S.

[0018] The control device 21 includes a main control unit 22, semiconductor drive units 23up, 23un, 23vp, 23vn, 23wp, 23wn, a DC capacitor 24, and a shunt resistor 25. In the following description, the semiconductor drive units 23up, 23un, 23vp, 23vn, 23wp, 23wn will be referred to collectively as semiconductor drive unit 23, or any one of them will be referred to as semiconductor drive unit 23.

[0019] The main control unit 22 outputs a drive signal (also called a gate signal) and a drive capability adjustment signal for controlling the main circuit 20, based on the DC current value detected by the shunt resistor 25. A more detailed configuration example of the main control unit 22 will be described later with reference to Figure 2.

[0020] The DC capacitor 24 is connected between the high-potential output node 31 and the low-potential output node 32 of the converter circuit 12. The DC voltage Vdc across the DC capacitor 24 is input to the main control unit 22.

[0021] The shunt resistor 25, acting as a current sensor, detects the current flowing through the DC bus 33 or 34. In Figure 1, the shunt resistor 25 is located on the low-potential DC bus 34, but it may also be located on the high-potential DC bus 33. The voltage across the ends of the shunt resistor 25 is input to the main control unit 22. Instead of the shunt resistor 25, a current transformer (CT) using a Hall element or the like may be used as a current detector, and the type of current sensor is not particularly limited.

[0022] The semiconductor drive units 23up, 23un, 23vp, 23vn, 23wp, and 23wn are provided in correspondence to the switching elements Sup, Sun, Svp, Svn, Swp, and Swn, respectively. Each semiconductor drive unit 23 controls the opening and closing timing of the corresponding switching element S and adjusts its drive capability based on gate signals and drive capability adjustment signals individually input from the main control unit 22. An example of the configuration of the semiconductor drive unit 23 will be described later with reference to Figure 3.

[0023] [Example configuration and operation of the main control unit] Figure 2 is a block diagram showing an example configuration of the main control unit 22 in Figure 1. As shown in Figure 2, the main control unit 22 includes a current detection unit 40, a voltage detection unit 41, a motor control unit 42, a drive signal generation unit 43, and a drive capability adjustment unit 44.

[0024] The current detection unit 40 and voltage detection unit 41 described above include an AD (Analog-to-Digital) conversion circuit, a buffer circuit, a filter circuit, and the like.

[0025] The motor control unit 42, drive signal generation unit 43, and drive capability adjustment unit 44 described above are composed of a combination of hardware such as a microcomputer including a CPU and memory, and an FPGA (Field Programmable Gate Array), and software (program). Alternatively, at least a part of these may be composed of logic circuits such as an ASIC (Application Specific Integrated Circuit). The functions of each component will be described below.

[0026] The current detection unit 40 detects the DC current Idc flowing through the low-potential DC bus 34 based on the voltage Vr across the shunt resistor 25. Details of the current detection technology in the single-shunt system will be described later.

[0027] The voltage detection unit 41 detects the DC voltage Vdc input to the inverter device 10 based on the voltage Vc across the DC capacitor 24.

[0028] The motor control unit 42 generates a voltage command value VC to be applied to the motor 13 based on the information detected by the current detection unit 40 and the voltage detection unit 41, and the operation command OC, such as the set rotation speed command value. For example, the motor control unit 42 estimates the operating state of the motor 13, such as the rotation speed, using known sensorless speed control, and generates a voltage command value VC based on the estimated operating state.

[0029] The drive signal generation unit 43 generates a drive signal DS (also called a gate signal) for controlling the on / off state of each switching element S constituting the main circuit 20 of the inverter device 10, based on the voltage command value VC.

[0030] In the first embodiment, the drive signal generation unit 43 generates the drive signal DS by PWM control based on a comparison between the triangular wave carrier signal and the voltage command value VC. Alternatively, the drive signal DS output to each switching element S may be generated using other methods such as the spatial vector method, instead of using the triangular wave carrier signal.

[0031] The voltage command value VC is often updated at regular control cycles (for example, at the timing of the peaks or troughs of the triangular wave carrier signal). Therefore, at the timing of the voltage command value VC update, the drive signal generation unit 43 and the drive capability adjustment unit 44 can pre-calculate the on and off timings of the gate signal, as well as the lengths of the on and off times, for one cycle of the next carrier signal.

[0032] The drive capability adjustment unit 44 generates a drive capability adjustment signal AS (also simply called an adjustment signal) for adjusting the switching speed of each switching element S based on the voltage command value VC and the drive signal DS. The drive capability adjustment unit 44 outputs the generated drive capability adjustment signal AS to the semiconductor drive unit 23 corresponding to each switching element S. Each switching element S changes its switching speed according to the drive capability adjustment signal AS.

[0033] [1. Shunt Current Detection Technology] The following describes the single-shunt current detection technology. In the inverter device 10 that drives the electric motor 13, a single-shunt system is used to reduce the number of three-phase current sensors connected to the output terminal. In the single-shunt system, the value of the three-phase AC current output from the inverter device 10 is restored based on the measurement result of the DC current detected by the shunt resistor 25 connected to the DC bus 33 or 34.

[0034] In this single-shunt system, the DC current value is detected in at least two switching states for each PWM cycle in order to restore the three-phase output current. At this time, after the output state of the main circuit 20 is switched by the switching of multiple switching elements S, there is a waiting time T before the current is actually detected. MINis provided. This waiting time T MIN is necessary to ensure the sample hold time and dead time of the AD conversion circuit, and to avoid the effects such as ringing and control delay associated with switching. Specifically, the waiting time T MIN is often set for each driving ability of the switching element based on the results of previously conducted tests or calculations. Also, since the recovery current and surge voltage depend on the magnitude of the output current, the waiting time T MIN may be set or switched using the output current information as well.

[0035] The current detection unit 40 in the present embodiment detects a direct current when the waiting time elapses after switching to the switching state in a predetermined switching state. The switching state is determined based on the drive signal DS generated by the drive signal generation unit 43. Further, the current detection unit 40 restores the output current of each phase of the inverter device 10 based on the detected direct current value and the drive signal DS. The waiting time T MIN may be a preset value or switched to a value specified by the drive ability adjustment unit 44.

[0036] In the one-shunt type current detection technique as described above, since the waiting time T MIN is required in principle, there is a problem that current detection cannot be performed when the voltage vector is output for a period shorter than the waiting time T[[ID=

[19] ] MIN As a result, there is a period during which current detection cannot be performed even during normal operation. In particular, in the case of a low modulation rate where the output voltage of the inverter is small or an overmodulation rate where the output voltage is large, the influence of the waiting time T MIN is so great that almost no current can be detected. As a result, there is a risk that the control of the motor 13 becomes unstable, etc., and the control response of the motor 13 is limited.

[0037] As will be described in detail later, in the inverter device 10 of this embodiment, the switching speed of each switching element S is adjusted by the drive capability adjustment unit 44, thereby suppressing the effects of ringing and reducing the waiting time T MIN This can be shortened. As a result, the controllability of the electric motor 13 can be improved and the operating range of the electric motor 13 can be expanded.

[0038] [Example configuration and operation of the semiconductor drive unit] Figure 3 shows an example configuration of the semiconductor drive unit 23 in Figure 1. Figure 3 shows three examples of methods for adjusting the switching speed of the switching element S. However, any method that allows for adjustment of the switching speed is acceptable, not limited to the following three examples.

[0039] Specifically, referring to Figure 3(A), the semiconductor drive unit 23 includes a drive circuit 50 and a plurality of resistance adjustment circuits 51. The drive circuit 50 includes an NPN bipolar transistor 52 and a PNP bipolar transistor 53 connected in series between a power node (not shown) and ground (not shown). A drive signal DS is input to the gates of the bipolar transistors 52 and 53.

[0040] Multiple resistance adjustment circuits 51 are connected in parallel between the connection nodes of bipolar transistors 52 and 53 and the gate of the switching element S. Each resistance adjustment circuit 51 includes a resistor 54 and a switch 55 connected in series. The on / off state of the switch 55 of each resistance adjustment circuit 51 is controlled by a drive capability adjustment signal AS. By switching each switch 55 on and off, the gate resistance value of the switching element S can be changed, thereby adjusting the switching speed of the switching element S.

[0041] Referring to Figure 3(B), the semiconductor drive unit 23 includes a drive voltage adjustment circuit 56 and a drive circuit 50. The configuration of the drive circuit 50 is the same as in Figure 3(A). In the drive circuit 50, the connection nodes of the bipolar transistors 52 and 53 are connected to the gates of the switching element S. The gates of the bipolar transistors 52 and 53 are input to a drive signal DS amplified by a voltage amplifier 57 (for example, an operational amplifier circuit) that constitutes the drive voltage adjustment circuit 56. The amplification factor of the voltage amplifier 57 can be adjusted by the drive capability adjustment signal AS. This allows the gate voltage when switching the bipolar transistors 52 and 53 on and off to be adjusted, thereby allowing the switching speed of the switching element S to be adjusted.

[0042] Referring to Figure 3(C), the semiconductor drive unit 23 includes a drive circuit control unit 58 and a plurality of drive circuits 59 connected in parallel. Each drive circuit 59 includes an enhancement-type P-channel MOSFET 60 connected between a power supply node (not shown) and the gate of the switching element S, and an enhancement-type N-channel MOSFET 61 connected between the gate of the switching element S and ground (not shown).

[0043] The drive circuit control unit 58 supplies drive signals DS to the gates of MOSFETs 60 and 61 that constitute the drive circuit 59 selected by the drive capability adjustment signal AS. This allows the number of parallel-connected MOSFETs that are turned on to be changed according to the drive capability adjustment signal AS, thereby adjusting the drive current for charging and discharging the gates of the switching element S. As a result, the switching speed of the switching element S can be adjusted.

[0044] Figure 4 shows an example of the change in switching waveform with and without drive capability adjustment. Figure 4(A) shows the waveform of the collector-emitter voltage Vce at turn-on, and Figure 4(B) shows the waveform of the collector current Ic at turn-on. In Figures 4(A) and (B), the waveform without drive capability adjustment is shown by a solid line, and the waveform with drive capability adjustment is shown by a dashed line.

[0045] Referring to Figure 4(A), by adjusting the drive capability and reducing the switching speed of the switching element S, a delay occurs in the timing at which the collector-emitter voltage Vce drops from the power supply voltage Vdc to zero voltage.

[0046] Referring to Figure 4(B), by adjusting the drive capability to reduce the switching speed of the switching element S, the fluctuation rate of the collector current Ic during turn-on is reduced, and overshoot due to the recovery current is suppressed.

[0047] Note that while Figures 4(A) and (B) show the current overshoot due to the recovery current, the illustration of the oscillation component is omitted. In actual circuits, the switching waveform often contains an oscillation component.

[0048] Specifically, the recovery current during switching and the change in the current path (commutation) when the switching element S is turned off cause LC resonances based on the capacitive and inductive components in the loop composed of DC buses 33 and 34, DC capacitor 24, switching element S, and shunt resistor 25 to be excited. The oscillation waveform based on these LC resonances is then included in the switching waveform as ringing.

[0049] Here, the capacitive and inductive components in the loop are determined by the circuit that makes up the loop. Due to constraints such as physical distances including insulation distance and component size, the inductive components will occur at a certain magnitude. Therefore, in order to reduce the oscillation components, it is necessary to reduce the energy that causes ringing, such as recovery current and current commutation.

[0050] It is generally known that reducing the turn-on speed of the corresponding switch when a recovery current is generated reduces the recovery current. Furthermore, reducing the current change during turn-off, i.e., the turn-off speed, can suppress the excitation of oscillations in the circuit loop including the shunt resistor. In other words, if there are concerns about adverse effects due to ringing, the effects of ringing can be suppressed by temporarily reducing the switching speeds of both the turn-on and turn-off of the switching element S. As a result, the waiting time T in shunt current detection is reduced. MIN This can reduce the amount of switching required. However, reducing the switching speed leads to increased switching losses, so it is best to use as few switching elements as possible that change their drive capability.

[0051] [Details of the operation of the main control unit 22] Figure 5 is a timing diagram showing an example of the operation of the main control unit 22 in Figure 2. In Figure 5, the waveforms of the drive signals DSu, DSv, DSw (collectively referred to as drive signals DS) for each phase, the switching state SWS, the drive capability adjustment signals ASu, ASv, ASw (collectively referred to as drive capability adjustment signals AS) for each phase, the DC current Idc, and the current detection timing are shown for one cycle of the PWM carrier signal.

[0052] The motor control unit 42 and drive signal generation unit 43 of the main control unit 22 update command values ​​such as the voltage command value VC and drive signal DS based on the voltage and current values ​​detected up to that point, at each control cycle equal to the period of the triangular wave carrier signal CR. Specifically, in the case of Figure 5, the main control unit 22 updates the command value at the peak of the carrier signal CR (time t1).

[0053] The drive signal generation unit 43 generates the drive signals DS for each phase based on a comparison between the voltage command value VC for each phase and the carrier signal CR. Specifically, in the case of Figure 5, between time t2 and time t17, the U-phase voltage command value VCu becomes greater than the carrier signal CR, so the U-phase drive signal DSu becomes high level ("1"), and during the rest of the period shown in the figure, the U-phase drive signal DSu becomes low level ("0"). Similarly, between time t5 and time t14, the V-phase drive signal DSv becomes high level ("1"), and between time t8 and time t11, the W-phase drive signal DSw becomes high level ("1").

[0054] In this embodiment, when the drive signal DS is at a high level ("1"), the switching element S of the upper arm is in the ON state and the switching element S of the lower arm is in the OFF state. When the drive signal DS is at a low level ("0"), the switching element S of the upper arm is in the OFF state and the switching element S of the lower arm is in the ON state.

[0055] However, the above drive signals DSu, DSv, and DSw are the drive signals before the dead time is applied. During the on / off switching, a dead time is provided in which both the upper and lower arms have their switching elements S in the off state. Specifically, in the case of Figure 5, the dead time is from time t2 to time t3, from time t5 to time t6, from time t8 to time t9, from time t11 to time t12, from time t14 to time t15, and from time t17 to time t18.

[0056] The drive signals after the dead time are as follows: The drive signal DSup for the switching element Sup of the U-phase upper arm is high level from time t3 to time t17 and low level during the other periods shown in Figure 1. The drive signal DSun for the switching element Sun of the U-phase lower arm is low level from time t2 to time t18 and high level during the other periods shown in Figure 5.

[0057] Similarly, the drive signal DSvp for the V-phase upper arm switching element Svp is high level from time t6 to time t14 and low level for the rest of the time in Figure 1. The drive signal DSvn for the V-phase lower arm switching element Svn is low level from time t5 to time t15 and high level for the rest of the time in Figure 5.

[0058] Similarly, the drive signal DSwp for the W-phase upper arm switching element Swp is high level from time t9 to time t11 and low level for the rest of the time shown in Figure 1. The drive signal DSwn for the W-phase lower arm switching element Swn is low level from time t8 to time t12 and high level for the rest of the time shown in Figure 5.

[0059] When the drive signals for the upper arm and the lower arm of each phase are at a high level, the corresponding switching element S is turned on, and when they are at a low level, the corresponding switching element S is turned off.

[0060] Figure 6 is a diagram illustrating the switching states of the main circuit 20 corresponding to the drive signal DS in Figure 5. Furthermore, Figure 6 shows the current paths corresponding to each switching state. Here, the U-phase output current iu and W-phase output current iw are considered positive, and the V-phase output current iv is considered negative. The output current in the direction from the inverter device 10 to the motor 13 is considered positive.

[0061] There are four switching states SWS of the main circuit 20 of the inverter device 10 corresponding to each drive signal DS in Figure 5, from A to D. Referring to Figure 6(A), in switching state A (from time t1 to t2 and from time t18 onwards in Figure 5), the switching elements Sup, Svp, and Swp on the upper arm of any of the U-phase, V-phase, and W-phase are in the off state, and the switching elements Sun, Svn, and Swn on the lower arm of any of the U-phase, V-phase, and W-phase are in the on state. In this case, no current flows through the shunt resistor 25.

[0062] Referring to Figure 6(B), in switching state B (times t3 to t5 and t15 to t17 in Figure 5), the switching element Sup on the upper arm of the U-phase is ON, and the switching element Sun on the lower arm of the U-phase is OFF. On the other hand, the switching elements Svp and Swp on the upper arms of the V-phase and W-phase are OFF, while the switching elements Svn and Swn on the lower arms of the V-phase and W-phase are ON. In this case, the U-phase current iu flows through the shunt resistor 25.

[0063] Referring to Figure 6(C), in switching state C (times t6 to t8 and t12 to t14 in Figure 5), the switching elements Sup and Svp on the upper arms of the U and V phases are ON, while the switching elements Sun and Svn on the lower arms of the U and V phases are OFF. On the other hand, the switching element Swp on the upper arm of the W phase is OFF, while the switching element Swn on the lower arm of the W phase is ON. In this case, the W phase current iw flows through the shunt resistor 25.

[0064] Referring to Figure 6(D), in switching state D (times t8 to t11 in Figure 5), the switching elements Sup, Svp, and Swp on the upper arms of the U, V, and W phases are ON, and the switching elements Sun, Svn, and Swn on the lower arms of the U, V, and W phases are OFF. In this case, no current flows through the shunt resistor 25.

[0065] Therefore, the U-phase current iu can be detected in switching state B, and the W-phase current iw can be detected in switching state C. The V-phase current iv can be calculated from the relationship iu + iv + iw = 0. In this way, the three-phase output current can be reconstructed based on the currents detected in multiple switching states.

[0066] Referring again to Figure 5, the drive capability adjustment unit 44 determines which switching element S's drive capability to adjust during the adjustment period, based on the switching timing of each switching element S estimated when the voltage command value VC is updated. In the case of Figure 5, the drive capability adjustment period is set to the falling edge period of the carrier signal CR (i.e., half a period of the carrier signal CR from time t1 to time t10). Alternatively, the adjustment period may be set in relation to the carrier signal CR, such as the rising edge period of the carrier signal CR, or it may be set in relation to some operation, such as a fixed period ending at the current detection timing.

[0067] In the example shown in Figure 5, drive capability adjustment is performed to reduce the switching speed from the initially set normal value during the switching of the U-phase upper and lower arms, which is performed immediately before detecting the U-phase current at time t4, and during the switching of the V-phase upper and lower arms, which is performed immediately before detecting the W-phase current at time t7. If current detection is not performed after switching (specifically, the switching of the W-phase upper and lower arms and the switching in the latter half of the cycle of the carrier signal CR), drive capability adjustment is not performed.

[0068] Waiting time T' MIN This assumes that the switching speed is reduced compared to normal, and the normal waiting time T MIN It is set to a shorter time than T'. MIN The specific value is set based on the results of tests or calculations performed in advance.

[0069] Figure 7 is a timing diagram showing another example of the operation of the main control unit 22 in Figure 2. The timing diagram in Figure 7 corresponds to the timing diagram in Figure 5 and shows the waveforms of the drive signal DS, switching state SWS, drive capability adjustment signal AS, DC current Idc for each phase, and current detection timing for each phase during one carrier cycle.

[0070] The control operation in Figure 7 differs from that in Figure 5 in that the W-phase current is detected at time t13 in addition to time t7, and the U-phase current is detected at time t16 in addition to time t4. Therefore, the first and second halves of one cycle of the carrier signal CR are set as adjustment periods for the drive capability.

[0071] Specifically, in the switching of the upper and lower arms of the U-phase performed immediately before detecting the U-phase current at time t4, the switching of the upper and lower arms of the V-phase performed immediately before detecting the W-phase current at time t7, the switching of the upper and lower arms of the W-phase performed immediately before detecting the W-phase current at time t13, and the switching of the upper and lower arms of the V-phase performed immediately before detecting the U-phase current at time t16, a drive capability adjustment is performed to reduce the switching speed to a level lower than normal. The standby time is set to the initial normal standby time T, assuming that the switching speed will be reduced to a level lower than normal. MIN Shorter waiting time T' MIN This is set to [value]. If current detection is not performed after switching (specifically, switching of the W-phase upper and lower arms at times t8 and t9, and switching of the U-phase upper and lower arms at times t17 and t18), the drive capability adjustment will not be performed.

[0072] Other aspects of Figure 7 are the same as those in Figure 5, so the same reference numerals are used for the same or corresponding parts, and the explanation is not repeated.

[0073] Thus, taking into account the effect of current ripple due to switching, the number of current detections may be increased from two to four times per cycle of the carrier signal CR. Alternatively, the number of times the switching speed is adjusted may be varied depending on the number and method of current detection.

[0074] [Effects of Embodiment 1] In the inverter device 10 as a power conversion device of Embodiment 1, a corresponding drive capability adjustment signal is adjusted for each semiconductor drive unit 23 based on the relationship between the switching timing of the corresponding switching element S and the timing of current detection by the current sensor 25. As a result, the ringing effect caused by the switching operation immediately before current detection is suppressed by switching the switching speed. Furthermore, style Waiting time T from the switching immediately before detection to current detection. MIN This reduces the current detection range, thereby expanding the operating range in which current can be detected, and consequently improving the control characteristics of the motor.

[0075] In Embodiment 1, the drive capability of the switching element S was adjusted to reduce the switching speed, but the reverse is also possible. For example, if the inductive and capacitive components of the circuit loop including the shunt resistor are small and ringing hardly occurs, the drive capability can be adjusted to increase the switching speed and reduce the dead time, thereby reducing the waiting time T MIN Efforts may be made to reduce this. An example of increasing the switching speed will be described in Embodiment 3.

[0076] Embodiment 2. In Embodiment 2, the drive capability adjustment and standby time T are performed. MIN This section explains an example of switching between making and not making changes to the drive capacity adjustment and the waiting time T. MIN A comparative example in which none of the above changes are made will be described, and then the operation of the main control unit of the power converter of this embodiment will be described in comparison to that example.

[0077] The hardware configuration of the power conversion device (for example, an inverter device) in Embodiment 2 is the same as that of Embodiment 1, which was described with reference to Figures 1 to 4, so the description will not be repeated.

[0078] [Operation of the main control unit in the comparative example] Figure 8 is a timing diagram showing the control operation of a comparative example. The timing diagram in Figure 8 corresponds to the timing diagram in Figure 5 and shows the drive signal DS, switching state SWS, drive capability adjustment signal AS, DC current waveform, and current detection timing for each phase during one carrier cycle.

[0079] The control operation in Figure 8 uses a normal waiting time T as the waiting time until current detection. MIN The method used differs from that in Figure 5 in that no drive capability adjustment is performed in either switching operation. Furthermore, in the control operation of Figure 8, the period between the switching of the V phase and the switching of the W phase (i.e., switching state C) is shorter than in Figure 5. Other aspects of Figure 8 are the same as those in Figure 5, so the same or corresponding parts are denoted by the same reference numerals and the explanation is not repeated.

[0080] As shown in Figure 8, the current detection timing for the U phase (time t4) is within the switching state B period (from time t3 to t5). Therefore, the waiting time T MIN U-phase current detection is possible without any changes or adjustments to the drive capability. On the other hand, there is a waiting period T until the W-phase current detection timing. MIN Because the next W-phase switching occurs during this process, W-phase current detection is not possible. Therefore, in order to detect the W-phase current, the waiting time must be shorter T'. MIN In addition to making this change, it will be necessary to adjust the drive capability by slowing down the switching speed in order to suppress ringing during switching.

[0081] [Operation of the main control unit of this embodiment] Figure 9 is a timing diagram showing an example of the operation of the main control unit in the power converter of Embodiment 2. The timing diagram in Figure 9 corresponds to the timing diagram in Figure 8, but T' has a shorter waiting time until W-phase current detection. MINThis differs from the timing diagram in Figure 8 in that it is changed to a different configuration, and the drive capability adjustment is performed to slow down the switching speed during the switching of the upper and lower arms of the V phase immediately before the W phase current detection timing at time t7. As a result, the W phase current detection timing (time t7) falls within the period of switching state C (from time t6 to t8), making W phase current detection possible.

[0082] On the other hand, the waiting time until the current detection timing for the U phase (time t4) is the initially set normal waiting time T MIN This remains unchanged. No drive capability adjustment is performed during U-phase switching immediately before the current detection timing (time t4). Since current detection is possible without adjusting the drive capability in this way, it is possible to prevent unnecessary increases in switching losses due to a reduction in switching speed.

[0083] Thus, the drive capability adjustment unit 44 adjusts the initial normal waiting time T MIN T' MIN The system determines whether current detection becomes possible by shortening the standby time. If current detection becomes possible by shortening the standby time, the drive capability adjustment unit 44 adjusts the drive capability by slowing down the switching speed compared to normal. The above determination and the output of the drive capability adjustment signal AS are performed each time the voltage command value VC is updated, based on the on and off timings of the drive signal and the lengths of the on and off times estimated based on the voltage command value VC. The operation of the drive capability adjustment unit 44 performed each time the voltage command value VC is updated will be described below with reference to Figure 10.

[0084] Figure 10 is a flowchart showing the operation of the drive capability adjustment unit 44 in the power converter of Embodiment 2. The flowchart in Figure 10 shows the operation of the drive capability adjustment unit 44 when current detection is performed after switching of the upper and lower arms of any first phase, which is one of the U phase, V phase, and W phase.

[0085] First, in step S10, the drive capability adjustment unit 44 determines the waiting period T after switching of the upper and lower arms of the first phase based on an estimated time until the switching state changes, which is determined according to the voltage command value VC. MIN Determine whether the next switching will occur.

[0086] The drive capability adjustment unit 44 adjusts the initial normal standby period T MIN If it is determined that no further switching will occur (NO in step S10), the process proceeds to step S20. In step S20, the drive capability adjustment unit 44 sets the waiting time to the normal waiting time T MIN Set to the specified waiting time T MIN The current detection unit 40 outputs the current. Furthermore, the drive capability adjustment unit 44 outputs a drive capability adjustment signal AS to the semiconductor drive unit 23 of the first phase upper and lower arms so that the switching of the first phase upper and lower arms is performed at the initially set normal speed.

[0087] The drive capability adjustment unit 44 has a standby period T MIN If it is determined that the next switching will occur (YES in step S10), then in the next step S30, a waiting period T' will be observed after the switching of the upper and lower arms of the first phase. MIN Determine whether the next switching will occur during this time. Waiting time T' MIN is T MIN It is a shorter period of time.

[0088] The drive capability adjustment unit 44 controls the standby period T' MIN If it is determined that no further switching will occur (NO in step S30), the process proceeds to step S40. In step S40, the drive capability adjustment unit 44 adjusts the waiting time T' which is the waiting time with a reduced waiting time. MIN Set to the current detection unit 40 and set the waiting time T' MIN It outputs the following. Furthermore, the drive capability adjustment unit 44 switches the upper and lower arms of the first phase. Gu A drive capability adjustment signal AS is output to the semiconductor drive unit 23 of the first phase upper and lower arms so that it is executed at a low speed.

[0089] The drive capability adjustment unit 44 controls the standby period T' MIN If it is determined that the next switching will occur (YES in step S30), the process proceeds to step S50. In step S50, the drive capability adjustment unit 44 controls the current detection unit 40 so as not to perform current detection in the switching state after the switching of the upper and lower arms of the first phase. Furthermore, the drive capability adjustment unit 44 controls the switching of the upper and lower arms of the first phase Gu A drive capability adjustment signal AS is output to the semiconductor drive unit 23 of the first phase upper and lower arms so that it operates at normal speed.

[0090] The same applies when current detection is performed after switching of the upper and lower arms of the second phase, which is different from the first phase. This allows the length of the waiting time and the switching speed to be adjusted according to the duration of the multiple switching states for which current detection is performed for each cycle of the carrier signal.

[0091] [Effects of Embodiment 2] According to the inverter device 10 as a power conversion device of Embodiment 2, it is determined whether or not to shorten the standby time from the initial setting value depending on the duration of the switching state in which current detection is performed. If the standby time is shortened, the drive capability is adjusted to reduce the switching speed from the initial setting value in order to suppress the effects of ringing. As a result, the reduction of the standby time and the reduction of the switching speed are performed only when necessary for current detection, so adverse effects such as increased switching losses due to the decrease in switching speed can be suppressed while maintaining the number of current detections as much as possible.

[0092] Embodiment 3. In Embodiment 3, in addition to the switching timing of each phase based on the voltage command value VC, the waiting time until current detection and the switching speed are adjusted based on the polarity (positive and negative) of the output current of each phase detected and restored by the current detection unit. This will be explained in more detail below with reference to the drawings.

[0093] [Example of configuration of the main control unit 22A] Figure 11 shows the main control unit in the inverter device 10 as a power conversion device of Embodiment 3. 22A Configuration For example This is a block diagram. In the main control unit 22A of Figure 11, the drive capability adjustment unit 44 differs from the main control unit 22 of Figure 2 in that the value of the three-phase AC current restored by the current detection unit 40 is further input to it. Details of the operation of the drive capability adjustment unit 44 in Embodiment 3 will be described later with reference to Figures 12 and 13.

[0094] Other aspects of Figure 11 are the same as those in Figure 2, so the same or corresponding parts are denoted by the same reference numerals and the description will not be repeated. Also, the other hardware configuration of the power converter in Embodiment 3 is the same as that of Embodiment 1, which was described with reference to Figures 1, 3, and 4, so the description will not be repeated.

[0095] [Details of the operation of the main control unit 22A] Figure 12 is a timing diagram showing an example of the operation of the main control unit 22A in Figure 11. 2 The timing diagram in Figure 5 roughly corresponds to the timing diagram in Figure 5 and shows the drive signals DS for the upper and lower arms of each phase, the switching state SWS, the drive capability adjustment signals AS for the upper and lower arms of each phase, the DC current waveform, and the current detection timing for one carrier cycle.

[0096] However, while Figure 5 shows the drive signals DSu, DSv, and DSw for each phase before the dead time is applied, Figure 12 shows the drive signals for the upper and lower arms of each phase after the dead time is applied.

[0097] Furthermore, in Figure 5, the drive capability adjustment signal AS for the upper arm and the drive capability adjustment signal AS for the lower arm were the same, but in Figure 1 2 In this case, the drive capability adjustment signal AS for the upper arm and the drive capability adjustment signal AS for the lower arm may be different. Figure 1 2This shows the drive capability adjustment signal ASup corresponding to the switching element Sup on the U-phase upper arm, the drive capability adjustment signal ASun corresponding to the switching element Sun on the U-phase lower arm, the drive capability adjustment signal ASvp corresponding to the switching element Svp on the V-phase upper arm, the drive capability adjustment signal ASvn corresponding to the switching element Svn on the V-phase lower arm, the drive capability adjustment signal ASwp corresponding to the switching element Swp on the W-phase upper arm, and the drive capability adjustment signal ASwn corresponding to the switching element Swn on the W-phase lower arm.

[0098] Note that the switching states A to D in Figure 12 are the same as in Figure 5 and correspond to (A) to (D) in Figure 6, respectively. As in Figure 6, the polarity of the U-phase output current iu and the W-phase output current iw is set to positive, and the polarity of the V-phase output current is set to negative. Here, the polarity of the output current is set to positive when the output current flows from the main circuit 20 of the inverter device 10 towards the motor 13, and to negative when the output current flows in the reverse direction. In addition, each switching element S has a configuration in which an IGBT and a freewheeling diode are connected in parallel.

[0099] The behavior of the main circuit 20, including the switching of current paths and the generation of recovery current in response to the switching state, will be explained below with reference to Figures 5 and 12. Furthermore, the appropriate settings for the standby time and switching speed of the main circuit 20, taking its behavior into account, will be explained. As will be explained below, the behavior of the main circuit 20 changes depending on the polarity of the output current.

[0100] At time t2 in Figure 12, the switching element Sun of the lower U-phase arm is turned off. This transitions the system from switching state A shown in Figure 6(A) to a dead time when the switching element Sun of the lower U-phase arm is in the off state. During this dead time, current continues to flow through the freewheeling diode of the lower U-phase arm. Therefore, ringing does not occur when the lower U-phase arm is turned off, and adjustment of the driving capability of the switching element Sun of the lower U-phase arm is unnecessary.

[0101] At the next time t3, the switching element Sup on the upper U-phase arm is turned on. This transitions to switching state B shown in Figure 6(B), causing the current that was flowing through the freewheeling diode on the lower U-phase arm to be commutated to the switching element Sup on the upper U-phase arm. This commutation generates a recovery current, which causes ringing.

[0102] To suppress this ringing, the drive capability adjustment unit 44 adjusts the drive capability of the switching element Sup to reduce the turn-on speed of the U-phase upper arm. Furthermore, since ringing can be suppressed, the waiting time until current detection is reduced to the normal waiting time T. MIN From T MIN_A This can be shortened to waiting time T. MIN_A The specific value is set based on the results of tests or calculations performed in advance.

[0103] Waiting time T from time t2 MIN_A At time t4, after the time has elapsed, switching state B is maintained. At this time t4, the current detection unit 40 detects the current of the U phase.

[0104] At the next time t5, the switching element Svn on the lower V-series arm is turned off. This transitions the system from switching state B shown in Figure 6(B) to a dead time when the switching element Svn on the lower V-series arm is in the off state. Due to the turn-off of the switching element Svn, the current that was flowing through the switching element Svn on the lower V-series arm is commutated to the freewheeling diode on the upper V-series arm.

[0105] At the next time t6, the switching element Svp on the V-phase upper arm is turned on. This transitions to the switching state C shown in Figure 6(C), but forward current continues to flow through the freewheeling diode on the V-phase upper arm both before and after the switching element Svp is turned on. In this case, no recovery current is generated, and therefore no ringing caused by recovery current occurs. In addition, no commutation delay due to dead time occurs.

[0106] Thus, the switching of the upper and lower arms of the V phase at times t5 and t6 above avoids the effects of ringing and dead time due to recovery current. Therefore, the waiting time can be reduced to T MIN_B ( <T MIN_A This can be significantly reduced to the normal dead time t. d kara t' d This can be shortened to the above waiting time T. MIN_B The specific values ​​are set based on the results of prior tests or calculations. The turn-on speed of the V-phase upper arm can remain at the normal switching speed, and no adjustment of the drive capability is necessary.

[0107] Furthermore, if the turn-off speed of the V-phase lower arm is increased, the turn-off surge may become excessive, potentially damaging the equipment. In this case, whether or not to adjust the drive capability to the high-speed side is determined in advance, depending on the characteristics of the circuit and switching elements.

[0108] The subsequent operation of the main control unit 22 is the same as in Figure 5 of Embodiment 1, so the same or corresponding parts are denoted by the same reference numerals and the description is not repeated.

[0109] Figure 13 is a flowchart showing the operation of the drive capability adjustment unit 44 and the drive signal generation unit 43 in the power converter of Embodiment 3. The flowchart in Figure 13 shows the operation of the drive capability adjustment unit 44 and the drive signal generation unit 43 when current detection is performed after switching of the upper and lower arms of any first phase, which is one of the U phase, V phase, and W phase. The operation of the drive capability adjustment unit 44 and the drive signal generation unit 43 in Figure 13 is performed when the voltage command value VC is updated for each cycle of the carrier signal and after the update, and is determined according to the switching state of each switching element and the polarity of the output current based on the voltage command value VC.

[0110] In steps S100 and S110 of Figure 13, it is determined whether the polarity of the output current of the first phase is positive (YES in step S100) or negative (YES in step S110).

[0111] Furthermore, a hysteresis width and dead zone are set for determining the current polarity. For example, within ±10% of the rated current is determined to be the dead zone (NO for both steps S100 and S110). This is because, in the case of motors with large current fluctuations and near zero current where the current polarity is prone to change, the current polarity may change during one cycle of the carrier signal.

[0112] First, we will explain the case where the polarity of the output current of the first phase is positive (YES in step S100), and where it is estimated that the switching element S of the lower arm of the first phase will be turned on after the switching element S of the upper arm of the first phase is turned off, based on the voltage command value VC (YES in step S120). In this case, the current flowing through the first phase is commutated from the switching element S of the upper arm to the freewheeling diode of the lower arm due to the turn-off of the switching element S of the upper arm. Even when the switching element S of the lower arm is turned on, the current of the first phase continues to flow through the freewheeling diode of the lower arm. Therefore, ringing caused by recovery current does not occur.

[0113] Therefore, in the next step S130, the drive signal generation unit 43 sets the dead time to a normal value t d Shorter than t' d Set to the shortest waiting time. The drive capability adjustment unit 44 sets to the shortest waiting time. MIN_B ( <T MIN_A <T MIN Set to ) and set the waiting time T MIN_B The current detection unit 40 outputs the current. Furthermore, the drive capability adjustment unit 44 outputs a drive capability adjustment signal AS to the semiconductor drive units 23 of the upper and lower arms of the first phase so that the turn-off of the upper arm of the first phase is performed at high speed and the turn-on of the lower arm of the first phase is performed at normal speed.

[0114] On the other hand, if the polarity of the output current of the first phase is positive (YES in step S100), and it is estimated that the switching element S of the upper arm of the first phase will be turned on after the switching element S of the lower arm of the first phase is turned off based on the voltage command value VC (NO in step S120), the process proceeds to step S140. In this case, even if the switching element S of the lower arm is turned off, current continues to flow through the freewheeling diode of the lower arm. After this, the turning on of the switching element S of the upper arm causes commutation from the freewheeling diode of the lower arm to the switching element S of the upper arm. This causes ringing due to the recovery current. Therefore, it is necessary to suppress the effects of ringing.

[0115] Therefore, in step S140, the drive signal generation unit 43 sets the dead time to a normal value t d The drive capability adjustment unit 44 sets the waiting time to the normal value T. MIN Shorter than T MIN_B Longer T MIN_A Set to the specified waiting time T MIN_A The current detection unit 40 outputs the current. Furthermore, the drive capability adjustment unit 44 outputs a drive capability adjustment signal AS to the semiconductor drive units 23 of the upper and lower arms of the first phase so that the turn-off of the lower arm of the first phase is performed at a normal speed and the turn-on of the upper arm of the first phase is performed at a low speed.

[0116] Next, we will describe the case where the polarity of the output current of the first phase is negative (YES in step S110), and it is estimated that the switching element S of the upper arm of the first phase will be turned on after the switching element S of the lower arm of the first phase is turned off based on the voltage command value VC (YES in step S150). In this case, the current flowing through the first phase is commutated from the switching element S of the lower arm to the freewheeling diode of the upper arm due to the turn-off of the switching element S of the lower arm. Even when the switching element S of the upper arm is turned on, the current of the first phase continues to flow through the freewheeling diode of the upper arm. Therefore, ringing caused by recovery current does not occur.

[0117] Therefore, in the next step S160, the drive signal generation unit 43 sets the dead time to a normal value t d Shorter than t' d Set to the shortest waiting time. The drive capability adjustment unit 44 sets to the shortest waiting time. MIN_B ( <T MIN_A <T MIN Set to ) and set the waiting time T MIN_B The current detection unit 40 outputs the current. Furthermore, the drive capability adjustment unit 44 outputs a drive capability adjustment signal AS to the semiconductor drive units 23 of the upper and lower arms of the first phase so that the turn-off of the lower arm of the first phase is performed at high speed and the turn-on of the upper arm of the first phase is performed at normal speed.

[0118] On the other hand, if the polarity of the output current of the first phase is negative (YES in step S110), and it is estimated that the switching element S of the lower arm of the first phase will be turned on after the switching element S of the upper arm of the first phase is turned off based on the voltage command value VC (NO in step S150), the process proceeds to step S170. In this case, even if the switching element S of the upper arm is turned off, current continues to flow through the freewheeling diode of the upper arm. After this, the turning on of the switching element S of the lower arm causes commutation from the freewheeling diode of the upper arm to the switching element S of the lower arm. This causes ringing due to the recovery current. Therefore, it is necessary to suppress the effects of ringing.

[0119] Therefore, in step S170, the drive signal generation unit 43 sets the dead time to a normal value t d The drive capability adjustment unit 44 sets the waiting time to the normal value T. MIN Shorter than T MIN_B Longer T MIN_A Set to the specified waiting time T MIN_A The current detection unit 40 outputs the current. Furthermore, the drive capability adjustment unit 44 outputs a drive capability adjustment signal AS to the semiconductor drive units 23 of the upper and lower arms of the first phase so that the turn-off of the upper arm of the first phase is performed at a normal speed and the turn-on of the lower arm of the first phase is performed at a low speed.

[0120] Next, we will describe the case where the output current of the first phase is in a dead zone and cannot be determined to be either positive or negative (NO in both steps S100 and S110). In this case, in step S180, the main control unit 22 performs the same control as in the first embodiment. Specifically, the drive signal generation unit 43 sets the dead time to a normal value t d The drive capability adjustment unit 44 sets the waiting time to the normal value T. MIN Shorter than T MIN_B Longer T MIN_A Set to the specified waiting time T MIN_A The current detection unit 40 outputs the current. Furthermore, the drive capability adjustment unit 44 outputs a drive capability adjustment signal AS to the semiconductor drive units 23 of the upper and lower arms of the first phase so that the switching of the upper and lower arms is performed at a low speed.

[0121] Alternatively, the drive signal generation unit 43 sets the dead time to a normal value t d The drive capability adjustment unit 44 sets the standby time to the initially set normal value T. MIN You may leave it as is and not adjust the drive capability.

[0122] [Effects of Embodiment 3] As described above, according to the power converter of Embodiment 3, the standby time for current detection, the driving capability of the switching element S, and the dead time are adjusted based on the polarity of the output current in addition to the switching state of the main circuit 20 based on the voltage command value VC. This further reduces the standby time and the number of elements that require driving capability adjustment. Therefore, the control characteristics of the motor can be improved by expanding the operating range in which current can be detected while suppressing the increase in switching losses as much as possible.

[0123] Furthermore, Embodiment 3 may be combined with Embodiment 2. In other words, if current detection is possible without reducing the waiting time and adjusting the drive capability, these steps may be omitted.

[0124] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this application is indicated by the claims and not by the foregoing description, and all modifications within the meaning and scope equivalent to the claims are intended to be included. [Explanation of Symbols]

[0125] 10 Inverter device (power converter), 11 AC power supply, 12 Converter circuit, 13 Motor, 20 Main circuit (power converter), 21 Control device, 22, 22A Main control unit, 23 Semiconductor drive unit, 24 DC capacitor, 25 Shunt resistor (current sensor), 31 High-potential side output node, 32 Low-potential side output node, 33 High-potential side DC bus, 34 Low-potential side DC bus, 35, 36, 37 Output nodes, 40 Current detection unit, 41 Voltage detection unit, 42 Motor control unit, 43 Drive signal generation unit, 44 Drive capability adjustment unit, 50, 59 Drive circuit, 51 Resistance value adjustment circuit, 52 N-type bipolar transistor, 53 P-type bipolar transistor, 54 Resistor element, 55 Switch, 56 Drive voltage adjustment circuit, 57 Voltage amplifier, 58 Drive circuit control unit, 60, 61 MOSFET, AS Drive capability adjustment signal, CR carrier signal, DS drive signal, Ic collector current, Idc DC current, OC operation command, T MIN ,T' MIN ,T MIN_A ,T MIN_B Delay time, VC voltage command value, Vdc DC voltage, iu, iv, iw output current, t d ,t' d Dead time.

Claims

1. A control device for a power converter, The power converter includes a plurality of switching elements, and performs power conversion by switching the plurality of switching elements. The control device is A current sensor for detecting the current flowing through the plurality of switching elements, Each of the plurality of semiconductor drive units is provided for a corresponding switching element among the plurality of switching elements and adjusts the switching speed of the corresponding switching element according to a corresponding drive capability adjustment signal, The system includes a main control unit that outputs a drive signal to each of the plurality of switching elements for controlling the switching timing based on the current detection value from the current sensor. The main control unit is a control device for a power converter that generates a corresponding drive capability adjustment signal for each semiconductor drive unit based on the relationship between the switching timing of the corresponding switching element and the timing of current detection by the current sensor.

2. The control device for a power converter according to claim 1, wherein when the main control unit generates the drive capability adjustment signal to change the switching speed of the first switching element among the plurality of switching elements from an initial setting value to a lower speed, the control unit sets the time from the switching of the first switching element to the detection of current by the current sensor to be shorter than the initial setting value.

3. The control device for a power converter according to claim 1, wherein when the main control unit generates the drive capability adjustment signal to change the switching speed of the second switching element among the plurality of switching elements to a high speed from the initial setting value, the control device sets the time from the switching of the second switching element to the detection of current by the current sensor to be shorter than the initial setting value.

4. The aforementioned power converter is an inverter circuit that converts DC power supplied from a DC bus into three-phase AC power and outputs it to an electric motor. The aforementioned power converter is High-voltage DC busbar and Low-voltage DC bus and, It includes an upper arm switching element and a lower arm switching element, which are connected in series between the high-potential DC bus and the low-potential DC bus, corresponding to each phase of the three-phase AC power, The current sensor is provided on the high-potential DC bus or the low-potential DC bus. The control device for a power converter according to any one of claims 1 to 3, wherein the main control unit restores the three-phase current flowing between the power converter and the motor based on the currents detected in the multiple switching states of the multiple switching elements, and outputs the drive signal corresponding to each of the multiple switching elements based on the restored three-phase current.

5. In the case where current detection by the current sensor is performed in the switching state after switching of the upper arm and the lower arm of the first phase of the three phases, the control device for a power converter according to claim 4, wherein even if the main control unit changes the switching speed of the upper arm and the lower arm of the first phase to a lower speed than the initial setting value and shortens the waiting period until current detection is performed to a lower speed than the initial setting value, if it is predicted that the next switching will occur during the waiting period, the switching speed will not be changed from the initial setting value, the waiting period will not be changed from the initial setting value, and current detection will not be performed.

6. In the case where current detection by the current sensor is performed in the switching state after switching of the upper arm and the lower arm of the first phase of the three phases, the control unit for a power converter according to claim 4, if it is predicted that no further switching will occur during the waiting period, the control unit will perform current detection without changing the switching speed of the upper arm and the lower arm of the first phase from the initial setting value and without changing the waiting period until current detection is performed from the initial setting value.

7. In the case where the current sensor detects current in the switching state after switching of the upper arm and the lower arm of the first phase of the three phases, the main control unit changes the switching speed of either the upper arm or the lower arm of the first phase from the initial setting value, according to the polarity of the current of the first phase flowing between the power converter and the motor, and does not change the switching speed of the other switching element from the initial setting value, as described in claim 4.

8. The control device for a power converter according to claim 7, wherein, when the main control unit turns on the switching element of the lower arm of the first phase after turning off the switching element of the upper arm of the first phase while the current of the first phase is being output from the power converter in the direction of the motor, the dead time from the turn-off of the upper arm of the first phase to the turn-on of the lower arm of the first phase is set to be shorter than the initial setting value, and the switching speed of the upper arm of the first phase is set to be faster than the initial setting value.

9. The control device for a power converter according to claim 7, wherein, when the main control unit turns on the switching element of the upper arm of the first phase after turning off the switching element of the lower arm of the first phase while the current of the first phase is being input from the motor to the power converter, the dead time from the turn-off of the lower arm of the first phase to the turn-on of the upper arm of the first phase is set to be shorter than the initial setting value, and the switching speed of the lower arm of the first phase is set to be faster than the initial setting value.

10. A control device according to any one of claims 1 to 3, A power conversion device comprising a power converter that includes a plurality of switching elements and performs power conversion by switching the plurality of switching elements.

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