Methods for operating memory devices and memory devices

Abstract

This disclosure provides a memory device, a memory system, and a method for operating the memory device. In a particular embodiment, the disclosed memory device comprises a memory string each having a DSG transistor, a memory cell, and an SSG transistor, and the method comprises programming a first memory cell in a first memory string in a subset of the memory strings, the SSG transistors of the subset of memory strings being coupled to one another. In a particular embodiment, the disclosed method for operating the disclosed memory device comprises verifying the first memory cell without applying a prepulse phase to the first memory cell, programming a second memory cell in a second memory string in a subset after programming the first memory cell, and verifying the second memory cell, including applying a prepulse phase to the second memory cell.

Description

Technical Field

[0001] The present disclosure relates to a memory device and an operation method thereof.

Background Art

[0002] Flash memory is a low-cost and high-density non-volatile solid-state memory medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. With flash memory, various operations such as reading, programming (writing), and erasing can be performed. In the case of NAND flash memory, the erase operation can be performed at the block level, and the program operation or read operation can be performed at the page level.

Summary of the Invention

[0003] In one aspect, the present disclosure is a method for operating a memory device, the memory device comprising a memory string including a drain select gate (DSG) transistor, a memory cell, and a source select gate (SSG) transistor respectively, the method comprising programming a first memory cell of a first memory string in a subset of the memory strings, the SSG transistors of the subset of the memory strings being coupled to each other; verifying the first memory cell without applying a pre-pulse stage to the first memory cell; programming a second memory cell of a second memory string in the subset after programming the first memory cell; and verifying the second memory cell including applying a pre-pulse stage to the second memory cell.

[0004] In some implementations, the method further comprises programming a third memory cell of a third memory string in the subset after programming the first memory string; and verifying the third memory cell including applying a pre-pulse stage to the third memory cell.

[0005] In some implementations, verifying the first memory cell includes turning on the SSG transistors of a subset of memory strings and the DSG transistors of the first memory string, keeping the SSG transistors of memory strings other than the subset of memory strings off while verifying the first memory cell, and keeping the DSG transistors of memory strings other than the first memory string off while verifying the first memory cell.

[0006] In some implementations, verifying the first memory cell further includes applying a pass voltage to the unselected word line during verification of the first memory cell, and applying a verification voltage to the selected word line during verification of the first memory cell after the unselected word line has reached the pass voltage.

[0007] In some implementations, verifying the second memory cell includes turning on the SSG transistors of a subset of memory strings and the DSG transistors of the second memory string, turning on the SSG transistors of memory strings other than the subset of memory strings during the prepulse phase of verifying the second memory cell, and turning on the DSG transistors of memory strings other than the second memory string during the prepulse phase of verifying the second memory cell.

[0008] In some implementations, verifying the second memory cell further includes applying a pass voltage to the unselected word line during the prepulse phase of verifying the second memory cell, and applying a verification voltage to the selected word line during the verification of the second memory cell after the prepulse phase.

[0009] In some implementations, the first period during which the unselected word line reaches the pass voltage during verification of the first memory cell is shorter than the second period during which the unselected word line reaches the pass voltage during verification of the second memory cell.

[0010] In some implementations, the method further includes applying the same voltage to the SSG transistors of a subset of memory strings that are coupled to each other.

[0011] In some implementations, the first memory cell and the second memory cell are connected to the same word line.

[0012] In some implementations, the first time interval between turning on the DSG transistor of the first memory string and applying the first verification voltage to the selected word line is shorter than the second time interval between turning on the DSG transistor of the second memory string and applying the first verification voltage to the selected word line.

[0013] Another aspect of the present disclosure provides a method for operating a memory device, comprising: applying a first voltage to a first DSG transistor in a first memory string during a first verification operation of a first memory cell in a first memory string; applying a second voltage lower than the first voltage to a second DSG transistor in a second memory string before applying a verification voltage to a word line coupled to the first memory cell during the first verification operation; applying a first voltage to a second DSG transistor in a second memory string during a prepulse phase of a second verification operation of a second memory cell in the second memory string coupled to a word line; and applying a third voltage higher than the second voltage to the first DSG transistor in the first memory string during the prepulse phase, wherein a first SSG transistor in a first memory string and a second SSG transistor in a second memory string are coupled to each other, and the first verification operation precedes the second verification operation.

[0014] In some implementations, the second voltage turns off the second DSG transistor, and the third voltage turns on the first DSG transistor.

[0015] Another aspect of the present disclosure provides a memory device comprising: a memory string, each comprising a drain-selection gate (DSG) transistor, a memory cell, and a source-selection gate (SSG) transistor; and peripheral circuits coupled to the memory strings, configured to program a first memory cell of a first memory string in a subset of the memory strings, wherein the SSG transistors of the subset of memory strings are coupled to each other, and to verify the first memory cell without applying a prepulse phase to the first memory cell; and after programming the first memory cell, to program a second memory cell of a second memory string in the subset, and to verify the second memory cell, including applying a prepulse phase to the second memory cell.

[0016] In some implementations, the memory device further includes a DSG cut structure for isolating the DSG transistors of the memory string from each other, and an SSG cut structure for separating the memory string into subsets of memory strings, wherein the DSG transistors of the memory string in each subset are electrically coupled to each other, and the DSG transistors of the memory string in different subsets are isolated by the SSG cut structure.

[0017] In some implementations, peripheral circuits are further configured to program a third memory cell in a subset of third memory strings after programming the first memory cell, and to verify the third memory cell, including applying a prepulse phase to the third memory cell.

[0018] In some implementations, the peripheral circuitry is further configured to turn on the SSG transistors of a subset of memory strings and the DSG transistor of the first memory string, to keep the SSG transistors of memory strings other than the subset of memory strings off during verification of the first memory cell, and to keep the DSG transistors of memory strings other than the first memory string off during verification of the first memory cell.

[0019] In some implementations, the peripheral circuitry is further configured to apply a pass voltage to the unselected word line during verification of the first memory cell, and then, after the unselected word line reaches the pass voltage, to apply a verification voltage to the selected word line during verification of the first memory cell.

[0020] In some implementations, the peripheral circuitry is further configured to turn on the SSG transistors of a subset of memory strings and the DSG transistors of a second memory string, turn on and off the SSG transistors of memory strings other than the subset of memory strings during the prepulse phase for verifying the second memory cell, and turn on and off the DSG transistors of memory strings other than the second memory string during the prepulse phase for verifying the second memory cell.

[0021] In some implementations, the peripheral circuitry is further configured to apply a pass voltage to the unselected word line during the pre-pulse phase of verifying the second memory cell, and after the pre-pulse phase, to apply a verification voltage to the selected word line during the verification of the second memory cell.

[0022] In some implementations, the first period during which the unselected word line reaches the pass voltage during verification of the first memory cell is shorter than the second period during which the unselected word line reaches the pass voltage during verification of the second memory cell.

[0023] In some implementations, the peripheral circuitry is further configured to apply the same voltage to the SSG transistors of a subset of memory strings that are coupled to each other.

[0024] In some implementations, the first memory cell and the second memory cell are connected to the same word line.

[0025] In some implementations, a first time interval between turning on a DSG transistor of a first memory string and applying a first verification voltage to a select word line is shorter than a second time interval between turning on a DSG transistor of a second memory string and applying the first verification voltage to the select word line.

[0026] In some implementations, the SSG cut structure is a physical cut structure.

[0027] In some implementations, the SSG cut structure is an electrical cut structure.

[0028] Another aspect of the present disclosure provides a system comprising a memory device configured to store data, the memory device including memory strings each comprising a drain select gate (DSG) transistor, a memory cell, and a source select gate (SSG) transistor, a DSG cut structure for isolating the DSG transistors of the memory strings from each other, an SSG cut structure for separating the memory strings into subsets of memory strings, wherein the DSG transistors of the memory strings in each subset are electrically coupled to each other and the DSG transistors of the memory strings in different subsets are isolated by the SSG cut structure, and peripheral circuitry coupled to the memory strings and configured to program a first memory cell of a first memory string in a subset of the memory strings, verify the first memory cell without applying a pre-pulse phase to the first memory cell, wherein the SSG transistors of the subset of the memory strings are coupled to each other, program a second memory cell of a second memory string in the subset after programming the first memory cell, and verify the second memory cell including applying a pre-pulse phase to the second memory cell.

Brief Description of the Drawings

[0029] The accompanying drawings, incorporated herein and forming part thereof, illustrate aspects of the disclosure and, together with the text of the specification, further assist in explaining the principles of the disclosure and enabling those skilled in the art to prepare and use the disclosure. [Figure 1] A schematic diagram of a memory device including peripheral circuits according to several aspects of this disclosure is shown. [Figure 2] The image shows a cross-sectional side view of a memory cell array including a NAND memory string according to several aspects of this disclosure. [Figure 3] The following are block diagrams of memory devices including memory cell arrays and peripheral circuits relating to several aspects of this disclosure. [Figure 4A] A schematic diagram of a three-dimensional (3D) NAND memory string relating to several aspects of this disclosure is shown. [Figure 4B] A schematic block diagram of a 3D NAND memory string relating to several aspects of this disclosure is shown. [Figure 4C] A schematic block diagram of a 3D NAND memory string relating to several aspects of this disclosure is shown. [Figure 5A] The waveforms of the word line voltage applied to the selected word line during program operation are shown according to several aspects of this disclosure. [Figure 5B] The waveforms of the word line voltage applied to the selected word line during program operation are shown according to several aspects of this disclosure. [Figure 6A] The following are timing diagrams of program operation relating to several aspects of this disclosure. [Figure 6B] The following are timing diagrams of program operation relating to several aspects of this disclosure. [Figure 6C] The following are timing diagrams of program operation relating to several aspects of this disclosure. [Figure 7A] The following are schematic diagrams of various voltages applied to a memory string during program operation, relating to several aspects of this disclosure. [Figure 7B] The following are schematic diagrams of various voltages applied to a memory string during program operation, relating to several aspects of this disclosure. [Figure 7C] The following are schematic diagrams of various voltages applied to a memory string during program operation, relating to several aspects of this disclosure. [Figure 7D] The following are schematic diagrams of various voltages applied to a memory string during program operation, relating to several aspects of this disclosure. [Figure 8] A flowchart illustrating a method for operating a memory device according to several aspects of this disclosure is shown. [Figure 9] A block diagram of a system having a memory device according to several aspects of this disclosure is shown. [Figure 10A] The diagrams show a memory card having a memory device according to several aspects of this disclosure. [Figure 10B] The diagrams shown represent some aspects of a solid-state drive (SSD) having a memory device according to the present disclosure.

[0030] This disclosure will be explained with reference to the attached drawings. [Modes for carrying out the invention]

[0031] In general, terms can be understood at least partially from their use in context. For example, the term “one or more” as used herein may, at least partially depending on the context, be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a,” “an,” or “the” may, at least partially depending on the context, be understood to convey either a singular or plural usage. Furthermore, the term “based on” may be understood not necessarily to convey an exclusive set of factors, but instead, at least partially depending on the context, may allow for the presence of additional factors that are not necessarily explicitly described.

[0032] Memory devices such as NAND flash memory devices can store multiple bits of information in each memory cell, which has multiple states, in order to increase storage capacity and reduce the cost per bit. The programming operation of a NAND flash memory device involves numerous program cycles and verification cycles. Program time (t PROG To conserve time, the industry has primarily focused on reducing the number of verification cycles. However, for each verification cycle, residual channel potential may remain in the memory string channels after each program cycle, and applying the verification voltage pulse may cause a hot carrier injection (HCI) effect within the memory string channels. Both of these can negatively impact subsequent read operations, for example, by increasing the bad bit count (FBC). Therefore, to "clean" the channels, it is common practice to turn on the memory string channels before and after applying the verification voltage pulse in the so-called "pre-pulse phase" and "post-pulse phase," respectively, within each verification cycle. However, these operations during the pre-pulse and post-pulse phases extend the duration of each verification cycle, thus hindering the saving of program time.

[0033] To address one or more of the aforementioned problems, this disclosure provides a channel cleaning scheme for different memory strings having different channel potentials starting from the pre-pulse phase during a verification operation. In some implementations, the first programmed memory string can skip the pre-pulse phase and / or post-pulse phase in the verification cycle and not clean the channels of the memory string to save programming time. In some implementations, channel cleaning in both the pre-pulse and post-pulse phases of the verification operation can be skipped with respect to the first programmed memory string. In some other implementations, channel cleaning is performed only in the post-pulse phase of the verification operation for the first programmed memory string. The channel cleaning schemes disclosed herein can reduce programming time while still mitigating the adverse effects caused by residual channel potentials and HCI effects.

[0034] Figure 1 shows a schematic circuit diagram of a memory device 100 including peripheral circuits according to several embodiments of the present disclosure. The memory device 100 may include a memory cell array 101 and peripheral circuits 102 coupled to the memory cell array 101. The memory cell array 101 may be a NAND flash memory cell array in which memory cells 106 are provided in the form of an array of NAND memory strings 108, each extending vertically over a substrate (not shown). In several implementations, each NAND memory string 108 includes a plurality of memory cells 106 coupled in series and stacked vertically. Each memory cell 106 may hold a continuous analog value, such as voltage or charge, which depends on the number of electrons trapped within the region of the memory cell 106. Each memory cell 106 may be either a floating-gate memory cell including a floating-gate transistor, or a charge-trapped memory cell including a charge-trap transistor.

[0035] In some implementations, each memory cell 106 has two possible levels (memory states) and is therefore a single-level cell (SLC) capable of storing 1 bit of data. For example, the first level "0" can correspond to a first voltage range, and the second level "1" can correspond to a second voltage range. In some implementations, each memory cell 106 is an xLC capable of storing multiple bits of data at more than four levels. For example, an xLC can store 2 bits per cell (MLC), 3 bits per cell (TLC), or 4 bits per cell (QLC). Each xLC has a range of possible nominal storage values ​​(i.e., 2 N It can be programmed to assume that there are 2 (corresponding to N-bit data). In some implementations, at least one of the memory cells 106 corresponds to 2 (corresponding to N-bit data). N It is set to one of the individual levels, where N is an integer greater than 1.

[0036] As shown in Figure 1, each NAND memory string 108 may include a source selection gate (SSG) transistor 110 (also known as a lower selection gate (BSG) transistor) at its source end and a drain selection gate (DSG) transistor 112 (also known as a upper selection gate (TSG) transistor) at its drain end. The SSG transistor 110 and DSG transistor 112 may be configured to activate the selected NAND memory string 108 (array column) during read and program operations. In some implementations, the sources of the NAND memory strings 108 in the same block 104 are coupled via the same source line (SL) 114, for example, a common SL. In other words, according to some implementations, all NAND memory strings 108 in the same block 104 have an array common source (ACS). According to some implementations, the drain of each NAND memory string 108 is coupled to its respective bit line 116, and data can be read or written from each bit line 116 via an output bus (not shown). In some implementations, each NAND memory string 108 is configured to be selected or deselected by applying a selection voltage (e.g., a positive voltage exceeding the threshold voltage of the DSG transistor 112) or a deselection voltage (e.g., ground voltage) to each DSG transistor 112 via one or more DSG lines 113, and / or by applying a selection voltage (e.g., a positive voltage exceeding the threshold voltage of the SSG transistor 110) or a deselection voltage (e.g., ground voltage) to each SSG transistor 110 via one or more SSG lines 115.

[0037] As shown in Figure 1, a NAND memory string 108 can be organized into multiple blocks 104, each having a common source line 114, for example, coupled to ACS. In some implementations, each block 104 is the basic data unit for erase operations, i.e., all memory cells 106 on the same block 104 are erased simultaneously. To erase the memory cells 106 in a selected block 104, the source lines 114 coupled to the selected block 104 and to non-selected blocks 104 in the same plane as the selected block 104 can be biased with an erase voltage (Vers), such as a high positive bias voltage (e.g., 20V or higher). Memory cells 106 of adjacent NAND memory strings 108 can be coupled via word lines 118 that select which rows of memory cells 106 are affected by read and program operations.

[0038] As shown in Figure 1, the memory cell array 101 can include an array of memory cells 106 with multiple rows and multiple columns within each block 104. According to some implementations, one column of a memory cell corresponds to one NAND memory string 108. Multiple rows of memory cells 106 can each be coupled to a word line 118, and multiple columns of memory cells 106 can each be coupled to a bit line 116. Peripheral circuits 102 can be coupled to the memory cell array 101 via the bit lines 116 and word lines 118.

[0039] Figure 2 shows a cross-sectional side view of a memory cell array 101 including a NAND memory string 108 according to several embodiments of the present disclosure. As shown in Figure 2, the NAND memory string 108 can extend vertically through a memory stack 204 above a substrate 202. The substrate 202 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0040] The memory stack 204 may include interleaved gate conductive layers 206 and intergate dielectric layers 208. The number of pairs of gate conductive layers 206 and intergate dielectric layers 208 in the memory stack 204 can determine the number of memory cells 106 in the memory cell array 101. The gate conductive layers 206 may include, but are not limited to, conductive materials such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each gate conductive layer 206 includes a metal layer such as a tungsten layer. In some implementations, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding the memory cell 106, the gate of the DSG transistor 112, or the gate of the SSG transistor 110, and may extend laterally as a DSG line 113 at the upper end of the memory stack 204, an SSG line 115 at the lower end of the memory stack 204, or a word line 118 between the DSG line 113 and the SSG line 115.

[0041] In some implementations, a DSG cut 210 (also known as a TSG cut) is formed via a DSG line 113 that electrically isolates the DSG line 113 between adjacent regions (e.g., “sets” as referred herein), thereby allowing the DSG line 113 and DSG transistor 112 in different sets to be controlled individually in read and / or program operation. Similarly, in some implementations, an SSG cut 212 (also known as a BSG cut) is formed via an SSG line 115 that electrically isolates the SSG line 115 between adjacent regions (e.g., “finger” as referred herein), thereby allowing the SSG line 115 and SSG transistor 110 in different fingers to be controlled individually in read and / or program operation.

[0042] As shown in Figure 2, the NAND memory string 108 includes a channel structure that extends vertically through the memory stack 204. In some implementations, the channel structure includes a semiconductor material (e.g., as a semiconductor channel) and a dielectric material (e.g., as a memory film). It is understood that additional components of the memory cell array 101, including but not limited to gate line slits / source contacts, local contacts, and interconnect layers, may be formed, although these are not shown in Figure 2.

[0043] Referring back to Figure 1, the peripheral circuit 102 may be coupled to the memory cell array 101 via bit lines 116, word lines 118, source lines 114, SSG lines 115, and DSG lines 113. The peripheral circuit 102 may include any suitable analog, digital, or mixed-signal circuits to facilitate the operation of the memory cell array 101 by applying voltage and / or current signals to each selected memory cell 106 via bit lines 116, word lines 118, source lines 114, SSG lines 115, and DSG lines 113 and sensing voltage and / or current signals from each selected memory cell 106. The peripheral circuit 102 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 3 shows several typical peripheral circuits, including a page buffer / sense amplifier 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, registers 314, an interface (I / F) 316, and a data bus 318. It is understood that some examples may include additional peripheral circuits not shown in Figure 3.

[0044] The page buffer / sense amplifier 304 can be configured to sense (read) and program (write) data to and from the memory cell array 101 according to control signals from the control logic 312. In one example, the page buffer / sense amplifier 304 may store one or more pages of program data (written data referred to herein as “data pages”) to be programmed into a row of the memory cell array 101. In another example, the page buffer / sense amplifier 304 may verify the programmed selected memory cell 106 in each program / verification cycle of the program operation to ensure that the data is properly programmed into the memory cell 106 coupled to the selected word line 118. In yet another example, the page buffer / sense amplifier 304 may also sense a low-power signal from the bit line 116 representing data bits stored in the memory cell 106 and amplify a small voltage amplitude to a recognizable logic level during a read operation.

[0045] The column decoder / bit line driver 306 is controlled by control logic 312 and may be configured to select one or more NAND memory strings 108 by applying bit line voltages generated from a voltage generator 310. The row decoder / word line driver 308 is controlled by control logic 312 and may be configured to select or deselect block 104 of the memory cell array 101 and select or deselect word lines 118 of block 104. The row decoder / word line driver 308 may be further configured to drive word lines 118 using word line voltages generated from a voltage generator 310. In some implementations, the row decoder / word line driver 308 can also similarly select / deselect and drive SSG lines 115 and DSG lines 113. The voltage generator 310 may be controlled by the control logic 312 and configured to generate word line voltages (e.g., read voltage, program voltage, path voltage, local voltage, and verification voltage), bit line voltages, and source line voltages to be supplied to the memory cell array 101.

[0046] The control logic 312 can be coupled to each of the aforementioned peripheral circuits and can be configured to control the operation of each peripheral circuit. The register 314 can be coupled to the control logic 312 and may include a state register, a command register, and an address register for storing state information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 316 is coupled to the control logic 312 and functions as a control buffer for buffering control commands received from a memory controller (not shown) and / or a host (not shown) and relaying them to the control logic 312, and for relaying state information received from the control logic 312 to the memory controller and / or host. The interface 316 is also coupled to the column decoder / bit line driver 306 via the data bus 318 and can function as a data buffer for buffering and relaying data between the data input / output (I / O) interface and the memory cell array 101.

[0047] Figures 4A to 4C show schematic diagrams of 3D NAND memory strings according to some aspects of the present disclosure. Figure 4A shows an example of an array of 3D NAND memory strings (e.g., 108 in Figure 1) within a block (e.g., 104 in Figure 1). As shown in Figure 4A, each 3D NAND memory string may be coupled to several lines in different rows, e.g., DSG lines (DSG, e.g., 113 in Figure 1), dummy DSG lines (upper DMY), word lines (WL, e.g., 118 in Figure 1), dummy SSG lines (lower DMY), SSG lines (SSG, e.g., 115 in Figure 1), and common source lines (CSL, e.g., 114 in Figure 1). As shown in Figure 4A, in both the word line direction (x direction) and the bit line direction (y direction), the word lines may extend laterally to connect the memory cells of the 3D NAND memory string. With respect to the DSG and SSG lines, the DSG and SSG lines may be continuous in the word line direction (x direction) and connect the DSG transistors and SSG transistors of the 3D NAND memory string at the same position in the y direction (e.g., DSG0 and DSG0, SSG0 and SSG0), or they may be separated in the bit line direction (y direction) by DSG cut 402 and SSG cut 404 to form electrically isolated sets 406 and fingers 408 (shown in Figure 4B), which can be individually controlled in program operation.

[0048] As shown in Figures 4B and 4C, an array of 3D NAND memory strings can be divided into multiple sets 406 in the bit line direction (y-direction) by DSG cuts 402 that electrically isolate DSG lines and DSG transistors (e.g., DSG0, DSG1, DSG2, and DSG3, each of which is isolated in Figure 4A). As a result, each set 406 of the 3D NAND memory strings can be individually selected and controlled in program operation by controlling its respective DSG line. As shown in Figures 4B and 4C, an array of 3D NAND memory strings can also be divided into multiple fingers 408 in the bit line direction (y-direction) by SSG cuts 404 that electrically isolate SSG lines and SSG transistors (e.g., SSG0 and SSG1 are isolated from SSG2 and SSG3 in Figure 4A). As a result, each finger 408 of the 3D NAND memory strings can be individually selected and controlled in program operation by controlling its respective SSG line. It should be noted that each finger 408 can contain any appropriate number of sets 406, such as two sets 406 within one finger 408 as shown in Figure 4B, or three sets 406 within one finger 408 as shown in Figure 4C.

[0049] Taking Figure 4A as an example, the array of 3D NAND memory strings may be divided into four sets 406 by three DSG cuts 402, each containing a 3D NAND memory string having DSG0, DSG1, DSG2, and DSG3, respectively. The array of 3D NAND memory strings may also be divided into two fingers 408 by one SSG cut 404, one containing a 3D NAND memory string having SSG0 and SSG1, and the other containing a 3D NAND memory string having SSG2 and SSG3. In accordance with the scope of this disclosure, in several implementations, the array of 3D memory strings is divided into sets 406 and fingers 408 by DSG cuts 402 and SSG cuts 404, respectively, in program operation, with each set 406 being a basic unit of program operation for implementing a program operation scheme such as a 3 or 4-bit line (3BL or 4BL) biased program.

[0050] It is understood that the DSG cut 402 may be implemented as a physical cut that replaces a portion of the DSG line with a dielectric layer (e.g., the DSG cut 210 shown in Figure 2), or as an electrical cut that pre-programs (also known as trimming) different DSG transistors to different threshold voltage levels. Similarly, it is understood that the SSG cut 404 may be implemented as a physical cut that replaces a portion of the SSG line with a dielectric layer (e.g., the SSG cut 212 shown in Figure 2), or as an electrical cut that pre-programs (also known as trimming) different SSG transistors to different threshold voltage levels. It is also understood that the spacing between adjacent DSG cuts 402 or SSG cuts 404 (i.e., the number of 3D NAND memory strings in each set 406 or each finger 408) may differ in different examples.

[0051] In addition to the page buffer / sense amplifier 304 that provides corresponding data to each selected memory cell 106 in order to execute the program operation, the row decoder / word line driver 308 may be configured to apply a program voltage and a verification voltage to the selected word line 118 coupled to the selected row of the memory cell 106 in one or more program / verification cycles in order to raise the threshold voltage of each selected memory cell 106 to a desired level (to a desired range of threshold voltages) based on the corresponding data. For example, Figures 5A and 5B show waveforms of word line voltages applied to the selected word line in a program operation according to some aspects of the present disclosure.

[0052] As shown in Figures 5A and 5B, the program operation, according to several implementations, includes one or more loops 502, each containing a program cycle 504 and a verification cycle 506. As shown in Figure 5B, in each loop 502, the row decoder / word line driver 308 can be configured to apply a program voltage (Vpgm) on the selection word line 118 to select a row of memory cell 106 in the program cycle 504, and to sequentially apply one or more verification voltages (Vvfy) with incremental changes in voltage level to verify the selected row of memory cell 106 in the verification cycle 506. That is, in each loop 502, the peripheral circuit 102 can perform verification of the selected row of memory cell 106 at one or more levels in the verification cycle 506 after applying the program voltage in the program cycle 504. According to several implementations, the number of verification voltages applied in the verification cycle 506 depends on the level programmed by a particular loop 502. As a result, at the end of the program operation, for example, the selected memory cell 106 is 2 N It may be programmed at one of the individual levels, where N is a positive integer.

[0053] In some implementations, the program operation is an incremental step pulse program (ISPP) that gradually increases the program voltage on a step voltage basis within different loops 502. The magnitude of this “step” (e.g., the increase in the magnitude of the program voltage in each loop 502 relative to the program voltage in the immediately preceding loop 502) is known as the “pulse step height”. In accordance with the scope of this disclosure, in some implementations, the program operation includes at least a first loop 502 and a second loop 502 following the first loop 502, where the first loop 502 and the second loop 502 are the start and end loops of the ISPP, respectively.

[0054] Figure 6A shows a timing diagram of the program operation. The program operation may be an ISPP comprising multiple loops, each containing a program cycle (PGM) and a verification cycle (VFY), as previously described in Figures 5A and 5B. Each verification cycle may include a verification period (phase) in which one or more verification voltage pulses are applied to the selected word line (sel WL) to verify the selected memory cells coupled to the selected word line at one or more levels. As shown in Figure 6, each verification cycle includes a pre-pulse phase before the verification period in which the NAND memory string prepares for verification, and / or further includes a post-pulse phase (also known as a recovery period) immediately after the verification period in which the NAND memory string recovers from verification and prepares for another operation (e.g., a read operation) after the termination loop or prepares for the program in the next loop after any non-terminating loop.

[0055] As shown in Figure 6A, for each selected NAND memory string, a selection voltage (e.g., a positive voltage) may be applied to each selected DSG line (sel DSG) and selected SSG line (sel SSG) to verify the selected memory cells of each selected NAND memory string during the verification period, and each selected DSG transistor and selected SSG transistor may be turned ON during the verification period of each loop (e.g., T4 to T5). In contrast, for each unselected NAND memory string, a non-selection voltage (e.g., a ground voltage) may be applied to each unselected DSG line (unsel DSG) and unselected SSG line (unsel SSG) to prevent verification of the unselected memory cells of each unselected NAND memory string during the verification period, and each unselected DSG transistor and unselected SSG transistor may be turned OFF during the verification period of each loop (e.g., T4 to T5). Furthermore, at T3, a path voltage (e.g., a positive voltage) may be applied to each unselected word line (unsel WL).

[0056] On the other hand, the channel potential of the unselected NAND memory string is up-coupled to a positive potential during the pre-pulse phase, which can cause HCI in the channel between the DSG transistor and the SSG transistor. Therefore, as shown in Figure 6A, during the pre-pulse phase of each loop, a selection voltage may be applied to each unselected DSG line and unselected SSG line at T3 to turn on each unselected DSG transistor and unselected SSG transistor in order to lower the channel potential and eliminate HCI before the verification period, also known as "pre-pulse channel cleaning". Similarly, the channel potential of the unselected NAND memory string is down-coupled to a negative potential during the post-pulse phase, which can also cause HCI in the channel between the DSG transistor and the SSG transistor. Therefore, as shown in Figure 6A, during the post-pulse phase of each loop, a selection voltage may be applied to each unselected DSG line and unselected SSG line at T5 to turn on each unselected DSG transistor and unselected SSG transistor again in order to increase the channel potential and eliminate HCI before the next operation, also known as "post-pulse channel cleaning". However, the pre-pulse channel cleaning and post-pulse channel cleaning performed in each loop extend the duration of each verification cycle, which becomes a bottleneck in saving programming time.

[0057] In some implementations, different strings may have different levels of HCI effect by using SSG cuts (e.g., 212 in Figure 2, 404 in Figures 4A-4C) and DSG cuts (e.g., 210 in Figure 2, 402 in Figures 4A-4C). Figure 7A shows a schematic diagram of the state of memory cells in a memory string during program operation according to some aspects of the present disclosure. As shown in one exemplary example in Figure 7A, there are six strings Str0, Str1, Str2, Str3, Str4, and Str5 connected to the same bit line. The DSG transistors of the six strings Str0, Str1, Str2, Str3, Str4, and Str5 are isolated from each other by DSG cuts between adjacent DSG transistors. The six strings also belong to three fingers due to SSG cuts between the SSG transistors of Str1 and Str2, and between the SSG transistors of Str3 and Str4. Assume that in each finger, memory cells in even-numbered strings are programmed first, followed by memory cells in odd-numbered strings. In such a case, when memory cells in Str2 are programmed first, the unselected Str3 (e.g., erase state) in the same finger may have a low level of HCl effect while verifying the memory cells in Str2. However, if memory cells in Str3 in the same finger are programmed after the memory cells in Str2 are programmed, the unselected Str2 (e.g., programmed state) in the same finger may have a high level of HCl effect while verifying the memory cells in Str3. Therefore, this disclosure provides a separated channel cleaning scheme for different memory strings having different channel potentials starting from a pre-pulse phase during verification.

[0058] Therefore, in some implementations, pre-pulse channel cleaning and / or post-pulse channel cleaning can be skipped without significantly affecting the channel potential of certain unselected strings, particularly when SSG cuts are performed to separate 3D NAND memory strings into fingers. Figures 7B-7D are schematic diagrams of various voltages applied to memory strings during program operation according to some aspects of the present disclosure.

[0059] In the first scenario, when verifying the memory cell of Str2 (which was initially programmed within the finger) without applying a pre-pulse channel cleaning operation, the DSG and SSG transistors of Str0 and Str1, which are in different fingers from Str2, are closed relative to Str2, as shown in Figure 7B. That is, the memory cells coupled to the selected word lines in Str0 and Str1 are programmed and can be in a programmed state, while the memory cells coupled to the selected word lines in Str4 and Str5 are not programmed and are in an erased state, and the channels of Str0, Str1, Str4, and Str5 are floating. Therefore, the HCI effect in Str0, Str1, Str4, and Str5 is at a low level due to the boost-up channel potential. Furthermore, as shown in Figure 7C, when verifying the memory cell of Str2 without applying a pre-pulse channel cleaning operation, Str3, which is in the same finger as Str2, closes its DSG transistor and opens its SSG transistor. Since the memory cell coupled to the selected word line of Str3 is in an erased state, the channel potential of Str3 is flat at a high voltage level, thereby maintaining the low level HCI effect of Str3.

[0060] In the second scenario, when verifying the memory cells of Str3 (which are later programmed within the finger) without applying a pre-pulse channel cleaning operation, the DSG and SSG transistors of Str0 and Str1, which are in different fingers than Str2, are closed, as shown in Figure 7B. That is, the memory cells coupled to the selected word line in Str0 and Str1 are programmed and can be in a programmed state, while the memory cells coupled to the selected word line in Str4 and Str5 are in an erased state, and the channels of Str0, Str1, Str4, and Str5 are floating. Therefore, the HCI effect in Str0, Str1, Str4, and Str5 remains at a low level due to the boost-up channel potential. Furthermore, as shown in Figure 7D, when verifying the memory cells of Str3 without applying a pre-pulse channel cleaning operation, Str2, which is in the same finger as Str2, closes its DSG transistor and opens its SSG transistor. However, since the memory cells coupled to the selected word line in Str2 are in a programmed state, the channel potential above Str2 above the programmed memory cells rises further to a higher voltage level, thereby causing a high-level HCl effect in Str2.

[0061] In some implementations, each finger includes two strings, i.e., an even memory string and an odd memory string, and when the first memory cell of the even memory string is programmed first, the prepulse phase can be omitted during the verification cycle of the first memory cell, while the second memory cell of the odd memory string is programmed after the first memory cell, and the prepulse phase is not omitted during the verification cycle of the second memory cell. In some other implementations, each finger includes three or more strings, i.e., a first string, a second string, a third string, etc., and when the first memory cell of the first string in the finger is programmed first, the prepulse phase can be omitted during the verification cycle of the first memory cell, while the second memory cell of another memory string (i.e., a second string, a third string, etc.) is programmed after the first memory cell, and the prepulse phase is not omitted during the verification cycle of the second memory cell. Thus, according to some aspects of this disclosure, channel cleaning in the prepulse phase (and / or postpulse phase) of the verification cycle can be skipped. For example, in some implementations, when initially programming the memory cells of the first selection string with a finger, the memory cells can be verified without applying a pre-pulse phase. In some other implementations, when initially programming the memory cells of the memory strings within a finger, the memory cells can be verified without applying both a pre-pulse phase and a post-pulse phase.

[0062] As shown in Figure 6B, both the pre-pulse and post-pulse phases are omitted in the verification cycle. Specifically, the word line driver 308 of the peripheral circuit 102 can be configured to apply a selection voltage (e.g., a positive voltage) to the selected SSG line (sel SSG), thereby turning on the selected SSG transistor in the selected NAND memory string coupled to the selected SSG line at T3. Similarly, the word line driver 308 of the peripheral circuit 102 can be configured to apply a selection voltage (e.g., a positive voltage) to the selected DSG line (sel DSG), thereby turning on the selected DSG transistor in the selected NAND memory string coupled to the selected DSG line at T3. Furthermore, the word line driver 308 of the peripheral circuit 102 can be configured to apply a pass voltage (e.g., a positive voltage) to the unselected word line (sel WL) at T3.

[0063] Note that the selection voltage applied to the selected DSG line may be the same as or different from the selection voltage applied to the selected SSG line, and the pass voltage applied to the unselected word line may be the same as or different from the selection voltage applied to the selected SSG line and / or selected DSG line. Figure 6B shows that providing the selection voltage to the selected SSG line and selected DSG line, and providing the pass voltage to the unselected word line, occur at the same start time T3 and end time T6, but further consideration should be given. However, in actual implementation, the start time and / or end time for supplying the selection voltage to the selected SSG line and selected DSG line, and the start time and / or end time for supplying the pass voltage to the unselected word line may be different.

[0064] Furthermore, as shown in Figure 6B, the period during which the unselected word line reaches the pass voltage from T3 in the verification cycle is shorter than the period during which the unselected word line reaches the pass voltage from T3 in the prepulse phase, as shown in Figure 6A. Similarly, as shown in Figure 6B, the period during which the selected word line reaches the verification voltage from T4 in the verification cycle is shorter than the period during which the selected word line reaches the verification voltage from T4 in the verification cycle, as shown in Figure 6A. Note that Figure 6B shows that the starting point T4 for applying the verification voltage to select the word line is after time T3, but in several other implementations not shown in the figure, T3 and T4 may be at the same time.

[0065] In some implementations, the word line driver 308 of the peripheral circuit 102 can be configured to apply a non-selective voltage (e.g., ground voltage) to the unselected SSG lines (unsel SSG) and unselected SSG transistors in the unselected NAND memory string to turn off the unselected SSG transistors during the verification cycle. Similarly, the word line driver 308 of the peripheral circuit 102 can be configured to apply a non-selective voltage (e.g., ground voltage) to the unselected DSG lines (unsel DSG) and unselected DSG transistors in the unselected NAND memory string to turn off the unselected DSG transistors during the verification cycle. In other words, both pre-pulse channel cleaning and post-pulse channel cleaning can be skipped with respect to the unselected NAND memory string (e.g., having unselected SSG transistors and unselected DSG transistors), thereby saving programming time.

[0066] As shown in Figure 6C, in the verification cycle, the post-pulse phase is maintained while only the pre-pulse phase is omitted. Specifically, the word line driver 308 of the peripheral circuit 102 can be configured to apply a selection voltage (e.g., a positive voltage) to the selected SSG line (sel SSG) and selected SSG transistor in the selected NAND memory string to turn on the selected SSG transistor at T3. Similarly, the word line driver 308 of the peripheral circuit 102 can be configured to apply a selection voltage (e.g., a positive voltage) to the selected DSG line (sel DSG) and selected DSG transistor in the selected NAND memory string to turn on the selected DSG transistor at T3. Furthermore, the word line driver 308 of the peripheral circuit 102 can be configured to apply a pass voltage (e.g., a positive voltage) to the unselected word line (sel WL) at T3. Note that, as shown in Figure 6C, the time it takes for the unselected word line to reach the pass voltage from T3 in the verification cycle is shorter than the time it takes for the unselected word line to reach the pass voltage from T3 in the pre-pulse phase, as shown in Figure 6A.

[0067] In some implementations, the word line driver 308 of the peripheral circuit 102 can be configured to apply a non-selection voltage (e.g., ground voltage) to the unselected SSG lines (unsel SSG) and unselected SSG transistors in the unselected NAND memory string to turn off the unselected SSG transistors from T3 to T5 during the verification cycle, and then apply a selection voltage (e.g., positive voltage) to each unselected SSG to turn on each unselected SSG transistor in the post-pulse stage at T5. Similarly, the word line driver 308 of the peripheral circuit 102 can be configured to apply a non-selection voltage (e.g., ground voltage) to the unselected DSG lines (unsel DSG) and unselected DSG transistors in the unselected NAND memory string to turn off the unselected DSG transistors from T3 to T5 during the verification cycle, and then apply a selection voltage (e.g., positive voltage) to each unselected DSG to turn on each unselected DSG transistor in the post-pulse stage at T5. In other words, only pre-pulse channel cleaning is skipped, while post-pulse channel cleaning is maintained for unselected NAND memory strings (e.g., those with unselected SSG transistors and unselected DSG transistors), thereby saving program time.

[0068] Figure 8 shows a flowchart of a method 800 for operating a memory device according to several aspects of the present disclosure. The memory device may be any suitable memory device disclosed herein, such as memory device 100. The memory device may comprise a memory string, each comprising a drain-selection gate (DSG) transistor, a memory cell, and a source-selection gate (SSG) transistor. Method 800 can be implemented by peripheral circuits 102, such as a row decoder / word line driver 308, a page buffer / sense amplifier 304, and control logic 312. The steps shown in Method 800 are not exhaustive, and it should be understood that other steps may be performed before, after, or between any of the illustrated steps. Furthermore, some of the steps may be performed simultaneously or in an order different from that shown in Figure 8.

[0069] Referring to Figure 8, method 800 begins with step 802 in which the first memory cell of the first memory string in a subset of memory strings is initially programmed. The SSG transistors of the subset of memory strings are coupled to each other, and the voltage applied to the SSG transistors of the subset of memory strings may be the same. For example, as shown in Figure 7A, the first memory string may be Str2, and the subset of memory strings may contain Str2 and Str3 in the same finger, and the first memory cell is the memory cell in Str2 coupled to the selected word line. The programming process can be described in relation to the above explanation in connection with Figures 5A-5B and 6A-6C.

[0070] Method 800 proceeds to step 804, as shown in Figure 8, where the first memory cell can be verified without applying a prepulse step to the first memory cell. For example, as shown in Figures 6B and 6C, the prepulse step can be omitted in the verification process. Specifically, verifying the first memory cell may include turning on the SSG transistors of a subset of memory strings and the DSG transistors of the first memory string, keeping the SSG transistors of memory strings other than the subset of memory strings off during the verification of the first memory cell, and keeping the DSG transistors of memory strings other than the first memory string off during the verification of the first memory cell. In some implementations, verifying the first memory cell may further include applying a pass voltage to the unselected word lines during the verification of the first memory cell, and applying a verification voltage to the selected word lines during the verification of the first memory cell after the unselected word lines have reached the pass voltage.

[0071] Method 800 proceeds to step 806, as shown in Figure 8, where the second memory cell of the second memory string in the subset can be programmed after the first memory cell has been programmed. For example, as shown in Figure 7A, the second memory string may be Str3, and the subset of memory strings may contain Str2 and Str3 in the same finger, with the second memory cell being the memory cell in Str3 coupled to the selected word line. The programming process can be described in relation to the explanation above in connection with Figures 5A-5B and 6A-6C.

[0072] Method 800 proceeds to step 808, as shown in Figure 8, where the second memory cell can be verified, including applying a pre-pulse phase to the second memory cell. For example, as shown in Figure 6A, the verification process may include a pre-pulse phase and a post-pulse phase. Specifically, verifying the second memory cell may include applying a pass voltage to the unselected word line during the verification of the first memory cell, and applying a verification voltage to the selected word line during the verification of the first memory cell after the unselected word line has reached the pass voltage. In some implementations, verifying the second memory cell may further include turning on the SSG transistors of a subset of memory strings and the DSG transistors of the second memory string, turning on the SSG transistors of memory strings other than the subset of memory strings during the pre-pulse phase verifying the second memory cell, and turning on the DSG transistors of memory strings other than the second memory string during the pre-pulse phase verifying the second memory cell.

[0073] In some implementations, verifying a second memory cell may further include applying a pass voltage to the unselected word line during a pre-pulse phase for verifying the second memory cell, and applying a verification voltage to the selected word line during verification of the second memory cell after the pre-pulse phase. In some implementations, a first period during verification of the first memory cell in which the unselected word line reaches the pass voltage is shorter than a second period during verification of the second memory cell in which the unselected word line reaches the pass voltage. In some implementations, a first time interval between turning on the DSG transistor of the first memory string and applying the first verification voltage to the selected word line is shorter than a second time interval between turning on the DSG transistor of the second memory string and applying the first verification voltage to the selected word line.

[0074] Figure 9 shows a block diagram of a system 900 having a memory device according to several aspects of the present disclosure. System 900 may be a mobile phone, desktop computer, laptop computer, tablet, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, argument reality (AR) device, or any other suitable electronic device having internal storage. As shown in Figure 9, system 900 may include a host 908 and a memory system 902 having one or more memory devices 100 (shown in Figure 1) and a memory controller 906. The host 908 may be a processor of an electronic device such as a central processing unit (CPU), or a system-on-a-chip (SoC) such as an application processor (AP). The host 908 may be configured to send and receive data to and from the memory device 100.

[0075] The memory device 100 can be any memory device disclosed herein. The memory controller 906, according to several implementations, is coupled to the memory device 100 and the host 908 and configured to control the memory device 100. The memory controller 906 can manage data stored in the memory device 100 and communicate with the host 908. In several implementations, the memory controller 906 is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, CompactFlash® (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones. In several implementations, the memory controller 906 is designed to operate in high-duty-cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage in mobile devices such as smartphones, tablets, and laptop computers, and in enterprise storage arrays. The memory controller 906 may be configured to control operations of the memory device 100, such as read operations, erase operations, and program operations. The memory controller 906 can also be configured to manage various functions related to data stored in or to be stored in the memory device 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some implementations, the memory controller 906 is further configured to process error correction codes (ECC) with respect to data read from or written to the memory device 100. Any other appropriate functions, such as formatting the memory device 100, can also be performed by the memory controller 906. The memory controller 906 can communicate with an external device (e.g., host 908) according to a specific communication protocol.For example, the memory controller 906 may communicate with an external device via at least one of various interface protocols, such as the USB protocol, MMC protocol, Peripheral Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Extended Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, or Firewire protocol.

[0076] The memory controller 906 and one or more memory devices 100 can be incorporated into various types of storage devices contained in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 902 can be implemented and packaged in different types of final electronic products. In one example shown in Figure 10A, the memory controller 906 and a single memory device 100 may be incorporated into a memory card 912. The memory card 912 can include PC cards (PCMCIA, personal computer memory card international association), CF cards, SmartMedia (SM) cards, Memory Sticks, Multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 912 may further include a memory card connector 914 that connects the memory card 912 to a host (e.g., host 908 in Figure 10). In another example shown in Figure 10B, the memory controller 906 and multiple memory devices 100 may be incorporated into an SSD 916. The SSD916 may further include an SSD connector 918 that connects the SSD916 to a host (for example, the host 908 in Figure 9). In some implementations, the storage capacity and / or operating speed of the SSD916 is greater than the storage capacity and / or operating speed of the memory card 912.

[0077] The foregoing descriptions of specific implementations may be readily modified and / or adapted for various applications. Such adaptations and modifications are therefore intended to be within the meaning and scope of the equivalents of the disclosed implementations, based on the teachings and guidance presented herein.

[0078] The breadth and scope of this disclosure should not be limited by any of the typical implementations described above, but should be defined solely by the following claims and their equivalents.

[0079] While specific configurations and arrangements are described, it should be understood that these are for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, the subject matter described in this disclosure may be used for a variety of other applications. The functional and structural features described in this disclosure may be combined, adjusted, modified, and rearranged in a manner consistent with the scope of this disclosure.

Claims

1. A method for operating a memory device, wherein the memory device comprises a memory string each having a drain-selection gate (DSG) transistor, a memory cell, and a source-selection gate (SSG) transistor, and the method is Programming the first memory cell of a first memory string in a subset of memory strings, wherein the SSG transistors of the subset of memory strings are coupled to each other. Verifying the first memory cell without applying a prepulse step to the first memory cell, Programming the first memory cell and then programming the second memory cell of the second memory string in the subset, Verifying the second memory cell, including applying the prepulse step to the second memory cell. Methods that include...

2. After programming the first memory string, the third memory cell of the third memory string in the subset is programmed, Verifying the third memory cell, including applying the aforementioned prepulse step to the third memory cell. The method according to claim 1, further comprising:

3. Verifying the first memory cell is Turning on the SSG transistor of the subset of the memory string and the DSG transistor of the first memory string, During the verification of the first memory cell, the SSG transistors of the memory strings other than the subset of the memory strings are kept off, During the verification of the first memory cell, the DSG transistors of the memory strings other than the first memory string are kept off, Applying a path voltage to the unselected word line during verification of the first memory cell, After the non-selected word line reaches the path voltage, a verification voltage is applied to the selected word line during verification of the first memory cell. The method according to claim 1, further comprising:

4. Verifying the second memory cell is Turning on the SSG transistor of the subset of the memory string and the DSG transistor of the second memory string, In the prepulse stage of verifying the second memory cell, the SSG transistors of the memory strings other than the subset of the memory strings are turned on, In the prepulse step of verifying the second memory cell, the DSG transistors of the memory strings other than the second memory string are turned on, In the prepulse stage of verifying the second memory cell, the path voltage is applied to the unselected word line, After the prepulse stage, a verification voltage is applied to the selected word line during the verification of the second memory cell. The method according to claim 3, further comprising:

5. The first period during the verification of the first memory cell in which the unselected word line reaches the pass voltage is shorter than the second period during the verification of the second memory cell in which the unselected word line reaches the pass voltage. The method according to claim 4.

6. Apply the same voltage to the SSG transistors of the subset of memory strings that are coupled together. The method according to claim 1, further comprising:

7. The first memory cell and the second memory cell are coupled to the same word line. The method according to claim 1.

8. The first time interval between turning on the DSG transistor of the first memory string and applying the first verification voltage to the selected word line is shorter than the second time interval between turning on the DSG transistor of the second memory string and applying the first verification voltage to the selected word line. The method according to claim 4.

9. A method for operating a memory device, Applying a first voltage to the first DSG transistor in the first memory string during the first verification operation of the first memory cell in the first memory string, During the first verification operation, before applying the verification voltage to the word line coupled to the first memory cell, a second voltage lower than the first voltage is applied to the second DSG transistor in the second memory string, Applying the first voltage to the second DSG transistor in the second memory string during the prepulse phase of the second verification operation of the second memory cell in the second memory string that is coupled to the word line, During the prepulse stage, a third voltage higher than the second voltage is applied to the first DSG transistor in the first memory string. Includes, The first SSG transistor of the first memory string and the second SSG transistor of the second memory string are coupled to each other, and the first verification operation precedes the second verification operation. method.

10. The second voltage turns off the second DSG transistor. The third voltage opens the first DSG transistor. The method according to claim 9.

11. A memory device, A memory string, each comprising a drain-selection gate (DSG) transistor, a memory cell, and a source-selection gate (SSG) transistor, A peripheral circuit connected to the memory string, The first memory cell of the first memory string in the subset of the memory string is programmed, and the SSG transistors of the subset of the memory string are coupled to each other. The first memory cell is verified without applying a prepulse stage to the first memory cell. After programming the first memory cell, the second memory cell of the second memory string in the subset is programmed. The second memory cell is verified, including applying the prepulse step to the second memory cell. The peripheral circuit is configured in such a way as A memory device comprising the above features.

12. A DSG cut structure for isolating the DSG transistors of the memory string from each other, An SSG cut structure for separating the aforementioned memory string into a subset of memory strings, Furthermore, The DSG transistors of the memory string in each subset are electrically coupled to one another, and the DSG transistors of the memory string in different subsets are isolated by the SSG cut structure. The memory device according to claim 11.

13. The aforementioned peripheral circuitry is After programming the first memory cell, the third memory cell in the third memory string in the subset is programmed. The third memory cell is verified, including applying the prepulse step to the third memory cell. The memory device according to claim 12, further configured as follows.

14. The aforementioned peripheral circuitry is The SSG transistors of the subset of the memory string and the DSG transistors of the first memory string are turned on. During the verification of the first memory cell, the SSG transistors of the memory strings other than the subset of the memory strings are kept off. During the verification of the first memory cell, the DSG transistors of the memory strings other than the first memory string are kept off. During verification of the first memory cell, a path voltage is applied to the unselected word line. After the non-selected word line reaches the path voltage, a verification voltage is applied to the selected word line during verification of the first memory cell. The memory device according to claim 11, further configured as follows.

15. The aforementioned peripheral circuitry is The SSG transistors of the subset of the memory string and the DSG transistors of the second memory string are turned on. During the prepulse phase of verifying the second memory cell, the SSG transistors of the memory strings other than the subset of the memory strings are turned on and off. During the prepulse phase of verifying the second memory cell, the DSG transistors of the memory strings other than the second memory string are turned on and off. In the prepulse stage of verifying the second memory cell, the path voltage is applied to the unselected word line. After the prepulse stage, a verification voltage is applied to the selected word line during the verification of the second memory cell. The memory device according to claim 14, further configured as follows.

16. The first period during the verification of the first memory cell in which the unselected word line reaches the pass voltage is shorter than the second period during the verification of the second memory cell in which the unselected word line reaches the pass voltage. The memory device according to claim 15.

17. The aforementioned peripheral circuitry is Apply the same voltage to the SSG transistors of the subset of memory strings that are coupled to each other. The memory device according to claim 11, further configured as follows.

18. The first memory cell and the second memory cell are coupled to the same word line. The memory device according to claim 11.

19. The first time interval between turning on the DSG transistor of the first memory string and applying the first verification voltage to the selected word line is shorter than the second time interval between turning on the DSG transistor of the second memory string and applying the first verification voltage to the selected word line. The memory device according to claim 16.

20. The SSG cut structure is either a physical cut structure or an electrical cut structure. The memory device according to claim 12.

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