Substrates and semiconductor packages for semiconductor equipment

Abstract

To provide a substrate for semiconductor devices that is well adapted to miniaturization. [Solution] The substrate for semiconductor equipment comprises a first wiring layer 31 formed on a virtual plane with grid pattern wires 31a, and defining the current path pc by breaks 72a and 72b of the wires 31a; an insulating film laminated on the first wiring layer 31; and a second wiring layer 33 laminated on the insulating film and formed on a grid pattern second wires 33a that overlap the grid pattern, and defining the current path by breaks in the second wires. The grid pattern wires are spread across the virtual plane, and similarly the grid pattern second wires are spread across the surface of the insulating film. Since the grid patterns overlap, in the exposure apparatus, the optical path length of the irradiated light is kept constant when drawing the second wires, and exposure is achieved with good accuracy. The accuracy of the second wiring layer is improved, and miniaturization of the second wiring layer is realized.

Description

Technical Field

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[0001] The present invention relates to a substrate for a semiconductor device including a wiring layer that defines a current path.

Background Art

[0002] Patent Document 1 discloses a semiconductor package including a wiring layer contained in a multilayer film. In forming the multilayer film, the wiring layer includes conductive wires following a designed pattern. When an insulating film is laminated on the wiring layer, undulations following the designed pattern are established on the surface of the insulating film.

Prior Art Document

[0008] A substrate for a semiconductor device may include a second wiring layer laminated on the insulating film, formed by second wires of a grid pattern that overlaps the grid pattern, and which defines the current path by the break of the second wires. The grid pattern wires are spread across a virtual plane. Similarly, the second wires of the grid pattern are spread across the surface of the insulating film. Since the grid patterns overlap, the optical path length of the irradiated light is kept constant when drawing the second wires in the exposure apparatus. Exposure is achieved with good accuracy. The accuracy of the second wiring layer is improved. Miniaturization of the second wiring layer is achieved.

[0009] A substrate for semiconductor devices may include vias formed in the insulating film that connect the intersection of the first conductor and the intersection of the second conductor. Even if the vias are misaligned in the in-plane direction, good connectivity between the vias and the first conductor, and between the vias and the second conductor, is ensured at the intersections of the first and second conductors. The effect of via misalignment is minimized. The yield of the substrate for semiconductor devices can be increased.

[0010] The insulating film and the second wiring layer may be repeatedly laminated on the second wiring layer. A multilayer film with a build-up structure including the wiring layer, insulating film, and second wiring layer is formed on the surface of the core substrate. The grid patterns of all second wiring layers overlap the grid patterns of the wiring layers. In the exposure apparatus, the optical path length of the irradiated light is kept constant when drawing the second wire. The precision of all second wiring layers is improved. Miniaturization of the second wiring layers is achieved.

[0011] The wiring layer may be laminated on the surface of a core substrate formed from glass. The substrate for semiconductor equipment constitutes a package substrate.

[0012] The wiring layer may be laminated on the surface of a core substrate formed from silicon. The substrate for semiconductor devices constitutes an interposer.

[0013] According to a second embodiment of the present invention, a semiconductor package is provided comprising: a wiring layer formed on a virtual plane by wires in a grid pattern, wherein the breaks of the wires define the current path; an insulating film laminated on the wiring layer; and a semiconductor chip supported on the insulating film and connected to the path.

[0014] When an insulating film is laminated onto the wiring layer, ridges resembling the wires are established on the surface of the insulating film. When exposure is performed in accordance with the grid pattern using an exposure apparatus, the optical path length of the irradiated light is kept constant, resulting in exposure with good accuracy. The accuracy of the drawing is improved. Semiconductor packages are adapted to miniaturization.

[0015] A substrate for a semiconductor device is provided, comprising a core substrate, a first wiring layer formed on the front side of the core substrate with first conductors of a first grid pattern, the path of current defined by the break of the first conductors, a first insulating film laminated on the first wiring layer, a second wiring layer formed on the back side of the core substrate with second conductors of a second grid pattern following the first grid pattern, the path of current defined by the break of the second conductors, and a second insulating film laminated on the second wiring layer.

[0016] A symmetrical structure can be established on the front and back surfaces of the core substrate with respect to the core substrate. The front and back surfaces of the core substrate can have at least the same thermal expansion amounts in the in-plane direction. Warping of the substrate for semiconductor devices can be suppressed by establishing this symmetrical structure. [Effects of the Invention]

[0017] As described above, according to the form of disclosure, a substrate for semiconductor devices that can be well adapted to miniaturization is provided. [Brief explanation of the drawing]

[0018] [Figure 1]It is a conceptual diagram schematically showing the configuration of an implementation substrate according to an embodiment of the present invention. [Figure 2] It is a cross-sectional view schematically showing the configuration of a package substrate according to a specific example. [Figure 3] It is a partially enlarged plan view schematically showing the configuration of a wiring layer. [Figure 4] It is a conceptual diagram schematically showing the mechanism of exposure used in the manufacture of a multilayer film. [Figure 5] It is a conceptual diagram schematically showing a photoresist on a core substrate. [Figure 6] It is a conceptual diagram schematically showing the formed first wiring layer. [Figure 7] It is a conceptual diagram schematically showing a first insulating film covering the first wiring layer. [Figure 8] It is a conceptual diagram schematically showing a through-hole formed in the first insulating film. [Figure 9] It is a conceptual diagram schematically showing the mechanism of exposure performed on the first insulating film. [Figure 10] It is a conceptual diagram schematically showing a photoresist on the first insulating film. [Figure 11] It is a conceptual diagram schematically showing the formed second wiring layer. [Figure 12] It is a conceptual diagram schematically showing a second insulating film covering the second wiring layer. [Figure 13] It is a conceptual diagram schematically showing the formed multilayer film. [Figure 14] It is a conceptual diagram schematically showing the mechanism of exposure used in the manufacture of a multilayer film. [Figure 15] It is a conceptual diagram schematically showing the mechanism of exposure performed on the first insulating film. [Figure 16] It is a cross-sectional view schematically showing the configuration of a package substrate according to another specific example.

Embodiments for Carrying Out the Invention

[0019] Hereinafter, embodiments of the present invention will be described while referring to the accompanying drawings.

[0020] Figure 1 schematically shows the configuration of a mounting substrate 11 according to an embodiment of the present invention. The mounting substrate 11 comprises a printed circuit board (bare board) 12 and one or more semiconductor packages 13 mounted on the printed circuit board 12. The semiconductor packages 13 are connected to conductive pads of the printed circuit board 12 by solder balls 14 with a BGA (Ball Grid Array) structure. The semiconductor packages exchange electrical signals with the printed circuit board 12 through the action of the solder balls 14.

[0021] The semiconductor package 13 comprises a package substrate 15, one or more interposers 16 stacked on the package substrate 15, and one or more semiconductor chips 17 mounted on the interposers 16. The package substrate 15 has, for example, a core substrate 21 and multilayer films 22, 23 stacked in build-up on the front and back surfaces of the core substrate 21. The core substrate 21 may be formed from, for example, glass. A resin material may be used instead of glass. C4 bumps 24 are received on the surface of the package substrate 15. The C4 bumps 24 are formed from, for example, solder material. The C4 bumps 24 may include copper pillars. The C4 bumps 24 are formed to be smaller in diameter than the solder balls 14.

[0022] The interposer 16 includes, for example, a core substrate 26 and a multilayer film 27 that is built up on the surface of the core substrate 27. The core substrate 26 may be formed from, for example, silicon. Microbumps 28 are received on the surface of the interposer 16. The microbumps 28 are formed from, for example, copper. The microbumps 28 are formed to be smaller in diameter than the C4 bumps 24. The semiconductor chips 17 are bonded to the interposer 16 by the action of the microbumps 28. The semiconductor chips 17 may include a CPU (Central Processing Unit) chip, a GPU (Graphical Processing Unit) chip, other logic chips, and memory chips (DRAM or HBM).

[0023] As shown in Figure 2, the multilayer film 22 on the front side comprises a first wiring layer 31 formed on the surface of the core substrate 21 with conductive wires 31a, and a first insulating film 32 laminated on the first wiring layer 31. The conductive wires 31a may be made of a conductive plating film such as copper. The first insulating film 32 covers the conductive wires 31a. The first insulating film 32 may be formed from epoxy resin. Polyimide resin or other insulating materials may be used for the first insulating film 32.

[0024] A second wiring layer 33 is laminated onto the first insulating film 32. The second wiring layer 33 is formed on the surface of the first insulating film 32 with a conductive wire 33a. The conductive wire 33a may be made of a conductive plated film, such as copper. A second insulating film 34 is laminated onto the second wiring layer 33. The second insulating film 34 covers the conductive wire 33a. The second insulating film 34 may be made of epoxy resin. Polyimide resin or other insulating materials may be used for the second insulating film 34.

[0025] The second insulating film 34 is laminated in the order of a third wiring layer 35, a third insulating film 36, a fourth wiring layer 37, and a fourth insulating film 38. The third wiring layer 35 and the fourth wiring layer 37 are formed on the surfaces of the second insulating film 34 and the third insulating film 36 with conductive wires 35a and 37a, respectively. The conductive wires 35a and 37a may be made of a conductive plating film, such as copper. The wiring layers and insulating films can be repeatedly laminated in the same manner.

[0026] Vias 41 are formed in the first insulating film 32 to electrically connect the conductor 33a of the second wiring layer 33 to the conductor 31a of the first wiring layer 31. The vias 41 may be made of a conductive plating film such as copper. Similarly, vias 42 and 43 are formed in the individual insulating films 34 and 36 to electrically connect the upper wiring layers 35 and 37 to the lower wiring layers 33 and 35. The vias 42 and 43 ensure current flow between the upper and lower conductors 33a, 35a, and 37a.

[0027] Conductive pads 45 are placed on the surface of the uppermost layer. C4 bumps 24 of the interposer 16 are bonded to each conductive pad 45. Vias 46 are formed in the fourth insulating film 38 to electrically connect the conductive pads 45 to the conductors 37a of the fourth wiring layer 37. The vias 46 may be made of a conductive plating film, such as copper.

[0028] The multilayer film 23 on the back side comprises a first wiring layer 51 formed on the back surface of the core substrate 21 with conductive wires 51a, and a first insulating film 52 laminated on the first wiring layer 51. The conductive wires 51a may be made of a conductive plated film such as copper. The first insulating film 52 covers the conductive wires 51a. The first insulating film 52 may be formed from epoxy resin. Polyimide resin or other insulating materials may be used for the first insulating film 52.

[0029] A second wiring layer 53 is laminated on the first insulating film 52. The second wiring layer 53 is formed on the surface of the first insulating film 52 with a conductive wire 53a. The conductive wire 53a may be made of a conductive plated film, such as copper. A second insulating film 54 is laminated on the second wiring layer 53. The second insulating film 54 covers the conductive wire 53a. The second insulating film 54 may be made of epoxy resin. Polyimide resin or other insulating materials may be used for the second insulating film 54.

[0030] The second insulating film 54 is laminated in the order of a third wiring layer 55, a third insulating film 56, a fourth wiring layer 57, and a fourth insulating film 58. The third wiring layer 55 and the fourth wiring layer 57 are formed on the surfaces of the second insulating film 54 and the third insulating film 56 with conductive wires 55a and 57a, respectively. The conductive wires 55a and 57a may be made of a conductive plating film, such as copper. The wiring layers and insulating films can be laminated repeatedly in the same manner.

[0031] Vias 61 are formed in the first insulating film 52 to electrically connect the conductor 53a of the second wiring layer 53 to the conductor 51a of the first wiring layer 51. The vias 61 may be made of a conductive plating film such as copper. Similarly, vias 62 and 63 are formed in the individual insulating films 54 and 56 to electrically connect the upper wiring layers 55 and 57 to the lower wiring layers 53 and 55. The vias 62 and 63 ensure current flow between the upper and lower conductors 53a, 55a, and 57a.

[0032] Conductive pads 65 are placed on the bottom surface (back surface of the package substrate 15). Solder balls 14 are bonded to each conductive pad 65. Vias 66 are formed in the fourth insulating film 58 to electrically connect the conductive pads 65 to the conductors 57a of the fourth wiring layer 57. The vias 66 may be made of a conductive plating film, such as copper.

[0033] Through-holes (TGVs) 67 are formed in the core substrate 21, penetrating from both sides. The TGVs may be filled with, for example, copper or other conductive material. The through-holes 67 ensure electrical conductivity through specific wires 31a and 51a.

[0034] As shown in Figure 3, in the multilayer film 22, the conductors 31a of the first wiring layer 31 are formed in a grid pattern. The grid pattern should be spread across the entire surface of the first wiring layer 31. The grid pattern is drawn with contour lines parallel to the first reference line FL and contour lines parallel to the second reference line SL which is perpendicular to the first reference line FL. The line width WL of the conductors 31a should be set uniformly across the entire surface of the first wiring layer 31. The spacing Sp between conductors 31a extending parallel to the first reference line FL should be set uniformly across the entire surface of the first wiring layer 31. The spacing Sp between conductors 31a extending parallel to the second reference line SL should be set uniformly across the entire surface of the first wiring layer 31. The space of the grid pattern should be divided into squares by the conductors 31a. Instead of squares, it may be divided into rectangles. The first reference line FL and the second reference line SL are set in a predetermined positional relationship with respect to at least three alignment marks 71a, 71b, and 71c.

[0035] The first wiring layer 31 defines the current path pc by the breaks 72a and 72b in the conductors 31a. The break 72a may be established, for example, between two conductors 31a extending parallel to the first reference line FL, in a conductor 31a extending parallel to the second reference line SL. Similarly, the break 72b may be established, for example, between two conductors 31a extending parallel to the second reference line SL, in a conductor 31a extending parallel to the first reference line FL. It is desirable that the distance between the breaks 72a and 72b be minimized as much as possible.

[0036] The conductors 33a of the second wiring layer 33 are formed in a grid pattern. The grid pattern should be spread across the entire surface of the second wiring layer 33. The grid pattern is drawn with contour lines parallel to the first reference line FL and contour lines parallel to the second reference line SL, which is perpendicular to the first reference line FL. The line width WL of the conductors 33a should be set uniformly across the entire surface of the second wiring layer 33. The spacing Sp between conductors 33a extending parallel to the first reference line FL should be set uniformly across the entire surface of the second wiring layer 33. The spacing Sp between conductors 33a extending parallel to the second reference line SL should be set uniformly across the entire surface of the second wiring layer 33. The space of the grid pattern should be divided into squares by the conductors 33a. It may be divided into rectangles instead of squares. The first reference line FL and the second reference line SL are set in a predetermined positional relationship with respect to at least three alignment marks 73a, 73b, and 73c.

[0037] The second wiring layer 33 defines the current path pc by the breaks 74a and 74b in the conductors 33a. The break 74a may be established, for example, between two conductors 33a extending parallel to the first reference line FL, in a conductor 33a extending parallel to the second reference line SL. Similarly, the break 74b may be established, for example, between two conductors 33a extending parallel to the second reference line SL, in a conductor 33a extending parallel to the first reference line FL. It is desirable that the distance between the breaks 74a and 74b be minimized as much as possible.

[0038] The conductors 35a of the third wiring layer 35 are formed in a grid pattern. The grid pattern should be spread across the entire surface of the third wiring layer 35. The grid pattern is drawn with contour lines parallel to the first reference line FL and contour lines parallel to the second reference line SL which is perpendicular to the first reference line FL. The line width WL of the conductors 35a should be set uniformly across the entire surface of the third wiring layer 35. The spacing Sp between conductors 35a extending parallel to the first reference line FL should be set uniformly across the entire surface of the third wiring layer 35. The spacing Sp between conductors 35a extending parallel to the second reference line SL should be set uniformly across the entire surface of the third wiring layer 35. The space of the grid pattern should be divided into squares by the conductors 35a. It may be divided into rectangles instead of squares. The first reference line FL and the second reference line SL are set in a predetermined positional relationship with respect to at least three alignment marks 76a, 76b, and 76c.

[0039] The third wiring layer 35 defines the current path pc by the breaks 76a and 76b in the conductors 35a. The break 76a may be established, for example, between two conductors 35a extending parallel to the first reference line FL, in a conductor 35a extending parallel to the second reference line SL. Similarly, the break 76b may be established, for example, between two conductors 35a extending parallel to the second reference line SL, in a conductor 35a extending parallel to the first reference line FL. It is desirable that the distance between the breaks 76a and 76b be minimized as much as possible.

[0040] The grid pattern of the second wiring layer 33 overlaps with the grid pattern of the first wiring layer 31. To establish the overlap, the alignment marks 73a, 73b, and 73c of the second wiring layer 33 are aligned with the corresponding alignment marks 71a, 71b, and 71c of the first wiring layer 31, respectively. The grid pattern of the third wiring layer 35 overlaps with the grid pattern of the second wiring layer 33. To establish the overlap, the alignment marks 75a, 75b, and 75c of the third wiring layer 35 are aligned with the corresponding alignment marks 73a, 73b, and 73c of the second wiring layer 33, respectively. When wiring layers and insulating films are repeatedly stacked in a similar manner, the grid pattern of the upper wiring layer overlaps with the grid pattern of the lower wiring layer. Alignment marks are used similarly to establish the overlap. In this way, the grid patterns of the wiring layers overlap within a single multilayer film 22. When the multilayer film 22 is viewed from the vertical, one grid pattern can be identified.

[0041] The via 41 of the first insulating film 32 connects the intersection of the conductor 31a of the first wiring layer 31 and the intersection of the conductor 33a of the second wiring layer 33. At the intersection of conductors 31a and 33a, the corners partitioned by the side walls of the intersecting conductors 31a and 33a are formed as fillets. The via 42 of the second insulating film 34 connects the intersection of the conductor 33a of the second wiring layer 33 and the intersection of the conductor 35a of the third wiring layer 35. At the intersection of conductor 35a, the corners partitioned by the side walls of the intersecting conductors 35a are formed as fillets. The via 43 of the third insulating film 36 connects the intersection of the conductor 33a of the third wiring layer 33 and the intersection of the conductor 37a of the fourth wiring layer 37. At the intersection of conductor 37a, the corners partitioned by the side walls of the intersecting conductors 37a are formed as fillets. The multilayer films 23 and 27 can be configured similarly.

[0042] Next, the manufacturing method of the multilayer film 22 will be described. The first wiring layer 31, the second wiring layer 33, the third wiring layer 35, and the fourth wiring layer 37 are designed based on a grid pattern set on a virtual plane. Conductors 31a, 33a, 35a, and 37a are drawn according to the grid pattern. When setting the current path pc, open circuits 72a, 72b, 73a, 73b, 74a, and 74b are established in the conductors 31a, 33a, 35a, and 37a. Conductors 31a, 33a, 35a, and 37a are cut at the locations of the open circuits 72a, 72b, 73a, 73b, 74a, and 74b. Conductors 31a, 33a, 35a, and 37a are interconnected by vias 41, 42, and 43. For the design of the multilayer film 22, a CAD (computer-aided design) system optimized for circuit design may be used, for example.

[0043] As shown in Figure 4, a core substrate 21 is prepared. A base layer 81 is deposited on the surface of the core substrate 21. The base layer 81 may be formed from, for example, copper. For film deposition, sputtering may be used, for example. A negative-type photoresist 82 is laminated on the surface of the base layer 81. The photoresist 82 may be a liquid applied to the surface of the core substrate 21 or it may be in the form of a sheet that can be easily attached.

[0044] The photoresist 82 is exposed in an exposure apparatus. During exposure, UV light is irradiated onto the photoresist 82. The UV light is drawn according to the grid pattern. The UV light may be ultraviolet light regulated by a so-called reticle 83, or ultraviolet light for direct drawing (DI). The photoresist 82 hardens in response to the ultraviolet light. After that, as shown in Figure 5, the photoresist 82 is developed. The uncured photoresist 82 is removed. Trench 84 is formed. The underlying layer 81 is exposed in the trench 84. When the plating process is performed, a copper plating film grows from the underlying layer 81. Conductor wires 31a are formed. The conductor wires 31a are formed in a grid pattern.

[0045] As shown in Figure 6, the photoresist 82 is removed. The substrate 81 is exposed in the space surrounded by the conductor 31a and at the locations of the breaks 72a and 72b. The exposed substrate 81 is etched. The conductor 31a is cut at the breaks 72a and 72b. The current path pc is established. The first wiring layer 31 is formed.

[0046] As shown in Figure 7, the first insulating film 32 is laminated on the first wiring layer 31. For example, insulating film sheets are stacked. After softening in response to heat treatment, the insulating film sheets harden. At this time, undulations resembling the conductors 31a are established on the surface of the first insulating film 32. The conductors 31a are covered by the plateau region 85.

[0047] As shown in Figure 8, through holes 86 are formed in the first insulating film 32 to expose the conductor 31a. The through holes 86 correspond to vias 41. Subsequently, as shown in Figure 9, a base layer 87 is deposited on the surface of the first insulating film 32. The base layer 87 adheres to the inner wall surface of the through holes 86. The base layer 87 may be formed from, for example, copper. For deposition, sputtering may be used, for example. A negative-type photoresist 88 is laminated on the surface of the base layer 87. The photoresist 88 may be a liquid applied to the surface of the core substrate 21 or a sheet that can be easily attached. The surface of the photoresist 88 reflects the undulations of the first insulating film 32. A plateau 88a is formed on the surface of the photoresist 88, representing the plateau region 85 of the first insulating film 32.

[0048] The photoresist 88 is exposed using an exposure device. During exposure, UV light is shone onto the photoresist 88. The UV light draws according to the grid pattern. The UV light may be ultraviolet light regulated by the so-called reticle 89, or ultraviolet light used for direct writing (DI). The photoresist 88 hardens in response to the ultraviolet light. At this time, since the UV light follows a trajectory on the base 88a, the optical path length of the UV light (irradiated light) is kept constant. Exposure is achieved with good accuracy. The accuracy of the drawing is improved.

[0049] Subsequently, as shown in Figure 10, the photoresist 88 is developed. The uncured photoresist 88 is removed. A trench 91 is formed. The underlying layer 87 is exposed in the trench 91. When the plating process is performed, a copper plating film grows from the underlying layer 87. Conductors 33a are formed. The conductors 33a are formed in a grid pattern.

[0050] As shown in Figure 11, the photoresist 88 is removed. The underlayer 87 is exposed in the space surrounded by the conductor 33a and at the locations of the breaks 74a and 74b. The exposed underlayer 87 is etched. The conductor 33a is cut at the breaks 74a and 74b. The current path pc is established. The second wiring layer 33 is formed.

[0051] As shown in Figure 12, the second insulating film 34 is laminated on the second wiring layer 33. For example, insulating film sheets are stacked. After softening in response to heat treatment, the insulating film sheets harden. At this time, undulations resembling the conductors 33a are established on the surface of the second insulating film 34. The conductors 33a are covered by the plateau region 92.

[0052] As shown in Figure 13, the third wiring layer 35 and the fourth wiring layer 37 are similarly stacked repeatedly. A multilayer film 22 with a build-up structure, including alternating wiring layers 31, 33, 35, 37 and insulating films 32, 34, 36, 38, is formed on the surface of the core substrate 21. The grid patterns of all wiring layers 31, 33, 35, and 37 overlap. In the exposure apparatus, the optical path length of the UV ray is kept constant when drawing the wires 31a, 33a, 35a, and 37a. The precision of all wiring layers 31, 33, 35, and 37 is improved. Miniaturization of the wiring layers 31, 33, 35, and 37 is achieved. Multilayer films 23 and 27 can be manufactured in the same manner.

[0053] In this embodiment, grid pattern wires 31a, 33a, 35a, and 37a are laid out in each layer. The grid patterns of the upper wiring layers 33, 35, and 37 overlap with the grid patterns of the lower wiring layers 31, 33, and 35. In each grid pattern, the current path pc is defined by the open wires 72a, 72b, 74a, 74b, 75a, 75b, etc. Since the grid patterns overlap, the optical path length of the irradiated light is kept constant when drawing the wires 33a, 35a, and 37a in the exposure apparatus. Exposure is achieved with good accuracy. The accuracy of the wiring layers 33, 35, and 37 is improved. Miniaturization of the wiring layers 33, 35, and 37 is achieved. Similarly, in the multilayer film 23, the grid patterns of the upper wiring layers 53, 55, and 57 only need to overlap with the grid patterns of the lower wiring layers 51, 53, and 55. In each individual grid pattern, the current path is defined by a break in the wire. Since the grid patterns overlap, the optical path length of the irradiated light is kept constant in the exposure apparatus when drawing the wires. Similarly, in the multilayer film 27 of the interposer 16, the grid pattern of the upper wiring layer should overlap with the grid pattern of the lower wiring layer. In each individual grid pattern, the current path is defined by a break in the wire. Since the grid patterns overlap, the optical path length of the irradiated light is kept constant in the exposure apparatus when drawing the wires.

[0054] In the multilayer film 22, vias 41, 42, and 43 are formed in the first insulating film 32, the second insulating film 34, and the third insulating film 36. Each via 41, 42, and 43 connects the intersections of the lower layer conductors 31a, 33a, and 35a to the intersections of the upper layer conductors 33a, 35a, and 37a. Even if the vias 41, 42, and 43 are misaligned in the in-plane direction, good connectivity between the vias 41, 42, and 43 and the conductors 31a, 33a, 35a, and 37a is ensured at the intersections of the lower layer conductors 31a, 33a, and 35a and the upper layer conductors 33a, 35a, and 37a. The effect of the misalignment of the vias 41, 42, and 43 is minimized. The yield of the package substrate 15 and the interposer 16 can be increased. In particular, at the intersections of conductors 31a, 33a, 35a, and 37a, the corners are formed as fillets, which allows for a wider range of misalignment.

[0055] In the package substrate 15 according to this embodiment, the multilayer film 22 on the front side and the multilayer film 23 on the back side are formed in a symmetrical structure with respect to the core substrate 27. In forming the symmetrical structure, the multilayer films 22 and 23 only need to have the same layer structure. The number of wiring layers and insulating films should be the same for the multilayer films 22 and 23. The thickness of the wiring layers and insulating films should be the same. The grid patterns of the multilayer films 22 and 23 should be the same. The multilayer films 22 and 23 should have thermal expansion amounts that match at least in the in-plane direction. Warping of the package substrate 15 can be eliminated (or at least suppressed) by establishing a symmetrical structure.

[0056] As shown in Figures 14 and 15, in the exposure apparatus, positive-type photoresists 94 and 95 may be used instead of the aforementioned negative-type photoresists 82 and 88 for drawing the wires 31a, 33a, 35a and 37a. The positive-type photoresist 94 is laminated on the surface of the underlayer 81. The photoresist 94 may be applied to the surface of the core substrate 21, for example, by spin coating. The photoresist 94 is soft-baked. The photoresist 94 is dried.

[0057] Next, the photoresist 94 is exposed. During exposure, UV light is shone onto the photoresist 94. The UV light is used to draw a grid pattern. The UV light may be ultraviolet light regulated by the so-called reticle 96, or direct-in-direct (DI) ultraviolet light may be used. The solubility of the photoresist 94 is increased in response to the UV light irradiation. After that, the photoresist 94 is developed. Similar to Figure 5, trenches are formed in the photoresist 94. After the plating process, the conductive wire 31a is formed.

[0058] As shown in Figure 15, the underlayer 97 is formed on the surface of the first insulating film 32. The underlayer 97 adheres to the inner wall surface of the through hole 86. The underlayer 97 may be formed from, for example, copper. For film formation, sputtering may be used, for example. A positive-type photoresist 95 is laminated on the surface of the underlayer 97. The photoresist 95 may be applied to the surface of the core substrate 21 by, for example, spin coating. The photoresist 95 is soft-baked. The photoresist 95 is dried. The surface of the photoresist 95 reflects the undulations of the first insulating film 32. A plateau 95a is formed on the surface of the photoresist 95, representing the plateau region 85 of the first insulating film 32.

[0059] The photoresist 95 is exposed using an exposure apparatus. During exposure, UV light is irradiated onto the photoresist 95. The UV light draws according to the grid pattern. The UV light may be ultraviolet light regulated by the so-called reticle 98, or ultraviolet light used for direct writing (DI). The solubility of the photoresist 95 is increased in response to the UV light irradiation. At this time, since the UV light follows a trajectory on the plateau 95a, the optical path length of the UV light (irradiated light) is kept constant. Exposure is achieved with good accuracy. The accuracy of the drawing is improved.

[0060] Subsequently, the photoresist 95 is developed. Similar to Figure 10, trenches are formed in the photoresist 95. After the plating process, the conductors 33a are formed. The conductors 33a are formed in a grid pattern.

[0061] As described above, since the grid patterns overlap, the optical path length of the irradiated light is kept constant in the exposure apparatus when drawing the conductors 33a, 35a, and 37a. Exposure is achieved with good accuracy. The accuracy of the wiring layers 33, 35, and 37 is improved. Miniaturization of the wiring layers 33, 35, and 37 is achieved.

[0062] As shown in Figure 16, the package substrate 15 may be replaced with a coreless build-up substrate 101. The build-up substrate 101 comprises a first wiring layer 102 formed on a virtual plane with conductive wires 102a, and a first insulating film 103 laminated on the first wiring layer 102. The conductive wires 102a may be composed of a conductive plating film such as copper. The first insulating film 103 covers the conductive wires 102a. The first insulating film 103 may be formed from epoxy resin. Polyimide resin or other insulating materials may be used for the first insulating film 103.

[0063] A second wiring layer 104 is laminated onto the first insulating film 103. The second wiring layer 104 is formed on the surface of the first insulating film 103 with a conductor 104a. The conductor 104a may be made of a conductive plating film, such as copper. A second insulating film 105 is laminated onto the second wiring layer 104. The second insulating film 105 covers the conductor 104a. The second insulating film 105 may be formed from epoxy resin. Polyimide resin or other insulating materials may be used for the second insulating film 105.

[0064] The second insulating film 105 is laminated in order with wiring layers 106-109, 111 and insulating films 112-116. Each wiring layer 106-109, 111 is formed on the surface of insulating films 112-116 with conductors 106a-109a, 111a. The conductors 106a-109a, 111a may be made of a conductive plating film, such as copper. The wiring layers and insulating films can be laminated repeatedly in the same manner.

[0065] Vias are formed in the first insulating film 103 to electrically connect the conductor 104a of the second wiring layer 104 to the conductor 102a of the first wiring layer 31. The vias may be made of a conductive plating film, such as copper. Similarly, vias are formed in each insulating film 105, 112-115 to electrically connect the upper wiring layers 107-109, 111 to the lower wiring layers 106-109. The vias ensure current flow between the upper and lower conductors 104a, 106a-109a.

[0066] Conductive pads 45 are placed on the surface of the uppermost layer. C4 bumps 24 of the interposer 16 are bonded to each conductive pad 45. Vias 46 are formed in the insulating film 116 to electrically connect the conductive pads 45 to the conductors 111a of the wiring layer 111. The vias 46 may be made of a conductive plating film, such as copper.

[0067] In the build-up substrate 101, the conductors of the individual wiring layers 102a, 104a, 106a-109a, and 111a are formed in a grid pattern, similar to the first to fourth wiring layers 31, 33, 35, and 37 described above. The grid patterns of the upper wiring layers 104, 106-109, and 111 overlap with the grid patterns of the lower wiring layers 102, 104, and 106-109. Alignment marks are used in the same way to establish the overlap. Thus, the grid patterns of the wiring layers 102, 104, 106-109, and 111 overlap within a single build-up substrate 101. When the build-up substrate 101 is viewed from the vertical, one grid pattern can be identified.

[0068] In manufacturing the build-up board 101, individual wiring layers 102, 104, 106-109, and 111 are designed based on a grid pattern set on a virtual plane. Conductors 102a, 104a, 106a-109a, and 111a are drawn according to the grid pattern. When setting the current path, breaks are established in the conductors 102a, 104a, 106a-109a, and 111a. Conductors 102a, 104a, 106a-109a, and 111a are cut at the location of the break. Conductors 102a, 104a, 106a-109a, and 111a are interconnected by vias. For the design of the build-up board 101, a CAD (computer-aided design) system optimized for circuit design may be used, for example.

[0069] As described above, a core substrate is prepared. On the core substrate, wiring layers 102, 104, 106-109, 111 and insulating films 103, 105, 112-116 are laminated as described above. The wiring layers 102, 104, 106-109, 111 and insulating films 103, 105, 112-116 are separated from the core substrate. In this way, the build-up substrate 101 is manufactured. [Explanation of symbols]

[0070] 15...Substrate for semiconductor equipment (package substrate), 16...Substrate for semiconductor equipment (interposer), 17...Semiconductor chip, 21...Core substrate, 31...Wiring layer (first wiring layer), 31a...Conductor, 32...Insulating film (first insulating film), 33...Second wiring layer, 33a...Second conductor (conductor), 34...Second insulating film, 35...Second wiring layer (third wiring layer), 35a...Second conductor Wire (conductor), 37...Second wiring layer (fourth wiring layer), 37a...Second conductor (conductor), 41...Via, 42...Via, 43...Via, 51...Wiring layer (first wiring layer), 51a...Conductor, 52...Insulating film (first insulating film), 53...Second wiring layer, 53a...Second conductor (conductor), 55...Second wiring layer (third wiring layer), 55a...Second conductor (conductor), 57...Second wiring layer (fourth wiring layer) ), 57a...Second conductor (conductor), 61...Via, 62...Via, 63...Via, 72a...Break, 72b...Break, 74a...Break, 74b...Break, 76a...Break, 76b...Break, 101...Substrate for semiconductor equipment (build-up substrate), 102...Wiring layer (first wiring layer), 102a...Conductor, 103...Insulating film (first insulating film), 104...Second wiring layer, 104a...Second 2 conductor (conductor), 106...second wiring layer (wiring layer), 106a...second conductor (conductor), 107...second wiring layer (wiring layer), 107a...second conductor (conductor), 108...second wiring layer ( 108a...second conductor (conductor), 109...second conductor (wiring layer), 109a...second conductor (conductor), 111...second interconnect layer (wiring layer), 111a...second conductor (conductor).

Claims

1. 1. A wiring layer formed on a virtual plane by wires in a grid pattern, where the path of the current is defined by the break of the wires, An insulating film laminated on the wiring layer, A second wiring layer is laminated on the insulating film and formed by second conductors with a grid pattern that overlaps the grid pattern, and the break of the second conductors defines the path of the current. A substrate for semiconductor devices, characterized by comprising the following features.

2. A substrate for a semiconductor device according to claim 1, characterized in that it comprises vias formed in the insulating film that connect the intersection of the conductor and the intersection of the second conductor.

3. A substrate for a semiconductor device according to claim 2, characterized in that the insulating film and the second wiring layer are repeatedly laminated on the second wiring layer.

4. A substrate for a semiconductor device according to claim 3, characterized in that the wiring layer is laminated on the surface of a core substrate formed from glass.

5. A substrate for a semiconductor device according to claim 3, characterized in that the wiring layer is laminated on the surface of a core substrate formed from silicon.

6. 1. A wiring layer formed on a virtual plane by wires in a grid pattern, where the path of the current is defined by the break of the wires, An insulating film laminated on the wiring layer, A semiconductor chip supported on the insulating film and connected to the path A semiconductor package characterized by comprising the following features.

7. core substrate and A first wiring layer is formed on the front side of the core substrate by first conductors in a planar first grid pattern, and the break of the first conductors defines the path of the current, A first insulating film laminated on the first wiring layer, A second wiring layer is formed on the back side of the core substrate by second conductors forming a planar second lattice pattern that follows the first lattice pattern, and the break of the second conductors defines the path of the current. The second insulating film laminated on the second wiring layer and A substrate for semiconductor devices, characterized by comprising the following features.

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