Voltage-driven semiconductor device with a three-dimensional channel structure on a SiC stack

Abstract

In a voltage-driven semiconductor device provided on a cubic SiC layer on a hexagonal SiC layer, the carrier mobility and current density in the channel are improved, while suppressing the occurrence of stacking faults. By combining this with the robust voltage resistance capability of hexagonal SiC, it becomes possible to manufacture a high-performance voltage-driven semiconductor device. [Solution] In a SiC laminate in which a cubic SiC layer without a twinning interface is stacked on a hexagonal SiC layer via a matching interface, the sides consisting of the cubic SiC portion side surface and the hexagonal SiC portion side surface are exposed, the maximum width of the matching interface is set to 3 micrometers or less, and the width of the hexagonal SiC portion side surface perpendicular to the matching interface is set to 0.1 micrometers or more and 3.0 micrometers or less, and a three-dimensional channel is provided on the cubic SiC portion side surface.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device that controls the output current by a voltage applied to a gate electrode (voltage-driven type), using a laminate in which single-crystal cubic SiC is stacked on a single-crystal hexagonal SiC layer. In particular, the present invention relates to a semiconductor device having a three-dimensional channel structure that achieves low on-resistance due to a high-mobility channel, long-term reliability, high voltage resistance, and low leakage characteristics simultaneously. [Background technology]

[0002] Silicon carbide (SiC) is being increasingly used in next-generation power semiconductor devices because it has a higher dielectric breakdown field strength and lower conduction loss compared to silicon (Si). Currently, 4H-SiC, a type of hexagonal SiC, is mainly used as a substrate for power semiconductor devices. However, 4H-SiC has drawbacks, including a wide band gap resulting in a high trap density at the metal-oxide-semiconductor (MOS) interface, and poor long-term reliability of the gate insulating film.

[0003] In the field of power semiconductor devices using SiC, a trench MOSFET (trench MOSFET) with a trench structure, as provided in Japanese Patent No. 4738562 (Patent Document 1), has been put into practical use with the aim of further increasing the breakdown voltage and reducing the on-resistance. In addition, a power MOSFET structure with low conduction loss, as described in Japanese Patent No. 5184779 (Patent Document 2), is provided, in which the concentration on the outermost surface of the p-well is relatively lower compared to the peak concentration.

[0004] On the other hand, cubic SiC (3C-SiC), which has the narrowest band gap among the various crystal structures of SiC, has high bulk mobility and good long-term reliability of MOS interface characteristics and gate insulating films, but it has been difficult to obtain large-area, high-quality single-crystal thick films. To solve this problem, the applicant provides a multilayer epitaxial growth technology for growing high-quality cubic SiC with few crystal defects on a hexagonal SiC substrate using the structures and methods described in the prior inventions of Japanese Patent No. 6795805 (Patent Document 3) and Japanese Patent No. 7804352 (Patent Document 4). Furthermore, to prevent the depletion layer formed at the matching interface (X) between hexagonal SiC and cubic SiC from obstructing the current path, Japanese Patent No. 7804383 (Patent Document 5) exposes the section (Sx) of the heteromatching interface of SiC on the surface, and then applies 1 × 10⁻¹⁶ layers to the surface layer including the exposed heteromatching interface (Sx). 19 cm -3 By adding impurities at the concentrations mentioned above, a tunnel-doped region (Dt) is created, and a method has been proposed to keep the characteristic on-resistance of the semiconductor device low through a carrier transport mechanism via tunneling.

[0005] Alternatively, as a semiconductor device structure using cubic SiC as a substrate, as described in Japanese Patent Publication No. 5307381 (Patent Document 6), a structure is disclosed in which the gate insulating film on the surface of the SiC substrate is macroscopically parallel to a non-polar surface, and microscopically consists of a non-polar surface and a polar surface, with either a Si surface or a C surface being predominant among the polar surfaces. In this structure, even if the SiC has a non-polar surface as the main surface, a specific polar surface is oriented at the microscopic interface with the gate insulating film or metal, so that electric field variations that occur between different polar surfaces do not occur, and deterioration of interface smoothness due to differences in thermal oxidation rates is suppressed. As a result, Coulomb scattering at the interface between the gate insulating film and SiC is suppressed, and losses during conduction are reduced by improving channel mobility. In this specification, the channel mobility improvement effect provided by Patent Document 6 is referred to as the "polar surface orientation effect".

[0006] Furthermore, as a substrate for manufacturing the above-mentioned semiconductor device, Japanese Patent Publication No. 7-118854 (Patent Document 7) provides a method for forming a SiC film that exhibits small variations in SiC film thickness and excellent uniformity of film quality and flatness. In this method, a SiC film of a predetermined thickness is formed by growing SiC on a substrate containing Si atoms or C atoms by a chemical reaction using a Si source gas and a C source gas. The method discloses a method in which the Si source gas is thermally decomposed in a state where hydrogen gas is substantially absent, and the Si compound produced by this thermal decomposition is adsorbed onto a predetermined growth surface on the substrate, and the Si compound adsorbed onto the growth surface in the first step is carbonized with a carbon source gas to generate SiC, and these steps are alternately repeated once or more times under reduced pressure while heating the substrate. In this specification, this method is called "atomic layer epitaxy".

[0007] In addition to the above technologies, in order to improve the mobility of carriers by making the surface of the single-crystal SiC layer in contact with the film an appropriate surface, Japanese Patent Publication No. 6884532 (Patent Document 8) provides a method for manufacturing a SiC structure that includes a step of forming a film different from SiC so as to be in contact with a surface that is exposed to only one of either a SiC surface having a hexagonal close-packed structure or a SiC surface having a cubic close-packed structure, and the step of epitaxially growing SiC on a single-crystal SiC layer so that atomic step ends terminated on one of Si and C grow epitaxially faster than atomic step ends terminated on the other of Si and C. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Patent No. 4738562 [Patent Document 2] Patent No. 5184779 [Patent Document 3] Patent No. 6795805 [Patent Document 4] Patent No. 7804352 [Patent Document 5] Japanese Patent No. 7804383 [Patent Document 6] Japanese Patent No. 5307381 [Patent Document 7] Japanese Unexamined Patent Application Publication No. 7-118854 [Patent Document 8] Japanese Patent No. 6884532 [Summary of the Invention] [Problems to be Solved by the Invention]

[0009] In a conventional trench MOSFET using 4H-SiC as described in Patent Document 1, even when controlling the crystal orientation of the trench side surface, due to the width of the bandgap inherent in 4H-SiC (i.e., the height of the interface state density), the channel resistance becomes high, and there is a limit to reducing the on-resistance characteristic. In addition to this, since the leakage current density of the gate insulating film is also high, there has been a problem that long-term stable operation is impaired.

[0010] Patent Documents 6 and 8 provide methods for reducing channel resistance using cubic SiC MOSFETs. However, since cubic SiC has a lower breakdown electric field strength than 4H-SiC, when attempting to achieve the same breakdown voltage as hexagonal SiC, it is necessary to increase the thickness of the drift layer while lowering the impurity concentration, and there has been a problem that the on-resistance characteristic becomes high due to the increase in drift resistance.

[0011] To overcome the above problems, the method described in Patent Document 3 provides a structure and a method for manufacturing the same, in which a channel is provided in cubic SiC with high carrier mobility and a drift layer is provided in hexagonal SiC with a wide band gap. However, if a high electric field is applied to the matching interface between cubic SiC and hexagonal SiC, there is a concern that leakage current will increase due to the interface states. In particular, when reducing on-resistance by providing a highly doped layer (Dt) at the location where the intercept (Sx) of the matching interface between cubic SiC and hexagonal SiC is exposed, as in Patent Document 5, it is essential to ensure that the electric field does not apply to the surface where the intercept (Sx) of the matching interface is exposed in order to suppress current leakage. Furthermore, since the {111} plane of the cubic SiC in which the channel is provided is a polar plane, the interface state density with the gate insulating film is high, and the effective mass of electrons is larger compared to other crystal lattice planes, making it more difficult to reduce channel resistance compared to the non-polar plane of cubic SiC described in Patent Document 6.

[0012] As described in Patent Documents 3 and 4, when forming a cubic SiC layer without twinning interfaces (single-domain) on a hexagonal SiC layer, it is necessary to first form atomically flat basal plane terraces (WTs) parallel to the closest-packed planes of the hexagonal SiC crystal lattice and extend the width of these basal plane terraces to the critical value (Wc) for spontaneous nucleation. Basal plane terraces (WTs) can be formed by performing step-controlled epitaxy on locally grooved hexagonal SiC micro-inclined surfaces, but an epitaxial growth temperature of 1500°C or higher is required to maintain high crystal quality of the epitaxial growth layer. However, with step-controlled epitaxy at 1500°C or higher, it is not possible to reduce Wc to 6 micrometers or less. In other words, the lower limit of the single cell size remains at 6 micrometers, making it difficult to manufacture high-current semiconductor devices using finer, high-density MOSFET cells.

[0013] Furthermore, because there is a difference of approximately 0.3% in the direction parallel to the matching interface (X) between the crystal lattice spacing of cubic SiC and hexagonal SiC, crystal lattice strain occurs near the matching interface (X). This strain increases as the area of ​​the matching interface (X) increases (i.e., as the area of ​​the cubic SiC layer increases), inducing the motion of Half-Loop dislocations along the close-packed plane. The resulting stacking faults hinder carrier transport in semiconductor devices, leading to increased characteristic on-resistance and deterioration of long-term reliability.

[0014] This invention was obtained after extensive research to solve all of the above-mentioned problems. It further increases the channel mobility of cubic SiC, facilitates the improvement of current density through a fine device structure, suppresses the generation and movement of Half-Loop dislocations, and combines this with the robust voltage resistance capability of hexagonal SiC, thereby enabling the manufacture of extremely high-performance voltage-driven semiconductor devices. [Means for solving the problem]

[0015] The semiconductor device according to the present invention uses a SiC laminate in which a single crystal cubic SiC layer is stacked on a single crystal hexagonal SiC layer, and has the following configuration.

[0016] [Configuration 1] A voltage-driven semiconductor device having a three-dimensional structure provided on a SiC laminate in which a single crystal cubic SiC layer (Ec) without a twinning interface is stacked on a single crystal hexagonal SiC layer (Eh), wherein the closest-packed crystal lattice of the cubic SiC layer (Ec) abuts with the closest-packed crystal lattice of the lower hexagonal SiC layer (Eh) to form a matching interface (X), the SiC laminate is provided with a side surface (S) perpendicular to the matching interface (X), the width (d) of the matching interface (X) is kept to 3 micrometers or less by termination by the side surface (S), the channel (Ch) of the semiconductor device is formed on a cubic SiC partial side surface (Sc) that constitutes a part of the side surface (S), and the intercept (Sx) of the matching interface exposed on the side surface (S) is located at an offset distance (hx) of 0.1 micrometers or more and 3.0 micrometers or less from the lower end of the side surface (S). [Configuration 2] A semiconductor device as described in Configuration 1, characterized in that the carrier transport direction in the channel (Ch) is parallel to the matching interface (X), and the crystal lattice plane of the cubic SiC partial side surface (Sc) exposed on the side surface (S) belongs to the {1-10} plane. [Configuration 3] A semiconductor device as described in Configuration 1, wherein the carrier transport direction in the channel (Ch) is perpendicular to the matching interface (X), and the crystal lattice plane of the cubic SiC partial side surface (Sc) exposed on the side surface (S) belongs to at least one of the {1-10} plane or the {11-2} plane. [Configuration 4] A semiconductor device as described in Configuration 1, characterized in that a field relaxation region (B), which is a second-conductivity impurity doping region, is provided on the surface (Fc) of the hexagonal SiC layer adjacent to the lower end of the side surface. [Configuration 5] A semiconductor element as described in Configuration 1, characterized in that the side surface (S) is the outer surface of a columnar structure perpendicular to the matching interface (X). [Configuration 6] A semiconductor device according to any one of Configurations 1 to 5, characterized in that a concentration gradient of impurities consisting of a first conduction type is provided in at least one of the cubic SiC layer (Ec) or hexagonal SiC layer (Eh) that exposes the side surface (S), in a direction perpendicular to the matching interface (X). [Effects of the Invention]

[0017] The effects of the present invention are realized by synergistically combining the anisotropy of the effective carrier mass derived from the electronic energy structure of cubic SiC, the physical properties of the nonpolar surfaces of SiC, the unique behavior of carriers arising from energy barriers and crystal lattice strains that appear at matching interfaces of different crystal structures, and the dislocation-theoretic advantages brought about by the three-dimensional structure of the semiconductor device. The effects of the present invention are described below.

[0018] [Improved Current Density and Reduced Characteristic On-Resistance] The physical properties of the cubic SiC layer (Ec), a component of the present invention, are that the carrier mobility in the crystal is higher than that of the hexagonal SiC layer (Eh), and the interface state density with the gate insulating film is lower. These are the main factors that reduce channel resistance. Furthermore, in the present invention, channels are formed on the partial side surface (non-polar surface) of the single-domain cubic SiC layer, which also suppresses carrier scattering factors, thus maintaining the long-term stability and high reproducibility of the channel resistance suppression effect.

[0019] As shown in the perspective view of Figure 1 and the cross-sectional view of Figure 2, in the present invention, a cubic SiC layer (Ec) is heteroepitaxially grown on a hexagonal SiC layer (Eh) via a matching interface (X), and sides (S) such as trenches and columnar structures are provided, with the side (S) having exposed cubic SiC partial sides (Sc) and hexagonal SiC partial sides (S). Furthermore, the cross section (Sx) of the matching interface is exposed at a specific offset distance (hx) between 0.1 micrometers and 3.0 micrometers upward from the lower end of the side (S). In the present invention, since channels (Ch) are formed in the cubic SiC partial sides (Sc), it is possible to minimize the channel footprint in the horizontal direction of the substrate while increasing the area of ​​the cubic SiC partial sides (Sc) to expand the effective channel width. In addition, by making the cubic SiC portion side surface (Sc) a non-polar surface, it is possible to exhibit the polar surface orientation effect provided in Patent Document 6, and the channel mobility along the cubic SiC portion side surface (Sc) can be made to be superior to the channel mobility along the surface (Fc) of the cubic SiC layer.

[0020] When the crystal lattice plane of the cubic SiC partial side surface (Sc) shown in Figure 1 corresponds to a specific plane orientation of the {1-10} plane group, the effective mass of electrons within that side surface exhibits anisotropy. <111> For the orientation (perpendicular to X), the ratio of electrons to rest mass in a vacuum (effective mass ratio) is 0.32. On the other hand, for the orientation (parallel to X), the effective mass ratio is 0.25. Since electron mobility is inversely proportional to its effective mass, transporting electrons in the direction parallel to the matching interface (X) reduces the channel resistance by approximately 20%.

[0021] Furthermore, since the {1-10} plane of cubic SiC is a semipolar plane in which Si atoms and C atoms are exposed on the surface in an equal 1:1 ratio, charge imbalance and deposition of C atoms are suppressed. For this reason, as shown in the cross-sectional view in Figure 3, by providing a gate insulating film (Ox) and a gate electrode (G) on the side surface (Sc) of the cubic SiC portion, the interface state density can be kept lower than on other crystal lattice planes, making it possible to further reduce the channel resistance.

[0022] Furthermore, the structure of the semiconductor device provided by the present invention does not prevent the coexistence of channels (Ch) on the cubic SiC surface (Fc). For example, as shown in the cross-sectional view of Figure 4, the width of the channels (Ch) can be expanded by bringing the gate electrode (G) close to the cubic SiC surface (Fc) via a gate insulating film (Ox). In this case, the channel resistance can be further reduced compared to a semiconductor device using only channels (Ch) on the cubic SiC partial side surface (Sc).

[0023] Furthermore, each crystal lattice plane constituting the {1-10} plane group is similar to each crystal lattice plane constituting the {11-2} plane group, <111> The arrangement is symmetrical six times around the orientation axis. Therefore, by forming a hexagonal columnar structure as shown in the perspective view of Figure 5, and making the side surface of the cubic SiC portion either a {1-10} plane group or a {11-2} plane group crystal lattice plane, it becomes possible to increase the channel width per footprint compared to the trench side surface. Furthermore, by arranging multiple hexagonal columnar structures in a triangular lattice with {1-10} planes or {11-2} planes facing each other as shown in the plan views of Figures 6 and 7, the effective channel width per footprint is maximized, making it possible to further increase the current capacity of the semiconductor device. The cross-sectional view of the SiC stack consisting of hexagonal columnar structures is the same as in Figure 2.

[0024] In the present invention, as shown in the plan view of Figure 8, it is also possible to arrange a dodecagonal prismatic structure in a triangular lattice on the side surface of the cubic SiC layer, in which crystal lattice planes of the {1-10} plane group and crystal lattice planes of the {11-2} plane group are alternately adjacent. In this case, the effective mass ratio of electrons in the {1-10} plane and the effective mass ratio of electrons in the {11-2} plane are both <111> Since the ratio is 0.32 with respect to direction, current does not concentrate on any particular side. Also, the {1-10} plane and the {11-2} plane are <111> Because the planes are rotated 30 degrees around the axis of orientation, the angle between adjacent {1-10} and {11-2} planes is 150 degrees, which is wider than the 120 degrees that occurs when two {1-10} planes are adjacent. As a result, in the MOS structure, the maximum electric field strength applied to the gate insulating film (Ox) is reduced, further improving long-term reliability. The cross-sectional view of the SiC stack consisting of a dodecagonal prismatic structure is the same as in Figure 2.

[0025] [Achieving High Voltage Resistance and High Reliability through Protection of Matching Interface] In the trench-type MOSFET structure shown in the cross-sectional view of Figure 3, the carrier concentration transported in the channel (Ch) is controlled by the voltage applied to the gate electrode (G). In the present invention, similar to general trench-type MOSFETs including the structure provided in Patent Document 1, it is possible to form a junction field-effect transistor (JFET) structure by creating an electric field relaxation region (B) in the vicinity of the hexagonal SiC surface (Fh) located at the lower end of the side surface of the trench or columnar structure, so that the high electric field does not extend to the gate insulating film (Ox) adjacent to the channel (Ch). Here, the gap between mutually adjacent electric field relaxation regions (B) (JFET region) corresponds to the width of the trench or columnar structure and also coincides with the width (d) of the matching interface, so changing d also changes the pinch-off voltage (Vp) of the JFET. Figure 9 shows the dependence of the pinch-off voltage (Vp) on the width (d) of the matching interface. However, in accordance with the design of actual 1.2kV class power semiconductor devices, the concentration of the first conduction-type impurity in the drift layer provided within the hexagonal SiC layer (Ec) is set to 5 × 10⁻¹⁰ 15 cm -3 Assuming the concentration of the second conduction-type impurity in the electric field relaxation region (B) is 1 × 10⁻⁶ 18 cm -3 This is the assumption. From Figure 9, it can be seen that if d is 3 micrometers or less, Vp can be kept below 10V, and the electric field extending to the gate insulating film (Ox) is sufficiently suppressed. Furthermore, as d is reduced, Vp is relaxed even more, and for example, if d is 0.5 micrometers, Vp can be kept to an extremely low value of about 0.3V. In this specification, this pinch-off due to the electric field relaxation region (B) is called the "JFET effect".

[0026] As described above, although the JFET effect due to the electric field relaxation region (B) is clear, when a matched interface (X) is adjacent to the electric field relaxation region (B), the electric field extends to the interface levels contained in the interface and to the Half-Loop dislocations that occur in their vicinity, albeit slightly, causing current leakage. To avoid such current leakage, the present invention features a structure in which a segment (Sx) of the matched interface is placed in the "mid-section" of the side surface (S) of a trench or columnar structure, and is offset by an offset distance (hx) of 0.1 micrometers or more from the electric field relaxation region (B) formed at the lower end of these side surfaces (S), as shown in the perspective views of Figures 1 and 5 and the cross-sectional view of Figure 2. By using this structure, it is also possible to provide the tunnel-doped region (Dt) provided in Patent Document 5 on part or the entire surface of the matched interface (X).

[0027] Furthermore, in this invention, by providing a concentration gradient of first conduction-type impurities perpendicular to the matching interface (X) within the cubic SiC layer (Ec) or hexagonal SiC layer (Eh) that exposes the non-polar surface, it is possible to arbitrarily adjust the electric field distribution leaking from the electric field relaxation region (B). For example, by decreasing the concentration of first conduction-type impurities as it approaches the lower end of the side surface, the JFET effect within the hexagonal SiC layer (Eh) can be promoted, further reducing the electric field extending to the gate insulating film (Ox) and the matching interface (X).

[0028] As described above, by using the semiconductor device structure provided by the present invention, the electric field strength extending to the matching interface (X) and gate insulating film (Ox) is mitigated, allowing for the maintenance of the inherent breakdown voltage performance of hexagonal SiC while simultaneously achieving the low channel resistance of cubic SiC. In other words, a structure in which the matching interface (X) between the cubic SiC layer (Ec) and the hexagonal SiC layer (Eh) is located midway along the side of a trench or columnar structure spatially separates the effect of improving channel mobility from the electric field relaxation effect from the drift layer, resulting in an effect different from the structural characteristics of conventional trench MOSFETs using hexagonal SiC or Si as substrates. The offset distance (hx) should be selected from a value between 0.1 micrometers and 3.0 micrometers, taking into consideration the breakdown voltage design of the semiconductor device and the short-circuit withstand capability described later. When the offset distance (hx) falls below 0.1 micrometers, the electric field leaking from the lower end of the side surface (S) extends to the matching interface (X) and gate insulating film (Ox), and the stacking fault density, as described later, increases, degrading the long-term reliability of the semiconductor device. On the other hand, increasing the offset distance (hx) reduces the stacking fault density and also improves short-circuit withstand capability, but increases the resistance component during current flow. Therefore, it is even more desirable to keep the offset distance (hx) in the range of 1.0 to 1.5 micrometers.

[0029] [Improved Short-Circuit Withstand capability] The structure of the present invention has extremely high short-circuit withstand capability. The first reason for this is that, as shown in the cross-sectional view in Figure 3, fine JFET regions can be placed in the gaps between trenches and columnar structures, and in high drain voltage applied conditions such as load short circuit, the depletion layer expanding from the electric field relaxation region (B) quickly narrows the JFET region.

[0030] Secondly, the conduction band offset of 0.7 eV or more that occurs at the matched interface (X) located in the middle of the trench or columnar structure acts as a current limiting barrier to suppress excessive carrier acceleration when a high electric field is applied. This is a robustness unique to heterostructures that cannot be obtained in SiC semiconductor devices consisting of a single crystal structure.

[0031] Thirdly, because the hexagonal SiC layer (Eh), which has a relatively wide band gap and relatively low carrier mobility compared to cubic SiC, is located below the channel (Ch), excessive carrier inflow during a load short circuit is suppressed between the channel (Ch) and the electric field relaxation region (B). This makes it possible to keep the saturation current during a load short circuit low and extend the short-circuit withstand capability, which is the time until thermal breakdown of the semiconductor device. As described above, the present invention enables the manufacture of semiconductor devices with high robustness while employing a high-mobility channel, through the synergistic action of the current limiting mechanism of the physical properties of the matched interface (X) and the hexagonal SiC layer (Ec) and the electrostatic limiting by the electric field relaxation region (B).

[0032] [Suppression of stacking fault generation in cubic SiC layer] In this invention, by arranging channels (Ch) on the side surfaces (Sc) of cubic SiC portions of trenches and columnar structures, it is possible to expand the effective channel width, thereby reducing the area of ​​the cubic SiC layer (Ec) compared to conventional planar MOSFETs. As the area of ​​the cubic SiC layer (Ec) is reduced, the width (d) of the matching interface is also reduced, which relaxes the in-plane stress caused by the lattice mismatch between the lattice spacing of cubic SiC (0.3082 nanometers) and the lattice spacing of hexagonal SiC (for example, 0.3073 nanometers for 4H-SiC, a type of hexagonal SiC) in the direction parallel to the matching interface (X), thereby suppressing the generation and movement of Half-Loop dislocations within the cubic SiC layer. This is because as d is reduced, the contribution of elastic stress relaxation near the side surfaces (free surfaces) of trenches and columnar structures increases, and the driving force of Half-Loop dislocation movement is mechanically relaxed. As a result, the density of stacking faults remaining within the cubic SiC layer (Ec), which act as scattering factors for carriers crossing them, is reduced, and the inherently high channel mobility of cubic SiC is maintained. Figure 10 shows the dependence (calculated value) of stacking fault density (SFD) on the width of the matched interface (d) under the condition that the offset distance (hx) is kept constant at 1 micrometer. From the figure, it can be seen that when d is 3 micrometers or less, the stacking fault density (SFD) is 80 cm². -1It becomes clear that the following holds. Furthermore, the smaller the d is, the lower the SFD (the higher the carrier mobility) becomes. More preferably, d is set to 1 micrometer or less. In this case, the SFD can be suppressed to 10 cm -1 or less. As described above, the reduction of d means the reduction of the JFET region and also leads to the strengthening of the JFET effect.

[0033] In the present invention, a structure is provided in which the offset distance (hx) from the lower end of the side surface of a trench or a columnar structure to the section (Sx) of the alignment interface is 0.1 micrometer or more. This structure not only strengthens the JFET effect but also shows an effect in reducing the stacking fault density (SFD). For example, when the alignment interface (X) is located at the lower end of the side surface of a trench or a columnar structure (hx = 0 micrometer), the lower hexagonal SiC layer (Eh) is fixed as a part of a substrate with a much larger area compared to the cubic SiC layer (Ec) and has no free surface. In this case, the alignment interface (X) is constrained by the crystal lattice of the hexagonal SiC layer (Eh), and compressive stress concentrates in the nearby cubic SiC layer (Ec), promoting the generation and movement of half-loop dislocations (i.e., the generation of stacking faults). However, if the section (Sx) of the alignment interface is arranged in the "middle part" of the side surface (S) as in the present invention, a free surface corresponding to the offset distance (hx) is provided on the side surface (Sh) of the hexagonal SiC part, so that the stress distribution is also shared on the hexagonal SiC layer (Eh) side, suppressing the generation and expansion of stacking faults in the cubic SiC layer (Ec). FIG. 11 shows the change (calculated value) of the stacking fault density (SFD) with respect to the offset distance (hx) when the width (d) of the alignment interface is fixed at 1 micrometer. As shown in FIG. 11, when the offset distance (hx) is 0.1 micrometer or more, the SFD becomes 100 cm -1 or less, and a tendency is shown that the SFD decreases as the offset distance (hx) increases. More preferably, the offset distance (hx) is 0.5 micrometer or more, and the SFD at that time is the lower limit value of 10 cm -1 and the scattering of carriers due to stacking faults can be ignored.

[0034] [Effect of improving vertical mobility due to lattice strain] In this invention, it is possible to actively utilize the elastic strain originating from the crystal lattice mismatch between the cubic SiC layer (Ec) and the hexagonal SiC layer (Eh) to improve carrier transport properties. That is, with the generation and suppression of motion of the aforementioned Half-Loop dislocations, compressive stress remains in the cubic SiC layer (Ec) in a direction parallel to the matching interface (X). The elastic deformation at this time is based on Poisson's ratio and is perpendicular to the matching interface (X). <111> This generates tensile strain in the direction. This vertical tensile strain releases the degeneracy of the six equivalent energy valleys in the conduction band of the cubic SiC electronic structure. <111> This relatively lowers the potential of energy valleys with their principal axes in the direction. As a result, intervalley scattering is suppressed, and the potential of the energy valleys perpendicular to the matching interface (X) is reduced. <111> For electrons traveling in the direction (direction), this results in a reduction of effective mass of approximately 10% to 20% compared to a stress-free state without lattice distortion. This means that the channel resistance is reduced by approximately 10% to 20%. In the hexagonal columnar structure or dodecagonal columnar structure of the present invention (Figures 5, 6, 7, and 8), channels (Ch) are formed on the side perpendicular to the matching interface (X), and electrons travel in the vertical direction ( <111> When transporting in a particular direction, in addition to the anisotropy of mobility (orientation dependence) caused by the crystal orientation mentioned above, the mobility-enhancing effect (strained SiC effect) brought about by elastic strain originating from crystal lattice mismatch comes into play, enabling the realization of extremely low channel resistance. This can be considered a structural advantage unique to the present invention, which suppresses the generation and movement of Half-Loop dislocations at high-quality matching interfaces (X) while providing channels in fine trenches and on the sides (S) of columnar structures.

[0035] [Improved Long-Term Reliability] According to the present invention, by optimizing the concentration distribution of first-conductivity impurities in the hexagonal SiC layer (Eh) at the bottom of the trench or columnar structure, the concentration of electric fields near the gate insulating film in the off state can be effectively mitigated, thereby improving the long-term reliability of the semiconductor device. Furthermore, by dispersing the internal electric field and suppressing the saturation current during transient high-voltage application conditions such as load short circuits, it is possible to further improve the short-circuit withstand capability due to thermal breakdown. This makes it possible to provide a high-performance semiconductor device that achieves both high voltage resistance and robustness.

[0036] Furthermore, this configuration makes it possible to create a vertical impurity concentration gradient on the cubic SiC portion (Sc) of the trench or columnar structure side surface, thereby mitigating localized electric field concentration in the gate insulating film by homogenizing the electric field distribution in the depth direction in the channel region. This makes it possible to suppress short-channel effects and stabilize the threshold voltage while maintaining high channel mobility. As a result, a three-dimensional semiconductor device with low on-resistance, high reliability, and suitability for miniaturization can be realized.

[0037] Furthermore, the addition of impurities to the SiC crystal lattice can also lead to intentionally altering the lattice spacing. For example, in Patent Document 5, a tunnel-doped region (Dt) is formed by adding a high concentration of donor impurities (nitrogen and phosphorus) near the matching interface (X), but the nitrogen concentration added to the cubic SiC layer (Ec) is directed toward the matching interface (X) at 1 × 10⁻¹⁰. 21 cm -3 If the concentration is gradually increased until it reaches a certain level, the lattice spacing of the cubic SiC in contact with the matching interface (X) will decrease by 0.2%. On the other hand, if the phosphorus concentration added to the hexagonal SiC layer (Eh) is directed toward the matching interface (X) side, it will decrease by 1 × 10⁻¹⁰. 21 cm -3 If the nitrogen concentration is gradually increased to a certain level, the lattice spacing of the hexagonal SiC in contact with the matching interface (X) expands by 0.1%. As a result, the 0.3% lattice mismatch at the matching interface (X) is eliminated, and the motion of Half-Loop dislocations, which cause stacking fault expansion, is suppressed. On the other hand, although the concentration of elastic stress near the matching interface (X) is suppressed, the aforementioned "strained SiC effect" becomes dispersed and manifests over a wide area within the 3C-SiC layer (Ec) with a nitrogen concentration gradient.

[0038] [Measures to address current barriers at matching interfaces] In the manufacturing method provided by the present invention, regardless of whether the structure is trench-type or columnar, the cross section (Sx) of the matching interface is inevitably exposed. Therefore, by selective ion implantation into the cross section (Sx) of the matching interface, it is possible to provide a function similar to that of the tunnel-doped region described in Patent Document 5. [Modes for carrying out the invention]

[0039] The following describes embodiments of the semiconductor device provided by the invention. [Embodiment 1] (Transverse Channel MOSFET Structure) In this embodiment, electrons are transported in a direction parallel to the matching interface (X) in an n-channel MOSFET (hereinafter referred to as the "transverse channel" in this specification), with the first conduction type being n-type and the second conduction type being p-type. Furthermore, all electrodes (source electrode, gate electrode, drain electrode) are formed on the surface of the SiC laminate.

[0040] (SiC Laminate Manufacturing Process) In realizing the semiconductor device structure according to the present invention, the specific means for heteroepitaxial growth of a cubic SiC layer (referred to as a "3C-SiC layer" in this embodiment) on a hexagonal SiC layer via a matching interface are extremely important. For this reason, in this embodiment, the method for heteroepitaxial growth of the 3C-SiC layer (Ec) will be described with reference to Figure 12. As shown in Figure 12(a), a single-crystal hexagonal SiC wafer is used as the substrate (U) for heteroepitaxial growth. Hexagonal SiC includes 8H-SiC, 6H-SiC, and 4H-SiC, which have different stacking orders of crystal lattices, but it is desirable to select 4H-SiC, which has the widest band gap, as a power semiconductor material. In this case, it is desirable that the surface of the 4H-SiC is tilted in a specific direction from the (0001) plane, which is the closest packed plane of the crystal lattice, and the tilt angle (θ) is preferably between 1 degree and 10 degrees. In particular, commercially available single-crystal 4H-SiC wafers can be used if the tilt direction is set to the [11-20] orientation and the tilt angle (θ) is set to 4 degrees.

[0041] As shown in Figure 12(b), a 4H-SiC layer (Eh) is pre-formed on the surface of the substrate (U) by homoepitaxial growth. For example, in the case of a voltage-driven semiconductor device where the current path during conduction is perpendicular to the substrate surface, the above 4H-SiC layer (Eh) can be used as a drift region, and the concentration and film thickness of the 4H-SiC layer (Eh) can be determined according to the required breakdown voltage and formed accordingly. However, in this embodiment, since the current path is horizontal to the matching interface (X), it is not necessary to strictly determine the film thickness according to the breakdown voltage, and the donor concentration to be added is 1 × 10⁻⁶. 15 cm -3 From 1 x 10 16 cm -3 It should be within that range.

[0042] A 3C-SiC layer (Ec) is formed on the surface of the 4H-SiC layer (Eh) via a matching interface (X). By forming a matching interface (X) where the close-packed surface of the 3C-SiC layer (Ec) and the close-packed surface of the 4H-SiC layer (Eh) are in contact, the Double Positioning Boundary (DPB) within the 3C-SiC layer (Ec) is completely eliminated. Methods for heteroepitaxially growing a 3C-SiC layer (Ec) on a 4H-SiC layer (Eh) via a matching interface (X) are already known from Patent Documents 3 and 4, but these methods require expanding the width of the basal surface terrace beyond a critical value (Wc) determined by the epitaxial growth temperature in order to induce spontaneous nucleation of 3C-SiC. To avoid such a basal surface terrace expansion step, the present invention uses the following method. First, prior to epitaxial growth, multiple grooves (Gv) are provided on the surface of the 4H-SiC layer (Eh) as shown in Figure 12(c). These grooves (Gv), similar to those in Patent Document 3, are intended to locally inhibit step-controlled epitaxy of 4H-SiC and need to be provided parallel to a specific crystal orientation. However, since spontaneous nucleation of 3C-SiC is not required, the spacing (Wt) between adjacent grooves may be less than or equal to the critical value (Wc), and the ends of the grooves (Gv) do not necessarily have to include protrusions like those in Patent Document 4. Therefore, the grooves (Gv) can be arranged according to the required semiconductor device shape. Furthermore, the width (Wg) and depth of the grooves can be determined depending on the required width and spacing of the basal plane terraces. For example, if the width of the basal plane terrace is 3 micrometers and the spacing between adjacent basal plane terraces is 0.5 micrometers, then the width (Wg) and depth of the grooves should each be 0.5 micrometers.

[0043] Next, as shown in Figure 12(d), homoepitaxial growth of 4H-SiC is performed. The conditions for this can be the same as the step-controlled epitaxy conditions for 4H-SiC commonly used by those skilled in the art. The thickness of the 4H-SiC to be grown should be greater than the value obtained by dividing the distance between adjacent grooves (Wt) by the tangent of the inclination angle (θ), so that the entire area between adjacent grooves (Gv) is covered by the 4H-SiC (0001) surface. For example, if Wt is 10 micrometers and θ is 4 degrees, a 4H-SiC layer (Eh) with a thickness of 0.7 micrometers or more should be epitaxially grown. Note that during the above epitaxial growth, 1 × 10⁻¹⁶ nitrogen, which is a donor impurity, should be added. 15 cm -3 From 1 x 10 16 cm -3 It should be added at concentrations within this range.

[0044] In the above process, some kind of close-packed structure is exposed on the 4H-SiC(0001) surface. However, unless this structure is a specific cubic close-packed structure, it is not possible to obtain single-domain cubic SiC in the vertical epitaxial process described later. Therefore, in the surface modification treatment following the homoepitaxial growth process described above, the surface of the 4H-SiC layer (Ec) is modified to a specific cubic close-packed structure by applying the surface treatment described in Patent Document 6.

[0045] After the entire surface of the 4H-SiC layer (Eh) is covered with a cubic close-packed structure by the surface modification treatment described above, if atomic layer epitaxy as described in Patent Document 7 is used, as shown in Figure 12(e), a single-domain 3C-SiC layer (Ec) consisting of the same structure as the cubic close-packed structure exposed on the surface of the 4H-SiC layer (Eh) undergoes heteroepitaxial growth perpendicular to the close-packed plane without undergoing spontaneous nucleation (vertical epitaxial process). In carrying out this vertical epitaxial process, the growth temperature is set to a specific temperature between 1000°C and 1100°C, and chloride silane gas, hydrogen gas, and hydrocarbon gas are supplied intermittently. Dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), and tetrachlorosilane (SiCl4) can be used as the chloride silane gas, but by using dichlorosilane, which is a gas at room temperature, precise adjustment of the supply amount is possible. Furthermore, while methane (CH4), ethane (C2H6), propane (C3H8), and acetylene (C2H2) can be used as hydrocarbon gases, using acetylene (C2H2), which has a strong triple bond between carbon atoms, suppresses thermal decomposition in the gas phase and enables highly controllable epitaxial growth.

[0046] Furthermore, when adding donor impurities to the 3C-SiC layer (Ec) in the vertical epitaxial process, nitrogen (N) or ammonia (NH3) should be added in synchronization with the supply of hydrocarbon gas, according to the required donor concentration. Simultaneously supplying phosphine (PH3) in synchronization with the supply of silane chloride gas can further increase the donor concentration. However, in this embodiment, since n channels are formed on the side surface (Sc) of the 3C-SiC portion, acceptor impurities are added. In this case, trimethylaluminum (TMA) or aluminum chloride (AlCl3) vapor should be supplied in synchronization with the supply of silane chloride gas, according to the required acceptor impurity concentration. The acceptor impurity concentration to be added here is 5 × 10⁻⁶. 15 cm -3 From 1 x 10 17 cm -3 Within that range, you should select one while taking into account the gate threshold voltage.

[0047] In the aforementioned vertical epitaxial process, it is necessary to achieve high uniformity and precise epitaxial growth at the atomic layer level. This requires intentionally separating the timing of the thermal decomposition of silane chloride into SiCl and its adsorption onto the wafer surface from the timing of the adsorbed SiCl molecules being reduced and carbonized to produce SiC. The specific conditions for this can be those described in Patent Document 7. Through the above process, a 3C-SiC layer (Ec) is heteroepitaxially grown on a 4H-SiC layer (Eh) via a matching interface (X).

[0048] In this vertical epitaxial process, the thickness of the 3C-SiC layer (Ec) is a key consideration. In the process described later, lateral channels are formed on the side surface (Sc) of the 3C-SiC portion. To expand the channel width and reduce channel resistance, it becomes necessary to increase the thickness of the 3C-SiC layer (Ec). However, as the thickness of the 3C-SiC layer (Ec) increases, the time required for the vertical epitaxial process increases, and the internal stress near the matching interface (X) increases, leading to an increase in stacking fault density. Therefore, it is desirable for the channel width to be between 0.5 micrometers and 1 micrometer. Consequently, it is more desirable for the thickness of the 3C-SiC layer (Ec) grown in the vertical epitaxial process to be in the range of greater than 0.5 micrometers and less than or equal to 1.5 micrometers.

[0049] Furthermore, spontaneous polarization exists at the matching interface (X), and the resulting depletion layer acts as a barrier to electrons, so electrons transported within the 3C-SiC layer (Ec) do not leak to the 4H-SiC layer (Eh). In addition, the built-in potential formed between the p-type 3C-SiC layer (Ec) and the n-type 4H-SiC layer (Eh) also acts as a barrier to electrons. This is one of the advantages of the present invention in manufacturing lateral channel MOSFETs.

[0050] (Manufacturing Process for Lateral Channel MOSFETs) The manufacturing method for lateral channel MOSFETs will be explained using the process cross-sectional diagram shown in Figure 13. In order to provide a source contact region (Ds) and a drain contact region (Dr) at the location where the source electrode (Source) and drain electrode (Drain) will come into contact in the process described later, a mask film (Re) with openings for the source and drain portions is formed using photolithography technology, as shown in Figure 13(a). Next, using the mask film (Re) as a shield, the source contact region (Ds) and drain contact region (Dr) are formed by implanting ions of donor-type impurities such as nitrogen and phosphorus into a part of the surface vicinity of the 3C-SiC layer (Ec). The concentration of donor impurities to be added here is 10, as it is necessary to sufficiently reduce the contact resistance between the source electrode and the drain electrode. 19 cm -3 It is desirable to have the above, and more preferably 10 21 cm -3 This will further reduce contact resistance.

[0051] Next, as shown in Figure 13(b), a drift region (Dl) is formed. In this step, a mask film (Re) with an opening corresponding to the drift region (Dl) is formed using photolithography technology, and donor impurities such as nitrogen and phosphorus are added to the 3C-SiC layer (Ec) by ion implantation. The concentration of the donor impurities added in this step is set to exceed the acceptor concentration that was previously added to the 3C-SiC layer (Ec), and 10 16 cm -3 More than or equal to 10 18 cm -3 The following range should be determined while considering the width of the depletion layer formed within the drift region. Furthermore, ion implantation should preferably be performed at 500°C to improve the activation rate of donor impurities and reduce damage to the crystal lattice of the 3C-SiC (Ec) layer.

[0052] Next, the mask film (Re) is removed, and heat treatment is performed to activate the impurity ions. The purpose of this heat treatment is to restore the SiC crystal lattice damaged by ion irradiation and to lower the resistance of the region where impurity ions are added. For example, by performing heat treatment at 1650°C for 10 minutes, it is possible to reduce the resistivity of the source contact region (Ds) and drain contact region (Dr) to 20 mohm·cm or less.

[0053] Next, as shown in the plan view in Figure 14(a), if a trench parallel to the tilt direction of the 4H-SiC wafer (the [11-20] direction in this embodiment) is formed between the source contact region (Ds) and the drift region (Dl), a 3C-SiC partial side surface (Sc) consisting of a {1-10} plane is exposed on the side surface of the trench. Alternatively, as shown in the plan view in Figure 14(b), if a trench deflected by 30 degrees with respect to the [11-20] direction of the 4H-SiC wafer is formed between the source contact region (Ds) and the drift region (Dl), a 3C-SiC partial side surface (Sc) consisting of a {11-2} plane is exposed on the side surface of the trench. However, the depth of the trench formed here must be such that the cross section (Sx) of the matching interface is exposed on the side surface of the trench, while taking into account the offset distance (hx) described later.

[0054] Next, the manufacturing process flow in the cross section between A and A' shown in the plan view of Figure 14 will be explained using Figure 15. For the trench formation described above, general-purpose photolithography and dry etching techniques can be used, and as shown in Figure 15(a), the dry etching time is adjusted so that the offset distance (hx) from the lower end of the trench side surface to the cross section (Sx) of the matching interface is between 0.1 micrometers and 3 micrometers.

[0055] Furthermore, to prevent channel formation on the 4H-SiC side surface (Sh), a field film (Of) is deposited on the 4H-SiC surface (Fh) exposed at the lower end of the trench side surface (S), as shown in Figure 15(b). A SiO2 film that can be deposited by CVD or sputtering can be used as the field film (Of), and if its thickness is greater than or equal to the offset distance (hx), channel formation on surfaces other than the 3C-SiC side surface (Sc) can be avoided. Note that this process requires not only the deposition of SiO2 on the entire SiC laminate, but also the removal of SiO2 deposited on the 3C-SiC surface (Fc) and the 3C-SiC side surface (Sc). However, since general planarization and downflow etching (isotropic dry etching) techniques can be used, a detailed explanation is omitted in this embodiment.

[0056] Next, as shown in Figure 15(c), a gate insulating film (Ox) is formed to cover the 3C-SiC partial side surface (Sc) and the 3C-SiC surface (Fc). This gate insulating film (Ox) can be formed using methods such as thermal oxidation, CVD, or ALD, and the thickness of the gate insulating film can be controlled by the respective processing time. The thickness of the gate insulating film can be selected within the range of 30 to 200 nanometers, taking into account the gate capacitance and gate threshold voltage. For example, a 40-nanometer-thick SiO2 film can be obtained as the gate insulating film (Ox) by a wet oxidation method at 1100°C for 60 minutes. Since the 3C-SiC partial side surface (Sc) is a non-polar surface, applying the aforementioned surface modification treatment prior to the formation of the gate insulating film (Ox) results in a further improvement in channel mobility due to the polar surface orientation effect similar to that described in Patent Document 6.

[0057] After forming the gate insulating film (Ox), a Poly-Si film is formed as the gate electrode (G) to fill the trench. As shown in Figure 15(d), the effects of the present invention can be obtained even if the gate electrode (G) is in a structure that is only close to the side surface (Sc) of the 3C-SiC portion (side channel type), but by making it a structure that is also close to the 3C-SiC surface (Fc) as shown in Figure 15(e) (three-sided channel type), the channel width is expanded, resulting in a further reduction in channel resistance. If the surface of the Poly-Si film that is the gate electrode (G) is very uneven due to the influence of the trench, it may be planarized by CMP or other methods.

[0058] Next, the manufacturing process flow after gate electrode (G) formation will be explained using the plan view in Figure 16. After the formation of the Poly-Si film, a resist mask is formed to limit the gate electrode formation area using a commonly used photolithography technique. Subsequently, the unnecessary parts of the Poly-Si film are etched away by a dry etching method, and the gate electrode (G) is formed between the source contact region (Ds) and the drift region (Dl), as shown in Figure 16(a). Using a sputtering process following photolithography, the source electrode (Source) and drain electrode (Drain), respectively, are brought into contact with the source contact region (Ds) and drain contact region (Dr), as shown in Figure 16(b), making it possible to manufacture a trench MOSFET with a lateral channel.

[0059] (Comparison of Calculated Lateral Channel Resistances) Figure 17 shows the results of calculating the channel resistance (Rch_sp) of a side channel type MOSFET consisting of a {11-2} plane manufactured by the semiconductor device manufacturing process described above, using the width of the matching interface (d) and the width of the trench gap (w) as parameters. However, the polar plane orientation effect is not considered, and Rch_sp is shown as a value normalized by the channel resistance of a planar type MOSFET on a 3C-SiC surface (Fc) of the same footprint. That is, if Rch_sp is less than 1, superiority over conventional planar type MOSFETs on 3C-SiC becomes apparent. However, the channel width of each 3C-SiC side (Sc) is assumed to be 0.5 micrometers. As shown in Figure 17, Rch_sp shows a monotonically decreasing trend as d and w decrease, but when w is set to 1 micrometer, a lower channel resistance than that of a planar type MOSFET on a 3C-SiC surface can be achieved for d of 1.16 micrometers or less. Furthermore, if both w and d are set to 0.6 micrometers, the channel resistance becomes 0.57 times that of a 3C-SiC surface planar MOSFET. This is an advantage brought about by the effective channel width expansion according to the present invention.

[0060] On the other hand, Figure 18 shows the channel resistance (Rch_sp) of a side-channel MOSFET consisting of {1-10} planes, calculated using the width of the matching interface (d) and the width of the trench gap (w) as parameters. However, Rch_sp is shown as a value normalized to the channel resistance of a planar type on a 3C-SiC surface (Fc) with the same footprint. Similar to the side-channel MOSFET consisting of {11-2} planes, Rch_sp shows a monotonically decreasing trend as d and w decrease, but a value lower than the channel resistance of a planar type MOSFET on a 3C-SiC surface is achieved for d of 1.75 micrometers or less. Furthermore, when compared with the same d and w, the Rch_sp is more than 20% lower than that of the side-channel MOSFET consisting of {11-2} planes, clearly demonstrating the channel resistance reduction effect of the present invention. This result shows the advantage of the synergistic effect of the effective channel width expansion according to the present invention and the reduction effect of the effective carrier mass that occurs in specific crystal orientations.

[0061] Furthermore, Figure 19 shows the channel resistance (Rch_sp) of the three-sided channel MOSFET shown in Figure 15(e), calculated using the trench and columnar structure width (d) and trench width (w) as parameters. However, the trench sides are {1-10} planes. Also, Rch_sp is shown as a value normalized to the channel resistance of a planar type MOSFET on a 3C-SiC surface (Fc) with the same footprint. Similar to the side-channel MOSFET consisting of (1-10) planes, Rch_sp tends to decrease with decreasing d and w, but it is more than 41% lower when compared to the {1-10} side-channel MOSFET with the same d and w. Also, if d and w are 0.6 micrometers, the channel resistance becomes 0.37 times that of the planar type MOSFET on a 3C-SiC surface. This result, similar to the {1-10} side-channel MOSFET, shows a synergistic effect of increasing the effective channel width along with reducing the effective carrier mass. Furthermore, it is clear that the reduction in channel resistance is further enhanced when the polar plane orientation effect is also taken into account.

[0062] [Embodiment 2] (Longitudinal Channel MOSFET Structure) In this embodiment, electrons are transported perpendicular to the matching interface (X) in an n-channel MOSFET (hereinafter referred to as the "longitudinal channel" in this specification), with the first conduction type being n-type and the second conduction type being p-type. The source electrode and gate electrode are formed on the surface of the SiC laminate, and the drain electrode is formed on the back side of the SiC laminate.

[0063] (SiC Laminate Manufacturing Process) In order to form a practical longitudinal channel, it is necessary to expand the effective channel width by an assembly of MOSFET cells consisting of minute trenches or columnar structures, and it is necessary to subdivide the heteroepitaxially grown cubic SiC layer (Ec) to expose many sides. Therefore, in this embodiment, a means for stacking single-domain 3C-SiC layers in a minute region with a width of less than 3 micrometers is shown using the manufacturing process flow cross-sectional diagram of Figure 20.

[0064] Similar to Embodiment 1, in this embodiment, as shown in Figure 20(a), a single-crystal 4H-SiC wafer with a surface tilt direction of [11-20] and a tilt angle (θ) of 4 degrees is used as the substrate (U). However, since the output current of this MOSFET penetrates to the back side of the substrate, it is desirable that the resistivity of the 4H-SiC wafer be as low as possible, and one with a resistivity of 20 mohms·cm or less should be selected.

[0065] As shown in Figure 20(b), a 4H-SiC layer (Eh) is pre-formed on the surface of the substrate (U) by step-controlled epitaxy. In this embodiment, since the above 4H-SiC layer (Eh) is used as a drift region, it is necessary to determine the concentration of added impurities and the film thickness according to the required breakdown voltage. For example, when the breakdown voltage is 1200V, the donor impurity concentration to be added is 1 × 10⁻⁶ 16 cm -2 The film thickness should be approximately 11 micrometers. Nitrogen is preferable as the donor impurity.

[0066] A single-domain 3C-SiC layer (Ec) is formed on the surface of the 4H-SiC layer (Eh) via a matching interface (X). Similar to Embodiment 1, this embodiment also uses the following steps. First, prior to step-controlled epitaxy, multiple grooves (Gv) are provided on the surface of the 4H-SiC layer (Eh) as shown in Figure 20(c). These grooves (Gv), similar to those in Patent Document 3, are intended to locally inhibit the step-controlled epitaxy of the 4H-SiC, and the grooves (Gv) should be arranged according to the required MOSFET cell arrangement. The width (Wg) and depth of the grooves can be determined depending on the required width and spacing of the basal surface terraces. For example, if the width of the basal surface terrace is 3 micrometers and the spacing between adjacent basal surface terraces is 0.5 micrometers, the width (Wg) and depth of the grooves should each be 0.5 micrometers.

[0067] Next, as shown in Figure 20(d), epitaxial growth of 4H-SiC is performed. The conditions for this can be the step-controlled epitaxy conditions for 4H-SiC commonly used by those skilled in the art. The thickness of the 4H-SiC to be grown should be greater than the value obtained by dividing the distance between adjacent grooves (Wt) by the tangent of the inclination angle (θ), so that the entire area between adjacent grooves (Gv) is covered by the 4H-SiC (0001) surface. For example, if Wt is 10 micrometers and θ is 4 degrees, then a 4H-SiC layer with a thickness of 0.7 micrometers or more should be epitaxially grown. Note that during epitaxial growth, 1 × 10⁻¹⁶ nitrogen, a donor impurity, should be added. 16 cm -3 It should be added at a certain concentration.

[0068] Next, as shown in Figure 20(e), a selective epitaxial mask (Rx) made of silicon oxide (SiO2) is provided on the surface of the 4H-SiC layer (Eh). The thickness (tx) of the selective epitaxial mask can be determined according to the required thickness (tc) of the 3C-SiC layer (Ec). For example, if tc is 2 micrometers, then tx should be 2 micrometers or more. The method for forming the selective epitaxial mask (Rx) can be appropriately selected from sputtering, CVD, thermal oxidation, and vapor deposition. However, considering the degree of freedom in setting the target tx and in-plane uniformity, it is desirable to use a reduced-pressure CVD method using silane and oxygen, or TEOS.

[0069] Next, as shown in Figure 20(f), an opening is created in the selective epimask (Rx) using photolithography and dry etching techniques, partially exposing the surface (Fh) of the 4H-SiC layer. The shape of the opening can be the planar shape of the required channel region (such as the hexagonal prism structure shown in Figures 6 and 7, or the dodecagonal prism structure shown in Figure 8). Therefore, the width of the opening in the selective epimask (Rx) corresponds to d, and the width of the portion covered by the selective epimask (Rx) corresponds to w.

[0070] In this process, some kind of close-packed structure is exposed on the 4H-SiC surface (Fh), but unless this structure is a specific cubic close-packed structure, single-domain cubic SiC cannot be obtained. Therefore, a specific cubic close-packed structure is exposed on the 4H-SiC surface (Fc) by applying the surface modification treatment described in Patent Document 6.

[0071] Next, by using atomic layer epitaxy as described in Patent Document 7, it becomes possible to heteroepitaxially grow a single-domain 3C-SiC layer (Ec) perpendicular to the matching interface (X) without undergoing spontaneous nucleation. In carrying out this perpendicular epitaxial process, the growth temperature is set to a specific temperature between 1000°C and 1100°C, and chloride silane gas, hydrogen gas, and hydrocarbon gas are supplied intermittently. Dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), and tetrachlorosilane (SiCl4) can be used as the chloride silane gas, but by using dichlorosilane, which is a gas at room temperature, precise adjustment of the supply amount is possible. Furthermore, while methane (CH4), ethane (C2H6), propane (C3H8), and acetylene (C2H2) can be used as hydrocarbon gases, using acetylene (C2H2), which has a strong triple bond between carbon atoms, suppresses thermal decomposition in the gas phase and enables highly controllable atomic layer epitaxy. The optimal growth temperature when using dichlorosilane and acetylene is 1050°C.

[0072] In the vertical epitaxial process described above, in order to achieve precise epitaxial growth at the atomic layer level, the timing of the thermal decomposition of dichlorosilane into SiCl and its adsorption onto the wafer surface is intentionally separated from the timing of the adsorbed SiCl molecules being reduced and carbonized by acetylene to produce SiC. The specific conditions for this can be those described in Patent Document 7. One cycle consists of supplying dichlorosilane and then supplying acetylene, and by repeating the SiC growth at a thickness of 0.75 nanometers per cycle, a 3C-SiC layer (Ec) of the required thickness can be obtained.

[0073] Furthermore, since the SiCl molecules produced by the thermal decomposition of dichlorosilane do not adsorb onto the selective epitaxial mask (Rx) made of SiO2, the 3C-SiC layer (Ec) grows only at the openings of the selective epitaxial mask (Rx). By repeating the gas supply for 40 to 107 cycles in this vertical epitaxial process, a 3C-SiC layer (Ec) with a thickness of 30 to 80 nanometers is grown, as shown in Figure 20(g).

[0074] Subsequently, to form tunnel-doped regions (Dt), donor impurities are ion-implanted near the matching interface (X) while utilizing a selective epimask (Rx) as a shielding film. Nitrogen or phosphorus can be selected as the donor impurities to be implanted into each region. Since nitrogen replaces C positions in the SiC crystal lattice and phosphorus replaces Si positions, implanting both into the same region allows for a solid solubility exceeding 5 × 10⁻¹⁰ of each impurity. 19 cm -3 The above donor concentrations can be achieved. Furthermore, to improve the activation rate of donor impurities and avoid destruction of the SiC crystal lattice, it is desirable to perform nitrogen and phosphorus ion implantation at 500°C. Also, since the region to be implanted with donor impurities is approximately 0.1 micrometers deep, the acceleration energy for nitrogen ions should be selected within the range of 60 keV or less, and the acceleration energy for phosphorus ions within the range of 120 keV or less. The sum of the doses of each ion should be 5 × 10⁻⁶. 14 cm -2 As a result of the above, as shown in Figure 20(h), the region including the matching interface (X) is 5 × 10 20 cm -3 A tunnel-doped region (Dt) with a concentration exceeding [a certain value] can be formed.

[0075] Further vertical epitaxial processing is carried out to grow a 3C-SiC layer (Ec) of the required thickness, as shown in Figure 20(i). Subsequently, by removing the selective epitaxial mask (Rx) by wet etching, a subdivided 3C-SiC layer (Ec) can be obtained on the 4H-SiC layer (Eh), as shown in Figure 20(j).

[0076] Next, the entire surface of the SiC laminate is dry-etched to recess the 4H-SiC surface (Fh) relative to the matching interface (X), as shown in Figure 20(k). The distance between the matching interface (X) and the 4H-SiC surface (Fh) created by this process corresponds to the offset distance (hx). For this dry etching, high-frequency reactive etching or inductively coupled plasma reactive etching can be used in an atmosphere of mixed fluorine-based gas such as CF4 and oxygen gas. By keeping the pressure below 20 Pa, the etching rate can be increased, allowing for selective etching of the 4H-SiC surface (Fh) while suppressing damage to trenches and the sides of columnar structures.

[0077] Furthermore, as shown in Figure 20(l), an electric field relaxation region (B) is created on the 4H-SiC surface (Fh) by ion implanting acceptor impurities using a self-aligning method with a 3C-SiC layer (Ec) as a shield. Aluminum or boron is used as the acceptor impurity in this process. However, since boron has a low activation rate in the activation process described later and may diffuse outward, it is more desirable to use aluminum as the acceptor impurity. A BOX profile is formed near the 4H-SiC surface (Fh) by multi-stage implantation with appropriately selected dose and acceleration energy during ion implantation. For example, if the thickness of the electric field relaxation layer (B) is 0.5 micrometers, the maximum ion acceleration energy should be 350 keV. It is desirable to perform this ion implantation process at 700°C or higher to avoid damaging the crystal lattice of the 4H-SiC layer (Eh) due to ion implantation and to maintain a high activation rate of the implanted aluminum.

[0078] Next, a heat treatment is performed to activate the impurity ions implanted in the previous step. The purpose of this heat treatment is to restore the SiC crystal lattice damaged by ion irradiation and to lower the resistance of the regions where impurity ions are added. For example, a heat treatment at 1650°C for 10 minutes activates the impurities added to the tunnel-doped region (Dt) and the field-relaxed region (B).

[0079] In the above process flow, the film thickness (tc) of the 3C-SiC layer (Ec) to be grown in the vertical epitaxial process should be determined considering the amount of dry etching required to create the offset distance (hx). For example, if the channel width provided on the side surface (Sc) of the 3C-SiC portion is 0.5 micrometers and the offset distance (hx) is 0.5 micrometers, then tc should be 1.0 micrometer or more, and therefore the thickness tx of the selective epitaxial mask (Rx) should be 1.2 micrometers or more.

[0080] (Manufacturing process for longitudinal channel MOSFETs) Next, the manufacturing process for longitudinal channel MOSFETs, which uses the SiC laminate obtained in the above process to form channels on the 3C-SiC side surface (Sc) and transport carriers perpendicular to the matching interface (X), will be explained using the process flow cross-sectional diagram in Figure 21.

[0081] Figure 21(a) shows a cross-section of a SiC laminate after the vertical epitaxial process, in which tunnel-doped regions (Dt) and electric field relaxation regions (B) are formed. The 3C-SiC partial side surface (Sc) and 4H-SiC partial side surface (Sh) are exposed on the sides of the trenches and columnar structures. Next, as shown in Figure 21(b), a field film (Of) is embedded in the openings of the 3C-SiC layer (Eh). A CVD-formed SiO2 film can be used as the field film (Of). The thickness of the field film (Of) is set to be greater than or equal to the offset distance (hx). This field film (Of) covers the 4H-SiC partial side surface (Sh), preventing channel formation other than in the 3C-SiC partial side surface (Sc). Furthermore, the electric field extending to the gate insulating film (Ox) formed in a later process is also relaxed, improving the long-term reliability of the MOSFET.

[0082] Next, as shown in Figure 21(c), a gate insulating film (Ox) is formed to cover the 3C-SiC partial side surface (Sc). This gate insulating film (Ox) can be formed using methods such as thermal oxidation, CVD, or ALD, and the thickness of the gate insulating film can be controlled by the respective processing time. The thickness of the gate insulating film (Ox) should be selected within the range of 30 to 200 nanometers, taking into account the gate capacitance and gate threshold voltage. For example, a 40-nanometer thick SiO2 film can be obtained by wet oxidation at 1100°C for 60 minutes. Since the 3C-SiC partial side surface (Sc) is a non-polar surface, applying a surface modification treatment prior to the formation of the gate insulating film (Ox) results in a further improvement in channel mobility due to the polar surface orientation effect similar to that described in Patent Document 6.

[0083] As shown in Figure 21(d), after forming the gate insulating film (Ox), a Poly-Si film, which is the gate electrode (G), is deposited so as to fill the openings in the 3C-SiC layer (Ec), thereby forming a MOS structure in which the gate electrode (G) is in close proximity to the side surface (Sc) of the 3C-SiC portion.

[0084] The subsequent steps are the same as the conventional trench-type MOSFET manufacturing process, so a detailed explanation will be omitted. The gate insulating film (Ox) is removed from the 3C-SiC surface (Fc) before the source electrode is deposited. Finally, a drain electrode is formed on the back surface of the substrate (U), allowing for the manufacture of trench-type or columnar MOSFETs.

[0085] (Comparison of Calculated Results of Vertical Channel Resistance) Figure 22 shows the calculation results of the dependence of the channel resistance (Rch_sp) on the width of the matching interface (d) in a vertical channel on the 3C-SiC partial side surface (Sc) of the {1-10} plane provided on the trench side surface. However, polar plane orientation effect and strained SiC effect are not considered, and Rch_sp is normalized to the channel resistance of a planar type MOSFET on a 3C-SiC surface of the same footprint. Also, the channel length formed perpendicular to the matching interface (X) is assumed to be 1 micrometer. As is clear from the figure, when d is 1.2 micrometers or less, Rch_sp is 1 or less. Furthermore, as d and w decrease, Rch_sp shows a monotonic decreasing trend, and when d and w are both 0.6 micrometers, Rch_sp is 0.55.Therefore, the effect of reducing channel resistance by increasing the effective channel width according to the present invention is clear. Furthermore, since the effective mass of electrons perpendicular to the matching interface (X) is similar even on the {11-2} plane, similar results can be obtained by forming longitudinal channels in the 3C-SiC partial side surface (Sc) consisting of the {11-2} plane.

[0086] Figure 23 shows the dependence of the channel resistance (Rch_sp) on the width (d) of the hexagonal prismatic structure in the longitudinal channel on the 3C-SiC partial side surface (Sc) of the {1-10} plane exposed on the side surface of the hexagonal prismatic structure in Figure 6. However, the channel length formed perpendicular to the matching interface (X) on the 3C-SiC partial side surface is assumed to be 1 micrometer, and Rch_sp is normalized by the channel resistance of a planar MOSFET on a 3C-SiC surface with the same footprint. As is clear from the figure, Rch_sp exhibits a minimum value when d and w are equal, and Rch_sp is 0.15 when both w and d are 1.0 micrometers. Furthermore, if both w and d are 0.5 micrometers, Rch_sp can be reduced to 0.055. This is a result of the effective channel width increase according to the present invention. Furthermore, since the effective mass of electrons perpendicular to the matching interface (X) is similar even on the {11-2} plane, the same results can be obtained by forming a longitudinal channel on the 3C-SiC partial side surface (Sc) consisting of the {11-2} plane shown in Figure 7.

[0087] Figure 24 shows the dependence of the channel resistance (Rch_sp) on the width (d) of the dodecagonal prism structure in a longitudinal channel provided on the 3C-SiC side surface (Sc) of a dodecagonal prism structure consisting of {1-10} and {11-2} planes. The channel length is assumed to be 1 micrometer, and Rch_sp is normalized by the channel resistance of a planar MOSFET on a 3C-SiC surface with the same footprint. As is clear from the figure, Rch_sp exhibits a minimum value when d and w are equal, and Rch_sp is 0.15 when both w and d are 1.0 micrometers. Furthermore, if both w and d are 0.5 micrometers, Rch_sp can be reduced to 0.055. This is a result of the effective channel width increase according to the present invention. It is clear that the channel resistance can be further reduced by the present invention if strain SiC effects and polar plane orientation effects, which are not considered in the above calculations, are also taken into account.

[0088] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the claims, not in the sense described above, and all modifications are intended to be in the sense and scope equivalent to the claims.

[0089] For example, the effects of the present invention apply not only to the MOSFETs shown in the embodiments, but also to all semiconductor devices such as JFETs and IGBTs, in which the carrier concentration transported through the channel changes depending on the voltage applied to the gate electrode. In particular, when manufacturing IGBTs, it is sufficient to add a second-conductivity impurity to a portion of the substrate (U) or the hexagonal SiC layer (Eh). Although the embodiments of this specification show the manufacturing method and channel mobility calculation results for n channels, a similar channel resistance reduction effect is also observed for holes traveling through p channels where the first conduction type is p-type and the second conduction type is n-type.

[0090] Furthermore, while the embodiments described herein show not only trenches but also hexagonal prismatic and dodecagonal prismatic structures as three-dimensional channel structures, the structure of the prismatic structure does not necessarily need to be axially symmetric perpendicular to the matching interface. Also, in a honeycomb structure where the portion corresponding to the prismatic structure becomes an opening, the same channel resistance reduction effect as in the embodiments described herein can be obtained if the diameter of the opening is the same as the width of the prismatic structure.

[0091] In the embodiments, the process for realizing the structure of the semiconductor device provided by the present invention has also been mentioned. However, the patterning process for limiting the impurity doping region, the gate insulating film formation process, the electrode formation process, the cleaning process, etc., are the same as in conventional semiconductor device manufacturing processes and can be carried out by those skilled in the art, so a detailed description in this specification has been omitted.

[0092] Furthermore, the term "perpendicular to the matching interface" as used herein does not mean a precise 90 degrees. Rather, considering the tolerances of the SiC substrate surface and the dimensional accuracy and shape variations during SiC processing, a variation of up to 6 degrees is permitted.

[0093] This specification uses Miller indices to indicate the plane orientation of SiC crystals. Ideally, when a Miller index is negative, a horizontal line (bar) should be placed above the corresponding number. However, since this is not possible, within the scope of this specification, a minus sign "-" is placed before the corresponding number to indicate a negative value.

[0094] The Miller indices indicating crystal orientations and crystal lattice planes shown in the descriptions and figures of this specification use, as necessary, combinations of three indices applicable to cubic SiC or combinations of four indices applicable to hexagonal SiC. For example, the {111} plane of cubic SiC and <111> The orientations correspond to the {0001} plane of hexagonal SiC and <0001> Corresponding to orientations, the {1-10} plane and <1-10> orientation of cubic SiC correspond to the {1-100} plane and <1-100> orientation of hexagonal SiC, respectively, and the {11-2} plane and <11-2> orientation of cubic SiC correspond to the {11-20} plane and <11-20> orientation of hexagonal SiC, respectively.

[0095] Furthermore, in the diagrams referenced in this specification, common symbols are used for parts that have the same function, regardless of differences in the structure or manufacturing process of the semiconductor devices. [Brief explanation of the drawing]

[0096] [Figure 1] Perspective view showing the trench structure formed in a SiC stack. [Figure 2] Cross-sectional view showing a trench structure formed in a SiC laminate. [Figure 3] Cross-sectional view of a side-channel type MOSFET provided in a trench structure formed in a SiC laminate. [Figure 4] Cross-sectional view of a three-sided channel MOSFET provided in a trench structure formed in a SiC laminate. [Figure 5] A cross-sectional view showing a hexagonal prismatic structure formed in a SiC laminate. [Figure 6] A plan view showing a SiC laminate having a hexagonal prismatic structure consisting of {1-10} faces. [Figure 7] A plan view showing a SiC laminate having a hexagonal prismatic structure consisting of {11-2} faces. [Figure 8] A plan view showing a SiC laminate having a dodecagonal prismatic structure consisting of {1-10} faces and {11-2} faces. [Figure 9] A figure showing the dependence of the pinch-off voltage (Vp) on the width (d) of a trench or columnar structure. [Figure 10] A figure showing the change in stacking fault density (SFD) with respect to the width (d) of a trench or columnar structure. [Figure 11] This figure shows the change in stacking fault density (SFD) with respect to the offset distance (hx) from the lower end of the trench side surface to the cross section of the matching interface in a SiC stack. [Figure 12] Cross-sectional view showing the manufacturing process flow of a SiC laminate. [Figure 13] Cross-sectional view showing the process flow for forming electrode contact regions and drift regions on the surface of a SiC laminate. [Figure 14]A plan view showing the arrangement of trenches in a SiC laminate. [Figure 15] A cross-sectional view showing the process flow for forming a MOS structure on the side surface of a trench provided in a SiC laminate. [Figure 16] A plan view showing the process flow for attaching electrodes to the surface of a SiC laminate. [Figure 17] A figure showing the dependence of the normalized channel resistance (Rch_sp) on the trench width (d) in the lateral channel of the {11-2} plane. [Figure 18] This figure shows the dependence of the normalized channel resistance (Rch_sp) on the trench width (d) in the lateral channels of the {1-10} plane. [Figure 19] This figure shows the dependence of the normalized channel resistance (Rch_sp) on the trench width (d) in a three-plane transverse channel including the {1-10} planes. [Figure 20] Cross-sectional view showing the manufacturing process flow of a SiC laminate. [Figure 21] A cross-sectional view showing the manufacturing process flow of a MOSFET with a vertical channel. [Figure 22] This figure shows the dependence of the normalized channel resistance (Rch_sp) on the trench width (d) in the longitudinal channel of the {1-10} plane on the side of the trench. [Figure 23] This figure shows the dependence of the normalized channel resistance (Rch_sp) on the width (d) of the hexagonal prismatic structure in the longitudinal channels of the {1-10} faces of the hexagonal prismatic structure. [Figure 24] This figure shows the dependence of the normalized channel resistance (Rch_sp) on the width (d) of the dodecagonal prismatic structure in the longitudinal channels of the {1-10} and {11-2} faces of the dodecagonal prismatic structure. [Explanation of symbols]

[0097] U-shaped substrate Eh Hexagonal SiC layer or 4H-SiC layer Ec cubic SiC layer or 3C-SiC layer Sh hexagonal SiC partial side or 4H-SiC partial side Sc cubic SiC partial side or 3C-SiC partial side Fh hexagonal SiC surface or 4H-SiC surface Fc cubic SiC surface or 3C-SiC surface X consistent interface Side view of S SiC laminate Section of the matched interface exposed on the side of an Sx SiC stack. Ch Channel G Post Office Ox gate insulating film Of Field membrane B Electric field relaxation region Gv Grooves formed on hexagonal SiC surfaces or 4H-SiC surfaces Dt Tunnel Doping Area Rx Selective EpiMask Ds Source Contact Area Dr. Drain Contact Area Dl Drift Region Re Mask Film Source electrode Pr resist film Wg width of grooves formed on hexagonal SiC surface or 4H-SiC surface Wt Spacing of grooves formed on hexagonal SiC surface or 4H-SiC surface SFD (Stack Fault Density) Vp pinch-off voltage hx offset distance w Distance between opposing sides d. Maximum width of the matching interface (maximum width of trenches and columnar structures)

Claims

1. This is a voltage-driven semiconductor device with a three-dimensional structure provided on a SiC laminate in which a single-crystal cubic SiC layer (Ec) without a twinning interface is stacked on a single-crystal hexagonal SiC layer (Eh). Furthermore, the closest-packed surface of the crystal lattice of the cubic SiC layer (Ec) abuts against the closest-packed surface of the crystal lattice of the underlying hexagonal SiC layer (Eh) to form a matching interface (X). The SiC laminate is provided with a side surface (S) perpendicular to the matching interface (X), and the width (d) of the matching interface (X) is kept to 3 micrometers or less by the termination by the side surface (S). The channel (Ch) of the semiconductor device is formed on a cubic SiC partial side surface (Sc) that constitutes a part of the side surface (S). Furthermore, the semiconductor element is characterized in that the cross section (Sx) of the matching interface exposed on the side surface (S) is located at an offset distance (hx) of 0.1 micrometers or more and 3.0 micrometers or less from the lower end of the side surface (S).

2. The semiconductor device according to claim 1, wherein the carrier transport direction in the channel (Ch) is parallel to the matching interface (X), A semiconductor device characterized in that the crystal lattice plane of the cubic SiC portion side surface (Sc) exposed on the side surface (S) belongs to the {1-10} plane.

3. The semiconductor device according to claim 1, wherein the carrier transport direction in the channel (Ch) is perpendicular to the matched interface (X), A semiconductor device characterized in that the crystal lattice plane of the cubic SiC partial side surface (Sc) exposed on the side surface (S) belongs to at least one of the {1-10} plane or the {11-2} plane.

4. A semiconductor device according to claim 1, characterized in that a field relaxation region (B), which is a second-conductivity impurity doping region, is provided on the surface (Fc) of the hexagonal SiC layer adjacent to the lower end of the side surface (S).

5. A semiconductor element according to claim 1, characterized in that the side surface (S) is the outer surface of a columnar structure perpendicular to the matching interface (X).

6. A semiconductor device according to any one of claims 1 to 5, characterized in that a concentration gradient of an impurity consisting of a first conduction type is provided in at least one of the cubic SiC layer (Ec) or the hexagonal SiC layer (Eh) that exposes the side surface (S), in a direction perpendicular to the matching interface (X).

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