Frequency synthesizers and wireless communication devices

Abstract

To provide a frequency synthesizer having a smaller circuit scale and power consumption than before while being able to switch frequencies at high speed.SOLUTION: An accumulator 12 generates a count value cnt that increases or decreases with a predetermined step width within a predetermined range according to a clock signal clk. A digital / analog converter 13 generates a ramp voltage Vrmp that increases or decreases according to the count value cnt. A signal generating circuit 14 performs analog signal processing to generate an output frequency signal Vout having a signal level that changes with a waveform similar to a sine wave or a cosine wave according to the ramp voltage Vrmp.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This disclosure relates to a frequency synthesizer and a wireless communication device equipped therewith. [Background technology]

[0002] The fifth-generation mobile communication system (5G) has been put into practical use, and development of the sixth-generation mobile communication system (6G) is currently underway. For 6G, the use of millimeter waves and terahertz waves is being considered to achieve even greater capacity.

[0003] As frequencies increase, radio waves propagate less easily, resulting in a smaller cell area covered by a base station. Therefore, when a mobile station communicates while moving, it is assumed that frequent handovers will be necessary to switch between the mobile station and the base station it is communicating with. However, if the channel after a handover is fully occupied by other users, or if the propagation environment is poor, the handover will fail, and communication will be interrupted. To ensure successful handovers, the mobile station needs to use a frequency synthesizer capable of generating multiple frequencies to quickly monitor the availability of other channels at the next base station and adaptively select a channel with a good propagation environment. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] "A Technical Tutorial on Digital Signal Synthesis", Analog Devices, Inc., 1999 [Retrieved November 30, 2021], Internet <URL:https: / / www.analog.com / media / en / training-seminars / design-handbooks / Technical-Tutorial-DDS / technical-tutorial-DDS.pdf> [Overview of the project] [Problems that the invention aims to solve]

[0005] Examples of frequency synthesizers include PLL (Phase Lock Loop) frequency synthesizers and direct digital synthesizers.

[0006] Currently widely used PLL frequency synthesizers take tens of microseconds or more to switch frequencies, making it difficult to monitor multiple channels for short periods of time.

[0007] A direct digital synthesizer is disclosed, for example, in Non-Patent Document 1. A conventional direct digital synthesizer comprises, for example, an accumulator, a lookup table, and a digital-to-analog converter (DAC). The accumulator is a digital circuit that generates the phase value of the output signal. The lookup table is a ROM that stores a correspondence table of phases and amplitudes of sine waves, and converts the phase value generated by the accumulator into an amplitude value. The digital-to-analog converter converts the amplitude value generated by the lookup table into a voltage, generating a voltage signal having a sine wave waveform.

[0008] Direct digital synthesizers are capable of high-speed frequency switching. However, because direct digital synthesizers consist of large digital circuits including ROM, they consume a lot of power, making them difficult to integrate into portable terminal devices. Therefore, in order to integrate direct digital synthesizers into mobile stations or portable terminal devices, it is necessary to reduce their circuit size and power consumption.

[0009] The object of this disclosure is to provide a frequency synthesizer that can switch frequencies at high speed while having a smaller circuit size and lower power consumption than conventional synthesizers. Another object of this disclosure is to provide a wireless communication device equipped with such a frequency synthesizer. [Means for solving the problem]

[0010] A frequency synthesizer relating to one aspect of this disclosure is An accumulator that generates a count value that increases or decreases in a predetermined step size within a predetermined range in response to a clock signal, A digital-to-analog converter that generates a ramp voltage that increases or decreases according to the aforementioned count value, The system includes a signal generation circuit that generates an output frequency signal having a signal level that changes in a waveform similar to a sine wave or cosine wave according to the lamp voltage, by analog signal processing.

[0011] According to a frequency synthesizer relating to one aspect of this disclosure, The aforementioned signal generation circuit is A first differential amplifier that generates a first differential output signal by comparing the ramp voltage with a first reference voltage, A second differential amplifier that generates a second differential output signal by comparing the ramp voltage with a second reference voltage that is higher than the first reference voltage, The system includes a third differential amplifier that generates a third differential output signal by comparing the ramp voltage with a third reference voltage that is higher than the second reference voltage, The output frequency signal is the sum of the first and third differential output signals and the inverted signal of the second differential output signal.

[0012] According to a frequency synthesizer relating to one aspect of this disclosure, Each of the first to third differential amplifiers comprises a pair of bipolar transistors or a pair of field-effect transistors.

[0013] A frequency synthesizer relating to one aspect of this disclosure is The system further includes voltage divider resistors that generate the first to third reference voltages from the power supply voltage.

[0014] According to a frequency synthesizer relating to one aspect of this disclosure, The frequency synthesizer further includes first to third reference voltage sources that respectively generate the first to third reference voltages. The first to third reference voltage sources have components and layouts that are at least partially the same as those of the digital / analog converter.

[0015] According to a frequency synthesizer according to an aspect of the present disclosure, the frequency synthesizer further includes a level shift circuit that reduces the ramp voltage and the first to third reference voltages over a predetermined voltage range. The first to third differential amplifiers respectively compare the ramp voltage reduced by the level shift circuit with the first to third reference voltages reduced by the level shift circuit, and respectively generate the first to third differential output signals.

[0016] According to a frequency synthesizer according to an aspect of the present disclosure, a reference voltage source that generates the first reference voltage, and voltage dividing resistors that generate the second and third reference voltages from a power supply voltage and the first reference voltage. The reference voltage source has components and layouts that are at least partially the same as those of the digital / analog converter.

[0017] According to a frequency synthesizer according to an aspect of the present disclosure, the signal generation circuit generates, by analog signal processing, a first output frequency signal having a signal level that changes in a waveform similar to a sine wave in response to the ramp voltage, and a second output frequency signal having a signal level that changes in a waveform similar to a cosine wave in response to the ramp voltage.

[0018] According to a frequency synthesizer according to an aspect of the present disclosure, the signal generation circuit includes a first differential amplifier that compares the ramp voltage with the first reference voltage to generate a first differential output signal. A second differential amplifier that generates a second differential output signal by comparing the ramp voltage with a second reference voltage that is higher than the first reference voltage, A third differential amplifier that generates a third differential output signal by comparing the ramp voltage with a third reference voltage that is higher than the second reference voltage, A fourth differential amplifier that generates a fourth differential output signal by comparing the ramp voltage with a fourth reference voltage, A fifth differential amplifier that generates a fifth differential output signal by comparing the ramp voltage with a fifth reference voltage that is higher than the fourth reference voltage, The system includes a sixth differential amplifier that generates a sixth differential output signal by comparing the ramp voltage with a sixth reference voltage that is higher than the fifth reference voltage, The first output frequency signal is the sum of the first and third differential output signals and the inverted signal of the second differential output signal. The second output frequency signal is the sum of the fourth and sixth differential output signals and the inverted signal of the fifth differential output signal.

[0019] According to a frequency synthesizer relating to one aspect of this disclosure, Each of the first to sixth differential amplifiers comprises a pair of bipolar transistors or a pair of field-effect transistors.

[0020] A frequency synthesizer relating to one aspect of this disclosure is The first voltage divider resistor generates the first to third reference voltages from the power supply voltage, The system further comprises a second voltage divider resistor that generates the fourth to sixth reference voltages from the power supply voltage.

[0021] According to a frequency synthesizer relating to one aspect of this disclosure, The frequency synthesizer further comprises first to sixth reference voltage sources that generate the first to sixth reference voltages, respectively. The first to sixth reference voltage sources have at least partially the same components and layout as the components and layout of the digital-to-analog converter.

[0022] According to a frequency synthesizer relating to one aspect of this disclosure, The frequency synthesizer further comprises a level shift circuit that reduces the ramp voltage and the first to sixth reference voltages over a predetermined voltage range. The first to sixth differential amplifiers each generate the first to sixth differential output signals by comparing the ramp voltage, reduced by the level shift circuit, with the first to sixth reference voltages, reduced by the level shift circuit, instead of the ramp voltage and the first to sixth reference voltages.

[0023] A frequency synthesizer relating to one aspect of this disclosure is A reference voltage source that generates the first or fourth reference voltage, A first voltage divider resistor that generates the first to third reference voltages from the power supply voltage and the first or fourth reference voltage, The system further comprises a second voltage divider resistor that generates the fourth to sixth reference voltages from the power supply voltage and the first or fourth reference voltage, The reference voltage source has at least partially the same components and layout as the components and layout of the digital-to-analog converter.

[0024] A frequency synthesizer relating to one aspect of this disclosure is The system further comprises at least one frequency multiplier for multiplying the frequency of the output frequency signal.

[0025] A wireless communication device according to one aspect of this disclosure includes the frequency synthesizer. [Effects of the Invention]

[0026] According to one aspect of this disclosure, it is possible to provide a frequency synthesizer that can switch frequencies at high speed while having a smaller circuit size and lower power consumption than conventional synthesizers. [Brief explanation of the drawing]

[0027] [Figure 1]This is a block diagram showing the configuration of the frequency synthesizer 101 according to the first embodiment. [Figure 2] Figure 1 is a graph that schematically shows the waveforms of each signal generated by the frequency synthesizer 101. [Figure 3] Figure 1 is a block diagram showing the configuration of the accumulator 12. [Figure 4] This figure shows an example of the count value cnt generated by the accumulator 12 in Figure 1. [Figure 5] This figure shows another example of the count value cnt generated by the accumulator 12 in Figure 1. [Figure 6] Figure 1 is a circuit diagram showing the configuration of the digital-to-analog converter 13. [Figure 7] Figure 6 illustrates the operation of the digital-to-analog converter 13. [Figure 8] Figure 1 is a circuit diagram showing the configuration of the signal generation circuit 14. [Figure 9] Figure 8 is a circuit diagram showing an example of the configuration of differential amplifiers 41-43. [Figure 10] Figure 8 is a circuit diagram showing another example of the configuration of differential amplifiers 41-43. [Figure 11] Figure 8 is a graph that schematically shows the operating characteristics of each of the differential amplifiers 41 to 43. [Figure 12] This graph schematically shows the changes in operating characteristics when different reference voltages V2 and V3 are set for the pair of differential amplifiers 42 and 43 in Figure 8. [Figure 13] Figure 8 illustrates the operation of the signal generation circuit 14. [Figure 14] This graph schematically shows the frequency spectrum of the count value cnt generated by the accumulator 12 in Figure 1. [Figure 15] This graph schematically shows the frequency spectrum of the output frequency signal Vout generated by the signal generation circuit 14 in Figure 1. [Figure 16] This is a block diagram showing the configuration of the frequency synthesizer 101A according to the second embodiment. [Figure 17] Figure 16 is a circuit diagram showing the configuration of the digital-to-analog converter 13, the signal generation circuit 14A, and the digital-to-analog converters 15-1 to 15-3. [Figure 18] This is a block diagram showing a part of the configuration of a frequency synthesizer according to the first modification of the second embodiment. [Figure 19] This is a block diagram showing the configuration of the frequency synthesizer 101B according to a second modification of the second embodiment. [Figure 20] This is a block diagram showing the configuration of the frequency synthesizer 101C according to the third embodiment. [Figure 21] Figure 20 is a circuit diagram showing the configuration of the digital-to-analog converter 13, the signal generation circuit 14C, and the digital-to-analog converter 18. [Figure 22] This is a block diagram showing the configuration of the frequency synthesizer 101D according to the fourth embodiment. [Figure 23] Figure 22 is a graph that schematically shows the waveforms of each signal generated by the frequency synthesizer 101D. [Figure 24] Figure 22 is a circuit diagram showing the configuration of the signal generation circuit 14D. [Figure 25] Figure 24 is a diagram illustrating the operation of the signal generation circuit 14D. [Figure 26] This is a block diagram showing the configuration of the frequency synthesizer 101E according to the fifth embodiment. [Figure 27] Figure 26 is a circuit diagram showing the configuration of the signal generation circuit 14E. [Figure 28] This is a block diagram showing the configuration of the frequency synthesizer 101F according to a modified example of the fifth embodiment. [Figure 29] This is a block diagram showing the configuration of the frequency synthesizer 101G according to the sixth embodiment. [Figure 30] Figure 29 is a circuit diagram showing the configuration of the signal generation circuit 14G. [Figure 31] This is a block diagram showing the configuration of a wireless communication device according to the seventh embodiment. [Figure 32]This is a block diagram showing the configuration of a wireless communication device according to a modified example of the seventh embodiment. [Modes for carrying out the invention]

[0028] Hereinafter, frequency synthesizers and wireless communication devices according to each embodiment of the present disclosure will be described with reference to the drawings. Throughout the drawings, the same reference numerals indicate the same components.

[0029] [First Embodiment] Figure 1 is a block diagram showing the configuration of the frequency synthesizer 101 according to the first embodiment. Figure 2 is a graph schematically showing the waveforms of each signal generated by the frequency synthesizer 101 in Figure 1.

[0030] The frequency synthesizer 101 in Figure 1 comprises a clock signal source 11, an accumulator 12, a digital-to-analog converter (DAC) 13, and a signal generation circuit 14.

[0031] The clock signal source 11 generates a clock signal clk having a predetermined clock frequency fclk. Generally, the clock signal clk has a fixed clock frequency fclk.

[0032] The accumulator 12 generates a count value cnt that increases or decreases in a predetermined step size within a predetermined range in response to the clock signal clk. In the example in Figure 1, the accumulator 12 has a size of n bits, i.e., 0 to 2 n It is possible to generate an n-bit digital count value cnt that varies over -1. The count value cnt is generated within a predetermined range (i.e., 0 to 2) depending on the clock signal clk, as shown in Figure 2, for example. n It increases in predetermined step sizes within the range of -1. The count value cnt is 2 n When it exceeds -1, it overflows to 2 nIt is subtracted. Also, an n-bit frequency setting value K is input to the accumulator 12 from an external control circuit (not shown). The frequency setting value K has a time period T0=2, which is determined by the number of bits n in the accumulator 12. n This represents the number of times the count value cnt overflows in / fclk (in the example in Figure 2, K=2).

[0033] The digital-to-analog converter 13 generates a ramp voltage Vrmp that increases or decreases according to the count value cnt. In other words, the digital-to-analog converter 13 converts the count value cnt in digital form to the ramp voltage Vrmp in analog form. In the example in Figure 2, the ramp voltage Vrmp increases twice in time period T0 from a minimum (or local minimum) to a maximum (or local maximum).

[0034] The signal generation circuit 14 generates an output frequency signal Vout by analog signal processing, which has a signal level that changes in a waveform similar to a sine wave or cosine wave depending on the ramp voltage Vrmp. In the example in Figure 2, the output frequency signal Vout has a signal level that changes in a time period T0 corresponding to the phase value of a sine wave from 0 to 4π.

[0035] Here, "waveform similar to a sine wave (or cosine wave)" means a periodic signal waveform consisting of a combination of hyperbolic sine functions that can sufficiently approximate a sine wave (or cosine wave), as will be described later with reference to Figures 11 to 13. Furthermore, the output frequency signal Vout may contain small errors from the sine wave (or cosine wave) due to manufacturing variations in each component 11 to 14 of the frequency synthesizer 101, overflow of the accumulator 12, etc.

[0036] The count value cnt, the ramp voltage Vrmp, and the output frequency signal Vout each change periodically with a time period T0.

[0037] The frequency synthesizer 101 shown in Figure 1 is a direct digital synthesizer capable of generating sine or cosine wave signals of arbitrary frequencies without using a lookup table. The frequency synthesizer 101 can switch frequencies at high speed while reducing its circuit size and power consumption compared to conventional direct digital synthesizers.

[0038] Figure 3 is a block diagram showing the configuration of the accumulator 12 in Figure 1. The accumulator 12 is a digital circuit comprising an n-bit adder 21 and an n-bit latch 22. The adder 21 adds the frequency setting value K to the count value cnt output from the latch 22 and outputs it. The latch 22 stores the output value of the adder 21. On each rising edge of the clock signal clk, the latch 22 outputs the currently stored value as the count value cnt and stores the output value of the adder 21.

[0039] Figure 4 shows an example of the count value cnt generated by the accumulator 12 in Figure 1. Figure 5 shows another example of the count value cnt generated by the accumulator 12 in Figure 1. Figure 4 shows the case where n=4 and K=1, and Figure 5 shows the case where n=4 and K=3. In the case of n=4, the accumulator 12 is 0~2 n-1. That is, a count value that is cumulatively added within the range of 0 to 15 is generated. When the addition result of the adder 21 becomes 16 or more, an overflow occurs, and as a result, a value obtained by subtracting 16 from the original addition result is output. When the frequency setting value K = 1, the count value cnt increases by 1 each time the clock signal clk rises. When it reaches 16 after 15, an overflow occurs and it becomes 0, and then the count value cnt increases by 1 again. When the frequency setting value K = 3, the count value cnt increases by 3 each time the clock signal clk rises. When it reaches 18 after 15, an overflow occurs and it becomes 2, and then the count value cnt increases by 3 again. When the frequency setting value K = 5, the count value cnt increases by 5 each time the clock signal clk rises. When it reaches 20 after 15, an overflow occurs and it becomes 4, and then the count value cnt increases by 5 again. The overflow of the count value cnt, on average, is generated at a period of f = K × fclk / 2 n is generated.

[0040] The frequency of the output frequency signal Vout is equal to the frequency of the count value cnt and is represented by K × fclk / 2 n The number of bits n of the accumulator 12 is determined according to the number of channels used by the wireless communication device equipped with the frequency synthesizer 101. Generally, n = 8 to 12 is sufficient.

[0041] FIG. 6 is a circuit diagram showing the configuration of the digital / analog converter 13 in FIG. 1. The digital / analog converter 13 includes resistors R0, switches 31-1 to 31-(2 n -1), and constant current sources 32-1 to 32-(2 n -1). The switches 31-1 to 31-(2 n -1) have the same characteristics as each other. The constant current sources 32-1 to 32-(2 n -1) also have the same characteristics as each other and generate a predetermined current I.

[0042] In this specification, the switches 31-1 to 31-(2 n-1) are collectively called "switch 31", and constant current sources 32-1~32-(2 n -1) is collectively referred to as "constant current source 32".

[0043] The example in Figure 6 shows the case where n=3 bits, and the digital-to-analog converter 13 is 2 3 -1 = It is equipped with 7 switches 31 and 7 constant current sources 32. The count value cnt consists of 3 bits b1 to b3, where b1 is the least significant bit and b3 is the most significant bit. One switch 31 is turned on / off according to bit b1, two switches 31 are turned on / off in conjunction according to bit b2, and four switches 31 are turned on / off in conjunction according to bit b3.

[0044] Figure 7 illustrates the operation of the digital-to-analog converter 13 in Figure 6. The horizontal axis of Figure 7 shows the code consisting of bits b3, b2, and b1 of the count value, and the vertical axis shows the ramp voltage Vrmp corresponding to each code. When all switches 31 are off (i.e., the count value cnt is "000"), the ramp voltage Vrmp is equal to the power supply voltage Vcc. For each switch 31 that is turned on, the ramp voltage Vrmp decreases by I × R0 from the power supply voltage Vcc. When all switches 31 are on (i.e., the count value cnt is "111"), the ramp voltage Vrmp is Vcc - 7 × I × R0.

[0045] Figures 4 and 5 illustrate the accumulator 12 with n=4, and Figures 6 and 7 illustrate the digital-to-analog converter 13 with n=3. Note that the number of bits n of the digital-to-analog converter 13 is set to be equal to the number of bits n of the accumulator 12.

[0046] The digital-to-analog converter 13 in Figure 6 is a current-summing type converter that excels in high-speed operation, but any other type of converter may be used.

[0047] Figure 8 is a circuit diagram showing the configuration of the signal generation circuit 14 in Figure 1. The signal generation circuit 14 comprises differential amplifiers 41-43 and resistors R11-R16. Resistors R11-R14 are connected in series between the terminal of the positive power supply voltage Vcc and the terminal of the negative power supply voltage Vee, and are voltage divider resistors (or resistor ladder) that generate reference voltages V1-V3 from the power supply voltages Vcc and Vee. The resistance values ​​of resistors R12 and R13 are set to be equal to each other. Differential amplifier 41 generates a first differential output signal by comparing the ramp voltage Vrmp with the reference voltage V1. Differential amplifier 42 generates a second differential output signal by comparing the ramp voltage Vrmp with the reference voltage V2 which is higher than the reference voltage V1. Differential amplifier 43 generates a third differential output signal by comparing the ramp voltage Vrmp with the reference voltage V3 which is higher than the reference voltage V2. The output terminals of differential amplifiers 41-43 are connected to the terminal of the power supply voltage Vcc via resistors R15 and R16. The output frequency signal Vout is the sum of the differential output signals from differential amplifiers 41 and 43 and the inverted signal of the differential output signal from differential amplifier 42.

[0048] Figure 9 is a circuit diagram showing an example of the configuration of differential amplifiers 41-43 in Figure 8. Each of the differential amplifiers 41-43 comprises a pair of bipolar transistors Q1 and Q2, a constant current source 51, and resistors Ra-Rd. A ramp voltage Vrmp is applied to the base of bipolar transistor Q1, and a reference voltage Vx (x=1,2,3) is applied to the base of bipolar transistor Q2. Depending on the potential difference between the ramp voltage Vrmp and the reference voltage Vx, an output current Ix flows through the output terminals dout1 and dout2.

[0049] Figure 10 is a circuit diagram showing another example of the configuration of the differential amplifiers 41-43 in Figure 8. The signal generation circuit 14 may include the differential amplifiers 41A-43A of Figure 10 instead of the differential amplifiers 41-43 of Figure 9. Each of the differential amplifiers 41A-43A includes a pair of field-effect transistors Q1A and Q2A instead of the bipolar transistors Q1 and Q2 of Figure 9.

[0050] Figure 11 is a graph schematically showing the operating characteristics of each of the differential amplifiers 41 to 43 in Figure 8. The output current Ix of each differential amplifier 41 to 43 fluctuates with approximately the characteristics of the hyperbolic sine function tanh(Vrmp) with respect to the ramp voltage Vrmp (solid line) or the characteristics of its inverted signal (dashed line). When the ramp voltage Vrmp is within a predetermined voltage range Vtran centered on the reference voltage Vx, the output current Ix fluctuates according to the ramp voltage Vrmp, but when the ramp voltage Vrmp is outside the voltage range Vtran, the output current Ix does not substantially fluctuate even if the ramp voltage Vrmp changes.

[0051] Figure 12 is a schematic graph showing the change in operating characteristics when different reference voltages V2 and V3 are set for the pair of differential amplifiers 42 and 43 in Figure 8. The upper, middle, and lower panels of Figure 12 show the current Isum', which is the sum of the output currents of the differential amplifiers 42 and 43, in response to a change in the ramp voltage Vrmp. The upper panel of Figure 12 shows the case where reference voltages V2 and V3 with a large difference (shown as reference voltages V2a and V3a) are set, the lower panel of Figure 12 shows the case where reference voltages V2 and V3 with a small difference (shown as reference voltages V2c and V3c) are set, and the middle panel of Figure 12 shows the case where reference voltages V2 and V3 with an intermediate difference (shown as reference voltages V2b and V3b) are set. By combining the differential amplifiers 42 and 43, each having the characteristics of a hyperbolic sine function, the current Isum' fluctuates with respect to the ramp voltage Vrmp with characteristics of two hyperbolic sine functions linked together. In the upper and lower cases of Figure 12, the current Isum' deviates significantly from the half-period waveform of a sine wave. On the other hand, in the middle case of Figure 12, it can be seen that by appropriately setting the difference between the reference voltages V2 and V3, the current Isum' can be closely approximated to the half-period waveform of a sine wave.

[0052] Similarly, by appropriately setting the difference between the reference voltages V1 and V2, the sum of the output currents of the differential amplifiers 41 and 42 can also be made to closely approximate the waveform of the remaining half-period of the sine wave.

[0053] Figure 13 illustrates the operation of the signal generation circuit 14 in Figure 8. Figure 13 shows the current Isum, which is the sum of the output currents of the differential amplifiers 41 to 43, in response to a change in the ramp voltage Vrmp. When the digital-to-analog converter 13 has the configuration of Figure 6, the voltage range V1 to V3 is divided into eight parts, and eight ramp voltages Vrmp are generated as indicated by the arrows in Figure 13. The current Isum when the ramp voltage Vrmp = V1 is equal to the current Isum when the ramp voltage Vrmp = V3. Therefore, as shown in Figure 13, the digital-to-analog converter 13 does not need to be able to generate the ramp voltage Vrmp = V1 as long as it can generate the ramp voltage Vrmp = V3. By appropriately setting the difference between the reference voltages V1 to V3, the current Isum output from the differential amplifiers 41 to 43 can be made to closely approximate the waveform of the entire period of a sine wave.

[0054] When the count values ​​cnt are generated in the order 000, 001, 010, ..., 111, and the ramp voltage Vrmp in Figure 7 is generated according to these codes, a current Isum is generated that changes in a waveform similar to a sine wave, according to the characteristics in Figure 13. When the current Isum flows through a load resistor (not shown), an output frequency signal Vout is generated that has a voltage that changes in a waveform similar to a sine wave.

[0055] Figure 14 is a schematic graph showing the frequency spectrum of the count value cnt generated by the accumulator 12 in Figure 1. Figure 15 is a schematic graph showing the frequency spectrum of the output frequency signal Vout generated by the signal generation circuit 14 in Figure 1. The count value cnt may contain unwanted frequencies in addition to the desired frequency and its harmonics. Also, as mentioned above, the overflow of the count value cnt is, on average, f = K × fclk / 2 n The signal is generated at a certain frequency, and if left as is, there is a risk of large jitter (time error) occurring in the output frequency signal Vout. According to the frequency synthesizer 101 of the first embodiment, by generating a sine wave through analog signal processing of the signal generation circuit 14, unwanted waves are suppressed, and an output frequency signal Vout with low jitter and high frequency purity can be obtained.

[0056] The frequency synthesizer 101 according to the first embodiment generates sine waves by analog signal processing of the signal generation circuit 14, thereby enabling the generation of sine or cosine wave signals of arbitrary frequencies without the use of a lookup table. The frequency synthesizer 101 can switch frequencies at high speed while reducing its circuit size and power consumption compared to conventional direct digital synthesizers.

[0057] Conventional frequency synthesizers include a ROM containing thousands to tens of thousands of transistors to store a lookup table, and the ROM consumes approximately 30 to 40% of the total power consumption of the frequency synthesizer. According to the frequency synthesizer 101 of the first embodiment, the lookup table is no longer required, which significantly reduces the circuit size and power consumption compared to conventional models.

[0058] According to the frequency synthesizer 101 of the first embodiment, by using the accumulator 12, the frequency of the output frequency signal Vout can be precisely set even without a lookup table.

[0059] [Second Embodiment] Figure 16 is a block diagram showing the configuration of the frequency synthesizer 101A according to the second embodiment. The frequency synthesizer 101A includes a signal generation circuit 14A in place of the signal generation circuit 14 in Figure 1, and further includes digital-to-analog converters (DACs) 15-1 to 15-3.

[0060] The digital-to-analog converters 15-1 to 15-3 are reference voltage sources that generate reference voltages V1 to V3, respectively. The digital-to-analog converters 15-1 to 15-3 are replica circuits of the digital-to-analog converter 13, having at least partially the same components and layout as the digital-to-analog converter 13.

[0061] The signal generation circuit 14A operates based on reference voltages V1 to V3 supplied from external digital-to-analog converters 15-1 to 15-3, rather than on reference voltages V1 to V3 (see Figure 8) that it generates internally.

[0062] In the first embodiment, the ramp voltage Vrmp is generated by the digital-to-analog converter 13, and the reference voltages V1 to V3 are generated by the voltage divider resistors. In other words, the ramp voltage Vrmp and the reference voltages V1 to V3 are generated by different mechanisms. As a result, variations in the manufacturing of elements such as transistors and resistors, fluctuations in power supply voltage, and variations in element characteristics due to temperature may occur, potentially causing fluctuations in the output frequency signal Vout. In the second embodiment, the reference voltages V1 to V3 can be generated by digital-to-analog converters 15-1 to 15-3, which are replica circuits of the digital-to-analog converter 13, thereby improving PVT (process, power supply voltage, temperature) fluctuation tolerance.

[0063] Figure 17 is a circuit diagram showing the configuration of the digital-to-analog converter 13, the signal generation circuit 14A, and the digital-to-analog converters 15-1 to 15-3 shown in Figure 16.

[0064] The example in Figure 17 shows the case where n=3 bits, and the digital-to-analog converter 13 is 2 3 -1 = Equipped with 7 switches 31 and 7 constant current sources 32. Each of the digital / analog converters 15-2 and 15-3 is equipped with the same 7 switches 31 and 7 constant current sources 32 as the digital / analog converter 13. The digital / analog converter 15-1 is equipped with the same 7 switches 31 and 7 constant current sources 32 as the digital / analog converter 13 (as shown by circuit section 15-0), and further includes additional switches 33 and constant current sources 34 having the same characteristics as the switches 31 and constant current sources 32.

[0065] In the digital-to-analog converter 15-1, all switches 31 and 33 are pre-set to be on, thereby generating a reference voltage V1. In the digital-to-analog converter 15-2, four switches 31 are pre-set to be on and the remaining three switches 31 are pre-set to be off, thereby generating a reference voltage V2. In the digital-to-analog converter 15-3, all switches 31 are pre-set to be off, thereby generating a reference voltage V3.

[0066] The signal generation circuit 14A has a configuration obtained by removing resistors R11 to R14 from the signal generation circuit 14 in Figure 8. The differential amplifiers 41 to 43 each generate differential output signals by comparing the ramp voltage Vrmp with the reference voltages V1 to V3 generated by the digital-to-analog converters 15-1 to 15-3.

[0067] The circuit portion 15-0 of the digital / analog converter 15-1, and the digital / analog converters 15-2 and 15-3, have at least partially the same components and layout as those of the digital / analog converter 13. This makes them less susceptible to manufacturing variations of the elements and fluctuations in the power supply voltage. Furthermore, to reduce the impact of temperature-induced variations in element characteristics, the digital / analog converters 13 and 15-1 to 15-3 may be placed in close proximity to each other.

[0068] To improve the symmetry of the digital / analog converters 13 and 15-1 to 15-3, switches 33 and constant current sources 34 similar to those in digital / analog converter 15-1 may be added to digital / analog converters 13, 15-1, and 15-2.

[0069] Because differential amplifiers have a high common-mode rejection ratio (CMRR), even if there are PVT fluctuations, the fluctuations will cancel each other out if the same fluctuations are applied to the two input signals of the differential amplifier. Therefore, according to the frequency synthesizer 101A of the second embodiment, PVT fluctuation tolerance can be greatly improved.

[0070] Figure 18 is a block diagram showing a partial configuration of a frequency synthesizer according to a first modification of the second embodiment. The frequency synthesizer 101A in Figure 16 may include digital / analog converters 15A-2 and 15A-3 in Figure 18 instead of digital / analog converters 15-2 and 15-3 in Figure 17. Digital / analog converters 15A-2 and 15A-3 have a configuration in which the switch 31 and the constant current source 32 connected to it, which were turned off in the digital / analog converters 15-2 and 15-3 in Figure 17, are removed. Digital / analog converters 15-1, 15A-2, and 15A-3 have the same components and layout as digital / analog converter 13 with respect to the elements through which current flows. Furthermore, by removing elements through which no current flows from the digital / analog converter, the circuit size can be reduced while improving PVT fluctuation tolerance.

[0071] Figure 19 is a block diagram showing the configuration of a frequency synthesizer 101B according to a second modification of the second embodiment. The frequency synthesizer 101B includes a signal generation circuit 14B in place of the signal generation circuit 14A in Figure 16, and further includes level shift circuits 16, 17-1 to 17-3.

[0072] The level shift circuit 16 reduces the ramp voltage Vrmp over a predetermined voltage range, for example, about 0.7V. The level shift circuits 17-1 to 17-3 reduce the reference voltages V1 to V3 over predetermined voltage ranges, respectively. The level shift circuits 16, 17-1 to 17-3 are, for example, diodes, emitter follower circuits, and source follower circuits.

[0073] The signal generation circuit 14B is configured in the same way as the signal generation circuit 14A, however, in the signal generation circuit 14B, the differential amplifiers 41 to 43 compare the ramp voltage Vrmp, which has been reduced by the level shift circuit 16, with the reference voltages V1 to V3, which have been reduced by the level shift circuits 17-1 to 17-3, respectively, instead of the ramp voltage Vrmp and reference voltages V1 to V3, and generate differential output signals.

[0074] The ramp voltage Vrmp has a maximum value equal to the power supply voltage Vcc. However, generally, the speed and accuracy of a differential amplifier are maximized when it is operated at a voltage intermediate between the power supply voltage and the ground voltage. According to the frequency synthesizer 101B in Figure 19, the differential amplifiers 41-43 can be operated at high speed and with high accuracy by reducing the ramp voltage Vrmp and reference voltages V1-V3 over a predetermined voltage range using level shift circuits 16, 17-1 to 17-3.

[0075] [Third Embodiment] Figure 20 is a block diagram showing the configuration of the frequency synthesizer 101C according to the third embodiment. The frequency synthesizer 101C includes a signal generation circuit 14C instead of the signal generation circuit 14 in Figure 1, and further includes a digital-to-analog converter (DAC) 18.

[0076] The digital-to-analog converter 18 is a reference voltage source that generates a reference voltage V1. The digital-to-analog converter 18 is a replica circuit of the digital-to-analog converter 13, having at least partially the same components and layout as the digital-to-analog converter 13.

[0077] The signal generation circuit 14C operates based on a reference voltage V1 supplied from an external digital-to-analog converter 18 and reference voltages V2 to V3 generated internally.

[0078] Figure 21 is a circuit diagram showing the configuration of the digital-to-analog converter 13, the signal generation circuit 14C, and the digital-to-analog converter 18 shown in Figure 20.

[0079] The example in Figure 21 shows the case where n=3 bits, and the digital-to-analog converter 13 is 2 3-1 = It has seven switches 31 and seven constant current sources 32. The digital-to-analog converter 18 has the same seven switches 31 and seven constant current sources 32 as the digital-to-analog converter 13. The digital-to-analog converter 18 has the same configuration as the digital-to-analog converter 13 but with the resistor R0 removed. In the digital-to-analog converter 18, all of the switches 31 are set to be on, thereby generating a reference voltage V1.

[0080] The signal generation circuit 14C has the same configuration as the signal generation circuit 14 in Figure 8, but with resistor R11 removed. Resistors R12 to R14 are voltage divider resistors that generate reference voltages V2 and V3 from the power supply voltage Vcc and reference voltage V1.

[0081] The frequency synthesizer 101A according to the second embodiment includes a large number of digital-to-analog converters 15-1 to 15-3, which tends to increase power consumption. On the other hand, according to the frequency synthesizer 101C according to the third embodiment, reference voltages V1 to V3 can be generated simultaneously using an additional digital-to-analog converter 18 and resistors R12 to R14. Therefore, according to the frequency synthesizer 101C according to the third embodiment, the increase in power consumption can be minimized while improving PVT immunity.

[0082] [Fourth Embodiment] Figure 22 is a block diagram showing the configuration of the frequency synthesizer 101D according to the fourth embodiment. Figure 23 is a graph schematically showing the waveforms of each signal generated by the frequency synthesizer 101D in Figure 22.

[0083] The frequency synthesizer 101D includes a signal generation circuit 14D instead of the signal generation circuit 14 in Figure 1. The signal generation circuit 14D generates a first output frequency signal Vout1, which has a signal level that changes in a waveform similar to a sine wave according to the ramp voltage Vrmp, and a second output frequency signal Vout2, which has a signal level that changes in a waveform similar to a cosine wave according to the ramp voltage Vrmp, by analog signal processing.

[0084] When upconverting or downconverting a baseband signal or an intermediate frequency signal, or when modulating or demodulating a signal, it is often necessary to simultaneously generate two signals (i.e., a sine wave and a cosine wave) that have a phase difference of 90 degrees from each other. For this reason, the frequency synthesizer 101D according to the fourth embodiment simultaneously generates a first output frequency signal Vout1 that is similar to a sine wave and a second output frequency signal Vout2 that is similar to a cosine wave.

[0085] Figure 24 is a circuit diagram showing the configuration of the signal generation circuit 14D in Figure 22. The signal generation circuit 14D comprises differential amplifiers 41-46 and resistors R11-R16, R21-R26.

[0086] Resistors R11-R14 and R21 are connected in series between the terminal of the positive power supply voltage Vcc and the terminal of the negative power supply voltage Vee, forming the first voltage divider resistors that generate reference voltages V1-V3 from the power supply voltage. Resistors R14, R21-R24 are connected in series between the terminal of the positive power supply voltage Vcc and the terminal of the negative power supply voltage Vee, forming the second voltage divider resistors that generate reference voltages V4-V6 from the power supply voltage. The resistance values ​​of resistors R11 and R24 are set to be equal to each other. Also, resistors R12, R13, R22, R23 The resistance values ​​of the resistors are set to be equal to each other and twice the resistance values ​​of resistors R11 and R24.

[0087] Differential amplifier 41 generates a first differential output signal by comparing the ramp voltage Vrmp with a reference voltage V1. Differential amplifier 42 generates a second differential output signal by comparing the ramp voltage Vrmp with a reference voltage V2 that is higher than the reference voltage V1. Differential amplifier 43 generates a third differential output signal by comparing the ramp voltage Vrmp with a reference voltage V3 that is higher than the reference voltage V2.

[0088] Differential amplifier 44 generates a fourth differential output signal by comparing the ramp voltage Vrmp with a reference voltage V4. Differential amplifier 45 generates a fifth differential output signal by comparing the ramp voltage Vrmp with a reference voltage V5 that is higher than the reference voltage V4. Differential amplifier 46 generates a sixth differential output signal by comparing the ramp voltage Vrmp with a reference voltage V6 that is higher than the reference voltage V5.

[0089] The output terminals of differential amplifiers 41-43 are connected to the power supply voltage Vcc terminal via resistors R15 and R16. The output terminals of differential amplifiers 44-46 are connected to the power supply voltage Vcc terminal via resistors R25 and R26.

[0090] The first output frequency signal Vout1 is the sum of the differential output signals from differential amplifiers 41 and 43 and the inverted differential output signal from differential amplifier 42. The second output frequency signal Vout2 is the sum of the differential output signals from differential amplifiers 44 and 46 and the inverted differential output signal from differential amplifier 45.

[0091] Each of the differential amplifiers 41 to 46 may include a pair of bipolar transistors Q1, Q2 or a pair of field-effect transistors Q1A, Q2A, as shown in Figures 9 and 10.

[0092] Figure 25 illustrates the operation of the signal generation circuit 14D shown in Figure 24. Figure 25 shows the current Isum1, which is the sum of the output currents of differential amplifiers 41-43, and the current Isum2, which is the sum of the output currents of differential amplifiers 44-46, in response to a change in the ramp voltage Vrmp. By appropriately setting the difference between the reference voltages V1-V3, the current Isum1 output from differential amplifiers 41-43 can be closely approximated to a sinusoidal waveform. Similarly, by appropriately setting the difference between the reference voltages V4-V6, the current Isum2 output from differential amplifiers 44-46 can be closely approximated to a cosine waveform.

[0093] In the examples of FIGS. 24 and 25, the reference voltages V1 to V6 are set in the order of V4 < V1 < V5 < V2 < V6 < V3, but they may be set in other orders, for example, in the order of V1 < V4 < V2 < V5 < V3 < V6.

[0094] According to the frequency synthesizer 101D according to the fourth embodiment, both a sine wave and a cosine wave can be simultaneously generated with a small circuit scale and low power consumption, and the frequency can be switched at high speed.

[0095] According to the frequency synthesizer 101D according to the fourth embodiment, not only a sine wave and a cosine wave (that is, a sine wave with a phase of 0 degrees) but also an inverted signal of the sine wave (that is, a sine wave with a phase of 180 degrees) and an inverted signal of the cosine wave (that is, a sine wave with a phase of 270 degrees) may be simultaneously extracted from the output terminals of the differential amplifiers 41 to 46. <{

[0096] [Fifth Embodiment] FIG. 26 is a block diagram showing the configuration of a frequency synthesizer 101E according to the fifth embodiment. The frequency synthesizer 101E includes a signal generation circuit 14E instead of the signal generation circuit 14D in FIG. 22, and further includes digital / analog converters (DACs) 15-1 to 15-6.

[0097] The digital / analog converters 15-1 to 15-6 are reference voltage sources that respectively generate the reference voltages V1 to V6. The digital / analog converters 15-1 to 15-6 are replica circuits of the digital / analog converter 13 having at least partially the same components and layout as the components and layout of the digital / analog converter 13. The digital / analog converters 15-1 to 15-6 are configured in the same manner as the digital / analog converters 15-1 to 15-3 in FIG. 17 or 15A-2 and 15A-3 in FIG. 18.

[0098] The signal generation circuit 14E operates based on the reference voltages V1 to V6 supplied from the external digital / analog converters 15-1 to 15-6, rather than the reference voltages V1 to V6 generated inside it (see FIG. 24).

[0099] Figure 27 is a circuit diagram showing the configuration of the signal generation circuit 14E in Figure 26. The signal generation circuit 14E has a configuration obtained by removing resistors R11~R14 and R21~R24 from the signal generation circuit 14D in Figure 24. The differential amplifiers 41~46 each generate differential output signals by comparing the ramp voltage Vrmp with the reference voltages V1~V6 generated by the digital / analog converters 15-1~15-6.

[0100] According to the frequency synthesizer 101E of the fifth embodiment, PVT fluctuation tolerance can be improved, similar to the frequency synthesizer 101A of the second embodiment.

[0101] Figure 28 is a block diagram showing the configuration of a frequency synthesizer 101F according to a modified example of the fifth embodiment. The frequency synthesizer 101F includes a signal generation circuit 14F instead of the signal generation circuit 14E in Figure 26, and further includes level shift circuits 16, 17-1 to 17-6.

[0102] The level shift circuit 16 reduces the ramp voltage Vrmp over a predetermined voltage range, for example, about 0.7V. The level shift circuits 17-1 to 17-6 reduce the reference voltages V1 to V6 over predetermined voltage ranges, respectively.

[0103] The signal generation circuit 14F is configured similarly to the signal generation circuit 14E, however, in the signal generation circuit 14F, the differential amplifiers 41 to 46, instead of the ramp voltage Vrmp and reference voltages V1 to V6, compare the ramp voltage Vrmp, which has been reduced by the level shift circuit 16, with the reference voltages V1 to V6, which have been reduced by the level shift circuits 17-1 to 17-6, respectively, to generate differential output signals.

[0104] According to the frequency synthesizer 101F in Figure 28, similar to the frequency synthesizer 101B in Figure 19, the differential amplifiers 41-46 can be operated at high speed and with high precision by using level shift circuits 16, 17-1 to 17-6 to reduce the ramp voltage Vrmp and reference voltages V1-V6 over a predetermined voltage range.

[0105] [Sixth Embodiment] Figure 29 is a block diagram showing the configuration of the frequency synthesizer 101G according to the sixth embodiment. The frequency synthesizer 101G includes a signal generation circuit 14G in place of the signal generation circuit 14D in Figure 22, and further includes a digital-to-analog converter (DAC) 18G.

[0106] The digital-to-analog converter 18G is a reference voltage source that generates a reference voltage V4. The digital-to-analog converter 18G is a replica circuit of the digital-to-analog converter 13, having at least partially the same components and layout as the digital-to-analog converter 13. The digital-to-analog converter 18G is configured similarly to the digital-to-analog converter 18G in Figure 21.

[0107] The signal generation circuit 14G operates based on a reference voltage V4 supplied from an external digital-to-analog converter 18G and reference voltages V1-V3, V5, and V6 generated internally.

[0108] Figure 30 is a circuit diagram showing the configuration of the signal generation circuit 14G in Figure 29. The signal generation circuit 14G has the same configuration as the signal generation circuit 14D in Figure 22, but with resistor R21 removed. Resistors R11 to R14 are first voltage divider resistors that generate reference voltages V1 to V3 from the power supply voltage Vcc and the reference voltage V4. Resistors R14, R22 to R24 are second voltage divider resistors that generate reference voltages V5 and V6 from the power supply voltage Vcc and the reference voltage V4.

[0109] According to the frequency synthesizer 101G according to the sixth embodiment, similar to the frequency synthesizer 101C according to the third embodiment, it is possible to minimize an increase in power consumption while improving PVT tolerance.

[0110] As described above, when the reference voltages V1 to V6 are set in another order, for example, in the order of V1 < V4 < V2 < V5 < V3 < V6, the reference voltage source 18G generates the reference voltage V1. In this case, the reference voltages V2 and V3 are generated from the power supply voltage Vcc and the reference voltage V1, and the reference voltages V4 to V6 are generated from the power supply voltage Vcc and the reference voltage V1.

[0111] [Seventh Embodiment] FIG. 31 is a block diagram showing the configuration of a wireless communication device according to the seventh embodiment. The wireless communication device in FIG. 31 includes a control circuit 100, frequency synthesizers 101-1 and 101-2, frequency multipliers 102-1 and 102-2, a circulator 103, an antenna 104, a transmission circuit 111, a digital / analog converter (DAC) 112, a low-pass filter (LPF) 113, a mixer 114, a mixer 121, a low-pass filter (LPF) 122, an analog / digital converter (ADC) 123, and a reception circuit 124.

[0112] Each of the frequency synthesizers 101-1 and 101-2 is configured in the same manner as the frequency synthesizer 101 in FIG. 1. The control circuit 100 sets frequency setting values K1 and K2 in the frequency synthesizers 101-1 and 101-2, respectively. The frequency multipliers 102-1 and 102-2 multiply the frequencies of the output frequency signals of the frequency synthesizers 101-1 and 101-2 to generate carrier waves.

[0113] The circulator 103 separates the radio signal transmitted via the antenna 104 and the radio signal received via the antenna 104 from each other.

[0114] The transmitting circuit 111 generates a digital baseband signal. The digital-to-analog converter (DAC) 112 converts the digital baseband signal to an analog baseband signal. The low-pass filter (LPF) 113 removes high-frequency components from the analog baseband signal. The mixer 114 modulates the carrier wave generated by the frequency multiplier 102-1 with the filtered analog baseband signal to generate a radio signal. The generated radio signal is transmitted via the circulator 103 and antenna 104.

[0115] Mixer 121 demodulates the radio signal received via antenna 104 and circulator 103 using the carrier wave generated by frequency multiplier 102-2 to generate an analog baseband signal. Low-pass filter (LPF) 122 removes high-frequency components from the demodulated analog baseband signal. Analog-to-digital converter (ADC) 123 converts the filtered analog baseband signal into a digital baseband signal. Receiving circuit 124 processes the received digital baseband signal.

[0116] The wireless communication device shown in Figure 31 is a direct conversion type wireless communication device that does not include an intermediate frequency circuit.

[0117] According to the wireless communication device shown in Figure 31, the control circuit 100 can rapidly switch between frequencies by setting the frequency setpoints K1 and K2 to the frequency synthesizers 101-1 and 101-2, respectively. Therefore, according to the wireless communication device shown in Figure 31, even when communicating while moving, the status of other channels can be monitored in a short time, and a channel with a good propagation environment can be adaptively selected to ensure a reliable handover.

[0118] Figure 32 is a block diagram showing the configuration of a wireless communication device according to a modified example of the seventh embodiment. The wireless communication device in Figure 32 includes frequency synthesizers 101D-1, 101D-2, frequency multipliers 102A-1, 102A-2, transmission circuit 111A, and reception circuit 124A, instead of the frequency synthesizers 101-1, 101-2, frequency multipliers 102-1, 102-2, transmission circuit 111, and reception circuit 124 of Figure 31. Furthermore, the wireless communication device in Figure 32 includes a digital-to-analog converter (DAC) 115, a low-pass filter (LPF) 116, a mixer 117, a mixer 125, a low-pass filter (LPF) 126, and an analog-to-digital converter (ADC) 127.

[0119] Each of the frequency synthesizers 101D-1 and 101D-2 is configured similarly to the frequency synthesizer 101D in Figure 22, and generates a first output frequency signal similar to a sine wave and a second output frequency signal similar to a cosine wave. Each of the frequency multipliers 102A-1 and 102A-2 multiplies the frequencies of the two output frequency signals of the corresponding frequency synthesizers 101D-1 and 101D-2 to generate two carrier waves.

[0120] The transmitting circuit 111A generates a digital baseband signal including the I signal and the Q signal. The digital-to-analog converter (DAC) 115, low-pass filter (LPF) 116, and mixer 117 are configured similarly to the digital-to-analog converter 112, low-pass filter 113, and mixer 114. The digital-to-analog converter 112, low-pass filter 113, and mixer 114 process the I signal, while the digital-to-analog converter 115, low-pass filter 116, and mixer 117 process the Q signal.

[0121] The mixer 125, low-pass filter (LPF) 126, and analog-to-digital converter (ADC) 127 are configured similarly to the mixer 121, low-pass filter 122, and analog-to-digital converter 123. The mixer 121, low-pass filter 122, and analog-to-digital converter 123 process the I signal, while the mixer 125, low-pass filter 126, and analog-to-digital converter 127 process the Q signal. The receiving circuit 124A processes the received digital baseband signal, including the I and Q signals.

[0122] According to the wireless communication device shown in Figure 32, each of the frequency synthesizers 101D-1 and 101D-2 generates two mutually orthogonal output frequency signals, enabling quadrature phase modulation and demodulation with a smaller circuit size than conventional methods.

[0123] Although the wireless communication circuits in Figures 31 and 32 are configured to transmit and receive wireless signals, the frequency synthesizers 101, 101D, etc., according to the embodiment can also be applied to wireless communication devices configured to transmit or receive only wireless signals.

[0124] The wireless communication device shown in Figure 32 can also be applied to other modulation / demodulation methods such as QAM.

[0125] To generate a high-frequency carrier wave, two or more frequency multipliers may be provided in cascaded order after each frequency synthesizer. Alternatively, at least one frequency multiplier may be integrated into the frequency synthesizer.

[0126] [Other embodiments] Each of the embodiments and variations described may be combined in any way.

[0127] The level shift circuits described in the second and fifth embodiments may also be used in the frequency synthesizers according to the first, third, fourth, and sixth embodiments.

[0128] The wireless communication device according to the seventh embodiment may include a frequency synthesizer according to any embodiment among the first to sixth. The wireless communication device in Figure 31 may include the frequency synthesizer 101A in Figure 16, the frequency synthesizer 101B in Figure 19, or the frequency synthesizer 101C in Figure 20 instead of the frequency synthesizers 101-1 and 101-2 configured similarly to the frequency synthesizer 101 in Figure 1. The wireless communication device in Figure 32 may include the frequency synthesizer 101E in Figure 26, the frequency synthesizer 101F in Figure 28, or the frequency synthesizer 101G in Figure 29 instead of the frequency synthesizers 101D-1 and 101D-2 configured similarly to the frequency synthesizer 101D in Figure 22.

[0129] In the examples in Figures 2 and 23, the case where the count value cnt increases with time was described, but the accumulator of the frequency synthesizer according to the embodiment may be configured so that the count value cnt decreases with time. Also, in the examples in Figures 2 and 23, the case where the ramp voltage Vrmp increases with time was described, but the digital-to-analog converter of the frequency synthesizer according to the embodiment may be configured so that the ramp voltage Vrmp decreases with time. [Industrial applicability]

[0130] A frequency synthesizer and wireless communication device according to one aspect of this disclosure are applicable to a mobile station or portable terminal device of a wireless communication system. [Explanation of symbols]

[0131] 11 Clock signal source 12 Accumulator 13. Digital-to-Analog Converter (DAC) 14,14A~14G signal generation circuit 15-1~15-6 Digital-to-Analog Converter (DAC) 16 Level Shift Circuit 17-1~17-6 Level Shift Circuit 18,18G Digital-to-Analog Converter (DAC) 21 Adder 22 Latch 31-1~31-(2 n -1) Switch 32-1~32-(2 n -1) Constant current source 33 switches 34 Constant current source 41-46 Differential amplifier 51 Constant current source 100 control circuits 101, 101A~101G, 101-1, 101-2, 101D-1, 101D-2 Frequency Synthesizer 102-1, 102-2, 102A-1, 102A-2 frequency multiplier 103 Circulator 104 Antenna 111,111A Transmitter Circuit 112 Digital-to-Analog Converter (DAC) 113 Low-pass filter (LPF) 114 Mixer 115 Digital-to-Analog Converter (DAC) 116 Low-pass filter (LPF) 117 Mixer 121 Mixer 122 Low-pass filter (LPF) 123 Analog-to-Digital Converter (ADC) 124, 124A receiving circuit 125 Mixer 126 Low-pass filter (LPF) 127 Analog-to-Digital Converter (ADC) R0,R11~R16,R21~R26,Ra~Rd Resistance Q1, Q2 Bipolar Transistors Q1A, Q2A Field-effect transistors

Claims

1. An accumulator that generates a count value that increases or decreases in a predetermined step size within a predetermined range in response to a clock signal, A digital-to-analog converter that generates a ramp voltage that increases or decreases according to the aforementioned count value, A frequency synthesizer comprising a signal generation circuit that generates an output frequency signal having a signal level that changes in a waveform similar to a sine wave or cosine wave according to the ramp voltage by analog signal processing, The aforementioned signal generation circuit is A first differential amplifier that generates a first differential output signal by comparing the ramp voltage with a first reference voltage, A second differential amplifier that generates a second differential output signal by comparing the ramp voltage with a second reference voltage that is higher than the first reference voltage, The system includes a third differential amplifier that compares the ramp voltage with a third reference voltage that is higher than the second reference voltage to generate a third differential output signal, The output frequency signal is the sum of the first and third differential output signals and the inverted signal of the second differential output signal. The aforementioned frequency synthesizer is A reference voltage source that generates the first reference voltage, The second and third reference voltages are further provided with voltage divider resistors that generate them from the power supply voltage and the first reference voltage, The reference voltage source has at least partially the same components and layout as the components and layout of the digital / analog converter. Frequency synthesizer.

2. Each of the first to third differential amplifiers comprises a pair of bipolar transistors or a pair of field-effect transistors. The frequency synthesizer according to claim 1.

3. An accumulator that generates a count value that increases or decreases in a predetermined step size within a predetermined range in response to a clock signal, A digital-to-analog converter that generates a ramp voltage that increases or decreases according to the aforementioned count value, A frequency synthesizer comprising a signal generation circuit that generates, by analog signal processing, a first output frequency signal having a signal level that changes in a waveform similar to a sine wave according to the ramp voltage, and a second output frequency signal having a signal level that changes in a waveform similar to a cosine wave according to the ramp voltage, The aforementioned signal generation circuit is A first differential amplifier that generates a first differential output signal by comparing the ramp voltage with a first reference voltage, A second differential amplifier that generates a second differential output signal by comparing the ramp voltage with a second reference voltage that is higher than the first reference voltage, A third differential amplifier that generates a third differential output signal by comparing the ramp voltage with a third reference voltage that is higher than the second reference voltage, A fourth differential amplifier that generates a fourth differential output signal by comparing the ramp voltage with a fourth reference voltage, A fifth differential amplifier that generates a fifth differential output signal by comparing the ramp voltage with a fifth reference voltage that is higher than the fourth reference voltage, The system includes a sixth differential amplifier that generates a sixth differential output signal by comparing the ramp voltage with a sixth reference voltage that is higher than the fifth reference voltage, The first output frequency signal is the sum of the first and third differential output signals and the inverted signal of the second differential output signal. The second output frequency signal is the sum of the fourth and sixth differential output signals and the inverted signal of the fifth differential output signal. The aforementioned frequency synthesizer is A reference voltage source that generates the fourth reference voltage, A first voltage divider resistor that generates the first to third reference voltages from the power supply voltage and the fourth reference voltage, The system further comprises a second voltage divider resistor that generates the fifth and sixth reference voltages from the power supply voltage and the fourth reference voltage, The reference voltage source has at least partially the same components and layout as the components and layout of the digital / analog converter. The first to sixth reference voltages satisfy V4 < V1 < V5 < V2 < V6 < V3, Here, V1 to V6 represent the first to sixth reference voltages, respectively. Frequency synthesizer.

4. Each of the first to sixth differential amplifiers comprises a pair of bipolar transistors or a pair of field-effect transistors. The frequency synthesizer according to claim 3.

5. The system further comprises at least one frequency multiplier for multiplying the frequency of the output frequency signal. The frequency synthesizer according to claim 1 or 2.

6. A first frequency multiplier for multiplying the frequency of the first output frequency signal, The system further comprises a second frequency multiplier for multiplying the frequency of the second output frequency signal. The frequency synthesizer according to claim 3 or 4.

7. A frequency synthesizer according to one of claims 1 to 6, Wireless communication device.

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