Fin-type field-effect transistor

Abstract

To provide a FinFET in which the influence on a threshold voltage due to thickness deviation or non-uniformity of the outermost fin is suppressed in a FinFET using a gallium oxide-based semiconductor as a semiconductor layer.SOLUTION: A fin field effect transistor 1 according to an embodiment includes a semiconductor layer 10 made of a gallium oxide-based semiconductor and having a plurality of fins 120, a gate electrode 14 formed on the side surface of each of the plurality of fins 120 with a gate insulating film 13 interposed therebetween, a source electrode 15 connected to the plurality of fins 120 side of the semiconductor layer 10, and a drain electrode 16 connected to the opposite side of the plurality of fins 120 of the semiconductor layer 10, and the outermost fin 120b of the plurality of fins 120 is a dummy fin to which the source electrode 15 is not electrically connected.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a fin-type field-effect transistor. [Background technology]

[0002] Conventionally, fin-type field-effect transistors (FinFETs) using Ga2O3 as the semiconductor layer are known (see Non-Patent Literature 1). According to Non-Patent Literature 1, the fins are formed using lithography and dry etching, similar to the manufacturing method of general FinFETs. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] W. Li et al., “Single and multi-fin normally-off Ga2O3 vertical transistors with a breakdown voltage over 2.6 kV”, 2019 IEEE IEDM, 2019, pp 12.4.1 - 12.4.4. [Overview of the project] [Problems that the invention aims to solve]

[0004] However, in the manufacturing process of FinFETs, when forming fins by processing semiconductor layers using dry etching, problems often arise such as the outermost fin becoming thicker than the others, or the outer surface of the outermost fin becoming rough, reducing the uniformity of its thickness. Since the thickness of the fins, including the channel region, affects the magnitude of the FinFET's threshold voltage, deviations or non-uniformity in the thickness of the outermost fins result in deviations in the FinFET's threshold voltage.

[0005] Here, when using a semiconductor material that can be p-type, such as Si, an inverted MOS channel FET can be formed in which the portion corresponding to the trench between the fins of a FinFET is composed of a p-type semiconductor region acting as an inverted MOS channel. The p-type semiconductor region acting as an inverted MOS channel is formed by injecting acceptor impurities into the semiconductor material, and the threshold voltage of the inverted MOS channel FET can be adjusted by controlling the concentration of the acceptor impurities.

[0006] On the other hand, gallium oxide-based semiconductors such as Ga2O3 cannot be made p-type or are extremely difficult to manufacture. Therefore, when using gallium oxide-based semiconductors, it is difficult to manufacture inverting MOS channel FETs equipped with inverting MOS channel FETs composed of p-type semiconductor regions, and adjusting the threshold voltage using the p-type semiconductor region is difficult. For this reason, in order to obtain the desired threshold voltage in a FinFET that can be manufactured using gallium oxide-based semiconductors, the thickness of the fins must be precisely controlled, and deviations or non-uniformity in the thickness of the outermost fins become a major obstacle to obtaining the desired threshold voltage.

[0007] The object of the present invention is to provide a FinFET using a gallium oxide-based semiconductor as the semiconductor layer, wherein the influence of deviations and non-uniformity in the thickness of the outermost fin on the threshold voltage is suppressed. [Means for solving the problem]

[0008] One aspect of the present invention provides the following fin-type field-effect transistor to achieve the above objective.

[0009] [1] A fin-type field-effect transistor comprising: a semiconductor layer made of a gallium oxide semiconductor having a plurality of fins; a gate electrode formed on each side surface of the plurality of fins via a gate insulating film; a source electrode connected to the plurality of fins side of the semiconductor layer; and a drain electrode connected to the opposite side of the plurality of fins of the semiconductor layer, wherein the outermost fin of the plurality of fins is a dummy fin to which the source electrode is not electrically connected. [2] The fin-type field-effect transistor according to [1], wherein the source electrode is not electrically connected to at least a portion of the planar end of the inner fin of the dummy fin among the plurality of fins. [3] The fin-type field-effect transistor according to [1] or [2] above, wherein the source electrode covers the upper part of the dummy fin and an insulating film is formed between the upper end of the dummy fin and the source electrode. [4] The fin-type field-effect transistor according to [3] above, wherein the height of the dummy fin is lower than the height of the other fins among the plurality of fins. [5] The fin-type field-effect transistor according to [1] or [2] above, wherein a high-resistance region containing acceptor impurities is formed at the upper end of the dummy fin, and the source electrode is in contact with the high-resistance region. [6] The fin-type field-effect transistor according to [1] or [2] above, wherein the source electrode does not cover the upper part of the dummy fin. [7] The fin-type field-effect transistor according to [6] above, wherein the dummy fin is arranged to surround the inner fin of the plurality of fins from all sides. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a FinFET using a gallium oxide-based semiconductor as the semiconductor layer, in which the influence on the threshold voltage due to deviations and non-uniformity in the thickness of the outermost fin is suppressed. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1(a) is a vertical cross-sectional view of a fin-type field-effect transistor (FinFET) according to the first embodiment of the present invention. Figures 1(b) and (c) are schematic diagrams showing examples of the planar positional relationship between the fins and the source electrode in a FinFET according to the first embodiment of the present invention, respectively. [Figure 2]FIG. 2 is a scanning electron microscope (SEM) observation image of a cross section of an epitaxial layer immediately after fins are formed by dry etching. [Figure 3] FIG. 3(a) is a graph showing a gate current Ig and a drain current Id with respect to a gate voltage in a comparative sample. FIG. 3(b) is a graph showing a gate current Ig and a drain current Id with respect to a gate voltage in a FinFET having a source electrode with the shape shown in FIG. 1(b). [Figure 4] FIG. 4 is a schematic diagram showing an example of the positional relationship in the planar direction between a fin and a source electrode in a modified example of a FinFET according to the first embodiment of the present invention. [Figure 5] FIG. 5(a) is a vertical cross-sectional view of a FinFET according to the second embodiment of the present invention. FIGS. 5(b) and (c) are schematic diagrams showing examples of the positional relationship in the planar direction between a fin, a source electrode, and an insulating film in a FinFET according to the second embodiment of the present invention. [Figure 6] FIG. 6 is a vertical cross-sectional view of a modified example of a FinFET according to the second embodiment of the present invention. [Figure 7] FIG. 7(a) is a vertical cross-sectional view of a FinFET according to the third embodiment of the present invention. FIGS. 7(b) and (c) are schematic diagrams showing examples of the positional relationship in the planar direction between a fin, a source electrode, and a high-resistance region in a FinFET according to the third embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0012] 〔First Embodiment〕 (Configuration of Fin-Type Field-Effect Transistor) FIG. 1(a) is a vertical cross-sectional view of a fin-type field-effect transistor (FinFET) 1 according to the first embodiment of the present invention. FinFET 1 is a vertical FinFET including a semiconductor layer made of a gallium oxide-based semiconductor.

[0013] The gallium oxide-based semiconductor refers to Ga2O3 or Ga2O3 to which elements such as Al and In are added. For example, the gallium oxide-based semiconductor is (Ga , + , + ,

[0017] , Al y In (1-x-y) It has a composition represented by )2O3(0 < x ≤ 1, 0 ≤ y ≤ 1, 0 < x + y ≤ 1). When Al is added to Ga2O3, the bandgap widens, and when In is added, the bandgap narrows.

[0014] FinFET1 is composed of a gallium oxide-based semiconductor and includes a semiconductor layer 10 having a plurality of fins 120, a gate electrode 14 formed via a gate insulating film 13 on each side surface of the plurality of fins 120, a source electrode 15 connected to the side of the plurality of fins 120 of the semiconductor layer 10 (i.e., the upper side in FIG. 1(a)), and a drain electrode 16 connected to the opposite side of the plurality of fins 120 of the semiconductor layer 10 (i.e., the lower side in FIG. 1(a)). Also, an interlayer insulating film 17 is formed between and around the plurality of fins 120.

[0015] Here, let the outermost one of the plurality of fins 120 be fin 120b, and the one inside fin 120b be fin 120a. In FinFET1, the source electrode 15 does not cover above fin 120b and is not in contact with fin 120b. That is, in FinFET1, the outermost fin 120b is a dummy fin to which the source electrode 15 is not electrically connected. Typically, each of the plurality of fins 120 has a linear pattern and is arranged parallel to each other. [[ID=H14]]<00H116>

[0016] Typically, as shown in FIG. 1(a), the semiconductor layer 10 is composed of a substrate 11 made of a gallium oxide-based semiconductor and an epitaxial layer 12 made of a gallium oxide-based semiconductor formed on the substrate 11. In this case, the plurality of fins 120 are formed in the epitaxial layer 12.

[0017] The semiconductor layer 10 is an n-type layer containing donor impurities such as Si and Sn. At the upper end of fin 120a, an n + region 121 with a particularly high concentration of donor impurities is formed, and n +The source electrode 15 is connected to region 121. Note that, due to the manufacturing process, the upper end of the dummy fin 120b also contains n with a high concentration of donor impurities. + Region 121 may be formed, but n of fin 120b + The source electrode 15 is not connected to region 121.

[0018] The fins 120 are formed by processing the semiconductor layer 10 using lithography such as electron beam lithography or photolithography and dry etching. As described above, when the fins 120 are formed by dry etching, problems tend to occur such as the outermost fin 120b becoming thicker than the inner fin 120a, or the outer surface of the fin 120b becoming rough and reducing the uniformity of its thickness.

[0019] Figure 2 is a scanning electron microscope (SEM) image of a cross-section of the epitaxial layer 12 immediately after the fins 120 were formed by dry etching. The mask 50 on the fins 120 is an etching mask used for patterning the epitaxial layer 12 by dry etching. Figure 2 shows that the thickness of the outermost fin 120b is greater than the thickness of the inner fin 120a, and that the outer side surface 122 of fin 120b is rough and uneven, indicating that the thickness uniformity of fin 120b is lower than that of fin 120a.

[0020] As mentioned above, unlike inverting MOS channel FETs manufactured using p-type semiconductor materials such as Si, it is difficult to adjust the threshold voltage using the p-type semiconductor region in FinFETs. Therefore, in order to obtain the desired threshold voltage in FinFETs that can be manufactured using gallium oxide semiconductors, the thickness of the fins must be precisely controlled, and deviations or non-uniformity in the thickness of the outermost fins become a major obstacle to obtaining the desired threshold voltage.

[0021] Therefore, in FinFET1, the outermost fin 120b is made a dummy fin to which the source electrode 15 is not electrically connected, thereby preventing defects such as deviations in the threshold voltage of FinFET1 caused by variations in the thickness or non-uniformity of the fin 120b.

[0022] Figures 1(b) and 1(c) are schematic diagrams showing examples of the planar positional relationship between the fin 120 and the source electrode 15 in the FinFET 1, respectively. Figures 1(b) and 1(c) show the shape and position of the fin 120 and the source electrode 15 when viewed from above the FinFET 1. As shown in the examples in Figures 1(b) and 1(c), in the FinFET 1, the source electrode 15 does not cover the upper part of the fin 120b and does not contact the fin 120b. The region 151 of the source electrode 15 is a region located outside the region covering the upper part of the fin 120 for connecting contact plugs and lead wires from above.

[0023] Furthermore, in the example shown in Figure 1(c), the source electrode 15 does not cover or contact with any portion of the planar ends of the fin 120a (i.e., the right and left ends in Figure 1(c)). Therefore, even if there is an increase in thickness or roughness on the sides of the fin 120a at its planar ends, the source electrode 15 is not electrically connected to this portion, thus preventing defects such as deviations in the threshold voltage of the FinFET1 caused by thickness variations or non-uniformity at the planar ends of the fin 120a. For this reason, it is preferable that the source electrode 15 does not cover or electrically connect to at least a portion of the planar ends of the fin 120a.

[0024] As shown in Figure 1(c), if a region is provided at the planar end of the fin 120a where the source electrode 15 is not connected, if this region is too small, the above-mentioned effect of providing this region will be insufficient, and if it is too large, it may affect the operation of the FinFET1. For this reason, the planar length L1 of the region at the planar end of the fin 120a where the source electrode 15 is not connected is set to, for example, within the range of 1 to 10 μm.

[0025] Note that the source electrode 15 shown in FIGS. 1(b) and 1(c) may not include the region 151. In this case, a contact plug or a wire for extraction is connected to a region covering the fin 120 of the source electrode 15.

[0026] The gate insulating film 13 is made of an insulator such as HfO2, Al2O3, or SiO2. The gate electrode 14 is preferably made of a metal with a high work function such as Cr, Pt, or Ni. The source electrode 15 and the drain electrode 16 are, for example, composed of an electrode laminate structure that makes an ohmic contact with the semiconductor layer 10 such as Ti / Au or Ti / Al. The interlayer insulating film 17 is made of an insulator such as SiO2, SiN, or HfO2.

[0027] FinFET1 may have either normally-off characteristics or normally-on characteristics. For example, when FinFET1 has normally-off characteristics, when a voltage is applied to the gate electrode 14, channels are formed in each of the fins 120 sandwiched from both sides by the gate electrode 14, and current flows between the source electrode 15 and the drain electrode 16.

[0028] In FinFET1, for example, the donor concentration of the substrate 11 is 5×10 17 cm -3 or more, and the donor concentration of the n + region 121 is 1×10 18 cm -3 or more, and the height of the fin 120 is 1 μm or more. Also, when FinFET1 has normally-off characteristics, for example, the donor concentration of the epitaxial layer 12 is 1×10 16 cm -3 or less, the gate insulating film 13 is a HfO2 film with a thickness of 100 nm or less, the gate electrode 14 is made of Cr, and the thickness of the fin 120a is 500 nm or less.

[0029] The threshold voltage V th of FinFET1 is obtained by the following formula (1). Here, φ BV is the barrier height determined by the material of the gate electrode 14 and the material of the gate insulating film 13. OX ΔE is the voltage of the gate insulating film 13, which is determined by the donor concentration of fin 120, the material of the gate insulating film 13, and the thickness of the gate insulating film 13. C φ is the amount of band discontinuity on the conductor side, which is determined by the material of the gate insulating film 13 and the material of the fin 120. S E is the work function of fin 120, which is determined by the donor concentration, thickness, and dielectric constant of fin 120. F This is the Fermi energy determined by the donor concentration and temperature of fin 120.

[0030]

number

[0031] If the distance between fins 120a and 120b is too large, fin 120a will also experience the same increase in thickness and surface roughness as fin 120b. The effect of making fin 120b a dummy fin in this invention is particularly significant when the increase in thickness and surface roughness occur almost exclusively on fin 120b. For this reason, it is preferable that the distance between fins 120a and fin 120b be relatively small, for example, 10 μm or less. Typically, all fins 120 are formed at equal intervals. In this case, it is preferable that the distance between fins 120 is 10 μm or less.

[0032] (Evaluation of fin-type field-effect transistors) The characteristics of FinFET1, in which fin 120b is a dummy fin, and a comparative FinFET (hereinafter referred to as the comparative sample), in which the source electrode 15 covers the top of fin 120b and is connected to fin 120b, were measured and compared. The configuration of the comparative sample is the same as that of FinFET1, except that fin 120b is connected to the source electrode 15.

[0033] Figure 3(a) shows the gate current I as a function of the gate voltage in the comparative sample. g and drain current I dThis is a graph showing the relationship between gate voltage and gate current I in a FinFET1 equipped with a source electrode 15 having the shape shown in Figure 1(b). g and drain current I d This is a graph showing that.

[0034] According to Figure 3(a), the drain current I d From the time the current starts to increase until it saturates, there is a large step that is thought to be due to the thickness difference or non-uniformity of fin 120b. On the other hand, according to Figure 3(b), the drain current I d There is no step in the transition from when the value begins to increase until it saturates. This is thought to be because the source electrode 15 is not connected to the fin 120b, and therefore there is no influence from variations or non-uniformity in the thickness of the fin 120b.

[0035] (modified version) Figure 4 is a schematic diagram showing an example of the planar positional relationship between the fin 120 and the source electrode 15 in a modified version of FinFET1. Figure 4 shows the shapes of the fin 120 and the source electrode 15 when viewed from above FinFET1.

[0036] As shown in Figure 4, in FinFET1, the dummy fin 120b may be arranged to surround the inner fin 120a from all sides. By arranging fin 120b to surround fin 120a from all sides, it is possible to suppress the increase in thickness and roughness of the sides at the planar ends of fin 120a (i.e., the right and left ends in Figure 4).

[0037] In the example shown in Figure 4, the fin 120b surrounding the fin 120a from all sides is composed of a single continuous dummy fin, but it may also be composed of multiple dummy fins.

[0038] [Second Embodiment] The second embodiment of the present invention differs from the first embodiment in a structure for avoiding electrical connection between the source electrode 15 and the fin 120b. The same aspects as those of the first embodiment will be omitted or simplified in their description.

[0039] Figure 5(a) is a vertical cross-sectional view of a FinFET2 according to a second embodiment of the present invention. The FinFET2 is a vertical FinFET equipped with a semiconductor layer made of a gallium oxide-based semiconductor.

[0040] FinFET2, like FinFET1, is made of a gallium oxide semiconductor and comprises a semiconductor layer 10 having a plurality of fins 120, a gate electrode 14 formed on each side of the plurality of fins 120 via a gate insulating film 13, a source electrode 15 connected to the plurality of fins 120 side of the semiconductor layer 10, and a drain electrode 16 connected to the opposite side of the plurality of fins 120 of the semiconductor layer 10. In addition, an interlayer insulating film 17 is formed between and around the plurality of fins 120.

[0041] In FinFET2, the source electrode 15 covers the top of the fin 120b, but an insulating film 21 is formed between the upper end of the fin 120b and the source electrode 15, and the insulating film 21 insulates the source electrode 15 from the fin 120b. In other words, in FinFET2, as with FinFET1, the outermost fin 120b is a dummy fin to which the source electrode 15 is not electrically connected. The insulating film 21 is made of an insulator such as SiO2, SiN, HfO2, or Al2O3.

[0042] In FinFET2, as with FinFET1, the outermost fin 120b is made a dummy fin to which the source electrode 15 is not electrically connected, thereby preventing defects such as deviations in the threshold voltage of FinFET2 caused by variations in the thickness or non-uniformity of the fin 120b.

[0043] Figures 5(b) and (c) are schematic diagrams showing examples of the planar positional relationship between the fin 120, source electrode 15, and insulating film 21 in FinFET2. Figure 5(b) shows the shape and position of the fin 120, source electrode 15, and insulating film 21 when viewed from above FinFET2. As shown in the examples in Figures 5(b) and (c), in FinFET2, the source electrode 15 covers the top of the fin 120b, but the source electrode 15 and the fin 120b are insulated by the insulating film 21.

[0044] Furthermore, in the example shown in Figure 5(c), an insulating film 21 is also formed between the upper ends of the planar ends of the fin 120a (i.e., the right and left ends in Figure 5(c)) and the source electrode 15 to insulate them. Therefore, even if there is an increase in thickness or roughness on the side surface at the planar ends of the fin 120a, the source electrode 15 is not electrically connected to this portion, thus preventing defects such as deviations in the threshold voltage of the FinFET2 caused by thickness variations or non-uniformity at the planar ends of the fin 120a. For this reason, it is preferable that the source electrode 15 is not electrically connected to at least a portion of the planar ends of the fin 120a by the insulating film 21.

[0045] As shown in Figure 5(c), if a region is provided at the planar end of the fin 120a where the source electrode 15 is not connected, if this region is too small, the above-mentioned effect of providing this region will be insufficient, and if it is too large, it may affect the operation of the FinFET1. For this reason, the planar length L2 of the region at the planar end of the fin 120a where the source electrode 15 is not connected is set to, for example, within the range of 1 to 10 μm.

[0046] The source electrode 15 shown in Figures 5(b) and 5(c) may have a region 151 located outside the region covering the upper part of the fin 120 for connecting a contact plug or lead wire from above.

[0047] (modified version) Figure 6 is a vertical cross-sectional view of a modified FinFET2. In FinFET2, as shown in Figure 6, the height of fin 120b may be lower than the height of fin 120a. In this case, for example, an interlayer insulating film 17 is formed between the upper end of fin 120b and the source electrode 15 covering its upper portion, and the interlayer insulating film 17 insulates the source electrode 15 from fin 120b.

[0048] Furthermore, the height of at least a portion of the planar end of fin 120a may be lower, similar to fin 120b. In this case, an interlayer insulating film 17 is also formed between the upper end of the lowered portion of the planar end of fin 120a and the source electrode 15 covering that portion. Therefore, even if there is an increase in thickness or roughness on the side surface at the planar end of fin 120a, the source electrode 15 is not electrically connected to this portion, thus preventing defects such as deviations in the threshold voltage of FinFET2 caused by thickness variations or non-uniformity at the planar end of fin 120a. For this reason, it is preferable that the source electrode 15 is not electrically connected to at least a portion of the planar end of fin 120a by the interlayer insulating film 17.

[0049] [Third Embodiment] A third embodiment of the present invention differs from the first embodiment in a structure for avoiding electrical connection between the source electrode 15 and the fin 120b. The same aspects as those of the first embodiment will be omitted or simplified in their description.

[0050] Figure 7(a) is a vertical cross-sectional view of a FinFET3 according to a third embodiment of the present invention. The FinFET3 is a vertical FinFET equipped with a semiconductor layer made of a gallium oxide-based semiconductor.

[0051] FinFET3, like FinFET1, is made of a gallium oxide semiconductor and comprises a semiconductor layer 10 having a plurality of fins 120, a gate electrode 14 formed on each side of the plurality of fins 120 via a gate insulating film 13, a source electrode 15 connected to the plurality of fins 120 side of the semiconductor layer 10, and a drain electrode 16 connected to the opposite side of the plurality of fins 120 of the semiconductor layer 10. In addition, an interlayer insulating film 17 is formed between and around the plurality of fins 120.

[0052] In FinFET3, a high-resistance region 123 containing acceptor impurities is formed at the upper end of fin 120b, and the source electrode 15 is in contact with the high-resistance region 123. Therefore, although the source electrode 15 is in contact with fin 120b, it is insulated by the high-resistance region 123. In other words, in FinFET3, as with FinFET1, the outermost fin 120b is a dummy fin to which the source electrode 15 is not electrically connected. The high-resistance region 123 is formed, for example, by ion implantation of acceptor impurities such as N and Mg.

[0053] In FinFET3, as with FinFET1, the outermost fin 120b is made a dummy fin to which the source electrode 15 is not electrically connected, thereby preventing defects such as deviations in the threshold voltage of FinFET3 caused by variations in the thickness or non-uniformity of the fin 120b.

[0054] Figures 7(b) and 7(c) are schematic diagrams showing an example of the planar positional relationship between the fin 120, source electrode 15, and high-resistance region 123 in the FinFET3. Figures 7(b) and 7(c) show the shape and position of the fin 120, source electrode 15, and high-resistance region 123 when viewed from above the FinFET3. As shown in the example in Figures 7(b) and 7(c), in the FinFET3, the source electrode 15 covers the top of the fin 120b, but the source electrode 15 and the fin 120b are insulated by the high-resistance region 123.

[0055] Furthermore, in the example shown in Figure 7(c), a high-resistance region 123 is also formed at the upper end of the planar end of the fin 120a (i.e., the right and left ends in Figure 7(c)) to insulate the fin 120a from the source electrode 15. Therefore, even if there is an increase in thickness or roughness on the side surface at the planar end of the fin 120a, the source electrode 15 is not electrically connected to this portion, thus preventing defects such as deviations in the threshold voltage of the FinFET3 caused by thickness variations or non-uniformity at the planar end of the fin 120a. For this reason, it is preferable that the source electrode 15 is not electrically connected to at least a portion of the planar end of the fin 120a due to the high-resistance region 123.

[0056] As shown in Figure 7(c), if a region is provided at the planar end of the fin 120a where the source electrode 15 is not connected, if this region is too small, the above-mentioned effect of providing this region will be insufficient, and if it is too large, it may affect the operation of the FinFET1. For this reason, the planar length L3 of the region at the planar end of the fin 120a where the source electrode 15 is not connected is set to, for example, within the range of 1 to 10 μm. Note that the length L3 is equal to the planar length of the high-resistance region 123 in the fin 120a.

[0057] Note that the source electrode 15 shown in Figures 7(b) and 7(c) does not necessarily have to include region 151. In this case, the contact plug and lead wire are connected to the region covering the area above the fin 120 of the source electrode 15.

[0058] (Effects of the embodiment) According to the FinFETs 1 to 3 of the first to third embodiments described above, by making the outermost fin 120b of the plurality of fins 120 a dummy fin to which the source electrode 15 is not electrically connected, the influence of thickness variations and non-uniformity of the fin 120b on the threshold voltage can be suppressed. Furthermore, by ensuring that the source electrode 15 is not connected to at least a portion of the planar end of the fin 120a, the influence of thickness variations and non-uniformity of the planar end of the fin 120a on the threshold voltage can be suppressed.

[0059] Although embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention. Furthermore, the components of the above embodiments can be arbitrarily combined without departing from the spirit of the invention. Moreover, the embodiments described above do not limit the invention as claimed. It should also be noted that not all combinations of features described in the embodiments are necessarily essential for solving the problem of the invention. [Explanation of Symbols]

[0060] 1, 2, 3…FinFET, 10…Semiconductor layer, 11…Substrate, 12…Epitaxial layer, 120, 120a, 120b…Fin, 121…n + Region, 123…High-resistance region, 13…Gate insulating film, 14…Gate electrode, 15…Source electrode, 16…Drain electrode, 17…Interlayer insulating film, 21…Insulating film

Claims

1. A semiconductor layer made of gallium oxide-based semiconductor material and having multiple fins, A gate electrode formed on each side surface of the plurality of fins via a gate insulating film, Source electrodes connected to the plurality of fins on the semiconductor layer, A drain electrode connected to the opposite side of the plurality of fins of the semiconductor layer, Equipped with, The outermost fin among the plurality of fins is a dummy fin to which the source electrode is not electrically connected. Fin-type field-effect transistor.

2. The source electrode is not electrically connected to at least a portion of the planar end of the inner fin of the dummy fin among the plurality of fins. The fin-type field-effect transistor according to claim 1.

3. The source electrode covers the top of the dummy fin, An insulating film is formed between the upper end of the dummy fin and the source electrode. A fin-type field-effect transistor according to claim 1 or 2.

4. The height of the dummy fin is lower than the height of the other fins among the plurality of fins. The fin-type field-effect transistor according to claim 3.

5. A high-resistance region containing acceptor impurities is formed at the upper end of the dummy fin. The source electrode is in contact with the high-resistance region. A fin-type field-effect transistor according to claim 1 or 2.

6. The source electrode does not cover the upper part of the dummy fin. A fin-type field-effect transistor according to claim 1 or 2.

7. The dummy fin is arranged so as to surround the inner fin of the plurality of fins from all four sides. The fin-type field-effect transistor according to claim 6.

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