Gaming machine

Abstract

To suitably execute processing in control means.SOLUTION: In setting change processing, a set value to be selected is changed each time when a pressing operation of a reset button is started. The pressing operation of a reset button is monitored periodically, data stored in a reset present state storage area are shifted to a reset previous storage area when the monitoring is performed, and current monitoring result data are stored in the reset present state storage area. Contents of the reset previous storage area are non-operation data, and it is determined that the pressing operation of the reset button is started when contents of the reset current storage area are data for generating operation. In this case, before execution of first determination regarding whether or not the pressing operation of the reset button is started when starting setting change processing, the monitoring is executed twice and monitoring result information of the reset button is stored in each area in the above.SELECTED DRAWING: Figure 9

Description

Technical Field

[0005] , , ,

[0001] The present invention relates to a gaming machine.

Background Art

[0002] As gaming machines, pachinko machines and slot machines are known. For example, a pachinko machine includes a storage unit for storing game balls, and the game balls stored in the storage unit are guided to a game ball launching device and launched toward the game area in response to the player's launching operation. Then, when a game ball enters a ball entry unit provided in the game area, for example, a lottery process is executed, or for example, a process for increasing the number of game balls available to the player is executed.

[0003] In a slot machine, when a start lever is operated to start a new game in a situation where a game value such as a medal is bet, a lottery process is executed by control means. Further, when the lottery process is executed, rotation start control is executed by the control means to start the rotation of the reel, and when a stop button is operated during the rotation of the reel, rotation stop control is executed by the control means to stop the rotation of the reel. Then, when the stop result after the rotation stop of the reel corresponds to the winning combination of the lottery process, a privilege corresponding to the winning combination is given to the player (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Here, in a gaming machine such as the above example, it is necessary that the processing in each game is preferably executed, and there is still room for improvement in this regard.

[0006] The present invention has been made in view of the circumstances illustrated above, and aims to provide a gaming machine that enables the processing in each game to be executed appropriately. [Means for solving the problem]

[0007] To solve the above problems, the invention described in claim 1 provides a value information storage area capable of storing value information relating to the number of game values, A predetermined display control means that controls a predetermined display means to display a value information corresponding to the value information stored in the value information storage area, A game execution means that controls the game execution means so that a game unit operation is started when a trigger for starting a game occurs, and the game unit operation is terminated when a trigger for ending a game occurs. A game response execution means that executes game response processing using the value information after the completion of the game unit operation, A value information erasure means for erasing the value information stored in the value information storage area after the completion of the game unit operation and before the execution of the game corresponding processing, Within the scope of one game, before the value information stored in the value information storage area is erased by the value information erasure means, a separate storage execution means causes the value information stored in the value information storage area to be stored in a separate storage area, Equipped with, The aforementioned game-related execution means executes the game-related processing using the value information stored in the separate storage area. The process of storing the value information in the separate storage area by the separate storage execution means is characterized in that it is performed after the completion of the game unit operation and before the value information stored in the value information storage area is erased by the value information erasure means. [Effects of the Invention]

[0008] According to the present invention, it becomes possible to ensure that processing in each game is executed optimally. [Brief explanation of the drawing]

[0009] [Figure 1] This is a front view of the slot machine in the first embodiment. [Figure 2] This is a perspective view of a slot machine with the front door open. [Figure 3] This is a front view of the enclosure. [Figure 4] This diagram shows the arrangement of symbols on each reel. [Figure 5] This is an explanatory diagram showing the relationship between the patterns visible through the display window and the combination lines. [Figure 6] This is an explanatory diagram showing the relationship between the type of prize awarded and the benefits that are granted. [Figure 7] (a) This is a front view of the common display area, and (b) This is an explanatory diagram for explaining the content of the information corresponding to the stop order displayed on the shared display unit. [Figure 8] (a) and (b) are explanatory diagrams illustrating the relationship between the notification content of the stop order in the image display device and the display content of the stop order in the combined display unit. [Figure 9] This is an electrical diagram of a slot machine. [Figure 10] This is a flowchart showing the main processing performed on the primary MPU. [Figure 11] This is an explanatory diagram illustrating the signal path for power outage signals. [Figure 12] (a)~(e) This is a time chart showing how, once the main process starts, the process waits until the power outage signal reaches a HI level. [Figure 13] This flowchart shows the power outage processing performed by the main MPU. [Figure 14] (a)~(d) This is a time chart showing how to identify an information anomaly in the main RAM using information anomaly flags. [Figure 15] This flowchart shows the configuration change process executed on the main MPU. [Figure 16]It is an explanatory diagram for explaining the content of the storage area of the main-side RAM. [Figure 17] (a) - (h) It is a time chart showing the state where the clear process of the main-side RAM is executed in the setting change process. [Figure 18] It is a flowchart showing the setting change execution process executed by the main-side MPU. [Figure 19] It is a flowchart showing the timer interrupt process executed by the main-side MPU. [Figure 20] (a) It is a flowchart showing the sensor monitoring process executed by the main-side MPU, and (b) it is an explanatory diagram for explaining the content of the storage area provided in the main-side RAM. [Figure 21] (a) - (k) It is a time chart showing the state where the set value selected by the pressing operation of the reset button that is maintained when the supply of operating power is started does not change. [Figure 22] It is a flowchart showing the monitoring process of the door opening sensor executed by the main-side MPU. [Figure 23] It is a flowchart showing the notification process executed by the main-side MPU. [Figure 24] (a) - (i) It is a time chart showing the state where various notifications are executed when the supply of operating power is started and the setting change process is executed. [Figure 25] It is a flowchart showing the normal process executed by the main-side MPU. [Figure 26] It is a flowchart showing the start waiting process executed by the main-side MPU. [Figure 27] It is a flowchart showing the bed corresponding process executed by the main-side MPU. [Figure 28] It is a flowchart showing the control process of the bed display unit executed by the main-side MPU. [Figure 29] It is an explanatory diagram for explaining the content of the index value. [Figure 30]This is an explanatory diagram illustrating the relationship between the stopping order of the reels and the resulting winning combinations. [Figure 31] (a) This is an explanatory diagram illustrating the contents of the data in the main ROM used for the lottery process for determining the winning combination, and (b) This is an explanatory diagram illustrating the contents of the storage area in the main RAM used for the lottery process for determining the winning combination. [Figure 32] This is an explanatory diagram to explain the contents of the role selection tables. [Figure 33] (a) This is an explanatory diagram for the data set for IV=1, (b) This is an explanatory diagram for the data set for IV=16, and (c) This is an explanatory diagram for the data set for IV=17. [Figure 34] This flowchart shows the role selection process executed on the main MPU. [Figure 35] This flowchart shows the process of obtaining the judgment value, which is executed on the main MPU. [Figure 36] This flowchart shows the PV acquisition process performed on the main MPU. [Figure 37] This is a flowchart showing the process of acquiring winning data executed by the main MPU. [Figure 38] This flowchart shows the reel control process executed by the main MPU. [Figure 39] This is a flowchart showing the processing performed by the main MPU when a game ends. [Figure 40] This is an explanatory diagram for describing the game states and game intervals that exist in a slot machine. [Figure 41] (a) This is an explanatory diagram for explaining the first and second sections, and (b) This is an explanatory diagram for explaining the contents of each game state in the second section. [Figure 42] (a) An explanatory diagram for explaining the first CB role and the second CB role, and (b) An explanatory diagram for explaining the first CB state and the second CB state. [Figure 43] This is a flowchart showing the first control process for the game section, which is executed by the main MPU. [Figure 44]This flowchart shows the second control process for the game section, which is executed by the main MPU. [Figure 45] This flowchart shows the ending processing performed on the main MPU. [Figure 46] This flowchart shows the advantage lottery process performed by the main MPU at the start of the game. [Figure 47] This flowchart shows the normal processing performed on the primary MPU. [Figure 48] (a) This is an explanatory diagram for explaining the probability of selecting the game count mode, and (b) This is an explanatory diagram for explaining the probability of selecting the winning rate mode. [Figure 49] (a) An explanatory diagram for explaining the latch area; (b) An explanatory diagram for explaining an example of a second random number stored in the latch area; (c) An explanatory diagram for explaining an example of a high-order byte; (d) An explanatory diagram for explaining an example of a 7-bit random number. [Figure 50] This flowchart shows the second startup configuration process executed on the main MPU. [Figure 51] (a) This is an explanatory diagram for explaining the game count mode lottery table, and (b) This is an explanatory diagram for explaining the winning rate mode lottery table. [Figure 52] This flowchart shows the LV acquisition process executed on the main MPU. [Figure 53] This flowchart shows the freeze setting process performed by the main MPU during bonus transitions. [Figure 54] (a) to (e) are time charts showing how the freeze period is set. [Figure 55] This flowchart shows the process for establishing an advantageous state at the start of the game, which is executed on the main MPU. [Figure 56] This flowchart shows the processing for the pseudo-bonus that is executed on the main MPU. [Figure 57] This flowchart shows the clearing process performed by the main MPU at the end of the bonus round. [Figure 58](a) to (e) This is a time chart showing the timing of the execution of various processes when the pseudo-bonus state ends. [Figure 59] This flowchart shows the processing for the AT state at the start of the game, which is executed on the main MPU. [Figure 60] This flowchart shows the AT-specific processing performed on the main MPU. [Figure 61] This flowchart shows the external output setting process executed by the main MPU. [Figure 62] This flowchart shows the processing for external output performed on the main MPU. [Figure 63] (a) to (h) are time charts showing how the output modes of the first and second external signals are changed as appropriate. [Figure 64] This is an explanatory diagram illustrating the electrical configuration of the main MPU in the second embodiment. [Figure 65] (a) and (b) are explanatory diagrams illustrating the state of the jump status flag when a predetermined memory area is cleared to "0" by the CLR execution circuit. [Figure 66] (a) and (b) are explanatory diagrams illustrating the state of the jump status flag when the value of a specific memory area is deducted by 1 by the DEC execution circuit. [Figure 67] (a) This is an explanatory diagram for illustrating the data structure of the JR instruction, and (b) This is an explanatory diagram for illustrating the data structure of the JRS instruction. [Figure 68] This is an explanatory diagram illustrating an example of the contents of a program in which both the JR instruction and the JRS instruction are executed as JP instructions. [Figure 69] (a) to (c) are explanatory diagrams illustrating the stack area provided in the main RAM in the third embodiment. [Figure 70] This flowchart shows the advantage lottery process performed by the main MPU at the start of the game. [Figure 71] This flowchart shows the process for establishing an advantageous state at the start of the game, which is executed on the main MPU. [Figure 72] This flowchart shows the processing for the AT state at the start of the game, which is executed on the main MPU. [Figure 73] This flowchart shows the ending determination process executed on the main MPU. [Figure 74] This flowchart shows the ending determination process for the comparative example. [Figure 75] This flowchart shows the process for achieving an advantageous state at the start of the game in the comparative example. [Figure 76] This is a flowchart showing the weight period calculation process performed by the main MPU in the fourth embodiment. [Figure 77] (a) to (c) are explanatory diagrams to illustrate the details of the subtraction process for the weight counter. [Figure 78] This flowchart shows the medal monitoring process performed on the main MPU. [Figure 79] (a) to (c) are explanatory diagrams to explain the process of adding the monitoring period counter, and (d) is an explanatory diagram to explain the process of comparing the case where the monitoring period counter is added without executing the "SBC" instruction. [Figure 80] This flowchart shows the weight period calculation process performed by the main MPU in the fifth embodiment. [Figure 81] (a) and (b) are explanatory diagrams illustrating the process of adding weights to the counter. [Figure 82] This flowchart shows the medal monitoring process performed on the main MPU. [Figure 83] (a) and (b) are explanatory diagrams for explaining the process of subtracting the monitoring period counter, and (c) is an explanatory diagram for explaining a comparative example in which the monitoring period counter subtraction process is performed without executing the "ADC" instruction. [Figure 84] This is a flowchart showing the main processing performed by the main MPU in the sixth embodiment. [Figure 85]This is a flowchart showing the main processing performed by the main MPU in the seventh embodiment. [Modes for carrying out the invention]

[0010] <First Embodiment> Hereinafter, a first embodiment in which the present invention is applied to a slot machine 10, a type of amusement machine, will be described in detail with reference to the drawings. Figure 1 is a front view of the slot machine 10, Figure 2 is a perspective view of the slot machine 10 with the front door 12 open, and Figure 3 is a front view of the housing 11.

[0011] As shown in Figures 2 and 3, the slot machine 10 includes a housing 11 that forms its outer shell. The housing 11 is formed as a box shape that is open to the front by fixing a plurality of wooden panels together.

[0012] As shown in Figures 1 and 2, a front door 12 is attached to the front side of the housing 11. The front door 12 is supported by the housing 11, with a pivot point 15 located on the left side of the housing 11, allowing the internal space of the housing 11 to be opened and closed. The front door 12 is locked in a non-opening state by a locking device 13 located on its back surface, and this locked state is released by unlocking with a predetermined key on the key cylinder 14.

[0013] A door open sensor 16 is provided on the top of the housing 11. The door open sensor 16 is used to detect whether the front door 12 is in an open state relative to the housing 11. The door open sensor 16 is electrically connected to a main control unit 70, which will be described later. When the front door 12 is in a closed state relative to the housing 11, the door open sensor 16 sends a signal corresponding to the closed state to the main control unit 70. When the front door 12 is in an open state relative to the housing 11, the door open sensor 16 sends a signal corresponding to the open state to the main control unit 70.

[0014] As shown in Figure 1, a game panel 20 is provided near the upper center of the front door 12. The game panel 20 has three vertically elongated display windows 21L, 21M, and 21R arranged horizontally. The display windows 21L, 21M, and 21R are made of transparent or translucent material, and the inside of the slot machine 10 can be seen through each of the display windows 21L, 21M, and 21R.

[0015] As shown in Figures 2 and 3, the housing 11 is divided into upper and lower sections by a partition plate 11a, and a reel unit 31 is attached to the upper part of the partition plate 11a. The reel unit 31 comprises a left reel 32L, a middle reel 32M, and a right reel 32R, each formed in a cylindrical shape. Each reel 32L, 32M, and 32R is rotatably supported such that its central axis is the axis of rotation of the reel 32L, 32M, and 32R. The axes of rotation of each reel 32L, 32M, and 32R are arranged on the same axis extending in a substantially horizontal direction, and each reel 32L, 32M, and 32R corresponds one-to-one with each display window section 21L, 21M, and 21R. Therefore, a portion of the surface of each reel 32L, 32M, and 32R is visible through the corresponding display window section 21L, 21M, and 21R. Furthermore, when reels 32L, 32M, and 32R rotate in the forward direction, the surfaces of reels 32L, 32M, and 32R are displayed through the respective display windows 21L, 21M, and 21R, appearing as if they are moving from top to bottom.

[0016] As shown in Figure 1, a start lever 41 is provided on the lower left side of the game panel 20, which is operated to start the rotation of each reel 32L, 32M, and 32R. When a predetermined number or more of game media (or game value), which are either tokens or virtual tokens, are bet, the start lever 41 is operated, and each reel 32L, 32M, and 32R starts rotating simultaneously.

[0017] To the right of the start lever 41 are stop buttons 42, 43, and 44, which are operated to individually stop each of the rotating reels 32L, 32M, and 32R. Each stop button 42, 43, and 44 is located directly below the display windows 21L, 21M, and 21R corresponding to the reels 32L, 32M, and 32R that are to be stopped. Each stop button 42, 43, and 44 becomes ready to be stopped after a predetermined amount of time has elapsed since the left reel 32L began to rotate.

[0018] In addition, one game (game round) is considered to begin when the rotation of each reel 32L, 32M, and 32R starts based on the operation of the start lever 41, and when the rotation of each reel 32L, 32M, and 32R stops based on the operation of each stop button 42, 43, and 44, and when various processes such as dispensing game media and managing the game state are completed.

[0019] A coin slot 45 for inserting coins is provided on the lower right side of the display windows 21L, 21M, and 21R. Coins inserted through the coin slot 45 are guided to the hopper device 53 if acceptance is permitted, as shown in Figure 2, by a selector 52 located on the back of the front door 12, or guided to the coin tray 59 through a coin discharge port 58 located on the lower front of the front door 12 if acceptance is prohibited (see Figure 1). The hopper device 53 has the function of dispensing coins stored in the storage tank to the coin tray 59 through the coin discharge port 58 when a winning combination corresponding to the provision of a game medium is achieved on the main line ML, which will be described later. Below the coin slot 45, as shown in Figure 1, a return button 46 is provided, which is pressed when coins inserted into the coin slot 45 become jammed in the selector 52.

[0020] Lower left of the display windows 21L, 21M, and 21R, there is a first credit insertion button 47 for inserting the maximum amount of credited virtual tokens that can be bet at once, and a second credit insertion button 48 for inserting two virtual tokens at once. In this slot machine 10, there are situations where the number of game tokens (medals or virtual tokens) that can be bet (i.e., set as a bet) at once is "3" and situations where it is "2".

[0021] If the number of bets that can be placed at once is "3", and the current bet count is "0", and there are 3 or more virtual medals stored, and the first credit insertion button 47 is operated, the number of virtual medals will decrease by 3, but the number of bets will become "3". If the number of bets that can be placed at once is "3", and the current bet count is "1", and there are 2 or more virtual medals stored, and the first credit insertion button 47 is operated, the number of virtual medals will decrease by 2, but the number of bets will become "3". If the number of bets that can be placed at once is "3", and the current bet count is "2", and there are 1 or more virtual medals stored, and the first credit insertion button 47 is operated, the number of virtual medals will decrease by 1, but the number of bets will become "3". If the number of bets that can be placed at once is "2", and the current bet count is "0", and there are 2 or more virtual medals stored, and the first credit insertion button 47 is operated, the number of virtual medals will decrease by 2, but the number of bets will become "2". If the number of bets that can be placed at once is "2", and the current bet is "1", and one or more virtual tokens are stored, then pressing the first credit insertion button 47 will decrease the number of virtual tokens by one, but the bet will become "2".

[0022] Furthermore, if the first credit insertion button 47 is pressed when the number of stored virtual medals is less than the difference between the current number of bets and the number of bets that can be placed, the number of bets will increase by the amount of those virtual medals, and the number of virtual medals will become 0.

[0023] If the number of bets that can be placed at once is "3", and the current bet count is "0", and two or more virtual medals are stored, and the second credit insertion button 48 is operated, the number of bets will decrease by two instead of the number of virtual medals decreasing. If the number of bets that can be placed at once is "3", and the current bet count is "1", and one or more virtual medals are stored, and the second credit insertion button 48 is operated, the number of bets will decrease by one instead of the number of virtual medals decreasing. If the number of bets that can be placed at once is "2", and the current bet count is "0", and two or more virtual medals are stored, and the second credit insertion button 48 is operated, the number of bets will decrease by two instead of the number of virtual medals decreasing. If the number of bets that can be placed at once is "2", and the current bet count is "1", and one or more virtual medals are stored, and the second credit insertion button 48 is operated, the number of bets will decrease by one instead of the number of virtual medals decreasing.

[0024] Furthermore, if the second credit insertion button 48 is pressed while the number of stored virtual medals is 1 and the current bet is "0", the bet will become "1" and the number of virtual medals will become 0.

[0025] The first credit insertion button 47 has a wider pressing surface than the second credit insertion button 48, which is pressed when the player operates the button. This improves the operability of the first credit insertion button 47.

[0026] A payout button 51 is provided to the left of the start lever 41. This slot machine 10 has a credit function that stores any surplus inserted medals or medals paid out when winning as virtual medals until a predetermined maximum value (equivalent to 50 medals) is reached. When the payout button 51 is operated while virtual medals are stored, the virtual medals are dispensed as real medals from the medal dispenser 58.

[0027] Inside the housing 11, to the left of the hopper device 53, a power supply unit 54 is provided, as shown in Figures 2 and 3. The power supply unit 54 is equipped with a power switch 55 that is operated when the power is turned on or off, a reset button 56 for resetting various states of the slot machine 10, and a setting key insertion hole 57 into which a setting key held by the manager of the gaming hall is inserted and operated to change the setting value of the slot machine 10 within the range of "1" to "6".

[0028] Next, we will explain the designs attached to each reel, 32L, 32M, and 32R.

[0029] Figure 4 shows the symbol arrangements for the left reel 32L, the middle reel 32M, and the right reel 32R. As shown in the figure, each reel 32L, 32M, and 32R has 21 symbols arranged in a single row. In addition, each reel 32L, 32M, and 32R is numbered from "0" to "20". These numbers are used by the main control device 70, which will be described later, to recognize the symbols that are visible from the display windows 21L, 21M, and 21R, and are not actually assigned to the reels 32L, 32M, and 32R. However, these numbers will be used in the following explanation.

[0030] There are seven types of symbols: the "bell" symbol (for example, the 20th position on the left reel 32L), the "replay" symbol (for example, the 19th position on the left reel 32L), the "watermelon" symbol (for example, the 18th position on the left reel 32L), the "red 7" symbol (for example, the 15th position on the left reel 32L), the "BAR" symbol (for example, the 10th position on the left reel 32L), the "cherry" symbol (for example, the 9th position on the left reel 32L), and the "white 7" symbol (for example, the 5th position on the left reel 32L). The number and order of each symbol differ for each reel (32L, 32M, 32R).

[0031] Figure 5 is a front view of the display window sections 21L, 21M, and 21R. Each display window section 21L, 21M, and 21R is formed such that three of the 21 symbols attached to the corresponding reels 32L, 32M, and 32R are fully visible. Therefore, when all reels 32L, 32M, and 32R are stopped, 3 x 3 = 9 symbols are visible through the display window sections 21L, 21M, and 21R.

[0032] In this slot machine 10, a single main line ML is set up, connecting the positions where the symbols on each reel 32L, 32M, and 32R are visible. The main line ML is the line connecting the middle symbols on the left reel 32L, the middle symbols on the middle reel 32M, and the middle symbols on the right reel 32R. When a predetermined amount of game currency has been bet and the rotation of each reel 32L, 32M, and 32R begins, if a winning combination is achieved on the main line ML, the player will receive one of the following benefits: additional game currency, the opportunity to play again, or a change in the game state.

[0033] In other words, in this slot machine 10, only one main line ML is set as the line where a win can occur. Furthermore, this main line ML is set as a line that extends in a straight line. Therefore, even if a combination of winning symbols is formed on a straight line such as sub-line SL1 connecting the upper symbol of the left reel 32L, the middle symbol of the middle reel 32M, and the lower symbol of the right reel 32R, sub-line SL2 connecting the upper symbol of the left reel 32L, the upper symbol of the middle reel 32M, and the upper symbol of the right reel 32R, sub-line SL3 connecting the lower symbol of the left reel 32L, the lower symbol of the middle reel 32M, and the lower symbol of the right reel 32R, and sub-line SL4 connecting the lower symbol of the left reel 32L, the middle symbol of the middle reel 32M, and the upper symbol of the right reel 32R, a win will not occur.

[0034] The following explains the relationship between the winning combinations of symbols and the prizes awarded to winners, referring to Figure 6. Figure 6 is an explanatory diagram illustrating the relationship between the winning combinations of symbols and the prizes awarded to winners.

[0035] The types of small wins for which game tokens are awarded include the 1st, 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, and 9th compensation wins, the 1st bell win, the 2nd bell win, the 1st watermelon win, the 2nd watermelon win, and the cherry win. Specifically, in the main line ML, if the stopping symbol on the left reel 32L is a "bell" symbol, the stopping symbol on the middle reel 32M is a "bell" symbol, and the stopping symbol on the right reel 32R is a "red 7" symbol, it is considered a 1st compensation win. In the main line ML, if the stopping symbol on the left reel 32L is a "bell" symbol, the stopping symbol on the middle reel 32M is a "red 7" symbol, and the stopping symbol on the right reel 32R is a "bell" symbol, it is considered a 2nd compensation win. In the main line ML, if the stopping symbol on the left reel 32L is a "red 7", the stopping symbol on the middle reel 32M is a "bell", and the stopping symbol on the right reel 32R is a "bell", then it is a third compensation win. In the main line ML, if the stopping symbol on the left reel 32L is a "bell", the stopping symbol on the middle reel 32M is a "bell", and the stopping symbol on the right reel 32R is a "BAR", then it is a fourth compensation win. In the main line ML, if the stopping symbol on the left reel 32L is a "bell", the stopping symbol on the middle reel 32M is a "BAR", and the stopping symbol on the right reel 32R is a "bell", then it is a fifth compensation win. In the main line ML, if the stopping symbol on the left reel 32L is a "BAR" symbol, the stopping symbol on the middle reel 32M is a "Bell" symbol, and the stopping symbol on the right reel 32R is a "Bell" symbol, it is a 6th compensation win. In the main line ML, if the stopping symbol on the left reel 32L is a "Bell" symbol, the stopping symbol on the middle reel 32M is a "Bell" symbol, and the stopping symbol on the right reel 32R is a "White 7" symbol, it is a 7th compensation win. In the main line ML, if the stopping symbol on the left reel 32L is a "Bell" symbol, the stopping symbol on the middle reel 32M is a "White 7" symbol, and the stopping symbol on the right reel 32R is a "Bell" symbol, it is an 8th compensation win. In the main line ML, if the stopping symbol on the left reel 32L is a "white 7", the stopping symbol on the middle reel 32M is a "bell", and the stopping symbol on the right reel 32R is a "bell", then it is a 9th compensation win. If any of the 1st to 9th compensation wins occur, the number of game tokens awarded will be "1".

[0036] If, on the main line ML, the stopping symbol on the left reel 32L is a "bell", the stopping symbol on the middle reel 32M is a "bell", and the stopping symbol on the right reel 32R is a "bell", then the first bell is awarded. If, on the main line ML, the stopping symbol on the left reel 32L is a "bell", the stopping symbol on the middle reel 32M is a "bell", and the stopping symbol on the right reel 32R is a "replay", then the second bell is awarded. If either the first or second bell is awarded, the number of game tokens awarded will be "15".

[0037] If the stopping symbol on the left reel 32L on the main line ML is a "watermelon" symbol, the stopping symbol on the middle reel 32M is a "watermelon" symbol, and the stopping symbol on the right reel 32R is a "watermelon" symbol, then the first watermelon is awarded. If the stopping symbol on the left reel 32L on the main line ML is a "watermelon" symbol, the stopping symbol on the middle reel 32M is a "watermelon" symbol, and the stopping symbol on the right reel 32R is a "BAR" symbol, then the second watermelon is awarded. If either the first or second watermelon is awarded, the number of game tokens awarded will be "5". If the stopping symbol on the left reel 32L on the main line ML is a "cherry" symbol, then regardless of the stopping symbols on the middle reel 32M and the right reel 32R, a cherry is awarded. If a cherry is awarded, the number of game tokens awarded will be "2".

[0038] There are three types of wins that grant the bonus of being able to play the next game without betting any more betting tokens: regular replay win, 1st chance replay win, and 2nd chance replay win. Specifically, on the main line ML, if the stopping symbol on the left reel 32L is a "replay" symbol, the stopping symbol on the middle reel 32M is a "replay" symbol, and the stopping symbol on the right reel 32R is a "replay" symbol, on the main line ML, if the stopping symbol on the left reel 32L is a "red 7" symbol, the stopping symbol on the middle reel 32M is a "red 7" symbol, and the stopping symbol on the right reel 32R is a "BAR" symbol, on the main line ML, if the stopping symbol on the left reel 32L is a "replay" symbol and the stopping symbol on the middle reel 32M If the stopping symbol is a "Red 7" and the stopping symbol on the right reel 32R is a "Replay" symbol, if the stopping symbol on the left reel 32L on the main line ML is a "Replay" symbol, the stopping symbol on the middle reel 32M is a "Red 7" symbol, and the stopping symbol on the right reel 32R is a "BAR" symbol, or if the stopping symbol on the left reel 32L on the main line ML is a "Watermelon" symbol, the stopping symbol on the middle reel 32M is a "Red 7" symbol, and the stopping symbol on the right reel 32R is a "Bell" symbol, a normal replay is awarded. If the stopping symbol on the left reel 32L on the main line ML is a "Replay" symbol, the stopping symbol on the middle reel 32M is a "Cherry" symbol, and the stopping symbol on the right reel 32R is a "Bell" symbol, a first chance replay is awarded. If, on the main line ML, the stopping symbol on the left reel 32L is a "watermelon" symbol, the stopping symbol on the middle reel 32M is a "bell" symbol, and the stopping symbol on the right reel 32R is a "replay" symbol, then a second chance replay is awarded.

[0039] If any of the above replays are achieved, a special bonus is granted that allows you to play the next game without having to bet on any game currency. Specifically, if you achieve any of the replays in a game where you bet on game currency "3", you will be able to start the next game with game currency "3" already bet, without having to bet on any game currency. Also, if you achieve any of the replays in a game where you bet on game currency "2", you will be able to start the next game with game currency "2" already bet, without having to bet on any game currency.

[0040] There are two types of state transition wins that only result in a change of game state: the 1st CB win and the 2nd CB win. Specifically, the 1st CB win occurs when the stopping symbol on the left reel 32L on the main line ML is a "red 7", the stopping symbol on the middle reel 32M is a "red 7", and the stopping symbol on the right reel 32R is a "white 7". The 2nd CB win occurs when the stopping symbol on the left reel 32L on the main line ML is a "white 7", the stopping symbol on the middle reel 32M is a "white 7", and the stopping symbol on the right reel 32R is a "red 7". When the 1st CB win occurs, the game state changes to the 1st CB state ST2, and when the 2nd CB win occurs, the game state changes to the 2nd CB state ST3 (see Figure 40).

[0041] In the first CB state ST2 and the second CB state ST3, when a combination of symbols corresponding to a small win stops on the main line ML, a win is declared and medals are paid out regardless of whether a winning combination has been achieved. For example, even if no winning data corresponding to the first bell win is set, if a combination of symbols corresponding to the first bell win stops on the main line ML, game tokens will be awarded to the player. On the other hand, a replay win is only achieved if the corresponding winning combination has been won in the lottery.

[0042] In the first CB state ST2 and the second CB state ST3, reel control is performed differently from the non-CB state. In the non-CB state, reel control is performed for each reel 32L, 32M, and 32R that allows the reels to slide up to 4 symbols after stop buttons 42-44 are pressed. In other words, in the non-CB state, reel control is performed for each reel 32L, 32M, and 32R that stops the reels within a specified time (190 milliseconds) after stop buttons 42-44 are pressed. On the other hand, in the first CB state ST2 and the second CB state ST3, the above reel control, i.e., the same reel control as in normal gameplay, is performed for the middle reel 32M and the right reel 32R, but the above reel control is not performed for the left reel 32L. For the left reel 32L, reel control is performed that allows it to slide up to 1 symbol after the left stop button 42 is pressed. In other words, in the first CB state ST2 and the second CB state ST3, reel control is performed on the left reel 32L to stop it within a specified time (75 msec) that is shorter than the specified time after the left stop button 42 is operated.

[0043] Furthermore, in the first CB state ST2 and the second CB state ST3, the reel control that limits the slippage to a maximum of one symbol width is not limited to the left reel 32L. The control may also be applied to the reel corresponding to the first stop button operated, or to only a predetermined reel. Moreover, the reel control may be applied to the reels corresponding to the stop buttons operated in a certain order, such as the reel corresponding to the second or last stop button operated, which slips to a maximum of one symbol width.

[0044] In the first CB state ST2 and the second CB state ST3, if a winning combination corresponding to a replay win is achieved, the replay win takes priority. If a replay win is not possible, a first bell win may occur. Also, a first bell win may occur even if a winning combination corresponding to a replay win is not achieved.

[0045] Both the first CB state ST2 and the second CB state ST3 are game states in which the number of game tokens owned by the player does not increase. More specifically, both the first CB state ST2 and the second CB state ST3 are game states in which the number of game tokens owned by the player at the end of the game state is less than the number owned by the player at the start of the game state. Details of these first CB state ST2 and second CB state ST3 will be explained later.

[0046] Next, we will describe the devices used to perform various notifications and various effects.

[0047] As shown in Figure 1, an upper lamp 61 and a speaker 62 are provided above the front door 12, along with an image display device 63. The upper lamp 61 is controlled to emit light in a manner corresponding to an abnormality that occurs in the slot machine 10, and also in a manner corresponding to the winning result. The upper lamp 61 is also controlled to emit light in a manner corresponding to the display effects on the image display device 63. The speakers 62 are provided as a pair, left and right, and are controlled to output sound or voice corresponding to an abnormality that occurs in the slot machine 10, and also to output sound or voice corresponding to the winning result. The speakers 62 are also controlled to output sound in a manner corresponding to the display effects on the image display device 63.

[0048] The image display device 63 has a display surface and is configured as a liquid crystal display device equipped with a liquid crystal display, but is not limited to a liquid crystal display device. It may be other display devices having a display surface, such as a plasma display device, an organic EL display device, or a CRT, or it may be a dot matrix display device. When an abnormality occurs in the slot machine 10, the display control is performed so that an image corresponding to the abnormality is displayed on the display surface. In addition, the image display device 63 is controlled so that images corresponding to the winning results of the internal lottery and the winning results in each game are displayed on the display surface. In other words, the image display device 63 performs display effects.

[0049] The game panel 20 on the front door 12 is provided with a bet display unit 64 located below the display windows 21L, 21M, and 21R, which displays the number of game media currently bet, a credit display unit 65 which displays the number of stored virtual medals, a multi-purpose display unit 66 which displays the number of game media awarded when a small win occurs, displays information corresponding to the information provided by the image display device 63 when the stopping order of reels 32L, 32M, and 32R is announced, and also displays information for the management results of the game history, and a section display unit 67 which displays information corresponding to the fact that the game section is the second section.

[0050] The bet display unit 64 has three light-emitting units arranged vertically, and each light-emitting unit uses a single-color LED such as red. If the number of game tokens currently bet is "1", the bottom light-emitting unit will be lit and the remaining light-emitting units will be off. If the number of game tokens currently bet is "2", the bottom and middle light-emitting units will be lit and the top light-emitting unit will be off. If the number of game tokens currently bet is "3", all three light-emitting units will be lit. After all reels 32L, 32M, and 32R have stopped rotating in a game, all light-emitting units of the bet display unit 64 will be turned off, regardless of whether a replay has been achieved in that game or not. In this case, if it is the final game of the pseudo-bonus state ST4 described later, all the light-emitting parts of the bet display unit 64 will be turned off when the process to terminate the pseudo-bonus state ST4 is executed. If it is a game other than the final game, all the light-emitting parts of the bet display unit 64 will be turned off when the processing for one game is completed. Furthermore, if a replay has not been won, the lights-off state of each light-emitting part will be maintained until a new bet is made on the game medium. If a replay has been won, the lights-off state will be maintained for a predetermined period (for example, 2 seconds), after which the same number of light-emitting parts as the game in which the replay was won will be lit. The credit display unit 65 is composed of a 7-segment display, and each segment uses a single-color LED such as green.

[0051] Figure 7(a) is a front view of the common display area 68, which is provided with a dual-purpose display unit 66 and a section display unit 67. As shown in Figure 7(a), the common display area 68 integrates a dual-purpose display unit 66, which has two 7-segment displays 66a and 66b arranged side by side in the horizontal direction, and a section display unit 67, which consists of one light-emitting unit.

[0052] When any of the following minor wins (1st to 9th compensation wins, 1st bell win, 2nd bell win, 1st watermelon win, 2nd watermelon win, or cherry win) corresponding to the granting of game media are achieved, the number of game media granted corresponding to that win is displayed on the combined display unit 66 at the end of the game in which the minor win occurred. Specifically, when any of the 1st to 9th compensation wins occur in a non-CB state, the left 7-segment display unit 66a is turned off and "1" is displayed on the right 7-segment display unit 66b, indicating that "1" game media has been granted. When either the 1st bell win or the 2nd bell win occurs in a non-CB state, "1" is displayed on the left 7-segment display unit 66a and "5" is displayed on the right 7-segment display unit 66b, indicating that "15" game media have been granted. Furthermore, if either the first watermelon or the second watermelon is won while the game is not in a CB state, the left 7-segment display 66a will be hidden and the number "5" will be displayed on the right 7-segment display 66b to indicate that a game token of "5" has been awarded. Also, if a cherry is won while the game is not in a CB state, the left 7-segment display 66a will be hidden and the number "2" will be displayed on the right 7-segment display 66b to indicate that a game token of "2" has been awarded.

[0053] In the first CB state ST2 and the second CB state ST3, the number of game tokens awarded upon winning a minor role is "1," as will be explained in detail later. Therefore, when a minor role is won in the first CB state ST2 or the second CB state ST3, the left 7-segment display 66a will be turned off and "1" will be displayed on the right 7-segment display 66b, indicating that "1" game token has been awarded.

[0054] On the other hand, even if a win occurs that does not award any game medium, such as a replay win or a CB win, the combined display unit 66 will not display anything corresponding to that win, and in this case, the 7-segment displays 66a and 66b will remain hidden. The display of the number of game mediums awarded on the combined display unit 66 ends when game mediums are bet to start the next game after the game in which the display was made, and at the moment of this bet, the 7-segment displays 66a and 66b will remain hidden.

[0055] When the stopping order of reels 32L, 32M, and 32R is announced on the image display device 63, information corresponding to the announced stopping order is displayed on the multi-purpose display unit 66. Figure 7(b) is an explanatory diagram for explaining the content of the information corresponding to the stopping order displayed on the multi-purpose display unit 66. As shown in Figure 7(b), in this slot machine 10, the stopping order of reels 32L, 32M, and 32R announced on the image display device 63 is a stopping order in which the first stop is the left reel 32L, the second stop is the middle reel 32M, and the third stop is the right reel 32R; a stopping order in which the first stop is the left reel 32L, the second stop is the right reel 32R, and the third stop is the middle reel 32M; a stopping order in which the first stop is the middle reel 32M, the second stop is the left reel 32L, and the third stop is the right reel 32R; and a stopping order in which the first stop is the middle reel 32M and the third stop is the There are several possible stopping sequences: one where the second stop is the right reel 32R and the third stop is the left reel 32L; one where the first stop is the right reel 32R, the second stop is the left reel 32L, and the third stop is the middle reel 32M; one where the first stop is the right reel 32R, the second stop is the middle reel 32M, and the third stop is the left reel 32L; one where the first stop is the left reel 32L and the remaining reels are arbitrary; one where the first stop is the middle reel 32M and the remaining reels are arbitrary; and one where the first stop is the right reel 32R and the remaining reels are arbitrary.

[0056] The notification of the stopping order on the image display device 63 may be performed in the non-CB state when, during the lottery process for winning a role, a role is won that includes the first bell winning data and one of the first to sixth compensation winning data, or when a role is won that includes the second bell winning data and one of the seventh to ninth compensation winning data. Specifically, when a role is won that includes the first bell winning data and one of the first to sixth compensation winning data, a first bell win is achieved if reels 32L, 32M, and 32R stop in the stopping order corresponding to the winning role among the above stopping orders, and one of the first to sixth compensation wins may be achieved if reels 32L, 32M, and 32R do not stop in the stopping order corresponding to the winning role. If a first bell win is achieved, the player is given a game medium of "15" as previously explained, and if one of the first to sixth compensation wins is achieved, the player is given a game medium of "1" as previously explained.

[0057] If a winning combination includes data for the 2nd bell win and also includes data for the 7th to 9th compensation wins, a 2nd bell win is achieved if reels 32L, 32M, and 32R stop in the order corresponding to the winning combination from the above stopping sequences. If reels 32L, 32M, and 32R do not stop in the order corresponding to the winning combination, one of the 7th to 9th compensation wins may be achieved. If a 2nd bell win is achieved, the player will be awarded a game token of "15" as previously explained. If one of the 7th to 9th compensation wins is achieved, the player will be awarded a game token of "1" as previously explained.

[0058] When any of the above stop sequences are announced by the image display device 63, the left 7-segment display 66a of the dual-purpose display unit 66 remains blank, while the right 7-segment display 66b displays the stop sequence corresponding to the announced sequence. The content of this display is as shown in Figure 7(b), and the content of the stop sequence display on the dual-purpose display unit 66 is set to correspond one-to-one with the content of the stop sequence announcement on the image display device 63. However, this is not the only option, and the dual-purpose display unit 66 may be configured to correspond to some or all of the content of the stop sequence announcement on the image display device 63 with multiple types of display content.

[0059] The content of the stop order displayed in the dual-purpose display unit 66 differs from the content of the display that is shown when the dual-purpose display unit 66 displays information corresponding to the distribution of game media. This makes it easier to distinguish whether the content displayed in the dual-purpose display unit 66 corresponds to the number of game media distributed or to the stop order of reels 32L, 32M, and 32R.

[0060] Figures 8(a) and 8(b) are explanatory diagrams illustrating the relationship between the notification content of the stop order in the image display device 63 and the display content of the stop order in the combined display unit 66.

[0061] When the stopping order of reels 32L, 32M, and 32R is announced on the image display device 63, as shown in Figure 8(a), the image display device 63 displays the same number of unit display images G1 to G3 as the number of stop operations required to end the game, and each unit display image G1 to G3 displays an image corresponding to the stopping order of reels 32L, 32M, and 32R. Specifically, the left unit display image G1 corresponding to the left reel 32L, the middle unit display image G2 corresponding to the middle reel 32M, and the right unit display image G3 corresponding to the right reel 32R are displayed. In Figure 8(a), the stopping order is shown when the first stop is the middle reel 32M, the second stop is the left reel 32L, and the third stop is the right reel 32R. Therefore, the left unit display image G1 shows the image "2" corresponding to the stopping order of the left reel 32L, the middle unit display image G2 shows the image "1" corresponding to the stopping order of the middle reel 32M, and the right unit display image G3 shows the image "3" corresponding to the stopping order of the right reel 32R.

[0062] In the image display device 63, as described above, an image is displayed that indicates the stopping order of the reels 32L, 32M, and 32R, whereas in the multi-purpose display unit 66, as shown in Figure 8(b), the letter "L" is displayed, corresponding to the stopping order of the reels 32L, 32M, and 32R. In other words, in the image display device 63, unit display images G1 to G3 corresponding to the number of reels 32L, 32M, and 32R are displayed, and each unit display image G1 to G3 displays an image corresponding to the stopping order of the corresponding reels 32L, 32M, and 32R, whereas in the multi-purpose display unit 66, a display unrelated to the number of reels 32L, 32M, and 32R is displayed. As a result, even if the multi-purpose display unit 66 displays information corresponding to the notification of the stopping order of the reels 32L, 32M, and 32R, it is possible to draw the player's attention to the display content in the image display device 63.

[0063] The display range of the dual-purpose display unit 66 is narrower than that of the image display device 63. This also makes it possible to reduce the amount of attention players pay to the dual-purpose display unit 66 compared to the image display device 63. Furthermore, the dual-purpose display unit 66 is located on the opposite side from the image display device 63, with the display windows 21L, 21M, and 21R that allow the reels 32L, 32M, and 32R to be visible in between. As a result, the dual-purpose display unit 66 is positioned at a distance from the image display device 63, which also makes it possible to reduce the amount of attention players pay to the dual-purpose display unit 66.

[0064] When the stopping order of reels 32L, 32M, and 32R is announced, the display on the combined display unit 66 corresponding to the stopping order of reels 32L, 32M, and 32R, and the display on the image display device 63 corresponding to the stopping order of reels 32L, 32M, and 32R, start after the prize draw process has been performed and before the stopping operations of reels 32L, 32M, and 32R are activated. In this case, the display on the combined display unit 66 corresponding to the stopping order of reels 32L, 32M, and 32R starts before the display on the image display device 63 corresponding to the stopping order of reels 32L, 32M, and 32R, but these displays may start simultaneously or almost simultaneously, and the order of display start may be reversed. Furthermore, the displays on the combined display unit 66 and the image display device 63 corresponding to the stopping order of reels 32L, 32M, and 32R end when a stop command is issued for all reels 32L, 32M, and 32R in the game to which the display was executed.

[0065] The dual-purpose display unit 66 is located in the center of the common display area 68, while the section display unit 67 is located in the corner of the common display area 68. The section display unit 67 is a display unit for informing the player that the game section is the second section SC2 of the two sections SC2, which consist of the first section SC1. The second section SC2 is a section in which a favorable game state (specifically, pseudo-bonus state ST4 and AT state ST5) can be started and can continue, by informing the player of the stopping order of reels 32L, 32M, and 32R, which allows for the establishment of advantageous wins for the player when different winning combinations are achieved depending on the stopping order of reels 32L, 32M, and 32R, and the expected value of game media acquired in one game (the value obtained by subtracting the number of game media bet in one game from the expected number of game media given in one game) can be 1 or more when an advantageous game state is won. On the other hand, Section 1 SC1 is a section in which the above-mentioned advantageous game state does not begin and in which the above-mentioned advantageous game state does not continue.

[0066] The section display unit 67 lights up when the player wins a role where the winning combination depends on the stopping order of reels 32L, 32M, and 32R, or a role where the winning combination depends on the stopping order of reels 32L, 32M, and 32R, and the stopping order of reels 32L, 32M, and 32R is announced, resulting in a favorable game state where the expected value of winnings on the game medium is 1 or more. In this case, the pseudo-bonus state ST4 and AT state ST5 fall under the above favorable game state, while the second section SC2, which is neither the pseudo-bonus state ST4 nor the AT state ST5, does not fall under the above favorable game state. Therefore, when transitioning from the first section SC1 to the second section SC2, the section display unit 67 may or may not switch from the off state to the on state. If the section display unit 67 remains off when transitioning to the second section SC2, the section display unit 67 will turn on when the pseudo-bonus state ST4 or AT state ST5 starts in the second section SC2. Once the section display unit 67 is on, it will remain on until the second section SC2 ends, and will turn off when the second section SC2 ends and transitioning to the first section SC1.

[0067] As described above, the section display unit 67 is configured to remain lit once it is turned on in the second section SC2 until the second section SC2 ends. The shared display unit 66, which is consolidated in the common display area 68, is turned on when a game medium is provided and turned off at the start of the next game. It is also turned on when the stopping order of reels 32L, 32M, and 32R is displayed on the image display device 63 and turned off at the end of that game. Therefore, in a configuration where the section display unit 67 is placed within the common display area 68 so as not to be too conspicuous to the player, it is possible to actively create a situation where only the section display unit 67 is lit in the common display area 68 when it is the second section SC2, making it easier for the manager of the gaming hall to check the section display unit 67.

[0068] In addition, instead of maintaining the illuminated state of the section display unit 67 in the second section SC2, the section display unit 67 may be configured to blink at a predetermined interval. Furthermore, other displays such as liquid crystal displays may be used as the combined display unit 66 and the section display unit 67.

[0069] The slot machine 10 is equipped with various control devices. Specifically, as shown in Figure 3, a main control device 70 is provided above the reel unit 31. The main control device 70 is attached to the back plate 11b that forms the rear of the housing 11. The main control device 70 is composed of a main control board 71 housed in a board box 81. An MPU 72 is mounted on one of the board surfaces of the main control board 71, which is the element mounting surface. The board box 81 is made transparent so that the MPU 72 housed inside the board box 81 can be seen from the outside. The board box 81 is made transparent and colorless, but it may be made transparent with a color if it is possible to see the MPU 72 housed inside the board box 81 from the outside. The main control device 70 is mounted on the back plate 11b of the housing 11 such that the opposing wall portion 82 facing the element mounting surface of the main control board 71 faces forward towards the slot machine 10. Therefore, by opening the front door 12 toward the front of the slot machine 10 relative to the housing 11 and exposing the internal space of the housing 11, it becomes possible to visually inspect the opposing wall portion 82 of the circuit board box 81, and to visually inspect the MPU 72 through the opposing wall portion 82.

[0070] The circuit board box 81 is formed by combining multiple case bodies front to back, and these case bodies are provided with connecting parts 83 to prevent separation of the case bodies and to leave a trace when they are separated. Multiple connecting parts 83 are arranged in parallel on one side of the roughly rectangular circuit board box 81. This allows for the separation of the case bodies to be prevented by using some of the connecting parts 83, and even if some of the connecting parts 83 are destroyed to separate the case bodies, it is possible to prevent separation again by connecting other connecting parts 83 afterward. Furthermore, because the connecting parts 83 are destroyed and a trace is left when the case bodies are separated, it is possible to determine whether the separation of the case bodies has been done improperly by visually checking the connecting parts 83. In addition, a sealing seal 84 is attached to the side of the circuit board box 81 other than the side on which the connecting parts 83 are arranged, straddling the boundary between the case bodies. When the sealing seal 84 is peeled off, the adhesive layer remains on the case bodies. This makes it possible to leave a trace if the sealing sticker 84 is removed when separating the case.

[0071] As shown in Figure 2, the slot machine 10 is equipped with a performance control device 90 in addition to the main control device 70. The performance control device 90 is positioned behind the image display device 63 at the front door 12. Based on commands received from the main control device 70, the performance control device 90 controls the upper lamp 61, speaker 62, and image display device 63. The performance control device 90, like the main control device 70, has a control board housed in a circuit board box.

[0072] Next, the electrical configuration of this slot machine 10 will be explained based on the block diagram in Figure 9.

[0073] As previously described, the main control board 71 of the main control device 70 is equipped with an MPU 72. The MPU 72 includes a ROM 73 that stores various control programs and fixed value data executed by the MPU 72, a RAM 74 which is a memory for temporarily storing various data when executing the control programs stored in the ROM 73, a first random number circuit 75 that sequentially updates a first random number within a predetermined numerical range based on a clock signal output from the clock circuit, a second random number circuit 76 that sequentially updates a second random number within a predetermined numerical range based on a clock signal output from the clock circuit, and a clock circuit that outputs a square wave of a predetermined frequency. In addition, the MPU 72 also incorporates interrupt circuits, data input / output circuits, etc. It should be noted that the ROM 73 and RAM 74 being integrated into a single chip for the MPU 72 is not a mandatory configuration; they may each be configured as separate chips.

[0074] The MPU72 is equipped with input and output ports. Various sensors are connected to the input side of the MPU72, including a door open sensor 16, a start detection sensor 41a that detects the operation of the reel unit 31 and the start lever 41, stop detection sensors 42a, 43a, and 44a that individually detect the operation of each stop button 42, 43, and 44, a coin insertion detection sensor 45a that detects coins inserted from the coin slot 45, credit insertion detection sensors 47a and 48a that individually detect the operation of each credit insertion button 47 and 48, a settlement detection sensor 51a that detects the operation of the settlement button 51, a payout detection sensor for the hopper device 53, and a reset detection sensor and a setting key detection sensor that detect the operation of the reset button 56 and setting key insertion hole 57 provided on the power supply unit 54. Signals from each of these sensors are input to the MPU72.

[0075] The output side of the MPU 72 is connected to the reel unit 31, the selector drive unit 52a provided on the selector 52, the payout motor of the hopper device 53, the bet display unit 64, the credit display unit 65 (not shown in Figure 9), the multi-purpose display unit 66, the section display unit 67, the external output terminal board 78, and the performance control device 90, etc. In each game, the rotation drive control of each reel 32L, 32M, and 32R of the reel unit 31 is performed by the MPU 72. The selector 52 has the function of detecting the inserted medals into the medal slot 45 with the inserted medal detection sensor 45a if acceptance is permitted, and then guiding them to the hopper device 53, or discharging them into the medal tray 59 without detection by the inserted medal detection sensor 45a if acceptance is prohibited. The selector drive unit 52a has the function of switching the state of the selector 52 between an acceptance permitted state and an acceptance prohibited state, and specifically operates the passage switching piece provided on the selector 52 between an acceptance permitted position and an acceptance prohibited position. The MPU72 switches the state of the selector 52 between an acceptance-allowed state and an acceptance-prohibited state by switching the output state and stop state of the drive signal to the selector drive unit 52a.

[0076] The MPU 72 controls the drive of the hopper device 53 when a minor win is achieved and medals are dispensed. The MPU 72 also controls the display of the bet display unit 64 so that the number of bets is announced when a bet of game media occurs. The MPU 72 also controls the display of the credit display unit 65 so that the number of virtual game media stored is displayed when virtual game media are stored. The MPU 72 also controls the display of the combined display unit 66 so that the number of game media to be awarded is displayed when game media are awarded. The MPU 72 also controls the display of the section display unit 67 so that when a notification start trigger occurs in the second section SC2, it is announced that it is the second section SC2. The MPU 72 also controls the display of the combined display unit 66 so that a display corresponding to the game management result is shown. Furthermore, the external output terminal board 78 is installed on the internal space side of the housing 11, and the MPU 72 outputs signals to the external output terminal board 78, thereby outputting signals (specifically, a first external signal and a second external signal) to the management computer of the gaming hall through the external output terminal board 78.

[0077] The MPU 72 sends commands to the performance control device 90 at each timing in each game, and when it sends a command to the performance control device 90 to notify the stopping order of reels 32L, 32M, and 32R on the image display device 63, it executes display control of the combined display unit 66 so that the display corresponding to the content to be notified is shown. In this case, the direct display control of the image display device 63 is performed by the performance control device 90, while the direct display control of the combined display unit 66 is performed by the MPU 72. In other words, the image display device 63, which is subject to relatively complex display control, is directly controlled by the performance control device 90, while the combined display unit 66, which is subject to relatively simple display control, is directly controlled by the MPU 72. This makes it possible to reduce the processing load on the MPU 72 while performing both displays that prioritize increased attention to the performance and displays that prioritize reliability.

[0078] The input side of the MPU 72 is connected to a power outage monitoring circuit 54b provided in the power supply unit 54 (see Figure 11). The power supply unit 54 is equipped with a power supply unit 54a that supplies drive power to each electronic device of the slot machine 10, including the main control unit 70, and a power outage monitoring circuit 54b. The power outage monitoring circuit 54b monitors the voltage applied to the power supply unit 54a from an external power source, and sets the output level of the power outage signal to the MPU 72 to HI level if the voltage exceeds a reference voltage (e.g., 5V), and sets the output level of the power outage signal to the MPU 72 to LOW level if the voltage falls below the reference voltage. The MPU 72 performs power outage processing upon receiving a LOW level power outage signal, and after power is restored, it is possible to return to the processing state before the power outage. The power supply unit 54 is also equipped with a power outage power supply unit to supply backup power to the RAM 74 as power during power outage when the supply of operating power from an external power source is interrupted. As a result, even when the power supply from the external power source is cut off, data will be retained in RAM74 as long as backup power can be supplied by the power supply unit during the power outage (for example, for one or two days).

[0079] The performance control device 90 includes a performance control board 91 for controlling the execution of various notifications and various performances. The performance control board 91 is equipped with an MPU 92. The MPU 92 has a built-in ROM 93 that stores various control programs and fixed value data executed by the MPU 92, and a RAM 94 which is a memory for temporarily storing various data when executing the control programs stored in the ROM 93. It also has a built-in clock circuit that outputs a square wave of a predetermined frequency, an interrupt circuit, a data input / output circuit, and a random number generation circuit.

[0080] It is not mandatory for the ROM 93 and RAM 94 to be integrated into a single chip for the MPU 92; they may be configured as separate chips. Furthermore, while the RAM 94 does not receive backup power from the power supply unit of the power supply device 54 when the power supply from the external power source is interrupted, it may be configured to receive backup power.

[0081] The MPU92 is equipped with both an input port and an output port. As previously explained, the MPU72 of the main control unit 70 is connected to the input side of the MPU92, and receives various commands from the MPU72. The upper lamp 61, speaker 62, and image display device 63 are connected to the output side of the MPU92. Based on the commands received from the MPU72 of the main control unit 70, the MPU92 controls the illumination of the upper lamp 61, the sound output of the speaker 62, and the display of the image display device 63, thereby enabling various notifications and effects to be displayed.

[0082] The performance control board 91, although not shown in the diagram, is equipped with a video display processor (VDP), character ROM, and video RAM in addition to the MPU 92. The VDP is a type of drawing circuit that directly operates the image processing device, which acts as a liquid crystal display driver for the image display device 63. The VDP intervenes in the reading and writing of data to the video RAM and reads image data to be stored in the video RAM from the character ROM at predetermined timings to display on the image display device 63. The character ROM serves as an image data library for storing character data such as patterns displayed on the image display device 63. This character ROM holds bitmap image data of various display patterns, a color palette table referenced when determining the expression color of each dot in the bitmap image, and so on. The video RAM is a memory for storing display data to be displayed on the image display device 63. When the MPU 92 determines the content of the performance based on a command received from the MPU 72 of the main control device 70, it outputs a drawing list to the VDP that instructs the content of the image corresponding to each update timing according to the determined performance content. The VDP reads image data from the character ROM according to the drawing list and uses the read image data to create display data in the video RAM. The VDP then outputs an image signal corresponding to the created display data to the image display device 63, causing the image display device 63 to display the image corresponding to the display data.

[0083] For the purposes of the following explanation, the MPU 72, ROM 73, and RAM 74 of the main control device 70 will be referred to as the main MPU 72, main ROM 73, and main RAM 74, respectively, and the MPU 92, ROM 93, and RAM 94 of the performance control device 90 will be referred to as the performance-side MPU 92, performance-side ROM 93, and performance-side RAM 94, respectively.

[0084] <Regarding the various processes executed by the main MPU72> Next, we will explain the processes performed by the main MPU72. First, we will explain the main processes performed by the main MPU72 when the supply of operating power to the main MPU72 begins, referring to the flowchart in Figure 10.

[0085] First, the power outage signal is read (step S101). The power outage signal will now be explained. Figure 11 is an explanatory diagram illustrating the signal path of the power outage signal. As shown in Figure 11, the power supply unit 54 includes a power supply unit 54a that uses power supplied from an external power source to supply operating power to various electronic devices, including the main control unit 70, and a power outage monitoring circuit 54b that monitors the voltage applied to the power supply unit 54a from the external power source and sets the output level of the power outage signal to LOW when the voltage falls below a reference voltage. The power supply unit 54a and the main control unit 70 are electrically connected by a power line ELN, and operating power is supplied from the power supply unit 54a to the main control unit 70 through the power line ELN.

[0086] The power outage monitoring circuit 54b and the main MPU 72 are electrically connected by a signal line LN, and a power outage signal is transmitted from the power outage monitoring circuit 54b to the main MPU 72 through the signal line LN. The main MPU 72 is provided with an input port 72a, and information corresponding to the state of the power outage signal is stored in a predetermined bit (specifically, the most significant bit) of this input port 72a. In this case, if power is being supplied normally from the external power supply to the power supply unit 54a, a HI-level power outage signal is transmitted from the power outage monitoring circuit 54b to the main MPU 72. Specifically, a 5V signal is transmitted as the HI-level power outage signal, but the voltage of this power outage signal is arbitrary. When a HI-level power outage signal is transmitted, the predetermined bit of the input port 72a stores the information "1", which is one of the binary values, as information corresponding to the power outage signal. If power is not being supplied normally from the external power supply to the power supply unit 54a, a LOW-level power outage signal is transmitted from the power outage monitoring circuit 54b to the main MPU 72. Specifically, a LOW-level power outage signal is a signal of less than 5V. When a LOW level power outage signal is transmitted, the predetermined bit of the input port 72a stores the other value of the binary information, "0", as information corresponding to the power outage signal. Note that the HI / LOW relationship of the power outage signal may be reversed, and the power outage signal may be transmitted when power is being supplied normally from the external power source to the power supply unit 54a, and not transmitted when power is not being supplied normally from the external power source to the power supply unit 54a.

[0087] The main MPU 72 is basically configured to periodically determine whether or not a power outage has occurred by monitoring the predetermined bit of input port 72a in the power outage processing (step S503) of the timer interrupt processing (Figure 19) described later. However, the execution of the timer interrupt processing (Figure 19) is prohibited when the main processing starts, and the execution of the timer interrupt processing (Figure 19) is first permitted when the main processing finishes. Therefore, when the supply of operating power starts, the presence or absence of a power outage is determined in step S101 by monitoring the predetermined bit of input port 72a without waiting for the execution of the timer interrupt processing (Figure 19). Subsequently, it is determined whether or not the power outage signal received from the power outage monitoring circuit 54b is at a HI level by determining whether or not "1" is stored in the predetermined bit of input port 72a (step S102).

[0088] If the power outage signal is at a LOW level (step S102: NO), the process returns to step S101, and the information stored in the predetermined bits of input port 72a is read again (step S101). The process determines whether the power outage signal received from the power outage monitoring circuit 54b is at a HI level by determining whether the information is "1" or not (step S102). If the power outage signal is at a HI level (step S102: YES), the process proceeds to step S103 and beyond.

[0089] The process of waiting for the power outage signal to reach a HI level after the main process has started will be explained with reference to the time chart in Figure 12. Figure 12(a) shows the period during which operating power is supplied to the main MPU 72, Figure 12(b) shows the state of the power outage signal transmitted from the power outage monitoring circuit 54b, Figure 12(c) shows the period during which the main process is executed on the main MPU 72, Figure 12(d) shows the period during which the main process is waiting for the progress of the main process, and Figure 12(e) shows the period during which the process for when a power outage occurs is executed triggered by the timer interrupt process (Figure 19) identifying that the power outage signal is at a LOW level.

[0090] At timing t1, as shown in Figure 12(a), the power supply unit 54a begins supplying operating power to the main MPU 72, and as shown in Figure 12(c), the main processing (Figure 10) begins in the main MPU 72. In this case, immediately after the power supply to the power supply unit 54a begins, the power supply may not be stable, which may cause the voltage level of the power outage signal to be unstable. In the example shown in the time chart of Figure 12, as shown in Figure 12(b), the voltage of the power outage signal becomes unstable at less than 5V from timing t1 to timing t2. In contrast, as already explained, the main processing (Figure 10) executes steps S101 and S102, so as shown in Figure 12(d), it waits until the power outage signal reaches a HI level from timing t1 to timing t2 before proceeding to steps S103 and beyond.

[0091] Subsequently, at timing t2, the power outage signal stabilizes at a HI level, as shown in Figure 12(b). Therefore, as shown in Figure 12(d), the state in which processing is on hold (i.e., the state in which a negative judgment is made in step S102) is released, and the process proceeds to steps S103 and beyond. This makes it possible to complete the main process (Figure 10) while the power outage signal is stable at a HI level, and to start the process to proceed with the game.

[0092] Subsequently, at timing t3, the main process (Figure 10) ends as shown in Figure 12(c). In this case, the execution of the timer interrupt process (Figure 19) changes from a prohibited state to a permitted state. With the execution of the timer interrupt process (Figure 19) permitted, the timer interrupt process (Figure 19) is executed periodically, and the timer interrupt process (Figure 19) determines whether or not the predetermined bit of input port 72a has a value of "1" in it, thereby determining whether or not the power outage signal is at a HI level.

[0093] Subsequently, at timing t4, the supply of operating power from the external power source to the power supply unit 54a is stopped as shown in Figure 12(a), causing the power outage signal to change from a HI level to a LOW level as shown in Figure 12(b). When the power outage signal has changed to a LOW level, the timer interrupt process (Figure 19) detects this, and the processing for when a power outage occurs is executed from timing t4 to timing t5 as shown in Figure 12(e).

[0094] Figure 13 is a flowchart showing the power outage processing performed in step S503 of the timer interrupt processing (Figure 19).

[0095] In the power outage processing, it is first determined whether the power outage signal is at a HI level by checking whether the predetermined bit of input port 72a has a value of "1" (step S201). If the power outage signal is at a HI level (step S201: YES), the power outage processing is terminated without executing the power outage processing shown in steps S202 to S205.

[0096] If the value of the predetermined bit in input port 72a is "0", that is, if the power outage signal is at a LOW level (step S201: NO), the power outage flag in the main RAM 74 is set to "1" (step S202), a checksum is calculated using the information stored in the checksum calculation target area among the many memory areas in the main RAM 74 (step S203), and the calculated checksum is stored in the memory area of ​​the main RAM 74 that was not subject to checksum calculation (step S204). Then, after clearing all output ports of the main MPU 72 to "0" (step S205), an infinite loop is established. This infinite loop continues until the supply of operating power for power outages to the main MPU 72 is completely stopped. As a result, if the processing for power outages is executed normally when the supply of operating power to the main MPU 72 is stopped, the power outage flag in the main RAM 74 is set to "1", and the checksum is stored in the main RAM 74.

[0097] As described above, once power is supplied to the main MPU 72, the execution of the processes from step S103 onwards in the main process (Figure 10) is delayed until the power outage signal stabilizes at a HI level. This makes it possible to start the process for advancing the game only when a HI level power outage signal is stably output.

[0098] When the main process (Figure 10) is started, the timer interrupt process (Figure 19) is disabled. As a result, even if the power outage signal is not stable at a HI level, the power outage processing is not executed, and consequently, the processing for when a power outage occurs is not executed. In this case, the main process (Figure 10) repeatedly monitors the predetermined bit on input port 72a until the power outage signal reaches a HI level. This makes it possible to monitor whether the power outage signal is at a HI level even when the timer interrupt process (Figure 19) is disabled.

[0099] Returning to the explanation of the main process (Figure 10), if a positive result is obtained in step S102, the internal function setting process is executed (step S103). In the internal function setting process, various initial settings are performed for the register group and I / O devices, etc., within the main MPU 72.

[0100] Subsequently, the information anomaly flag 74g (see Figure 9) provided in the main RAM 74 is set to "1" (step S104). The information anomaly flag 74g is used by the main MPU 72 to determine whether or not an information anomaly has occurred in the main RAM 74 when the power supply for operation begins.

[0101] Subsequently, in order to determine whether or not an information anomaly has occurred, it is first determined whether or not the power outage flag in the main RAM 74 is set to "1" (step S105). Then, a checksum is calculated using the information stored in the checksum calculation target area among the many memory areas provided in the main RAM 74 (step S106), and it is determined whether or not the calculated checksum matches the checksum calculated in step S203 of the power outage processing (Figure 13) when the supply of operating power was stopped last time and stored in the main RAM 74 (steps S107 and S108). Furthermore, it is determined whether or not the setting value data stored in the setting value memory area provided in the main RAM 74 is 6 or greater (step S109). The setting value data of "0" corresponds to the setting value of "1", the setting value data of "1" corresponds to the setting value of "2", the setting value data of "2" corresponds to the setting value of "3", the setting value data of "3" corresponds to the setting value of "4", the setting value data of "4" corresponds to the setting value of "5", and the setting value data of "5" corresponds to the setting value of "6". Setting values ​​between "0" and "5" are considered normal, while values ​​of 6 or higher indicate an abnormality.

[0102] If the power outage flag is set to "1" (step S105: YES), the checksum matches (step S108: YES), and the setting value data is less than 6 (step S109: NO), it means that no information anomaly has occurred in the main RAM 74. In this case, the information anomaly flag 74g of the main RAM 74 is cleared to "0" (step S110). On the other hand, if the power outage flag is not set to "1" (step S105: NO), the checksum does not match (step S108: NO), or the setting value data is 6 or greater (step S109: YES), the information anomaly flag 74g is kept set to "1".

[0103] If a negative determination is made in step S105, if a negative determination is made in step S108, if an affirmative determination is made in step S109, or if the process in step S110 is executed, it is determined whether or not a setting change operation has been performed when the supply of operating power is started (step S111). Specifically, it is determined whether or not the setting key inserted into the setting key insertion hole 57 is turned ON. If no setting change operation has been performed (step S111: NO), it is determined whether or not the information abnormality flag 74g of the main RAM 74 is set to "1" (step S112).

[0104] If the information anomaly flag 74g is not set to "1" (step S112: NO), it means that the power outage processing during the previous power outage was executed successfully and no information anomalies occurred in the main RAM 74. In this case, the value of the stack pointer stored in the main RAM 74 is written to the stack pointer of the main MPU 72, and the data saved in the main RAM 74 is restored to the registers of the main MPU 72, thereby restoring the state of the registers of the main MPU 72 to the state before the power was cut off (step S113). The power outage flag in the main RAM 74 is also cleared to "0" (step S114). A power restoration command is also sent to the performance MPU 92 to recognize the execution of the power restoration process (step S115).

[0105] Subsequently, the execution of the timer interrupt process (Figure 19) is permitted (step S116). At the time when the supply of operating power to the main MPU 72 begins, the execution of the timer interrupt process (Figure 19) is not permitted, but the execution of the process in step S116 permits the execution of the timer interrupt process (Figure 19). As a result, the timer interrupt process (Figure 19) is activated periodically. After that, the address returns to the address before the power was cut off (step S117).

[0106] If the information anomaly flag 74g is set to "1" (step S112: YES), the operation disable process is executed. In the operation disable process, all output ports of the main MPU 72 are cleared to "0", thereby turning off all actuators connected to those output ports (step S118), and an error notification process is executed to notify the hall manager, etc., of the occurrence of an error (step S119). This then results in an infinite loop. Even if the supply of operating power to the main MPU 72 is stopped, this operation disable process will be executed again when the supply of operating power is restarted until the setting change process described later (Figure 15) is executed. If the setting change process described later (Figure 15) is executed, the execution of the operation disable process is avoided.

[0107] Figure 14 is a time chart showing how an information anomaly in the main RAM 74 is identified using the information anomaly flag 74g. Figure 14(a) shows the period during which the main process (Figure 10) is executed, Figure 14(b) shows the state of the information anomaly flag 74g, Figure 14(c) shows the period during which the anomaly detection process (steps S105 to S109) is executed, and Figure 14(d) shows the period during which the operation prohibition process (steps S118 and S119) is executed.

[0108] First, let's explain the case where no information anomalies occur in the main RAM74.

[0109] When power is supplied to the main MPU 72, the main processing (Figure 10) starts on the main MPU 72 at timing t1, as shown in Figure 14(a). Then, at timing t2, the information anomaly flag 74g is set to "1", as shown in Figure 14(b), and then the anomaly detection process (steps S105 to S109) is executed from timing t3 to t4, as shown in Figure 14(c). In this case, the anomaly detection process (steps S105 to S109) does not identify that an information anomaly has occurred in the main RAM 74. Therefore, at timing t4, the information anomaly flag 74g is cleared to "0", as shown in Figure 14(b), and the operation prohibition process (steps S118 and S119) is not executed, as shown in Figure 14(d). Subsequently, at timing t5, the main processing (Figure 10) ends as shown in Figure 14(a), and processing to advance the game (timer interrupt processing (Figure 19), normal processing (Figure 25)) begins.

[0110] Next, we will explain the case where an information anomaly occurs in the main RAM 74.

[0111] When power is supplied to the main MPU 72, the main processing (Figure 10) starts on the main MPU 72 at timing t6, as shown in Figure 14(a). Then, at timing t7, the information anomaly flag 74g is set to "1", as shown in Figure 14(b), and then the anomaly detection process (steps S105 to S109) is executed from timing t8 to t9, as shown in Figure 14(c). In this case, the anomaly detection process (steps S105 to S109) identifies that an information anomaly has occurred in the main RAM 74. Therefore, as the state in which the information anomaly flag 74g is set to "1", as shown in Figure 14(b), the operation prohibition process (steps S118 and S119) starts at timing t9, as shown in Figure 14(d).

[0112] As described above, after the information anomaly flag 74g, which is a flag used by the main MPU 72 to determine whether or not an information anomaly has occurred in the main RAM 74. is set to "1", an anomaly detection process is executed to perform various checks to determine whether or not an information anomaly has occurred in the main RAM 74. If the anomaly detection process determines that an information anomaly has occurred in the main RAM 74, the state in which the information anomaly flag 74g is set to "1" is maintained. If the anomaly detection process determines that no information anomaly has occurred in the main RAM 74, the information anomaly flag 74g is cleared to "0". If the state in which the information anomaly flag 74g is set to "1" is maintained, the operation prohibition process is executed. If the value of the information anomaly flag 74g is "0", the operation prohibition process is not executed and the process to allow the game to proceed is started. By initially setting the information anomaly flag 74g to "1" and then clearing the information anomaly flag 74g to "0" if it is determined that no information anomaly has occurred in the main RAM 74, it becomes possible to execute the operation prohibition process even if an information anomaly has actually occurred but various checks to determine whether or not an information anomaly has occurred in the main RAM 74 are not performed due to the occurrence of electrical noise.

[0113] Returning to the explanation of the main process (Figure 10), if the setting key inserted into the setting key insertion hole 57 is turned ON when the supply of operating power is started, that is, if a setting change operation has been performed (step S111: YES), then after the setting change process is executed (step S120), the normal process is executed (step S121).

[0114] Figure 15 is a flowchart showing the setting change process in step S120.

[0115] First, the starting address setting process is executed (step S301). In the starting address setting process, when a clear process is executed to initialize the memory area of ​​the main RAM 74 by clearing it to "0" at the start of the setting change process, the address of the memory area of ​​the main RAM 74 that is the target of the clear process is set. Figure 16 is an explanatory diagram for explaining the contents of the memory area of ​​the main RAM 74. As shown in Figure 16, each memory area of ​​the main RAM 74 has an address set. The addresses are set as sequential information. Specifically, the address "0000" is set as the initial address, the address "0001" is set as the next sequential address, the address "0002" is set as the next sequential address, and so on, with the addresses continuing to be sequential thereafter.

[0116] The second CB winning data area is set as the memory area corresponding to the starting address "0000" and is an area for storing the second CB winning data. If the second CB winning data is selected in the role lottery process described later (Figure 34), the second CB winning data is set in the second CB winning data area, and if a second CB win is achieved, the second CB winning data is cleared from the second CB winning data area.

[0117] For the starting address "0000", the next address in sequence, "0001", is designated as the first CB winning data area, which is an area for storing the first CB winning data. If the first CB winning data is selected in the role lottery process described later (Figure 34), the first CB winning data is set in the first CB winning data area, and if the first CB win is achieved, the first CB winning data is cleared from the first CB winning data area.

[0118] For "0001", the next memory area corresponding to "0002" is the setting value storage area, which is an area for storing the setting value to be used. The setting value selected in the setting change process (Figure 15) is stored in the setting value storage area.

[0119] The memory area corresponding to "0003" is set to the continuous game count counter 74c, the memory area corresponding to "0004" is set to the total acquisition counter 74d, the memory area corresponding to "0005" is set to the credit counter 74b, and the memory area corresponding to "0006" is set to the door state area 74e. In addition, various memory areas are set in the memory areas corresponding to "0007" to "k-3". These various memory areas include the second section flag, which will be described later. In addition, the memory area corresponding to "k-2" is set to the bet count history counter 74f, the memory area corresponding to "k-1" is set to the grant count history counter, the memory area corresponding to "k" is set to the pseudo-bonus state flag, the memory area corresponding to "k+1" is set to the pseudo-bonus continuation counter, the memory area corresponding to "k+2" is set to the bet count setting counter 74a, and the memory area corresponding to "k+3" is set to the medium grant counter. In addition, the memory area for addresses from "k+4" onwards is set to, for example, the information anomaly flag 74g. The information anomaly flag 74g has already been explained, and the other counters 74a to 74e and the various areas 74f will be explained later.

[0120] In the starting address setting process in step S301, "0001" is set as the starting address in the clear target address set in the register of the main MPU72. As will be explained in detail later, the "0" clear and initialization of the memory area of ​​the main RAM74 is performed on the memory area of ​​the address set in the clear target address, and then the clear target address is incremented by 1 so that it becomes the next sequential address, and the "0" clear and initialization is performed on the memory area corresponding to the clear target address after the increment. In this case, if "0001" is set as the starting address in the clear target address, the memory areas corresponding to addresses from "0001" onwards will be subject to "0" clear and initialization, while the memory area corresponding to the address "0000" will not be subject to "0" clear and initialization.

[0121] Subsequently, it is determined whether an information anomaly has occurred in the main RAM 74 by checking whether the information anomaly flag 74g of the main RAM 74 is set to "1" (step S302). It is also determined whether the reset button 56 was pressed when the power supply for operation was started (step S303). If both steps S302 and S303 result in a negative determination, the start address correction process is executed (step S304). In the start address correction process, the address to be cleared in the main MPU 72 is overwritten with "0000" as the corrected start address. If "0000" is set as the start address in the address to be cleared, all memory areas of the main RAM 74 are subject to "0" clear and initialization.

[0122] In other words, if a setting change process is started while an information anomaly has occurred in the main RAM 74 and the information anomaly flag 74g is set to "1", then the memory areas subject to the "0" clear and initialization performed at the start of the setting change process will be all memory areas of the main RAM 74. Furthermore, even if a setting change process is started while no information anomaly has occurred in the main RAM 74 and the value of the information anomaly flag 74g is "0", if the reset button 56 is pressed in addition to the setting key being pressed when the power supply is started, then the memory areas subject to the "0" clear and initialization performed at the start of the setting change process will be all memory areas of the main RAM 74.

[0123] If a positive determination is made in step S302, if a positive determination is made in step S303, or if the process in step S304 is executed, the memory area of ​​the main RAM 74 corresponding to the address set as the address to be cleared is reset to "0" and initialized (step S305). After that, the update process for the address to be cleared is executed (step S306). In this update process, the value of the address to be cleared is increased by 1, so that the address set as the address to be cleared is changed to the next address in the order of addresses in the main RAM 74. Then, it is determined whether the address after the update exceeds the end address, which is the last address in the order of addresses in the main RAM 74 (step S307). If a negative determination is made in step S307, the memory area of ​​the address after the update is reset to "0" and initialized (step S305), and the processes in steps S306 and S307 are executed again. If a positive determination is made in step S307, it means that the clearing process of the main RAM 74 has been completed. In this case, the process proceeds to step S308.

[0124] Here, we will explain how the clearing process of the main RAM 74 is performed during the setting change process, referring to the time chart in Figure 17. Figure 17(a) shows the period during which operating power is supplied to the main MPU 72, Figure 17(b) shows the period during which the main process (Figure 10) is performed on the main MPU 72, Figure 17(c) shows the period during which the setting key inserted into the setting key insertion hole 57 is turned ON as part of the setting change operation, Figure 17(d) shows the period during which the reset button 56 is pressed, Figure 17(e) shows the state of the information abnormality flag 74g, Figure 17(f) shows the period during which the setting change process (Figure 15) is performed on the main MPU 72, Figure 17(g) shows the period during which a clearing process is performed on a part of the memory area of ​​the main RAM 74, and Figure 17(h) shows the period during which a clearing process is performed on the entire memory area of ​​the main RAM 74.

[0125] First, we will explain the case where the power supply for operation begins without the reset button 56 being pressed, and the setting change process is executed in a situation where no information abnormality has occurred in the main RAM 74.

[0126] At timing t1, power supply to the main MPU 72 begins as shown in Figure 17(a), and at the same timing t1, the main processing (Figure 10) begins on the main MPU 72 as shown in Figure 17(b). Also, as shown in Figure 17(c), a setting change operation is performed when the power supply to the operating system begins. Subsequently, at timing t2, the information anomaly flag 74g is set to "1" as shown in Figure 17(e), but at timing t3, the information anomaly flag 74g is cleared to "0" because the anomaly detection process (steps S105 to S109) in the main processing (Figure 10) determines that no information anomaly has occurred in the main RAM 74.

[0127] Subsequently, at timing t4, the main MPU 72 starts a configuration change process (Figure 15) as shown in Figure 17(f). When this configuration change process (Figure 15) starts, the main RAM 74 is cleared. However, since no information anomalies occurred in the main RAM 74 when the power supply was started, the value of the information anomaly flag 74g is "0" as shown in Figure 17(e). Furthermore, the reset button 56 was not pressed when the power supply was started, as shown in Figure 17(d). Therefore, when the main RAM 74 is cleared, a partial clear process is performed, setting the starting address to "0001" as shown in Figure 17(g). In this case, as already explained, the second CB winning data area, which is a memory area in the main RAM 74 with an initial address set, is excluded from the "0" clear and initialization process. The "0" clear and initialization are then sequentially performed on the memory areas other than this area, and the process ends at timing t5 as shown in Figure 17(g). This makes it possible to maintain the information in the second CB winning data area in the state it was in before the previous power supply interruption, even when the setting change process (Figure 15) is executed.

[0128] Next, we will explain the case where the power supply is started while the reset button 56 is pressed, and the setting change process is executed when no information abnormality occurs in the main RAM 74.

[0129] At timing t6, power supply to the main MPU 72 is started as shown in Figure 17(a), and at the same timing t6, the main processing (Figure 10) is started in the main MPU 72 as shown in Figure 17(b). Also, as shown in Figure 17(c), a setting change operation is performed when the power supply to the main MPU is started, and as shown in Figure 17(d), the reset button 56 is pressed. Subsequently, at timing t7, the information anomaly flag 74g is set to "1" as shown in Figure 17(e), but at timing t8, the information anomaly flag 74g is cleared to "0" because the anomaly detection process (steps S105 to S109) in the main processing (Figure 10) determines that no information anomaly has occurred in the main RAM 74.

[0130] Subsequently, at timing t9, the main MPU 72 starts a configuration change process (Figure 15) as shown in Figure 17(f). When this configuration change process (Figure 15) starts, the main RAM 74 is cleared. However, since no information anomalies occurred in the main RAM 74 when the power supply was started, the value of the information anomaly flag 74g is "0" as shown in Figure 17(e). On the other hand, the reset button 56 was pressed as shown in Figure 17(d) when the power supply was started, and this pressing operation continues at timing t9. Therefore, when the main RAM 74 is cleared, a complete clear process is executed, setting the starting address to "0000", as shown in Figure 17(h). In this case, as already explained, the "0" clear and initialization are sequentially performed on all memory areas of the main RAM 74, including the second CB winning data area, which is a memory area where the initial address is set in the main RAM 74, and this process ends at timing t10 ​​as shown in Figure 17(h). This makes it possible to initialize the entire storage area of ​​the main RAM 74 when the configuration change process (Figure 15) is executed.

[0131] Next, we will explain the case where the power supply is started when the reset button 56 has not been pressed, and the setting change process is executed when an information anomaly occurs in the main RAM 74.

[0132] At timing t11, power supply to the main MPU 72 is started as shown in Figure 17(a), and at the same timing t11, the main processing (Figure 10) is started on the main MPU 72 as shown in Figure 17(b). Also, as shown in Figure 17(c), a setting change operation is performed when the power supply to the operating system is started. Subsequently, at timing t12, the information anomaly flag 74g is set to "1" as shown in Figure 17(e), and further, in the anomaly detection process (steps S105 to S109) in the main processing (Figure 10), it is identified that an information anomaly has occurred in the main RAM 74, and the state in which the information anomaly flag 74g is set to "1" is maintained.

[0133] Subsequently, at timing t13, the main MPU 72 starts the configuration change process (Figure 15) as shown in Figure 17(f). When this configuration change process (Figure 15) starts, the main RAM 74 is cleared. However, since an information anomaly occurred in the main RAM 74 when the power supply was started, the value of the information anomaly flag 74g is "1" as shown in Figure 17(e). Therefore, when clearing the main RAM 74 in this case, a complete clear process is performed, setting the starting address to "0000" as shown in Figure 17(h). In this case, as already explained, a "0" clear and initialization is sequentially performed on all memory areas of the main RAM 74, including the second CB winning data area, which is a memory area where the initial address is set in the main RAM 74, and this process ends at timing t14 as shown in Figure 17(h). This makes it possible to start the process to change the setting value after initializing all memory areas of the main RAM 74 when the configuration change process (Figure 15) is executed while an information anomaly has occurred in the main RAM 74.

[0134] Returning to the explanation of the setting change process (Figure 15), if a positive determination is made in step S307, a setting change start command is sent to the performance-side MPU 92 (step S308). When the performance-side MPU 92 receives the setting change start command, it controls the upper lamp 61, speaker 62, and image display device 63 to perform a notification indicating that the setting value is being changed. In this case, the image display device 63 may be configured to display an image that allows the administrator of the gaming hall to recognize the operation performed to change the setting value.

[0135] Subsequently, the configuration change execution process is executed (step S309). Figure 18 is a flowchart of the configuration change execution process.

[0136] First, the timer interrupt process (Figure 19) is authorized (step S401). At the time when power is supplied to the main MPU 72, the timer interrupt process (Figure 19) is not authorized. However, when the setting change process (Figure 15) is executed in the main process (Figure 10), the execution of step S401 of the setting change execution process (Figure 18) is performed, thereby authorizing the timer interrupt process (Figure 19). As a result, the timer interrupt process (Figure 19) is activated periodically.

[0137] Figure 19 is a flowchart showing the timer interrupt process. Note that the timer interrupt process is triggered, for example, every 1.49 milliseconds.

[0138] First, further interrupts to the timer interrupt processing (Figure 19) are disabled (step S501). Then, register saving processing is performed (step S502). In the register saving processing, the values ​​of all registers in the main MPU 72 used in the normal processing (Figure 25), which will be described later, are saved to the main RAM 74. After that, power outage processing is performed (step S503). The processing content of the power outage processing is as already explained. After that, stepping motor control processing is performed to drive the stepping motors provided on each reel 32L, 32M, and 32R in order to rotate each reel 32L, 32M, and 32R (step S504). Sensor monitoring processing is also performed (step S505).

[0139] Figure 20(a) is a flowchart of the sensor monitoring process. First, a shift process for the detection state memory area is performed (step S601). Figure 20(b) is an explanatory diagram for explaining the contents of the detection state memory area provided in the main RAM 74. As shown in Figure 20(b), the main RAM 74 is provided with a reset current memory area 74h and a reset previous memory area 74i as detection state memory areas. The reset current memory area 74h stores information corresponding to the state of the reset button 56 as determined in the most recent sensor monitoring process (Figure 20(a)). Specifically, in the most recent sensor monitoring process (Figure 20(a)), if a HI level signal indicating that the reset button 56 is being pressed is received as a detection signal from the reset button 56, the information "1" is stored in the reset current memory area 74h. If a LOW level signal indicating that the reset button 56 is not being pressed is received, the reset current memory area 74h is cleared to "0". Furthermore, the reset last memory area 74i stores information corresponding to the state of the reset button 56 as determined in the sensor monitoring process of the previous processing cycle (Figure 20(a)). Specifically, if the sensor monitoring process of the previous processing cycle (Figure 20(a)) received a HI level signal from the reset button 56 indicating that the reset button 56 was being pressed, the reset last memory area 74i stores the information "1". If the sensor monitoring process of the previous processing cycle (Figure 20(a)) received a LOW level signal indicating that the reset button 56 was not being pressed, the information in the reset last memory area 74i is "0".

[0140] In step S601, the shifting process of the detection state memory area overwrites the information stored in the reset current memory area 74h with the information stored in the reset previous memory area 74i. Then, the signal received from the reset button 56 is identified, and if the identified signal is at a HI level (step S602: YES), "1" is set in the reset current memory area 74h (step S603), and if the identified signal is at a LOW level (step S602: NO), the reset current memory area 74h is cleared to "0" (step S604).

[0141] If the process in step S603 or step S604 is executed, other processes are executed (step S605). In the other processes, processes are executed to identify the contents of detection signals from various sensors other than the sensor that detects the pressing operation of the reset button 56.

[0142] Returning to the explanation of the timer interrupt processing (Figure 19), after executing the sensor monitoring processing, a timer subtraction process is executed to subtract the values ​​of each counter and timer (step S506). In addition, a command output process is executed to send various commands to the performance-side MPU 92 (step S507). Furthermore, a port output process is executed to output data corresponding to the I / O device from the input / output port (step S508). In this port output process, the combined display unit 66 is controlled to display a number corresponding to the value of the media allocation counter of the main-side RAM 74, which will be described later, when the notification of the stopping order of reels 32L, 32M, and 32R has not been executed. Note that if the value of the media allocation counter is "0" when the notification of the stopping order of reels 32L, 32M, and 32R has not been executed, the combined display unit 66 is turned off. In addition, control processing for the bet display unit 64 is executed so that the display corresponding to the number of bets is executed on the bet display unit 64 (step S509). Furthermore, management processing is performed to manage the game history and display the corresponding content on the combined display unit 66 (step S510). Specifically, the ratio of the total number of games in the second section SC2, described later, to the total number of games is calculated, and the resulting ratio is displayed on the combined display unit 66. After that, the values ​​of each register that were saved in the main RAM 74 in step S502 are restored to the corresponding registers in the main MPU 72 (step S511), and the execution of the next timer interrupt processing (Figure 19) is permitted (step S512).

[0143] Returning to the explanation of the setting change execution process (Figure 18), after allowing the execution of the timer interrupt process (Figure 19) in step S401, it is determined whether or not the timer interrupt process (Figure 19) has been executed (step S402), and the system waits in step S402 until the timer interrupt process (Figure 19) is executed. The processing configuration for determining whether or not the timer interrupt process (Figure 19) has been executed is arbitrary, but in this slot machine 10, an executed flag is provided in the register of the main MPU 72, and when the supply of operating power to the main MPU 72 is started, the executed flag is cleared to "0", and thereafter, each time the timer interrupt process (Figure 19) is executed, a process is executed to set the executed flag to "1". In this case, step S402 determines whether the executed flag in the register of the main MPU72 is set to "1". If the executed flag is not set to "1", a negative determination is made in step S402. If the executed flag is set to "1", a positive determination is made in step S402. If a positive determination is made in step S402, the executed flag in the register of the main MPU72 is cleared to "0" (step S403).

[0144] Next, it is determined whether the value in the setting value storage area provided in the main RAM 74 is 6 or greater (step S404). The setting value storage area is an area used by the main MPU 72 to identify the setting value currently being selected. If the value in the setting value storage area is "0", the setting value being selected is "1". If the value in the setting value storage area is "1", the setting value being selected is "2". If the value in the setting value storage area is "2", the setting value being selected is "3". If the value in the setting value storage area is "3", the setting value being selected is "4". If the value in the setting value storage area is "4", the setting value being selected is "5". If the value in the setting value storage area is "5", the setting value being selected is "6". If the value in the setting value storage area is 6 or greater, it means that the value in the setting value storage area has exceeded the maximum value, so the setting value storage area is cleared to "0" (step S405). As a result, the setting value being selected becomes "1".

[0145] If a negative determination is made in step S404, or if the processing in step S405 is executed, it is determined whether or not the timer interrupt processing (Figure 19) has been executed (step S406), and the system waits in step S406 until the timer interrupt processing (Figure 19) is executed. Specifically, similar to step S402, it is determined whether or not the executed flag in the register of the main MPU72 is set to "1". The executed flag is cleared to "0" when a positive determination is made in step S402, and as already explained, a process to set the executed flag to "1" is executed each time the timer interrupt processing (Figure 19) is executed. Therefore, in step S406, it is determined whether or not the timer interrupt processing (Figure 19) has been executed at least once since the positive determination was made in step S402. If the executed flag is not set to "1", a negative determination is made in step S406, and if the executed flag is set to "1", a positive determination is made in step S406. If a positive result is obtained in step S406, the executed flag in the register of the main MPU72 is cleared to "0" (step S407).

[0146] Next, it is determined whether the start lever 41 is turned ON (step S408). If the start lever 41 is turned ON while the setting change execution process is running, the selected setting value is confirmed as the one to be used. If the start lever 41 is not turned ON (step S408: NO), it is determined whether the reset button 56 has been pressed (step S409). Specifically, it is determined whether the information stored in the reset previous memory area 74i of the main RAM 74 is "0", which corresponds to the reset button 56 not being pressed, and whether the information stored in the reset current memory area 74h of the main RAM 74 is "1", which corresponds to the reset button 56 being pressed. If a negative determination is made in step S409, the process returns to step S406. If a positive determination is made in step S409, the value in the setting value memory area of ​​the main RAM 74 is incremented by 1 (step S410). After that, the process returns to step S404, and if the value in the setting value storage area after adding 1 is 6 or more (step S404: YES), the setting value storage area is cleared to "0" (step S405), and then the process from step S406 onwards is executed. If the start lever 41 is in the ON position (step S408: YES), the process waits until the setting key inserted in the setting key insertion hole 57 is turned OFF (step S411: NO), and if the setting key is turned OFF (step S411: YES), the setting change execution process is terminated.

[0147] In other words, when the setting change execution process is running, each time the reset button 56 is pressed, the selected setting value is changed to a setting value with one level higher in terms of advantage. Also, if the reset button 56 is pressed when the setting value is already set to "6", which is the highest level of advantage, the setting value memory area is cleared to "0", and the setting value becomes "1", which is the lowest level of advantage. Furthermore, when the start lever 41 is turned ON, the selected setting value is confirmed as the one to be used, and then the setting key inserted into the setting key insertion hole 57 is turned OFF, ending the setting change execution process.

[0148] In the setting change execution process, as described above, the processes in steps S402 and S406 are executed, resulting in two interrupt waiting periods occurring between the start of the setting change execution process (Figure 18) and the start of the initial determination process to determine whether or not the reset button 56 has been pressed. These interrupt waiting periods allow the process to wait for a new timer interrupt process (Figure 19) to be executed. Because these interrupt waiting periods are set, even if the supply of operating power to the main MPU 72 starts when the reset button 56 is pressed, and the setting change execution process (Figure 18) starts while the reset button 56 is still pressed, the maintained press of the reset button 56 will not cause a change in the selected setting value. This will be explained with reference to the time chart in Figure 21.

[0149] Figure 21 is a time chart showing how the selected setting value is not changed by the continued pressing of the reset button 56 when operating power is supplied while the reset button 56 is pressed. Figure 21(a) shows the period during which operating power is supplied to the main MPU 72, Figure 21(b) shows the period during which the main processing (Figure 10) is executed in the main MPU 72, Figure 21(c) shows the period during which the ON operation is performed by the setting key inserted into the setting key insertion hole 57, Figure 21(d) shows the period during which the reset button 56 is pressed, Figure 21(e) shows the period during which a clear operation is performed on the entire memory area of ​​the main RAM 74, and Figure 21(f) shows the setting change execution operation. Figure 18 shows the period during which the logic is being executed, Figure 21(g) shows the period during which the timer interrupt processing (Figure 19) is being executed, Figure 21(h) shows the interrupt waiting period due to steps S402 and S406 of the setting change execution processing (Figure 18), Figure 21(i) shows the state of the reset current memory area 74h of the main RAM 74, Figure 21(j) shows the state of the reset previous memory area 74i of the main RAM 74, and Figure 21(k) shows the timing of the identification of the trigger for changing the setting value to be selected.

[0150] At timing t1, power supply to the main MPU 72 is started as shown in Figure 21(a), and at the same timing t1, the main processing (Figure 10) is started on the main MPU 72 as shown in Figure 21(b). In addition, as shown in Figure 21(c), an ON operation is performed using the setting key when power supply is started, and as shown in Figure 21(d), the reset button 56 is pressed.

[0151] As described above, the ON operation is performed by the setting key, and thereafter the setting change process (Figure 15) is started. When the setting change process (Figure 15) is started, the clearing process of the main RAM 74 is executed. However, as described above, the reset button 56 was pressed when the power supply for this operation was started, and this pressing operation continues at timing t2. Therefore, at timing t2, as shown in Figure 21(e), the clearing process for the entire memory area of ​​the main RAM 74 is started. In this case, the reset current memory area 74h and the reset previous memory area 74i are also cleared to "0" by this clearing process.

[0152] Subsequently, at timing t3, the clear process is completed as shown in Figure 21(e). At timing t3, the setting change execution process (Figure 18) is started as shown in Figure 21(f). In this case, in the setting change execution process (Figure 18), the execution of the timer interrupt process (Figure 19) is permitted in step S401, and the process waits until the timer interrupt process (Figure 19) is executed in step S402. In other words, an interrupt waiting period occurs as shown in Figure 21(h).

[0153] At timing t4 during the interrupt waiting period, the timer interrupt process (Figure 19) is executed, interrupting the setting change execution process (Figure 18), as shown in Figure 21(g). At timing t5, while the timer interrupt process (Figure 19) is being executed, the sensor monitoring process (Figure 20(a)) in step S505 of the timer interrupt process (Figure 19) is executed to determine whether or not the reset button 56 is being pressed. At timing t5, the reset button 56 is still being pressed, as shown in Figure 21(d). Therefore, at timing t5, "1" is set in the reset current memory area 74h, as shown in Figure 21(i). The information in the previous reset memory area 74i remains at "0". The timer interrupt process (Figure 19) ends at timing t6, as shown in Figure 21(g). As a result, the processing executed by the main MPU 72 returns to the setting change execution process (Figure 18).

[0154] In the configuration change execution process (Figure 18), since the timer interrupt process (Figure 19) has already been executed, a positive determination is made in step S402 and the processes from step S403 onwards are executed. Then, in step S406, the system waits until the timer interrupt process (Figure 19) is executed again. In other words, as shown in Figure 21(h), an interrupt waiting period occurs at timing t7.

[0155] At timing t8 during the interrupt waiting period, the timer interrupt process (Figure 19) is executed, interrupting the setting change execution process (Figure 18) as shown in Figure 21(g). At timing t9, while the timer interrupt process (Figure 19) is being executed, the sensor monitoring process (Figure 20(a)) of step S505 in the timer interrupt process (Figure 19) is executed. In this case, first the information stored in the reset current memory area 74h is shifted to the reset previous memory area 74i, but since "1" is already set in the reset current memory area 74h, "1" is set in the reset previous memory area 74i at timing t9, as shown in Figure 21(j). Also, the sensor monitoring process (Figure 20(a)) determines whether or not the reset button 56 is being pressed. At timing t9, the press operation of the reset button 56 is continuing, as shown in Figure 21(d). Therefore, at the timing of t9, "1" is set in the reset current memory area 74h as shown in Figure 21(i). The timer interrupt process (Figure 19) ends at the timing of t10 as shown in Figure 21(g). As a result, the process executed by the main MPU 72 returns to the setting change execution process (Figure 18).

[0156] In the configuration change execution process (Figure 18), the timer interrupt process (Figure 19) has already been executed, so a positive determination is made in step S406 and the processes from step S408 onwards are executed. Then, at timing t11, as shown in Figure 21(k), a process is executed to determine whether or not the press operation of the reset button 56 in step S409 has started. Specifically, it is determined whether the information stored in the reset previous memory area 74i of the main RAM 74 is "0", which corresponds to the reset button 56 not being pressed, and whether the information stored in the reset current memory area 74h of the main RAM 74 is "1", which corresponds to the reset button 56 being pressed. In this case, as shown in Figure 21(j), the information in the reset previous memory area 74i is "1", and as shown in Figure 21(i), the information in the reset current memory area 74h is "1". Therefore, in step S409, it is not determined that the press operation of the reset button 56 has started. This makes it possible to prevent the selected setting value from being changed by the continued pressing of the reset button 56 when the power supply is started while the reset button 56 is pressed.

[0157] Subsequently, at timing t12, step S406 of the setting change execution process (Figure 18) is executed. In step S406, the system waits until the timer interrupt process (Figure 19) is executed again. In other words, as shown in Figure 21(h), an interrupt waiting period occurs at timing t12. At timing t13 during this interrupt waiting period, the press operation of the reset button 56 is released as shown in Figure 21(d). Also, at timing t14, the timer interrupt process (Figure 19) is executed, interrupting the setting change execution process (Figure 18) as shown in Figure 21(g). At timing t15, while the timer interrupt process (Figure 19) is being executed, the sensor monitoring process (Figure 20(a)) of step S505 in the timer interrupt process (Figure 19) is executed. In this case, the information stored in the reset current memory area 74h is first shifted to the reset previous memory area 74i. However, since the reset current memory area 74h is already set to "1", at the timing of t15, "1" is set in the reset previous memory area 74i as shown in Figure 21(j). In addition, the sensor monitoring process (Figure 20(a)) determines whether or not the reset button 56 has been pressed. At the timing of t15, the reset button 56 has not been pressed as shown in Figure 21(d). Therefore, at the timing of t15, the reset current memory area 74h is cleared to "0" as shown in Figure 21(i). The timer interrupt process (Figure 19) ends at the timing of t16 as shown in Figure 21(g). As a result, the processing executed by the main MPU 72 returns to the setting change execution process (Figure 18).

[0158] In the configuration change execution process (Figure 18), the timer interrupt process (Figure 19) has already been executed, so a positive determination is made in step S406 and the processes from step S408 onwards are executed. Then, at the timing of t17, as shown in Figure 21(k), a process is executed to determine whether or not the press operation of the reset button 56 in step S409 has started. Specifically, it is determined whether the information stored in the reset previous memory area 74i of the main RAM 74 is "0", which corresponds to the reset button 56 not being pressed, and whether the information stored in the reset current memory area 74h of the main RAM 74 is "1", which corresponds to the reset button 56 being pressed. In this case, as shown in Figure 21(j), the information in the reset previous memory area 74i is "1", and as shown in Figure 21(i), the information in the reset current memory area 74h is "0". Therefore, in step S409, it is not determined that the press operation of the reset button 56 has started.

[0159] Subsequently, at timing t18, step S406 of the setting change execution process (Figure 18) is executed. In step S406, the system waits until the timer interrupt process (Figure 19) is executed again. In other words, as shown in Figure 21(h), an interrupt waiting period occurs at timing t18. At timing t19 during this interrupt waiting period, the timer interrupt process (Figure 19) is executed, interrupting the setting change execution process (Figure 18), as shown in Figure 21(g). At timing t20, while the timer interrupt process (Figure 19) is being executed, the sensor monitoring process (Figure 20(a)) of step S505 in the timer interrupt process (Figure 19) is executed. In this case, first the information stored in the reset current memory area 74h is shifted to the reset previous memory area 74i, but since the information in the reset current memory area 74h is "0", the reset previous memory area 74i is cleared to "0" at timing t20, as shown in Figure 21(j). Furthermore, the sensor monitoring process (Figure 20(a)) determines whether or not the reset button 56 is pressed. At the timing t20, the reset button 56 is not pressed, as shown in Figure 21(d). Therefore, at the timing t20, the reset status memory area 74h is cleared to "0", as shown in Figure 21(i). The timer interrupt process (Figure 19) terminates at the timing t21, as shown in Figure 21(g). As a result, the processing executed by the main MPU 72 returns to the setting change execution process (Figure 18).

[0160] Furthermore, if a positive result is obtained in step S406, the executed flag of the main MPU72 is cleared to "0" in step S407, and the timer interrupt process (Figure 19) will not be executed between the execution of step S407 and the execution of step S406 again. Therefore, if a positive result is obtained in step S406 and step S406 is executed again, an interrupt waiting period will definitely occur at that time, and this interrupt waiting period will be cleared when the timer interrupt process (Figure 19) is executed once.

[0161] As described above, in the setting change execution process (Figure 18), the processes in steps S402 and S406 are executed, resulting in two interrupt waiting periods, which are periods for waiting for the process to progress until a new timer interrupt process (Figure 19) is executed, between the start of the setting change execution process (Figure 18) and the start of the first determination process to determine whether or not the reset button 56 has been pressed. Because these interrupt waiting periods are set, even if the supply of operating power to the main MPU 72 starts when the reset button 56 is pressed, and the setting change execution process (Figure 18) starts while the reset button 56 is still pressed, the contents of the information in the reset previous memory area 74i and the reset current memory area 74h will indicate that the reset button 56 is still being pressed when the first determination process to determine whether or not the reset button 56 has been pressed starts after the setting change execution process (Figure 18) has started. Therefore, in step S409, it is not determined that the reset button 56 has been pressed. This makes it possible to prevent the selected setting value from being changed by the continued pressing of the reset button 56 when the power supply is started while the reset button 56 is pressed.

[0162] Returning to the explanation of the setting change process (Figure 15), after executing the setting change execution process in step S309, a setting change completion command is sent to the performance-side MPU 92 (step S310). When the performance-side MPU 92 receives the setting change completion command, it controls the upper lamp 61, speaker 62, and image display device 63 so that the notification indicating that the setting value is being changed is terminated. After that, reset state information is set in the door state area 74e of the main-side RAM 74 (step S311).

[0163] The door state area 74e is an area referenced by the main MPU 72 when determining whether or not a change in the open / closed state of the front door 12 relative to the housing 11 has occurred. Figure 22 is a flowchart showing the monitoring process of the door open sensor 16, which is performed in the other processing (step S605) of the sensor monitoring process (Figure 20(a)) in the main MPU 72.

[0164] If the door open sensor 16 receives a signal indicating that the front door 12 is in an open state (step S701: YES), it is determined whether the information stored in the door state area 74e is open information (step S702). Open information indicates that in the processing cycle immediately preceding this monitoring process, the door open sensor 16 received a signal indicating that the front door 12 is in an open state. If open information is stored in the door state area 74e (step S702: YES), this monitoring process is terminated. If the information in the door state area 74e is anything other than open information (step S702: NO), that is, if closed information is stored in the door state area 74e, if reset state information is stored in the door state area 74e, or if the information in the door state area 74e is "0", an open command is sent to the performance-side MPU 92 (step S703). When the performance-side MPU 92 receives the open command, it controls the upper lamp 61, speaker 62, and image display device 63 so that a notification indicating that the front door 12 is in an open state is executed.

[0165] Subsequently, the open information is stored in the door state area 74e (step S704). As a result, even if the door open sensor 16 continues to receive a signal indicating that the front door 12 is in an open state during the next processing cycle of this monitoring process, the open information is stored in the door state area 74e, and a positive determination is made in step S702, preventing the transmission of a new open command. Therefore, it is possible to prevent the open command from being repeatedly transmitted while the front door 12 is maintained in an open state.

[0166] If a signal corresponding to the front door 12 being in a closed state is received from the door open sensor 16 (step S701: NO), it is determined whether the information stored in the door state area 74e is closed information (step S705). Closed information is information indicating that a signal corresponding to the front door 12 being in a closed state was received from the door open sensor 16 in the processing round immediately preceding this monitoring process. If closed information is stored in the door state area 74e (step S705: YES), this monitoring process is terminated. If information other than closed information is stored in the door state area 74e (step S705: NO), that is, if open information is stored in the door state area 74e, if reset state information is stored in the door state area 74e, or if the information in the door state area 74e is "0", a close command is sent to the performance-side MPU 92 (step S706). When the performance-side MPU92 receives a closing command, it terminates the notification indicating that the front door 12 is in the open state, and then controls the upper lamp 61, speaker 62, and image display device 63 to execute a notification indicating that the front door 12 has changed from the open state to the closed state. This notification indicating that the door has been closed continues for 30 seconds unless the front door 12 becomes open again. If the front door 12 becomes open again, the notification indicating that the front door 12 is in the open state starts again.

[0167] Subsequently, the closed information is stored in the door state area 74e (step S707). As a result, even if the door open sensor 16 continues to receive a signal indicating that the front door 12 is in a closed state during the next processing cycle of this monitoring process, the closed information is stored in the door state area 74e, and a positive determination is made in step S705, preventing the transmission of a new close command. Therefore, it is possible to prevent the close command from being repeatedly transmitted while the front door 12 is maintained in a closed state.

[0168] Figure 23 is a flowchart showing the notification process executed on the production-side MPU92. The notification process is repeatedly executed on the production-side MPU92 at a relatively short interval (e.g., 2 milliseconds).

[0169] If a setting change start command is received (step S801: YES), the setting change notification start process is executed (step S802). In this start process, the upper lamp 61, speaker 62, and image display device 63 are controlled so that a setting change notification is started to indicate that the setting value is being changed. In this case, the image display device 63 may be configured to display an image that allows the administrator of the gaming hall to recognize the operation to change the setting value. After this start process is executed, until a setting change end command is received from the main MPU 72, the upper lamp 61, speaker 62, and image display device 63 are controlled in other processes in step S818 so that the content of the setting change notification continues or is updated.

[0170] If an open command is received (step S803: YES), and if a setting change notification is being executed (step S804: YES), the notification process is terminated without performing any processing in response to the reception of the open command. This makes it possible to prioritize the setting change notification over the door open notification, which indicates that the front door 12 is in an open state. If an open command is received (step S803: YES) and a setting change notification is not being executed (step S804: NO), the door open notification start process is executed (step S805). In this start process, the upper lamp 61, speaker 62, and image display device 63 are controlled so that the door open notification, which indicates that the front door 12 is in an open state, is started. After this start process is executed, until a close command is received from the main MPU 72, the upper lamp 61, speaker 62, and image display device 63 are controlled in other processes in step S818 so that the content of the door open notification continues or is updated.

[0171] If a setting change completion command is received (step S806: YES), the termination process for the setting change notification is executed (step S807). In this termination process, the upper lamp 61, speaker 62, and image display device 63 are controlled so that the setting change notification is terminated. In addition, the clear process for the performance-side RAM 94 is executed (step S808). In this clear process, each memory area of ​​the performance-side RAM 94 is reset to "0" and initialized. This makes it possible to initialize not only each memory area of ​​the main-side RAM 74 but also each memory area of ​​the performance-side RAM 94 when the setting value to be used is set in the main-side MPU 72. When the performance-side RAM 94 is initialized, the upper lamp 61, speaker 62, and image display device 63 will execute an initialization post-notification.

[0172] If a closing command is received (step S809: YES), and if a setting change notification is being executed (step S810: YES), the notification process is terminated without performing any processing in response to the reception of the closing command. This makes it possible to prioritize the setting change notification over the door closing notification, which indicates that the front door 12 has changed from an open state to a closed state. If a closing command is received (step S809: YES), and a setting change notification is not being executed (step S810: NO), the termination process for the door open notification is executed (step S811). In this termination process, the upper lamp 61, speaker 62, and image display device 63 are controlled so that the door open notification, which indicates that the front door 12 is in an open state, is terminated.

[0173] Subsequently, the door closing notification start process is executed (step S812). In this start process, the upper lamp 61, speaker 62, and image display device 63 are controlled so that a door closing notification is started to indicate that the front door 12 has changed from an open state to a closed state. After this start process is executed, the upper lamp 61, speaker 62, and image display device 63 are controlled in other processes in step S818 so that the content of the door closing notification continues or is updated until the door closing notification period (specifically 30 seconds) has elapsed. In addition, the setting process for the door closing notification counter provided in the performance-side RAM 94 is executed (step S813). In this setting process, information corresponding to the door closing notification period (specifically 30 seconds) is set in the door closing notification counter.

[0174] If the value of the door closing notification counter in the RAM 94 on the production side is 1 or greater (step S814: YES), the value of the door closing notification counter is deducted by 1 (step S815). Then, by determining whether the value of the door closing notification counter after the deduction is "0", it is determined whether the door closing notification period has elapsed since the door closing notification started (step S816). If the value of the door closing notification counter is "0" (step S816: YES), the door closing notification termination process is executed (step S817). In this termination process, the upper lamp 61, speaker 62 and image display device 63 are controlled so that the door closing notification, which indicates that the front door 12 has changed from an open state to a closed state, is terminated.

[0175] Next, we will explain how various notifications are executed when the supply of operating power is started and the setting change process (Figure 15) is executed, referring to the time chart in Figure 24. Figure 24(a) shows the period when operating power is supplied to the main MPU 72, Figure 24(b) shows the period when the main process (Figure 10) is executed in the main MPU 72, Figure 24(c) shows the period when the front door 12 is in the open state, Figure 24(d) shows the period when the memory area clearing process of the main RAM 74 is executed, Figure 24(e) shows the period when the setting change execution process (Figure 18) is executed, Figure 24(f) shows the period when the setting change notification is executed, Figure 24(g) shows the timing when reset state information is set in the door state area 74e of the main RAM 74, Figure 24(h) shows the period when the door open notification is executed, and Figure 24(i) shows the period when the door closed notification is executed.

[0176] As shown in Figure 24(c), at a timing of t1 when the front door 12 is in the open state, power supply to the main MPU 72 is started as shown in Figure 24(a), and the main processing (Figure 10) is started in the main MPU 72 as shown in Figure 24(b) at the same timing of t1. In addition, since the front door 12 is in the open state and the ON operation is performed by the setting key when the power supply is started, the setting change process (Figure 15) is started at timing t2. When the setting change process (Figure 15) is started, the clearing process of the main RAM 74 is executed, but the reset button 56 was not pressed when the power supply was started, and furthermore, no information abnormality occurred in the main RAM 74. Therefore, at timing t2, the clearing process of a part of the storage area of ​​the main RAM 74 is started as shown in Figure 24(d). In this case, the door state area 74e is also cleared to "0" by the clearing process, so neither open information nor closed information is stored in the door state area 74e. Furthermore, the state in which the timer interrupt processing (Figure 19) is disabled has continued since the start of power supply.

[0177] Subsequently, at timing t3, the clear process is completed as shown in Figure 24(d). At the same timing t3, the setting change execution process (Figure 18) is started as shown in Figure 24(e). Also, immediately before the setting change execution process (Figure 18) is started, the process in step S308 of the setting change process (Figure 15) is executed, sending a setting change start command from the main MPU 72 to the performance MPU 92. Therefore, as shown in Figure 24(f), the setting change notification is started at timing t3. Note that in the setting change execution process (Figure 18), the execution of the timer interrupt process (Figure 19) is permitted in step S401, and since no open information is stored in the door state area 74e, an open command is sent to the performance MPU 92 in the monitoring process of the door open sensor 16 in the timer interrupt process (Figure 19). However, since the setting change notification has already started, the door open notification is not started.

[0178] Subsequently, at timing t4, the configuration change execution process (Figure 18) is completed as shown in Figure 24(e). In this case, the process of step S310 in the configuration change process (Figure 15) is executed, and a configuration change completion command is sent from the main MPU 72 to the production MPU 92. Therefore, as shown in Figure 24(e), the notification of configuration change in progress is terminated at timing t4.

[0179] Subsequently, at timing t5, the process of step S311 in the setting change process (Figure 15) is executed, and reset state information, which is neither open nor closed, is stored in the door state area 74e. Then, the timer interrupt process (Figure 19) is executed, and at timing t6, the monitoring process of the door open sensor 16 (Figure 22) is executed in the timer interrupt process (Figure 19). In this case, as shown in Figure 24(c), the front door 12 is in the open state and reset state information is stored in the door state area 74e, so an open command is sent to the performance-side MPU 92. Therefore, at timing t6, the door open notification is started as shown in Figure 24(h). Note that at timing t6, open information is set in the door state area 74e, so as shown in Figure 24(g), the reset state information is no longer stored in the door state area 74e.

[0180] Subsequently, at timing t7, the front door 12 closes as shown in Figure 24(c). In this case, since open information is stored in the door state area 74e, a close command is sent to the performance-side MPU 92 when the monitoring process for the door open sensor 16 (Figure 22) is executed by the timer interrupt process (Figure 19). Therefore, at timing t7, the door open notification ends as shown in Figure 24(h), and the door closed notification begins as shown in Figure 24(i). Note that closed information is set in the door state area 74e at timing 7. Subsequently, at timing t8, the door closed notification period (specifically 30 seconds) has elapsed, and the door closed notification ends as shown in Figure 24(i).

[0181] As described above, in a configuration where a clearing process of the storage area of ​​the main RAM 74 is executed when a setting change process (Figure 15) is executed to set the setting value to be used, when the setting change execution process (Figure 18) is completed, reset state information that is neither open nor closed information is stored in the door state area 74e. As a result, if the front door 12 is in the open state when the setting change execution process (Figure 18) is completed, the setting change notification ends and the door open notification starts immediately afterward. Also, if the front door 12 is in the closed state when the setting change execution process (Figure 18) is completed, the setting change notification ends and the door closed notification starts immediately afterward. Therefore, when the setting change execution process (Figure 18) is completed, it is possible to ensure that either the setting change notification is followed by the door open notification or the door closed notification. Thus, it is possible to reliably notify whether the front door 12 is in the open state or the front door 12 is in the closed state.

[0182] Furthermore, if the front door 12 is in the closed state at the time the setting change execution process (Figure 18) is completed and the reset state information is set in the door state area 74e, the monitoring process of the door open sensor 16 (Figure 22) in the timer interrupt process (Figure 19) will determine that the front door 12 is in the closed state while the reset state information is stored in the door state area 74e, and a close command will be sent to the performance-side MPU 92. In this case, a door close notification will be executed after the setting change notification, rather than a door open notification.

[0183] Next, the normal processing performed on the main MPU72 will be explained based on the flowchart in Figure 25.

[0184] First, the start-waiting process is executed (step S901). Figure 26 is a flowchart of the start-waiting process. First, it is determined whether the bet-set flag for replays, located in the main RAM 74, is set to "1" (step S1001). The bet-set flag for replays is a flag used by the main MPU 72 to determine whether the same number of bets as the previous game have already been set, in the case that any replay win occurred in the previous game. If the determination in step S1001 is negative, then, on the condition that any replay win occurred in the previous game (step S1002: YES), the value of the bet-count history counter 74f, also located in the main RAM 74, is set to the bet-count setting counter 74a (see Figure 9), also located in the main RAM 74 (step S1003). The bet-count setting counter 74a is a counter used by the main MPU 72 to determine the number of bets for the game to be executed, and the bet-count history counter 74f is a counter used by the main MPU 72 to determine the number of bets for the previous game. After that, the flag for pre-set bets during replay is set to "1" (step S1004).

[0185] If a positive result is obtained in step S1001, if a negative result is obtained in step S1002, or if the process in step S1004 is executed, the bet response process is executed (step S1005). Figure 27 is a flowchart of the bet response process.

[0186] If the current game state is not the 2nd CB state ST3 (Step S1101: NO), the maximum bet amount, which is the maximum number of game tokens that can be bet in this game, is set to "3" (Step S1102). If the current game state is the 2nd CB state ST3 (Step S1101: YES), the maximum bet amount, which is the maximum number of game tokens that can be bet in this game, is set to "2" (Step S1103). In other words, in this slot machine 10, the maximum bet amount is set to "2" when the game state is the 2nd CB state ST3, and to "3" when the game state is not the 2nd CB state ST3.

[0187] If the process in step S1102 or step S1103 is executed, it is determined whether a valid bet operation has been performed, provided that the value of the bet count setting counter 74a in the main RAM 74 is not the maximum bet amount for the current bet (step S1104: NO), and that there is one or more virtual medals stored (step S1105). The main RAM 74 is provided with a credit counter 74b (see Figure 9) as an area for storing the number of virtual medals stored. In step S1105, it is determined whether there is one or more virtual medals stored by checking whether the value of the credit counter 74b is 1 or more. In addition, if the first credit insertion button 47 is operated, it is determined that a valid bet operation has been performed, and if the second credit insertion button 48 is operated, it is determined that a valid bet operation has been performed, provided that the value of the bet count setting counter 74a is 1 or less.

[0188] If a positive result is obtained in step S1105, the bet setting process is executed (step S1106). In the bet setting process, if the first credit insertion button 47 is operated, if the sum of the value of the bet number setting counter 74a and the value of the credit counter 74b is equal to or greater than the maximum bet, the value of the bet number setting counter 74a is set to the maximum bet, and the value of the virtual medals used in the setting is subtracted from the credit counter 74b. If the sum of the value of the bet number setting counter 74a and the value of the credit counter 74b is less than the maximum bet, the value of the credit counter 74b is added to the bet number setting counter 74a, and then the value of the credit counter 74b is cleared to "0". Furthermore, during the bet setting process, if the second credit insertion button 48 is operated, and the sum of the value of the bet setting counter 74a and the value of the credit counter 74b is 2 or more, the value of the bet setting counter 74a is set to "2", and the number of virtual medals used in the setting is subtracted from the credit counter 74b. If the sum of the value of the bet setting counter 74a and the value of the credit counter 74b is less than 2, the value of the credit counter 74b is added to the bet setting counter 74a, and then the value of the credit counter 74b is cleared to "0".

[0189] If a positive determination is made in step S1104, if a negative determination is made in step S1105, or if the process in step S1106 is executed, it is determined whether or not one medal has been detected by the inserted medal detection sensor 45a due to a medal being inserted into the medal slot 45 (step S1107). If a positive determination is made in step S1107, if the value of the bet count setting counter 74a of the main RAM 74 is less than the maximum bet (step S1108: NO), the value of the bet count setting counter 74a is incremented by 1 (step S1109), and if the value of the bet count setting counter 74a is equal to or greater than the maximum bet (step S1108: YES), the value of the credit counter 74b of the main RAM 74 is incremented by 1 (step S1110). If the process in step S1109 or step S1110 is executed, the acceptance prohibition process is executed (step S1112) on the condition that the value of the bet number setting counter 74a is equal to or greater than the maximum bet number and the value of the credit counter 74b is equal to or greater than the maximum storage memory (specifically "50"). As a result of the acceptance prohibition process being executed, even if a medal is inserted into the medal slot 45, the medal will not be detected by the inserted medal detection sensor 45a and will be discharged into the medal tray 59.

[0190] If a negative determination is made in step S1107, if a negative determination is made in step S1111, or if the process in step S1112 is executed, it is determined whether the current game state is the first CB state ST2 (step S1113). If the current game state is the first CB state ST2 (step S1113: YES), and provided that the value of the bet number setting counter 74a is "3" (step S1114: YES), the bet setting flag at the time of acceptance, which is set in the main RAM 74, is set to "1" (step S1115). On the other hand, if the current game state is not the first CB state ST2 (step S1113: NO), and provided that the value of the bet number setting counter 74a is 2 or more (step S1116: YES), the bet setting flag at the time of acceptance is set to "1" (step S1115).

[0191] The bet setting flag at acceptance is a flag used by the main MPU72 to determine whether the number of game tokens required to start one game have been bet. If the game state is the first CB state ST2, a game cannot be started unless "3" game tokens are bet, and a game can only be started when "3" game tokens are bet. Also, if the game state is not the first CB state ST2, a game cannot be started unless two or more game tokens are bet, and a game can only be started when two or more game tokens are bet.

[0192] Returning to the explanation of the start waiting process (Figure 26), after executing the bet response process in step S1005, it is determined whether or not the settlement button 51 has been operated (step S1006). If the settlement button 51 has been operated (step S1006: YES), after executing the settlement process (step S1007), the bet setting flag in the main RAM 74 at the time of receipt is cleared to "0" (step S1008). In the settlement process of step S1007, if the bet setting flag in the main RAM 74 at the time of replay is not set to "1", the hopper device 53 is driven and controlled so that a number of medals corresponding to the sum of the value of the bet number setting counter 74a and the value of the credit counter 74b are discharged into the medal tray 59. In this case, both the bet number setting counter 74a and the credit counter 74b are cleared to "0". On the other hand, if the bet setting flag for replay in the main RAM 74 is set to "1", the hopper device 53 is driven and controlled so that the number of medals corresponding to the value of the credit counter 74b is dispensed into the medal tray 59. In this case, the credit counter 74b is reset to "0".

[0193] As described above, the bet count setting counter 74a is set when the start waiting process is executed. As already explained, the slot machine 10 is provided with a bet display unit 64 on the front of the slot machine 10, and the bet display unit 64 displays the value corresponding to the bet count setting counter 74a. The display control of the bet display unit 64 is performed in the control process of the bet display unit 64 in step S509 of the timer interrupt process (Figure 19). Figure 28 is a flowchart of the control process of the bet display unit 64.

[0194] If the value of the bet count setting counter 74a is "0" (step S1201: YES), the all-lights-off process is executed (step S1202). As a result of the all-lights-off process, all three light-emitting units arranged vertically in the bet display unit 64 are turned off.

[0195] If the value of the bet count setting counter 74a is "1" (step S1203: YES), the first lighting process is executed (step S1204). When the first lighting process is executed, the bottom of the three light-emitting parts arranged vertically in the bet display unit 64 lights up, and the remaining light-emitting parts turn off.

[0196] If the value of the bet count setting counter 74a is "2" (step S1205: YES), the second lighting process is executed (step S1206). When the second lighting process is executed, the bottom and middle light-emitting parts of the three vertically arranged light-emitting parts in the bet display unit 64 are lit, while the top light-emitting part is turned off.

[0197] If the value of the bet count setting counter 74a is "3" (step S1205: NO), the third lighting process is executed (step S1207). When the third lighting process is executed, all three light-emitting parts arranged vertically in the bet display unit 64 become lit.

[0198] Returning to the explanation of the normal process (Figure 25), after executing the start waiting process in step S901, it is determined whether "1" is set in either the bet setting flag for replay or the bet setting flag for acceptance in the main RAM 74 (step S902). If the determination in step S902 is negative, the process returns to step S901. If the determination in step S902 is positive, it is determined whether the start lever 41 has been operated (step S903). If the start lever 41 has not been operated, the process returns to step S901.

[0199] If the start lever 41 is operated (step S903: YES), the main line ML is activated and then the acceptance prohibition process is executed (step S904). Because the acceptance prohibition process is executed, even if a medal is inserted into the medal slot 45, the medal will not be detected by the inserted medal detection sensor 45a and will be ejected into the medal tray 59. Also, in step S905, a start-up setting process is executed to make various settings when the game starts. In the start-up setting process, both the bet setting flag for replays and the bet setting flag for acceptance are cleared to "0".

[0200] Subsequently, in step S906, a lottery process for determining the winning combination in the current game is executed. In step S907, a freeze setting process for bonus transitions is executed to set a freeze period during which the reels 32L, 32M, and 32R wait to start spinning. In step S908, if a freeze period has been set, the system waits for the execution of subsequent processes. If a freeze period has not been set or if the measurement of the freeze period has been completed, in step S909, a reel control process is executed to drive and control each reel 32L, 32M, and 32R in a manner corresponding to the result of the lottery process for the winning combination in the current game.

[0201] Subsequently, in step S910, the media provision process is executed. In the media provision process, if a minor win has occurred in the current game, a process is executed to provide the player with a number of game media corresponding to the minor win. Specifically, when virtual medals are provided, a value corresponding to the minor win is added to the credit counter 74b of the main RAM 74, and if the value of the credit counter 74b has reached the upper limit of the stored memory, the hopper device 53 is driven and controlled so that the number of medals exceeding the upper limit of the stored memory is dispensed into the medal tray 59. In addition, during the media provision process, information on the number of game media to be provided is stored in the media provision counter provided in the main RAM 74. If the combined display unit 66 has not yet announced the stopping order of reels 32L, 32M, and 32R, the combined display unit 66 is displayed in the port output process (step S508) of the timer interrupt process (Figure 19) so that a value corresponding to the information stored in the media provision counter is displayed. This allows the player to determine the number of game media awarded as a result of a winning combination by checking the combined display unit 66 when a winning combination is achieved. The information stored in the media awarding counter is reset to "0" at the end of the pseudo-bonus state ST4 or when a new bet of game media is made. If the value of the media awarding counter becomes "0" when the stopping order of reels 32L, 32M, and 32R is not being announced, the combined display unit 66 will not display the number "0", but will instead turn off.

[0202] Subsequently, in step S911, the history storage process is executed (step S911). In the history storage process, the value of the bet count setting counter 74a of the main RAM 74 is set to the bet count history counter 74f of the main RAM 74. Also, the value of the media allocation counter of the main RAM 74 is set to the allocation count history counter of the main RAM 74.

[0203] Subsequently, in step S912, a processing step is performed to enable the setting of the game state and game section corresponding to the result of the current game. In step S913, an external output setting process is performed to output the status of the slot machine 10 to the management computer of the gaming hall. Then, in step S914, a reception permission process is performed. Once the reception permission process is performed, the tokens inserted from the token slot 45 are detected by the inserted token detection sensor 45a and then collected by the hopper device 53.

[0204] <Regarding the lottery process for roles> Next, we will explain the lottery process for determining the winning role, which is performed in step S906 of the normal process (Figure 25).

[0205] In the role selection process, the first random number obtained from the first random number circuit 75 is used to select the index value IV. Figure 29 is an explanatory diagram for explaining the contents of index value IV. There are 17 index values ​​IV set from "1" to "17", and winning data is set corresponding to each index value IV. In the following explanation, please refer to the explanatory diagram in Figure 30 as appropriate.

[0206] As shown in Figure 29, index values ​​IV=1 to 6 are set with data for the first bell win and one of the first to sixth compensation win data. When a win occurs with index value IV=1, as shown in Figure 30, if the first stop (the reel where the stop command was first issued) is the left reel 32L, the second stop (the reel where the stop command was second issued) is the middle reel 32M, and the third stop (the reel where the stop command was last issued) is the right reel 32R, a first bell win is guaranteed regardless of the timing of operation of each stop button 42 to 44, and in all other cases, a first compensation win may occur. When a win occurs with index value IV=2, if the first stop is the left reel 32L, the second stop is the right reel 32R, and the third stop is the middle reel 32M, a first bell win is guaranteed regardless of the timing of operation of each stop button 42 to 44, and in all other cases, a fourth compensation win may occur. If the win occurs with index value IV=3, and the first stop is the middle reel 32M, the second stop is the left reel 32L, and the third stop is the right reel 32R, then regardless of the timing of operation of stop buttons 42-44, the first bell win is guaranteed, and in other cases, the third compensation win may occur. If the win occurs with index value IV=4, and the first stop is the middle reel 32M, the second stop is the right reel 32R, and the third stop is the left reel 32L, then regardless of the timing of operation of stop buttons 42-44, the first bell win is guaranteed, and in other cases, the sixth compensation win may occur. If the win occurs with index value IV=5, and the first stop is the right reel 32R, the second stop is the left reel 32L, and the third stop is the middle reel 32M, then regardless of the timing of operation of stop buttons 42-44, the first bell win is guaranteed, and in other cases, the second compensation win may occur. If the win occurs with an index value of IV=6, and the first stop is the right reel 32R, the second stop is the middle reel 32M, and the third stop is the left reel 32L, then regardless of the timing of operation of each stop button 42-44, the first bell win is guaranteed, and in all other cases, the fifth compensation win may occur.

[0207] As previously explained, in this slot machine 10, when not in a CB state, reel control is performed on each reel 32L, 32M, and 32R that allows the reels to slide up to 4 symbols after stop buttons 42-44 are pressed. In other words, reel control is performed on each reel 32L, 32M, and 32R that stops the reels within a specified time (190 milliseconds) after stop buttons 42-44 are pressed. This type of reel control makes it easier to achieve winning combinations and prevents winning combinations that do not correspond to winning combinations from occurring. However, because the amount of rotation of the reels 32L, 32M, and 32R that can be slid is limited as described above, if there are five or more symbols between the symbols that make up the combination of symbols necessary to achieve a win on a single reel 32L, 32M, or 32R, depending on the timing of the operation of the corresponding stop buttons 42 to 44, it is possible that the symbols in question will not stop on the main line ML (this phenomenon is also called a "missed win"). Winning the first bell, second bell, and various replays are winning patterns in which no missed wins occur if the reels 32L, 32M, and 32R are stopped in the corresponding order, while winning the first to ninth compensation wins, first watermelon win, second watermelon win, cherry win, first CB win, and second CB win are winning patterns in which missed wins may occur depending on the timing of the stop operation of the stop buttons 42 to 44 relative to the rotation position of the reels 32L, 32M, and 32R.

[0208] As shown in Figure 29, index values ​​IV=7 to 9 are set to have data for the second bell win, as well as data for the seventh to ninth compensation win. When a win occurs with index value IV=7, as shown in Figure 30, if the first stop is the left reel 32L, a second bell win is guaranteed regardless of the type of reels 32L, 32M, and 32R targeted for the second and third stops, and the timing of operation of each stop button 42 to 44. Otherwise, a seventh compensation win may occur. When a win occurs with index value IV=8, if the first stop is the middle reel 32M, a second bell win is guaranteed regardless of the type of reels 32L, 32M, and 32R targeted for the second and third stops, and the timing of operation of each stop button 42 to 44. Otherwise, a ninth compensation win may occur. If a win occurs with index value IV=9, and the first stop is the right reel 32R, a second bell win is guaranteed regardless of the type of the second and third stop target reels 32L, 32M, and 32R, or the timing of operation of each stop button 42-44. Otherwise, an eighth compensation win may occur.

[0209] As shown in Figure 29, the index value IV=10 is set to the data for the first bell win. When a win occurs with index value IV=10, as shown in Figure 30, the first bell win is guaranteed regardless of the stopping order of reels 32L, 32M, and 32R and the timing of operation of each stop button 42-44.

[0210] As shown in Figure 29, the index value IV=11 is set to only the data for the first watermelon win. If a win occurs with index value IV=11, the first watermelon can be awarded regardless of the stopping order of reels 32L, 32M, and 32R, as shown in Figure 30. However, depending on the timing of operation of each stop button 42 to 44, the first watermelon may not be awarded. As shown in Figure 29, the index value IV=12 is set to only the data for the second watermelon win. If a win occurs with index value IV=12, the second watermelon can be awarded regardless of the stopping order of reels 32L, 32M, and 32R, as shown in Figure 30. However, depending on the timing of operation of each stop button 42 to 44, the second watermelon may not be awarded.

[0211] As shown in Figure 29, only cherry winning data is set for index value IV=13. When a win occurs with index value IV=13, a cherry can be awarded regardless of the stopping order of reels 32L, 32M, and 32R, as shown in Figure 30. However, depending on the timing of the operation of the left stop button 42 in relation to the rotation position of the left reel 32L, a cherry may not be awarded.

[0212] As shown in Figure 29, the index value IV=14 is set to only the data for winning the first chance replay. When a win occurs with index value IV=14, as shown in Figure 30, the first chance replay is guaranteed regardless of the stopping order of reels 32L, 32M, and 32R and the timing of operation of stop buttons 42 to 44. Also, as shown in Figure 29, the index value IV=15 is set to only the data for winning the second chance replay. When a win occurs with index value IV=15, as shown in Figure 30, the second chance replay is guaranteed regardless of the stopping order of reels 32L, 32M, and 32R and the timing of operation of stop buttons 42 to 44. Also, as shown in Figure 29, the index value IV=16 is set to only the data for winning a normal replay. When a win occurs with index value IV=16, as shown in Figure 30, the normal replay is guaranteed regardless of the stopping order of reels 32L, 32M, and 32R and the timing of operation of stop buttons 42 to 44.

[0213] As shown in Figure 29, only CB winning data is set for index value IV=17. In this case, if the number of bets on the game medium is "3" and a win occurs with index value IV=17, it means that the 1st CB winning data has been won, and if the number of bets on the game medium is "2" and a win occurs with index value IV=17, it means that the 2nd CB winning data has been won. In other words, the 1st CB winning data is data that is set as a winning combination only when the number of bets on the game medium is "3". And the 1st CB win can only occur when the number of bets on the game medium is "3". Also, the 2nd CB winning data is data that is set as a winning combination only when the number of bets on the game medium is "2". And the 2nd CB win can only occur when the number of bets on the game medium is "2". If the 1st CB winning data is set, and the number of bets on the game medium is "3", then the 1st CB win can occur regardless of the stopping order of reels 32L, 32M, and 32R, as shown in Figure 30. However, depending on the timing of operation of each stop button 42-44, it is possible that the first CB win may not occur. If the data for the second CB win is set, and the number of bets on the game medium is "2", then as shown in Figure 30, the second CB win may occur regardless of the stopping order of reels 32L, 32M, and 32R. However, depending on the timing of operation of each stop button 42-44, it is possible that the second CB win may not occur.

[0214] Here, winning data other than the 1st CB winning data and the 2nd CB winning data is erased in the game in which it was won, regardless of whether the corresponding prize was achieved or not, and is not carried over to subsequent games. In contrast, the 1st CB winning data and the 2nd CB winning data are retained in memory until the corresponding prize is achieved, even in subsequent games following the game in which they were won, unless the main RAM 74 is cleared. In this case, in games where either the 1st CB winning data or the 2nd CB winning data is carried over, the index value IV corresponding to the 1st CB winning data or the 2nd CB winning data is excluded from the lottery.

[0215] In other words, if the game is played with a bet of "3," and as a result the first CB winning data is set in the main RAM74 but the first CB win is not achieved, and the first CB winning data is carried over, then even if the game is played again with a bet of "3," the index value IV corresponding to the first CB winning data will be excluded from the draw, and even if the game is played again with a bet of "2," the index value IV corresponding to the second CB winning data will be excluded from the draw. This makes it possible to prevent either the first or second CB winning data from being newly stored even if either of them is already stored, thus preventing multiple CB winning data from being accumulated and stored.

[0216] The second CB winning data is stored in the second CB winning data area corresponding to address "0000" in the main RAM 74, and the first CB winning data is stored in the first CB winning data area corresponding to address "0001" in the main RAM 74 (see Figure 16). As already explained, when the setting change process (Figure 15) is executed, the main RAM 74 clear process is executed. In this case, if the reset button 56 is not pressed when the power supply is started and no information abnormality occurs in the main RAM 74, the clear process is executed on the storage areas of the main RAM 74 except for the second CB winning data area. However, if the reset button 56 is pressed when the power supply is started or an information abnormality occurs in the main RAM 74, the clear process is executed on all storage areas of the main RAM 74, including the second CB winning data area. This makes it possible to choose whether or not to erase the second CB winning data depending on whether or not the reset button 56 is pressed when no information abnormality occurs in the main RAM 74. Furthermore, if an information anomaly occurs in the main RAM 74, it becomes possible to perform a clear process on the entire memory area of ​​the main RAM 74, including the second CB winning data.

[0217] In the configuration described above, where the index value IV is set, a point value PV is set for each index value IV corresponding to each game state. Specifically, when the state is 1st CB state ST2 or 2nd CB state ST3, only index value IV=16 is set as the target of the lottery, and index values ​​IV=1~15 and 17 are not set as the target of the lottery. Furthermore, when the state is not CB and neither the 1st CB winning data nor the 2nd CB winning data is stored, all index values ​​IV=1~17 are set as the target of the lottery, and when the state is not CB and either the 1st CB winning data or the 2nd CB winning data is stored, index values ​​IV=1~16 are set as the target of the lottery, but index value IV=17 is not set as the target of the lottery.

[0218] When the number of bets is "2" in a non-CB state, the point value PV set for each index value IV=1 to 16 is the same regardless of whether the 1st CB winning data or the 2nd CB winning data is stored or not. As a result, when the number of bets is "2" in a non-CB state, the winning probabilities for each index value IV=1 to 16 are the same whether either the 1st CB winning data or the 2nd CB winning data is stored or neither the 1st CB winning data or the 2nd CB winning data is stored. Similarly, when the number of bets is "3" in a non-CB state, the point value PV set for each index value IV=1 to 16 is the same regardless of whether either the 1st CB winning data or the 2nd CB winning data is stored or not. As a result, when the number of bets is "3" in a non-CB state, the winning probabilities for each index value IV=1 to 16 are the same whether either the 1st CB winning data or the 2nd CB winning data is stored or neither the 1st CB winning data or the 2nd CB winning data is stored.

[0219] When the number of bets is "2" in a non-CB state, the probability of winning at each index value IV=1 to 16 is lower than when the number of bets is "3" in a non-CB state. Specifically, when the number of bets is "2" in a non-CB state, the probability of winning at each index value IV=1 to 16 is less than 2 / 3 of the probability when the number of bets is "3" in a non-CB state. As a result, games played with a bet of "3" have a higher probability of winning small prizes that grant game tokens and replays that grant replays than games played with a bet of "2".

[0220] However, in a non-CB state where neither the 1st CB winning data nor the 2nd CB winning data is stored, the probability of winning when the index value IV = 17 is approximately 1 / 2.2, whereas in a non-CB state where neither the 1st CB winning data nor the 2nd CB winning data is stored, the probability of winning when the index value IV = 17 is approximately 1 / 3.3. This makes it possible to make the probability of a game with a bet of "2" being played and the 2nd CB winning data being stored in the main RAM 74 in a non-CB state where neither the 1st CB winning data nor the 2nd CB winning data is stored higher than the probability of a game with a bet of "3" being played and the 1st CB winning data being stored in the main RAM 74 in a non-CB state where neither the 1st CB winning data nor the 2nd CB winning data is stored.

[0221] In this slot machine 10, six setting values ​​from "1" to "6" are pre-set, and by executing the setting change process (Figure 15) described earlier, it is possible to set the setting value to be used. Then, in the prize draw process, the winning index value IV is drawn according to the winning probability corresponding to the setting value to be used. A setting value of "n+1" is more advantageous for the player than a setting value of "n". Specifically, a setting value of "n+1" is more advantageous for the player than a setting value of "n" because the winning probability of a given index value IV (i.e., a given prize) is higher when the setting value is "n+1" than when the setting value is "n". In a non-CB state, the winning probability of each index value IV changes according to the setting value. However, this is not limited to this, and it is also possible to have a configuration where the winning probability of some index values ​​IV changes according to the setting value, while the winning probability of other index values ​​IV does not change according to the setting value. Note that the point value PV exemplified in Figure 29 is for a setting value of "3". In the CB state, as described above, only the index value IV=16 is subject to the lottery, but the point value PV for this index value IV is the same regardless of the setting.

[0222] This section describes the specific configuration for performing the role lottery process. Figure 31(a) is an explanatory diagram illustrating the contents of the data in the main ROM 73 used for the role lottery process.

[0223] The main ROM 73 pre-stores the following tables as data referenced when executing the draw for winning hands: a set of winning hands draw tables 73a for setting 1, referenced when the setting value for the target is "1"; a set of winning hands draw tables 73b for setting 2, referenced when the setting value for the target is "2"; a set of winning hands draw tables 73c for setting 3, referenced when the setting value for the target is "3"; a set of winning hands draw tables 73d for setting 4, referenced when the setting value for the target is "4"; a set of winning hands draw tables 73e for setting 5, referenced when the setting value for the target is "5"; and a set of winning hands draw tables 73f for setting 6, referenced when the setting value for the target is "6". Each set of winning hands draw tables 73a to 73f contains data for the corresponding setting value that enables the execution of the draw for winning hands based on the relationship between the index value IV and the point value PV in each game state, as shown in Figure 29.

[0224] Figure 32 is an explanatory diagram illustrating the contents of the role lottery tables 73a to 73f. While Figure 32 shows the role lottery table 73c for setting 3 as an example, the other role lottery tables 73a, 73b, 73d to 73f have the same basic data structure, although the specific point values ​​PV differ.

[0225] The role selection tables 73a to 73f each have data sets 101a to 10q corresponding to index values ​​IV=1 to 17. Specifically, there is a data group 101a for IV=1 that is referenced when performing the hand lottery process for index value IV=1, a data group 101b for IV=2 that is referenced when performing the hand lottery process for index value IV=2, a data group 101c for IV=3 that is referenced when performing the hand lottery process for index value IV=3, a data group 101d for IV=4 that is referenced when performing the hand lottery process for index value IV=4, a data group 101e for IV=5 that is referenced when performing the hand lottery process for index value IV=5, a data group 101f for IV=6 that is referenced when performing the hand lottery process for index value IV=6, a data group 101g for IV=7 that is referenced when performing the hand lottery process for index value IV=7, a data group 101h for IV=8 that is referenced when performing the hand lottery process for index value IV=8, and a data group 101f for IV=6 that is referenced when performing the hand lottery process for index value IV=9. Data set 101i for IV=9, data set 101j for IV=10 which is referenced when performing the draw process for index value IV=10, data set 101k for IV=11 which is referenced when performing the draw process for index value IV=11, data set 101l for IV=12 which is referenced when performing the draw process for index value IV=12, and data set 101l for IV=13 which is referenced when performing the draw process for index value IV=13 1m is set, along with a data group 101n for IV=14, which is referenced when performing the lottery process for the index value IV=14; a data group 101o for IV=15, which is referenced when performing the lottery process for the index value IV=15; a data group 101p for IV=16, which is referenced when performing the lottery process for the index value IV=16; and a data group 101q for IV=17, which is referenced when performing the lottery process for the index value IV=17.

[0226] As will be explained in more detail later, in any game state, the lottery process for winning a prize involves referring to each data group 101a to 101q in order, starting with the data group 101a for IV=1. Each of these data groups 101a to 101q contains data indicating whether or not each game state is subject to lottery, data indicating the type of winning data to be set when the corresponding index value IV is won, and data indicating the point value PV for each game state that is subject to lottery.

[0227] The contents of data sets 101a to 101q will be explained with reference to the explanatory diagram in Figure 33. Figure 33(a) is an explanatory diagram for data set 101a for IV=1, Figure 33(b) is an explanatory diagram for data set 101p for IV=16, and Figure 33(c) is an explanatory diagram for data set 101q for IV=17. Although the contents of the data sets 101b to 101o for IV=2 to 15 differ, the basic data structure is the same.

[0228] As shown in Figures 33(a) to 33(c), each data group 101a, 101p, and 101q contains game state data 102a, 103a, and 104a, respectively, which indicate whether or not a game state is eligible for a lottery. Each game state data 102a, 103a, and 104a has a data capacity of 1 byte. In the game state data 102a, 103a, and 104a, there are five types of game states that can be classified: CB state (1st CB state ST2 or 2nd CB state ST3), non-CB state where CB winning data (1st CB winning data or 2nd CB winning data) is not stored and the number of bets is "2" (hereinafter referred to as the 2-coin bet state in non-internal mode), non-CB state where CB winning data (1st CB winning data or 2nd CB winning data) is not stored and the number of bets is "3" (hereinafter referred to as the 3-coin bet state in non-internal mode), non-CB state where CB winning data (1st CB winning data or 2nd CB winning data) is stored and the number of bets is "2" (hereinafter referred to as the 2-coin bet state in internal mode), and non-CB state where CB winning data (1st CB winning data or 2nd CB winning data) is stored and the number of bets is "3" (hereinafter referred to as the 3-coin bet state in internal mode). Of these five game states, the CB state is assigned the lowest bit D0 in game state data 102a, 103a, and 104a; the non-internal 2-coin bet state is assigned the second lowest bit D1 in game state data 102a, 103a, and 104a; the non-internal 3-coin bet state is assigned the third lowest bit D2 in game state data 102a, 103a, and 104a; the internal 2-coin bet state is assigned the fourth lowest bit D3 in game state data 102a, 103a, and 104a; and the internal 3-coin bet state is assigned the fifth lowest bit D4 in game state data 102a, 103a, and 104a. The remaining bits D5 to D7 in game state data 102a, 103a, and 104a are blank and not assigned to any game state.

[0229] Regarding the data set 101a for IV=1, as already explained, the index value IV=1 is not set as a target for the lottery in the CB state, but is set as a target for the lottery in the non-internal 2-coin bet state, non-internal 3-coin bet state, internal 2-coin bet state, and internal 3-coin bet state. Therefore, as shown in Figure 33(a), in the game state data 102a, the least significant bit D0 is set to "0", and the second to fifth least significant bits D1 to D4 are set to "1". The content of this data is the same for the data sets 101b to 101o for IV=2 to 15.

[0230] Regarding the data set 101p for IV=16, as already explained, the index value IV=16 is set as a target for drawing in all of the following states: CB state, non-internal 2-coin bet state, non-internal 3-coin bet state, internal 2-coin bet state, and internal 3-coin bet state. Therefore, as shown in Figure 33(b), in the game state data 103a, the least significant to fifth bits D0 to D4 are set to "1".

[0231] Regarding the data set 101q for IV=17, as already explained, the index value IV=17 is not set as a target for drawing in the CB state, the internal 2-coin bet state, and the internal 3-coin bet state, but is set as a target for drawing in the non-internal 2-coin bet state and the non-internal 3-coin bet state. Therefore, as shown in Figure 33(c), in the game state data 104a, the least significant bit D0, the fourth least significant bit D3, and the fifth least significant bit D4 are set to "0", while the second least significant bit D1 and the third least significant bit D2 are set to "1".

[0232] As described above, with the game state data 102a, 103a, and 104a set, it becomes possible to determine whether or not the index value IV of the corresponding data group 101a to 101q is subject to a draw in the game state corresponding to the bit set to "1" in the game state data 102a, 103a, and 104a.

[0233] As shown in FIGS. 33(a) to 33(c), in each data group 101a, 101p, 101q, winning target data 102b, 103b, 104b are set as data indicating the type of winning data set when the corresponding index value IV is elected. The winning target data 102b, 103b, 104b have a data capacity of 2 bytes. Specifically, as shown in FIG. 33(a) for the data group 101a for IV = 1, the winning target data 102b is set with first bell winning data and first interpolation winning data. Specifically, as shown in FIG. 33(b) for the data group 101p for IV = 16, the winning target data 103b is set with normal replay winning data. Specifically, as shown in FIG. 33(c) for the data group 101q for IV = 17, the winning target data 104b is set with CB winning data.

[0234] Since the winning target data 102b, 103b, 104b are set as described above, as a result of performing a role lottery process by referring to the data groups 101a to 101q, when the index value IV of a predetermined data group 101a to 101q is elected, it becomes possible to specify the type of the elected winning data by referring to the predetermined data group 101a to 101q.

[0235] As shown in Figures 33(a) to 33(c), each data group 101a, 101p, and 101q has point value data 102c, 103c, and 104c set as data indicating the point value PV for each game state subject to lottery. Point value data 102c, 103c, and 104c are set as a combination of address data, which is a 1-byte data capacity, and point value PV, which is a 2-byte data capacity, for the number of bits set to "1" in the corresponding game state data 102a, 103a, and 104a, and are set corresponding to each bit that is set to "1". In this case, if there are multiple combinations of address data and point value PV in point value data 102c, 103c, and 104c, the combinations corresponding to the lower bits in the corresponding game state data 102a, 103a, and 104a are set to earlier addresses in the address data.

[0236] Regarding the data group 101a for IV=1, as already explained, the index value IV=1 is not set as a target for drawing in the CB state, but is set as a target for drawing in the 2-coin bet state during non-internal, 3-coin bet state during non-internal, 2-coin bet state during internal, and 3-coin bet state during internal. In this case, as shown in Figure 33(a), four types of combinations of address data and point value PV are set in the point value data 102c. The first address data A(0) corresponds to the second lowest bit D1 in the game state data 102a, i.e., the 2-coin bet state during non-internal, and a point value PV of "900" is set in association with A(0). The next address data A(1) corresponds to the third lowest bit D2 in the game state data 102a, i.e., the 3-coin bet state during non-internal, and a point value PV of "3000" is set in association with A(1). The next address data, A(2), corresponds to the fourth bit from the bottom, D3, in the game state data 102a, i.e., the internal 2-coin bet state, and a point value PV of "900" is set in association with A(2). The next address data, A(3), corresponds to the fourth bit from the bottom, D3, in the game state data 102a, i.e., the internal 3-coin bet state, and a point value PV of "3000" is set in association with A(3).

[0237] Regarding the data group 101p for IV=16, as already explained, the index value IV=16 is set as the target of the draw in all of the following states: CB state, non-internal 2-coin bet state, non-internal 3-coin bet state, internal 2-coin bet state, and internal 3-coin bet state. In this case, as shown in Figure 33(b), five types of combinations of address data and point value PV are set in the point value data 103c. The first address data, B(0), corresponds to the lowest bit D0 in the game state data 103a, i.e., the CB state, and a point value PV of "9000" is set in association with B(0). The next address data, B(1), corresponds to the second lowest bit D1 in the game state data 103a, i.e., the non-internal 2-coin bet state, and a point value PV of "5500" is set in association with B(1). The next address data, B(2), corresponds to the third bit from the bottom, D2, in the game state data 103a, i.e., the 3-coin bet state while not internal, and a point value PV of "9000" is set in association with B(2). The next address data, B(3), corresponds to the fourth bit from the bottom, D3, in the game state data 103a, i.e., the 2-coin bet state while internal, and a point value PV of "5500" is set in association with B(3). The next address data, B(4), corresponds to the fourth bit from the bottom, D3, in the game state data 103a, i.e., the 3-coin bet state while internal, and a point value PV of "9000" is set in association with B(4).

[0238] Regarding the data group 101q for IV=17, as already explained, the index value IV=17 is not set as a target for drawing in the CB state, the internal 2-coin bet state, and the internal 3-coin bet state, but is set as a target for drawing in the non-internal 2-coin bet state and the non-internal 3-coin bet state. In this case, as shown in Figure 33(c), there are two types of combinations of address data and point value PV set in the point value data 104c. The first address data C(0) corresponds to the second lowest bit D1 in the game state data 102a, i.e., the non-internal 2-coin bet state, and a point value PV of "30000" is set in association with C(0). The next address data C(1) corresponds to the third lowest bit D2 in the game state data 102a, i.e., the non-internal 3-coin bet state, and a point value PV of "20000" is set in association with C(1).

[0239] As described above, with point value data 102c, 103c, and 104c set, if the game state data 102a, 103a, and 104a in the data group 101a to 101q is identified as being eligible for the lottery in the current game state, then the point value PV corresponding to the current game state can be identified by referring to point value data 102c, 103c, and 104c.

[0240] As described above, the draw process for winning hands is performed using the data sets 101a to 101q for IV=1 to 17, and various areas of the main RAM 74 are used in this draw process. Figure 31(b) is an explanatory diagram illustrating the contents of the memory areas of the main RAM 74 used for the draw process.

[0241] As shown in Figure 31(b), the main RAM 74 is equipped with a determination value counter 74j, a lottery number counter 74k, and an address counter 74l. The determination value counter 74j is used to determine whether the current game state is a CB state, a non-internal 2-coin bet state, a non-internal 3-coin bet state, an internal 2-coin bet state, or an internal 3-coin bet state. The lottery number counter 74k is used to determine which index value IV is being targeted in the lottery process for winning hands. The address counter 74l is used to determine which address data among the point value data 102c, 103c, and 104c of the data group 101a to 101q for IV=1 to 17 that is being referenced is being referenced.

[0242] The following explains the processing configuration for the role selection process, referring to the flowchart in Figure 34.

[0243] First, a first random number is obtained to determine whether a winning combination is achieved (step S1301). In this slot machine 10, when the start lever 41 is operated, the first random number at that moment is latched from the first random number circuit 75. The first random number circuit 75 generates a first random number between "0" and "65535", and when the main MPU 72 confirms that the start lever 41 has been operated, it stores the value latched by the first random number circuit 75 in the main RAM 74. This configuration makes it possible to quickly obtain the first random number when the start lever 41 is operated. The first random number circuit 75 is configured to latch the value of the free run counter each time the start lever 41 is operated.

[0244] After obtaining the first random number, the system checks the setting value storage area of ​​the main RAM 74 to determine which setting value is being used, and reads the corresponding role lottery tables 73a to 73f from the main ROM 73 into the main RAM 74 (step S1302). In this case, if the setting value being used is "1", the role lottery table group 73a for setting 1 is read; if the setting value being used is "2", the role lottery table group 73b for setting 2 is read; if the setting value being used is "3", the role lottery table group 73c for setting 3 is read; if the setting value being used is "4", the role lottery table group 73d for setting 4 is read; if the setting value being used is "5", the role lottery table group 73e for setting 5 is read; and if the setting value being used is "6", the role lottery table group 73f for setting 6 is read.

[0245] Subsequently, the process of acquiring the judgment value is executed (step S1303). Figure 35 is a flowchart of the process of acquiring the judgment value. If the current game state is the CB state (first CB state ST2 or second CB state ST3) (step S1401: YES), the judgment value counter 74j of the main RAM 74 is set to "1" (step S1402), and then this acquisition process is terminated. Note that the judgment value counter 74j is cleared to "0" when the judgment value acquisition process is started. Therefore, when the process in step S1402 is executed, the value of the judgment value counter 74j becomes "1".

[0246] If the current game state is not CB state (Step S1401: NO), the value of the bet count setting counter 74a of the main RAM 74 is added to the judgment value counter 74j (Step S1403). In this case, if the value of the bet count setting counter 74a is "2", that is, if the number of bets in this game is "2", the value of the judgment value counter 74j becomes "2", and if the value of the bet count setting counter 74a is "3", that is, if the number of bets in this game is "3", the value of the judgment value counter 74j becomes "3".

[0247] Subsequently, if CB winning data (first CB winning data or second CB winning data) is stored in the main RAM 74 (step S1404: YES), "2" is added to the judgment value counter 74j (step S1405), and then this acquisition process ends. If CB winning data (first CB winning data or second CB winning data) is not stored in the main RAM 74 (step S1404: NO), this acquisition process ends as is.

[0248] As described above, when the judgment value acquisition process (Figure 35) is executed, the value of the judgment value counter 74j becomes "1" if the game state is the CB state, the value of the judgment value counter 74j becomes "2" if the game state is the 2-coin bet state (not internal), the value of the judgment value counter 74j becomes "3" if the game state is the 3-coin bet state (not internal), the value of the judgment value counter 74j becomes "4" if the game state is the 2-coin bet state (internal), and the value of the judgment value counter 74j becomes "5" if the game state is the 3-coin bet state (internal). Thus, by checking the value of the judgment value counter 74j, it is possible to determine whether the current game state is the CB state, the 2-coin bet state (not internal), the 3-coin bet state (not internal), the 2-coin bet state (internal), or the 3-coin bet state (internal).

[0249] Returning to the explanation of the role lottery process (Figure 34), after the process of obtaining the judgment value is executed in step S1303, the lottery counter 74k of the main RAM 74 is set to "1" (step S1304). As already explained, the lottery counter 74k is used to identify which index value IV is the target of the lottery in the role lottery process. When the lottery counter 74k is set to "1", the index value IV that is the target of the lottery in the role lottery process becomes "1".

[0250] Next, the PV acquisition process is executed (step S1305). Figure 36 is a flowchart of the PV acquisition process. First, in step S1302 of the role lottery process (Figure 34), the data group 101a to 101q for IV=1 to 17 in the role lottery table group 73a to 73f read into the main RAM 74 is read (step S1501). In this case, if the value of the lottery counter 74k is X (X=1 to 17), the data group 101a to 101q for IV=X is read.

[0251] Subsequently, in step S1501, each bit of the game state data 102a to 104a in the data group 101a to 101q is shifted by one bit to the lower side (i.e., to the right) (step S1502). For example, in the case of game state data 102a in Figure 33(a), the data of bit Dm (m=1 to 7) is shifted to bit D(m-1). Also, the data of bit D0, which is the least significant bit, is shifted to the carry flag 77 (see Figure 9) provided on the main MPU 72. Then, it is determined whether the value of the carry flag 77 is "1" or not (step S1503). In the case of game state data 102a in Figure 33(a), if the process in step S1502 is executed once, the value of the carry flag 77 is "0". In the case of game state data 103a in Figure 33(b), if the process in step S1502 is executed once, the value of the carry flag 77 is "1".

[0252] If the value of the carry flag 77 is "1" (step S1503: YES), the value of the address counter 74l in the main RAM 74 is incremented by 1 (step S1504). As previously explained, the address counter 74l is used to identify which of the point value data 102c, 103c, and 104c of the data group 101a to 101q for IV=1 to 17 that is being referenced is being referenced. Note that the address counter 74l is cleared to "0" when the process in step S1501 is executed.

[0253] If a negative result is obtained in step S1503, or if the process in step S1504 is executed, the value of the judgment value counter 74j in the main RAM 74 is decremented by 1 (step S1505). As explained earlier, the judgment value counter 74j has a value set in step S1303 in the role lottery process (Figure 34) that corresponds to the current game state. Then, it is determined whether the value of the judgment value counter 74j after the 1 decrement is "0" or not (step S1506). If the value of the judgment value counter 74j is not "0" (step S1506: NO), the processes in steps S1502 to S1505 are executed again.

[0254] If the value of the judgment value counter 74j is "0" (step S1506: YES), it is determined whether the value of the carry flag 77 of the main MPU 72 is "1" (step S1507). If the value of the carry flag 77 is "1" (step S1507: YES), the address data corresponding to the current value of the address counter 74l in the main RAM 74 is identified from the point value data 102c to 104c in the data group 101a to 101q read in step S1501, and the point value PV corresponding to the identified address data is obtained from the point value data 102c to 104c (step S1508). This point value PV becomes the point value PV of the index value IV that is currently subject to lottery. On the other hand, if the value of the carry flag is "0" (step S1507: NO), "0" is recognized as the point value PV of the index value IV that is currently subject to lottery (step S1509).

[0255] As described above, in the PV acquisition process (Fig. 36), in step S1505, the value of the determination value counter 74j is decremented by 1, and when the value of the determination value counter 74j after the decrement becomes "0", the process for acquiring the point value PV in steps S1507 to S1509 is executed. Therefore, if the gaming state is the CB state, when the processes in steps S1502 to S1505 are executed once, the process for acquiring the point value PV in steps S1507 to S1509 is executed. If the gaming state is the two-bet state during non-internal play, when the processes in steps S1502 to S1505 are executed twice, the process for acquiring the point value PV in steps S1507 to S1509 is executed. If the gaming state is the three-bet state during non-internal play, when the processes in steps S1502 to S1505 are executed three times, the process for acquiring the point value PV in steps S1507 to S1509 is executed. If the gaming state is the two-bet state during internal play, when the processes in steps S1502 to S1505 are executed four times, the process for acquiring the point value PV in steps S1507 to S1509 is executed. If the gaming state is the three-bet state during internal play, when the processes in steps S1502 to S1505 are executed five times, the process for acquiring the point value PV in steps S1507 to S1509 is executed.

[0256] On the other hand, in step S1502, a shift process is performed on the game state data 102a to 104a. If, as a result of this shift process, the carry flag 77 of the main MPU 72 is set to "1", then in step S1504, the value of the address counter 74l of the main RAM 74 is incremented by 1. Furthermore, in the process for obtaining the point value PV in steps S1507 to S1509, if the value of the judgment value counter 74j becomes "0" in step S1506, and the value set in the carry flag 77 in the shift process in the preceding step S1502 is "1", then the point value PV corresponding to the address data of the address counter 74l of the main RAM 74 is obtained in the point value data 102c to 104c. If the value of the carry flag 77 is "0", then the point value PV becomes "0".

[0257] If the CB state is active, the process to obtain the point value PV in steps S1507 to S1509 is executed once after the process in steps S1502 to S1505 is executed as described above. Therefore, if the CB state is active and the carry flag 77 is "1" after the process in steps S1502 to S1505 is executed once, the point value PV corresponding to the first address data is obtained from point value data 102c to 104c, and if the carry flag 77 is "0", the point value PV will be "0".

[0258] If the game state is a non-internal two-coin bet state, then as described above, when the processing of steps S1502 to S1505 is executed twice, the processing to obtain the point value PV in steps S1507 to S1509 is executed. Therefore, if the carry flag 77 is "1" when the processing of steps S1502 to S1505 is executed twice in a non-internal two-coin bet state, the point value PV corresponding to the address data at that time is obtained from point value data 102c to 104c, and if the carry flag 77 is "0", the point value PV will be "0".

[0259] If the game state is a non-internal 3-coin bet state, then as described above, when the processing of steps S1502 to S1505 is executed three times, the processing to obtain the point value PV in steps S1507 to S1509 is executed. Therefore, if the game state is a non-internal 3-coin bet state, when the processing of steps S1502 to S1505 is executed three times, if the carry flag 77 is "1", the point value PV corresponding to the address data at that time is obtained from the point value data 102c to 104c, and if the carry flag 77 is "0", the point value PV will be "0".

[0260] If the game state is an internal 2-coin bet state, then as described above, when the processing of steps S1502 to S1505 is executed four times, the processing to obtain the point value PV in steps S1507 to S1509 is executed. Therefore, if the internal 2-coin bet state is in place, when the processing of steps S1502 to S1505 is executed four times, if the carry flag 77 is "1", the point value PV corresponding to the address data at that time is obtained from the point value data 102c to 104c, and if the carry flag 77 is "0", the point value PV will be "0".

[0261] If the game state is an internal 3-coin bet state, then as described above, when the processing of steps S1502 to S1505 is executed 5 times, the processing to obtain the point value PV in steps S1507 to S1509 is executed. Therefore, if the internal 3-coin bet state is in place, when the processing of steps S1502 to S1505 is executed 5 times, if the carry flag 77 is "1", the point value PV corresponding to the address data at that time is obtained from the point value data 102c to 104c, and if the carry flag 77 is "0", the point value PV will be "0".

[0262] If the value of the lottery counter 74k in the main RAM 74 is "1" and the data group 101a for IV=1 is read in step S1501, then as shown in Figure 33(a), the least significant bit D0 of the game state data 102a is "0", and the second to fifth least significant bits D1 to D4 are set to "1". Therefore, if step S1502 in the PV acquisition process (Figure 36) is executed once, the value of the carry flag 77 will be "0", and if step S1502 is executed two to five times, the value of the carry flag 77 will be "1".

[0263] In other words, if it is in a CB state, when the process to obtain the point value PV for steps S1507 to S1509 is executed, the carry flag 77 is "0", so the point value PV is "0". If it is in a non-internal two-bet state, when the process to obtain the point value PV for steps S1507 to S1509 is executed, the carry flag 77 is "1", and furthermore, since the process in step S1504 has been executed once before the process in steps S1507 to S1509 is executed, the value of address counter 74l is "1". Therefore, the address data corresponding to the value of address counter 74l is A(0), and the point value PV of "900" corresponding to that address data is obtained. If the game is in a non-internal 3-coin bet state, the carry flag 77 is "1" when the process to obtain the point value PV in steps S1507 to S1509 is executed. Furthermore, since the process in step S1504 is executed twice before the process in steps S1507 to S1509 is executed, the value of address counter 74l is "2". Therefore, the address data corresponding to the value of address counter 74l is A(1), and the point value PV of "3000" corresponding to that address data is obtained. If the game is in an internal 2-coin bet state, the carry flag 77 is "1" when the process to obtain the point value PV in steps S1507 to S1509 is executed. Furthermore, since the process in step S1504 is executed three times before the process in steps S1507 to S1509 is executed, the value of address counter 74l is "3". Therefore, the address data corresponding to the value of address counter 74l is A(2), and the point value PV of "900" corresponding to that address data is obtained. If the internal state is a 3-coin bet, the carry flag 77 is "1" when the process to obtain the point value PV in steps S1507 to S1509 is executed. Furthermore, since the process in step S1504 is executed four times before the process in steps S1507 to S1509 is executed, the value of address counter 74l is "4".Therefore, the address data corresponding to the value of address counter 74l becomes A(3), and the point value PV of "3000" corresponding to that address data is obtained.

[0264] If the value of the lottery counter 74k in the main RAM 74 is "16" and the data group 101p for IV=16 is read in step S1501, then as shown in Figure 33(b), all of the bits D0 to D4 from the least significant to the fifth least significant bit in the game state data 102a are set to "1". Therefore, when the process to obtain the point value PV in steps S1507 to S1509 is executed, the carry flag 77 is "1".

[0265] In other words, if it is in CB state, when the process to obtain the point value PV for steps S1507 to S1509 is executed, the carry flag 77 is "1", and furthermore, since the process of step S1504 has been executed once before the process of steps S1507 to S1509 is executed, the value of address counter 74l is "1". Therefore, the address data corresponding to the value of address counter 74l is B(0), and the point value PV of "9000" corresponding to that address data is obtained. If it is in a non-internal 2-coin bet state, when the process to obtain the point value PV for steps S1507 to S1509 is executed, the carry flag 77 is "1", and furthermore, since the process of step S1504 has been executed twice before the process of steps S1507 to S1509 is executed, the value of address counter 74l is "2". Therefore, the address data corresponding to the value of address counter 74l is B(1), and the point value PV of "5500" corresponding to that address data is obtained. If the game is in a non-internal 3-coin bet state, the carry flag 77 is "1" when the process to obtain the point value PV in steps S1507 to S1509 is executed. Furthermore, since the process in step S1504 has been executed 3 times before the process in steps S1507 to S1509 is executed, the value of address counter 74l is "3". Therefore, the address data corresponding to the value of address counter 74l is B(2), and the point value PV of "9000" corresponding to that address data is obtained. If the game is in an internal 2-coin bet state, the carry flag 77 is "1" when the process to obtain the point value PV in steps S1507 to S1509 is executed. Furthermore, since the process in step S1504 has been executed 4 times before the process in steps S1507 to S1509 is executed, the value of address counter 74l is "4". Therefore, the address data corresponding to the value of address counter 74l is B(3), and the point value PV of "5500" corresponding to that address data is obtained.If the internal state is a 3-coin bet, the carry flag 77 is "1" when the process to obtain the point value PV in steps S1507 to S1509 is executed. Furthermore, since the process in step S1504 has been executed 5 times before the process in steps S1507 to S1509 is executed, the value of address counter 74l is "5". Therefore, the address data corresponding to the value of address counter 74l is B(4), and the point value PV of "9000" corresponding to that address data is obtained.

[0266] If the value of the lottery counter 74k in the main RAM 74 is "17" and the data group 101q for IV=17 is read in step S1501, then as shown in Figure 33(c), the game state data 102a has "0" set in the least significant bit D0, the fourth least significant bit D3, and the fifth least significant bit D4, and "1" set in the second least significant bit D1 and the third least significant bit D2. Therefore, if step S1502 in the PV acquisition process (Figure 36) is executed once, four times, or five times, the value of the carry flag 77 will be "0", and if step S1502 is executed two times or three times, the value of the carry flag 77 will be "1".

[0267] In other words, if it is in a CB state, when the process to obtain the point value PV for steps S1507 to S1509 is executed, the carry flag 77 is "0", so the point value PV is "0". If it is in a non-internal two-bet state, when the process to obtain the point value PV for steps S1507 to S1509 is executed, the carry flag 77 is "1", and furthermore, since the process in step S1504 has been executed once before the process in steps S1507 to S1509 is executed, the value of address counter 74l is "1". Therefore, the address data corresponding to the value of address counter 74l is C(0), and the point value PV of "30000" corresponding to that address data is obtained. If the state is a 3-coin bet during non-internal play, the carry flag 77 is "1" when the process to obtain the point value PV in steps S1507 to S1509 is executed. Furthermore, since the process in step S1504 is executed twice before the process in steps S1507 to S1509 is executed, the value of address counter 74l is "2". Therefore, the address data corresponding to the value of address counter 74l is C(1), and the point value PV of "20000" corresponding to that address data is obtained. If the state is a 2-coin bet during internal play, the carry flag 77 is "0" when the process to obtain the point value PV in steps S1507 to S1509 is executed, so the point value PV is "0". If the state is a 3-coin bet during internal play, the carry flag 77 is "0" when the process to obtain the point value PV in steps S1507 to S1509 is executed, so the point value PV is "0".

[0268] As described above, in a configuration where the type of index value IV, which is set to a point value PV of 1 or more depending on the game state, can differ, instead of changing the numerical range of index value IV according to each game state, the index value IV is set to a fixed range, and the type of winning data associated with each index value IV is kept the same, while the type of index value IV, which is set to a point value PV of 1 or more within that fixed range, is changed. This eliminates the need to change the numerical range of index value IV for each game state, or to change the correspondence between index value IV and winning data for each game state, making it possible to simplify the data format.

[0269] Each of the index values ​​IV=1 to 17 is assigned a one-to-one correspondence to data sets 101a to 101q for IV=1 to 17. Each of these data sets 101a to 101q contains data for obtaining the point value PV (including "0") in each game state. This eliminates the need to prepare separate lottery tables for each game state, thus simplifying the data structure.

[0270] A judgment value corresponding to each game state is calculated, and if a bit set to "1" in the game state data 102a to 104a set in each of the data groups 101a to 101q for IV=1 to 17 corresponds to that judgment value, the point value PV corresponding to that bit set to "1" is obtained from the point value data 102c to 104c of the data groups 101a to 101q for IV=1 to 17. This makes it possible to obtain the point value PV corresponding to each game state even if the data groups 101a to 101q for IV=1 to 17 are set to be common to each game state.

[0271] Returning to the explanation of the role lottery process (Figure 34), after the PV acquisition process is executed in step S1305, the lottery value DV used to determine whether a role is correct or not is set (step S1306). In this lottery value setting process, the current lottery value DV is added to the point value PV acquired in step S1305 to set a new lottery value DV. In the initial lottery value setting process, the value of the first random number (one of 0 to 65535) acquired in step S1301 is set as the current lottery value DV, and the point value PV acquired in step S1305 is added to this value of the first random number to set a new lottery value DV. Note that if the point value PV acquired in step S1305 is "0", the lottery value DV will not change even if the process in step S1306 is executed. In other words, if the point value PV is "0" during the initial lottery value setting process, the first random number (one of the values ​​from 0 to 65535) becomes the lottery value DV. If the point value PV is "0" during the second and subsequent lottery value setting processes, the lottery value DV from the previous lottery value setting process becomes the current lottery value DV.

[0272] Subsequently, a determination of whether the hand is correct is made for the index value IV, which corresponds to the current value of the draw counter 74k (step S1307). In determining whether the hand is correct, it is determined whether the draw value DV exceeds "65535". If it exceeds "65535" (step S1307: YES), the process of acquiring the winning data is executed (step S1308). Figure 37 is a flowchart of the process of acquiring the winning data.

[0273] First, the winning data corresponding to the index value IV, which was won this time, is identified by referring to the winning target data 102b to 104b of the data group 101a to 101q corresponding to the current value of the lottery counter 74k in the main RAM 74 (step S1601). If the winning data is CB winning data (step S1602: YES), and the value of the bet number setting counter 74a in the main RAM 74 is "3" (step S1603: YES), the first CB winning data is stored in the main RAM 74 (step S1604). If the value of the bet number setting counter 74a is "2" (step S1603: NO), the second CB winning data is stored in the main RAM 74 (step S1605). If the winning data corresponding to the index value IV, which was won this time, is not CB winning data (step S1602: NO), the winning data identified in step S1601 is stored as is in the main RAM 74 (step S1606).

[0274] Returning to the explanation of the role lottery process (Figure 34), if the lottery value DV does not exceed "65535" (step S1307: NO), it means that the role corresponding to index value IV has not been determined. In this case, the value of the lottery counter 74k in the main RAM 74 is incremented by 1 (step S1309), and then it is determined whether or not there is a role corresponding to index value IV, that is, whether or not there is a selection target to determine whether it is correct or incorrect (step S1310). Specifically, it is determined whether or not the value of the lottery counter 74k, which has been incremented by 1, exceeds the maximum value of "17". If the value of the lottery counter 74k is less than or equal to the maximum value (step S1310: NO), the process returns to step S1305, and the determination of whether or not the role is correct or incorrect is continued. At this point, in step S1305, the data group 101a to 101q corresponding to the value of the lottery counter 74k after the increment is read to obtain the point value PV. In step S1306, the point value PV newly obtained in step S1305 is added to the lottery value DV used to determine whether the hand is correct or incorrect (i.e., the current lottery value DV) to obtain a new lottery value DV. In step S1307, the correctness of the hand is determined based on this lottery value DV.

[0275] If the process in step S1308 is executed, or if a positive result is made in step S1310, it means that the determination of whether the winning combination is correct or not has been completed. In this case, the first stop information setting process is performed to set stop information for reel stop control (step S1311). After that, the first control process for the game section is executed in step S1312, and the advantageous lottery process at the start of the game is executed in step S1313. The contents of these processes from steps S1311 to S1313 will be explained in detail later.

[0276] Subsequently, the stop order notification control process is executed (step S1314). In the stop order notification control process, under the condition that the game state is the pseudo-bonus state ST4 or AT state ST5 described later and the number of bets on the game medium is "3", the display control of the combined display unit 66 is executed so that the stop order of reels 32L, 32M, and 32R that enables the first bell win when index value IV=1 to 6 is announced, and the stop order of reels 32L, 32M, and 32R that enables the second bell win when index value IV=7 to 9 is announced, and a command is sent to the performance-side MPU 92 so that the announcement is executed on the image display device 63.

[0277] Subsequently, the process of sending a game start command is executed (step S1315). In this transmission process, if any winning combination has been won in the current combination lottery process (Figure 34), the information corresponding to the winning combination, the information corresponding to the current game state, and the information corresponding to the processing results of steps S1312 and S1313 are set as the game start command, and this game start command is sent to the performance-side MPU 92. The game start command is a command that makes the performance-side MPU 92 recognize that a new game has started, and is a command that makes the performance-side MPU 92 recognize the various information determined by the main-side MPU 72.

[0278] When the performance-side MPU 92 receives a game start command, it obtains various information about the current game from that command. The performance-side MPU 92 then determines the content of the performance in accordance with the information it has obtained. It then reads a data table corresponding to the determined performance content from the performance-side ROM 93 to the performance-side RAM 94, and executes the illumination control of the upper lamp 61, the sound output control of the speaker 62, and the display control of the image display device 63 according to the data table it has read.

[0279] Next, the reel control process, which is performed in step S909 of the normal process (Figure 25), will be explained with reference to the flowchart in Figure 38.

[0280] First, a rotation start process is performed to begin the rotation of each reel 32L, 32M, and 32R (step S1701). In the rotation start process, it is checked whether a predetermined wait time (specifically 4.1 seconds) has elapsed since the rotation of reels 32L, 32M, and 32R started in the previous game. If it has not elapsed, the system waits until the wait time has elapsed. Once the wait time has elapsed, the wait time for the next game is reset, and rotation start information is set in the motor control storage area provided in the main RAM 74. By performing this process, the stepping motor acceleration process is started in the stepping motor control process of step S504 in the timer interrupt process (Figure 19), and each reel 32L, 32M, and 32R begins to rotate. After that, the system waits until each reel 32L, 32M, and 32R rotates at a predetermined constant speed, and then the rotation start process is terminated. Furthermore, when the rotation speed of each reel 32L, 32M, and 32R reaches a constant speed, the main MPU 72 illuminates the lamps (not shown) of each stop button 42-44 to inform the player that it is possible to issue a stop command.

[0281] Next, it is determined whether or not one of the stop buttons 42-44 has been operated (step S1702). If none of the stop buttons 42-44 have been operated, the process in step S1702 is repeated until one of the stop buttons 42-44 has been operated. If it is determined that one of the stop buttons 42-44 has been operated, it is determined whether or not the stop button 42-44 corresponding to the rotating reel 32L, 32M, or 32R has been operated, i.e., whether or not a stop command has been issued (step S1703). If no stop command has been issued, the process returns to step S1702 and is repeated until one of the stop buttons 42-44 has been operated. If a stop command has been issued, a stop command is sent to the performance-side MPU 92 (step S1704). A stop command is a command that allows the performance-side MPU 92 to recognize which of the stop buttons 42-44 has been operated and whether or not a stop command has been issued. If a stop command is sent, the stop control processing shown in steps S1705 to S1711 is performed to stop the rotating reel.

[0282] In the stop control process, the symbol number of the symbol that has reached the base position (specifically the lower row) at the time the stop buttons 42 to 44 are operated is checked (step S1705). Specifically, the symbol number of the symbol that has reached the base position is checked based on the number of excitation pulses output from the time the detection signal of the reel index sensor is input. Then, based on the stop information stored in the main RAM 74, the slip count of the reels 32L, 32M, and 32R that should be stopped this time is calculated (step S1706).

[0283] In this slot machine 10, there are five stopping patterns for each reel 32L, 32M, and 32R when the stop buttons 42 to 44 are operated: a stopping pattern in which the reel stops as is at the position where it has reached the base position; a stopping pattern in which the corresponding reels 32L, 32M, and 32R are stopped after sliding by one symbol; a stopping pattern in which they are stopped after sliding by two symbol; a stopping pattern in which they are stopped after sliding by three symbol; and a stopping pattern in which they are stopped after sliding by four symbol. In step S1706, a value from "0" to "4" is calculated as the number of slips based on the stop information stored in the main RAM 74.

[0284] Next, the calculated number of slips is added to the symbol number of the reached symbol to determine the symbol number of the stopping symbol to actually stop at the base position (step S1707). Then, it is determined whether the symbol number of the reached symbol and the symbol number of the stopping symbol are equal for the reels 32L, 32M, and 32R that should be stopped this time (step S1708). If they are equal, a reel stop process is performed to stop the rotation of reels 32L, 32M, and 32R (step S1709). After that, it is determined whether all reels 32L, 32M, and 32R have stopped (step S1710). If all reels 32L, 32M, and 32R have not stopped, the second stop information setting process is performed (step S1711), and the process returns to step S1702.

[0285] Here, stop information refers to information that corresponds to the stopping pattern of each reel 32L, 32M, and 32R in accordance with the result of the prize draw process (Figure 34). By using this stop information, it is possible to calculate the number of slips (specifically "0" to "4") for the reached symbol that has reached the base position when each stop button 42 to 44 is stopped. As this stop information, slip number data showing the correspondence between each symbol and the slip number is pre-stored in the main ROM 73 in accordance with each draw result and the stopping order of each reel 32L, 32M, and 32R. However, it is not limited to this, and the slip number data corresponding to each draw result and the stopping order of each reel 32L, 32M, and 32R may be derived while the reels 32L, 32M, and 32R are rotating.

[0286] To set the above stop information, there are two processes: a first stop information setting process executed in step S1311 of the role lottery process (Figure 34), and a second stop information setting process executed in step S1711 of the reel control process (Figure 38). In the first stop information setting process, the stop information is set according to the result of the role lottery process. In the second stop information setting process, the stop information stored in the main RAM 74 in the first stop information setting process or the previous second stop information setting process is changed after some of the reels 32L, 32M, and 32R have stopped. In the second stop information setting process, the stop information is changed based on the set winning data, the stopping order of the reels 32L, 32M, and 32R, and the stopping outcomes of the stopped reels 32L, 32M, and 32R.

[0287] If it is determined in step S1710 that all reels 32L, 32M, and 32R have stopped, the winning determination process is executed in step S1712. In the winning determination process, the type of symbol stopped on the main line ML for each reel 32L, 32M, and 32R is determined. Based on the contents of the winning data stored in the main RAM 74, it is determined whether the combination of symbols stopped and displayed on the main line ML for each reel 32L, 32M, and 32R corresponds to the combination of symbols that won in the winning combination lottery process. If it is the combination of symbols that won, the winning combination is determined to have been won and the winning response process is executed. In the winning response process, if the winning combination is a minor win, the information of the number of game media to be given is set in the main RAM 74 so that game media can be given in the media giving process. On the other hand, if the winning combination is a replay win, a flag setting process is executed so that the re-play setting process is executed in the next start waiting process (Figure 26).

[0288] After executing the award determination process, an award result command is sent to the performance-side MPU92 (step S1713). The award result command includes data indicating whether or not an award was won, and if an award was won, it also includes data indicating the type of award.

[0289] Next, we will explain the processing that is performed at the end of the game, which is executed in step S912 of the normal processing (Figure 25), with reference to the flowchart in Figure 39. Note that the processing in step S912 of the normal processing (Figure 25) is executed after the reel control processing (step S909), so the processing that is performed at the end of the game is executed after the rotation of reels 32L, 32M, and 32R has all stopped in one game.

[0290] First, CB processing is executed to control the transition and progress between the first CB state ST2 and the second CB state ST3 (step S1801). In the CB processing, if the first CB win is achieved, the first CB state flag in the main RAM 74 is set to "1", and the first CB win data stored in the first CB win data area of ​​the main RAM 74 is cleared. Then, a first CB win command indicating a transition to the first CB state ST2 is sent to the performance side MPU 92. As a result, the game state becomes the first CB state ST2. In the first CB state ST2, as already explained, the game will only be executed when the game medium "3" is bet. In the CB processing, if the second CB win is achieved, the second CB state flag in the main RAM 74 is set to "1", and the second CB win data stored in the second CB win data area of ​​the main RAM 74 is cleared. Then, a command indicating a 2nd CB win is sent to the MPU92 on the production side, indicating that the game has transitioned to the 2nd CB state ST3. As a result, the game state becomes the 2nd CB state ST3. In the 2nd CB state ST3, as already explained, the game will only be played when the game medium "2" is bet.

[0291] In the CB processing, if the current game state is a CB state (1st CB state ST2 or 2nd CB state ST3), and if the first bell win has occurred in this game, the value of the total award counter set in the main RAM 74 is incremented by 1. The total award counter is a counter used by the main MPU 72 to determine the total number of game media awarded in the CB state, and is cleared to "0" when the CB state starts. If the value of the total award counter after incrementing by 1 reaches "30", which is the threshold for ending the CB state, the CB state flag corresponding to the current CB state is cleared to "0". Then, a CB end command indicating that the current CB state has ended is sent to the performance side MPU 92.

[0292] If the game is not in CB state (Step S1802: NO), the game jumps to the process corresponding to the current game state (Step S1803). Specifically, if the game state is normal game state ST1, the normal process is executed (Step S1804); if the game state is pseudo-bonus state ST4, the pseudo-bonus process is executed (Step S1805); if the game state is AT state ST5, the AT process is executed (Step S1806); and if the game state is end preparation state ST6, the second control process for the game section is executed (Step S1807). In addition, if any of the normal process in Step S1804, the pseudo-bonus process in Step S1805, or the AT process in Step S1806 is executed, the second control process for the game section (Step S1807) is also executed. Furthermore, if the game is in CB state, the second control process for the game section (Step S1807) is also executed. The processing contents of Steps S1804 to S1807 will be explained in detail later.

[0293] If the current game state is CB state, a positive determination is made in step S1802, and the normal processing in step S1804, the pseudo-bonus processing in step S1805, and the AT processing in step S1806 are not executed. Therefore, if the game is in CB state, the processing to advance the normal game state ST1, the processing to advance the pseudo-bonus state ST4, and the processing to advance the AT state ST5 are not executed. On the other hand, even if the current game state is CB state, the second control processing of the game section in step S1807 is executed. Therefore, even if the game is in CB state, the processing to advance the second section SC2 is executed.

[0294] <Regarding game status and game section> Next, the game state and game interval will be explained. Figure 40 is an explanatory diagram illustrating the game state and game interval present in this slot machine 10.

[0295] In this slot machine 10, there are four game states: normal game state ST1, first CB state ST2, second CB state ST3, pseudo bonus state ST4, AT state ST5, and end preparation state ST6. These game states ST1 to ST6 do not occur simultaneously with each other.

[0296] The normal game state ST1 is the game state reached when the clearing process of the main RAM 74 (steps S301 to S307) is executed. Furthermore, when the first CB state ST2 or the second CB state ST3 that occurred in the normal game state ST1 ends, or when the termination preparation state ST6 ends, the game state returns to the normal game state ST1. In the normal game state ST1, it is possible to play one game regardless of whether the number of bets on the game medium is "3" or "2".

[0297] In the normal game state ST1, regardless of whether 3 coins are bet or 2 coins bet, the expected net increase in game currency per game (the value obtained by subtracting the number of game currency bets per game from the expected number of game currency bets per game) is less than 1. Furthermore, in the normal game state ST1, there are two states: a non-internal state in which neither the 1st CB winning data nor the 2nd CB winning data is stored in the main RAM 74, and an internal state in which either the 1st CB winning data or the 2nd CB winning data is stored in the main RAM 74.

[0298] The first CB state ST2 is a game state that is entered when a first CB win is achieved while the first CB win data is stored in the first CB win data area of ​​the main RAM 74. In the first CB state ST2, it is possible to play one game if the number of bets on the game medium is "3", but it is not possible to play one game if the number of bets on the game medium is "2". The second CB state ST3 is a game state that is entered when a second CB win is achieved while the second CB win data is stored in the second CB win data area of ​​the main RAM 74. In the second CB state ST3, it is possible to play one game if the number of bets on the game medium is "2", but it is not possible to bet "3" game mediums because the bet limit is set to "2".

[0299] The first CB state ST2 and the second CB state ST3 are game states in which the number of game tokens owned by the player does not increase. More specifically, both the first CB state ST2 and the second CB state ST3 are game states in which the number of game tokens owned by the player at the end of the game state is less than the number of game tokens owned by the player at the start of the game state.

[0300] The pseudo-bonus state ST4 is a game state that is entered when the conditions for transitioning to the pseudo-bonus state ST4 are met in the normal game state ST1. The pseudo-bonus state ST4 ends when the remaining number of games in the pseudo-bonus state ST4 becomes "0" or when the ending conditions of the second section SC2 are met. If the pseudo-bonus state ST4 ends without the ending conditions of the second section SC2 (described later) being met, and the conditions for transitioning to the AT state ST5 are not met, the game transitions to the termination preparation state ST6. Also, if the pseudo-bonus state ST4 ends due to the fulfillment of the ending conditions of the second section SC2 (described later), the game transitions to the normal game state ST1.

[0301] In the pseudo-bonus state ST4, it is possible to play one game regardless of whether the number of bets on the game medium is "3" or "2". In the pseudo-bonus state ST4, there is a non-internal state in which neither the 1st CB winning data nor the 2nd CB winning data is stored in the main RAM 74, and an internal state in which either the 1st CB winning data or the 2nd CB winning data is stored in the main RAM 74.

[0302] In the pseudo-bonus state ST4, if an index value IV=1 to 6 is won, and the number of bets on the game medium is "3", the stopping order of reels 32L, 32M, and 32R that enables the first bell win will be announced. Also, in the pseudo-bonus state ST4, if an index value IV=7 to 9 is won, and the number of bets on the game medium is "3", the stopping order of reels 32L, 32M, and 32R that enables the second bell win will be announced. If the first or second bell win is achieved, "15" game mediums will be awarded. This makes it possible to increase the expected number of game mediums awarded in one game in the pseudo-bonus state ST4. When betting 3 coins in the pseudo-bonus state ST4, the expected net increase in game mediums in one game will be 1 or more, while when betting 2 coins in the pseudo-bonus state ST4, the expected net increase in game mediums in one game will be less than 1.

[0303] AT state ST5 is a game state that is entered when the conditions for transitioning to AT state ST5 are met in pseudo-bonus state ST4. AT state ST5 ends when the remaining number of games in AT state ST5 becomes "0" or when the ending conditions of the second section SC2 are met. If AT state ST5 ends without the ending conditions of the second section SC2 described later being met, the game transitions to the end preparation state ST6. Also, if AT state ST5 ends because the ending conditions of the second section SC2 described later are met, the game transitions to the normal game state ST1.

[0304] In AT state ST5, it is possible to execute one game regardless of whether the number of bets on the game medium is "3" or "2". In AT state ST5, there are two states: a non-internal state in which neither the 1st CB winning data nor the 2nd CB winning data is stored in the main RAM 74, and an internal state in which either the 1st CB winning data or the 2nd CB winning data is stored in the main RAM 74.

[0305] In AT state ST5, if the index value IV=1 to 6 is won, and the number of bets on the game medium is "3", the stopping order of reels 32L, 32M, and 32R that enables the first bell win will be announced. Also, in AT state ST5, if the index value IV=7 to 9 is won, and the number of bets on the game medium is "3", the stopping order of reels 32L, 32M, and 32R that enables the second bell win will be announced. If the first or second bell win is achieved, "15" game mediums will be awarded. This makes it possible to increase the expected number of game mediums awarded in one game in AT state ST5. In AT state ST5, if 3 coins are bet, the expected net increase in game mediums in one game will be 1 or more, and in AT state ST5, if 2 coins are bet, the expected net increase in game mediums in one game will be less than 1.

[0306] The termination preparation state ST6 is a game state that is entered when the pseudo-bonus state ST4 ends without the ending conditions of the second section SC2 (described later) being met and without the conditions for transitioning to the AT state ST5 being met. Also, the termination preparation state ST6 is a game state that is entered when the AT state ST5 ends without the ending conditions of the second section SC2 (described later) being met.

[0307] The termination preparation state ST6 ends when one game is played. When the termination preparation state ST6 ends, the game transitions to the normal game state ST1. In the termination preparation state ST6, one game can be played regardless of whether the number of bets on the game medium is "3" or "2". In the termination preparation state ST6, regardless of whether the bet is 3 or 2, the expected net increase in the game medium in one game is less than 1. Furthermore, the termination preparation state ST6 has a non-internal state in which neither the 1st CB winning data nor the 2nd CB winning data is stored in the main RAM 74, and an internal state in which either the 1st CB winning data or the 2nd CB winning data is stored in the main RAM 74.

[0308] In this configuration, where various game states ST1 to ST6 exist as described above, game intervals are set separately from these game states ST1 to ST6. The game intervals are set as the first interval SC1 and the second interval SC2. In other words, in this slot machine 10, the elements that determine the game state are the number of bets for the game media "2" and "3", the setting values ​​"1" to "6", the various game states ST1 to ST6, and the game intervals of the first interval SC1 and the second interval SC2.

[0309] Section 1 SC1 is a section in which an advantageous game state (pseudo-bonus state ST4 and AT state ST5) is not started, and in which the player is notified of the stopping order of reels 32L, 32M, and 32R, which allows for advantageous wins when different winning combinations are achieved depending on the stopping order of reels 32L, 32M, and 32R, resulting in a net expected increase in game currency per game (the value obtained by subtracting the number of game currency bets per game from the expected number of game currency given per game) being 1 or more, and in which the above advantageous game state is not continued. If the clearing process of the main RAM 74 (steps S301 to S307) is executed, it becomes the normal game state ST1 and Section 1 SC1. Also, if the initialization process of Section 2 SC2 is executed in Section 2 SC2, it becomes Section 1 SC1. Section 2 SC2 is a section in which the above advantageous game state can be started and can be continued.

[0310] Figure 41(a) is an explanatory diagram for illustrating the first section SC1 and the second section SC2. As described above, the first section SC1 is established when the clearing process of the main RAM 74 (steps S301 to S307) is executed, and the first section SC1 is established when the initialization process of the second section SC2 is executed. On the other hand, the second section SC2 is entered when a trigger for transitioning to the second section SC2 occurs in the first section SC1 based on the lottery process for winning combinations (Figure 34). In this case, if a game with a bet of "3" is played in the first section SC1, a trigger for transitioning to the second section SC2 may occur, while if a game with a bet of "2" is played in the first section SC1, a trigger for transitioning to the second section SC2 will not occur. Therefore, players who expect to transition to the second section SC2 in the first section SC1 need to play a game with a bet of "3", rather than a game with a bet of "2".

[0311] In the first section SC1, the expected net increase in game currency per game is always less than 1, whereas in the second section SC2, the expected net increase in game currency per game may be less than 1, or it may be 1 or more. Therefore, the second section SC2 is a more favorable situation than the first section SC1. Thus, players will expect to transition to the second section SC2 while in the first section SC1.

[0312] Section 1 SC1 ends when a trigger for transitioning to Section 2 SC2 occurs, and the game transitions to Section 2 SC2. In contrast, Section 2 SC2 ends when the pseudo-bonus state ST4, AT state ST5, or termination preparation state ST6 ends and the game transitions to the normal game state ST1. When Section 2 SC2 ends, the game transitions to Section 1 SC1. Furthermore, there are ending conditions for Section 2 SC2, which are that either the total number of games played by Section 2 SC2 continuing without a transition to Section 1 SC1 reaching the upper limit of games (specifically 1500 games), or the total net increase in game tokens with restrictions reaching the upper limit of net increase in tokens (specifically 2400 tokens) by Section 2 SC2 continuing without a transition to Section 1 SC1 reaching the upper limit of net increase in tokens. The limited total net increase in gaming media refers to the number of coins added to the predetermined net increase from a predetermined standard value, where the predetermined net increase is calculated by subtracting the total number of gaming media used to play games while SC2 is ongoing (0 if no games are played) from the total number of gaming media awarded by games played while SC2 is ongoing (0 if no gaming media are awarded).

[0313] In other words, if the second section SC2 continues and the total net increase in game tokens with restrictions from the start of the second section SC2 reaches the maximum net increase, the second section SC2 will end and the game will transition to the first section SC1. Also, if the second section SC2 continues and the number of games played from the start of the second section SC2 reaches the maximum number of games, the second section SC2 will end and the game will transition to the first section SC1. When either of these ending conditions is met, even if the pseudo-bonus state ST4 or AT state ST5 is still in progress, the pseudo-bonus state ST4 or AT state ST5 will end in the game in which the ending condition is met, and the second section SC2 will also end, transitioning to the first section SC1, which is the normal game state ST1. This makes it possible to prevent the second section SC2 from continuing excessively.

[0314] As shown in Figure 40, the normal game state ST1, the first CB state ST2, and the second CB state ST3 can occur in either the first section SC1 or the second section SC2. On the other hand, the pseudo-bonus state ST4, the AT state ST5, and the termination preparation state ST6 can never occur in the first section SC1, but only in the second section SC2.

[0315] Figure 41(b) is an explanatory diagram for explaining the contents of each game state ST1 to ST6 in the second section SC2. As already explained, in the normal game state ST1, pseudo-bonus state ST4, AT state ST5, and end preparation state ST6, the game can be played whether the number of bets on the game medium is "3" or "2". In the first CB state ST2, the game can only be played when the number of bets on the game medium is "3", and in the second CB state ST3, the game can only be played when the number of bets on the game medium is "2".

[0316] In the second section SC2, when the game is in the normal game state ST1, the expected net increase in game tokens is less than 1 regardless of whether a game with a bet of "3" or a game with a bet of "2" is played. In this case, in the normal game state ST1 of the second section SC2, as described later, a lottery process for transitioning to the pseudo-bonus state ST4 may be executed based on the result of the role lottery process (Figure 34) in each game. However, this transition lottery process is executed in games with a bet of "3" but not in games with a bet of "2". Furthermore, in the normal game state ST1 of the second section SC2, as described later, the value of the release game counter provided in the main RAM 74 is decremented by 1 each time a game is played. If the value of the release game counter after this decrement is "0", the transition to the pseudo-bonus state ST4 is confirmed. However, this decrement of the release game counter is executed in games with a bet of "3" but not in games with a bet of "2". Therefore, in the normal game state ST1 of the second section SC2, it is more advantageous for the player to have a game with a bet of "3" played than to have a game with a bet of "2".

[0317] In the pseudo-bonus state ST4, if a game with a bet of "3" is played, the expected net increase in game currency can be 1 or more, whereas if a game with a bet of "2" is played, the expected net increase in game currency is less than 1. Therefore, in the pseudo-bonus state ST4, it is more advantageous for the player to play a game with a bet of "3" than to play a game with a bet of "2". In the pseudo-bonus state ST4, as will be described later, a lottery process for transitioning to AT state ST5 may be performed based on the result of the role lottery process in each game (Figure 34), but this transition lottery process is performed in games with a bet of "3" and not in games with a bet of "2". Therefore, from this point of view as well, in the pseudo-bonus state ST4, it is more advantageous for the player to play a game with a bet of "3" than to play a game with a bet of "2".

[0318] When the AT state is ST5, if a game with a bet of "3" is played, the expected net increase in game currency can be 1 or more, whereas if a game with a bet of "2" is played, the expected net increase in game currency is less than 1. Therefore, when the AT state is ST5, it is more advantageous for the player to play a game with a bet of "3" than to play a game with a bet of "2". In the AT state ST5, as will be described later, based on the result of the role lottery process in each game (Figure 34), an additional lottery process to determine whether or not to increase the remaining number of sets in the AT state ST5, and a transition lottery process to an additional period in which the remaining number of sets in the AT state ST5 is more likely to increase may be performed. However, these additional lottery processes and transition lottery processes are performed in games with a bet of "3", but not in games with a bet of "2". Therefore, from this point of view as well, when the AT state is ST5, it is more advantageous for the player to play a game with a bet of "3" than to play a game with a bet of "2".

[0319] As described above, even if the configuration is such that games with a bet of "3" are played in the normal game state ST1, pseudo-bonus state ST4, and AT state ST5 of the second section SC2, the number of game tokens awarded in games with a bet of "2" in any of the normal game state ST1, pseudo-bonus state ST4, and AT state ST5 of the second section SC2 is added to the limited total net increase in game tokens in the second section SC2, and games with a bet of "2" in any of the normal game state ST1, pseudo-bonus state ST4, and AT state ST5 of the second section SC2 are added to the total number of games played as a result of the continuation of the second section SC2. In other words, even though games with a bet of "2" in any of the normal game state ST1, pseudo-bonus state ST4, and AT state ST5 of the second section SC2 are disadvantageous to the player, these games end up contributing to fulfilling the ending conditions of the second section SC2. From this perspective, in the second section SC2, if the game is in the normal game state ST1, the pseudo-bonus state ST4, or the AT state ST5, it is more advantageous for the player to have a game with a bet of "3" executed than to have a game with a bet of "2" executed.

[0320] Even in the second section SC2, just like in the first section SC1, it is possible to win the first CB and also win the second CB. If the first CB is won in the second section SC2, the second section SC2 enters the first CB state ST2, and the second section SC2 is maintained even when the first CB state ST2 is in place and after the first CB state ST2 ends. Also, if the second CB is won in the second section SC2, the second section SC2 enters the second CB state ST3, and the second section SC2 is maintained even when the second CB state ST3 is in place and after the second CB state ST3 ends. As already explained, both the first CB state ST2 and the second CB state ST3 are game states in which the number of game media owned by the player at the end of the game state is less than the number of game media owned by the player at the start of the game state. In other words, the first CB state ST2 and the second CB state ST3 are game states that are disadvantageous to the player. On the other hand, games played in either the first CB state ST2 or the second CB state ST3 in the second section SC2 are added to the total number of games played as the second section SC2 continues. In other words, even though games played in the first CB state ST2 and the second CB state ST3 are disadvantageous to the player, these games contribute to fulfilling the ending conditions of the second section SC2. Therefore, if the first CB state ST2 or the second CB state ST3 occurs in the second section SC2, it becomes more disadvantageous for the player.

[0321] Note that, although the net expected value of the game medium is less than 1 when the game with the bet number of "3" or the game with the bet number of "2" is executed in the second section SC2 in the end preparation state ST6, the second section SC2 ends as the pseudo bonus state ST4 or the AT state ST5 ends, and it is a game state in which only one game is executed. Therefore, the game executed in the end preparation state ST6 does not contribute to the restricted total net increase number of the game medium in the second section SC2, and furthermore, it does not contribute to the total number of games in the second section SC2. However, it is not limited to this, and even the game executed in the end preparation state ST6 may be configured to contribute to the restricted total net increase number of the game medium in the second section SC2 and further contribute to the total number of games in the second section SC2.

[0322] <Regarding the CB states ST2 and ST3> Next, the first CB state ST2 and the second CB state ST3 will be described in detail. FIG. 42(a) is an explanatory diagram for explaining the first CB role (that is, the index value IV in which the first CB winning data is to be stored in the main side RAM 74) and the second CB role (that is, the index value IV in which the second CB winning data is to be stored in the main side RAM 74), and FIG. 42(b) is an explanatory diagram for explaining the first CB state ST2 and the second CB state ST3.

[0323] As shown in FIG. 42(a), the first CB role can be won in the game with the bet number of "3", but cannot be won in the game with the bet number of "2". The first CB role is won with a probability of about 1 / 3.3 in the game with the bet number of "3". However, when it is in any of the winning state of the first CB role (that is, the state in which the first CB winning data is stored in the main side RAM 74), the winning state of the second CB role (that is, the state in which the second CB winning data is stored in the main side RAM 74), the first CB state ST2, and the second CB state ST3, the first CB role is excluded from the lottery target in the lottery process of the role (FIG. 34).

[0324] The 2nd CB role can be won in games where the bet is "2", but not in games where the bet is "3". In games where the bet is "2", the 2nd CB role is won with a probability of approximately 1 / 2.2. However, if the 1st CB role is won (i.e., the 1st CB winning data is stored in the main RAM 74), the 2nd CB role is won (i.e., the 2nd CB winning data is stored in the main RAM 74), or if the 1st CB state ST2 or 2nd CB state ST3 is active, the 2nd CB role is excluded from the draw in the role draw process (Figure 34).

[0325] In the state where the 1st CB role is won, the 1st CB can be won in games with a bet of "3", but not in games with a bet of "2". Therefore, even if a game with a bet of "2" is played in the state where the 1st CB role is won and the role lottery process (Figure 34) results in a loss where none of the index values ​​IV are won, the 1st CB will not be won regardless of the stopping order of reels 32L, 32M, 32R and the stopping timing of stop buttons 42-44. Also, even if a game with a bet of "2" is played in the state where the 1st CB role is won and the role lottery process (Figure 34) results in an index value IV, which can result in a so-called miss, the 1st CB will not be won regardless of the stopping order of reels 32L, 32M, 32R and the stopping timing of stop buttons 42-44. When a game with a bet of "3" is played in the state where the 1st CB role is won and the 1st CB is won, the state becomes 1st CB state ST2.

[0326] As shown in Figure 42(b), in the first CB state ST2, it is possible to play a game with a bet of "3", but it is not possible to play a game when the bet is 2 or less. In the first CB state ST2, in the lottery process for the winning combination in each game (Figure 34), there is a 3 / 10 probability that normal replay winning data will be stored in the main RAM 74. If normal replay winning data is stored, a normal replay will be awarded regardless of the stopping order of reels 32L, 32M, and 32R, as long as the left stop button 42 is operated at the predetermined timing. If the left stop button 42 is not operated at the predetermined timing, a normal replay will not be awarded even if normal replay winning data is stored.

[0327] In the first CB state ST2, if the normal replay winning data is not stored in the main RAM 74 during the role lottery process (Figure 34), or if the normal replay winning data is stored in the main RAM 74 but the timing of the left stop button 42 operation is not at the predetermined timing and a normal replay win cannot be achieved, a first bell win may be achieved. In this case, a first bell win will be achieved regardless of the stopping order of reels 32L, 32M, and 32R, but a first bell win may not be achieved depending on the stopping timing of the left stop button 42.

[0328] However, the configuration is not limited to this, and if normal replay winning data is stored in the main RAM 74 during the role lottery process (Figure 34) in the first CB state ST2, the configuration may be such that a normal replay is reliably achieved regardless of the stopping order of reels 32L, 32M, and 32R and the stopping timing of each stop button 42 to 44. Also, if normal replay winning data is not stored in the main RAM 74 during the role lottery process (Figure 34) in the first CB state ST2, the configuration may be such that a first bell is reliably achieved regardless of the stopping order of reels 32L, 32M, and 32R and the stopping timing of each stop button 42 to 44.

[0329] In the first CB state ST2, if the first bell is won, "1" game token is awarded. As already explained, in the first CB state ST2, the game can only be played if "3" game tokens are bet. In contrast, the number of game tokens awarded in a game in the first CB state ST2 is "1". The first CB state ST2 ends when "30" game tokens have been awarded. Therefore, in the first CB state ST2, the event of "1" game token being awarded in a game played by betting "3" game tokens must occur 30 times. In this case, the number of game tokens the player possesses will decrease by at least 60 from the start to the end of the first CB state ST2. Thus, the first CB state ST2 is a disadvantageous game state for the player.

[0330] Furthermore, in the first CB state ST2, as described above, it is possible for a normal replay to occur, and it is also possible for neither a normal replay nor a first bell to occur. In that case, if the first CB state ST2 occurs in the second section SC2, the first CB state ST2, which is disadvantageous to the player, will continue for 30 games or more, and that number of games will be added to the total number of games played in the second section SC2.

[0331] In the state where the 2nd CB role is won, a 2nd CB win can occur in games with a bet of "2", but not in games with a bet of "3". Therefore, even if a game with a bet of "3" is played in the state where the 2nd CB role is won and the role lottery process (Figure 34) results in a loss where none of the index values ​​IV are won, the 2nd CB win will not occur regardless of the stopping order of reels 32L, 32M, 32R and the stopping timing of stop buttons 42-44. Also, even if a game with a bet of "3" is played in the state where the 2nd CB role is won and the role lottery process (Figure 34) results in a win of index value IV, where a so-called miss can occur, the 2nd CB win will not occur regardless of the stopping order of reels 32L, 32M, 32R and the stopping timing of stop buttons 42-44. When a game with a bet of "2" is played in the state where the 2nd CB role is won and a 2nd CB win occurs, the state becomes 2nd CB state ST3.

[0332] As shown in Figure 42(b), in the second CB state ST3, it is possible to play the game with a bet of "2", and the maximum bet for the game medium is also "2". In the second CB state ST3, in the lottery process for winning a role in each game (Figure 34), there is a 3 / 10 probability that normal replay winning data will be stored in the main RAM 74. If normal replay winning data is stored, a normal replay will be awarded regardless of the stopping order of reels 32L, 32M, and 32R, as long as the left stop button 42 is operated at the predetermined timing. If the left stop button 42 is not operated at the predetermined timing, a normal replay will not be awarded even if normal replay winning data is stored.

[0333] In the second CB state ST3, if the normal replay winning data is not stored in the main RAM 74 during the role lottery process (Figure 34), or if the normal replay winning data is stored in the main RAM 74 but the timing of the left stop button 42 operation is not at the predetermined timing and a normal replay win cannot be achieved, a first bell win may be achieved. In this case, a first bell win will be achieved regardless of the stopping order of reels 32L, 32M, and 32R, but a first bell win may not be achieved depending on the stopping timing of the left stop button 42.

[0334] However, the configuration is not limited to this, and if normal replay winning data is stored in the main RAM 74 during the role lottery process (Figure 34) in the second CB state ST3, the configuration may be such that a normal replay is reliably achieved regardless of the stopping order of reels 32L, 32M, and 32R and the stopping timing of each stop button 42 to 44. Also, if normal replay winning data is not stored in the main RAM 74 during the role lottery process (Figure 34) in the second CB state ST3, the configuration may be such that a first bell is reliably achieved regardless of the stopping order of reels 32L, 32M, and 32R and the stopping timing of each stop button 42 to 44.

[0335] In the 2nd CB state ST3, if the first bell is won, "1" game token is awarded. As already explained, in the 2nd CB state ST3, the game can only be played if "2" game tokens are bet. In contrast, the number of game tokens awarded in the game in the 2nd CB state ST3 is "1". The 2nd CB state ST3 ends when "30" game tokens have been awarded. Therefore, in the 2nd CB state ST3, the event of "1" game token being awarded in a game played by betting "2" game tokens must occur 30 times. In this case, the number of game tokens the player possesses will decrease by at least 30 from the start to the end of the 2nd CB state ST3. Thus, the 2nd CB state ST3 is a disadvantageous game state for the player. However, the degree of disadvantage in the 2nd CB state ST3 is lower than in the 1st CB state ST2.

[0336] Furthermore, in the second CB state ST3, as described above, it is possible for a normal replay to occur, and it is also possible for neither a normal replay nor a first bell to occur. In that case, if the second CB state ST3 occurs in the second section SC2, the second CB state ST3, which is disadvantageous to the player, will continue for 30 games or more, and that number of games will be added to the total number of games played in the second section SC2.

[0337] As described above, in a configuration where the 1st CB state ST2 and 2nd CB state ST3 are set as unfavorable game states for the player, by playing a game with a bet of "2", the player enters a state where the 2nd CB role is won, but the 2nd CB win is not achieved. Then, by playing a game with a bet of "3", it becomes possible to play without transitioning to the 1st CB state ST2 or 2nd CB state ST3, regardless of the stopping order of reels 32L, 32M, 32R and the stopping timing of each stop button 42-44, as a result of the role lottery process (Figure 34) in each game. In other words, if the player enters a state where the 2nd CB role is won by playing a game with a bet of "2", then playing a game with a bet of "3" will prevent the 2nd CB win from being achieved, even if the player enters a state where the 2nd CB role is won. Also, in the state where the 2nd CB role is won, even if a game with a bet of "3" is played, the 1st CB role is excluded from the lottery in the role lottery process (Figure 34), so the player does not enter a state where the 1st CB role is won. Furthermore, because the state of winning the 1st CB role is not achieved, the 1st CB win is not established, and the game state does not transition to the 1st CB state ST2. This makes it possible to play a game with a bet of "3" while preventing transitions to the 1st CB state ST2 and the 2nd CB state ST3. And by playing a game with a bet of "3", as explained earlier, a transition to the 2nd section SC2 may occur, as well as a transition to the pseudo-bonus state ST4.

[0338] As shown in Figure 42(a), the probability of winning the 2nd CB prize in a game with a bet of "2" is approximately 1 / 2.2, while the probability of winning the 1st CB prize in a game with a bet of "3" is approximately 1 / 3.3. In other words, the probability of winning the 2nd CB prize is set higher than the probability of winning the 1st CB prize. This makes it possible to reduce the number of games required to reach the state of winning the 2nd CB prize when playing a game with a bet of "2" in a gaming hall, etc. On the other hand, even if a game with a bet of "3" is played by mistake before reaching the state of winning the 2nd CB prize, the probability of winning the 1st CB prize is lower than the probability of winning the 2nd CB prize, making it difficult to win the 1st CB prize.

[0339] Furthermore, the configuration is not limited to one in which the probability of winning the second CB role is higher than the probability of winning the first CB role; it may also be a configuration in which the probability of winning the first CB role is higher than the probability of winning the second CB role, or a configuration in which the probability of winning the first CB role and the probability of winning the second CB role are the same or approximately the same.

[0340] <Regarding Section 2, SC2> Next, we will explain the second section SC2. First, we will explain the first control processing of the game section, which is executed by the main MPU72, referring to the flowchart in Figure 43. The first control processing of the game section is executed in step S1312, which is after the determination of whether a winning combination is achieved in the combination lottery process (Figure 34) and before the advantageous lottery process at the start of the game (step S1313).

[0341] First, it is determined whether the second section flag in the main RAM 74 is set to "1" (step S1901). The second section flag is used by the main MPU 72 to determine whether the game section is the second section SC2. If the second section flag is set to "1", it is the second section SC2, and if the value of the second section flag is "0", it is the first section SC1. If the second section flag is set to "1" (step S1901: YES), the processing from step S1902 onwards is not executed. As a result, if it is the second section SC2, the lottery process for the number of games to be released in step S1906 is not executed.

[0342] If the second section flag is not set to "1" (step S1901: NO), it is determined whether the current game state is the first CB state ST2 or the second CB state ST3 (step S1902). If the current game state is the first CB state ST2 or the second CB state ST3 (step S1902: YES), the processes from step S1903 onwards are not executed. As a result, even if the first section is SC1, if the state is the first CB state ST2 or the second CB state ST3, the process to set the second section to SC2 in step S1905 and the lottery process for the number of release games in step S1906 are not executed.

[0343] If the current game state is neither the first CB state ST2 nor the second CB state ST3 (step S1902: NO), the system determines whether the number of bets for the current game is "3" by checking whether the value of the bet count setting counter 74a in the main RAM 74 is "3" (step S1903). If the number of bets for the current game is "2" (step S1903: NO), the processes from step S1904 onwards are not executed. As a result, even if it is the first section SC1, in games where the number of bets is "2", the process to set the second section SC2 in step S1905 and the lottery process for the number of games to be released in step S1906 are not executed.

[0344] If the number of bets for this game is "3" (Step S1903: YES), it is determined whether or not an index value IV was won in the current hand lottery process (Figure 34) (Step S1904). If the current hand lottery process (Figure 34) is a loss (Step S1904: NO), the processes from Step S1905 onwards are not executed. As a result, even if it is the first section SC1, if the hand lottery process (Figure 34) is a loss, the process to set the second section SC2 in Step S1905 and the lottery process for the number of release games in Step S1906 are not executed.

[0345] If any index value IV is selected in the current role lottery process (Figure 34) (Step S1904: YES), the second section flag of the main RAM 74 is set to "1", and the continuation game counter 74c (see Figure 9) and the total acquired counter 74d (see Figure 9) provided in the main RAM 74 are both cleared to "0" (Step S1905). Setting the second section flag to "1" makes it the second section SC2.

[0346] The continuous game count counter 74c is a counter used by the main MPU 72 to determine the number of games played since the start of the second section SC2 when the second section SC2 continues without an intervening first section SC1. If the value of the continuous game count counter 74c in the second section SC2 reaches the value corresponding to the upper limit of games (specifically 1500 games), even if it is in the middle of the pseudo-bonus state ST4 or AT state ST5, the second section SC2 will end at the game in which the value was reached, and the situation will transition to the first section SC1, which is the normal game state ST1.

[0347] The total acquisition counter 74d is a counter used by the main MPU 72 to determine the limited total net increase in game tokens from the start of the second section SC2 when the second section SC2 continues without the first section SC1 being in between. The limited total net increase in game tokens is, as already explained, the value obtained by subtracting the total number of game tokens consumed to play a game while the second section SC2 is continuing (0 if no game is being played) from the total number of game tokens granted by games played while the second section SC2 is continuing (0 if no game tokens are being granted) is set as a predetermined difference in tokens, and the minimum value of this predetermined difference in tokens is set as a predetermined standard value, and the net increase in the predetermined difference in tokens is the number of tokens from the predetermined standard value. In the second section SC2, if the total acquired count counter 74d reaches the value corresponding to the upper limit of net increase in coins (specifically 2400 coins), even if it is in the middle of the pseudo-bonus state ST4 or AT state ST5, the second section SC2 will end in the game in which the value was reached, and the game will transition to the first section SC1, which is the normal game state ST1.

[0348] Subsequently, a lottery process for determining the number of games to be released is performed (step S1906). The number of games to be released is a counter used by the main MPU 72 to determine the number of games required for a transition to the pseudo-bonus state ST4 to occur if the transition to the pseudo-bonus state ST4 is not won. In the lottery process for determining the number of games to be released, first, a lottery table for the number of games to be released, which is pre-stored in the main ROM 73, is read, and numerical information is obtained from a lottery counter that is periodically updated in the main RAM 74. Then, the number of games to be released is selected by comparing the numerical information obtained from the lottery counter with the lottery table for the number of games to be released. In this case, one of the following will be selected as the number of games to be released: 50 games, 100 games, 200 games, 300 games, 400 games, 500 games, 600 games, 700 games, and 800 games. The probability of selecting each of these number of games to be released is the same. However, this is not limited to this, and a configuration in which the probability of selecting a larger number of games to be released is set to be higher may be used, or a configuration in which the probability of selecting a smaller number of games to be released is set to be higher may be used. After executing the lottery process for the number of unlocked games, the number of unlocked games selected in that lottery process is set to the unlocked game counter provided in the main RAM 74 (step S1907). The unlocked game counter is a counter used by the main MPU 72 to identify the remaining number of unlocked games.

[0349] Subsequently, the section display unit 67 lighting lottery process is executed (step S1908). In the section display unit 67 lighting lottery process, a lighting lottery table provided in the main ROM 73 and a lottery counter that is periodically updated in the main RAM 74 are used to determine by lottery whether the section display unit 67 will be lit from the beginning when setting the second section SC2 (i.e., immediately lit), or whether the section display unit 67 will be lit when transitioning to the pseudo-bonus state ST4 (i.e., waiting to be lit). In the lottery process for the roles in this game (Figure 34), if the index value IV = any of 1 to 10 is selected, there is a 50% chance of immediate illumination and a 50% chance of waiting for illumination; if the index value IV = 11 is selected, there is a 65% chance of immediate illumination and a 35% chance of waiting for illumination; if the index value IV = 12 is selected, there is a 62% chance of immediate illumination and a 38% chance of waiting for illumination; and if the index value IV = 13 is selected, there is an 80% chance of immediate illumination and a 20 If the player selects "wait to light up" with a certain probability, and the index value IV=14 is selected, there is a 75% chance of immediate lighting and a 25% chance of waiting to light up. If the player selects IV=15, there is a 70% chance of immediate lighting and a 30% chance of waiting to light up. If the player selects IV=16, there is a 40% chance of immediate lighting and a 60% chance of waiting to light up. If the player selects IV=17, there is a 30% chance of immediate lighting and a 70% chance of waiting to light up. In this case, the lower the probability of winning an index value IV in the draw process (Figure 34), the higher the probability of immediate lighting being selected.

[0350] If immediate illumination is selected in the illumination lottery process for the section display unit 67 (step S1908) (step S1909: YES), the illumination process for the section display unit 67 is executed (step S1910). In the illumination process for the section display unit 67, the section display unit 67 is switched from the off state to the on state. As a result, the section display unit 67 begins to notify that it is the second section SC2.

[0351] On the other hand, if the lighting lottery process for the section display unit 67 (step S1908) selects "waiting to light" (step S1909: NO), the lighting waiting flag provided in the main RAM 74 is set to "1" (step S1911). The lighting waiting flag is a flag used by the main MPU 72 to identify that the section display unit 67 is in a state where it is waiting to switch from the off state to the on state in the second section SC2.

[0352] Next, the second control process for the game section, which is executed by the main MPU 72, will be explained with reference to the flowchart in Figure 44. The second control process for the game section is executed in step S1807 of the response process at the end of the game (Figure 39). As described above, the response process at the end of the game is executed after the rotation of all reels 32L, 32M, and 32R in one game has stopped, so the second control process for the game section is also executed after the rotation of all reels 32L, 32M, and 32R in one game has stopped.

[0353] If the second section flag of the main RAM 74 is set to "1" and the current game section is the second section SC2 (Step S2001: YES), the state of the flag in the main RAM 74 is checked to determine whether the current game state is the termination preparation state ST6 (Step S2002). The termination preparation state ST6 is a game state that is entered when the pseudo-bonus state ST4 or AT state ST5 ends without the ending conditions of the second section SC2 being met, and the second section SC2 ends when transitioning to the normal game state ST1.

[0354] If the game is in the termination preparation state ST6 (step S2002: YES), it is determined whether the termination preparation complete flag in the main RAM 74 is set to "1" (step S2003). The termination preparation complete flag is a flag used by the main MPU 72 to determine whether or not one game has been executed in the termination preparation state ST6. In the pseudo-bonus processing (step S1805) in the game termination processing (Figure 39), if it is determined that the remaining number of games in the pseudo-bonus state ST4 is 0 and that the game will then transition to the normal game state ST1, the flag to set the game to the termination preparation state ST6 is set and the termination preparation complete flag is cleared to "0". Also, in the AT processing (step S1806) in the game termination processing (Figure 39), if it is determined that one set has ended and the game will transition to the normal game state ST1 while the remaining number of sets in the AT state ST5 is 0, the flag to set the game to the termination preparation state ST6 is set and the termination preparation complete flag is cleared to "0".

[0355] If the "Ready to End" flag is not set to "1" (Step S2003: NO), the process from Step S2005 onwards is executed after setting the "Ready to End" flag to "1" (Step S2004). If the "Ready to End" flag is set to "1" (Step S2003: YES), it means that one game has been executed in the "Ready to End" state ST6. In this case, the process to terminate the second section SC2 is executed.

[0356] Specifically, the initialization process for the second section SC2 is performed first (step S2014). During the initialization process for the second section SC2, the second section flag in the main RAM 74 is cleared to "0". This makes the game section the first section SC1. Also, during the initialization process for the second section SC2, even if the player is in AT state ST5, the game state is changed to normal game state ST1 by clearing various data (including the AT state flag) that indicate that the player is in AT state ST5, including a counter that stores the remaining number of games in AT state ST5. Note that even if the player is in the middle of the first CB state ST2 or the second CB state ST3, the initialization process for the second section SC2 will be performed, ending the second section SC2, but the first CB state ST2 and the second CB state ST3 will continue without ending.

[0357] Subsequently, if the section indicator unit 67 is lit, the section indicator unit 67 is switched from the lit state to the off state (step S2015). This terminates the notification that the section indicator unit 67 is in the second section SC2. Then, a second section initialization command is sent to the performance-side MPU 92 to indicate that the second section SC2 has been initialized (step S2016). This causes the performance-side MPU 92 to execute the performance corresponding to the completion of the second section SC2.

[0358] If the system is not in the termination preparation state ST6 (step S2002: NO), or if the process in step S2004 is executed, the value of the continuation game count counter 74c in the main RAM 74 is incremented by 1 (step S2005). As previously explained, the continuation game count counter 74c is a counter used by the main MPU 72 to determine the number of games executed from the start of the second section SC2 when the second section SC2 continues without the first section SC1 being in between.

[0359] Subsequently, it is determined whether the value of the continuation game counter 74c after the increment of 1 is 1500 or more, which is the upper limit of games (step S2006). If the value of the continuation game counter 74c is 1500 or more, it means that the ending condition for the second section SC2 has been met. In this case, a positive determination is made in step S2006, and the processing to terminate the second section SC2 in steps S2014 to S2016 is executed. The processing contents of steps S2014 to S2016 are as already explained. As a result, the second section SC2 ends and the first section SC1 begins, and if the AT state ST5 was in progress, the AT state ST5 is forcibly terminated and the game returns to the normal game state ST1.

[0360] If the value of the continuous game counter 74c is less than 1500 (Step S2006: NO), it is determined whether a first chance replay, a second chance replay, or a normal replay was achieved in the current game (Step S2007). In this case, the determination in Step S2007 applies regardless of whether the number of bets in the current game was "2" or "3", and also regardless of whether the current game is in normal game state ST1, first CB state ST2, second CB state ST3, pseudo bonus state ST4, or AT state ST5.

[0361] If no replay wins occur (Step S2007: NO), the number of bets for the current game is subtracted from the total winnings counter 74d of the main RAM 74 (Step S2008). In this case, the number of bets for the current game is determined from the value of the bet history counter 74f, not the value of the bet setting counter 74a. As already explained, in normal processing (Figure 25), the value of the bet setting counter 74a is set to the bet history counter 74f at a timing after all reels 32L, 32M, and 32R have finished spinning in one game, and before the timing when the corresponding processing at the end of the game (Step S912) begins. Therefore, at the timing when the second control processing of the game section (Figure 44) begins, the bet history counter 74f is set to the number of bets for the current game. Furthermore, even if a replay win occurred in the previous game and the current game is a replay resulting from that replay win, the number of bets in the current game (i.e., the value of the bet history counter 74f) will be subtracted from the total winnings counter 74d.

[0362] As previously explained, the total acquisition counter 74d is a counter used by the main MPU 72 to determine the total net increase in game tokens, subject to the limits of game tokens, from the start of the second section SC2 when the second section SC2 continues without the first section SC1 being in between. The total net increase in game tokens, subject to the limits of game tokens, is defined as the number of tokens added to the predetermined net increase from the predetermined standard value, when the predetermined net increase is calculated by subtracting the total number of game tokens consumed to play a game while the second section SC2 is continuing (0 if no game tokens are being played) from the total number of game tokens granted by games played while the second section SC2 is continuing (0 if no game tokens are being granted), and the minimum value of this predetermined net increase is used as the predetermined standard value.

[0363] Subsequently, it is determined whether any of the following small wins (1st to 9th compensation wins, 1st bell win, 2nd bell win, 1st watermelon win, 2nd watermelon win, and cherry win) that result in the awarding of game tokens have occurred in the current game (Step S2009). In this case, the determination in Step S2009 is made regardless of whether the number of bets in the current game is "2" or "3", and the determination in Step S2009 is made regardless of whether the current game is in normal game state ST1, 1st CB state ST2, 2nd CB state ST3, pseudo bonus state ST4, or AT state ST5.

[0364] If a positive result is obtained in step S2009, the number of game media awarded in this game is added to the total acquisition counter 74d of the main RAM 74 (step S2010). In this case, the number of game media awarded in this game is determined from the value of the award history counter, not the value of the media award counter. As already explained, in normal processing (Figure 25), the value of the media award counter is set to the award history counter at a timing after all reels 32L, 32M, and 32R have finished rotating in one game and the media award processing (step S910) has finished, but before the timing when the corresponding processing at the end of the game (step S912) begins. Therefore, at the timing when the second control processing of the game section (Figure 44) begins, the number of game media awarded in this game is set in the award history counter.

[0365] If a negative result is obtained in step S2009, or if the process in step S2010 is executed, it is determined whether the value of the total acquired counter 74d in the main RAM 74 is 0 or greater (step S2011). If the value of the total acquired counter 74d is less than 0 (step S2011: NO), the total acquired counter 74d is cleared to "0" (step S2012).

[0366] As described above, in step S2008, the number of bets for the current game is subtracted from the total acquired counter 74d. For example, if no small wins occur in a game during the normal game state ST1 immediately after transitioning to the second section SC2, the value of the total acquired counter 74d will be less than 0. In this case, a negative judgment is made in step S2011, and the total acquired counter 74d is cleared to "0" in step S2012. This makes it possible to measure the limited total net increase in game tokens, which is the increase in the predetermined net increase from the predetermined standard value, using the total acquired counter 74d, when the predetermined net increase is defined as the difference between the total number of game tokens granted by games played while the second section SC2 is continuing ("0" if no game tokens are granted) and the total number of game tokens consumed to play a game while the second section SC2 is continuing ("0" if no game is played).

[0367] If a positive result is obtained in step S2007, step S2011, or step S2012, it is determined whether the value of the total acquired counter 74d exceeds the upper limit of net increase, "2400" (step S2013). If the value of the total acquired counter 74d exceeds "2400", it means that the ending condition for the second section SC2 has been met. In this case, a positive result is obtained in step S2013, and the process to terminate the second section SC2 in steps S2014 to S2016 is executed. The processing in steps S2014 to S2016 is as already explained. As a result, the second section SC2 ends and the first section SC1 begins, and if the player was in the middle of AT state ST5, AT state ST5 is forcibly terminated and the player returns to normal game state ST1.

[0368] Here, if any replay win occurs, a positive result is made in step S2007, and the processes in steps S2008 to S2012 are not executed. In games in which a replay win occurs, the game tokens owned by the player at the start of the game are used when setting the bet, but as a benefit of the replay win, it is possible to play a new game with the same number of bets as the number of bets made in the game in which the replay win occurred. In other words, the number of game tokens owned by the player does not change in games in which a replay win occurs. In this case, by not executing the processes in steps S2008 to S2012 in games in which a replay win occurs, it becomes possible to omit the execution of the process to change the value of the total acquired counter 74d in games in which the number of game tokens owned by the player does not change, thereby eliminating the execution of unnecessary processes.

[0369] On the other hand, even in games where a replay win is achieved, step S2013 determines whether the value of the total acquired counter 74d exceeds the upper limit of net increase, "2400". This makes it possible to determine if the value of the total acquired counter 74d actually exceeded the upper limit of net increase, "2400", in a game prior to the game in which the replay win was achieved, but the initialization process of the second section SC2 was not executed due to noise or other reasons, and to ensure that the initialization process of the second section SC2 is executed in the subsequent game in which the replay win is achieved.

[0370] If a negative result is obtained in step S2013, the ending processing is executed (step S2017). Figure 45 is a flowchart of the ending processing.

[0371] First, it is determined whether the first ending flag in the main RAM 74 is set to "1" (step S2101). The first ending flag is a flag used by the main MPU 72 to identify that there is a high probability that the number of game executions in the second section SC2, which is measured using the continuation game counter 74c, will reach the upper limit of the number of games.

[0372] If the first ending flag is not set to "1" (step S2101: NO), it is determined whether the sum of the value of the continuation game count counter 74c in the main RAM 74, the value of the AT continuation counter provided in the main RAM 74, the value of the set count counter provided in the main RAM 74, and the value of the initial continuation game count in one set of AT state ST5 (50 games) is equal to or greater than the upper limit of games in the second section SC2 (step S2102). The AT continuation counter is a counter used by the main MPU 72 to identify the remaining number of continuation games in one set of AT state ST5. The initial number of continuation games in one set of AT state ST5 is 50 games, and the remaining number of continuation games may increase if an additional condition is met during that set. The set count counter is a counter used by the main MPU 72 to identify the remaining number of sets of AT state ST5. The upper limit of games in the second section SC2 is set to 1500 games, as already explained. Furthermore, the maximum number of games in the second section SC2 is not limited to 1500 games; it may be less than 1500 games or more than 1500 games.

[0373] If a positive result is obtained in step S2102, the first ending flag is set to "1" (step S2103). When the first ending flag is set to "1", as will be explained in detail later, no further increases in the remaining number of continuation games or sets will occur in AT state ST5. This makes it possible to prevent further increases in the remaining number of continuation games and sets in AT state ST5 when the ending conditions for the second section SC2 are met.

[0374] Subsequently, the first ending command is sent to the production-side MPU92 (step S2104). This first ending command includes information on the number of games required until the ending conditions of the second section SC2 are met, that is, information corresponding to the difference between the value of the continuation game counter 74c and the upper limit of the number of games in the second section SC2.

[0375] The performance-side MPU92 can understand that the main-side MPU72 has set the first ending flag to "1" by receiving the first endin...

Claims

[Claim 1] A value information storage area capable of storing value information related to the number of game values, A predetermined display control means that controls a predetermined display means to display a value information corresponding to the value information stored in the value information storage area, A game execution means controls the game execution means so that a game unit operation is started when a trigger for starting a game occurs, and the game unit operation is terminated when a trigger for ending a game occurs. A game response execution means that executes game response processing using the value information after the completion of the game unit operation, A value information erasure means for erasing the value information stored in the value information storage area after the completion of the game unit operation and before the execution of the game corresponding processing, Within the scope of one game, before the value information stored in the value information storage area is erased by the value information erasure means, a separate storage execution means causes the value information stored in the value information storage area to be stored in a separate storage area, Equipped with, The aforementioned game-related execution means executes the game-related processing using the value information stored in the separate storage area. The gaming machine is characterized in that the process of storing the value information in the separate storage area by the separate storage execution means is performed after the completion of the game unit operation and before the value information stored in the value information storage area is erased by the value information erasure means.

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