Image sensing device

Abstract

To provide an image sensing device which has multi-floating diffusions (FD) and an analog-digital converter and an operation method of the same.SOLUTION: An image sensing device includes: a photoelectric element PD; first and second FD1, FD2 configured to store the electric charge generated by the PD; a transfer gate TG having one end connected to the PD and the other end connected to the FD1; a first DCG transistor DCG having one end connected to the FD1 and the other end connected to the FD2; a first pixel circuit configured to generate first output voltage based on the voltage of the FD1; a second pixel circuit configured to generate second output voltage based on the voltage of the FD2; a first analog-digital converter 310 configured to receive the provision of the first output voltage and convert the first output voltage to a first digital signal; and a second analog-digital converter 320 arranged so as to be separated from the first analog-digital converter and configured to receive the provision of the second output voltage and convert the second output voltage to a second digital signal.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to an image sensing device.

Background Art

[0002] An image sensing device is one of semiconductor devices that convert optical information into an electrical signal. Such image sensing devices include a charge coupled device (CCD) image sensing device and a complementary metal-oxide semiconductor (CMOS) image sensing device, etc. The CMOS image sensor is abbreviated as CIS (CMOS image sensor).

[0003] As a method for realizing a high dynamic range (HDR) scene using a CIS, a multiple exposure method, a multiple conversion gain (MCG) method, etc. are used respectively. However, since such methods go through a process of repeatedly reading data several times and then synthesizing it, there is a problem that the frame rate decreases.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The technical problem to be solved by the present invention is to provide an image sensing device including a multiple floating diffusion and an analog-to-digital convertor.

[0005] Another technical problem to be solved by the present invention is to provide an operating method of an image sensing device that can realize an HDR scene with a single read operation.

[0006] The technical problems that this invention aims to solve are not limited to those mentioned above, and any other problems not mentioned can be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] An image sensing device according to the technical concept of the present invention to solve the aforementioned problems comprises: a photoelectric element that generates an electric charge in response to light; a first floating diffusion FD1 in which the charge generated by the photoelectric element is stored; a second floating diffusion FD2 in which the charge generated by the photoelectric element is stored; a transfer gate with one end connected to the photoelectric element and the other end connected to the first floating diffusion FD1; a reset transistor that resets the voltages of the first and second floating diffusions based on a reset signal; and a first DCG (Dual Conversion Gate) with one end connected to the first floating diffusion and the other end connected to the second floating diffusion. A gain transistor may include a first DCG transistor that connects a first floating diffusion and a second floating diffusion based on a first DCG control signal, a first pixel circuit that generates a first output voltage based on the voltage of the first floating diffusion, a second pixel circuit that generates a second output voltage based on the voltage of the second floating diffusion, a first analog-to-digital converter that receives the first output voltage and converts it into a first digital signal, and a second analog-to-digital converter that is located separately from the first analog-to-digital converter and receives the second output voltage and converts it into a second digital signal.

[0008] An image sensing device according to the technical concept of the present invention for solving the aforementioned problems includes a first pixel circuit that generates and outputs a first output voltage in a high-conversion manner based on a charge generated by a single photoelectric element, a first analog-to-digital converter that receives the first output voltage and converts it into a first digital signal, a second pixel circuit that generates and outputs a second output voltage different from the first output voltage in a low-conversion manner based on a charge generated by a single photoelectric element PD, and a second analog-to-digital converter that receives the second output voltage and converts it into a second digital signal, wherein the first analog-to-digital converter is arranged on a first plate, and the second analog-to-digital converter may be arranged on a second plate different from the first plate.

[0009] An operating method for an image sensing device according to the technical concept of the present invention for solving the aforementioned problems may include: linking a first floating diffusion and a second floating diffusion based on a first DCG control signal; resetting the voltage levels of the first floating diffusion and the second floating diffusion to a reset level; transitioning the voltage level of the first floating diffusion from a reset level to a first signal level based on the charge generated from a photoelectric element; transitioning the voltage level of the second floating diffusion from a reset level to a second signal level different from the first signal level based on the charge generated from a photoelectric element; separating the first floating diffusion and the second floating diffusion based on a first DCG control signal; generating a first digital signal based on the level difference between the reset level and the first signal level of the first floating diffusion; and generating a second digital signal based on the level difference between the reset level and the second signal level of the second floating diffusion.

[0010] Further details of this invention are included in the detailed description and drawings. [Brief explanation of the drawing]

[0011] [Figure 1]This is an illustrative block diagram of an image sensing device according to several embodiments of the present invention. [Figure 2] This figure illustrates the stack structure of an image sensing device according to several embodiments of the present invention. [Figure 3] This is a circuit diagram illustrating the structure of the pixels included in the pixel array shown in Figure 1. [Figure 4] This diagram illustrates the operation of the circuit shown in Figure 3. [Figure 5] This diagram illustrates the operation of the circuit shown in Figure 3. [Figure 6] This diagram illustrates the operation of the circuit shown in Figure 3. [Figure 7] This diagram illustrates the operation of the circuit shown in Figure 3. [Figure 8] This diagram illustrates the charge potentials of the photoelectric element and the first and second floating diffusions. [Figure 9] This diagram illustrates the charge potentials of the photoelectric element and the first and second floating diffusions. [Figure 10] This figure shows the waveform of the signal applied to a pixel and the change in output voltage during one sensing period. [Figure 11] This diagram illustrates the operation of a pixel circuit, which does not include the technical concept of the present invention. [Figure 12] This figure illustrates the stacked structure of an image sensing device according to another embodiment of the present invention. [Figure 13] This figure illustrates a stacked structure of an image sensing device according to several other embodiments of the present invention. [Figure 14] This figure illustrates a stacked structure of an image sensing device according to several other embodiments of the present invention. [Figure 15] This figure illustrates a stacked structure of an image sensing device according to several other embodiments of the present invention. [Figure 16]An exemplary block diagram of an image sensing device according to some other embodiments of the present invention. [Figure 17a] A circuit diagram for explaining the structure of pixels included in the pixel array of FIG. 16. [Figure 17b] A diagram showing the waveforms of signals applied to a pixel and the change in output voltage during one sensing period of FIG. 17a. [Figure 18] A diagram for explaining the stacked structure of the image sensing device shown in FIG. 17a. [Figure 19] A diagram for explaining the stacked structure of an image sensing device according to some other embodiments of the present invention. [Figure 20] A diagram for explaining the stacked structure of an image sensing device according to some other embodiments of the present invention. [Figure 21] A diagram for explaining the stacked structure of an image sensing device according to some other embodiments of the present invention. [Figure 22] A diagram for explaining the stacked structure of an image sensing device according to some other embodiments of the present invention. [Figure 23] An exemplary block diagram of an image sensing device according to some other embodiments of the present invention. [Figure 24] A circuit diagram for explaining the structure of pixels included in the pixel array of FIG. 23. [Figure 25] A diagram for explaining the stacked structure of an image sensing device according to some other embodiments of the present invention. [Figure 26] A diagram for explaining the stacked structure of an image sensing device according to some other embodiments of the present invention. [Figure 27] A diagram for explaining the stacked structure of an image sensing device according to some other embodiments of the present invention. [Figure 28] A diagram for explaining the stacked structure of an image sensing device according to some other embodiments of the present invention. [Figure 29] This is a block diagram of an electronic device including a multi-camera module. [Figure 30] This is a block diagram of an electronic device including a multi-camera module. [Figure 31] Figures 29 and 30 are detailed block diagrams of the camera module. [Modes for carrying out the invention]

[0012] Embodiments of the technical concept of the present invention will be described below with reference to the attached drawings.

[0013] Figure 1 is an illustrative block diagram of an image sensing device according to several embodiments of the present invention.

[0014] The image sensing device 1 may include a pixel array 100, a logic circuit 200, an analog-to-digital converter circuit 300, and a memory 400. The pixel array 100 includes a plurality of pixels 110, which are connected to row lines extending in a first direction and column lines extending along a second direction intersecting the first direction, and are arranged in a matrix configuration. Each pixel 110 may include at least one photoelectric element that generates an electric charge in response to light, and a pixel circuit that generates an output voltage using the charge generated by the photoelectric element. In Figure 1, the pixel array 100 is shown in a 6x8 matrix configuration, but this is illustrative, and this embodiment is not limited thereto, and the pixel array 100 may include a variety of numbers of pixels.

[0015] The logic circuit 200 may include circuits for driving the pixel array. For example, the logic circuit 200 may include a row driver for driving the row lines, a read-out circuit for obtaining output voltages from the pixels 110 via the column lines, control logic for controlling the row driver and read-out circuit, a power supply circuit, an input / output interface, and an image signal processor.

[0016] The analog-to-digital converter circuit 300 may include multiple analog-to-digital converters. Each analog-to-digital converter receives an image signal in analog form and converts it into a digital signal. The analog-to-digital converter uses the CDS (Correlated Double Sampling) method to convert the analog signal into a digital signal. The analog-to-digital converter circuit 300 may be located separately from the logic circuit 200, or it may be incorporated within the logic circuit 200.

[0017] The memory 400 may include a storage element, which can be implemented as at least one of a MIM (Metal-Insulator-Metal) capacitor, a charge trap element, an MTJ (Magnetic Tunnel Junction) element, and a GST (Germanium (Ge)-Antimony (Sb)-Tellurium (Te) element). The memory 400 is connected to the pixel 110 and / or logic circuit 200.

[0018] Figure 2 is a diagram illustrating the stack structure of an image sensing device according to several embodiments of the present invention.

[0019] Referring to Figures 1 and 2, the image sensing device is formed in a stacked structure including a first plate P1 and a second plate P2. The second plate P2 is formed parallel to the first plate P1. Specifically, the second plate P2 is formed on top of the first plate P1 and parallel to the first plate P1. The first plate may include a pixel array area PA and a pixel periphery area PS. The pixel array 100 is located in the pixel array area PA. The logic circuit 200 may be located in the pixel periphery area PS or in the second plate P2.

[0020] The second plate may include a first area P2_1 and a second area P2_2. The second area P2_2 is formed physically separate from the first area P2_1. In some embodiments, when the analog-to-digital converter circuit 300 shown in Figure 1 includes a plurality of analog-to-digital converters 310, 320, the first analog-to-digital converter 310 is located in the first area P2_1, and the second analog-to-digital converter 320 is located in the second area P2_2.

[0021] Figure 3 is a circuit diagram illustrating the structure of the pixels included in the pixel array of Figure 1.

[0022] Referring to Figure 3, the pixel 110 may include a photoelectric element PD, a reset transistor RT that resets the voltage levels of the first and second floating diffusion elements FD1 and FD2 to the reset level V_RST, a transfer gate TG that transfers the charge generated by the photoelectric element PD to the first and second floating diffusion elements FD1 and FD2, a DCG transistor DCG that connects the first floating diffusion element FD1 and the second floating diffusion element FD2, a first pixel circuit 111, and a second pixel circuit 112.

[0023] A photoelectric element (PD) senses an external image (or light) and generates an electric charge. For example, a photoelectric element (PD) may include an organic photodiode. When the photoelectric element (PD) is an organic photodiode, it may include first and second electrodes arranged parallel to each other and an organic photoconversion layer provided between them, which accepts light in a predetermined wavelength band and generates an electric charge. The photoelectric element (PD) may be a photodiode, phototransistor, photogate, pinned photodiode, or a combination thereof, but the embodiments are not limited thereto.

[0024] One end of the transfer gate TG is connected to the photoelectric element PD, and the other end is connected to the first floating diffusion FD1. Based on the transfer gate signal S_TG, the transfer gate TG connects the photoelectric element PD to the first floating diffusion FD1 and the second floating diffusion FD2.

[0025] The first pixel circuit 111 may include a first source follower transistor SF1 and a first selection transistor ST1. The gate terminal of the first source follower transistor SF1 is connected to the first floating diffusion FD1, and the source terminal is supplied with a pixel voltage V_PIX. The first source follower transistor SF1 operates as a source follower buffer amplifier by the charge transferred to the first floating diffusion FD1. That is, the first source follower transistor SF1 can amplify the charge generated by the photoelectric element PD and transferred to the first floating diffusion FD1 using the pixel voltage V_PIX and transfer it to the first selection transistor ST1. The first selection transistor ST1 is controlled by a selection signal SEL provided by the low driver and performs switching and addressing operations. The source terminal of the first selection transistor ST1 is connected to the drain terminal of the first source follower transistor SF1 and outputs a first output voltage V_OUT1 to the column connected to the first selection transistor ST1. The first output voltage V_OUT1 is supplied to the first analog-to-digital converter 310.

[0026] The second pixel circuit 112 may include a second source follower transistor SF2 and a second select transistor ST2. The gate terminal of the second source follower transistor SF2 is connected to the second floating diffusion FD2, and the source terminal is supplied with the pixel voltage V_PIX. The second source follower transistor SF2 operates as a source follower buffer amplifier by the charge transferred to the second floating diffusion FD2. That is, the second source follower transistor SF2 can amplify the charge generated by the photoelectric element PD and transferred to the second floating diffusion FD2 using the pixel voltage V_PIX and transfer it to the second select transistor ST2. The second select transistor ST2 is controlled by a select signal SEL provided from the low driver and performs switching and addressing operations. The source terminal of the second select transistor ST2 is connected to the drain terminal of the second source follower transistor SF2, outputting the second output voltage V_OUT2 to the column connected to the second select transistor ST2. The second output voltage V_OUT2 is supplied to the second analog-to-digital converter 320.

[0027] In some embodiments, the first and second floating diffusions FD1, FD2 may be MIM capacitors, or they may be in the form of cylindrical capacitors used in DRAM cells. Referring further to Figure 2, the first and second floating diffusions FD1, FD2 may be formed between the first plate P1 and the second plate P2 in the case of MIM capacitors, and on the second plate P2 in the case of cylindrical capacitors.

[0028] One end of the DCG transistor DCG is connected to the first floating diffusion element FD1 and the photoelectric element PD, and the other end is connected to the second floating diffusion element FD2. The DCG transistor DCG adjusts the amount of charge supplied from the photoelectric element PD and / or the first floating diffusion element FD1 to the second floating diffusion element FD2 based on the DCG control signal S_DCG.

[0029] Figure 3 shows that only the first and second pixel circuits 111 and 112 are connected to a single photoelectric element PD, but the embodiment is not limited to this and may further include multiple pixel circuits similar to the first and second pixel circuits 111 and 112.

[0030] Next, the operation of the pixel 110 circuit in Figure 3 will be explained with reference to Figures 4 through 10.

[0031] Figures 4 through 7 illustrate the operation of the circuit in Figure 3. Figures 8 through 9 illustrate the charge potentials of the photoelectric element and the first and second floating diffusions. Figure 10 shows the waveform of the signal applied to the pixel and the change in output voltage during one sensing period.

[0032] The operation of the pixel circuit described below is merely one example, and its detailed configuration can be modified as needed.

[0033] Referring to Figures 4 and 10, prior to the first time point t1, the DCG control signal S_DCG transitions from a logical low level (hereinafter referred to as L level) to a logical high level (hereinafter referred to as H level). That is, the DCG control signal S_DCG is enabled. As a result, the DCG transistor DCG is turned on. That is, the first floating diffusion FD1 and the second floating diffusion FD2 can be electrically connected.

[0034] At the first time point t1, the reset signal RESET transitions from L level to H level. That is, the reset signal RESET is enabled. Therefore, the reset transistor RT is turned on. Meanwhile, the DCG control signal S_DCG remains at the H level. That is, the DCG control signal S_DCG can remain enabled. Because the DCG control signal S_DCG remains at the H level, the DCG transistor DCG remains turned on, and therefore the first floating diffusion FD1 and the second floating diffusion FD2 can remain electrically connected. Consequently, when the reset transistor RT is turned on, both the first floating diffusion FD1 and the second floating diffusion FD2 are reset to the pixel voltage V_PIX.

[0035] Next, referring to Figures 5 and 10, after the first time point t1 and before the second time point t2, the reset signal RESET transitions from a high level to a low level. That is, the reset signal RESET is disabled. As a result, the reset transistor RT is turned off. On the other hand, the DCG control signal S_DCG remains at a high level. That is, the DCG control signal S_DCG can remain in the enabled state. By maintaining the high level of the DCG control signal S_DCG, the DCG transistor DCG remains in the turned-on state, and as a result, the first floating diffusion FD1 and the second floating diffusion FD2 can remain electrically connected.

[0036] After the reset transistor RT is turned off and before the second time point t2, the selection signal SEL transitions from the L level to the H level. That is, the selection signal SEL is enabled. As a result, the first and second selection transistors ST1 and ST2 are turned on. The first source follower transistor SF1 outputs the charge level of the first floating diffusion FD1 as the first output voltage V_OUT1 using the pixel voltage V_PIX. In this case, the first output voltage V_OUT1 may be the reset voltage V_RST. The second source follower transistor SF2 outputs the charge level of the second floating diffusion FD2 as the second output voltage V_OUT2 using the pixel voltage V_PIX. In this case, since the DCG transistor DCG remains turned on, the charge level of the first floating diffusion FD1 is the same as the charge level of the second floating diffusion FD2. That is, the second output voltage V_OUT2 may also be the reset voltage V_RST.

[0037] Next, referring to Figures 6 and 10, at the second time point t2, the transfer gate signal S_TG transitions from the L level to the H level. That is, the transfer gate signal S_TG is enabled. Therefore, the transfer gate TG is turned on. On the other hand, the DCG control signal S_DCG remains at the H level. That is, the DCG control signal S_DCG can remain in the enabled state. By the DCG control signal S_DCG remaining at the H level, the DCG transistor DCG remains in the turned-on state, and therefore the first floating diffusion FD1 and the second floating diffusion FD2 can remain electrically connected. Consequently, when the transfer gate TG is turned on, the charge stored in the photoelectric element PD is transferred to the first floating diffusion FD1 and the second floating diffusion FD2. That is, the charge levels of the first floating diffusion FD1 and the second floating diffusion FD2 increase (charging).

[0038] Referring further to Figure 8, prior to the second time point t2, the photoelectric element PD stores the charge generated by sensing the external image (or light). Subsequently, at the second time point t2, the transfer gate control signal S_TG transitions from the L level to the H level, causing charge to move from the photoelectric element PD to the first and second floating diffusions FD2, which have relatively lower charge potentials. That is, the charge level of the photoelectric element PD (H1 in Figure 8) decreases.

[0039] Referring further to Figure 9, in some embodiments, as mentioned above, the first floating diffusion FD1 and the second floating diffusion FD2 may have different capacitances, so the degree to which the charge level of the first floating diffusion FD1 increases may differ from the degree to which the charge level of the second floating diffusion FD2 increases. In some embodiments, the capacitance of the first floating diffusion FD1 may be smaller than the capacitance of the second floating diffusion FD2. Therefore, the degree to which the charge level of the first floating diffusion FD1 increases H2 may be smaller than the degree to which the charge level of the second floating diffusion FD2 increases H3. In Figures 8 and 9, the transition of the transfer gate control signal S_TG from L level to H level is shown to cause the charge level of the photoelectric element PD to decrease from H1 to 0, but this is illustrative and the embodiments are not limited thereto.

[0040] Referring to Figures 7 and 10, at the third time point t3, the transfer gate signal S_TG transitions from a high level to a low level. That is, the transfer gate signal S_TG is disabled. Therefore, the transfer gate TG is turned off. Also at the third time point t3, the DCG control signal S_DCG transitions from a high level to a low level. That is, the DCG control signal S_DCG is disabled. Therefore, the DCG transistor DCG is turned off, and the first floating diffusion FD1 and the second floating diffusion FD2 are electrically isolated.

[0041] After the third time point t3, the selection signal SEL transitions from L level to H level. That is, the selection signal SEL is enabled. As a result, the first and second selection transistors ST1 and ST2 are turned on. On the other hand, the transfer gate signal S_TG and the DCG control signal S_DCG remain at L level. That is, the transfer gate signal S_TG and the DCG control signal S_DCG can remain in the disabled state. Because the transfer gate signal S_TG and the DCG control signal S_DCG remain at L level, the transfer gate TG and the DCG transistor DCG can remain in the turned-off state. As a result, the photoelectric element PD and the first floating diffusion FD1, and the first floating diffusion FD1 and the second floating diffusion FD2 can each remain electrically isolated.

[0042] The first source follower transistor SF1 outputs the charge level of the first floating diffusion FD1 as the first output voltage V_OUT1 using the pixel voltage V_PIX. In this case, the first output voltage V_OUT1 may be the first signal voltage V_S1. The second source follower transistor SF2 outputs the charge level of the second floating diffusion FD2 as the second output voltage V_OUT2 using the pixel voltage V_PIX. In this case, since the DCG transistor DCG remains in the turned-off state, the second output voltage V_OUT2 is different from the first output voltage V_OUT1. Specifically, the second output voltage V_OUT2 may be the second signal voltage V_S2. The first signal voltage V_S1 may have a higher level than the second signal voltage V_S2.

[0043] The method of converting the charge of the floating diffusion to an output voltage differs depending on the difference in capacitance between the first and second floating diffusions FD1 and FD2, or the control of the charge transfer of the DCG transistor DCG. That is, the charge-voltage conversion coefficients of the first pixel circuit 111 and the second pixel circuit 112 may be different. In some embodiments, the method by which the first pixel circuit 111 generates the first output voltage V_OUT1 may be a high-conversion method, and the method by which the second pixel circuit 112 generates the second output voltage V_OUT2 may be a low-conversion method.

[0044] The first and second output voltages V_OUT1 and V_OUT2, output through the process described above, are converted into first and second digital signals, respectively, via the first and second analog-to-digital converters ADC1 and ADC2. Each analog-to-digital converter ADC1 and ADC2 compares the levels of the reset voltage V_RST and the respective signal voltages V_S1 and V_S2 using the CDS method and generates digital signals based on the level difference (DV1 and DV2 in Figure 10). In other words, the first and second digital signals are generated simultaneously.

[0045] Next, the effects of the present invention will be described with reference to Figure 11.

[0046] Figure 11 is a diagram illustrating the operation of a pixel circuit that does not include the technical concept of the present invention.

[0047] Specifically, unlike the one shown in Figure 3, this is a description of an image sensing device that includes first and second floating diffusions connected by a DCG transistor, but includes one pixel circuit and an analog-to-digital converter to sense the voltage of each floating diffusion. Referring to Figure 11, without the technical concept of the present invention, two voltage lead processes are required to generate two different output voltages. That is, compared to Figure 10, the voltage of the first floating diffusion with the DCG transistor turned off is sensed between time point 4 t4 and time point 5 t5, and thereafter, with the DCG transistor turned on, the voltages of the first and second floating diffusions must be sensed after time point 5 t5. Therefore, the first and second digital signals are not generated simultaneously, and as a result, the sensing period T of the image signal increases.

[0048] The image sensing device according to this embodiment simultaneously reads two analog image signals generated by different CG (Conversion Gain) to realize an HDR scene. Therefore, the sensing period T of the image signal can be shortened compared to the case in Figure 11 (a in Figure 10 < b in Figure 11).

[0049] However, including additional analog-to-digital converters in an image sensing device may present design challenges related to integration limits. Such design limitations can be overcome by forming the image sensing device as a stacked structure composed of multiple plates, as explained with reference to Figure 2, and by placing the additional analog-to-digital converters on these plates.

[0050] Figure 12 illustrates the stacked structure of an image sensing device according to another embodiment of the present invention. The following explanation will focus on the differences from Figure 2.

[0051] Referring to Figure 12, the image sensing device is formed in a stacked structure including a first plate P1 and a second plate P2. The second plate P2 is formed parallel to the first plate P1. Specifically, the second plate P2 is formed on top of the first plate P1 and parallel to the first plate P1. The first plate P1 may include a pixel array area PA and a pixel periphery area PS. The pixel array 100 is located in the pixel array area PA. The first analog-to-digital converter 310 is located in the pixel periphery area PS. The second analog-to-digital converter 320 is located on the second plate P2.

[0052] Figure 13 illustrates the stacked structure of an image sensing device according to several other embodiments of the present invention. The following explanation will focus on the differences from Figure 2.

[0053] Referring to Figure 13, the image sensing device is formed as a stacked structure including a first plate P1, a second plate P2, and a third plate P3. Each of the plates P1, P2, and P3 is formed parallel to the others. Specifically, the second plate P2 is formed on top of the first plate P1 and parallel to the first plate P1, and the third plate P3 is formed between the first plate P1 and the second plate P2 and parallel to the first and second plates P1 and P2. The first plate P1 may include a pixel array area PA and a pixel periphery area PS. The pixel array 100 is located in the pixel array area PA. The first analog-to-digital converter 310 is located on the second plate P2. The second analog-to-digital converter 320 is located on the third plate P3.

[0054] Figure 14 is a diagram illustrating the stacked structure of an image sensing device according to several other embodiments of the present invention. The differences from Figure 2 will be explained below.

[0055] Referring to Figure 14, the image sensing device is formed as a stacked structure including a first plate P1, a second plate P2, and a third plate P3. Each of the plates P1, P2, and P3 is formed parallel to each other. Specifically, the second plate P2 is formed on top of the first plate P1 and parallel to the first plate P1, and the third plate P3 is formed between the first plate P1 and the second plate P2 and parallel to the first and second plates P1 and P2. The third plate P3 may include a first area P3_1 and a second area P3_2. The second area P3_2 is formed physically separate from the first area P3_1. In this case, the first analog-to-digital converter 310 is located in the first area P3_1, and the second analog-to-digital converter 320 is located in the second area P3_2.

[0056] Figure 15 is a diagram illustrating the stacked structure of an image sensing device according to several other embodiments of the present invention. The differences from Figure 14 will be explained below.

[0057] Referring to Figure 15, the second plate P2 may include a first area P2_1 and a second area P2_2. The second area P2_2 is formed physically separate from the first area P2_1. In this case, the first analog-to-digital converter 310 is located in the first area P2_1, and the second analog-to-digital converter 320 is located in the second area P2_2.

[0058] Figure 16 is an illustrative block diagram of an image sensing device according to several other embodiments of the present invention. The differences from Figure 1 will be explained below.

[0059] Referring to Figure 16, the image sensing device 2 may include a pixel array 100, a logic circuit 200, an analog-to-digital converter circuit 500, and a memory 400. The pixel array 100 may include multiple pixels 120. The analog-to-digital converter circuit 500 may include multiple analog-to-digital converters 510, 520, and 530.

[0060] Figure 17a is a circuit diagram illustrating the structure of the pixels included in the pixel array of Figure 16. Figure 17b shows the waveform of the signal applied to the pixel and the change in output voltage during one sensing period of Figure 17a. The following explanation will focus on the differences from Figure 3.

[0061] Referring to Figure 17a, pixel 120 may include a photoelectric element PD, a reset transistor RT that resets the voltage levels of the first to third floating diffusions FD1, FD2, and FD3 to the reset level V_RST, a transfer gate TG that transfers the charge generated by the photoelectric element PD to the first to third floating diffusions FD1, FD2, and FD3, a first DCG transistor DCG1 that connects the first floating diffusion FD1 and the second floating diffusion FD2, a second DCG transistor DCG2 that connects the second floating diffusion FD2 and the third floating diffusion FD3, and first to third pixel circuits 121, 122, and 123. The first and second pixel circuits 121 and 122 are similar to the first and second pixel circuits 111 and 112 in Figure 3, respectively.

[0062] One end of the transfer gate TG is connected to the photoelectric element PD, and the other end is connected to the first floating diffusion FD1. Based on the transfer gate signal S_TG, the transfer gate TG connects the photoelectric element PD to the first to third floating diffusion FD1, FD2, and FD3.

[0063] The third pixel circuit 123 may include a third source follower transistor SF3 and a third select transistor ST3. The gate terminal of the third source follower transistor SF3 is connected to the third floating diffusion FD3, and the source terminal is supplied with the pixel voltage V_PIX. The third source follower transistor SF3 operates as a source follower buffer amplifier by the charge transferred to the third floating diffusion FD3. That is, the third source follower transistor SF3 can amplify the charge generated by the photoelectric element PD and transferred to the third floating diffusion FD3 using the pixel voltage V_PIX and transfer it to the third select transistor ST3. The third select transistor ST3 is controlled according to the select signal SEL provided from the low driver and performs switching and addressing operations. The source terminal of the third select transistor ST3 is connected to the drain terminal of the third source follower transistor SF3, outputting the third output voltage V_OUT3 to the column connected to the third select transistor ST3. The third output voltage V_OUT3 is supplied to the third analog-to-digital converter 530.

[0064] In some embodiments, the first to third floating diffusions FD1, FD2, and FD3 may be MIM capacitors, or they may take the form of cylindrical capacitors used in DRAM cells. Referring further to Figure 18, if the first to third floating diffusions FD1, FD2, and FD3 are in the form of MIM capacitors, they are formed between the second plate P2 and the third plate P3, and if they are cylindrical capacitors, they are formed on the second plate P2 or the third plate P3.

[0065] One end of the first DCG transistor DCG1 is connected to the first floating diffusion element FD1 and the photoelectric element PD, and the other end is connected to the second and third floating diffusion elements FD2 and FD3. The first DCG transistor DCG1 adjusts the amount of charge supplied from the photoelectric element PD and / or the first floating diffusion element FD1 to the second and third floating diffusion elements FD2 and FD3 based on the first DCG control signal S_DCG1.

[0066] One end of the second DCG transistor DCG2 is connected to the first and second floating diffusion elements FD1 and FD2 and the photoelectric element PD, and the other end is connected to the third floating diffusion element FD3. The second DCG transistor DCG2 adjusts the amount of charge supplied from the photoelectric element PD and / or the first and second floating diffusion elements FD1 and FD2 to the third floating diffusion element FD3 based on the second DCG control signal S_DCG2.

[0067] Figure 17a shows that only the first to third pixel circuits 121, 122, and 123 are connected to a single photoelectric element PD, but the embodiment is not limited to this and may further include multiple pixel circuits similar to the first to third pixel circuits 121, 122, and 123.

[0068] Next, referring to Figure 17b, the operation of the pixel circuit shown in Figure 17a will be explained. The operation of the pixel circuit shown in Figure 17a is the same as that described in Figures 4 to 10.

[0069] Referring to Figure 17b, prior to the first time point t1, the first and second DCG control signals S_DCG1 and S_DCG2 transition from the L level to the H level. That is, the first and second DCG control signals S_DCG1 and S_DCG2 are enabled. As a result, the first and second DCG transistors DCG1 and DCG2 are turned on. That is, the first floating diffusion FD1 and the second floating diffusion FD2, and the second floating diffusion FD2 and the third floating diffusion FD3 are electrically connected.

[0070] At the first time point t1, the reset signal RESET transitions from L level to H level. That is, the reset signal RESET is enabled. Therefore, the reset transistor RT is turned on. Meanwhile, the first and second DCG control signals S_DCG1 and S_DCG2 remain at the H level. That is, the first and second DCG control signals S_DCG1 and S_DCG2 can remain enabled. Because the first and second DCG control signals S_DCG1 and S_DCG2 remain at the H level, the first and second DCG transistors DCG1 and DCG2 remain turned on, and therefore the first to third floating diffusions FD1, FD2, and FD3 can remain electrically connected. Consequently, when the reset transistor RT is turned on, the first to third floating diffusions FD1, FD2, and FD3 are all reset to the pixel voltage V_PIX.

[0071] Next, after the first time point t1 and before the second time point t2, the reset signal RESET transitions from a high level to a low level. That is, the reset signal RESET is disabled. As a result, the reset transistor RT is turned off. On the other hand, the first and second DCG control signals S_DCG1 and S_DCG2 remain at the high level. That is, the first and second DCG control signals S_DCG1 and S_DCG2 can remain in the enabled state. Because the first and second DCG control signals S_DCG1 and S_DCG2 maintain the high level, the first and second DCG transistors DCG1 and DCG2 remain in the turned-on state, and as a result, the first to third floating diffusions FD1, FD2, and FD3 can remain electrically connected.

[0072] After the reset transistor RT is turned off and before the second time point t2, the selection signal SEL transitions from the L level to the H level. That is, the selection signal SEL is enabled. As a result, the first to third selection transistors ST1, ST2, and ST3 are turned on. The first source follower transistor SF1 outputs the charge level of the first floating diffusion FD1 as the first output voltage V_OUT1 using the pixel voltage V_PIX. In this case, the first output voltage V_OUT1 may be the reset voltage V_RST. The second and third source follower transistors SF2 and SF3 output the charge levels of the second and third floating diffusions FD2 and FD3, respectively, as the second and third output voltages V_OUT2 and V_OUT3 using the pixel voltage V_PIX. In this case, since the first and second DCG transistors DCG1 and DCG2 remain turned on, the charge levels of the first to third floating diffusions FD1, FD2, and FD3 are all the same. In other words, the second and third output voltages V_OUT2 and V_OUT3 can also be the reset voltage V_RST.

[0073] Next, at the second time point t2, the transfer gate signal S_TG transitions from the low level to the high level. That is, the transfer gate signal S_TG is enabled. Therefore, the transfer gate TG is turned on. Meanwhile, the first and second DCG control signals S_DCG1 and S_DCG2 remain at the high level. That is, the first and second DCG control signals S_DCG1 and S_DCG2 can remain in the enabled state. Because the first and second DCG control signals S_DCG1 and S_DCG2 maintain the high level, the first and second DCG transistors DCG1 and DCG2 remain in the turned-on state, and therefore the first to third floating diffusions FD1, FD2, and FD3 can remain electrically connected. Consequently, when the transfer gate TG is turned on, the charge stored in the photoelectric element PD is transferred to the first to third floating diffusions FD1, FD2, and FD3. In other words, the charge levels of each floating diffusion FD1, FD2, and FD3 increase.

[0074] Prior to the second time point t2, the photoelectric element PD stores the charge it generated by sensing an external image (or light). Thereafter, at the second time point t2, the transfer gate control signal S_TG transitions from the L level to the H level, causing charge to move from the photoelectric element PD to the first or second floating diffusion elements FD1, FD2, and FD3, which have relatively lower charge potentials. In other words, the charge level of the photoelectric element PD decreases.

[0075] Since the first to third floating diffusions FD1, FD2, and FD3 may each have different capacitances, the degree to which the charge levels of the floating diffusions FD1, FD2, and FD3 increase may also differ.

[0076] At the third time point t3, the transfer gate signal S_TG transitions from a high level to a low level. That is, the transfer gate signal S_TG is disabled. Therefore, the transfer gate TG is turned off. Also at the third time point t3, the first and second DCG control signals S_DCG1 and S_DCG2 transition from high levels to low levels. That is, the first and second DCG control signals S_DCG1 and S_DCG2 are disabled. Therefore, the first and second DCG transistors DCG1 and DCG2 are turned off, and the first to third floating diffusions are electrically isolated, respectively.

[0077] After the third time point t3, the selection signal SEL transitions from L level to H level. That is, the selection signal SEL is enabled. As a result, the first to third selection transistors ST1, ST2, and ST3 are turned on. On the other hand, the transfer gate signal S_TG and the first and second DCG control signals S_DCG1 and S_DCG2 remain at L level. That is, the transfer gate signal S_TG and the first and second DCG control signals S_DCG1 and S_DCG2 can remain in the disabled state. By maintaining the L level of the transfer gate signal S_TG and the first and second DCG control signals S_DCG1 and S_DCG2, the transfer gate TG and the first and second DCG transistors DCG1 and DCG2 can remain in the turned-off state. As a result, the photoelectric element PD and the first to third floating diffusion elements FD1, FD2, and FD3 can each remain electrically isolated.

[0078] The first source follower transistor SF1 outputs the charge level of the first floating diffusion FD1 as the first output voltage V_OUT1 using the pixel voltage V_PIX. In this case, the first output voltage V_OUT1 may be the first signal voltage V_S1. The second source follower transistor SF2 outputs the charge level of the second floating diffusion FD2 as the second output voltage V_OUT2 using the pixel voltage V_PIX. The third source follower transistor SF3 outputs the charge level of the third floating diffusion FD3 as the third output voltage V_OUT3 using the pixel voltage V_PIX. In this case, since the first and second DCG transistors DCG1 and DCG2 remain in the turned-off state, their respective output voltages V_OUT1, V_OUT2, and V_OUT3 may all be different depending on the difference in capacitance of each floating diffusion FD1, FD2, and FD3 or the control of charge transfer between the first and second DCG transistors DCG1 and DCG2. In other words, the method of converting the floating diffusion charge into an output voltage may differ for each pixel circuit. In some embodiments, the method by which the first pixel circuit 121 generates the first output voltage V_OUT1 may be a high-conversion method, and the method by which the second pixel circuit 122 generates the second output voltage V_OUT2 may be a low-conversion method. The method by which the third pixel circuit 123 generates the third output voltage V_OUT3 may be any other method.

[0079] The first to third output voltages V_OUT1, V_OUT2, and V_OUT3 outputted through the process described above are converted into first to third digital signals, respectively, via the first to third analog-to-digital converters ADC1, ADC2, and ADC3. Each analog-to-digital converter ADC1, ADC2, and ADC3 compares the levels of the reset voltage V_RST and the respective signal voltages V_S1, V_S2, and V_S3 using the CDS method and generates a digital signal based on the level difference (DV1, DV2, and DV3 in Figure 17b). In other words, by electrically isolating the first to third floating diffusions FD1, FD2, and FD3, and simultaneously sensing the voltage of each floating diffusion using the first to third pixel circuits 121, 122, and 123, it is possible to simultaneously output the output voltages V_OUT1, V_OUT2, and V_OUT3, which are different from each other.

[0080] Figure 18 is a diagram illustrating the stacked structure of the image sensing device shown in Figure 17a.

[0081] Referring to Figure 18, the image sensing device is formed in a stacked structure including a first plate P1, a second plate P2, and a third plate P3. Each of the plates P1, P2, and P3 is formed parallel to the others. Specifically, the second plate P2 is formed on top of the first plate P1 and parallel to the first plate P1, and the third plate P3 is formed between the first plate P1 and the second plate P2 and parallel to the first and second plates P1 and P2. The first plate P1 may include a pixel array area PA and a pixel periphery area PS. The pixel array 100 is located in the pixel array area PA. The logic circuit 200 may be located in the pixel periphery area PS, or in the second plate P2 or the third plate P3. The first analog-to-digital converter 510 is located on the second plate P2. The second and third analog-to-digital converters 520 and 530 are located on the third plate P3.

[0082] The third plate P3 may include a first area P3_1 and a second area P3_2. The second area P3_2 is formed physically separate from the first area P3_1. In this case, the second analog-to-digital converter 520 is located in the first area P3_1, and the third analog-to-digital converter 530 is located in the second area P3_2.

[0083] Figure 19 illustrates the stacked structure of an image sensing device according to several other embodiments of the present invention. The following explanation will focus on the differences from Figure 18.

[0084] Referring to Figure 19, the second plate P2 may include a first area P2_1 and a second area P2_2. The second area P2_2 is formed physically separate from the first area P2_1. In this case, the first analog-to-digital converter 510 is located in the first area P2_1, and the second analog-to-digital converter 520 is located in the second area P2_2. The third analog-to-digital converter 530 is located in the third plate P3.

[0085] Figure 20 illustrates the stacked structure of an image sensing device according to several other embodiments of the present invention. The following explanation will focus on the differences from Figure 18.

[0086] The first analog-to-digital converter 510 is located in the pixel peripheral area PS of the first plate P1. The logic circuit 200 may be located in the pixel peripheral area PS or on the second plate P2.

[0087] Figure 21 is a diagram illustrating the stacked structure of an image sensing device according to several other embodiments of the present invention. The following explanation will focus on the differences from Figure 19.

[0088] The first analog-to-digital converter 510 is located in the pixel peripheral area PS of the first plate P1. The logic circuit 200 may be located in the pixel peripheral area PS or on the third plate P3.

[0089] Figure 22 illustrates the stacked structure of an image sensing device according to several other embodiments of the present invention. The following explanation will focus on the differences from Figure 19.

[0090] The first analog-to-digital converter 510 is located in the pixel peripheral area PS of the first plate P1. The second analog-to-digital converter 520 is located on the second plate P2. The third analog-to-digital converter 530 is located on the third plate P3. The logic circuit 200 may be located in the pixel peripheral area PS, or on the second plate P2 or the third plate P3.

[0091] Figure 23 is an illustrative block diagram of an image sensing device according to several other embodiments of the present invention. The differences from Figure 1 will be explained below.

[0092] Referring to Figure 23, the image sensing device may include a pixel array 100, a logic circuit 200, an analog-to-digital converter circuit 600, and a memory 400. The pixel array 100 may include multiple pixels 130. The analog-to-digital converter circuit 600 may include multiple analog-to-digital converters 610, 620.

[0093] Figure 24 is a circuit diagram illustrating the structure of the pixels included in the pixel array of Figure 23. The following explanation will focus on the differences between this diagram and Figures 3 and 17a.

[0094] Referring to Figure 24, pixel 130 may include a photoelectric element PD, a reset transistor RT that resets the voltage levels of the first to third floating diffusion elements FD1, FD2, and FD3 to the reset level V_RST, a transfer gate TG that transfers the charge generated by the photoelectric element PD to the first to third floating diffusion elements FD1, FD2, and FD3, a first DCG transistor DCG1 that connects the first floating diffusion element FD1 and the second floating diffusion element FD2, a second DCG transistor DCG2 that connects the second floating diffusion element FD2 and the third floating diffusion element FD3, and first to third pixel circuits 131, 132, and 133. The first to third pixel circuits 131, 132, and 133 are the same as the first to third pixel circuits 121, 122, and 123 in Figure 17a.

[0095] The first output voltage V_OUT1 output at the output terminal of the first pixel circuit 131 is supplied to the first analog-to-digital converter 610. The second and third output voltages V_OUT2 and V_OUT3 output at the output terminals of the second and third pixel circuits 132 and 133 are supplied to the second analog-to-digital converter 620.

[0096] The operation in Figure 24 is the same as the operation in Figure 3, which was explained with reference to Figures 4 to 10. That is, by electrically isolating the first to third floating diffusions FD1, FD2, and FD3, and simultaneously sensing the voltage of each floating diffusion using the first to third pixel circuits 131, 132, and 133, it is possible to simultaneously output different output voltages V_OUT1, V_OUT2, and V_OUT3.

[0097] Figure 25 is a diagram illustrating a stacked structure of an image sensing device according to several other embodiments of the present invention. The stacked structure in Figure 25 is similar to the stacked structure of the image sensing device in Figure 15.

[0098] Referring to Figure 25, the second plate P2 may include a first area P2_1 and a second area P2_2. The second area P2_2 is formed physically separate from the first area P2_1. In this case, the first analog-to-digital converter 610 is located in the first area P2_1, and the second analog-to-digital converter 620 is located in the second area P2_2. The logic circuit 200 may be located in the pixel peripheral area PS, or it may be located in the third plate P3.

[0099] Figure 26 is a diagram illustrating a stacked structure of an image sensing device according to several other embodiments of the present invention. The stacked structure in Figure 26 is similar to the stacked structure of the image sensing device in Figure 14.

[0100] Referring to Figure 26, the third plate P3 may include a first area P3_1 and a second area P3_2. The second area P3_2 is formed physically separate from the first area P3_1. In this case, the first analog-to-digital converter 610 is located in the first area P3_1, and the second analog-to-digital converter 620 is located in the second area P3_2. The logic circuit 200 may be located in the pixel peripheral area PS or in the second plate P2.

[0101] Figure 27 is a diagram illustrating a stacked structure of an image sensing device according to several other embodiments of the present invention. The stacked structure in Figure 27 is similar to the stacked structure of the image sensing device in Figure 22.

[0102] Referring to Figure 27, the first analog-to-digital converter 610 is located in the pixel peripheral area PS of the first plate P1. The second analog-to-digital converter 620 is located on the second plate P2. The logic circuit 200 may be located in the pixel peripheral area PS, or it may be located on the third plate P3.

[0103] Figure 28 is a diagram illustrating a stacked structure of an image sensing device according to several other embodiments of the present invention. The stacked structure in Figure 28 is similar to the stacked structure of the image sensing device in Figure 27.

[0104] Referring to Figure 28, the first analog-to-digital converter 610 is located in the pixel peripheral area PS of the first plate P1. The second analog-to-digital converter 620 is located on the third plate P3. The logic circuit 200 may be located in the pixel peripheral area PS or on the second plate P2.

[0105] Figures 29 and 30 are block diagrams of an electronic device including a multi-camera module. Figure 31 is a detailed block diagram of the camera module shown in Figures 29 and 30. Hereafter, the image sensing device 1140 is the same as the image sensing device 1 shown in Figure 1, the image sensing device 2 shown in Figure 16, and the image sensing device 3 shown in Figure 23.

[0106] Referring to Figure 29, the electronic device 1000 may include a camera module group 1100, an application processor 1200, a PMIC 1300, and an external memory 1400.

[0107] The camera module group 1100 may include multiple camera modules 1100a, 1100b, and 1100c. Although the drawings show an embodiment in which three camera modules 1100a, 1100b, and 1100c are arranged, the embodiment is not limited thereto. In some embodiments, the camera module group 1100 can be modified to include only two camera modules or to include n camera modules (where n is a natural number greater than or equal to 4).

[0108] The detailed configuration of camera module 1100b will be described in more detail below with reference to Figure 31, but the following description can also be applied to other camera modules 1100a and 1100b depending on the embodiment.

[0109] Referring to Figure 31, the camera module 1100b may include a prism 1105, an optical path folding element (OPFE, 1110), an actuator 1130, an image sensing device 1140, and a storage unit 1150.

[0110] The prism 1105 includes a reflective surface 1107 made of light-reflecting material and deforms the path of light L incident from the outside.

[0111] In some embodiments, the prism 1105 changes the path of light L incident in a first direction X to a second direction Y perpendicular to the first direction X. The prism 1105 also rotates the reflective surface 1107 of the light-reflecting material in direction A around the central axis 1106, or rotates the central axis 1106 in direction B, thereby changing the path of light L incident in the first direction X to the perpendicular second direction Y. In this case, the OPFE 1110 also moves in a third direction Z perpendicular to the first direction X and the second direction Y.

[0112] In some embodiments, as shown in the figures, the maximum rotation angle of the prism 1105 in the A direction may be 15 degrees or less in the positive (+) A direction and greater than 15 degrees in the negative (-) A direction, but the embodiments are not limited thereto.

[0113] In some embodiments, the prism 1105 moves approximately 20 degrees in the positive (+) or negative (-)B direction, or between 10 and 20 degrees, or between 15 and 20 degrees, where the angle of movement can be the same angle in the positive (+) or negative (-)B direction, or to approximately similar angles within a range of approximately 1 degree.

[0114] In some embodiments, the prism 1105 can move the reflective surface 1106 of the light-reflecting material in a third direction (e.g., the Z direction) parallel to the extension of the central axis 1106.

[0115] In some embodiments, the camera module 1100b is composed of two or more prisms, which can change the path of light L incident in a first direction X to a second direction Y perpendicular to the first direction X, then back to the first direction X or a third direction Z, and then back to the second direction Y, and so on.

[0116] The OPFE1110 may include, for example, m (where m is a natural number) groups of optical lenses. The m lenses move in a second direction Y to change the optical zoom ratio of the camera module 1100b. For example, if the basic optical zoom ratio of the camera module 1100b is Z, then moving the m optical lenses included in the OPFE1110 can change the optical zoom ratio of the camera module 1100b to 3Z, 5Z, or 5Z or higher.

[0117] The actuator 1130 moves the OPFE 1110 or optical lens (hereinafter referred to as the optical lens) to a specific position. For example, the actuator 1130 adjusts the position of the optical lens so that the image sensor 1142 is positioned at the focal length of the optical lens for accurate sensing.

[0118] The image sensing device 1140 may include an image sensor 1142, control logic 1144, and memory 1146. The image sensor 1142 senses an image to be sensed using light L provided through an optical lens. The control logic 1144 controls the overall operation of the camera module 1100b and processes the sensed image. For example, the control logic 1144 can control the operation of the camera module 1100b in response to control signals provided via the control signal line CSLb and extract image data corresponding to a specific image (e.g., a person's face, arms, legs, etc. in the image) from the sensed image.

[0119] In some embodiments, the control logic 1144 can perform image processing such as encoding and noise reduction on the sensed image.

[0120] Memory 1146 stores information necessary for the operation of the camera module 1100b, such as calibration data 1147. Calibration data 1147 is information necessary for the camera module 1100b to generate image data using light L supplied from an external source, and may include, for example, information on the degree of rotation, information on the focal length, and information on the optical axis. If the camera module 1100b is implemented as a multi-state camera where the focal length changes depending on the position of the optical lens, the calibration data 1147 may include the focal length values ​​for each position (or state) of the optical lens and information related to autofocusing.

[0121] The storage unit 1150 stores image data sensed via the image sensor 1142. The storage unit 1150 is located outside the image sensing device 1140 and can be implemented in a stacked configuration with the sensor chips that make up the image sensing device 1140. In some embodiments, the image sensor 1142 is composed of a first plate, and the control logic 1144, storage unit 1150, and memory 1146 are composed of a first or second plate, and can be implemented in a configuration in which multiple plates are stacked. The stacked structure of the image sensing device 1140 is as described above.

[0122] In some embodiments, the storage unit 1150 is implemented as an EEPROM (Electrically Erasable Programmable Read-Only Memory), but the embodiments are not limited thereto. In some embodiments, the image sensor 1142 is composed of a pixel array, and the control logic 1144 may include an analog-to-digital converter and an image signal processing unit for processing the sensed image.

[0123] Referring to both Figure 29 and Figure 31, in some embodiments, each of the multiple camera modules 1100a, 1100b, and 1100c may include an actuator 1130. Therefore, each of the multiple camera modules 1100a, 1100b, and 1100c may contain the same or different calibration data 1147 corresponding to the operation of the actuator 1130 contained within it.

[0124] In some embodiments, one of the multiple camera modules 1100a, 1100b, 1100c (e.g., 1100b) may be a folded lens camera module including the prism 1105 and OPFE 1110 described above, while the remaining camera modules (e.g., 1100a, 1100c) may be vertical camera modules that do not include the prism 1105 and OPFE 1110, but are not limited thereto.

[0125] In some embodiments, one of the multiple camera modules 1100a, 1100b, 1100c (e.g., 1100c) may be a vertical depth camera that extracts depth information using IR (Infrared Ray). In this case, the application processor 1200 merges the image data provided by such a depth camera with the image data provided by the other camera modules (e.g., 1100a or 1100b) to generate a 3D depth image.

[0126] In some embodiments, at least two camera modules (e.g., 1100a, 1100b) of a plurality of camera modules 1100a, 1100b, 1100c may have different fields of view (angles of view). In this case, for example, the optical lenses of at least two camera modules (e.g., 1100a, 1100b) of the plurality of camera modules 1100a, 1100b, 1100c may be different from each other, but are not limited thereto.

[0127] Furthermore, in some embodiments, the field of view of each of the multiple camera modules 1100a, 1100b, and 1100c may differ from one another. For example, camera module 1100a may be an ultrawide camera, camera module 1100b may be a wide camera, and camera module 1100c may be a telephoto camera, but this is not limited to that. In this case, the optical lenses included in each of the multiple camera modules 1100a, 1100b, and 1100c may also differ from one another, but this is not limited to that.

[0128] In some embodiments, the multiple camera modules 1100a, 1100b, and 1100c are physically separated from each other. That is, instead of the sensing area of ​​a single image sensor 1142 being divided and used by the multiple camera modules 1100a, 1100b, and 1100c, an independent image sensor 1142 is placed inside each of the multiple camera modules 1100a, 1100b, and 1100c.

[0129] Referring again to Figure 29, the application processor 1200 may include an image processing unit 1210, a memory controller 1220, and internal memory 1230. The application processor 1200 can be implemented by separating it from multiple camera modules 1100a, 1100b, and 1100c, for example, on a separate semiconductor chip.

[0130] The image processing device 1210 may include a plurality of sub-image processors 1212a, 1212b, 1212c, an image generator 1214, and a camera module controller 1216.

[0131] The image processing device 1210 may include multiple sub-image processors 1212a, 1212b, and 1212c in a number corresponding to the number of camera modules 1100a, 1100b, and 1100c.

[0132] Image data generated from camera module 1100a is provided to sub-image processor 1212a via image signal line ISLa, image data generated from camera module 1100b is provided to sub-image processor 1212b via image signal line ISLb, and image data generated from camera module 1100c is provided to sub-image processor 1212c via image signal line ISLc. Such transfer of image data is performed, for example, using a Camera Serial Interface (CSI) based on MIPI (Mobile Industry Processor Interface), but is not limited to this.

[0133] On the other hand, in some embodiments, a single sub-image processor may be arranged to support multiple camera modules. For example, instead of sub-image processors 1212a and 1212c being implemented separately as shown in the figure, they may be integrated into a single sub-image processor, and the image data provided from camera modules 1100a and 1100c are selected by a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor. In this case, sub-image processor 1212b is not integrated and receives image data from camera module 1100b.

[0134] In some embodiments, image data generated from camera module 1100a is provided to sub-image processor 1212a via image signal line ISLa, image data generated from camera module 1100b is provided to sub-image processor 1212b via image signal line ISLb, and image data generated from camera module 1100c is provided to sub-image processor 1212c via image signal line ISLc. The image data processed by sub-image processor 1212b is then directly provided to image generator 1214, but the image data processed by sub-image processor 1212a and the image data processed by sub-image processor 1212c are selected by a selection element (e.g., a multiplexer) before being provided to image generator 1214.

[0135] Each of the sub-image processors 1212a, 1212b, and 1212c performs image processing on the image data provided by the camera modules 1100a, 1100b, and 1100c, including bad pixel correction, 3A adjustment (auto-focus correction, auto-white balance, auto-exposure), noise reduction, sharpening, gamma control, and remosaic.

[0136] In some embodiments, remosaic signal processing can be performed in the respective camera modules 1100a, 1100b, and 1100c before being provided to the sub-image processors 1212a, 1212b, and 1212c.

[0137] Image data processed by each sub-image processor 1212a, 1212b, and 1212c is provided to the image generator 1214. The image generator 1214 generates an output image using the image data provided by each sub-image processor 1212a, 1212b, and 1212c, based on generating information or a mode signal.

[0138] Specifically, the image generator 1214 merges at least a portion of the image data generated by the image processors 1212a, 1212b, and 1212c based on image generation information or mode signals to generate an output image. Alternatively, the image generator 1214 selects one of the image data generated by the image processors 1212a, 1212b, and 1212c based on image generation information or mode signals to generate an output image.

[0139] In some embodiments, the image generation information may include a zoom signal (or zoom factor). Also, in some embodiments, the mode signal may be a signal based on a mode selected by the user, for example.

[0140] If the image generation information is a zoom signal (zoom factor), and each camera module 1100a, 1100b, and 1100c has a different field of view (field of view angle), the image generator 1214 will operate differently depending on the type of zoom signal. For example, if the zoom signal is the first signal, the image generator 1214 will generate the output image using the image data output from sub-image processor 1212a and the image data output from sub-image processor 1212b. If the zoom signal is a second signal different from the first signal, the image generator 1214 will generate the output image using the image data output from sub-image processor 1212c and the image data output from sub-image processor 1212b. If the zoom signal is a third signal different from the first and second signals, the image generator 1214 does not perform such image data merging, but instead selects one of the image data output from each of the sub-image processors 1212a, 1212b, and 1212c to generate the output image. However, the embodiment is not limited to this, and the method of processing the image data can be modified and implemented in any way as needed.

[0141] Referring to Figure 30, in some embodiments, the image processing device 1210 may further include a selection unit 1213 that selects the outputs of sub-image processors 1212a, 1212b, and 1212c and transmits them to the image generator 1214.

[0142] In this case, the selection unit 1213 performs different operations depending on the zoom signal or zoom factor. For example, if the zoom signal is the fourth signal (for example, the zoom magnification is the first magnification), the selection unit 1213 selects one of the outputs of the sub-image processors 1212a, 1212b, and 1212c and transmits it to the image generator 1214.

[0143] Furthermore, if the zoom signal is a fifth signal different from the fourth signal (for example, the zoom magnification is the second magnification), the selection unit 1213 sequentially transmits p outputs (where p is a natural number greater than or equal to 2) from the outputs of sub-image processors 1212a, 1212b, and 1212c to the image generator 1214. For example, the selection unit 1213 sequentially transmits the outputs of sub-image processor 1212b and sub-image processor 1212c to the image generator 1214. Also, the selection unit 1213 sequentially transmits the outputs of sub-image processor 1212a and sub-image processor 1212b to the image generator 1214. The image generator 1214 merges the sequentially provided p outputs to generate a single output image.

[0144] Here, image processing such as demosaicing, downscaling to video / preview resolution size, gamma correction, and HDR (High Dynamic Range) processing is performed in advance by sub-image processors 1212a, 1212b, and 1212c, and then the processed image data is transmitted to the image generator 1214. Therefore, even if the processed image data is provided to the image generator 1214 via the selection unit 1213 on a single signal line, the image merging operation of the image generator 1214 can be performed at high speed.

[0145] In some embodiments, the image generator 1214 can receive multiple image data with different exposure times from at least one of the multiple sub-image processors 1212a, 1212b, and 1212c, and generate merged image data with an increased dynamic range by performing HDR (high dynamic range) processing on the multiple image data.

[0146] The camera module controller 1216 provides control signals to each of the camera modules 1100a, 1100b, and 1100c. The control signals generated by the camera module controller 1216 are provided to the corresponding camera modules 1100a, 1100b, and 1100c via the mutually separated control signal lines CSLa, CSLb, and CSLc.

[0147] One of the multiple camera modules 1100a, 1100b, and 1100c is designated as the master camera (e.g., 1100b) by image generation information including a zoom signal or a mode signal, while the remaining camera modules (e.g., 1100a and 1100c) are designated as slave cameras. This information is included in the control signals and provided to the corresponding camera modules 1100a, 1100b, and 1100c via the mutually isolated control signal lines CSLa, CSLb, and CSLc.

[0148] The camera modules operating as master and slave are changed depending on the zoom factor or operating mode signal. For example, if the field of view of camera module 1100a is wider than that of camera module 1100b, and the zoom factor indicates a lower zoom magnification, camera module 1100a operates as the master and camera module 1100b operates as the slave. Conversely, if the zoom factor indicates a higher zoom magnification, camera module 1100b operates as the master and camera module 1100a operates as the slave.

[0149] In some embodiments, the control signals provided from the camera module controller 1216 to each of the camera modules 1100a, 1100b, and 1100c may include a sync enable signal. For example, if camera module 1100b is the master camera and camera modules 1100a and 1100c are slave cameras, the camera module controller 1216 transmits a sync enable signal to camera module 1100b. Upon receiving such a sync enable signal, camera module 1100b generates a sync signal based on the provided sync enable signal and provides the generated sync signal to camera modules 1100a and 1100c via the sync signal line SSL. Camera modules 1100b and 1100a and 1100c transmit image data to the application processor 1200 in synchronization with such sync signals.

[0150] In some embodiments, the control signals provided from the camera module controller 1216 to multiple camera modules 1100a, 1100b, and 1100c may include mode information via mode signals. Based on such mode information, the multiple camera modules 1100a, 1100b, and 1100c can operate in a first operating mode and a second operating mode in relation to the sensing speed.

[0151] Multiple camera modules 1100a, 1100b, and 1100c generate an image signal at a first speed (for example, an image signal at a first frame rate) in a first operating mode, encode it at a second speed higher than the first speed (for example, encode an image signal at a second frame rate higher than the first frame rate), and transmit the encoded image signal to the application processor 1200. At this time, the second speed may be 30 times or less the first speed.

[0152] The application processor 1200 stores the received image signal, in other words, the encoded image signal, in an internal memory 1230 or an external storage 1400. Subsequently, it reads the encoded image signal from the memory 1230 or storage 1400, decodes it, and displays the image data generated based on the decoded image signal. For example, one of the multiple sub-image processors 1212a, 1212b, and 1212c of the image processing device 1210 performs decoding and also performs image processing on the decoded image signal.

[0153] Multiple camera modules 1100a, 1100b, and 1100c generate image signals at a third speed lower than the first speed in a second operating mode (for example, generating image signals at a third frame rate lower than the first frame rate) and transmit the image signals to the application processor 1200. The image signals provided to the application processor 1200 may be unencoded signals. The application processor 1200 performs image processing on the received image signals or stores the image signals in memory 1230 or storage 1400.

[0154] The PMIC1300 supplies power, such as power supply voltage, to each of the multiple camera modules 1100a, 1100b, and 1100c. For example, under the control of the application processor 1200, the PMIC1300 supplies first power to camera module 1100a via power signal line PSLa, second power to camera module 1100b via power signal line PSLb, and third power to camera module 1100c via power signal line PSLc.

[0155] The PMIC 1300 responds to the power control signal PCON from the application processor 1200 to generate power corresponding to each of the multiple camera modules 1100a, 1100b, and 1100c, and also adjusts the power level. The power control signal PCON may include power adjustment signals for each operating mode of the multiple camera modules 1100a, 1100b, and 1100c. For example, the operating mode may include a low power mode, in which case the power control signal PCON may include information about the camera modules operating in low power mode and the power levels to be set. The power levels provided to each of the multiple camera modules 1100a, 1100b, and 1100c may be the same or different from each other. Furthermore, the power levels can be changed dynamically.

[0156] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the embodiments described above. It can be manufactured in a variety of different forms, and a person with ordinary skill in the art to which the present invention belongs will understand that it can be implemented in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the above-described embodiment is illustrative in all respects and not limiting. [Explanation of Symbols]

[0157] 1: Image sensing device 100: Pixel Array 111: First Pixel Circuit 112: Second Pixel Circuit 200: Logic circuits, 300: Analog-to-Digital Converter Circuit 310: First Analog-to-Digital Converter 320: Second Analog-to-Digital Converter 400: Memory PD: Photoelectric element FD1: First Floating Diffusion FD2: Second Floating Diffusion TG: TransferGate RT: Reset transistor DCG: DCG Transistor

Claims

1. An image sensing device, wherein the image sensing device is A photoelectric element that generates an electric charge in response to light, A first floating diffusion in which the charge generated by the photoelectric element is stored, A second floating diffusion in which the charge generated by the aforementioned photoelectric element is stored, A third floating diffusion in which the charge generated by the aforementioned photoelectric element is stored, A transfer gate, one end of which is connected to the photoelectric element and the other end of which is connected to the first floating diffusion, A reset transistor directly connected to the first floating diffusion and not directly connected to the second floating diffusion, which resets the voltages of the first and second floating diffusion based on a reset signal, A first DCG (Dual Conversion Gain) transistor having one end directly connected to the first floating diffusion and the other end directly connected to the second floating diffusion, wherein the first DCG transistor connects the first floating diffusion and the second floating diffusion based on the first DCG control signal, A second DCG transistor having one end directly connected to the second floating diffusion and the other end directly connected to the third floating diffusion, the second DCG transistor connecting the second floating diffusion and the third floating diffusion based on the second DCG control signal, A first pixel circuit that generates a first output voltage based on the voltage of the first floating diffusion, A second pixel circuit that generates a second output voltage based on the voltage of the second floating diffusion, A third pixel circuit that generates a third output voltage based on the voltage of the third floating diffusion, A first analog-to-digital converter that receives the first output voltage and converts the first output voltage into a first digital signal, A second analog-digital converter is provided with the first analog-digital converter and is arranged separately from the first analog-digital converter, and receives the second output voltage and converts the second output voltage into a second digital signal. The system includes a third analog-digital converter, which is positioned separately from the first and second analog-digital converters and receives the third output voltage to convert the third output voltage into a third digital signal, The first pixel circuit includes a first source follower transistor, and the second pixel circuit includes a second source follower transistor. The gate terminal of the first source follower transistor is connected between the first floating diffusion and the reset transistor, and the gate terminal of the second source follower transistor is connected to the second floating diffusion and the first DCG transistor. The second floating diffusion is not directly connected to any of the transfer gates. An image sensing device in which the first analog-to-digital converter is arranged on a first plate, and the second analog-to-digital converter is arranged on a second plate different from the first plate.

2. The image sensing apparatus according to claim 1, wherein the first floating diffusion and the second floating diffusion have different capacitances.

3. An image sensing device, wherein the image sensing device is A first pixel circuit that generates a first output voltage in a high-conversion manner based on the charge generated by a single photoelectric element and outputs it, A first analog-to-digital converter that receives the first output voltage and converts the first output voltage into a first digital signal, A second pixel circuit that generates a second output voltage different from the first output voltage in a low-conversion manner based on the charge generated by the aforementioned single photoelectric element and outputs it, A third pixel circuit that generates and outputs a third output voltage different from the first and second output voltages in a manner different from the high-conversion and low-conversion methods, based on the charge provided by the aforementioned single photoelectric element, The system includes a second analog-to-digital converter that receives the second output voltage or the third output voltage and converts the second output voltage or the third output voltage into a second digital signal, The first analog-to-digital converter is placed on the first plate, An image sensing device in which the second analog-to-digital converter is located on a second plate different from the first plate.

4. Based on the first DCG control signal, the first floating diffusion and the second floating diffusion are electrically connected. While maintaining the aforementioned connection, the voltage levels of the first floating diffusion and the second floating diffusion are simultaneously reset to the reset level. After the reset, while maintaining the connection, the voltage level of the first floating diffusion is transitioned from the reset level to the first signal level based on the charge generated from the photoelectric element, and the voltage level of the second floating diffusion is transitioned from the reset level to a second signal level different from the first signal level based on the charge generated from the photoelectric element. Based on the first DCG control signal, the first floating diffusion and the second floating diffusion are electrically isolated. A first digital signal is generated based on the level difference between the reset level and the first signal level of the first floating diffusion. A method for operating an image sensing device, comprising generating a second digital signal based on the level difference between the reset level and the second signal level of the second floating diffusion.

5. The method for operating an image sensing apparatus according to claim 4, wherein the first floating diffusion and the second floating diffusion are separated based on the first DCG control signal before the first and second digital signals are generated.

6. Based on the second DCG control signal, the second floating diffusion and the third floating diffusion are linked. The voltage level of the third floating diffusion is reset to the reset level. Based on the charge generated from the photoelectric element, the voltage level of the third floating diffusion is transitioned from the reset level to the third signal level. Based on the second DCG control signal, the second floating diffusion and the third floating diffusion are separated. A method for operating an image sensing apparatus according to claim 4 or 5, further comprising generating a third digital signal based on the level difference between the reset level and the third signal level of the third floating diffusion.

Images