Photoelectric converter

Abstract

To provide a photoelectric conversion device that can effectively suppress generation of aliases due to electric charges leaking into a photoelectric conversion unit of a pixel.SOLUTION: A photoelectric conversion device has: pixels that each have an amplification transistor generating a signal according to electric charges generated in a photoelectric conversion unit, and a selection transistor controlling output of the signal; and output lines through which the signals are output from the pixels. The photoelectric conversion unit has a first semiconductor region of a first conductivity type for storing the electric charges, the selection transistor has a second semiconductor region of the first conductivity type to which the output line is connected, and the pixel further has a third semiconductor region of the first conductivity type that can discharge the electric charges. The second semiconductor region is adjacent to the first semiconductor region with a first element isolation structure therebetween, and is adjacent to the third semiconductor region with a second element isolation structure therebetween. The shortest distance between the first semiconductor region and the second semiconductor region with the first element isolation structure therebetween is larger than the shortest distance between the second semiconductor region and the third semiconductor region with the second element isolation structure therebetween.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device.

Background Art

[0002] In recent years, CMOS image sensors suitable for high-speed reading have been widely used in imaging systems such as digital still cameras and digital video cameras. Patent Document 1 describes a CMOS image sensor configured to suppress a phenomenon in which charges leak from a saturated photodiode into an adjacent photodiode, so-called blooming, by arranging charge discharge regions between pixels.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, the charges leaking into the photodiode are not limited to the charges overflowing from the photodiode of an adjacent pixel, and charges overflowing from other parts may also leak into the photodiode. With the technique described in Patent Document 1, it was not always possible to sufficiently suppress the charges leaking into the photodiode. An object of the present invention is to provide a photoelectric conversion device capable of effectively suppressing the generation of false signals caused by charges leaking into the photoelectric conversion part of a pixel.

Means for Solving the Problems

[0005] According to one disclosure of this specification, a photoelectric conversion device is provided, comprising: a pixel provided on a semiconductor substrate, having a photoelectric conversion unit; a floating diffusion unit to which charge generated in the photoelectric conversion unit is transferred; an amplifying transistor that generates a signal corresponding to the voltage of the floating diffusion unit; and a selection transistor that controls the output of the signal; and an output line from which the signal is output from the pixel, wherein the photoelectric conversion unit has a first semiconductor region of a first conductivity type for accumulating charge generated by photoelectric conversion; the selection transistor has a second semiconductor region of the first conductivity type constituting a node to which the output line is connected; and the pixel further has a third semiconductor region of the first conductivity type configured to discharge charge, wherein the second semiconductor region is adjacent to the first semiconductor region via a first element isolation structure and adjacent to the third semiconductor region via a second element isolation structure, and the shortest distance between the first semiconductor region and the second semiconductor region via the first element isolation structure is greater than the shortest distance between the second semiconductor region and the third semiconductor region via the second element isolation structure.

[0006] Furthermore, according to another disclosure of this specification, a pixel provided on a semiconductor substrate has a photoelectric conversion unit, a floating diffusion unit to which the charge generated in the photoelectric conversion unit is transferred, an amplifying transistor that generates a signal corresponding to the voltage of the floating diffusion unit, and a selection transistor that controls the output of the signal, and an output line from which the signal is output from the pixel, wherein the photoelectric conversion unit has a first semiconductor region of a first conductivity type for accumulating a charge of a first polarity generated by photoelectric conversion, and the selection transistor has a second semiconductor region of the first conductivity type that constitutes a node to which the output line is connected. The pixel further comprises a third semiconductor region of the first conductivity type configured to discharge the charge of the first polarity, the second semiconductor region is adjacent to the first semiconductor region via a first element isolation structure and adjacent to the third semiconductor region via a second element isolation structure, and the potential barrier of the first element isolation structure for the charge of the first polarity between the first semiconductor region and the second semiconductor region is higher than the potential barrier of the second element isolation structure for the charge of the first polarity between the second semiconductor region and the third semiconductor region. [Effects of the Invention]

[0007] According to the present invention, the generation of false signals caused by charge leakage into the photoelectric conversion section of a pixel can be effectively suppressed, and high-quality images can be obtained. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram showing the schematic configuration of a photoelectric conversion device according to a first embodiment of the present invention. [Figure 2] This is an equivalent circuit diagram showing an example of pixel configuration in a photoelectric conversion device according to the first embodiment of the present invention. [Figure 3] This is a timing diagram showing the operation of pixels in a photoelectric conversion device according to the first embodiment of the present invention. [Figure 4] These are a plan view and a cross-sectional view showing the pixel structure in a photoelectric conversion device according to the first embodiment of the present invention. [Figure 5]These are a plan view and a cross-sectional view showing the pixel structure in a photoelectric conversion device according to a second embodiment of the present invention. [Figure 6] These are a plan view and a cross-sectional view showing the pixel structure in a photoelectric conversion device according to a third embodiment of the present invention. [Figure 7] These are a plan view and a cross-sectional view showing the pixel structure in a photoelectric conversion device according to a fourth embodiment of the present invention. [Figure 8] These are a plan view and a cross-sectional view showing the pixel structure in a photoelectric conversion device according to the fifth embodiment of the present invention. [Figure 9] These are a plan view and a cross-sectional view showing the pixel structure in a photoelectric conversion device according to the sixth embodiment of the present invention. [Figure 10] These are a plan view and a cross-sectional view showing the pixel structure in a photoelectric conversion device according to the seventh embodiment of the present invention. [Figure 11] This is an equivalent circuit diagram showing an example of pixel configuration in a photoelectric conversion device according to the eighth embodiment of the present invention. [Figure 12] This is a plan view showing the structure of a pixel in a photoelectric conversion device according to the eighth embodiment of the present invention. [Figure 13] This is a cross-sectional view showing the structure of a pixel in a photoelectric conversion device according to the eighth embodiment of the present invention. [Figure 14] This is a block diagram showing the schematic configuration of an imaging system according to the ninth embodiment of the present invention. [Figure 15] This figure shows an example configuration of an imaging system and a mobile body according to the tenth embodiment of the present invention. [Figure 16] This is a block diagram showing the schematic configuration of a device according to the 11th embodiment of the present invention. [Modes for carrying out the invention]

[0009] [First Embodiment] The photoelectric conversion device according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 4. FIG. 1 is a block diagram showing a schematic configuration of the photoelectric conversion device according to the present embodiment. FIG. 2 is an equivalent circuit diagram showing a configuration example of pixels in the photoelectric conversion device according to the present embodiment. FIG. 3 is a timing diagram showing the operation of pixels in the photoelectric conversion device according to the present embodiment. FIG. 4 is a plan view and a cross-sectional view showing the structure of pixels in the photoelectric conversion device according to the present embodiment.

[0010] As shown in FIG. 1, the photoelectric conversion device according to the present embodiment includes a pixel region 10, a vertical scanning circuit 20, a readout circuit 30, a horizontal scanning circuit 40, an output circuit 50, and a control circuit 60.

[0011] The pixel region 10 is provided with a plurality of pixels 12 arranged in a matrix over a plurality of rows and a plurality of columns. Each pixel 12 includes a photoelectric conversion unit composed of a photoelectric conversion element such as a photodiode, and outputs a pixel signal according to the amount of incident light. The number of rows and columns of the pixel array arranged in the pixel region 10 is not particularly limited. In addition to the effective pixels that output pixel signals according to the amount of incident light, the pixel region 10 may also be provided with optical black pixels in which the photoelectric conversion unit is shielded from light, dummy pixels that do not output signals, and the like.

[0012] In each row of the pixel array arranged in the pixel region 10, a control line 14 is arranged extending in a first direction (the horizontal direction in FIG. 1). Each of the control lines 14 is connected to the pixels 12 arranged in the first direction, and forms a common signal line for these pixels 12. Each of the control lines 14 may include a plurality of signal lines. The control line 14 is connected to the vertical scanning circuit 20. The first direction in which the control line 14 extends is sometimes referred to as the row direction or the horizontal direction.

[0013] In each column of the pixel array arranged in the pixel region 10, output lines 16 are arranged extending in a second direction (vertical direction in FIG. 1) intersecting the first direction. Each of the output lines 16 is respectively connected to pixels 12 arranged in the second direction, and forms a common signal line for these pixels 12. Each of the output lines 16 may include a plurality of signal lines. The output lines 16 are connected to the readout circuit 30. Note that the second direction in which the output lines 16 extend may be referred to as the column direction or the vertical direction.

[0014] The vertical scanning circuit 20 has a function of generating a control signal for driving the pixels 12 in accordance with a control signal from the control circuit 60 and supplying it to the pixels 12 via the control lines 14. The vertical scanning circuit 20 may be configured using a shift register or an address decoder. The vertical scanning circuit 20 drives the pixels 12 arranged in the pixel region 10 in row units by the control signal supplied via the control lines 14. The signals read out from the pixels 12 in row units are input to the readout circuit 30 via the output lines 16 of each column.

[0015] The readout circuit 30 has a function of holding the pixel signals read out from the pixel region 10 and performing signal processing such as predetermined processing on the pixel signals, for example, correction processing by correlated double sampling, amplification processing, analog-to-digital conversion processing, etc. The readout circuit 30 has a signal holding circuit for holding the pixel signals output from the pixel region 10.

[0016] The horizontal scanning circuit 40 has a function of generating a control signal for sequentially transferring the pixel signals processed by the readout circuit 30 to the output circuit 50 column by column in accordance with a control signal from the control circuit 60 and supplying it to the readout circuit 30. The horizontal scanning circuit 40 may be configured using a shift register or an address decoder.

[0017] The output circuit 50 consists of a buffer amplifier, a differential amplifier, and the like, and has the function of performing predetermined signal processing on the pixel signals of the column selected by the horizontal scanning circuit 40, and outputting the processed pixel data to the outside of the photoelectric converter 100. Examples of signal processing performed by the output circuit 50 include correction processing by correlated double sampling and amplification processing.

[0018] The control circuit 60 has the function of supplying control signals to the vertical scanning circuit 20, the readout circuit 30, the horizontal scanning circuit 40, and the output circuit 50 to control their operation and timing. Some or all of the control signals supplied to the vertical scanning circuit 20, the readout circuit 30, the horizontal scanning circuit 40, and the output circuit 50 may be supplied from outside the photoelectric converter 100.

[0019] Next, an example of the pixel configuration in the photoelectric converter according to this embodiment will be explained using Figure 2. Figure 2 shows six pixels 12 selected from among the multiple pixels 12 that constitute the pixel region 10, arranged in a 3-row (n-th row to (n+2)-row) x 2-column (m-th column to (m+1)-column) block. Some of the symbols shown in Figure 2 have symbols representing row numbers or column numbers added in parentheses.

[0020] Each of the pixels 12 may be composed of a photoelectric conversion unit PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M4, and a selection transistor M5. Each of the pixels 12 may further have a capacitive addition transistor M3, as shown in Figure 2. Here, we will describe a pixel configuration including the capacitive addition transistor M3. The transfer transistor M1, reset transistor M2, capacitive addition transistor M3, amplification transistor M4, and selection transistor M5 may be composed of MOS transistors. Each of the pixels 12 may have a microlens and a color filter arranged in the optical path from the incident light to the photoelectric conversion unit PD. The microlens focuses the incident light to the photoelectric conversion unit PD. The color filter selectively transmits light of a predetermined color.

[0021] The photoelectric conversion unit PD may be, for example, a photodiode with its anode connected to the ground node and its cathode connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the capacitive addition transistor M3 and the gate of the amplification transistor M4. The connection nodes of the drain of the transfer transistor M1, the source of the capacitive addition transistor M3, and the gate of the amplification transistor M4 form a so-called stray diffusion unit FD. The capacitive component (stray diffusion capacitance) connected to the stray diffusion unit FD functions as a charge retention unit.

[0022] The drain of the capacitive transistor M3 is connected to the source of the reset transistor M2. In the case of a pixel configuration that does not include the capacitive transistor M3, the source of the reset transistor M2 is connected to the floating diffuser FD. The drains of the reset transistor M2 and the amplifier transistor M4 are connected to the power supply voltage node (voltage: Vdd). The source of the amplifier transistor M4 is connected to the drain of the selection transistor M5. The source of the selection transistor M5 is connected to output line 16. Note that the voltage supplied to the drain of the reset transistor M2 and the voltage supplied to the drain of the amplifier transistor M4 may be the same or different.

[0023] In the pixel configuration shown in Figure 2, each row of control lines 14 includes four signal lines connected to the gates of the transfer transistor M1, the capacitive transistor, the reset transistor M2, and the selection transistor M5. The signal line connected to the gate of the transfer transistor M1 is supplied with the control signal pTX from the vertical scanning circuit 20. The signal line connected to the gate of the reset transistor M2 is supplied with the control signal pRES from the vertical scanning circuit 20. The signal line connected to the gate of the capacitive transistor M3 is supplied with the control signal pFDinc from the vertical scanning circuit 20. The signal line connected to the gate of the selection transistor M5 is supplied with the control signal pSEL from the vertical scanning circuit 20. When each transistor is composed of an N-type MOS transistor, a High-level control signal supplied from the vertical scanning circuit 20 turns the corresponding transistor ON. Conversely, a Low-level control signal supplied from the vertical scanning circuit 20 turns the corresponding transistor OFF.

[0024] Furthermore, each column's output line 16 includes three signal lines 161, 162, and 163. These three signal lines 161, 162, and 163 are connected to different pixels 12 in the same column. For example, as shown in Figure 2, each pixel 12 in a column located in the nth row may be connected to the signal line 161 of the corresponding column. Each pixel 12 in a column located in the (n+1)th row may be connected to the signal line 162 of the corresponding column. Each pixel 12 in a column located in the (n+2)th row may be connected to the signal line 163 of the corresponding column. Pixels 12 in other rows are also connected to one of the signal lines 161, 162, or 163 of the corresponding column, similar to these pixels 12. Note that the number of signal lines constituting each column's output line 16 is not limited to three; it may be two or fewer, or four or more.

[0025] In this embodiment, the explanation assumes that electrons are used as the signal charge among the electron-hole pairs generated in the photoelectric conversion unit PD by light incidence. When electrons are used as the signal charge, each transistor constituting the pixel 12 may be composed of an N-type MOS transistor. However, the signal charge is not limited to electrons, and holes may also be used as the signal charge. When holes are used as the signal charge, the conductivity type of each transistor and semiconductor region will be the opposite conductivity type to that described in this embodiment. In this specification, if the first conductivity type is N-type, the second conductivity type is P-type, and if the first conductivity type is P-type, the second conductivity type is N-type. Also, if the charge of the first polarity is a negative charge (electron), the charge of the second polarity is a positive charge (hole), and if the charge of the first polarity is a positive charge (hole), the charge of the second polarity is a negative charge (electron).

[0026] Furthermore, the names of the source and drain of a MOS transistor may differ depending on the transistor's conductivity type and the function being considered. Some or all of the names of the source and drain used in this embodiment may also be referred to by their reversed names. In this specification, the terminals of a MOS transistor may also be referred to as the main node (source and drain) and the control node (gate).

[0027] The photoelectric conversion unit PD converts incident light into an amount of charge corresponding to the amount of light (photoelectric conversion) and stores the generated charge. The transfer transistor M1 is controlled to turn on by the control signal pTX, thereby transferring the charge held by the photoelectric conversion unit PD to the floating diffusion unit FD. The floating diffusion unit FD holds the charge transferred from the photoelectric conversion unit PD and sets the voltage at the input node of the amplification unit (gate of amplification transistor M4) to a voltage corresponding to its capacitance (floating diffusion capacitance) and the amount of charge transferred.

[0028] The capacitance-adding transistor M3 is controlled by the control signal pFDinc and has the role of switching the capacitance of the floating diffusion section FD according to its operating state. That is, when the capacitance-adding transistor M3 is turned on, it adds its gate capacitance to the capacitance of the floating diffusion section FD, and when it is turned off, it disconnects its gate capacitance from the floating diffusion section FD.

[0029] The reset transistor M2 is controlled by the control signal pRES and turns on simultaneously with the capacitive addition transistor M3, thereby resetting the floating diffusion section FD to a predetermined voltage corresponding to the voltage Vdd. At the same time, the transfer transistor M1 can also be turned on to reset the photoelectric conversion section PD.

[0030] The selection transistor M5 is controlled to turn on by the control signal pSEL, thereby putting the signal of the pixel 12 into a state where it can be output to the output line 16 (selected state). In other words, the selection transistor M5 controls the output of the signal to the output line 16. The amplification transistor M4 is configured such that a voltage Vdd is supplied to its drain and a bias current is supplied to its source from a current source (not shown) via the selection transistor M5, forming an amplification section (source follower circuit) with its gate as the input node. As a result, the amplification transistor M4 generates a signal corresponding to the voltage of the floating diffusion section FD and outputs it to the output line 16 via the selection transistor M5.

[0031] Next, the basic operation of pixel 12 will be explained using Figure 3. Figure 3 shows an example of a timing diagram for outputting a pixel signal at low brightness. The horizontal axis represents time, and the vertical axis represents voltage. Figure 3 shows the waveforms of the control signals pSEL, pRES, pFDinc, and pTX supplied from the vertical scanning circuit 20 to pixel 12.

[0032] Immediately before time t1, the control signals pSEL, pRES, pFDinc, and pTX are assumed to be at a low level. At time t1, the vertical scanning circuit 20 controls the control signals pSEL, pRES, and pFDinc from a low level to a high level. As a result, the selection transistor M5, reset transistor M2, and capacitive addition transistor M3 are turned on, the pixel 12 is selected, and the floating diffusion unit FD is reset to a voltage corresponding to the voltage Vdd.

[0033] At the following time t2, the vertical scanning circuit 20 controls the control signal pFDinc from a high level to a low level. This turns off the capacitive transistor M3, releasing the reset state of the floating diffusion unit FD, and disconnecting the gate capacitance of the capacitive transistor M3 from the floating diffusion unit FD. This reduces the capacitance of the floating diffusion unit FD during readout, thereby reducing noise. After the capacitive transistor M3 is turned off, the signal output from the amplification transistor M4 to the output line 16 via the selection transistor M5 becomes a reset level signal corresponding to the reset voltage of the floating diffusion unit FD.

[0034] During the period from time t3 to time t4, the vertical scanning circuit 20 controls the control signal pTX from a low level to a high level. This turns on the transfer transistor M1, and the charge accumulated in the photoelectric conversion unit PD is transferred to the floating diffusion unit FD. As a result, the floating diffusion unit FD has a voltage corresponding to its capacitance value and the amount of charge transferred from the photoelectric conversion unit PD. At time t4, the control signal pTX transitions to a low level and the transfer transistor M1 is turned off. Then, the signal output from the amplification transistor M4 to the output line 16 via the selection transistor M5 becomes a pixel signal corresponding to the amount of charge generated in the photoelectric conversion unit PD.

[0035] Next, the specific structure of the pixel 12 in the photoelectric converter according to this embodiment will be explained using Figure 4. Figure 4(a) is a plan view of the pixel 12, and Figure 4(b) is a cross-sectional view taken along line AA' of Figure 4(a). Note that, for simplification, the capacitive transistor M3 is not shown in Figure 4. Also, in Figure 4(a), for simplification, each region is shown as a rectangular shape, but this does not represent the actual shape of each part, but rather indicates that each part is at least located in this region.

[0036] Figure 4(a) shows an example of a planar layout of a single pixel 12. Active regions 112, 114, and 126 are defined in the area of ​​the semiconductor substrate 110 where the pixel 12 is located. The area between the active regions 112, 114, and 126 is an element isolation region 128 for electrically isolating the active regions 112, 114, and 126 using insulating structures such as STI (Shallow Trench Isolation) or pn junction isolation. On the semiconductor substrate 110, the gate electrode 130 of the transfer transistor M1, the gate electrode 134 of the reset transistor M2, the gate electrode 138 of the amplification transistor M4, and the gate electrode 140 of the selection transistor M5 are provided.

[0037] The active region 112 contains components of the pixel 12, including the photoelectric conversion unit PD, the transfer transistor M1, and a portion of the floating diffusion unit FD. In a plan view, the gate electrode 130 is arranged to traverse the active region 112. On one side of the gate electrode 130 within the active region 112, there is an N-type semiconductor region 150 that constitutes the charge storage region of the photoelectric conversion unit PD. On the other side of the gate electrode 130 within the active region 112, there is an N-type semiconductor region 154 that constitutes a portion of the floating diffusion unit FD.

[0038] The active region 114 contains the remaining components of the pixel 12, including the floating diffusion section FD, the reset transistor M2, the amplification transistor M4, and the selection transistor M5. In a plan view, each of the gate electrodes 134, 138, and 140 is arranged to traverse the active region 114. Within the active region 114, an N-type semiconductor region 168 is provided in the portion between the gate electrode 134 and the gate electrode 138, which constitutes the drains of the reset transistor M2 and the amplification transistor M4. Within the active region 114, an N-type semiconductor region 156 is provided in the portion adjacent to the N-type semiconductor region 168 via the channel region below the gate electrode 134, which constitutes the remaining components of the floating diffusion section FD and the source of the reset transistor M2. The N-type semiconductor region 156 is electrically connected to the N-type semiconductor region 154 and the gate electrode 138 via wiring (not shown). These connection nodes collectively constitute the floating diffusion section FD. In the active region 114, an N-type semiconductor region 174 is provided in the portion between the gate electrode 138 and the gate electrode 140, which constitutes the source of the amplification transistor M4 and the drain of the selection transistor M5. In the active region 114, an N-type semiconductor region 178 is provided in the portion adjacent to the N-type semiconductor region 174 via the channel region below the gate electrode 140, which constitutes the source of the selection transistor M5.

[0039] The active region 126 serves as a charge discharge region for discharging leaked charge (electrons). The active region 126 is provided with an N-type semiconductor region 182 that enables charge discharge. The N-type semiconductor region 182 may be connected to a node to which the power supply voltage is supplied, thereby actively discharging leaked charge to the outside.

[0040] As shown in Figure 4(a), the N-type semiconductor region 150 and the N-type semiconductor region 178 are adjacent to each other via an element isolation region 128. Also, the N-type semiconductor region 178 and the N-type semiconductor region 182 are adjacent to each other via an element isolation region 128. As shown in Figure 4(b), an element isolation structure 128A made of an insulating structure such as STI is provided in the element isolation region 128 between the N-type semiconductor region 150 and the N-type semiconductor region 178. An element isolation structure 128B made of an insulating structure such as STI is provided in the element isolation region 128 between the N-type semiconductor region 178 and the N-type semiconductor region 182.

[0041] In this embodiment of the photoelectric converter, the shortest distance between N-type semiconductor regions 150 and 178 via the element isolation structure 128A is greater than the shortest distance between N-type semiconductor regions 178 and 182 via the element isolation structure 128B. In other words, the separation width between N-type semiconductor regions 150 and 178 by the element isolation structure 128A is wider than the separation width between N-type semiconductor regions 178 and 182 by the element isolation structure 128B. By configuring the photoelectric converter in this way, the potential barrier for electrons between N-type semiconductor regions 150 and 178 becomes higher than the potential barrier for electrons between N-type semiconductor regions 178 and 182. This suppresses the leakage of electrons generated in the N-type semiconductor region 178 into the photoelectric converter PD, which causes false signals, and improves image quality.

[0042] For example, when the potential of the output line 16 decreases in response to the output signal of a pixel 12 belonging to a read row, electrons may be generated in the N-type semiconductor region 178 that constitutes the source of the selection transistor M5 of a pixel 12 belonging to a non-read row. By making the isolation width of the element isolation structure 128A wider than the isolation width of the element isolation structure 128B, these electrons are more likely to flow into the N-type semiconductor region 182 beyond the element isolation structure 128B than into the N-type semiconductor region 150 beyond the element isolation structure 128A. As a result, leakage of electrons generated in the N-type semiconductor region 178 into the photoelectric conversion unit PD is suppressed, and false signals can be reduced.

[0043] Thus, according to this embodiment, the generation of false signals caused by charge leakage into the photoelectric conversion section of the pixel can be effectively suppressed, and high-quality images can be obtained.

[0044] [Second Embodiment] A photoelectric conversion device according to a second embodiment of the present invention will be described with reference to Figure 5. Components similar to those in the photoelectric conversion device according to the first embodiment are denoted by the same reference numerals, and their descriptions are omitted or simplified.

[0045] The photoelectric converter according to this embodiment is the same as the photoelectric converter according to the first embodiment, except that the layout of each pixel 12 is different. In this embodiment, the differences from the photoelectric converter according to the first embodiment will be described in detail, and parts that are the same as those of the photoelectric converter according to the first embodiment will be omitted from the explanation as appropriate.

[0046] Figure 5 shows a plan view and a cross-sectional view of the pixel structure in the photoelectric converter according to this embodiment. Figure 5(a) is a plan view of pixel 12, and Figure 5(b) is a cross-sectional view of Figure 5(a) along line BB'. Note that, for simplification, the capacitive transistor M3 is not shown in Figure 5. Also, in Figure 5(a), for simplification, each region is shown as a rectangle, but this does not represent the actual shape of each part, but rather indicates that each part is at least located within this region.

[0047] Figure 5(a) shows an example of a planar layout of a single pixel 12. Active regions 112, 116, and 118 are defined in the area of ​​the semiconductor substrate 110 where the pixel 12 is located. The area between the active regions 112, 116, and 118 is an element isolation region 128 for electrically isolating the active regions 112, 116, and 118 using insulating structures such as STI or pn junction isolation. On the semiconductor substrate 110, the gate electrode 130 of the transfer transistor M1, the gate electrode 134 of the reset transistor M2, the gate electrode 138 of the amplification transistor M4, and the gate electrode 140 of the selection transistor M5 are provided.

[0048] Similar to the first embodiment, the active region 112 is provided with a portion of the photoelectric conversion unit PD, the transfer transistor M1, and the floating diffusion unit FD, which are components of the pixel 12.

[0049] The active region 116 contains the other part of the floating diffusion section FD and the reset transistor M2, which are components of the pixel 12. In a plan view, the gate electrode 134 is arranged to traverse the active region 116. On one side of the gate electrode 134 in the active region 116, there is an N-type semiconductor region 156 which constitutes the other part of the floating diffusion section FD and the source of the reset transistor M2. The N-type semiconductor region 156 is electrically connected to the gate electrode 138 via wiring (not shown). These connection nodes as a whole constitute the floating diffusion section FD. On the other side of the gate electrode 134 in the active region 116, there is an N-type semiconductor region 158 which constitutes the drain of the reset transistor M2.

[0050] The active region 118 is provided with the amplification transistor M4 and the selection transistor M5, which are components of the pixel 12. In a plan view, each of the gate electrodes 138 and 140 is arranged to traverse the active region 118. In the active region 118, the portion between the gate electrode 138 and the gate electrode 140 is provided with an N-type semiconductor region 174 which constitutes the source of the amplification transistor M4 and the drain of the selection transistor M5. In the active region 118, the portion adjacent to the N-type semiconductor region 174 via the channel region below the gate electrode 138 is provided with an N-type semiconductor region 172 which constitutes the drain of the amplification transistor M4. In the active region 118, the portion adjacent to the N-type semiconductor region 174 via the channel region below the gate electrode 140 is provided with an N-type semiconductor region 178 which constitutes the source of the selection transistor M5.

[0051] As shown in Figure 5(a), the N-type semiconductor region 150 and the N-type semiconductor region 178 are adjacent to each other via an element isolation region 128. Also, the N-type semiconductor region 178 and the N-type semiconductor region 158 are adjacent to each other via an element isolation region 128. As shown in Figure 5(b), an element isolation structure 128A made of an insulating structure such as STI is provided in the element isolation region 128 between the N-type semiconductor region 150 and the N-type semiconductor region 178. An element isolation structure 128C made of an insulating structure such as STI is provided in the element isolation region 128 between the N-type semiconductor region 178 and the N-type semiconductor region 158.

[0052] In this embodiment of the photoelectric converter, the distance between N-type semiconductor regions 150 and 178 is greater than the distance between N-type semiconductor regions 178 and 158. In other words, the separation width between N-type semiconductor regions 150 and 178 by the element separation structure 128A is wider than the separation width between N-type semiconductor regions 178 and 158 by the element separation structure 128C. By configuring the photoelectric converter in this way, the potential barrier for electrons between N-type semiconductor regions 150 and 178 becomes higher than the potential barrier for electrons between N-type semiconductor regions 178 and 158. This suppresses the leakage of electrons generated in N-type semiconductor region 178 into the photoelectric converter PD, which can cause false signals, thereby improving image quality.

[0053] When the potential of the output line 16 decreases, electrons may be generated in the N-type semiconductor region 178 that constitutes the source of the selection transistor M5, as described in the first embodiment. By making the isolation width of the element isolation structure 128A wider than the isolation width of the element isolation structure 128C, these electrons are more likely to flow into the N-type semiconductor region 158 beyond the element isolation structure 128C than to flow into the N-type semiconductor region 150 beyond the element isolation structure 128A. As a result, leakage of electrons generated in the N-type semiconductor region 178 into the photoelectric conversion unit PD is suppressed, and false signals can be reduced.

[0054] In this embodiment, the N-type semiconductor region 158, which is the destination for electron discharge, is a semiconductor region that constitutes the drain of the reset transistor M2 and is connected to a node to which the power supply voltage is supplied. Therefore, electrons that flow into the N-type semiconductor region 158 are discharged via the power supply. In this embodiment, since the drain of the reset transistor M2 is used as the destination for electron discharge, there is no need to separately provide an active region 126 as the destination for electron discharge, and it is possible to improve layout efficiency compared to the first embodiment.

[0055] Thus, according to this embodiment, the generation of false signals caused by charge leakage into the photoelectric conversion section of the pixel can be effectively suppressed, and high-quality images can be obtained.

[0056] [Third Embodiment] A photoelectric conversion device according to a third embodiment of the present invention will be described with reference to Figure 6. Components similar to those in the photoelectric conversion device according to the first or second embodiment will be denoted by the same reference numerals, and their descriptions will be omitted or simplified.

[0057] The photoelectric converter according to this embodiment is the same as the photoelectric converter according to the second embodiment, except that the element isolation structure separating the N-type semiconductor regions 150 and 178 and the N-type semiconductor regions 178 and 158 is different. In this embodiment, the differences from the photoelectric converter according to the second embodiment will be described in detail, and parts that are the same as those of the photoelectric converter according to the first or second embodiment will be omitted as appropriate.

[0058] Figure 6 shows a plan view and a cross-sectional view of the pixel structure in the photoelectric converter according to this embodiment. Figure 6(a) is a plan view of pixel 12, and Figure 6(b) is a cross-sectional view of Figure 6(a) along the CC' line. Note that, for simplification, the capacitive transistor M3 is not shown in Figure 6. Also, in Figure 6(a), for simplification, each region is shown as a rectangle, but this does not represent the actual shape of each part, but rather indicates that at least each part is located in this region.

[0059] The planar layout of the pixels 12 in the photoelectric converter according to this embodiment is the same as that of the photoelectric converter according to the second embodiment, as shown in Figure 6(a). That is, the N-type semiconductor region 150 and the N-type semiconductor region 178 are adjacent to each other via the element isolation region 128. Also, the N-type semiconductor region 178 and the N-type semiconductor region 158 are adjacent to each other via the element isolation region 128. However, in this embodiment, instead of the insulating structure used in the first and second embodiments, a pn junction isolation is used as the element isolation structure that separates the N-type semiconductor regions 150 and 178 and the N-type semiconductor regions 178 and 158.

[0060] In other words, in this embodiment, as shown in Figure 6(b), a P-type semiconductor region with reverse conductivity to the N-type semiconductor regions 150 and 178 is provided as an element isolation structure 128D in the element isolation region 128 between the N-type semiconductor region 150 and the N-type semiconductor region 178. Furthermore, a P-type semiconductor region with reverse conductivity to the N-type semiconductor regions 178 and 158 is provided as an element isolation structure 128E in the element isolation region 128 between the N-type semiconductor region 178 and the N-type semiconductor region 158. In Figure 6(b), it is assumed that the element isolation structures 128D and 128E are formed by multiple ion implantations, and the diagram schematically shows that the element isolation structures 128D and 128E are composed of multiple P-type semiconductor regions of different depths.

[0061] In this embodiment of the photoelectric converter, the distance between N-type semiconductor regions 150 and 178 is greater than the distance between N-type semiconductor regions 178 and 158. In other words, the separation width between N-type semiconductor regions 150 and 178 by the element isolation structure 128D is wider than the separation width between N-type semiconductor regions 178 and 158 by the element isolation structure 128E. By configuring the photoelectric converter in this way, the potential barrier for electrons between N-type semiconductor regions 150 and 178 becomes higher than the potential barrier for electrons between N-type semiconductor regions 178 and 158. This suppresses the leakage of electrons generated in N-type semiconductor region 178 into the photoelectric converter PD, which can cause false signals, thereby improving image quality.

[0062] When the potential of the output line 16 decreases, electrons may be generated in the N-type semiconductor region 178 that constitutes the source of the selection transistor M5, as described in the first embodiment. By making the isolation width of the element isolation structure 128D wider than the isolation width of the element isolation structure 128E, these electrons are more likely to flow into the N-type semiconductor region 158 beyond the element isolation structure 128E than to flow into the N-type semiconductor region 150 beyond the element isolation structure 128D. As a result, leakage of electrons generated in the N-type semiconductor region 178 into the photoelectric conversion unit PD is suppressed, and false signals can be reduced.

[0063] Furthermore, since pn junction isolation is used as the element isolation structures 128D and 128E in this embodiment, the number of electrons generated by defects present at the interface between the element isolation insulating film (such as STI) and the semiconductor is reduced, making it possible to improve dark-time characteristics such as dark current.

[0064] Thus, according to this embodiment, the generation of false signals caused by charge leakage into the photoelectric conversion section of the pixel can be effectively suppressed, and high-quality images can be obtained.

[0065] [Fourth Embodiment] A photoelectric conversion device according to the fourth embodiment of the present invention will be described with reference to Figure 7. Components similar to those in the photoelectric conversion devices of the first to third embodiments will be denoted by the same reference numerals, and their descriptions will be omitted or simplified.

[0066] The photoelectric converter according to this embodiment is the same as the photoelectric converter according to the third embodiment, except that the relationship between the element isolation structure separating the N-type semiconductor regions 150 and 178 and the element isolation structure separating the N-type semiconductor regions 178 and 158 is different. In this embodiment, the differences from the photoelectric converter according to the third embodiment will be explained in detail, and parts that are the same as the photoelectric converter according to the first to third embodiments will be omitted as appropriate.

[0067] Figure 7 shows a plan view and a cross-sectional view of the pixel structure in the photoelectric converter according to this embodiment. Figure 7(a) is a plan view of pixel 12, and Figure 7(b) is a cross-sectional view of Figure 7(a) along the DD' line. Note that, for simplification, the capacitive transistor M3 is not shown in Figure 7. Also, in Figure 7(a), for simplification, each region is shown as a rectangle, but this does not represent the actual shape of each part, but rather indicates that at least each part is located in this region.

[0068] The basic planar layout of the pixels 12 in the photoelectric converter according to this embodiment is the same as that of the photoelectric converter according to the third embodiment, as shown in Figure 7(a). That is, the N-type semiconductor region 150 and the N-type semiconductor region 178 are adjacent to each other via the element isolation region 128. Also, the N-type semiconductor region 178 and the N-type semiconductor region 158 are adjacent to each other via the element isolation region 128. However, in this embodiment, the relationship between the element isolation structure 128D that separates the N-type semiconductor regions 150 and 178 and the element isolation structure 128F that separates the N-type semiconductor regions 178 and 158 differs from that of the third embodiment.

[0069] In other words, in this embodiment, as shown in Figure 7(b), the impurity concentration of the P-type semiconductor region constituting the element isolation structure 128D is higher than the impurity concentration of the P-type semiconductor region constituting the element isolation structure 128F. In the P-type semiconductor region constituting the element isolation region 128, the potential barrier to electrons increases as the impurity concentration increases.

[0070] The separation width between N-type semiconductor regions 150 and 178 by the element isolation structure 128D does not necessarily need to be wider than the separation width between N-type semiconductor regions 178 and 158 by the element isolation structure 128F, as in the third embodiment. It is sufficient that the potential barrier for electrons between N-type semiconductor regions 150 and 178 is higher than the potential barrier for electrons between N-type semiconductor regions 178 and 158 as a result of lowering the impurity concentration of the P-type semiconductor region constituting the element isolation structure 128F. As long as this condition is satisfied, the separation width between N-type semiconductor regions 150 and 178 by the element isolation structure 128D may be less than or equal to the separation width between N-type semiconductor regions 178 and 158 by the element isolation structure 128F.

[0071] The impurity concentration in the P-type semiconductor region constituting the device isolation structure 128D does not necessarily need to be higher than the impurity concentration in the P-type semiconductor region constituting the device isolation structure 128F throughout the entire depth direction. For example, as shown in Figure 7(b), it is sufficient that the concentration of P-type impurities at the depth where the N-type semiconductor regions 150 and 178 are located is higher than the concentration of P-type impurities at the depth where the N-type semiconductor regions 178 and 158 are located.

[0072] By configuring the photoelectric converter in this way, it is possible to suppress the leakage of electrons generated in the N-type semiconductor region 178 into the photoelectric converter PD, which causes false signals, and to improve image quality. When the potential of the output line 16 decreases, as described in the first embodiment, electrons may be generated in the N-type semiconductor region 178 that constitutes the source of the selection transistor M5. If the impurity concentration of the element isolation structure 128D is made higher than the impurity concentration of the element isolation structure 128F, these electrons are more likely to flow into the N-type semiconductor region 158 beyond the element isolation structure 128F than to flow into the N-type semiconductor region 150 beyond the element isolation structure 128D. As a result, it is possible to suppress the leakage of electrons generated in the N-type semiconductor region 178 into the photoelectric converter PD, and to reduce false signals.

[0073] Thus, according to this embodiment, the generation of false signals caused by charge leakage into the photoelectric conversion section of the pixel can be effectively suppressed, and high-quality images can be obtained.

[0074] [Fifth Embodiment] A photoelectric conversion device according to the fifth embodiment of the present invention will be described with reference to Figure 8. Components similar to those in the photoelectric conversion devices of the first to fourth embodiments will be denoted by the same reference numerals, and their descriptions will be omitted or simplified.

[0075] The photoelectric converter according to this embodiment is the same as the photoelectric converter according to the second embodiment, except that the element isolation structure separating the N-type semiconductor regions 178 and 158 is different. In this embodiment, the differences from the photoelectric converter according to the second embodiment will be described in detail, and parts that are the same as the photoelectric converter according to the first to fourth embodiments will be omitted as appropriate.

[0076] Figure 8 shows a plan view and a cross-sectional view of the pixel structure in the photoelectric converter according to this embodiment. Figure 8(a) is a plan view of pixel 12, and Figure 8(b) is a cross-sectional view of Figure 8(a) along the line EE'. Note that, for simplification, the capacitive transistor M3 is not shown in Figure 8. Also, in Figure 8(a), for simplification, each region is shown as a rectangle, but this does not represent the actual shape of each part, but rather indicates that at least each part is located in this region.

[0077] The basic planar layout of the pixels 12 in the photoelectric converter according to this embodiment is the same as that of the photoelectric converter according to the second embodiment, as shown in Figure 8(a). That is, the N-type semiconductor region 150 and the N-type semiconductor region 178 are adjacent to each other via the element isolation region 128. Also, the N-type semiconductor region 178 and the N-type semiconductor region 158 are adjacent to each other via the element isolation region 128. However, in this embodiment, the element isolation structure 128G that separates the N-type semiconductor regions 178 and 158 is different from the element isolation structure 128C in the second embodiment.

[0078] In other words, in this embodiment, as shown in Figure 8(b), the element isolation structure 128A between N-type semiconductor regions 150 and 178 is made of an insulating structure, and the element isolation structure 128G between N-type semiconductor regions 178 and 158 is made of a P-type semiconductor region. Generally, the element isolation ability of an insulating structure that physically inhibits charge movement is higher than that of pn junction isolation, which electrically inhibits charge movement. Therefore, when compared with the same isolation width, the potential barrier of the element isolation structure 128A for electrons is higher than the potential barrier of the element isolation structure 128G for electrons.

[0079] The separation width between N-type semiconductor regions 150 and 178 by the element isolation structure 128A does not necessarily need to be wider than the separation width between N-type semiconductor regions 178 and 158 by the element isolation structure 128G, as in the third embodiment. As a result of configuring the element isolation structures 128A and 128G in this way, it is sufficient that the potential barrier for electrons between N-type semiconductor regions 150 and 178 is higher than the potential barrier for electrons between N-type semiconductor regions 178 and 158. As long as this condition is satisfied, the separation width between N-type semiconductor regions 150 and 178 by the element isolation structure 128A may be less than or equal to the separation width between N-type semiconductor regions 178 and 158 by the element isolation structure 128G.

[0080] By configuring the photoelectric converter in this way, it is possible to suppress the leakage of electrons generated in the N-type semiconductor region 178 into the photoelectric converter PD, which causes false signals, and to improve image quality. When the potential of the output line 16 decreases, as described in the first embodiment, electrons may be generated in the N-type semiconductor region 178 that constitutes the source of the selection transistor M5. By configuring the element isolation structure 128A with an insulating structure with high element isolation ability, these electrons are more likely to flow into the N-type semiconductor region 158 beyond the element isolation structure 128G than into the N-type semiconductor region 150 beyond the element isolation structure 128A. As a result, it is possible to suppress the leakage of electrons generated in the N-type semiconductor region 178 into the photoelectric converter PD, and to reduce false signals.

[0081] Thus, according to this embodiment, the generation of false signals caused by charge leakage into the photoelectric conversion section of the pixel can be effectively suppressed, and high-quality images can be obtained.

[0082] [Sixth Embodiment] A photoelectric conversion device according to the sixth embodiment of the present invention will be described with reference to Figure 9. Components similar to those in the photoelectric conversion devices of the first to fifth embodiments will be denoted by the same reference numerals, and their descriptions will be omitted or simplified.

[0083] The photoelectric converter according to this embodiment is the same as the photoelectric converter according to the second embodiment, except that the relationship between the element isolation structure separating the N-type semiconductor regions 150 and 178 and the element isolation structure separating the N-type semiconductor regions 178 and 158 is different. In this embodiment, the differences from the photoelectric converter according to the second embodiment will be described in detail, and parts that are the same as the photoelectric converter according to the first to fifth embodiments will be omitted as appropriate.

[0084] Figure 9 shows a plan view and a cross-sectional view of the pixel structure in the photoelectric converter according to this embodiment. Figure 9(a) is a plan view of pixel 12, and Figure 9(b) is a cross-sectional view of Figure 9(a) along the FF' line. Note that, for simplification, the capacitive transistor M3 is not shown in Figure 9. Also, in Figure 9(a), for simplification, each region is shown as a rectangle, but this does not represent the actual shape of each part, but rather indicates that each part is at least located in this region.

[0085] The basic planar layout of the pixels 12 in the photoelectric converter according to this embodiment is the same as that of the photoelectric converter according to the second embodiment, as shown in Figure 9(a). That is, the N-type semiconductor region 150 and the N-type semiconductor region 178 are adjacent to each other via the element isolation region 128. Also, the N-type semiconductor region 178 and the N-type semiconductor region 158 are adjacent to each other via the element isolation region 128. However, in this embodiment, the relationship between the element isolation structure 128A that separates the N-type semiconductor regions 150 and 178 and the element isolation structure 128H that separates the N-type semiconductor regions 178 and 158 differs from that of the second embodiment.

[0086] In other words, in this embodiment, as shown in Figure 9(b), the depth of the element isolation structure 128A provided between the N-type semiconductor regions 150 and 178 is different from the depth of the element isolation structure 128H provided between the N-type semiconductor regions 150 and 178. Generally, for element isolation insulator structures of the same width, the greater the depth, the higher the potential barrier to electrons.

[0087] The separation width between N-type semiconductor regions 150 and 178 by the element isolation structure 128A does not necessarily need to be wider than the separation width between N-type semiconductor regions 178 and 158 by the element isolation structure 128H, as in the case of the second embodiment. As a result of configuring the element isolation structures 128A and 128H in this way, it is sufficient that the potential barrier for electrons between N-type semiconductor regions 150 and 178 is higher than the potential barrier for electrons between N-type semiconductor regions 178 and 158. As long as this condition is satisfied, the separation width between N-type semiconductor regions 150 and 178 by the element isolation structure 128A may be less than or equal to the separation width between N-type semiconductor regions 178 and 158 by the element isolation structure 128H.

[0088] By configuring the photoelectric converter in this way, it is possible to suppress the leakage of electrons generated in the N-type semiconductor region 178 into the photoelectric converter PD, which causes false signals, and thereby improve image quality. When the potential of the output line 16 decreases, as described in the first embodiment, electrons may be generated in the N-type semiconductor region 178 that constitutes the source of the selection transistor M5. By configuring the element isolation structure 128A with an insulating structure deeper than the element isolation structure 128H, these electrons are more likely to flow into the N-type semiconductor region 158 beyond the element isolation structure 128H than into the N-type semiconductor region 150 beyond the element isolation structure 128A. As a result, it is possible to suppress the leakage of electrons generated in the N-type semiconductor region 178 into the photoelectric converter PD, and reduce false signals.

[0089] Thus, according to this embodiment, the generation of false signals caused by charge leakage into the photoelectric conversion section of the pixel can be effectively suppressed, and high-quality images can be obtained.

[0090] [Seventh Embodiment] A photoelectric conversion device according to the seventh embodiment of the present invention will be described with reference to Figure 10. Components similar to those in the photoelectric conversion devices of the first to sixth embodiments will be denoted by the same reference numerals, and their descriptions will be omitted or simplified.

[0091] The photoelectric converter according to this embodiment is the same as the photoelectric converter according to the second embodiment, except for differences in the relationship between the element isolation structure separating the N-type semiconductor regions 150 and 178 and the element isolation structure separating the N-type semiconductor regions 178 and 158, and the configuration of the N-type semiconductor region 158. In this embodiment, the differences from the photoelectric converter according to the second embodiment will be explained in detail, and parts that are the same as the photoelectric converter according to the first to sixth embodiments will be omitted as appropriate.

[0092] Figure 10 shows a plan view and a cross-sectional view of the pixel structure in the photoelectric converter according to this embodiment. Figure 10(a) is a plan view of pixel 12, and Figure 10(b) is a cross-sectional view of Figure 10(a) along the line GG'. Note that, for simplification, the capacitive transistor M3 is not shown in Figure 10. Also, in Figure 10(a), for simplification, each region is shown as a rectangle, but this does not represent the actual shape of each part, but rather indicates that each part is at least located in this region.

[0093] The basic planar layout of the pixels 12 in the photoelectric converter according to this embodiment is the same as that of the photoelectric converter according to the second embodiment, as shown in Figure 10(a). That is, the N-type semiconductor region 150 and the N-type semiconductor region 178 are adjacent to each other via the element isolation region 128. Also, the N-type semiconductor region 178 and the N-type semiconductor region 158 are adjacent to each other via the element isolation region 128. However, in this embodiment, the relationship between the element isolation structure separating the N-type semiconductor regions 150 and 178 and the element isolation structure separating the N-type semiconductor regions 178 and 158, and the configuration of the N-type semiconductor region 158, differ from those of the second embodiment.

[0094] In other words, in this embodiment, as shown in Figure 10(b), the N-type semiconductor region 158 is provided deeper in the semiconductor substrate 110 than the N-type semiconductor region 150 that constitutes the charge storage region of the photoelectric conversion unit PD. By configuring the N-type semiconductor region 158 in this way, the potential barrier for electrons between the N-type semiconductor regions 150 and 178 becomes higher than the potential barrier for electrons between the N-type semiconductor regions 178 and 158.

[0095] The separation width between the N-type semiconductor regions 150 and 178 by the element separation structure 128A does not necessarily need to be wider than the separation width between the N-type semiconductor regions 178 and 158 by the element separation structure 128I, as in the case of the second embodiment. As a result of configuring the N-type semiconductor region 158 as described above, it is sufficient that the potential barrier for electrons between the N-type semiconductor regions 150 and 178 is higher than the potential barrier for electrons between the N-type semiconductor regions 178 and 158. As long as this condition is satisfied, the separation width between the N-type semiconductor regions 150 and 178 by the element separation structure 128A may be less than or equal to the separation width between the N-type semiconductor regions 178 and 158 by the element separation structure 128I.

[0096] By configuring the photoelectric converter in this way, it is possible to suppress the leakage of electrons generated in the N-type semiconductor region 178 into the photoelectric converter PD, which can cause false signals, thereby improving image quality. When the potential of the output line 16 decreases, as described in the first embodiment, electrons may be generated in the N-type semiconductor region 178 that constitutes the source of the selection transistor M5. By providing the N-type semiconductor region 158 deeper in the semiconductor substrate 110 than the N-type semiconductor region 150, these electrons are more likely to flow into the N-type semiconductor region 158 beyond the element isolation structure 128I than into the N-type semiconductor region 150 beyond the element isolation structure 128A. As a result, it is possible to suppress the leakage of electrons generated in the N-type semiconductor region 178 into the photoelectric converter PD, thereby reducing false signals.

[0097] Thus, according to this embodiment, the generation of false signals caused by charge leakage into the photoelectric conversion section of the pixel can be effectively suppressed, and high-quality images can be obtained.

[0098] [Eighth Embodiment] A photoelectric conversion device according to the eighth embodiment of the present invention will be described with reference to Figures 11 to 13. Components similar to those in the photoelectric conversion devices of the first to seventh embodiments will be denoted by the same reference numerals, and their descriptions will be omitted or simplified. Figure 11 is an equivalent circuit diagram showing an example of the pixel configuration in the photoelectric conversion device according to this embodiment. Figure 12 is a plan view showing the pixel structure in the photoelectric conversion device according to this embodiment. Figure 13 is a cross-sectional view showing the pixel structure in the photoelectric conversion device according to this embodiment.

[0099] The photoelectric converter according to this embodiment is the same as the photoelectric converter according to the first to seventh embodiments, except for the configuration of the pixels 12. In this embodiment, the differences from the photoelectric converter according to the first embodiment will be described in detail, and parts that are the same as those of the photoelectric converter according to the first to seventh embodiments will be omitted as appropriate.

[0100] An example of the configuration of a pixel 12 in the photoelectric converter according to this embodiment will be explained with reference to Figure 11. Figure 11 shows two pixels 12 that are arranged in a 1 row (nth row) x 2 column (mth column to (m+1)th column) block from among the multiple pixels 12 that make up the pixel area 10. Some of the symbols shown in Figure 11 have symbols representing row numbers or column numbers added in parentheses.

[0101] Each of the pixels 12 may be composed of photoelectric conversion units PD1, PD2, transfer transistors M11, M12, reset transistor M2, amplification transistor M4, and selection transistors M51, M52. Each of the pixels 12 may further have a capacitive addition transistor M3, as shown in Figure 11. Here, we will describe a pixel configuration including the capacitive addition transistor M3. The transfer transistors M11, M12, reset transistor M2, capacitive addition transistor M3, amplification transistor M4, and selection transistors M51, M52 may be composed of MOS transistors. Each of the pixels 12 may have a microlens and a color filter arranged in the optical path from the incident light to the photoelectric conversion units PD1, PD2. The microlens focuses the incident light to the photoelectric conversion units PD1, PD2. The color filter selectively transmits light of a predetermined color.

[0102] The photoelectric conversion unit PD1 may be, for example, a photodiode with its anode connected to a ground node and its cathode connected to the source of the transfer transistor M11. The photoelectric conversion unit PD2 may be, for example, a photodiode with its anode connected to a ground node and its cathode connected to the source of the transfer transistor M12. The drains of the transfer transistor M11 and the transfer transistor M12 are connected to the source of the capacitive-adding transistor M3 and the gate of the amplifying transistor M4. The connection nodes of the drains of the transfer transistors M11 and M12, the source of the capacitive-adding transistor M3 and the gate of the amplifying transistor M4 form a so-called stray diffusion unit FD. The capacitive component (stray diffusion capacitance) connected to the stray diffusion unit FD functions as a charge-holding unit.

[0103] The drain of the capacitive transistor M3 is connected to the source of the reset transistor M2. In the case of a pixel configuration that does not include the capacitive transistor M3, the source of the reset transistor M2 is connected to the floating diffuser FD. The drains of the reset transistor M2 and the amplifier transistor M4 are connected to the power supply voltage node (voltage: Vdd). The source of the amplifier transistor M4 is connected to the drains of the selection transistor M51 and the selection transistor M52. The source of the selection transistor M51 is connected to signal line 161 of the output line 16. The source of the selection transistor M52 is connected to signal line 162 of the output line 16.

[0104] Pixel 12 can also be considered as containing two pixels in which two photoelectric conversion units PD1 and PD2 share one floating diffusion unit FD. Note that the number of photoelectric conversion units PD in pixel 12 is not limited to two, but may be three or more. In this case, a number of transfer transistors M1 corresponding to the number of photoelectric conversion units PD can be provided. Furthermore, the number of selection transistors M5 in pixel 12 is not limited to two, but may be three or more. In this case, the output lines 16 of each column may include a number of signal lines corresponding to the number of selection transistors M5.

[0105] In the pixel configuration shown in Figure 11, each row of control lines 14 includes six signal lines connected to the gates of transfer transistors M11 and M12, the gate of the capacitive transistor, the gate of the reset transistor M2, and the gates of selection transistors M51 and M52. The signal line connected to the gate of transfer transistor M11 is supplied with control signal pTX1 from the vertical scanning circuit 20. The signal line connected to the gate of transfer transistor M12 is supplied with control signal pTX2 from the vertical scanning circuit 20. The signal line connected to the gate of reset transistor M2 is supplied with control signal pRES from the vertical scanning circuit 20. The signal line connected to the gate of capacitive transistor M3 is supplied with control signal pFDinc from the vertical scanning circuit 20. The signal line connected to the gate of selection transistor M51 is supplied with control signal pSEL1 from the vertical scanning circuit 20. The signal line connected to the gate of selection transistor M52 is supplied with control signal pSEL2 from the vertical scanning circuit 20. When each transistor is composed of an N-type MOS transistor, the corresponding transistor is turned on when a high-level control signal is supplied from the vertical scanning circuit 20. Furthermore, when a low-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor is turned off.

[0106] Next, the specific structure of the pixel 12 in the photoelectric conversion device according to this embodiment will be described using Figures 12 and 13. Figure 12 is a plan view of the pixel 12, Figure 13(a) is a cross-sectional view of Figure 12 along line HH', and Figure 13(b) is a cross-sectional view of Figure 12 along line II'. In Figure 12, for simplification, each region is shown as a rectangular shape, but this does not represent the actual shape of each part, but rather indicates that each part is at least located within this region.

[0107] Figure 12 shows an example of a planar layout of a single pixel 12. Active regions 112, 120, 122, 124, and 126 are defined in the area of ​​the semiconductor substrate 110 where the pixel 12 is located. The areas between the active regions 112, 120, 122, 124, and 126 are element isolation regions 128 for electrically isolating the active regions 112, 120, 122, 124, and 126 using insulating structures such as STI or pn junction isolation. On the semiconductor substrate 110, the gate electrode 130 of the transfer transistor M11, the gate electrode 132 of the transfer transistor M12, the gate electrode 134 of the reset transistor M2, and the gate electrode 136 of the capacitive addition transistor M3 are provided. Also on the semiconductor substrate 110, the gate electrode 138 of the amplification transistor M4, the gate electrode 140 of the selection transistor M51, and the gate electrode 142 of the selection transistor M52 are provided.

[0108] The active region 112 contains components of the pixel 12, including the photoelectric conversion unit PD, transfer transistors M11 and M12, and a portion of the floating diffusion unit FD. In a plan view, each of the gate electrodes 130 and 132 is arranged to traverse the active region 112. Within the active region 112, an N-type semiconductor region 154, which constitutes a portion of the floating diffusion unit FD, is provided in the portion between the gate electrode 130 and the gate electrode 132. Within the active region 112, an N-type semiconductor region 150, which constitutes the charge storage region of the photoelectric conversion unit PD1, is provided in the portion adjacent to the N-type semiconductor region 154 via the channel region below the gate electrode 130. Within the active region 112, an N-type semiconductor region 152, which constitutes the charge storage region of the photoelectric conversion unit PD2, is provided in the portion adjacent to the N-type semiconductor region 154 via the channel region below the gate electrode 132.

[0109] The active region 120 contains the reset transistor M2, the capacitive transistor M3, and the remaining part of the floating diffusion section FD, which are components of the pixel 12. In a plan view, each of the gate electrodes 134 and 136 is arranged to traverse the active region 120. In the active region 120, the portion between the gate electrode 134 and the gate electrode 136 contains an N-type semiconductor region 164 which constitutes the source of the reset transistor M2 and the drain of the capacitive transistor M3. In the active region 120, the portion adjacent to the N-type semiconductor region 164 via the channel region below the gate electrode 134 contains an N-type semiconductor region 158 which constitutes the drain of the reset transistor. In the active region 120, the portion adjacent to the N-type semiconductor region 164 via the channel region below the gate electrode 136 contains an N-type semiconductor region 166 which constitutes the source of the capacitive transistor M3 and the remaining part of the floating diffusion section FD. The N-type semiconductor region 166 is electrically connected to the N-type semiconductor region 154 and the gate electrode 138 via wiring (not shown). These connection nodes together constitute the floating diffusion unit (FD).

[0110] The active region 122 is provided with an amplifying transistor M4, one of the components of the pixel 12. In a plan view, the gate electrode 138 is arranged to traverse the active region 120. On one side of the gate electrode 138 in the active region 122, an N-type semiconductor region 170 is provided, which constitutes the drain of the amplifying transistor M4. On the other side of the gate electrode 138 in the active region 122, an N-type semiconductor region 172 is provided, which constitutes the source of the amplifying transistor M4.

[0111] The active region 124 is provided with the selection transistors M51 and M52, which are components of the pixel 12. In a plan view, each of the gate electrodes 140 and 142 is arranged to traverse the active region 124. In the active region 124, the portion between the gate electrode 140 and the gate electrode 142 is provided with an N-type semiconductor region 176 which constitutes the drain of the selection transistor M51 and the drain of the selection transistor M52. In the active region 124, the portion adjacent to the N-type semiconductor region 176 via the channel region below the gate electrode 140 is provided with an N-type semiconductor region 178 which constitutes the source of the selection transistor M51. In the active region 124, the portion adjacent to the N-type semiconductor region 176 via the channel region below the gate electrode 142 is provided with an N-type semiconductor region 180 which constitutes the source of the selection transistor M52.

[0112] An N-type semiconductor region 182 is provided in the active region 126. The active region 126 serves as a charge discharge region for discharging leaked charge (electrons). The N-type semiconductor region 182 may also be connected to a node to which the power supply voltage is supplied, thereby actively removing leaked charge.

[0113] As shown in Figure 12, the N-type semiconductor region 150 and the N-type semiconductor region 178 are adjacent to each other via an element isolation region 128. Also, the N-type semiconductor region 178 and the N-type semiconductor region 182 are adjacent to each other via an element isolation region 128. As shown in Figure 13(a), an element isolation structure 128J made of an insulating structure such as STI is provided in the element isolation region 128 between the N-type semiconductor region 150 and the N-type semiconductor region 178. An element isolation structure 128K made of an insulating structure such as STI is provided in the element isolation region 128 between the N-type semiconductor region 178 and the N-type semiconductor region 182.

[0114] Furthermore, as shown in Figure 12, the N-type semiconductor region 150 and the N-type semiconductor region 180 are adjacent to each other via an element isolation region 128. Also, the N-type semiconductor region 180 and the N-type semiconductor region 172 are adjacent to each other via an element isolation region 128. As shown in Figure 13(b), an element isolation structure 128L made of an insulating structure such as STI is provided in the element isolation region 128 between the N-type semiconductor region 150 and the N-type semiconductor region 180. An element isolation structure 128M made of an insulating structure such as STI is provided in the element isolation region 128 between the N-type semiconductor region 180 and the N-type semiconductor region 172.

[0115] In this embodiment of the photoelectric converter, the distance between N-type semiconductor regions 150 and 178 is greater than the distance between N-type semiconductor regions 178 and 182. In other words, the separation width between N-type semiconductor regions 150 and 178 by the element isolation structure 128J is wider than the separation width between N-type semiconductor regions 178 and 182 by the element isolation structure 128K. Also, the distance between N-type semiconductor regions 150 and 180 is greater than the distance between N-type semiconductor regions 180 and 172. In other words, the separation width between N-type semiconductor regions 150 and 180 by the element isolation structure 128L is wider than the separation width between N-type semiconductor regions 180 and 172 by the element isolation structure 128M.

[0116] By configuring the photoelectric converter in this way, the potential barrier for electrons between N-type semiconductor regions 150 and 178 becomes higher than the potential barrier for electrons between N-type semiconductor regions 178 and 182. Furthermore, the potential barrier for electrons between N-type semiconductor regions 150 and 180 becomes higher than the potential barrier for electrons between N-type semiconductor regions 180 and 172. This suppresses the leakage of electrons generated in N-type semiconductor regions 178 and 180 into the photoelectric converter PD1, which can cause false signals, thereby improving image quality.

[0117] When the potential of the output line 16 decreases, as described in the first embodiment, electrons may be generated in the N-type semiconductor region 178 that constitutes the source of the selection transistor M51 and the N-type semiconductor region 180 that constitutes the source of the selection transistor M52. If the element isolation structure 128J is made wider than the element isolation structure 128K, electrons generated in the N-type semiconductor region 178 are more likely to flow into the N-type semiconductor region 182 beyond the element isolation structure 128K than to flow into the N-type semiconductor region 150 beyond the element isolation structure 128J. As a result, leakage of electrons generated in the N-type semiconductor region 178 into the photoelectric conversion unit PD1 can be suppressed, and false signals can be reduced. Similarly, if the element isolation structure 128L is made wider than the element isolation structure 128M, electrons generated in the N-type semiconductor region 180 are more likely to flow into the N-type semiconductor region 172 beyond the element isolation structure 128M than to flow into the N-type semiconductor region 150 beyond the element isolation structure 128L. As a result, it is possible to suppress the leakage of electrons generated in the N-type semiconductor region 180 into the photoelectric conversion unit PD1, thereby reducing false signals.

[0118] Thus, according to this embodiment, the generation of false signals caused by charge leakage into the photoelectric conversion section of the pixel can be effectively suppressed, and high-quality images can be obtained.

[0119] In this embodiment, an example is shown in which the element isolation structure 128J and element isolation structure 128K, and the element isolation structure 128J and element isolation structure 128K are composed of insulating structures with different isolation widths. However, any configuration described in other embodiments can be applied to these. Furthermore, a configuration combining at least two of the other embodiments may also be applied to these.

[0120] [Ninth Embodiment] An imaging system according to the ninth embodiment of the present invention will be described with reference to Figure 14. Figure 14 is a block diagram showing the schematic configuration of the imaging system according to this embodiment.

[0121] The photoelectric converter 100 described in the first to eighth embodiments above is applicable to various imaging systems. Examples of applicable imaging systems include digital still cameras, digital camcorders, surveillance cameras, photocopiers, fax machines, mobile phones, in-vehicle cameras, and observation satellites. Camera modules, which include optical systems such as lenses and imaging devices, are also included in imaging systems. Figure 14 shows a block diagram of a digital still camera as an example of these.

[0122] The imaging system 200 illustrated in Figure 14 includes an imaging device 201, a lens 202 for forming an optical image of a subject onto the imaging device 201, an aperture 204 for varying the amount of light passing through the lens 202, and a barrier 206 for protecting the lens 202. The lens 202 and the aperture 204 are an optical system that focuses light onto the imaging device 201. The imaging device 201 is a photoelectric conversion device 100 described in any of the first to eighth embodiments, which converts the optical image formed by the lens 202 into image data.

[0123] The imaging system 200 also includes a signal processing unit 208 that processes the output signal from the imaging device 201. The signal processing unit 208 generates image data from the digital signal output by the imaging device 201. The signal processing unit 208 also performs various corrections and compressions as needed before outputting the image data. The imaging device 201 may include an AD conversion unit that generates the digital signal processed by the signal processing unit 208. The AD conversion unit may be formed on the semiconductor layer (semiconductor substrate) on which the photoelectric conversion unit of the imaging device 201 is formed, or on a semiconductor substrate separate from the semiconductor layer on which the photoelectric conversion unit of the imaging device 201 is formed. The signal processing unit 208 may also be formed on the same semiconductor substrate as the imaging device 201.

[0124] The imaging system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. Furthermore, the imaging system 200 includes a recording medium 214 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading data from the recording medium 214. The recording medium 214 may be built into the imaging system 200 or it may be detachable.

[0125] Furthermore, the imaging system 200 includes an overall control and calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, the timing signals and the like may be input from an external source, and the imaging system 200 only needs to include at least an imaging device 201 and a signal processing unit 208 that processes the output signals output from the imaging device 201.

[0126] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0127] Thus, according to this embodiment, a high-performance imaging system can be realized by applying the photoelectric conversion device 100 according to the first to eighth embodiments.

[0128] [Tenth Embodiment] An imaging system and mobile body according to a seventh embodiment of the present invention will be described with reference to Figure 15. Figure 15 is a diagram showing the configuration of the imaging system and mobile body according to this embodiment.

[0129] Figure 15(a) shows an example of an imaging system for an in-vehicle camera. The imaging system 300 includes an imaging device 310. The imaging device 310 is the photoelectric converter 100 described in any of the first to eighth embodiments above. The imaging system 300 includes an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the imaging device 310. The imaging system 300 also includes a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 318 may use any of this distance information to determine the possibility of collision. The means for acquiring distance information may be implemented by specially designed hardware, or by a software module. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0130] The imaging system 300 is connected to the vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 318. The imaging system 300 is also connected to a warning device 340 that issues a warning to the driver based on the judgment result of the collision judgment unit 318. For example, if the collision judgment result of the collision judgment unit 318 indicates a high probability of collision, the control ECU 330 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 340 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0131] In this embodiment, the imaging system 300 captures images of the area around the vehicle, for example, the front or rear. Figure 15(b) shows the imaging system when capturing images of the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the imaging system 300 or the imaging device 310. This configuration allows for further improvement of the accuracy of distance measurement.

[0132] The above example illustrates control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or automatically prevent vehicles from straying from their lanes. Furthermore, the imaging system can be applied not only to vehicles such as the vehicle itself, but also to moving objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to moving objects but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0133] [Embodiment No. 11] An apparatus according to the 11th embodiment of the present invention will be described with reference to Figure 16. Figure 16 is a block diagram showing the schematic configuration of the apparatus according to this embodiment.

[0134] Figure 16 is a schematic diagram showing an instrument EQP including a photoelectric converter APR. The photoelectric converter APR has the functions of any of the first to eighth embodiments of the photoelectric converter 100. All or part of the photoelectric converter APR is a semiconductor device IC. The photoelectric converter APR in this example can be used, for example, as an image sensor, an AF (Auto Focus) sensor, a photometering sensor, or a distance measuring sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including a photoelectric conversion unit are arranged in a matrix. The semiconductor device IC may have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0135] The photoelectric converter APR may have a stacked structure (chip stacking structure) comprising a first semiconductor chip equipped with multiple photoelectric conversion units and a second semiconductor chip equipped with peripheral circuits. The peripheral circuits on the second semiconductor chip can each be a column circuit corresponding to a pixel row of the first semiconductor chip. Alternatively, the peripheral circuits on the second semiconductor chip can each be a matrix circuit corresponding to a pixel or pixel block of the first semiconductor chip. Connections between the first and second semiconductor chips can be made using through-silicon vias (TSVs), direct bonding of conductors such as copper for inter-chip wiring, microbump connections between chips, or wire bonding.

[0136] The photoelectric converter APR may include a semiconductor device IC as well as a package PKG that houses the semiconductor device IC. The package PKG may include a substrate on which the semiconductor device IC is fixed, a cover made of glass or the like that faces the semiconductor device IC, and connecting members such as bonding wires or bumps that connect terminals provided on the substrate to terminals provided on the semiconductor device IC.

[0137] The EQP device may further comprise at least one of the following: an optical device OPT, a control unit CTRL, a processing unit PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric converter APR as a photoelectric converter, and is, for example, a lens, shutter, or mirror. The control unit CTRL controls the photoelectric converter APR and is, for example, a semiconductor device such as an ASIC. The processing unit PRCS processes the signals output from the photoelectric converter APR and constitutes an AFE (analog front end) or a DFE (digital front end). The processing unit PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application-specific integrated circuit). The display device DSPL is an EL display device or liquid crystal display device that displays information (images) obtained from the photoelectric converter APR. The memory device MMRY is a magnetic device or semiconductor device that stores information (images) obtained from the photoelectric converter APR. The memory device MMRY is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive. The mechanical device MCHN has movable parts or propulsion parts such as motors and engines. The device EQP displays signals output from the photoelectric converter APR on the display device DSPL, or transmits them to the outside using a communication device (not shown) provided by the device EQP. For this purpose, it is preferable that the device EQP further includes a memory device MMRY and a processing device PRCS, separate from the memory circuit and arithmetic circuit of the photoelectric converter APR.

[0138] The EQP (Equipment Equipped Device) shown in Figure 16 can be electronic devices such as information terminals with imaging capabilities (e.g., smartphones and wearable devices) or cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, surveillance cameras). In cameras, the mechanical device MCHN can drive components of the optical device OPT for zooming, focusing, and shutter operation. Furthermore, the EQP can be transportation equipment (mobile devices) such as vehicles, ships, and aircraft. Also, the EQP can be medical devices such as endoscopes and CT scanners.

[0139] The mechanical device MCHN in transport equipment can be used as a mobile device. The device EQP as transport equipment is suitable for transporting the photoelectric converter APR, or for assisting and / or automating driving (operation) through its imaging function. The processing device PRCS for assisting and / or automating driving (operation) can perform processing to operate the mechanical device MCHN as a mobile device based on information obtained from the photoelectric converter APR.

[0140] The photoelectric converter APR according to this embodiment can provide high value to its designers, manufacturers, distributors, buyers, and / or users. Therefore, by installing the photoelectric converter APR in the EQP (Equipment Equipment), the value of the EQP can also be increased. Thus, when manufacturing and selling the EQP, deciding to install the photoelectric converter APR of this embodiment in the EQP is advantageous in increasing the value of the EQP.

[0141] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways.

[0142] For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or in which a part of the configuration of another embodiment is replaced, is also an embodiment of the present invention.

[0143] Furthermore, the circuit configurations of the pixels 12 shown in Figures 2 and 11 are illustrative and can be modified as appropriate. For example, each pixel 12 may have two or more photoelectric conversion elements. In this case, multiple photoelectric conversion elements may share one floating diffusion section FD. Alternatively, multiple photoelectric conversion elements may share one microlens to form pupil-splitting pixels, enabling the detection of phase differences. Also, the capacitive addition transistor M3 does not necessarily have to be connected between the reset transistor M2 and the floating diffusion section FD, but may be connected between the floating diffusion section FD and the ground node. Furthermore, the pixels 12 do not necessarily have to include the capacitive addition transistor M3.

[0144] Furthermore, the planar layout of the pixels 12 shown in the above embodiment is illustrative and can be modified as appropriate. The present invention is broadly applicable to cases in which at least the semiconductor region constituting the charge storage region of the photoelectric conversion unit and the semiconductor region constituting the source of the selected transistor are adjacent to each other via an element isolation region.

[0145] Furthermore, the imaging systems shown in the ninth and tenth embodiments above are examples of imaging systems to which the photoelectric conversion device of the present invention can be applied, and the imaging systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 14 and 15(a).

[0146] It should be noted that the above embodiments are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various forms without departing from its technical concept or its main features.

[0147] The above-disclosed embodiment includes the following configuration. (Composition 1) A pixel provided on a semiconductor substrate, having a photoelectric conversion unit, a floating diffusion unit to which the charge generated in the photoelectric conversion unit is transferred, an amplifying transistor that generates a signal corresponding to the voltage of the floating diffusion unit, and a selection transistor that controls the output of the signal, The pixel has an output line from which the signal is output, The photoelectric conversion unit has a first semiconductor region of a first conductivity type for accumulating the charge generated by photoelectric conversion. The selected transistor has a second semiconductor region of the first conductivity type that constitutes the node to which the output line is connected, The pixel further comprises a third semiconductor region of the first conductivity type configured to discharge charge, The second semiconductor region is adjacent to the first semiconductor region via the first element isolation structure, and is adjacent to the third semiconductor region via the second element isolation structure. The shortest distance between the first semiconductor region and the second semiconductor region via the first element isolation structure is greater than the shortest distance between the second semiconductor region and the third semiconductor region via the second element isolation structure. A photoelectric conversion device characterized by the following features. (Configuration 2) A pixel provided on a semiconductor substrate, having a photoelectric conversion unit, a floating diffusion unit to which the charge generated in the photoelectric conversion unit is transferred, an amplifying transistor that generates a signal corresponding to the voltage of the floating diffusion unit, and a selection transistor that controls the output of the signal, The pixel has an output line from which the signal is output, The photoelectric conversion unit has a first semiconductor region of a first conductivity type for accumulating the charge of the first polarity generated by photoelectric conversion. The selected transistor has a second semiconductor region of the first conductivity type that constitutes the node to which the output line is connected, The pixel further comprises a third semiconductor region of the first conductivity type configured to discharge the charge of the first polarity, The second semiconductor region is adjacent to the first semiconductor region via the first element isolation structure, and is adjacent to the third semiconductor region via the second element isolation structure. The potential barrier for the first polarity charge of the first element isolation structure between the first semiconductor region and the second semiconductor region is higher than the potential barrier for the first polarity charge of the second element isolation structure between the second semiconductor region and the third semiconductor region. A photoelectric conversion device characterized by the following features. (Composition 3) The third semiconductor region is connected to a node to which the power supply voltage is supplied. A photoelectric conversion device according to configuration 1 or 2, characterized by the above. (Composition 4) The third semiconductor region is the main node of the amplification transistor. A photoelectric conversion device according to configuration 3, characterized by the features described above. (Composition 5) The pixel further includes a reset transistor for resetting the voltage of the floating diffusion section. The third semiconductor region is the main node of the reset transistor. A photoelectric conversion device according to configuration 3, characterized by the features described above. (Composition 6) The first element isolation structure is composed of an insulating structure. A photoelectric conversion device according to any one of configurations 1 to 5, characterized by the above. (Composition 7) The second element isolation structure is composed of an insulating structure. A photoelectric conversion device according to configuration 6, characterized by the features described above. (Composition 8) The insulating structure constituting the first element isolation structure is provided deeper into the semiconductor substrate than the insulating structure constituting the first element isolation structure. A photoelectric conversion device according to configuration 7, characterized by the features described above. (Composition 9) The second element isolation structure is composed of a fourth semiconductor region of a second conductivity type different from the first conductivity type. A photoelectric conversion device according to configuration 6, characterized by the features described above. (Composition 10) The first element isolation structure is composed of a fifth semiconductor region of a second conductivity type different from the first conductivity type. A photoelectric conversion device according to any one of configurations 1 to 5, characterized by the above. (Composition 11) The second element isolation structure is composed of a sixth semiconductor region of the second conductivity type. A photoelectric conversion device according to configuration 10, characterized by the above. (Composition 12) The impurity concentration in the fifth semiconductor region is higher than that in the sixth semiconductor region. A photoelectric conversion device according to configuration 11, characterized by the features described above. (Composition 13) The third semiconductor region is provided deeper in the semiconductor substrate than the first semiconductor region. A photoelectric conversion device according to any one of configurations 1 to 12, characterized by the above. (Composition 14) The system comprises a plurality of selection transistors connected to the amplification transistor, and a plurality of output lines provided corresponding to the plurality of selection transistors, The pixel has a plurality of third semiconductor regions corresponding to each of the plurality of selection transistors' second semiconductor regions. A photoelectric conversion device according to any one of configurations 1 to 13, characterized by the above. (Composition 15) Having a plurality of pixels connected to the output line A photoelectric conversion device according to any one of configurations 1 to 14, characterized by the above. (Composition 16) A photoelectric conversion device according to any one of configurations 1 to 15, A signal processing device that processes the signal output from the aforementioned photoelectric converter and An imaging system characterized by having the following features. (Composition 17) It is a mobile object, A photoelectric conversion device according to any one of configurations 1 to 15, Distance information acquisition means that acquires distance information to an object from a parallax image based on a signal from the aforementioned photoelectric converter, Control means for controlling the moving body based on the distance information A mobile body characterized by having the following features. (Composition 18) A photoelectric conversion device according to any one of configurations 1 to 15, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A mechanical device controlled based on information obtained from the aforementioned photoelectric converter, A display device for displaying information obtained by the aforementioned photoelectric converter, and A memory device for storing information obtained by the aforementioned photoelectric converter, and at least one of the following: A device characterized by being equipped with the following features. [Explanation of symbols]

[0148] FD...Floating Diffusion Unit M4…Amplifying transistor M5, M51, M52…Selectable transistor PD, PD1, PD2... Photoelectric conversion unit 12... pixels 16…Output line 100... Photoelectric converter 128A~128M... Element isolation structure 150, 172, 178, 180, 182…N-type semiconductor region

Claims

1. A pixel provided on a semiconductor substrate, having a photoelectric conversion unit, a floating diffusion unit to which the charge generated in the photoelectric conversion unit is transferred, an amplifying transistor that generates a signal corresponding to the voltage of the floating diffusion unit, and a selection transistor that controls the output of the signal, The pixel has an output line from which the signal is output, The photoelectric conversion unit has a first semiconductor region of a first conductivity type for accumulating the charge generated by photoelectric conversion. The selected transistor has a second semiconductor region of the first conductivity type that constitutes a node to which the output line is connected, The pixel further comprises a third semiconductor region of the first conductivity type configured to discharge charge, The second semiconductor region is adjacent to the first semiconductor region via the first element isolation structure, and is adjacent to the third semiconductor region via the second element isolation structure. The shortest distance between the first semiconductor region and the second semiconductor region via the first element isolation structure is greater than the shortest distance between the second semiconductor region and the third semiconductor region via the second element isolation structure. A photoelectric conversion device characterized by the following features.

2. A pixel provided on a semiconductor substrate, having a photoelectric conversion unit, a floating diffusion unit to which the charge generated in the photoelectric conversion unit is transferred, an amplifying transistor that generates a signal corresponding to the voltage of the floating diffusion unit, and a selection transistor that controls the output of the signal, The pixel has an output line from which the signal is output, The photoelectric conversion unit has a first semiconductor region of a first conductivity type for accumulating the charge of the first polarity generated by photoelectric conversion. The selected transistor has a second semiconductor region of the first conductivity type that constitutes a node to which the output line is connected. The pixel further comprises a third semiconductor region of the first conductivity type configured to discharge the charge of the first polarity, The second semiconductor region is adjacent to the first semiconductor region via the first element isolation structure, and is adjacent to the third semiconductor region via the second element isolation structure. The potential barrier for the first polarity charge of the first element isolation structure between the first semiconductor region and the second semiconductor region is higher than the potential barrier for the first polarity charge of the second element isolation structure between the second semiconductor region and the third semiconductor region. A photoelectric conversion device characterized by the following features.

3. The third semiconductor region is connected to a node to which the power supply voltage is supplied. The photoelectric conversion device according to claim 1 or 2, characterized in that it is a photoelectric conversion device.

4. The third semiconductor region is the main node of the amplification transistor. The photoelectric conversion device according to claim 3.

5. The pixel further includes a reset transistor for resetting the voltage of the floating diffusion section. The third semiconductor region is the main node of the reset transistor. The photoelectric conversion device according to claim 3.

6. The first element isolation structure is composed of an insulating structure. The photoelectric conversion device according to claim 1 or 2, characterized in that it is a photoelectric conversion device.

7. The second element isolation structure is composed of an insulating structure. The photoelectric conversion device according to claim 6.

8. The insulating structure constituting the first element isolation structure is provided deeper into the semiconductor substrate than the insulating structure constituting the second element isolation structure. The photoelectric conversion device according to claim 7.

9. The second element isolation structure is composed of a fourth semiconductor region of a second conductivity type different from the first conductivity type. The photoelectric conversion device according to claim 6.

10. The first element isolation structure is composed of a fifth semiconductor region having a second conductivity type different from the first conductivity type. The photoelectric conversion device according to claim 1 or 2, characterized in that it is a photoelectric conversion device.

11. The second element isolation structure is composed of the sixth semiconductor region of the second conductivity type. The photoelectric conversion device according to claim 10, characterized in that it is a photoelectric conversion device.

12. The impurity concentration in the fifth semiconductor region is higher than the impurity concentration in the sixth semiconductor region. The photoelectric conversion device according to claim 11, characterized in that it is a photoelectric conversion device.

13. The third semiconductor region is provided deeper in the semiconductor substrate than the first semiconductor region. The photoelectric conversion device according to claim 1 or 2, characterized in that it is a photoelectric conversion device.

14. The system comprises a plurality of selection transistors connected to the amplification transistor, and a plurality of output lines provided corresponding to the plurality of selection transistors, The pixel has a plurality of third semiconductor regions corresponding to each of the plurality of second semiconductor regions of the plurality of selected transistors. The photoelectric conversion device according to claim 1 or 2, characterized in that it is a photoelectric conversion device.

15. Having a plurality of pixels connected to the output line The photoelectric conversion device according to claim 1 or 2, characterized in that it is a photoelectric conversion device.

16. A photoelectric conversion device according to claim 1 or 2, A signal processing device that processes the signal output from the aforementioned photoelectric converter and An imaging system characterized by having the following features.

17. It is a mobile object, A photoelectric conversion device according to claim 1 or 2, Distance information acquisition means that acquires distance information to an object from a parallax image based on a signal from the aforementioned photoelectric converter, Control means for controlling the moving body based on the distance information A mobile body characterized by having the following features.

18. A photoelectric conversion device according to claim 1 or 2, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A mechanical device controlled based on information obtained from the aforementioned photoelectric converter, A display device for displaying information obtained by the aforementioned photoelectric converter, and A memory device for storing information obtained by the aforementioned photoelectric converter, and at least one of the following: A device characterized by being equipped with the following features.

Images