Composite electronic components

Abstract

To suppress warpage in a composite electronic component having a structure where wiring structures are provided on a surface and a rear face of an insulation layer where an electronic component is embedded.SOLUTION: A composite electronic component 1 includes an insulation layer 12 where an electronic component 2 is embedded; a first wiring structure positioned on a surface 12b side of the insulation layer 12 and including an insulation layer 11 and conductor layers C0 and C1 arranged on both surfaces thereof; and a second wiring structure positioned on a surface 12a side of the insulation layer 12 and including insulation layers 13 and 14 and conductor layers C2 to C4 arranged on both surfaces thereof. The insulation layer 14 is composed of a material obtained by impregnating a core material with a resin, and the insulation layer 11 is composed of a resin material containing no core material. Thus, since the core material is contained in the second wiring structure having the larger number of layers than the first wiring structure, occurrence of warpage can be effectively suppressed.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a composite electronic component, and particularly to a composite electronic component including an insulating layer in which an electronic component is embedded and wiring structures provided on the front and back surfaces of the insulating layer.

Background Art

[0002] Patent Document 1 discloses a printed wiring board having a structure in which an electronic component is embedded in an insulating layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a composite electronic component is configured by further providing wiring structures on the front and back surfaces of an insulating layer in which an electronic component is embedded, problems may occur in terms of shape (for example, warpage), strength (for example, cracking and chipping), terminal connection reliability, and the like.

[0005] In the present disclosure, a composite electronic component having a structure in which wiring structures are provided on the front and back surfaces of an insulating layer in which an electronic component is embedded and having improved quality is described.

Means for Solving the Problems

[0006] A composite electronic component relating to one aspect of the present disclosure comprises a first insulating layer in which an electronic component is embedded; a first wiring structure located on one surface side of the first insulating layer and including at least one second insulating layer and conductor layers arranged on both sides thereof; and a second wiring structure located on the other surface side of the first insulating layer and including a plurality of third insulating layers having more layers than the second insulating layer and conductor layers arranged on both sides thereof, wherein at least one of the plurality of third insulating layers is made of a material in which a resin is impregnated into a core material, and the second insulating layer is made of a resin material that does not contain a core material.

[0007] According to this disclosure, since the core material is included in the second wiring structure, which has more layers than the first wiring structure, the reliability of the shape can be improved, for example, by effectively suppressing the occurrence of warping.

[0008] In this disclosure, the first insulating layer may be made of a resin material that does not contain a core material. This ensures that the embedding of electronic components is not hindered.

[0009] In this disclosure, of the multiple third insulating layers, the outermost insulating layer is made of a material in which a core material is impregnated with resin, and the other insulating layers are made of a resin material that does not contain a core material. Of the conductor layers included in the second wiring structure, a portion of the outermost first conductor layer may constitute an external terminal. In this case, since the core material is placed as a base for the first conductor layer that constitutes the external terminal, the core material is less likely to affect the characteristics of the internal circuit.

[0010] In this disclosure, the coefficient of thermal expansion of the electronic component may be smaller than that of the outermost insulating layer among the multiple third insulating layers, the outermost insulating layer among the multiple third insulating layers may have a smaller coefficient of thermal expansion than that of the second insulating layer, and the second insulating layer may have a smaller coefficient of thermal expansion than that of the first insulating layer. This makes it possible to further improve the reliability of the shape.

[0011] In this disclosure, the conductor layer included in the second wiring structure may further include a second conductor layer including a first coil pattern and a third conductor layer including a second coil pattern that overlaps with the first coil pattern in a plan view. In this case, since there is no core material between the first and second coil patterns, the core material does not affect the characteristics of the first and second coil patterns.

[0012] In this disclosure, the first wiring structure further includes a fourth conductor layer including a third coil pattern and a fifth conductor layer including a fourth coil pattern that overlaps with the third coil pattern in a plan view, wherein the third coil pattern may be connected to the first coil pattern and the fourth coil pattern may be connected to the second coil pattern. This makes it possible to magnetically couple the third and fourth coil patterns and to connect a circuit consisting of the first and second coil patterns and a circuit consisting of the third and fourth coil patterns in series.

[0013] In this disclosure, the outermost insulating layer among the multiple third insulating layers may have its core material offset toward the first conductor layer in the thickness direction. This reduces interference between the core material and the conductor pattern. [Effects of the Invention]

[0014] Thus, according to the technology disclosed herein, it is possible to provide a composite electronic component with improved quality, having a structure in which wiring structures are provided on both the front and back surfaces of an insulating layer in which electronic components are embedded. [Brief explanation of the drawing]

[0015] [Figure 1] Figure 1 is a schematic perspective view showing the appearance of a composite electronic component 1 according to one embodiment of the technology described herein. [Figure 2] Figure 2(a) is a schematic cross-sectional view of the cross-section along line AA shown in Figure 1, viewed from one direction, and Figure 2(b) is a schematic cross-sectional view of the cross-section along line AA shown in Figure 1, viewed from the opposite direction. [Figure 3]Figure 3 is a schematic exploded perspective view of the composite electronic component 1. [Figure 4] Figure 4 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer C4. [Figure 5] Figure 5 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer C3. [Figure 6] Figure 6 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer C2. [Figure 7] Figure 7 is a schematic plan view of the layer in which the ESD protection component 2 is embedded. [Figure 8] Figure 8 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer C1. [Figure 9] Figure 9 is a schematic plan view showing the shape of the conductor pattern provided on the conductor layer C0. [Figure 10] Figure 10 is an equivalent circuit diagram of the composite electronic component 1. [Figure 11] Figure 11 is a process diagram for explaining the manufacturing method of the composite electronic component 1. [Figure 12] Figure 12 is a process diagram for explaining the manufacturing method of the composite electronic component 1. [Figure 13] Figure 13 is a process diagram for explaining the manufacturing method of the composite electronic component 1. [Figure 14] Figure 14 is a process diagram for explaining the manufacturing method of the composite electronic component 1. [Figure 15] Figure 15 is a process diagram for explaining the manufacturing method of the composite electronic component 1. [Figure 16] Figure 16 is a process diagram for explaining the manufacturing method of the composite electronic component 1. [Figure 17] Figure 17 is a process diagram for explaining the manufacturing method of the composite electronic component 1. [Figure 18] Figure 18 is a process diagram for explaining the manufacturing method of the composite electronic component 1. [Figure 19] Figure 19 is a process diagram for explaining the manufacturing method of the composite electronic component 1. [Figure 20]Figure 20 is a process diagram illustrating the manufacturing method of the composite electronic component 1. [Figure 21] Figure 21 is a process diagram illustrating the manufacturing method of the composite electronic component 1. [Figure 22] Figure 22 is a process diagram illustrating the manufacturing method of the composite electronic component 1. [Figure 23] Figure 23 is a process diagram illustrating the manufacturing method of the composite electronic component 1. [Modes for carrying out the invention]

[0016] The embodiments of the technology described herein will be described in detail below with reference to the attached drawings.

[0017] Figure 1 is a schematic perspective view showing the appearance of a composite electronic component 1 according to one embodiment of the technology described herein.

[0018] The composite electronic component 1 according to this embodiment is a surface-mount type chip component, and as shown in Figure 1, it comprises a base body 10 and a plurality of external terminals arranged in an array on the surface of the base body 10. The plurality of external terminals consist of eight signal terminals 20 to 27 and two ground terminals 28 and 29.

[0019] Figure 2(a) is a schematic cross-sectional view of the cross-section along line AA shown in Figure 1, viewed from one direction, and Figure 2(b) is a schematic cross-sectional view of the cross-section along line AA shown in Figure 1, viewed from the opposite direction.

[0020] As shown in Figures 2(a) and (b), the base body 10 has a structure in which insulating layers 11 to 14 made of resin or the like are stacked in this order. Of these, insulating layer 11 is provided on one surface 12b side of insulating layer 12, and insulating layers 13 and 14 are provided on the other surface 12a side of insulating layer 12. A conductor layer C1 is formed on one surface 12b side of insulating layer 12. Conductor layer C1 is covered by insulating layer 11. A conductor layer C0 is formed on the surface of insulating layer 11. Conductor layer C0 is covered by solder resist 31. The insulating layer 11 and the conductor layers C0 and C1 arranged on both sides thereof constitute a first wiring structure. Conductor layers C0 and C1 are embedded in insulating layers 11 and 12, respectively. As a result, the flatness of the outermost surface of the first wiring structure is improved compared to the case in which the conductor layer C0 is provided so as to protrude from the surface of insulating layer 11, so that sufficient insulating properties can be ensured even if the thickness of solder resist 31 is reduced. In the examples shown in Figures 2(a) and (b), the first wiring structure includes one insulating layer 11, but the number of insulating layers included in the first wiring structure is not particularly limited.

[0021] A conductor layer C2 is formed on the other surface 12a of the insulating layer 12. Conductor layer C2 is covered by the insulating layer 13. Conductor layer C3 is formed on the surface of the insulating layer 13. Conductor layer C3 is covered by the insulating layer 14. Conductor layer C4 is formed on the surface of the insulating layer 14. Conductor layer C4 is covered by solder resist 32. The insulating layers 13, 14 and the conductor layers C2 to C4 arranged on both sides thereof constitute a second wiring structure. Conductor layers C2 and C3 are embedded in the insulating layers 13 and 14, respectively. In contrast, conductor layer C4 protrudes from the surface of the insulating layer 14. In the examples shown in Figures 2(a) and (b), the second wiring structure includes two insulating layers 13 and 14, but the number of insulating layers included in the second wiring structure is not particularly limited, as long as it is greater than the number of insulating layers included in the first wiring structure.

[0022] Insulating layers 11 to 14 are all interlayer films with conductive layers on both sides, and in that sense, solder resists 31 and 32 do not qualify as insulating layers. Therefore, the insulating layers located on the outermost surface are insulating layers 11 and 14. Solder resist 31 covers the entire outermost surface of insulating layer 11. As a result, the conductive layer C0 is covered by solder resist 31 without being exposed. In contrast, solder resist 32 has partial openings, and a portion of the conductive layer C4 exposed through these openings is used as an external terminal.

[0023] An ESD protection component 2 is embedded in the insulating layer 12. Since the ESD protection component 2 is made of a semiconductor substrate, its coefficient of thermal expansion is significantly different from that of the insulating layers 11 to 14. However, in this embodiment, the ESD protection component 2 is embedded approximately in the center in the stacking direction, and insulating layers 11, 13, and 14 are provided on both sides of it. This allows for a high degree of freedom in adjusting the symmetry in the stacking direction by adjusting the thickness, and makes it less likely for the entire composite electronic component 1 to warp due to temperature changes.

[0024] Furthermore, in this embodiment, of the insulating layers 11 to 14, the outermost insulating layer 14 is made of a material in which the core material 15 is impregnated with resin. The other insulating layers 11 to 13 are made of resin material that does not contain a core material. In this way, by using a material in which the core material 15 is impregnated with resin as the material for insulating layer 14, the overall strength is increased.

[0025] The coefficient of thermal expansion of the resin and wiring conductors used in the wiring board material is larger than that of electronic components. Therefore, in the configuration illustrated in Figure 2, the balance of the coefficient of thermal expansion relative to the electronic components differs between the front and back sides (insulating layer 14 side and insulating layer 11 side). In contrast, by using a material containing the core material 15 as the insulating layer 14, the coefficient of thermal expansion of the insulating layer 14 can be set lower than that of insulating layers 11 and 13, thereby suppressing the occurrence of warping. Furthermore, since the insulating layer 14 is located on the outermost layer and components that have little impact on circuit characteristics, such as external terminals, are provided on its surface, the influence of the core material 15 on circuit characteristics can be kept relatively small. In addition, the difference in the coefficient of thermal expansion between the insulating layer 14 and the motherboard impregnated with the core material (e.g., glass cloth) is reduced, which suppresses stress differences caused by heat, etc. This makes it possible to suppress the deterioration of quality in solder connections between external terminals and the motherboard.

[0026] Because vias (120-127) connected to internal electronic components with a low coefficient of thermal expansion are required to be small in diameter, the risk of connection problems tends to be higher. In contrast, by adopting the configuration of this embodiment, thermal expansion is suppressed by the electronic components with a low coefficient of thermal expansion and the insulating layer 14, and an improvement in connection quality can be expected.

[0027] In this embodiment, the coefficient of thermal expansion of the electronic components may be designed to be smallest first, followed by the insulating layer 14 which can suppress thermal stress between the motherboard and the electronic components, then insulating layers 11 and 13, and then the insulating layer 12 into which the electronic components are embedded, in that order of increasing coefficient of thermal expansion. Here, in order to prevent interference between the conductor layer C3 embedded in the insulating layer 14 and the core material 15, it is preferable that the core material 15 be offset towards the conductor layer C4 in the thickness direction.

[0028] Since the insulating layers 11-13 are made of a resin material without a core, circuit characteristics, ease of forming fine wiring, and processability for forming smaller vias are improved. For example, since coil patterns are formed on both sides of the insulating layers 11 and 13, if a material containing a core is used for the insulating layers 11 and 13, the core may affect the coupling between coil patterns. However, in this embodiment, since a resin material without a core is used for the insulating layers 11 and 13, it is possible to obtain coil characteristics that are almost as designed. Also, since the ESD protection component 2 is embedded in the insulating layer 12, if a material containing a core is used for the insulating layer 12, the core may hinder the embedding. However, in this embodiment, since a resin material without a core is used for the insulating layer 12, embedding the ESD protection component 2 becomes easier. Furthermore, it is possible to suppress dielectric breakdown caused by ESD by reducing the wiring and interlayer space required to improve circuit characteristics, and naturally, the withstand voltage characteristics are improved. Furthermore, although numerous via conductors exist between the insulating layers 11-13, the insulating layers 11-13 do not contain any core material, making it easy to form vias for embedding via conductors.

[0029] Figure 3 is a roughly exploded perspective view of composite electronic component 1.

[0030] As shown in Figure 3, coil patterns 41 to 48 are embedded in the composite electronic component 1. Of these, coil patterns 41 and 42 are located in the conductor layer C3, coil patterns 43 and 44 are located in the conductor layer C2, coil patterns 45 and 46 are located in the conductor layer C1, and coil patterns 47 and 48 are located in the conductor layer C0. Coil patterns 41 and 43 overlap each other in a plan view via the insulating layer 13, and coil patterns 42 and 44 also overlap each other in a plan view via the insulating layer 13. Furthermore, coil patterns 45 and 47 overlap each other in a plan view via the insulating layer 11, and coil patterns 46 and 48 also overlap each other in a plan view via the insulating layer 11.

[0031] Figures 4-6, 8, and 9 are schematic plan views showing the shapes of the conductor patterns provided in conductor layers C4, C3, C2, C1, and C0, respectively. Figure 7 is a schematic plan view of the layer in which the ESD protection component 2 is embedded. Here, the AA line shown in Figures 4-9 corresponds to the cross-section shown in Figures 2(a) and (b).

[0032] As shown in Figure 4, the conductor layer C4 is provided with conductor patterns 50-59 and a ground pattern GP. The portions of conductor patterns 50-57 that are exposed from the solder resist 32 are surface-treated and used as signal terminals 20-27, respectively. The portions of conductor patterns 58 and 59 that are exposed from the solder resist 32 are surface-treated and used as ground terminals 28 and 29, respectively. Conductor patterns 58 and 59 are connected to each other via the ground pattern GP. The ground pattern GP is a linearly extending conductor pattern, and its width is narrower than the width of conductor patterns 58 and 59. Thus, since the ground pattern GP, ​​signal terminals 20-27, and conductor patterns 58 and 59 are all located on the same conductor layer C4, there is no need to add a dedicated conductor layer for the ground pattern GP.

[0033] As shown in Figure 5, the conductor layer C3 is provided with coil patterns 41, 42 and conductor patterns 60, 61, 63-66. The outer edge of coil pattern 41 is connected to conductor pattern 52 via via conductor 102. The outer edge of coil pattern 42 is connected to conductor pattern 57 via via conductor 107. In addition, conductor patterns 60, 61, 63-66 are connected to conductor patterns 50, 51, 53-56, respectively, via via conductors 100, 101, 103-106 provided in the insulating layer 14. Coil patterns 41 and 42 are adjacent to each other with a gap G1 in between. In the conductor layer C3, there is no ground pattern or anything similar in the gap G1, so coil patterns 41 and 42 are directly adjacent to each other with the insulating layer 14 in between.

[0034] As shown in Figure 6, the conductor layer C2 is provided with coil patterns 43, 44 and conductor patterns 70-76. The outer edge of coil pattern 43 is connected to conductor pattern 63 via via conductor 113. The outer edge of coil pattern 44 is connected to conductor pattern 66 via via conductor 116. Conductor patterns 70-74 are connected to conductor patterns 60, 61, 64, 65, and 68, respectively, via via conductors 110, 111, 114, 115, and 118. Conductor patterns 75 and 76 are connected to the inner edges of coil patterns 41 and 42, respectively, via via conductors 112 and 117. Coil patterns 43 and 44 are adjacent to each other with a gap G1 in between. In the conductor layer C2, no ground pattern or the like is provided in the gap G1, and coil patterns 43 and 44 are directly adjacent to each other with an insulating layer 13 in between.

[0035] Coil patterns 41 to 44 all have a configuration in which the conductor pattern is wound approximately 4 times. Coil patterns 41 and 43 overlap in the stacking direction, and their pattern shapes are almost identical except for the positions of the outer and inner edges. Similarly, coil patterns 42 and 44 overlap in the stacking direction, and their pattern shapes are almost identical except for the positions of the outer and inner edges. Furthermore, the pattern shapes of coil patterns 41 and 42 are symmetrical in plan view, and the pattern shapes of coil patterns 43 and 44 are symmetrical in plan view.

[0036] As shown in Figure 7, terminal electrodes 80 to 87 are provided on the surface of the ESD protection component 2. Terminal electrodes 80 to 83 are connected to conductor patterns 70 to 73, respectively, via via conductors 120 to 123 provided in the insulating layer 12. Terminal electrodes 84 to 87 are also connected to the conductor pattern 74 in common via via conductors 124 to 127 provided in the insulating layer 12.

[0037] As shown in Figure 8, the conductor layer C1 is provided with coil patterns 45, 46 and conductor patterns 91, 93, 94, 97. The outer edge of coil pattern 45 is connected to conductor pattern 70 via via conductor 130. The outer edge of coil pattern 46 is connected to conductor pattern 73 via via conductor 135. The inner edge of coil pattern 45 is connected to conductor pattern 75 via via conductor 132. The inner edge of coil pattern 46 is connected to conductor pattern 76 via via conductor 136. In addition, conductor patterns 91 and 94 are connected to conductor patterns 71 and 72, respectively, via via conductors 131 and 134. Furthermore, conductor patterns 93 and 97 are connected to the inner edges of coil patterns 43 and 44, respectively, via via conductors 133 and 137. Coil patterns 45 and 46 are adjacent to each other with a gap G2 in between. In the conductor layer C1, no ground pattern or anything similar is provided in the gap G2, and coil patterns 45 and 46 are directly adjacent to each other via the insulating layer 12.

[0038] As shown in Figure 9, coil patterns 47 and 48 are provided in the conductor layer C0. The outer and inner ends of coil pattern 47 are connected to conductor patterns 91 and 93, respectively, via conductors 141 and 143. The outer and inner ends of coil pattern 48 are connected to conductor patterns 94 and 97, respectively, via conductors 144 and 147. Coil patterns 47 and 48 are adjacent to each other with a gap G2 in between. In the conductor layer C0, no ground pattern or the like is provided in the gap G2, so coil patterns 47 and 48 are directly adjacent to each other with an insulating layer 11 in between.

[0039] Coil patterns 45 to 48 all have a configuration in which the conductor pattern is wound approximately 5 times. Coil patterns 45 and 47 overlap in the stacking direction, and their pattern shapes are almost identical except for the positions of the outer and inner edges. Similarly, coil patterns 46 and 48 overlap in the stacking direction, and their pattern shapes are almost identical except for the positions of the outer and inner edges. Furthermore, the pattern shapes of coil patterns 45 and 46 are symmetrical in plan view, and the pattern shapes of coil patterns 47 and 48 are symmetrical in plan view.

[0040] Figure 10 is an equivalent circuit diagram of the composite electronic component 1 according to this embodiment.

[0041] As shown in Figure 10, in the composite electronic component 1 according to this embodiment, coil patterns 45 and 41 are connected in series between signal terminals 20 and 22, coil patterns 47 and 43 are connected in series between signal terminals 21 and 23, coil patterns 48 and 44 are connected in series between signal terminals 24 and 26, and coil patterns 46 and 42 are connected in series between signal terminals 25 and 27. Then, common mode filter CMF1 is formed by the magnetic coupling of coil patterns 41 and 43, common mode filter CMF2 is formed by the magnetic coupling of coil patterns 42 and 44, common mode filter CMF3 is formed by the magnetic coupling of coil patterns 45 and 47, and common mode filter CMF4 is formed by the magnetic coupling of coil patterns 46 and 48. Furthermore, protective elements integrated into the ESD protection component 2 are inserted between signal terminals 20, 21, 24, and 25 and ground terminals 28 and 29. Thus, the composite electronic component 1 according to this embodiment constitutes an array of common mode filters with ESD protection function. The ground terminal 29 is connected to the ESD protection component 2 via the ground pattern GP.

[0042] The ground pattern GP connects the ground terminals 28 and 29 by connecting the conductor pattern 58 and conductor pattern 59. Here, the conductor pattern 59 does not have a corresponding via conductor, and therefore the ground potential applied to the ground terminal 29 is supplied to the conductor pattern 58 via the conductor pattern 59 and the ground pattern GP. In other words, the ground terminal 29 is used as a so-called dummy terminal. The reason for providing such a ground terminal 29 is to ensure sufficient mounting strength when the composite electronic component 1 according to this embodiment is mounted on a circuit board. Furthermore, since there is no via conductor in the position that overlaps with the conductor pattern 59 in a plan view, the conductor pattern 59 is prone to delamination, but in this embodiment, since the conductor pattern 59 is connected to the conductor pattern 58 via the ground pattern GP, ​​delamination of the conductor pattern 59 is also prevented.

[0043] As described above, the composite electronic component 1 according to this embodiment has a configuration in which one insulating layer 11 is placed on one surface 12b side of the insulating layer 12 in which the ESD protection component 2 is embedded, and two insulating layers 13 and 14 are placed on the other surface 12a side, and a material in which a core material 15 impregnated with resin is used as the material for the insulating layer 14. In this way, since the insulating layer containing the core material 15 is placed on the wiring structure on the side with more insulating layers, it is possible to effectively prevent overall warping. In addition, by providing an insulating layer 14 with a core material 15, the overall strength of the composite electronic component 1 can be improved. Furthermore, since the insulating layer 14 has a lower coefficient of thermal expansion than the insulating layer 12 in which the ESD protection component 2 is embedded, and the insulating layers 11 and 13 in which the conductor layers are placed, the stress when the composite electronic component 1 is mounted on a substrate such as a motherboard is reduced. As a result, the reliability of the composite electronic component 1 is improved.

[0044] On the other hand, the insulating layers 11 and 13 located between the coil patterns that are coupled to each other are made of a resin material that does not contain a core material, so the core material does not affect the coil characteristics. Furthermore, the insulating layer 12 into which the ESD protection component 2 is embedded is also made of a resin material that does not contain a core material, so the embedding is not hindered by the core material.

[0045] Furthermore, when the composite electronic component 1 is mounted on the circuit board, the number of turns, wiring length, and coil diameter of the coil patterns 45-48, which are further from the circuit board, are larger than those of the coil patterns 41-44, which are closer to the circuit board. As a result, the coil patterns 45-48, which have greater inductance, become less affected by the circuit board.

[0046] Furthermore, since coil patterns 41-44 are arranged on the other surface 12a side of the insulating layer 12 in which the ESD protection component 2 is embedded, and coil patterns 45-48 are arranged on the other surface 12b side, the inductance of each common mode filter can be sufficiently increased, and the warping of the composite electronic component 1 caused by the difference in thermal expansion coefficients between the insulating layers 11-14 and the ESD protection component 2 can be reduced.

[0047] Furthermore, since coil patterns 41-44 and coil patterns 45-48 are sufficiently separated in the stacking direction, and their pattern shapes, specifically their diameter and number of turns, are different from each other, magnetic coupling between them is suppressed. Therefore, even if the pattern shape of coil patterns 41-44 is changed for characteristic adjustment, the characteristics of coil patterns 45-48 hardly change, making design changes easy. Moreover, since the two coil patterns located in the same conductor layer are symmetrical in plan view, there is almost no difference in characteristics between the two common-mode filters, and pattern design is also simplified.

[0048] Next, a method for manufacturing the composite electronic component 1 according to this embodiment will be described.

[0049] Figures 11 to 23 are process diagrams illustrating the manufacturing method of the composite electronic component 1 according to this embodiment.

[0050] First, a carrier-attached copper foil 200 is prepared, and a resist pattern 201 is formed on its surface (Figure 11). The carrier-attached copper foil 200 has a structure in which a release layer is provided between two layers of copper foil. The resist pattern 201 is a negative pattern of the conductive layer C0. In this state, electrolytic plating is performed to remove the resist pattern 201 and form the conductive layer C0 (Figure 12). Next, an insulating layer 11 is formed on the surface of the carrier-attached copper foil 200 so that the conductive layer C0 is embedded (Figure 13). As a result, the conductive pattern located in the conductive layer C0 is covered on its sides and top by the insulating layer 11.

[0051] Next, a portion of the conductor layer C0 is exposed by forming vias 202 at the locations where via conductors should be formed, and then a seed layer 203 is formed on the surface of the insulating layer 11 by electroless plating (Figure 14). Here, since the insulating layer 11 does not contain a core material, it is possible to easily form vias 202. Next, a resist pattern 204 is formed on the surface of the seed layer 203, and then the conductor layer C1 is formed by electrolytic plating (Figure 15). Next, after removing the resist pattern 204 (Figure 16), an insulating layer 12A is formed on the surface of the insulating layer 11 so that the conductor layer C1 is embedded, and the ESD protection component 2 is mounted on its surface (Figure 17). As a result, the conductor pattern located in the conductor layer C1 is covered on the sides and top by the insulating layer 12A. Next, an insulating layer 12B is formed on the surface of the insulating layer 12A so that the ESD protection component 2 is embedded (Figure 18). As a result, the ESD protection component 2 is embedded in the insulating layer 12 consisting of insulating layers 12A and 12B.

[0052] Next, by repeating the process described using Figures 14 to 16, a conductive layer C2 is formed on the surface of the insulating layer 12, and then an insulating layer 13 is formed on the surface of the insulating layer 12 so that the conductive layer C2 is embedded (Figure 19). By repeating this process, a conductive layer C3 is formed on the surface of the insulating layer 13, and then an insulating layer 14 is formed on the surface of the insulating layer 13 so that the conductive layer C3 is embedded (Figure 20). Here, if a material in which the core material 15 is offset in the thickness direction to the opposite side of the conductive layer C3 is used as the material for the insulating layer 14, interference between the core material 15 and the conductive layer C3 becomes less likely. For example, by adjusting the temperature and time in the low-pressure and high-pressure states during the curing process of the insulating layer 14 by hot pressing, it is possible to offset the core material 15 to the side that contacts the insulating layer 14 and the solder resist layer 32 relative to the surface that contacts the insulating layers 13 and 14. Next, a conductive layer C4 is formed on the surface of the insulating layer 14, then one layer of copper foil is peeled off via a release layer provided on the carrier-attached copper foil 200 (Figure 21), and the remaining copper foil on the carrier-attached copper foil 200 is removed by etching (Figure 22). This etching also removes the seed layer used to form the conductive layer C4. Then, solder resists 31 and 32 are formed on the outermost surfaces of the insulating layers 11 and 14, respectively (Figure 23), and signal terminals 21-27 and ground terminals 28 and 29 are formed by surface treatment, completing the composite electronic component 1 according to this embodiment.

[0053] Thus, in the manufacturing process of the composite electronic component 1 according to this embodiment, a material in which a core material 15 is impregnated with resin is used as the material for the insulating layer 14 which serves as the base for the external terminals, while resin materials with excellent processability are used for the other insulating layers 11 to 13. As a result, it is possible to manufacture a composite electronic component 1 that is less prone to warping while keeping the process difficulty low.

[0054] While embodiments of the technology described herein have been explained above, it goes without saying that the technology described herein is not limited to the embodiments described above, and various modifications are possible without departing from its spirit, and these modifications are also included within the scope of the technology described herein.

[0055] For example, in the above embodiment, the ESD protection component 2 is embedded in the insulating layer 12, but the electronic components embedded in the insulating layer 12 are not limited to this. [Explanation of symbols]

[0056] 1. Composite electronic components 2 ESD protection parts (electronic parts) 10 Base Body 11-14, 12A, 12B Insulating layer 12a, 12b Surface of the insulating layer 15 Core material 20-27 Signal terminals 28,29 Ground terminal 31,32 Solder Resist 41-48 Coil Patterns 50-59 Conductor Pattern Conductor patterns 60, 61, 63~66, 68 70-76 Conductor Pattern 80~87 Terminal electrode 91, 93, 94, 97 Conductor patterns 100~107, 110~118, 120~127, 130~137, 141, 143, 144, 147 via conductors 200 Carrier-equipped copper foil 201 Resist Pattern 202 Beer 203 Seed Layer 204 Resist Patterns C0~C4 Conductor Layers CMF1~CMF4 Common Mode Filters G1, G2 gap GP Ground Pattern

Claims

1. A first insulating layer in which electronic components are embedded, A first wiring structure located on one surface side of the first insulating layer, comprising at least one second insulating layer and conductor layers arranged on both sides thereof, A second wiring structure comprising a plurality of third insulating layers located on the other surface side of the first insulating layer, having more layers than the second insulating layer, and conductor layers arranged on both sides thereof, Of the aforementioned plurality of third insulating layers, the insulating layer located on the outermost surface is made of a material in which a resin is impregnated into a core material, while the other insulating layers are made of a resin material that does not contain a core material. The first and second insulating layers are made of a resin material that does not contain a core material. A composite electronic component in which a portion of the first conductor layer located on the outermost surface of the conductor layers included in the second wiring structure constitutes an external terminal.

2. The aforementioned electronic component has a lower coefficient of thermal expansion than the insulating layer located at the outermost layer among the plurality of third insulating layers. Of the plurality of third insulating layers, the insulating layer located at the outermost surface has a smaller coefficient of thermal expansion than the second insulating layer. The composite electronic component according to claim 1, wherein the second insulating layer has a smaller coefficient of thermal expansion than the first insulating layer.

3. The composite electronic component according to claim 1, wherein the conductor layer included in the second wiring structure further includes a second conductor layer including a first coil pattern and a third conductor layer including a second coil pattern that overlaps with the first coil pattern in a plan view.

4. The first wiring structure further includes a fourth conductor layer containing a third coil pattern and a fifth conductor layer containing a fourth coil pattern that overlaps with the third coil pattern in a plan view. The third coil pattern is connected to the first coil pattern, The composite electronic component according to claim 3, wherein the fourth coil pattern is connected to the second coil pattern.

5. The composite electronic component according to any one of claims 1 to 4, wherein the insulating layer located on the outermost surface of the plurality of third insulating layers has the core material offset toward the first conductor layer in the thickness direction.

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