Exposure apparatus and exposure method

Abstract

To improve yield of semiconductor devices.SOLUTION: An exposure apparatus of an embodiment exposes a substrate. The exposure apparatus includes a stage, a storage device and a control device. The stage is constituted so as to be capable of holding the substrate. The storage device is constituted so as to be capable of storing a plurality of correction maps having alignment correction values different from each other. The control device selects one correction map from a plurality of correction maps on the basis of measurement results of a plurality of alignment marks arranged on the substrate or the amount of warp of the substrate. The control device controls an exposure position to the substrate by moving the stage on the basis of the selected one correction map.SELECTED DRAWING: Figure 13

Description

[Technical Field]

[0001] The embodiments relate to an exposure apparatus and an exposure method. [Background technology]

[0002] Three-dimensional stacking technology, which involves stacking semiconductor circuit boards in three dimensions, is well known. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2007-158200 [Overview of the project] [Problems that the invention aims to solve]

[0004] To improve the yield of semiconductor devices. [Means for solving the problem]

[0005] The exposure apparatus of the embodiment exposes a substrate. The exposure apparatus includes a stage, a storage device, and a control device. The stage is configured to hold the substrate. The storage device is configured to store a plurality of correction maps having different alignment correction values. The control device selects one correction map from the plurality of correction maps based on the measurement results of a plurality of alignment marks placed on the substrate or the amount of warping of the substrate. The control device controls the exposure position on the substrate by moving the stage based on the selected correction map. [Brief explanation of the drawing]

[0006] [Figure 1] A schematic diagram illustrating the general method for manufacturing a semiconductor device. [Figure 2] A schematic diagram showing an example of a possible overlap misalignment component that can occur during the manufacturing process of semiconductor devices. [Figure 3]Schematic diagram showing an example of the arrangement of alignment marks used in the manufacturing process of semiconductor devices. [Figure 4] Table showing an example of the correction performance of the overlay misalignment component in the in-plane of the wafer in an exposure apparatus and a bonding apparatus used in the manufacturing process of semiconductor devices. [Figure 5] Block diagram showing an example of the configuration of a semiconductor manufacturing system according to the first embodiment. [Figure 6] Block diagram showing an example of the configuration of an exposure apparatus according to the first embodiment. [Figure 7] Block diagram showing an example of the configuration of a bonding apparatus according to the first embodiment. <00所00076>Block diagram showing an example of the configuration of a server according to the first embodiment. [Figure 9] Flowchart showing an example of the exposure process of an exposure apparatus according to the first embodiment. [Figure 10] Schematic diagram showing an overview of the bonding process of a bonding apparatus according to the first embodiment. [Figure 11] Schematic diagram showing a specific example of the bonding sequence of a bonding apparatus according to the first embodiment. [Figure 12] Flowchart showing an example of a method for creating a map correction value used in an exposure apparatus according to the first embodiment. [Figure 13] Flowchart showing an example of a process related to alignment correction of random components in a semiconductor manufacturing system according to the first embodiment. [Figure 14] Schematic diagram showing an example of a method for improving the bonding overlay in the first comparative example. [Figure 15] Schematic diagram showing an example of a method for improving the bonding overlay in the first embodiment. [Figure 16] Diagram showing an example of the relationship between the wafer magnification and the polynomial regression coefficient in a bonded wafer manufactured by a semiconductor manufacturing system according to the second embodiment. [Figure 17] Flowchart showing an example of a method for creating an overlay correction formula used in an exposure apparatus according to the second embodiment. U [Figure 18]A flowchart showing an example of a process related to alignment correction of random components in a semiconductor manufacturing system according to the second embodiment. [Figure 19] A schematic diagram for explaining Zernike polynomials. [Figure 20] A block diagram showing an example of the configuration of a memory device according to the third embodiment. [Figure 21] A circuit diagram showing an example of the circuit configuration of a memory cell array included in a memory device according to the third embodiment. [Figure 22] A perspective view showing an example of the structure of a memory device according to the third embodiment. [Figure 23] A plan view showing an example of the planar layout of a memory cell array included in a memory device according to the third embodiment. [Figure 24] A cross-sectional view showing an example of the cross-sectional structure of a memory cell array included in a memory device according to the third embodiment. [Figure 25] A cross-sectional view taken along line XXV-XXV of FIG. 24, showing an example of the cross-sectional structure of a memory pillar included in a memory device according to the third embodiment. [Figure 26] A cross-sectional view showing an example of the cross-sectional structure of a memory device according to the third embodiment. [Figure 27] A flowchart showing an example of a method for creating map correction values used in an exposure apparatus according to the fourth embodiment. [Figure 28] A flowchart showing an example of a process related to alignment correction of random components in a semiconductor manufacturing system according to the fourth embodiment. [Figure 29] A schematic diagram showing an example of a method for improving a bonding overlay in the second comparative example. [Figure 30] A schematic diagram showing an example of a method for improving a bonding overlay in the fourth embodiment. [Figure 31] A diagram showing an example of the relationship between the warp amount of the upper wafer and the polynomial regression coefficient in a bonded wafer manufactured by a semiconductor manufacturing system according to the fifth embodiment. [Figure 32] A flowchart showing an example of a method for creating map correction values used in an exposure apparatus according to the fifth embodiment. [Figure 33] A flowchart showing an example of a process related to alignment correction of random components in a semiconductor manufacturing system according to the fifth embodiment. [Modes for carrying out the invention]

[0007] Embodiments are described below with reference to the drawings. Each embodiment exemplifies an apparatus or method for realizing the technical idea of ​​the invention. The drawings are schematic or conceptual. Dimensions and proportions in each drawing are not necessarily identical to those of reality. Illustrations of the components are omitted where appropriate. Hatching added to the drawings is not necessarily related to the material or properties of the components. In this specification, components having substantially the same function and configuration are given the same reference numeral. Numbers added to reference numerals are used to distinguish between elements that are referred to by the same reference numeral and are similar to each other.

[0008] The semiconductor device described herein is formed by joining two semiconductor circuit boards, each having a semiconductor circuit formed on it, and then separating the joined semiconductor circuit boards into individual chips. Hereinafter, a semiconductor circuit board is referred to as a "wafer." The process of joining two wafers is referred to as the "joining process." The apparatus used to perform the joining process is referred to as the "joining apparatus." The wafer placed on top during the joining process is referred to as the "upper wafer UW." The wafer placed on the bottom during the joining process is referred to as the "lower wafer LW." The pair of joined wafers, i.e., the upper wafer UW and the lower wafer LW, is referred to as the "joined wafer BW." In this specification, the X and Y directions are intersecting directions and are parallel to the surface of the wafer. The Z direction is intersecting directions with respect to both the X and Y directions and is perpendicular to the surface of the wafer. The "surface of the wafer" is the side on which the semiconductor circuit is formed by the preceding process described later. The "back surface of the wafer" is the side opposite to the surface of the wafer. In this specification, “up and down” is defined based on the direction along the Z-axis.

[0009] <Overview of Semiconductor Device Manufacturing Method> Figure 1 is a schematic diagram showing an overview of the semiconductor device manufacturing method. The general process flow in the semiconductor device manufacturing method described herein will be explained below with reference to Figure 1.

[0010] First, wafers are assigned to lots ("lot assignment"). A lot may contain multiple wafers. For example, lots can be classified into lots containing upper wafers (UW) and lots containing lower wafers (LW). Then, front-end processes are carried out on each of the lots containing upper wafers (UW) and lower wafers (LW), and semiconductor circuits are formed on each of them. Front-end processes include a combination of "exposure processing," "exposure OL (overlay) measurement," and "processing."

[0011] Exposure is a process that transfers the pattern of a mask onto a wafer coated with resist by irradiating the wafer with light transmitted through a mask. The area on which the mask pattern is transferred in a single exposure corresponds to "1 shot." A "shot" corresponds to the exposure area in the exposure process. In the exposure process, 1 shot of exposure is repeatedly performed with a shift in the exposure position. In other words, the exposure process is performed using a step-and-repeat method. In the exposure process, the arrangement and shape of each shot are corrected based on the measurement results of alignment marks (described later) and various correction values, and the overlap position with the underlying pattern formed on the wafer is adjusted (aligned). The arrangement (layout) of multiple shots on the upper wafer UW and the arrangement (layout) of multiple shots on the lower wafer LW are set to be the same. Hereafter, the device that performs the exposure process will be called the "exposure device." The correction values ​​used for the alignment of the overlap position, that is, the control parameters of the exposure device to suppress overlap misalignment, will be called "alignment correction values." When a polynomial is used to correct alignment, the coefficient of each term is called the "alignment correction coefficient." That is, the alignment correction value can be calculated based on the alignment correction coefficient of each term and the exposure position.

[0012] Exposure OL measurement is a process that measures the amount of overlap misalignment between the pattern formed by the exposure process and the underlying pattern for the exposure process. The measurement results of the overlap misalignment obtained by exposure OL measurement can be used for rework determination of the exposure process and for calculating alignment correction values ​​to be applied to subsequent lots. The processing process is a process in which the wafer is processed (e.g., etched) using the mask formed by the exposure process. Once the processing process is complete, the used mask is removed and the next process is performed.

[0013] Once the preceding process is complete, the bonding process is performed. In the bonding process, the bonding apparatus positions the surface of the upper wafer UW and the surface of the lower wafer LW facing each other. The bonding process then adjusts (aligns) the overlapping position of the pattern formed on the surface of the upper wafer UW and the pattern formed on the surface of the lower wafer LW. Then, the bonding apparatus bonds the surfaces of the upper wafer UW and the lower wafer LW together to form a bonded wafer BW.

[0014] For bonded wafers BW formed by the bonding process, bonded OL (overlay) measurement is performed. Bonded OL measurement is a process that measures the amount of overlap misalignment between the pattern formed on the surface of the upper wafer UW and the pattern formed on the surface of the lower wafer LW. The measurement results of the overlap misalignment obtained by bonded OL measurement can be used to calculate alignment correction values ​​to be applied to the exposure process of subsequent lots.

[0015] The amount of overlap misalignment that occurs during exposure and bonding processes can be expressed by a combination of various components. Figure 2 is a schematic diagram showing an example of overlap misalignment components that may occur in the manufacturing process of semiconductor devices. Figure 2 illustrates the mathematical formulas corresponding to each overlap misalignment component and the change in shape of one shot based on those formulas. As shown in Figure 2, the overlap misalignment components include, for example, (A) offset component, (B) magnification component, (C) rhombus (orthogonality) component, (D) eccentricity magnification component, (E) base formation component, (F) fan formation component, (G) C-shaped magnification component, (H) accordion formation component, (I) eccentric C-shaped distortion component, and (J) river flow formation component. Each of the overlap misalignment components (A) to (J) in Figure 2 further includes components in the X and Y directions.

[0016] The following lists the formulas corresponding to each component (A) to (J) in Figure 2. In the following formulas, "x" and "y" correspond to the X-coordinate and Y-coordinate, respectively. "dx" and "dy" are the superposition displacement amounts in the X and Y directions, respectively. "K1" to "K20" correspond to the coefficients (polynomial regression coefficients) of the superposition displacement components. (A) The offset (shift) component in the X direction is "dx = K1". The offset (shift) component in the Y direction is "dy = K2". (B) The magnification component in the X direction is "dx = K3·x". The magnification component in the Y direction is "dy = K4·y". (C) The rhombic (orthogonality) component in the X direction is "dx = K5·y". The rhombic (orthogonality) component in the Y direction is "dy = K6·x". (D) The eccentricity ratio component in the X direction is “dx = K7·x 2 The eccentricity component in the Y direction is "dy = K8·y 2 "That is the case." (E) The base forming component in the X direction is "dx = K9·x·y". The base forming component in the Y direction is "dy = K10·x·y". (F) The sector forming component in the X direction is “dx = K11·y 2 The sector forming component in the Y direction is "dy = K12·x 2 "That is the case." (G) The C-shaped magnification component in the X direction is "dx = K13·x 3 ". The C-shaped magnification component in the Y direction is "dy = K14·y 3 ". (H) The accordion formation component in the X direction is "dx = K15·x 2 ·y". The accordion formation component in the Y direction is "dy = K16·x·y 2 ". (I) The C-shaped distortion component in the X direction is "dx = K17·x·y 2 ". The C-shaped distortion component in the Y direction is "dy = K18·x 2 ·y". (J) The river flow formation component in the X direction is "dx = K19·y 3 ". The river flow formation component in the Y direction is "dy = K20·x 3 ".

[0017] That is, in this example, the misregistration amount Ex in the X direction is calculated by "Ex = K1 + K3·x + dy + K5·y + K7·x 2 + K9·x·y + K11·y 2 + K13·x 3 + K15·x 2 ·y + K17·x·y 2 + K19·y 3 ". The misregistration amount Ey in the Y direction is calculated by "Ey = K2 + K4·y + K6·x + K8·y 2 + K10·x·y + K12·x 2 + K14·y 3 + K16·x·y 2 + K18·x 2 ·y + K20·x 3 ". Note that when the misregistration component is expressed by polynomial regression, not only K₁ to K₂₀ but also coefficients assigned to higher-order misregistration components may be used as polynomial regression coefficients. In this specification, each of K₁ to K₂₀ is referred to as a "K value". That is, the measurement result of registration can be decomposed for each K value by polynomial regression.

[0018] In Figure 2, the overlap misalignment component at the shot level is illustrated, but the overlap misalignment component occurring within the wafer plane can also be represented by the same overlap misalignment component as at the shot level. Hereafter, the overlap misalignment component of the magnification component occurring within the wafer plane will also be referred to as the "wafer magnification." The exposure apparatus and the bonding apparatus each utilize the measurement results of alignment marks formed on the wafer for the alignment of the overlapping positions.

[0019] Figure 3 is a schematic diagram showing an example of the arrangement of alignment marks used in the manufacturing process of semiconductor devices. Figure 3(A) illustrates the position of alignment marks AM measured during exposure processing. Figure 3(B) illustrates the position of alignment marks AM on the upper wafer UW measured during bonding processing. Figure 3(C) illustrates the position of alignment marks AM on the lower wafer LW measured during bonding processing.

[0020] As shown in Figure 3(A), the exposure apparatus can measure alignment marks AM at multiple points (at least three or more) placed on the wafer during the exposure process. The exposure apparatus can then calculate correction values ​​for overlap misalignment components such as shift components, magnification components, and orthogonality components in the X and Y directions by approximating the measurement results of the multiple alignment marks AM using a function in a Cartesian coordinate system. This allows the exposure apparatus to correct both the overlap misalignment component on a shot-by-shot basis and the overlap misalignment component within the wafer plane.

[0021] Furthermore, the exposure apparatus can set, for example, the correction amount for the shift component, the correction amount for the magnification component, and the correction amount for the orthogonality component for each shot. In this specification, the alignment correction method using the alignment correction values ​​set for each shot is called "exposure map correction." The set of alignment correction values ​​for each shot used in exposure map correction is called "map correction values." Map correction values ​​can be created based on exposure OL measurement results, bond OL measurement results, etc. "Map correction values" may also be called "exposure position correction maps" or "correction maps." At least one of the shift component, magnification component, and orthogonality component is required as the alignment correction value for each shot applied in exposure map correction. In this way, the exposure apparatus can correct complex overlap misalignment components.

[0022] As shown in Figures 3(B) and (C), the bonding apparatus measures at least three alignment marks AM_C, AM_L, and AM_R located on the upper wafer WU and lower wafer LW during the bonding process. Alignment mark AM_C is located near the center of the wafer. Based on the measurement result of alignment mark AM_C, the bonding apparatus aligns the shift component of the wafer. Alignment marks AM_L and AM_R are located on one and the other side of the outer periphery of the wafer, respectively. Based on the measurement results of alignment marks AM_L and AM_R, the bonding apparatus aligns the rotation component of the wafer (the same orthogonality component in the X and Y directions). In this way, the bonding apparatus can calculate correction values ​​for the shift and rotation components using at least three alignment marks AM_C, AM_L, and AM_R, and correct simple overlap misalignment components within the wafer surface.

[0023] Furthermore, the bonding apparatus can correct the wafer magnification by deforming the stage that holds the wafer. When correcting the wafer magnification, the bonding apparatus may use, for example, the alignment correction value of the wafer magnification used in the exposure process, or the wafer magnification value calculated based on the measurement results of the exposure OL. The bonding apparatus can measure the alignment marks AM of the upper wafer UW and the lower wafer LW in parallel. For example, the alignment marks AM_C of the upper wafer UW and the lower wafer LW are measured simultaneously due to the constraints on the placement of the alignment marks AM, and are therefore positioned offset from the wafer center in opposite directions.

[0024] Figure 4 is a table showing an example of the correction performance of overlap misalignment components within the wafer surface in exposure and bonding equipment used in the manufacturing process of semiconductor devices. As shown in Figure 4, the shift component can be corrected in both the exposure and bonding equipment. The wafer magnification that is common in the X and Y directions (XY common magnification component) can be corrected in both the exposure and bonding equipment. The wafer magnification that differs between the X and Y directions (XY difference magnification component) can be corrected in the exposure equipment. On the other hand, the XY difference magnification component is difficult to correct in the bonding equipment. The rotation component can be corrected in both the exposure and bonding equipment. The rotation component that differs between the X and Y directions (i.e., orthogonality component) can be corrected in the exposure equipment. On the other hand, the orthogonality component is difficult to correct in the bonding equipment. The overlap misalignment component that occurs randomly within the wafer surface (random component) can be corrected on a shot-by-shot basis in the exposure equipment. On the other hand, the random component is difficult to correct in the bonding equipment.

[0025] [1] First Embodiment In the exposure apparatus 1 according to the first embodiment, a map correction value capable of suppressing the generation of random components in the bonded OL is selected based on the wafer magnification during the exposure process. Details of the exposure apparatus 1 according to the first embodiment are described below.

[0026] [1-1] Composition [1-1-1] Configuration of the semiconductor manufacturing system PS Figure 5 is a block diagram showing an example of the configuration of a semiconductor manufacturing system PS according to the first embodiment. As shown in Figure 5, the semiconductor manufacturing system PS includes, for example, an exposure apparatus 1, a bonding apparatus 2, and a server 3.

[0027] The exposure apparatus 1, bonding apparatus 2, and server 3 are configured to communicate via a network NW. The network NW may utilize either wired or wireless communication. The bonding apparatus 2 performs bonding using the upper wafer UW and lower wafer LW, which were used in the previous step by exposure apparatus 1, to create a bonded wafer BW. Server 3 is, for example, a computer that controls the entire semiconductor manufacturing process. Server 3 manages lot processing steps and correction values ​​used in each manufacturing step. The semiconductor manufacturing system PS may also include superposition measurement devices.

[0028] [1-1-2] Configuration of exposure apparatus 1 Figure 6 is a block diagram showing an example of the configuration of an exposure apparatus 1 according to the first embodiment. As shown in Figure 6, the exposure apparatus 1 includes, for example, a control device 10, a storage device 11, a transport device 12, a communication device 13, and an exposure unit 14.

[0029] The control device 10 is a computer or similar device that controls the overall operation of the exposure apparatus 1. The control device 10 controls the storage device 11, the transport device 12, the communication device 13, and the exposure unit 14. Although not shown in the diagram, the control device 10 includes a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), etc. The CPU is a processor that executes various programs related to the control of the apparatus. ROM is a non-volatile storage medium that stores the control programs of the apparatus. RAM is a volatile storage medium used as the CPU's workspace.

[0030] The storage device 11 is a storage medium used to store data, programs, and the like. The storage device 11 stores, for example, an exposure recipe 110, correction value information 111, and a map correction value set 112. The exposure recipe 110 is a table in which the settings for the exposure process are recorded. The exposure recipe 110 includes information such as the shape and layout of the shot, the amount of exposure, the focus setting, and the alignment setting. The exposure recipe 110 may be prepared for each processing step or processing lot. The correction value information 111 is a log that records the alignment correction values ​​(i.e., alignment results) used when the exposure process was performed. The map correction value set 112 includes multiple map correction values. The map correction values ​​include the alignment correction values ​​for each shot. The method for creating map correction values ​​will be described later.

[0031] The transport device 12 is equipped with a transport arm capable of transporting wafers and a transition for temporarily placing multiple wafers. For example, the transport device 12 transports wafers WF received from an external coating and developing device to the exposure unit 14. After the exposure process, the transport device 12 transports the wafers WF received from the exposure unit 14 to the outside of the exposure device 1. The "coating and developing device" is an apparatus that performs pre-processing and post-processing of the exposure process. The pre-processing of the exposure process includes the process of coating the wafer with a resist material (photosensitive material). The post-processing of the exposure process includes the process of developing the pattern exposed on the wafer. Multiple semiconductor manufacturing apparatuses may be used as the apparatus for the pre-processing and post-processing of the exposure process.

[0032] The communication device 13 is a communication interface that can connect to a network. The exposure device 1 may operate based on operations performed by a terminal on the network, or it may store the exposure recipe 110 and correction value information 111 on a server on the network.

[0033] The exposure unit 14 is a set of components used in the exposure process. The exposure unit 14 includes, for example, a wafer stage 140, a reticle stage 141, a light source 142, a projection optical system 143, and a camera 144. The wafer stage 140 has the function of holding the wafer WF. The reticle stage 141 has the function of holding the reticle RT (mask). The respective stage positions of the wafer stage 140 and the reticle stage 141 can be controlled based on the control of the control device 10. The light source 142 irradiates the reticle RT with the light it generates. The projection optical system 143 focuses the light that has passed through the reticle RT onto the surface of the wafer WF. The camera 144 is an imaging mechanism used to measure alignment marks AM.

[0034] [1-1-3] Configuration of the joining device 2 Figure 7 is a block diagram showing an example of the configuration of the joining device 2 according to the first embodiment. As shown in Figure 7, the joining device 2 includes, for example, a control device 20, a transport device 21, a communication device 22, and a joining unit 23.

[0035] The control device 20 is a computer that controls the overall operation of the bonding apparatus 2. The control device 20 controls the transport apparatus 21, the communication apparatus, and the bonding unit 23. Although not shown in the illustration, the control device 20 includes a CPU, ROM, RAM, etc., similar to the exposure apparatus 1.

[0036] The transport device 21 is a device equipped with a transport arm capable of transporting wafers and a transition for temporarily placing multiple wafers. For example, the transport device 21 transports the upper wafer UW and lower wafer LW received from the pre-processing device for bonding to the bonding unit 23. After the bonding process, the transport device 21 transports the bonded wafer BW received from the bonding unit 23 to the outside of the bonding device 2. The transport device 21 may also be equipped with a mechanism for inverting the wafers.

[0037] The communication device 22 is a communication interface that can be connected to a network NW. The connecting device 2 may operate based on the control of a terminal on the network NW, or it may store operation logs on a server 3 on the network NW, or it may calculate alignment correction values ​​based on the information stored on the server 3.

[0038] The bonding unit 23 is a set of components used in the bonding process. The bonding unit 23 includes, for example, a lower stage 230, a stress device 231, a camera 232, an upper stage 233, a pressing pin 234, and a camera 235. The lower stage 230 has the function of holding the lower wafer LW. The lower stage 230 includes, for example, a wafer chuck that holds the wafer by vacuum suction. The stress device 231 has the function of applying stress to the lower stage 230 and deforming the lower wafer LW through the lower stage 230. Depending on the amount of deformation of the lower stage 230 by the stress device 231, the amount of expansion (scaling) of the lower wafer LW held in the lower stage 230 changes. The camera 232 is located on the lower stage 230 side and is an imaging mechanism used to measure the alignment mark AM of the upper wafer UW. The upper stage 233 has the function of holding the upper wafer UW. The upper stage 233 includes, for example, a wafer chuck that holds the wafer by vacuum suction. The pressing pin 234 is a pin that is driven vertically based on the control of the control device 20 and can press the upper surface of the center of the upper wafer UW held on the upper stage 233. The camera 235 is an imaging mechanism located on the upper stage 233 side and used to measure the alignment mark AM of the lower wafer LW. The bonding apparatus 2 may have a vacuum pump used for vacuum adsorption of the lower stage 230 and the upper stage 233.

[0039] The lower stage 230 and the upper stage 233 are configured to allow the lower wafer LW held on the lower stage 230 and the upper wafer UW held on the upper stage 233 to be positioned opposite each other. That is, the upper stage 233 can be positioned above the lower stage 230. In other words, the lower stage 230 and the upper stage 233 can face each other. In the bonding process, the upper surface of the upper wafer UW is the back surface of the upper wafer UW and is held on the upper stage 233 of the bonding apparatus 2. In the bonding process, the lower surface of the upper wafer UW is the front surface of the upper wafer UW and corresponds to the bonding surface. The upper surface of the lower wafer LW is the front surface of the lower wafer LW and corresponds to the bonding surface. The lower surface of the lower wafer LW is the back surface of the lower wafer LW and is held on the lower stage 230 of the bonding apparatus 2. The bonding apparatus 2 can adjust the shift component and rotation component of the overlap misalignment by adjusting the relative positions of the lower stage 230 and the upper stage 233. Furthermore, the bonding apparatus 2 can adjust the XY common wafer magnification of the lower wafer LW held on the deformed lower stage 230 by deforming the lower stage 230 with the stress device 231.

[0040] The “pre-treatment device for bonding” described above is a device that modifies and hydrophilizes the bonding surfaces of the upper wafer UW and lower wafer LW before the bonding process of the bonding device 2. Briefly, the pre-treatment device first performs plasma treatment on the surfaces of the upper wafer UW and lower wafer LW to modify their surfaces. In the plasma treatment, oxygen ions or nitrogen ions are generated from oxygen gas or nitrogen gas, which are the processing gases, under a predetermined reduced-pressure atmosphere, and the generated oxygen ions or nitrogen ions are irradiated onto the bonding surfaces of each wafer. After that, the pre-treatment device supplies pure water to the surfaces of the upper wafer UW and lower wafer LW. As a result, hydroxyl groups adhere to the surfaces of the upper wafer UW and lower wafer LW, making the surfaces hydrophilic. In the bonding process, the upper wafer UW and lower wafer LW, whose bonding surfaces have been modified and hydrophilized in this way, are used. The bonding device 2 may be combined with the pre-treatment device and the like to constitute a bonding system.

[0041] [1-1-4] Server 3 Configuration Figure 8 is a block diagram showing an example of the configuration of a server 3 according to the first embodiment. As shown in Figure 8, the server 3 includes, for example, a CPU 30, a ROM 31, a RAM 32, a storage device 33, and a communication device 34. The CPU 30 is a processor that executes various programs related to the control of the server 3. The ROM 31 is a non-volatile storage device that stores the control programs of the server 3. The RAM 32 is a volatile storage device used as a workspace for the CPU 30. The storage device 33 is a non-volatile storage medium capable of storing information received from the exposure device 1, bonding device 2, etc. The communication device 34 is a communication interface that can be connected to a network NW.

[0042] [1-2] Method for manufacturing semiconductor devices Below, we will describe a specific example of a process using the exposure apparatus 1 as a method for manufacturing a semiconductor device according to the first embodiment. That is, a semiconductor device is manufactured using the exposure method (exposure process) of the first embodiment described below.

[0043] [1-2-1] Overview of exposure process Figure 9 is a flowchart showing an example of the exposure process of the exposure apparatus 1 according to the first embodiment. The outline of the exposure process of the exposure apparatus 1 will be described below with reference to Figure 9.

[0044] When the exposure apparatus 1 is notified by the coating and developing apparatus that the wafer pretreatment is complete, it starts the exposure process (start).

[0045] First, the exposure apparatus 1 loads a wafer (S100). The wafer loaded from the coating and developing apparatus is held by the wafer stage 140.

[0046] Next, the exposure apparatus 1 checks the exposure recipe 110 (S101). Based on this, the control device 10 determines the processing conditions to be applied to the loaded wafer.

[0047] Next, the exposure apparatus 1 measures the alignment marks AM (S102). Specifically, the camera 144 photographs multiple alignment marks AM placed at predetermined positions on the wafer.

[0048] Next, the exposure apparatus 1 performs alignment correction processing (S103). Specifically, the control device 10 calculates alignment correction values ​​such as the shot arrangement and shot shape to be exposed on the wafer based on the measurement results of multiple alignment marks AM. Furthermore, the exposure apparatus 1 according to the first embodiment selects a map correction value based on the wafer magnification correction value included in the calculated alignment correction value and uses it for alignment. For this reason, in the exposure apparatus 1 according to the first embodiment, when exposure processing is performed continuously on multiple wafers included in one lot, different map correction values ​​may be applied to each wafer.

[0049] Next, the exposure apparatus 1 executes the exposure sequence (S104). Specifically, the control device 10 controls the light source 142, wafer stage 140, and reticle stage 141 based on the alignment correction value calculated in S103 to irradiate the wafer with light that has passed through the mask in a step-and-repeat manner.

[0050] Next, the exposure apparatus 1 updates the correction value information 111 (S105). That is, in S105, the alignment correction value calculated in S103 is associated with the processed wafer and recorded in the correction value information 111.

[0051] Next, the exposure apparatus 1 unloads the wafer (S106). The unloaded wafer is then passed to the coating and developing apparatus. The coating and developing apparatus performs processes such as heat treatment, development, and cleaning on the wafer after the exposure process is complete. This forms a pattern on the wafer.

[0052] When the wafer is unloaded, the exposure apparatus 1 terminates the exposure process (end).

[0053] [1-2-2] Overview of the joining process Figure 10 is a schematic diagram showing an overview of the joining process of the joining device 2 according to the first embodiment. In the joining process, (1) to (8) in Figure 10 each show the state of the joining unit 23 during the joining process. The overview of the joining process will be described below with reference to Figure 10. In the following description, the alignment of the shift component will be referred to as "shift alignment," and the alignment of the rotational component will be referred to as "rotational alignment."

[0054] Figure 10(1) shows the state of the joining unit 23 before the joining process.

[0055] When the bonding process begins, the control device 20 controls the stress device 241 based on a common wafer magnification alignment correction value in the X and Y directions to deform the lower stage 240 as shown in Figure 10 (2). The bonding device 2 may obtain such alignment correction values ​​from the server 3, or it may calculate them based on alignment correction values ​​obtained from the exposure device 1 or the server 3.

[0056] Next, the control device 20 instructs the transport device 21 to transport the lower wafer LW to the lower stage 230 and the upper wafer UW to the upper stage 233. Then, as shown in Figure 10 (3), the control device 20 causes the lower stage 230 to hold the lower wafer LW and the upper stage 233 to hold the upper wafer UW. The surfaces of the upper wafer UW and lower wafer LW that are transported to the bonding device 2 have been modified and hydrophilized by a pre-treatment device for the bonding process.

[0057] Next, the control device 20 performs rotational alignment. Specifically, as shown in (4) of Figure 10, the control device 20 first controls the positions of the lower stage 230 and the upper stage 233 to align the optical axis of the camera 232 on the lower stage 230 with the alignment mark AM_L on the upper wafer UW, and align the optical axis of the camera 235 on the upper stage 233 with the alignment mark AM_L on the lower wafer LW. Then, the control device 20 measures the alignment mark AM_L on the upper wafer UW using the camera 232 and measures the alignment mark AM_L on the lower wafer LW using the camera 235.

[0058] Next, as shown in (5) of Figure 10, the control device 20 controls the positions of the lower stage 230 and the upper stage 233 to align the optical axis of the camera 232 on the lower stage 230 with the alignment mark AM_R on the upper wafer UW, and align the optical axis of the camera 235 on the upper stage 233 with the alignment mark AM_R on the lower wafer LW. Then, the control device 20 measures the alignment mark AM_R on the upper wafer UW using camera 232 and measures the alignment mark AM_R on the lower wafer LW using camera 235. After that, the control device 20 calculates the correction amount for the rotational component superposition misalignment based on the measurement results of the alignment marks AM_L and AM_R obtained by cameras 232 and 235 through the processes in (4) and (5) of Figure 10.

[0059] Next, the control device 20 performs camera origin alignment. Specifically, as shown in (6) of Figure 10, the control device 20 controls the positions of the lower stage 230 and the upper stage 233 to insert a common target 236 between the optical axis of camera 232 on the lower stage 230 and the optical axis of camera 235 on the upper stage 233. Then, based on the measurement results of the common target 236 by cameras 232 and 235, the control device 20 aligns the origins of cameras 232 and 235, respectively.

[0060] Next, the control device 20 performs shift alignment. Specifically, as shown in (7) of Figure 10, the control device 20 first controls the positions of the lower stage 230 and the upper stage 233 to align the optical axis of the camera 232 on the lower stage 230 with the alignment mark AM_C on the upper wafer UW, and align the optical axis of the camera 235 on the upper stage 233 with the alignment mark AM_C on the lower wafer LW. Then, the control device 20 measures the alignment mark AM_C on the upper wafer UW using camera 232 and the alignment mark AM_C on the lower wafer LW using camera 235. After that, the control device 20 calculates the alignment correction value of the shift component based on the measurement results of the alignment marks AM_C on the lower wafer LW and the upper wafer UW.

[0061] Next, the control device 20 executes the bonding sequence as shown in (8) of Figure 10. Specifically, first, the control device 20 performs horizontal alignment based on the alignment correction values ​​calculated from rotational alignment and shift alignment, respectively, and the calibration result of the camera origin, and adjusts the relative position of the lower stage 230 and the upper stage 233. Then, the control device 20 moves the upper stage 233 closer to the lower stage 230 to adjust the distance between the upper wafer UW and the lower wafer LW. After that, the control device 20 pushes down the center of the upper wafer UW by lowering the pressing pin 244, bringing the surface of the upper wafer UW into contact with the surface of the lower wafer LW.

[0062] Subsequently, the control device 20 sequentially releases the upper wafer UW from the upper stage 243 (vacuum adsorption) from the inside outwards. As a result, the upper wafer UW falls onto the lower wafer LW, and the surfaces of the upper wafer UW and the lower wafer LW are joined together. Specifically, van der Waals forces (intermolecular forces) are generated between the modified bonding surface of the upper wafer UW and the modified bonding surface of the lower wafer LW, and the contact portions of the upper wafer UW and the lower wafer LW are joined together. Furthermore, since the bonding surfaces of the upper wafer UW and the lower wafer LW are hydrophilic, the hydrophilic groups in the contact portions of the upper wafer UW and the lower wafer LW form hydrogen bonds (intermolecular forces), and the contact portions of the upper wafer UW and the lower wafer LW are joined together more firmly.

[0063] [1-2-3] Specific examples of junction sequences Figure 11 is a schematic diagram showing a specific example of the bonding sequence of the bonding apparatus 2 according to the first embodiment. The times T1 to T5 in Figure 11 represent consecutive times in the bonding sequence. The "plane" in Figure 11 shows the state of vacuum adsorption to the upper wafer UW and the progress of bonding. The "cross-section" in Figure 11 shows a cross-section of the upper wafer UW along the XX line shown in the "plane" of Figure 11. A specific example of the bonding sequence will be described below with reference to Figure 11.

[0064] First, the upper wafer UW is held on the upper stage 233 by vacuum adsorption in each of the regions CRV, DIV, and CEV (time T1). Specifically, four regions CRV are arranged so as to include the vertices of an X shape. Four regions DIV are arranged so as to include the vertices of a cross shape. The regions CRV and DIV are arranged alternately near the outer periphery of the upper wafer UW. As a result, the combination of regions CRV and DIV forms a ring-shaped region near the outer periphery of the upper wafer UW. Region CEV is a ring-shaped region surrounding the central part of the upper wafer UW in a plan view, and is surrounded by a combination of regions DIV and CRV. The pressing pin 334 is located in the central part of region CEV.

[0065] Then, the control device 20 releases the vacuum adsorption of regions DIV and CEV, and uses the pressing pin 234 to push down the center of the upper wafer UW, bringing the surface of the upper wafer UW into contact with the surface of the lower wafer LW. As a result, the bonding region BA expands from the center of the upper wafer UW toward the outer edge (time T2).

[0066] As time elapses from time T2, bonding progresses in the upper wafer UW in the adjacent region CRV. On the other hand, bonding in the region CRV of the upper wafer UW does not progress because it is vacuum-adsorbed by the upper stage 233 (time T3). Due to this difference in bonding progress, localized stress may be generated in the upper wafer UW. As a result, the portion of the upper wafer UW where localized stress has occurred may be bonded to the lower wafer LW in a distorted state. Hereafter, the portion of the upper wafer UW that is bonded to the lower wafer LW in a distorted state will be referred to as the "distorted portion DP".

[0067] Subsequently, the control device 20 releases the vacuum adsorption of region CRV. Then, the portion of the upper wafer UW that was held by the upper stage 233 in region CRV falls to the lower wafer LW side, and as time progresses, the bonding region BA is formed up to the outermost periphery of the upper wafer UW (times T4-T5). That is, the bonding region BA is formed over the entire bonding surface between the upper wafer UW and the lower wafer LW, and the bonding of the upper wafer UW and the lower wafer LW in that bonding sequence is completed.

[0068] [1-2-4] How to create map correction values Figure 12 is a flowchart showing an example of a method for creating map correction values ​​used in the exposure apparatus 1 according to the first embodiment. An example of a method for creating map correction values ​​will be described below with reference to Figure 12.

[0069] First, multiple lower wafers LW are prepared by exposing them with different wafer magnifications in a predetermined exposure process (S110). That is, in S110, two or more lower wafers LW with different wafer magnifications are prepared. The predetermined exposure process in S110 corresponds to the exposure process of the wiring layer near the surface of the lower wafer LW and is a process that has a significant impact on the bonding OL. In this specification, this predetermined exposure process is also referred to as the "exposure process of the bonding surface of the lower wafer LW".

[0070] Next, multiple upper wafers UW are prepared by exposing them with a fixed wafer magnification in a predetermined exposure process (S111). The predetermined exposure process in S111 corresponds to the exposure process of the wiring layer near the surface of the upper wafer UW and is a process that has a significant impact on the bonding OL. In this specification, this predetermined exposure process is also referred to as the "exposure process of the bonding surface of the upper wafer UW".

[0071] Next, the wafer magnification of each of the multiple lower wafers is corrected so that the wafer magnification set in S110 becomes equivalent to the wafer magnification set in S111, and the bonding process of the lower wafer LW and the upper wafer UW is performed (S112). That is, in S112, the lower wafer LW is held in a state where the lower stage 230 has been deformed to a shape based on the wafer magnification set in S110, and the lower wafer LW and the upper wafer UW are bonded together. As a result, for each lower wafer LW with a different wafer magnification, a bonding process corrected to match the wafer magnification of the upper wafer UW is performed.

[0072] Next, bonding OL measurement is performed (S113). This bonding OL measurement provides bonding OL measurement results for each wafer magnification set in S110. The bonding OL measurement results are stored, for example, in server 3.

[0073] Next, the server 3 creates a map correction value (S114) that associates the wafer magnification correction value with the bonding OL measurement result, based on the bonding OL measurement result in S113. The created map correction values ​​are then stored in the storage device 11 of the exposure apparatus 1 as a map correction value set 112. Each map correction value is associated with, for example, wafer magnification correction values ​​within a predetermined range that differs from each other. This predetermined range is set, for example, based on the wafer magnification correction value set in S110.

[0074] [1-2-5] Flow from exposure treatment to bonding treatment Figure 13 is a flowchart showing an example of a process related to the alignment correction of random components in the semiconductor manufacturing system PS according to the first embodiment. The flow from exposure processing to bonding processing in the first embodiment will be described below with reference to Figure 13.

[0075] First, the pre-processing steps for the upper wafer UW and the lower wafer LW are performed. Specifically, in the pre-processing step for the upper wafer UW, the exposure process for the upper wafer UW is performed (S120). Correction value information 111a, including the wafer magnification correction value used in the exposure process of S120, is stored in the server 3 (S121). Meanwhile, in the pre-processing step for the lower wafer LW, the exposure process for the lower wafer LW is performed using a map correction value based on the wafer magnification correction value used (S130). Specifically, in the exposure process of S130, the exposure apparatus 1 calculates the alignment correction coefficient of the magnification component in the wafer plane based on the measurement results of at least three alignment marks, and selects one correction map from multiple correction maps based on the magnitude of the calculated alignment correction coefficient of the magnification component. For example, as a map correction value to be applied to a wafer with a large wafer magnification, the exposure apparatus 1 selects a map correction value created based on the bonding OL measurement results of a bonded wafer BW using the lower wafer LW, which was set to a large wafer magnification in S110. Furthermore, the exposure apparatus 1 selects a map correction value to be applied to wafers with a small wafer magnification, based on the bonding OL measurement results of the bonding wafer BW using the lower wafer LW, which was set to a small wafer magnification in S110. Then, the correction value information 111b, including the wafer magnification correction value used in the exposure process in S130, is stored in the server 3 (S131).

[0076] Once the processing of the preceding steps for the upper wafer UW and the lower wafer LW is completed (S140), the server 3 calculates a correction value for the wafer magnification in the bonding process based on the correction value information 111a and 111b stored in S121 and S131, respectively (S141). Specifically, in S141, the difference between the processing value of the wafer magnification in the upper wafer UW (alignment correction value + overlay correction value) and the processing value of the wafer magnification in the lower wafer LW (alignment correction value + overlay correction value) is calculated. The server 3 then feeds forward the calculation result of S141 to the bonding apparatus 2. In this example, the "alignment correction value" is a correction value for the overlap misalignment component calculated based on the measurement result of the alignment mark AM. The "overlay correction value" is a correction value calculated based on the result of exposure OL measurement in advanced process control performed during large-scale lot processing, for example.

[0077] Subsequently, the bonding apparatus 2 performs the bonding process using the wafer magnification correction value calculated in S141. That is, the bonding apparatus 2 determines the wafer magnification correction value for the bonding process based on the alignment results of the exposure processes of the upper wafer UW and lower wafer LW in the previous process. In other words, during the bonding process, the bonding apparatus 2 controls the stress device 231 based on the difference in the alignment results of the exposure processes of the upper wafer UW and lower wafer LW in the previous process to deform the lower stage 230 (Figure 10 (2)). Other operations in the bonding process are the same as those described using Figure 10.

[0078] The above explanation illustrates the case where server 3 is used to determine the wafer magnification correction value in the bonding process, but is not limited to this. The exposure apparatus 1 or bonding apparatus 2 may calculate the wafer magnification correction value in the bonding process. In this case, information regarding the wafer magnification correction value is exchanged between the exposure apparatus 1 and bonding apparatus 2. If there is no map correction value associated with the wafer magnification correction value, the exposure apparatus 1 may use a map correction value associated with a wafer magnification correction value that is close to the wafer magnification correction value, or it may use a map correction value calculated based on a combination of multiple map correction values. Alternatively, the exposure apparatus 1 or server 3 may create a relationship formula between the wafer magnification and the correction value for each shot based on multiple combinations of wafer magnification and map correction values, and use a map correction value based on this relationship formula in the exposure process.

[0079] [1-3] Effects of the first embodiment The exposure apparatus 1 according to the first embodiment described above can improve the yield of semiconductor devices. The effects of the exposure apparatus 1 according to the first embodiment will be described in detail below.

[0080] In semiconductor devices formed by joining two wafers, the wafer magnification (i.e., wafer size) of one wafer and the other wafer before joining may differ. For example, the wafer magnification can vary depending on the film stress (i.e., wafer warpage) on the front and back surfaces of the wafer. Therefore, the variation in wafer magnification between one wafer and the other wafer may differ depending on the design of the circuits and elements. Furthermore, as explained using Figure 3, the joining apparatus 2 has difficulty correcting the overlapping misalignment of random components. For this reason, the strained area DP explained using Figure 11 can be a cause of overlapping misalignment of random components in the joining overlay (OL). As a method to suppress the overlapping misalignment of random components in the joining wafer BW, it is conceivable to use exposure map correction in a predetermined exposure process in the preceding step that improves the joining OL.

[0081] Here, using a comparative example, an example of a method for improving the bonding overlay in the first embodiment will be described. In this example, it is assumed that the variation in wafer magnification in the preprocessing of the upper wafer UW is small, and the variation in wafer magnification in the preprocessing of the lower wafer LW is large. In the following description, "good overlap" corresponds to suppressing the overlap misalignment between the background pattern and the pattern formed by the exposure process during the exposure process, and to suppressing the overlap misalignment between the pattern of the upper wafer UW and the pattern of the lower wafer LW during the bonding process. "Poor overlap" corresponds to the existence of areas where the overlap misalignment between the background pattern and the pattern formed by the exposure process is large during the exposure process, and to the existence of areas where the overlap misalignment between the pattern of the upper wafer UW and the pattern of the lower wafer LW is large during the bonding process.

[0082] Figure 14 is a schematic diagram showing an example of a method for improving the bonding overlay in the first comparative example. Figures 14(A) and (B) correspond to before and after applying exposure map correction, respectively, and show the results of lot exposure OL measurement and bonding OL measurement. It is assumed that the overlay in the exposure OL of the upper wafer UW is good both before and after applying exposure map correction.

[0083] As shown in Figure 14(A), in the exposure process of the preceding step, the lower wafer LW1 has a large wafer magnification correction amount (large Mag correction amount), while the lower wafer LW2 has a small wafer magnification correction amount (small Mag correction amount). In the exposure OL measurements of lower wafers LW1 and LW2, the overlap is good. Then, the bonding process is performed with the wafer magnification of lower wafers LW1 and LW2 corrected respectively. In this example, in both bonded wafer BW1, which is formed by bonding lower wafer LW1 and upper wafer UW, and bonded wafer BW2, which is formed by bonding lower wafer LW2 and upper wafer UW, there remains an overlap misalignment of the random component due to the wafer magnification correction in the bonding process. Therefore, the overlap is poor in the bonding OL measurements of bonded wafers BW1 and BW2, respectively.

[0084] In the first comparative example, a map correction value MCV1 is created based on the bonding OL measurement results of the bonded wafer BW1, and the map correction value MCV1 is used for processing subsequent lots. Then, as shown in Figure 14(B), in the exposure OL measurement of subsequent lots, the exposure OL of the lower wafer LW3, which has a large wafer magnification correction amount, and the lower wafer LW4, which has a small wafer magnification correction amount, may worsen due to the application of the map correction value MCV1. This is because the use of a map correction value that can improve the overlap of the bonding process may cause an overlap misalignment between the pattern formed by the exposure process and the underlying pattern. The bonding OL measurement results for bonded wafer BW3, in which the lower wafer LW3 and the upper wafer UW are bonded, may be good because the overlap misalignment of random components is suppressed due to the use of the map correction value MCV1 in the exposure process of the lower wafer LW3. However, the tendency of the overlap misalignment of random components may change depending on the wafer magnification correction amount. Therefore, in the bonded wafer BW4, which is formed by joining the lower wafer LW4 and the upper wafer UW, the amount of Mag correction in the exposure process is small, while the map correction value MCV1, which corresponds to a "large Mag correction amount," is used. As a result, the improvement in the superposition misalignment of random components may be worse than in the bonded wafer BW3.

[0085] Therefore, the exposure apparatus 1 according to the first embodiment has a function to select the map correction value MCV to be used in the exposure process according to the correction value of the wafer magnification.

[0086] Figure 15 is a schematic diagram showing an example of a method for improving bonding overlay in the first embodiment. Figures 15(A) and (B) correspond to before and after applying exposure map correction in the first embodiment, respectively, and show the results of lot exposure OL measurement and bonding OL measurement. It is assumed that the overlay in the exposure OL of the upper wafer UW is good both before and after applying exposure map correction. As shown in Figure 15(A), the example before applying exposure map correction in the first embodiment is the same as the example before applying exposure map correction in the first comparative example.

[0087] In the first embodiment, a map correction value MCV1 is created based on the wafer magnification correction amount used in the exposure process of the lower wafer LW1 and the result of the bonding OL measurement of the bonding wafer BW1, and a map correction value MCV2 is created based on the wafer magnification correction amount used in the exposure process of the lower wafer LW2 and the result of the bonding OL measurement of the bonding wafer BW2. Then, map correction values ​​MCV1 and MCV2 are stored in the storage device 11 of the exposure apparatus 1 as a map correction value set 112. The map correction value set 112 is then used for processing subsequent lots.

[0088] Then, as shown in Figure 14(B), in the exposure process of subsequent lots in the first embodiment, a map correction value MCV corresponding to the wafer magnification correction amount is used. Specifically, the map correction value MCV1 associated with "large Mag correction amount" is applied to the lower wafer LW5, which has a large wafer magnification correction amount. The map correction value MCV2 associated with "small Mag correction amount" is applied to the lower wafer LW6, which has a small wafer magnification correction amount. As a result, the exposure OL measurement result for the lower wafer LW5 may be worse than when map correction value MCV1 is not applied. Similarly, the exposure OL measurement result for the lower wafer LW6 may be worse than when map correction value MCV2 is not applied.

[0089] Then, in the bonding process of subsequent lots, the wafer magnification is corrected for both the case where the lower wafer LW5 is bonded to the upper wafer UW, and the case where the lower wafer LW6 is bonded to the upper wafer UW. The bond OL measurement results for bonded wafer BW5, where the lower wafer LW5 and the upper wafer UW are bonded, can be good because the superposition misalignment of random components is suppressed, as a map correction value MCV1 that matches the Mag correction amount of the exposure process for the lower wafer LW5 is used. Similarly, the bond OL measurement results for bonded wafer BW6, where the lower wafer LW6 and the upper wafer UW are bonded, can be good because the superposition misalignment of random components is suppressed, as a map correction value MCV2 that matches the Mag correction amount of the exposure process for the lower wafer LW6 is used.

[0090] As described above, the exposure apparatus 1 according to the first embodiment can suppress overlap misalignment in the bonding process, although it can increase the overlap misalignment in the exposure process. In terms of the impact on yield, deterioration of bonding OL may be greater than deterioration of exposure OL. In response to this, the exposure apparatus 1 according to the first embodiment suppresses overlap misalignment in processes with a narrow range of acceptable overlap misalignment (e.g., bonding process) by appropriately tolerating overlap misalignment in processes with a wide range of acceptable overlap misalignment (e.g., the exposure process of the preceding process). As a result, the exposure apparatus 1 according to the first embodiment can improve the yield of semiconductor devices.

[0091] [2] Second embodiment The semiconductor manufacturing system PS according to the second embodiment has the same configuration as the first embodiment. In the second embodiment, the correction of the superposition misalignment of random components dependent on the wafer magnification of the lower wafer LW is performed in a different manner than in the first embodiment. Details of the semiconductor manufacturing system PS according to the second embodiment are described below.

[0092] [2-1] Relationship between wafer magnification and polynomial regression coefficient Figure 16 shows an example of the relationship between the wafer magnification ratio and the polynomial regression coefficient in a bonded wafer BW manufactured by the semiconductor manufacturing system PS according to the second embodiment. The superposition misalignment components shown in (D) to (J) of Figure 16 correspond to the superposition misalignment components shown in (D) to (J) of Figure 2, respectively. In the graphs shown in the boxes for each superposition misalignment component, the vertical axis shows the polynomial regression coefficient (K value), and the horizontal axis shows the wafer magnification correction value (W_Mag).

[0093] As shown in Figure 16, in this example, K7-K16, K19, and K20 do not have strong sensitivity to the wafer magnification correction value. On the other hand, K17 and K18 have strong sensitivity to the wafer magnification correction value. That is, in the bonded wafer BW of this example, the amount of overlap misalignment based on K17 and K18 of the bonded OL measurement may change depending on the wafer magnification of the lower wafer LW. Therefore, in the semiconductor manufacturing system PS according to the second embodiment, a relationship equation is created between the polynomial regression coefficients (e.g., K17 and K18) obtained by the bonded OL measurement and the wafer magnification correction value, and this is used for alignment in the exposure process.

[0094] [2-2] Method for manufacturing semiconductor devices Below, we will describe a specific example of a semiconductor device manufacturing method using the semiconductor manufacturing system PS according to the second embodiment. That is, a semiconductor device is manufactured using the exposure method (exposure process) of the second embodiment described below.

[0095] [2-2-1] How to create a correction formula Figure 17 is a flowchart showing an example of a method for creating an OL correction formula used in the exposure apparatus 1 according to the second embodiment. An example of a method for creating an OL correction formula will be explained with reference to Figure 17.

[0096] First, the processes S110 to S113 are executed, similar to the first embodiment. That is, multiple lower wafers LW are prepared by exposing them with different wafer magnifications in a predetermined exposure process (S110). Then, multiple upper wafers UW are prepared by exposing them with a fixed wafer magnification in a predetermined exposure process (S111). After that, the wafer magnifications of the lower wafers LW are corrected to be equivalent to the wafer magnification set in S111, and the bonding process of the lower wafers LW and upper wafers UW is executed (S112). After that, bonding OL measurement is performed (S113).

[0097] Next, the server 3 creates an OL (overlay) correction formula (S200) that associates the wafer magnification correction value with the bonded OL measurement result, based on the bonded OL measurement result in S113. The created OL correction formula is then stored, for example, in the storage device 11 of the exposure apparatus 1. The OL correction formula is a relationship formula between the wafer magnification correction value and a predetermined K value. In other words, by substituting the wafer magnification correction value into the OL correction formula, the exposure apparatus 1 can calculate a K value that can be used for alignment correction. The predetermined K value is a parameter that depends on the wafer magnification in the bonding process, for example, K17 and K18. The K value used in the OL correction formula is not limited to K17 and K18, and other K values ​​may be used. In the second embodiment, at least a K value that is sensitive to the wafer magnification correction value in the bonded OL should be used in the OL correction formula.

[0098] [2-2-2] Flow from exposure treatment to bonding treatment Figure 18 is a flowchart showing an example of a process related to the alignment correction of random components in the semiconductor manufacturing system PS according to the second embodiment. Below, with reference to Figure 18, the differences between the flow from exposure processing to bonding processing in the second embodiment and the first embodiment will be explained.

[0099] In the second embodiment, the exposure process in the pre-processing of the lower wafer LW differs from that of the first embodiment. Specifically, the flowchart shown in Figure 18 has a configuration in which S130 and S131 are replaced with S210 and S211, respectively, compared to the flowchart shown in Figure 13. That is, in the pre-processing of the lower wafer LW, the processes of S210 and S211 are executed in order.

[0100] In the S210 process, the exposure process of the lower wafer LW is performed using alignment based on the OL correction formula created in S200 and the wafer magnification correction value. Specifically, in the alignment correction process (S103 in Figure 9), the exposure apparatus 1 according to the second embodiment calculates the wafer magnification correction value (e.g., K3 and K4) by polynomial regression using the measurement results of at least three alignment marks AM. K17 and K18 can also be calculated in this polynomial regression. The exposure apparatus 1 then corrects the K values ​​(e.g., K17 and K18) used for alignment correction within the wafer surface based on the magnitude of the calculated wafer magnification correction value. The K values ​​used for correcting the K values ​​are those calculated by substituting the wafer magnification correction value into the OL correction formula. For example, K17 and K18 calculated based on the OL correction value are used as offsets for the alignment correction value within the wafer surface. In this example, it is sufficient that the K-value parameter used for alignment is changed based on the wafer magnification correction value obtained from the measurement results of the alignment mark AM.

[0101] Then, in the S211 process, correction value information 111b, including the wafer magnification correction value used in S210, is stored in the server 3. Once the processing of the preceding processes for the upper wafer UW and the lower wafer LW is completed (S140), the processes S141 and S142 are executed, as in the first embodiment. Other processes in the exposure apparatus 1 according to the second embodiment are the same as in the first embodiment.

[0102] [2-3] Effects of the second embodiment According to the exposure apparatus 1 of the second embodiment described above, the lower wafer is exposed in the same manner as in the first embodiment. L Although the overlap misalignment due to the exposure process in the pre-processing of W becomes large, the overlap misalignment between the upper wafer UW and the lower wafer LW in the bonding process can be suppressed. As a result, the exposure apparatus 1 according to the second embodiment can improve the yield of semiconductor devices, similar to the first embodiment.

[0103] [2-4] Modified form of the second embodiment In the second embodiment, an example was given of performing alignment correction processing using polynomial regression coefficients based on wafer magnification, but the invention is not limited thereto. Zernike polynomials may be used to create the OL correction formula. Zernike polynomials are functions (orthogonal polynomials) defined inside a unit circle with radius "1". Specifically, Zernike polynomials are expressed, for example, by equation (1) below.

[0104]

number

[0105] In equation (1), “W(x,y)” represents the wavefront at coordinate (x,y). j (x,y)” represents the j-th Zernike polynomial. j " indicates the Zernike coefficient (i.e., the coefficient of the Zernike polynomial) corresponding to the j-th Zernike polynomial. "J" indicates the number of Zernike polynomials used in the expansion. The sum of Zernike polynomials can (approximately) represent all surface shapes. Figure 19 is a schematic diagram illustrating the Zernike polynomials, showing images of the 2nd to 16th Zernike polynomials. "Z2" is, for example, called tilt in the X direction. "Z3" is, for example, called tilt in the Y direction. "Z4" is, for example, called defocus. "Z5" is, for example, called astigmatism. "Z6" is, for example For example, "Z7" is called coma aberration in the X direction. "Z8" is called coma aberration in the Y direction. "Z9" is called spherical aberration. "Z10" is called Trefoil aberration in the X direction. "Z11" is called Trefoil aberration in the Y direction. "Z12" is called second-order astigmatism. "Z13" is called second-order slanted astigmatism. "Z14" is called second-order coma aberration in the X direction. "Z15" is called second-order coma aberration in the Y direction. "Z16" is called second-order spherical aberration.

[0106] In the exposure apparatus 1 according to the second embodiment, during the exposure process, information on the wavefront corresponding to the wafer surface can be acquired and wafer focusing can be performed. When using Zernike polynomials in the second embodiment, Zernike polynomials and coefficients that have a large correlation with the wafer magnification correction value in the bonding process are used to create the OL correction formula. In this case, during the exposure process, the exposure apparatus 1 calculates Zernike coefficients corresponding to the surface shape of the lower wafer LW based on measurement results such as wavefront aberration and focus. The exposure apparatus 1 may then change the offset value in the alignment correction process based on the numerical value obtained by substituting predetermined Zernike coefficients into the OL correction formula. The exposure apparatus 1 only needs to calculate the offset value using an OL correction formula based on the surface shape and alignment results of the lower wafer LW and use it in the alignment correction process.

[0107] [3] Third embodiment The third embodiment relates to a specific example of a semiconductor device to which the semiconductor device manufacturing method described in the first and second embodiments can be applied. Below, a memory device 4, which is a NAND flash memory, is described as a specific example of a semiconductor device.

[0108] [3-1] Composition [3-1-1] Configuration of memory device 4 Figure 20 is a block diagram showing an example of the configuration of a memory device 4 according to the third embodiment. As shown in Figure 20, the memory device 4 includes, for example, a memory interface (memory I / F) 40, a sequencer 41, a memory cell array 42, a driver module 43, a raw decoder module 44, and a sense amplifier module 45.

[0109] The memory interface 40 is a hardware interface that connects to an external memory controller. The memory interface 40 communicates with the memory device 4 and the memory controller according to the interface standard. The memory interface 40 supports, for example, the NAND interface standard.

[0110] The sequencer 41 is a control circuit that controls the overall operation of the memory device 4. Based on commands received via the memory interface 40, the sequencer 41 controls the driver module 43, the row decoder module 44, the sense amplifier module 45, etc., to perform read operations, write operations, erase operations, etc.

[0111] The memory cell array 42 is a memory circuit that includes a collection of multiple memory cells. The memory cell array 42 includes multiple blocks BLK0 to BLKn (where n is an integer greater than or equal to 1). Block BLK is used, for example, as a data erasure unit. The memory cell array 42 is also provided with multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line and one word line. Each memory cell is identified based on an address that identifies the word line WL and an address that identifies the bit line BL.

[0112] The driver module 43 is a driver circuit that generates voltages used in read, write, and erase operations. The driver module 43 is connected to the row decoder module 44 via multiple signal lines. The driver module 43 can change the voltage applied to each of the multiple signal lines based on the page address received via the memory interface 40.

[0113] The row decoder module 44 is a decoder that decodes the row address received via the memory I / F 40. Based on the decoding result, the row decoder module 44 selects one block BLK. The row decoder module 44 then transfers the voltages applied to multiple signal lines to multiple wirings (such as word lines WL) provided in the selected block BLK.

[0114] The sense amplifier module 45 is a sense circuit that senses data read from a selected block BLK based on the voltage of the bit line BL during read operations. The sense amplifier module 45 transmits the read data to the memory controller via the memory I / F 40. In addition, during write operations, the sense amplifier module 45 can apply a voltage to each bit line BL corresponding to the data to be written to the memory cell.

[0115] [3-1-2] Circuit configuration of memory cell array 42 Figure 21 is a circuit diagram showing an example of the circuit configuration of a memory cell array 42 provided in the memory device 4 according to the third embodiment. Figure 21 shows one of several block BLKs included in the memory cell array 42. As shown in Figure 21, the block BLK includes, for example, string units SU0 to SU3.

[0116] Each string unit SU contains multiple NAND strings NS. Each NAND string NS is associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). Each bit line BL0 to BLm is assigned a different column address. Each bit line BL is shared among multiple blocks BLK by NAND strings NS that are assigned the same column address. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, as well as selection transistors STD and STS.

[0117] Each memory cell transistor MT includes a control gate and a charge storage layer, and stores data nonvolatilically. The memory cell transistors MT0 to MT7 of each NAND string NS are connected in series. The control gates of the memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. Each of the word lines WL0 to WL7 is provided for each block BLK. A collection of multiple memory cell transistors MT connected to a common word line WL in the same string unit SU is called, for example, a "cell unit CU". When each memory cell transistor MT stores 1 bit of data, the cell unit CU stores "1 page of data". Depending on the number of bits of data stored by the memory cell transistors MT, the cell unit CU may have a storage capacity of 2 pages or more.

[0118] The selection transistors STD and STS are used for selecting string unit SU, respectively. The drain of selection transistor STD is connected to the associated bit line BL. The source of selection transistor STD is connected to one end of the series-connected memory cell transistors MT0 to MT7. The gates of the selection transistor STDs included in string units SU0 to SU3 are connected to the selection gate lines SGD0 to SGD3, respectively. The drain of selection transistor STS is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of selection transistor STS is connected to the source line SL. The gate of selection transistor STS is connected to the selection gate line SGS. The source line SL is shared, for example, by multiple blocks BLK.

[0119] [3-1-3] Structure of memory device 4 An example of the structure of the memory device 4 according to the third embodiment is described below. In the third embodiment, the X direction corresponds to the extension direction of the word line WL, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to the perpendicular direction to the surface of the semiconductor substrate used to form the memory device 4.

[0120] Figure 22 is a perspective view showing an example of the structure of a memory device 4 according to the third embodiment. As shown in Figure 22, the memory device 4 includes a memory chip MC and a CMOS chip CC. The lower surface of the memory chip MC corresponds to the surface of the lower wafer LW. The upper surface of the CMOS chip CC corresponds to the surface of the upper wafer UW. The memory chip MC includes, for example, a memory area MR, extraction areas HR1 and HR2, and a pad area PR1. The CMOS chip CC includes, for example, a sense amplifier area SR, a peripheral circuit area PERI, transfer areas XR1 and XR2, and a pad area PR2.

[0121] The memory area MR includes the memory cell array 42. The lead-out areas HR1 and HR2 include wiring used for connecting the stacked wiring provided on the memory chip MC and the low decoder module 44 provided on the CMOS chip CC. The pad area PR1 includes pads used for connecting the memory device 4 and the memory controller. The lead-out areas HR1 and HR2 sandwich the memory area MR in the X direction. The pad area PR1 is adjacent to the memory area MR and the lead-out areas HR1 and HR2 in the Y direction.

[0122] The sense amplifier area SR includes the sense amplifier module 45. The peripheral circuit area PERI includes the sequencer 41 and the driver module 43, etc. The transfer areas XR1 and XR2 include the row decoder module 44. The pad area PR2 includes the memory I / F 40. The sense amplifier area SR and the peripheral circuit area PERI are located adjacent to each other in the Y direction and overlap with the memory area MR. The transfer areas XR1 and XR2 sandwich the sense amplifier area SR and peripheral circuit area PERI pair in the X direction and overlap with the lead areas HR1 and HR2, respectively. The pad area PR2 overlaps with the pad area PR1 of the memory chip MC.

[0123] The memory chip MC has multiple adhesive pads BP at the bottom of each of the following areas: the memory area MR, the lead areas HR1 and HR2, and the pad area PR1. The adhesive pads BP in the memory area MR are connected to the associated bit lines BL. The adhesive pads BP in the lead area HR are connected to the associated wiring (e.g., word lines WL) among the stacked wiring provided in the memory area MR. The adhesive pads BP in the pad area PR1 are connected to pads (not shown) provided on the top surface of the memory chip MC. The pads provided on the top surface of the memory chip MC are used, for example, for connections between the memory device 4 and the memory controller.

[0124] The CMOS chip CC has multiple adhesive pads BP on top of each of the sense amplifier area SR, peripheral circuit area PERI, transfer areas XR1 and XR2, and pad area PR2. The adhesive pad BP of the sense amplifier area SR overlaps with the adhesive pad BP of the memory area MR. The adhesive pads BP of the transfer areas XR1 and XR2 overlap with the adhesive pads BP of the lead-out areas HR1 and HR2, respectively. The adhesive pad BP of pad area PR1 overlaps with the adhesive pad BP of pad area PR2.

[0125] The memory device 4 has a structure in which the lower surface of the memory chip MC and the upper surface of the CMOS chip CC are joined together. Of the multiple bonding pads BP provided on the memory device 4, two bonding pads BP facing each other between the memory chip MC and the CMOS chip CC are electrically connected by bonding. As a result, the circuits within the memory chip MC and the circuits within the CMOS chip CC are electrically connected via the bonding pads BP. The pair of bonding pads BP facing each other between the memory chip MC and the CMOS chip CC may have a boundary or may be integrated.

[0126] (Planar layout of memory cell array 42) Figure 23 is a plan view showing an example of the planar layout of a memory cell array 42 provided in a memory device 4 according to the third embodiment. Figure 23 shows a region containing one block BLK of the memory region MR. As shown in Figure 23, the memory device 4 includes, for example, a plurality of slits SLT, a plurality of slits SHE, a plurality of memory pillars MP, a plurality of bit lines BL, and a plurality of contacts CV. In the memory region MR, the planar layout described below is repeatedly arranged in the Y direction.

[0127] Each slit SLT has a structure in which, for example, an insulating material is embedded. Each slit SLT insulates adjacent wiring (e.g., word lines WL0 to WL7, and selection gate lines SGD and SGS) through it. Each slit SLT has a portion that extends along the X direction and crosses the memory area MR and the lead areas HR1 and HR2 along the X direction. Multiple slit SLTs are arranged in the Y direction. The areas separated by the slit SLTs correspond to blocks BLK.

[0128] Each slit SHE has a structure in which, for example, an insulating material is embedded. Each slit SHE insulates adjacent wiring (at least the selected gate line SGD) through the slit SLT. Each slit SHE has a portion that extends along the X direction and crosses the memory area MR. Multiple slit SHEs are aligned in the Y direction. In this example, three slit SHEs are positioned between adjacent slit SLTs. Multiple regions separated by slit SLTs and SHEs correspond to string units SU0 to SU3, respectively.

[0129] Each memory pillar MP functions, for example, as a single NAND string NS. Multiple memory pillar MPs are arranged in a staggered pattern, for example, 19 rows, in the region between two adjacent slits SLT. Then, counting from the top of the paper, one slit SHE overlaps each of the 5th, 10th, and 15th memory pillar MPs.

[0130] Each bit line BL has a portion that extends along the Y direction and traverses the region where multiple block BLKs are provided along the Y direction. Multiple bit lines BLs are aligned in the X direction. Each bit line BL is positioned to overlap with at least one memory pillar MP for each string unit SU. In this example, two bit lines BL overlap with each memory pillar MP.

[0131] Each contact CV is placed between one of the multiple bit lines BL that overlap the memory pillar MP and the memory pillar MP in question. The contact CV electrically connects the memory pillar MP and the bit line BL. Note that the contact CV between the memory pillar MP that overlaps with the slit SHE and the bit line BL is omitted.

[0132] (Cross-sectional structure of memory cell array 42) Figure 24 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array 42 provided in a memory device 4 according to the third embodiment. Figure 24 shows a cross-section along the Y direction, including the memory pillar MP and the slit SLT within the memory region MR. In Figure 24, the Z direction refers to the bottom of the paper, but in the explanation of Figure 24, the top of the paper is referred to as "upper" and the bottom of the paper as "lower". As shown in Figure 24, the memory device 4 includes, for example, insulating layers 50-57, conductive layers 60-66, and contacts V1 and V2.

[0133] The insulating layer 50 is provided, for example, at the bottom layer of the memory chip MC. A conductive layer 60 is provided on top of the insulating layer 50. An insulating layer 51 is provided on top of the conductive layer 60. Conductive layers 61 and insulating layers 52 are provided alternately on top of the insulating layer 51. An insulating layer 53 is provided on top of the uppermost conductive layer 61. Conductive layers 62 and insulating layers 54 are provided alternately on top of the insulating layer 53. An insulating layer 55 is provided on top of the uppermost conductive layer 62. Conductive layers 63 and insulating layers 56 are provided alternately on top of the insulating layer 55. An insulating layer 57 is provided on top of the uppermost conductive layer 63. A conductive layer 64 is provided on top of the insulating layer 57. A contact V1 is provided on top of the conductive layer 64. A conductive layer 65 is provided on top of the contact V1. A contact V2 is provided on the conductive layer 65. A conductive layer 66 is provided on the contact V2. Hereinafter, the wiring layers on which conductive layers 64, 65, and 66 are provided will be referred to as "M0", "M1", and "M2", respectively.

[0134] Each of the conductive layers 60, 61, 62, and 63 is formed, for example, as a plate extending along the XY plane. Conductive layer 64 is formed, for example, as a line extending in the Y direction. Conductive layers 60, 61, and 63 are used as source line SL, selection gate line SGS, and selection gate line SGD, respectively. Multiple conductive layers 62 are used, in order from the conductive layer 60 side, as word lines WL0 to WL7, respectively. Conductive layer 64 is used as bit line BL. Contacts V1 and V2 are provided in a columnar shape. Conductive layers 64 and 65 are connected via contact V1. Conductive layer 65 and conductive layer 66 are connected via contact V2. Conductive layer 65 is, for example, a wiring formed as a line extending in the X direction. Conductive layer 66 is in contact with the interface of the memory chip MC and is used as a bonding pad BP. Conductive layer 66 contains, for example, copper.

[0135] The slit SLT has a plate-shaped portion that extends along the XZ plane, dividing the insulating layers 51-56 and the conductive layers 61-63. Each memory pillar MP is provided extending along the Z direction and penetrates the insulating layers 51-56 and the conductive layers 61-63. Each memory pillar MP includes, for example, a core member 70, a semiconductor layer 71, and a laminated film 72. The core member 70 is an insulator provided extending along the Z direction. The semiconductor layer 71 covers the core member 70. The lower part of the semiconductor layer 71 is in contact with the conductive layer 60. The laminated film 72 covers the side surface of the semiconductor layer 71. A contact CV is provided on the semiconductor layer 71. The conductive layer 64 is in contact with the contact CV.

[0136] The illustrated region shows the contact CV corresponding to one of the two memory pillar MPs. For memory pillar MPs that do not have a contact CV connected in this region, a contact CV is connected in a region not shown. The portion where the memory pillar MP intersects with multiple conductive layers 61 functions as a selection transistor STS. The portion where the memory pillar MP intersects with conductive layer 62 functions as a memory cell transistor MT. The portion where the memory pillar MP intersects with multiple conductive layers 63 functions as a selection transistor STD.

[0137] (Cross-sectional structure of memory pillar MP) Figure 25 is a cross-sectional view along the line XXV-XXV in Figure 24, showing an example of the cross-sectional structure of a memory pillar MP in the memory device 4 according to the third embodiment. Figure 25 shows a cross-section including the memory pillar MP and the conductive layer 62, and parallel to the conductive layer 60. As shown in Figure 25, the laminated film 72 includes, for example, a tunnel insulating film 73, an insulating film 74, and a block insulating film 75.

[0138] The core member 70 is provided, for example, in the center of the memory pillar MP. The semiconductor layer 71 surrounds the sides of the core member 70. The tunnel insulating film 73 surrounds the sides of the semiconductor layer 71. The insulating film 74 surrounds the sides of the tunnel insulating film 73. The block insulating film 75 surrounds the sides of the insulating film 74. The conductive layer 62 surrounds the sides of the block insulating film 75. The semiconductor layer 71 is used as the channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors STD and STS. The tunnel insulating film 73 and the block insulating film 75 each contain, for example, silicon oxide. The insulating film 74 is used as the charge storage layer for the memory cell transistor MT and contains, for example, silicon nitride. Thus, each of the memory pillar MP functions as one NAND string NS.

[0139] (Cross-sectional structure of memory device 4) Figure 26 is a cross-sectional view showing an example of the cross-sectional structure of a memory device 4 according to the third embodiment. Figure 26 shows a cross-section including the memory region MR and the sense amplifier region SR, that is, a cross-section including the memory chip MC and the CMOS chip CC. As shown in Figure 26, the memory device 4 includes a semiconductor substrate 80, conductive layers GC and 81-84, and contacts CS and C0-C3 in the sense amplifier region SR.

[0140] The semiconductor substrate 80 is a substrate used for forming a CMOS chip CC. The semiconductor substrate 80 includes a plurality of well regions (not shown). A transistor TR is formed in each of the plurality of well regions. The plurality of well regions are separated by, for example, STI (Shallow Trench Isolation). A conductive layer GC is provided on the semiconductor substrate 80 via a gate insulating film. The conductive layer GC in the sense amplifier region SR is used as the gate electrode of the transistor TR included in the sense amplifier module 45. A contact C0 is provided on the conductive layer GC. Two contacts CS are provided on the semiconductor substrate 80 corresponding to the source and drain of the transistor TR.

[0141] A conductive layer 81 is provided above contact CS and above contact C0. A contact C1 is provided above conductive layer 81. A conductive layer 82 is provided above contact C1. Conductive layers 81 and 82 are electrically connected via contact C1. A contact C2 is provided above conductive layer 82. A conductive layer 83 is provided above contact C2. Conductive layers 82 and 83 are electrically connected via contact C2. A contact C3 is provided above conductive layer 83. A conductive layer 84 is provided above contact C3. Conductive layers 83 and 84 are electrically connected via contact C3. Hereinafter, the wiring layers on which conductive layers 81 to 84 are provided will be referred to as "D0", "D1", "D2", and "D3", respectively.

[0142] The conductive layer 84 is in contact with the interface of the CMOS chip CC and is used as a bonding pad BP. The conductive layer 84 in the sense amplifier region SR is bonded to the conductive layer 66 in the memory region MR (i.e., the bonding pad BP of the memory chip MC) which is located opposite it. Each conductive layer 84 in the sense amplifier region SR is electrically connected to a single bit line BL. The conductive layer 84 contains, for example, copper.

[0143] In memory device 4, the wiring layer D3 of the CMOS chip CC and the wiring layer M2 of the memory chip MC are adjacent to each other due to the bonding of the memory chip MC and the CMOS chip CC. The semiconductor substrate 80 corresponds to the back side of the upper wafer UW, and the wiring layer D3 corresponds to the front side of the upper wafer UW. The insulating layer 50 corresponds to the back side of the lower wafer LW, and the wiring layer M2 corresponds to the front side of the lower wafer LW. The semiconductor substrate used to form the memory chip MC is removed during processes such as the formation of pads after the bonding process.

[0144] [3-2] Effects of the third embodiment As described above, the memory device 4 includes, for example, a memory chip MC, which has a structure in which memory cells are stacked in three dimensions, and a CMOS chip CC, which includes other control circuits. Between the memory chip MC and the CMOS chip CC, the memory chip MC tends to have greater variation in wafer magnification between wafers. Specifically, because the memory chip MC has a high-layered memory cell array 42, the variation in wafer warp is larger, and the variation in wafer magnification can be larger. On the other hand, the arrangement of shots in the CMOS chip CC is closer to an ideal grid with respect to the exposure apparatus. For this reason, when bonding is performed, it is preferable that the wafer on which the memory chip MC is formed is assigned to the lower wafer LW, which can correct the wafer magnification, and the wafer on which the CMOS chip CC is formed is assigned to the upper wafer UW. As a result, the yield of the memory device 4 can be improved in each of the first and second embodiments.

[0145] [4] Fourth Embodiment The semiconductor manufacturing system PS according to the fourth embodiment has the same configuration as the first embodiment. The fourth embodiment corrects the overlap misalignment of random components that depend on the amount of warpage of the upper wafer UW using a method similar to that of the first embodiment. Details of the semiconductor manufacturing system PS according to the fourth embodiment are described below.

[0146] [4-1] Method for manufacturing semiconductor devices Below, we will describe a specific example of a semiconductor device manufacturing method according to the fourth embodiment, using the exposure apparatus 1. That is, the semiconductor device is manufactured using the exposure method (exposure process) of the first embodiment described below.

[0147] [4-1-1] How to create map correction values Figure 27 is a flowchart showing an example of a method for creating map correction values ​​used in the exposure apparatus 1 according to the first embodiment. An example of a method for creating map correction values ​​will be described below with reference to Figure 27.

[0148] First, multiple upper wafers UW with different amounts of warping are prepared, and exposure processing is performed on each of them (S300). In other words, in the S300 process, two or more upper wafers UW with different amounts of warping are prepared. The exposure processing in the S300 process corresponds to the exposure processing of the bonding surface of the upper wafer UW.

[0149] Next, multiple lower wafers LW with approximately equal amounts of warpage are prepared, and exposure processing is performed on each of them (S301). That is, in the process of S301, amount of curvature Two or more lower wafers LW with approximately equal values ​​are prepared. The exposure process in S301 corresponds to the exposure process of the bonding surface of the lower wafer LW.

[0150] Next, the bonding process between the lower wafer LW and the upper wafer UW is performed (S302). This forms multiple bonded wafers BW using upper wafers UW with different amounts of warping.

[0151] Next, bonding OL measurement is performed (S303). This bonding OL measurement provides bonding OL measurement results for each amount of warpage of the upper wafer UW set in the S300 process. The bonding OL measurement results are stored, for example, in server 3.

[0152] Next, Server 3 creates a map correction value (S304) that associates the wafer warpage with the bonded OL measurement result, based on the bonded OL measurement result in the S303 process. The created map correction values ​​are then stored as a map correction value set 112 in the storage device 11 of the exposure apparatus 1. Each map correction value is associated, for example, with a predetermined range of wafer warpage that is different from each other. This predetermined range is set, for example, as a reference for the wafer warpage set in the S300 process.

[0153] Furthermore, even if the amount of warping of the lower wafer LW differs, the impact on the multiple map correction values ​​created in the S304 process is small. For this reason, the amount of warping of the lower wafer LW prepared in the S301 process may differ.

[0154] [4-1-2] Flow from exposure treatment to bonding treatment Figure 28 is a flowchart showing an example of a process related to the alignment correction of random components in the semiconductor manufacturing system PS according to the fourth embodiment. The flow from exposure processing to bonding processing in the first embodiment will be described below with reference to Figure 28.

[0155] First, the amount of warpage of the upper wafer UW, which is the target of exposure at the bonding surface, is measured (S310). The data on the amount of warpage of the upper wafer UW is transferred to the exposure apparatus 1 via, for example, the server 3 and stored in the storage device 11 of the exposure apparatus 1.

[0156] Next, exposure processing of the bonding surface of the upper wafer UW is performed using a map correction value corresponding to the measured amount of warpage (S311). For example, exposure apparatus 1 selects a map correction value created based on the bonding OL measurement results of a bonding wafer BW using an upper wafer UW with a large amount of warpage as the map correction value to be applied to a wafer with a large amount of warpage. Also, exposure apparatus 1 selects a map correction value created based on the bonding OL measurement results of a bonding wafer BW using an upper wafer UW with a small amount of warpage as the map correction value to be applied to a wafer with a small amount of warpage.

[0157] In addition, the pre-processing of the lower wafer LW is performed in parallel with the processing in S310 and S311 (S320). This forms the lower wafer LW.

[0158] Once the preceding processes for the associated upper wafer UW and lower wafer LW are completed (S330), the bonding process is performed (S331). This forms a bonded wafer BW in which the associated upper wafer UW and lower wafer LW are bonded together.

[0159] Furthermore, if there is no map correction value associated with the wafer magnification correction value, the exposure apparatus 1 may use a map correction value associated with a warp amount close to the warp amount of the wafer, or it may use a map correction value calculated based on a combination of multiple map correction values. Alternatively, the exposure apparatus 1 or server 3 may create a relationship formula between the wafer warp amount and the overlay correction value for each shot based on multiple combinations of wafer warp amount and map correction value, and a map correction value based on this relationship formula may be used in the exposure process.

[0160] [4-2] Effects of the fourth embodiment In semiconductor devices formed by bonding two wafers, misalignment of random components in the bonding overlay (OL) may occur depending on the amount of warping of the upper wafer UW. One possible cause is that the stress applied to the upper wafer UW during the bonding process changes according to the amount of warping of the upper wafer UW. When the stress applied to the upper wafer UW changes, the stress on the upper wafer UW when it peels off from the upper stage 233 and falls onto the lower wafer LW during the bonding process changes, which can cause misalignment of the overlap. As a method to suppress such misalignment of random components in the bonding wafer BW, it is conceivable to use exposure map correction in a predetermined exposure process in the preceding process that improves the bonding OL.

[0161] Here, using the second comparative example, an example of a method for improving the bonding overlay in the fourth embodiment will be described. In this example, it is assumed that the variation in wafer warpage in the pre-processing of the lower wafer LW is small, and the variation in wafer warpage in the pre-processing of the upper wafer UW is large.

[0162] Figure 29 is a schematic diagram showing an example of a method for improving the bonding overlay in the second comparative example. Figures 29(A) and (B) correspond to before and after applying exposure map correction, respectively, and show the results of exposure OL measurement and bonding OL measurement at the bonding surface of the lot. It is assumed that the overlay in the exposure OL of the lower wafer LW is good both before and after applying exposure map correction.

[0163] As shown in Figure 29(A), in the exposure process of the preceding step, the upper wafer UW1 has a large amount of warp, while the upper wafer UW2 has a small amount of warp. The exposure OL measurements of upper wafers UW1 and UW2 show good overlap. Then, through the bonding process, bonded wafers BW1 and BW2 are formed using upper wafers UW1 and UW2, respectively. In this example, in both bonded wafer BW1, which is formed by bonding upper wafer UW1 and lower wafer LW, and bonded wafer BW2, which is formed by bonding upper wafer UW2 and lower wafer LW, there remains an overlap misalignment of the random component due to the wafer magnification correction in the bonding process. Therefore, the bonded OL measurements of bonded wafers BW1 and BW2 show poor overlap.

[0164] In the second comparative example, a map correction value MCV3 is created based on the bonding OL measurement results of the bonded wafer BW1, and the map correction value MCV3 is used for processing subsequent lots. As a result, as shown in Figure 29(B), in the exposure OL measurement of subsequent lots, the exposure OL of the upper wafer UW3, which has a large amount of wafer warp, and the upper wafer UW4, which has a small amount of wafer warp, may worsen due to the application of the map correction value MCV3. This is because the use of a map correction value that can improve the overlap of the bonding process may cause an overlap misalignment between the pattern formed by the exposure process and the underlying pattern. In the bonding OL measurement results of bonded wafer BW3, in which the upper wafer UW3 and the lower wafer LW are bonded, the overlap misalignment of random components is suppressed and the results may be better because the map correction value MCV3 is used in the exposure process of the upper wafer UW3.

[0165] However, the tendency of the overlap misalignment of random components can change depending on the amount of warping of the upper wafer UW. For this reason, in the bonded wafer BW4, where the upper wafer UW4 and the lower wafer LW are joined, the amount of improvement in the overlap misalignment of random components may be worse than in the bonded wafer BW3, because the amount of wafer warping during the exposure process is small, while the map correction value MCV3 corresponding to "large wafer warping" is used. Thus, the amount of improvement in the overlap misalignment of random components may differ depending on the amount of warping of the upper wafer UW. For this reason, in the second comparative example, the amount of improvement in the overlay may decrease depending on the amount of warping of the upper wafer UW.

[0166] Therefore, the exposure apparatus 1 according to the fourth embodiment has a function to select a map correction value MCV to be used in the exposure process of the bonding surface of the upper wafer UW according to the amount of warping of the upper wafer UW during the exposure process.

[0167] Figure 30 is a schematic diagram showing an example of a method for improving bonding overlay in the fourth embodiment. Figures 30(A) and (B) correspond to before and after applying exposure map correction in the fourth embodiment, respectively, and show the results of exposure OL measurement and bonding OL measurement at the bonding surface of the lot. It is assumed that the overlay in the exposure OL of the upper wafer UW is good both before and after applying exposure map correction. As shown in Figure 30(A), the example before applying exposure map correction in the fourth embodiment is the same as the example before applying exposure map correction in the second comparative example.

[0168] In the fourth embodiment, a map correction value MCV3 is created based on the amount of warpage of the upper wafer UW1 measured before exposure processing of the bonding surface of the upper wafer UW1 and the result of bonding OL measurement of the bonding wafer BW1. Similarly, a map correction value MCV4 is created based on the amount of warpage of the upper wafer UW2 measured before exposure processing of the bonding surface of the upper wafer UW2 and the result of bonding OL measurement of the bonding wafer BW2. Then, map correction values ​​MCV3 and MCV4 are stored in the storage device 11 of the exposure apparatus 1 as a map correction value set 112. Subsequently, the map correction value set 112 is used for processing subsequent lots.

[0169] Then, as shown in Figure 30(B), in the exposure process of subsequent lots in the fourth embodiment, a map correction value MCV corresponding to the amount of warpage of the upper wafer UW is used. Specifically, the map correction value MCV3 associated with "large wafer warpage" is applied to the upper wafer UW5, which has a large amount of wafer warpage. The map correction value MCV4 associated with "small wafer warpage" is applied to the upper wafer UW6, which has a small amount of wafer warpage. As a result, the exposure OL measurement result for the upper wafer UW5 may be worse than when the map correction value MCV3 is not applied. Similarly, the exposure OL measurement result for the upper wafer UW6 may be worse than when the map correction value MCV4 is not applied.

[0170] Then, through the bonding process, a bonded wafer BW5 is formed using the upper wafer UW5 and the associated lower wafer LW, and a bonded wafer BW6 is formed using the upper wafer UW6 and the associated lower wafer LW. In the bonding OL measurement results for bonded wafer BW5, a map correction value MCV3 that matches the amount of warpage of the upper wafer UW5 is used in the exposure process of the bonding surface of the upper wafer UW5, which suppresses the overlapping misalignment of random components and can result in good performance. Similarly, in the bonding OL measurement results for bonded wafer BW6, a map correction value MCV4 that matches the amount of warpage of the upper wafer UW6 is used in the exposure process of the bonding surface of the upper wafer UW6, which suppresses the overlapping misalignment of random components and can result in good performance.

[0171] As described above, the exposure apparatus 1 according to the fourth embodiment can suppress overlap misalignment in the bonding process, although it can suppress overlap misalignment in the bonding process, while the overlap misalignment in the bonding process is large during the exposure process of the bonding surface of the upper wafer UW. In terms of the impact on yield, the deterioration of bonding OL may be greater than the deterioration of exposure OL on the bonding surface of the upper wafer UW. In response to this, the exposure apparatus 1 according to the fourth embodiment appropriately tolerates overlap misalignment in processes where the range of acceptable overlap misalignment is wide (for example, the exposure process of the preceding process). As a result, the exposure apparatus 1 according to the fourth embodiment can suppress overlap misalignment in processes where the range of acceptable overlap misalignment is narrow (for example, the bonding process). Consequently, the exposure apparatus 1 according to the fourth embodiment can improve the yield of semiconductor devices, similar to the first embodiment.

[0172] [5] Fifth embodiment The semiconductor manufacturing system PS according to the fifth embodiment has the same configuration as the first embodiment. The fifth embodiment corrects the superposition misalignment of random components that depend on the amount of warpage of the upper wafer UW using a method similar to that of the second embodiment. Details of the semiconductor manufacturing system PS according to the fifth embodiment are described below.

[0173] [5-1] Relationship between the amount of warpage of the upper wafer (UW) and the polynomial regression coefficient Figure 31 shows an example of the relationship between the amount of warpage of the upper wafer UW and the polynomial regression coefficient in a bonded wafer BW manufactured by the semiconductor manufacturing system PS according to the fifth embodiment. The superposition misalignment components shown in (D) to (J) of Figure 31 correspond to the superposition misalignment components shown in (D) to (J) of Figure 2, respectively. In the graphs shown in the boxes for each superposition misalignment component, the vertical axis shows the polynomial regression coefficient (K value), and the horizontal axis shows the amount of warpage of the upper wafer UW (UW warpage).

[0174] As shown in Figure 31, in this example, K7-K16, K19, and K20 do not have strong sensitivity to the amount of warpage of the upper wafer UW. On the other hand, K17 and K18 have strong sensitivity to the amount of warpage of the upper wafer UW. That is, in the bonded wafer BW of this example, the amount of overlap misalignment based on K17 and K18 of the bonded OL measurement may change depending on the magnitude of the warpage of the upper wafer UW. Therefore, in the semiconductor manufacturing system PS according to the fifth embodiment, a relationship equation is created between the polynomial regression coefficients (e.g., K17 and K18) obtained by bonded OL measurement and the amount of warpage of the upper wafer UW, and this is used for alignment in the exposure process.

[0175] [5-2] Method for manufacturing semiconductor devices Below, we will describe a specific example of a semiconductor device manufacturing method using the semiconductor manufacturing system PS according to the fifth embodiment. That is, a semiconductor device is manufactured using the exposure method (exposure process) of the fifth embodiment described below.

[0176] [5-2-1] How to create a correction formula Figure 32 is a flowchart showing an example of a method for creating an OL correction formula used in the exposure apparatus 1 according to the fifth embodiment. An example of a method for creating an OL correction formula will be explained with reference to Figure 32.

[0177] First, as in the fourth embodiment, the processes S300 to S303 are executed. That is, multiple upper wafers UW with different amounts of warping are prepared, and exposure processing is performed on the bonding surface of the upper wafers UW (S300). Multiple lower wafers LW with approximately equal amounts of warping are prepared, and exposure processing is performed on the bonding surface of the lower wafers LW (S301). Then, bonding processing of the lower wafers LW and upper wafers UW is performed (S302). After that, bonding OL measurement is performed on each of the multiple bonded wafers BW formed in the process of S302 (S303).

[0178] Next, the server 3 creates an OL (overlay) correction formula (S400) that associates the amount of warpage of the upper wafer UW with the measurement results of the bonded OL in the processing of S303. The created OL correction formula is then stored, for example, in the storage device 11 of the exposure apparatus 1. The OL correction formula is a relationship formula between the amount of warpage of the upper wafer UW and a predetermined K value. In other words, by substituting the measured value of the amount of warpage of the upper wafer UW into the OL correction formula, the exposure apparatus 1 can calculate a K value correction value that can be used to correct the alignment. This K value is a parameter that depends on the amount of warpage of the upper wafer UW, and is, for example, K17 and K18. The K value used in the OL correction formula is not limited to K17 and K18, and other K values ​​may be used. In the fifth embodiment, it is sufficient that at least a K value that is sensitive to the amount of warpage of the upper wafer UW in the bonded OL is used in the OL correction formula.

[0179] [5-1-2] Flow from exposure treatment to bonding treatment Figure 33 is a flowchart showing an example of a process related to the alignment correction of random components in the semiconductor manufacturing system PS according to the fifth embodiment. The flow from exposure processing to bonding processing in the fifth embodiment will be described below with reference to Figure 33.

[0180] First, the amount of warpage of the upper wafer UW, which is the target of exposure at the bonding surface, is measured (S310). The data on the amount of warpage of the upper wafer UW is transferred to the exposure apparatus 1 via, for example, the server 3 and stored in the storage device 11 of the exposure apparatus 1.

[0181] Next, exposure processing of the bonding surface of the upper wafer UW is performed (S410) using the OL correction formula created in the S400 process and the OL correction value based on the amount of warpage of the upper wafer UW measured in the S310 process. Specifically, the exposure apparatus 1 according to the fifth embodiment first calculates the OL correction values ​​of K17 and K18, for example, by substituting the numerical value of the amount of warpage of the upper wafer UW into the OL correction formula. Then, in the alignment correction process (S103 in Figure 9), the exposure apparatus 1 reflects the OL correction values ​​of K17 and K18 calculated based on the amount of warpage of the upper wafer UW into the OL correction value calculated by polynomial regression using the measurement results of at least three alignment marks AM. That is, the K value calculated by substituting the amount of warpage of the upper wafer UW into the OL correction formula is used for the correction of the K value. For example, the OL correction values ​​(K17 and K18) calculated based on the amount of warpage of the upper wafer UW are used as an offset for the alignment correction value in the wafer surface.

[0182] In addition, the pre-processing of the lower wafer LW is performed in parallel with the processing in S310 and S311 (S320). This forms the lower wafer LW.

[0183] Once the preceding processes for the associated upper wafer UW and lower wafer LW are completed (S330), a bonding process is performed (S331). This forms a bonded wafer BW in which the associated upper wafer UW and lower wafer LW are bonded. Other processes in the exposure apparatus 1 according to the fifth embodiment are the same as in the fourth embodiment.

[0184] [5-2] Effects of the fifth embodiment According to the exposure apparatus 1 of the fifth embodiment described above, similar to the fourth embodiment, the overlapping misalignment of the upper wafer UW during the exposure process becomes large, but the overlapping misalignment during the bonding process can be suppressed. As a result, the exposure apparatus 1 of the fifth embodiment can improve the yield of semiconductor devices, similar to the fourth embodiment.

[0185] In addition, a Zernike polynomial may be used to create the OL correction formula in the fifth embodiment, similar to the modification in the fourth embodiment. In this example, the OL correction formula is created using Zernike coefficients that have a strong correlation with the amount of warpage of the upper wafer UW. The exposure process 1 then calculates a correction value for the Zernike coefficient based on the amount of warpage of the upper wafer UW and uses it in the alignment correction process. That is, the exposure apparatus 1 may correct the numerical value of a predetermined Zernike coefficient in the alignment correction based on the correction value of a predetermined Zernike coefficient calculated based on the amount of warpage of the upper wafer UW. Even when a Zernike polynomial is used to create the OL correction formula, overlap misalignment in the bonding process can be suppressed in the same way as when polynomial regression coefficients are used.

[0186] [6] Others The flowchart used to describe the operation in the above embodiment is merely an example. The order of each operation described using the flowchart may be changed as far as possible, other processes may be added, or some processes may be omitted. In the above embodiment, the case in which alignment correction is applied to the lower wafer LW placed (held) on the lower stage 230 and then bonding is illustrated, but the invention is not limited to this. The alignment correction in the bonding process may be applied, for example, to the upper wafer UW placed (held) on the upper stage 233, or to both the upper wafer UW held on the upper stage 233 and the lower wafer LW held on the lower stage 230. The fourth embodiment may be combined with any of the first to third embodiments. The fifth embodiment may be combined with any of the first to third embodiments. In this specification, instead of a CPU, an MPU (Micro Processing Unit), ASIC (Application Specific Integrated Circuit), or FPGA (field-programmable gate array) may be used. Furthermore, each of the processes described in the embodiments may be implemented by dedicated hardware. The processes described in the embodiments may include a mixture of processes performed by software and processes performed by hardware, or they may consist of only one or the other.

[0187] The amount of wafer warpage may be measured by the exposure apparatus 1 or by an external measuring device. In this specification, the amount of wafer warpage is expressed, for example, by the difference between the height of the outer edge of the wafer and the height of the center of the wafer. For example, micrometers (μm) are used as the unit of wafer warpage. The amount of wafer warpage may also be expressed as a signed distance from a three-point reference plane based on the measurement result of the height of the center of the wafer. For example, the amount of wafer warpage is set to positive if it is above the three-point reference plane and negative if it is below. The amount of wafer warpage can be measured, for example, by calculating the wafer shape (warpage) by measuring the height of each coordinate of the wafer using a laser displacement meter, confocal displacement meter, capacitive type, heterodyne interferometer, Fizeau interferometer, etc.

[0188] In this specification, “connection” means being electrically connected and does not exclude the intervening of other elements. “Electrically connected” may be via an insulator, as long as it is possible to operate in the same way as if electrically connected. “Columnar” means a structure provided within a hole formed in the manufacturing process. “Plan view” corresponds to viewing the object perpendicular to the surface of the semiconductor substrate 80, for example. “Region” may be considered a configuration included by the semiconductor substrate 80 of the CMOS chip CC. For example, if the semiconductor substrate 80 is specified to include a memory region MR, the memory region MR is associated with the region above the semiconductor substrate 80. The bonding pad BP may be called the “bonding metal”. The camera 144 of the exposure apparatus 1 may be configured with a separate optical system (microscope) and a light-receiving sensor. Cameras 144, 232, and 235 may each be called a “measuring device” as long as they are capable of measuring the alignment mark AM. In this specification, “overlap misalignment” may be rephrased as “positional misalignment”.

[0189] The configuration described in the third embodiment is merely illustrative, and the configuration of the memory device 4 is not limited to those. The circuit configuration, planar layout, and cross-sectional structure of the memory device 4 can be appropriately modified according to the design of the memory device 4. For example, the third embodiment illustrates a case where the memory chip MC is provided on top of the CMOS chip CC, but the CMOS chip CC may be provided on top of the memory chip MC. The embodiment illustrates a case where the memory chip MC is assigned to the lower wafer LW and the CMOS chip CC is assigned to the upper wafer UW, but the memory chip MC may be assigned to the upper wafer UW and the CMOS chip CC may be assigned to the lower wafer LW. When applying the manufacturing method described in the first and second embodiments, it is preferable that the wafer with a large variation in wafer magnification between wafers be assigned to the lower wafer LW. This can suppress overlapping misalignment during the bonding process, thereby suppressing the occurrence of defects caused by overlapping misalignment.

[0190] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0191] 1…Exposure device, 2…Bonding device, 3…Server, 4…Memory device, 10…Control device, 11…Storage device, 110…Exposure recipe, 111…Correction value information, 12…Transport device, 13…Communication device, 14…Exposure unit, 140…Wafer stage, 141…Reticle stage, 142…Light source, 143…Projection optical system, 144…Camera, 20…Control device, 21…Transport device, 22…Communication device, 23…Bonding unit, 230…Lower stage, 231…Stress device, 232…Camera, 233…Upper stage, 234…Pressing pin, 235…Camera, 236…Common target, 30…CPU, 31…ROM, 32…RAM, 33…Storage device, 34…Communication device, 40…Memory interface Face, 41... Sequencer, 42... Memory cell array, 43... Driver module, 44... Row decoder module, 45... Sense amplifier module, 50-57... Insulator layer, 50... Insulator layer, 51-57... Insulator layer, 60-66... ​​Conductive layer, 70... Core component, 71... Semiconductor layer, 72... Multilayer film, 73... Tunnel insulating film, 74... Insulating film, 75... Block insulating film, 80... Semiconductor substrate, 81-84... Conductive layer, C0-C3, V1, V2... Contacts, M0-M2, D0-D3... Wiring layer, BLK... Block, SU... String unit, MT... Memory cell transistor, TR... Transistor, BL... Bit line, WL... Word line, SGD, SGS... Selected gate line

Claims

1. An exposure apparatus for exposing a substrate, A stage configured to hold the aforementioned substrate, A storage device configured to store multiple correction maps having different alignment correction values, The system includes a control device configured to control the exposure position on the substrate by selecting one correction map from the plurality of correction maps based on the measurement results of a plurality of alignment marks placed on the substrate or the amount of warpage of the substrate, and moving the stage based on the selected correction map. Exposure apparatus.

2. The exposure includes exposure of the substrate in multiple shots, The correction map includes alignment correction values ​​for each shot. The exposure apparatus according to claim 1.

3. The device further comprises a measuring device for measuring the aforementioned plurality of alignment marks, The control device, in the exposure process of the substrate, calculates an alignment correction coefficient for the magnification component within the plane of the substrate based on the measurement results of the plurality of alignment marks, and selects one correction map from the plurality of correction maps based on the magnitude of the alignment correction coefficient. The exposure apparatus according to claim 1.

4. The exposure apparatus according to claim 1, wherein the selection of one correction map from the plurality of correction maps is based on the amount of warping of the substrate.

5. An exposure apparatus for exposing a substrate, A stage configured to hold the aforementioned substrate, A measuring device configured to measure a plurality of alignment marks formed on the substrate, The system includes a control device configured to control the exposure position on the substrate by moving the stage based on a first alignment correction coefficient and a second alignment correction coefficient, The control device calculates the first alignment correction coefficient by polynomial regression using the measurement results of the alignment marks during the exposure process of the substrate, and corrects the second alignment correction coefficient based on the magnitude of the first alignment correction coefficient or the amount of warping of the substrate. Exposure apparatus.

6. The first alignment correction coefficient corresponds to the positional misalignment of the magnification component, The exposure apparatus according to claim 5.

7. The second alignment correction coefficient is calculated by the polynomial regression and corrected based on the magnitude of the first alignment correction coefficient. The exposure apparatus according to claim 5.

8. The exposure position is represented by a coordinate system using the X direction and the Y direction intersecting the X direction, where the X coordinate is "x" and the Y coordinate is "y", The alignment correction formula in the X direction is K3·x and K17·x·y ２ The sum of the following, The alignment correction formula in the Y direction is K4·y and K18·x ２ - Includes the sum with y, The K3 and K4 correspond to the first alignment correction coefficients, The K17 and K18 correspond to the second alignment correction coefficients, The exposure apparatus according to claim 7.

9. The second alignment correction coefficient is the coefficient of the Zernike polynomial. The exposure apparatus according to claim 5.

10. Based on the measurement results of multiple alignment marks placed on the substrate or the amount of warping of the substrate, one correction map is selected from multiple correction maps having different alignment correction values. The method includes controlling the exposure position on the substrate based on the selected correction map. Exposure method.

11. The correction map includes alignment correction values ​​for each shot. The exposure method according to claim 10.

12. Measuring the aforementioned multiple alignment marks, Based on the measurement results of the alignment marks, the alignment correction coefficient of the magnification component within the plane of the substrate is calculated, The system further comprises selecting one correction map from a plurality of correction maps based on the magnitude of the alignment correction coefficient. The exposure method according to claim 10.

13. The exposure method according to claim 10, wherein selecting one correction map from the plurality of correction maps is based on the amount of warpage of the substrate.

14. Measuring alignment marks formed on the circuit board, The first alignment correction coefficient is calculated by polynomial regression using the measurement results of the alignment marks, The second alignment correction coefficient is corrected based on the magnitude of the first alignment correction coefficient or the amount of warpage of the substrate, The method includes controlling the exposure position on the substrate based on the first alignment correction coefficient and the corrected second alignment correction coefficient. Exposure method.

15. The first alignment correction coefficient corresponds to the positional misalignment of the magnification component, The exposure method according to claim 14.

16. The second alignment correction coefficient is calculated by the polynomial regression and corrected based on the magnitude of the first alignment correction coefficient. The exposure method according to claim 14.

17. The exposure position is represented by a coordinate system using the X direction and the Y direction intersecting the X direction, where the X coordinate is "x" and the Y coordinate is "y", The alignment correction formula in the X direction is K3·x and K17·x·y ２ The sum of the following, The alignment correction formula in the Y direction is K4·y and K18·x ２ - Includes the sum with y, The K3 and K4 correspond to the first alignment correction coefficients, The K17 and K18 correspond to the second alignment correction coefficients, The exposure method according to claim 16.

18. The second alignment correction coefficient is the coefficient of the Zernike polynomial. The exposure method according to claim 14.

19. A semiconductor manufacturing system comprising an exposure apparatus for exposing a substrate and a bonding apparatus for bonding two of the substrates, The exposure apparatus is A stage configured to hold the aforementioned substrate, A measuring device for measuring multiple alignment marks arranged on the aforementioned substrate, A storage device configured to store multiple correction maps having different alignment correction values, The system includes a control device configured to control the exposure position on the substrate by selecting one correction map from a plurality of correction maps based on the measurement results of the plurality of alignment marks or the amount of warpage of the substrate during exposure processing on the substrate, and by moving the stage based on the selected correction map. The bonding apparatus is a semiconductor manufacturing system that, after the exposure process, performs a bonding process on each of the two substrates using the correction map selected in the exposure process.

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