Sense amplifier circuit and semiconductor memory device

Abstract

To provide a sense amplifier and a semiconductor storage device, capable of reducing an effect of a capacity difference between bit line side input and reference potential side input to increase a reading margin to achieve a highly reliable operation.SOLUTION: A sense amplifier circuit of an embodiment is a complementary and latch type sense amplifier circuit in which an input signal is input from each of a pair of input terminals to a corresponding gate terminal in a sense amplifier main body, and includes an isolation gate that electrically isolates the input terminal from the corresponding gate terminal before the sense amplifier main body effectively becomes an enable state, and capacitive elements having capacity identical to each other, connected between the gate terminal and a power supply.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] ,

[0004]

[0001] Embodiments of the present invention relate to a sense amplifier circuit and a semiconductor memory device.

Background Art

[0002] In recent years, a sense amplifier circuit is known as a circuit for reading a minute signal such as data stored in a memory cell. When performing complementary input of such a sense amplifier circuit, the capacitances of the bit line side input and the reference potential side input are different.

Prior Art Documents

Patent Documents

[0008] The sense amplifier circuit of the embodiment is a complementary, latching sense amplifier circuit in which input signals are input to the sense amplifier body from each of a pair of input terminals to corresponding gate terminals, and comprises an isolation gate that electrically isolates the input terminals and the corresponding gate terminals prior to the sense amplifier body becoming effectively enabled, and capacitive elements with equal capacitance connected between the gate terminals and the power supply, respectively. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is an explanatory diagram illustrating the schematic configuration of a semiconductor memory device according to an embodiment. [Figure 2] Figure 2 is an explanatory diagram illustrating an example of the main components of a sense amplifier circuit according to an embodiment. [Figure 3] Figure 3 is a flowchart of the operation process of the embodiment. [Figure 4] Figure 4 is an explanatory diagram of the signal waveforms for each part. [Figure 5] Figure 5 illustrates the change in input signal voltage in a conventional example with a noise cancellation circuit and in this embodiment. [Figure 6] Figure 6 shows the cumulative failure rate in a conventional example with a noise cancellation circuit and in this embodiment. [Figure 7] Figure 7 is an explanatory diagram of an example of the main components of a modified sense amplifier circuit according to the embodiment. [Figure 8] Figure 8 is a timing chart of a modified example of the embodiment. [Modes for carrying out the invention]

[0010] The semiconductor memory device of the embodiment will be described in detail below with reference to the drawings. However, the present invention is not limited by these embodiments.

[0011] Figure 1 is an explanatory diagram illustrating the schematic configuration of a semiconductor memory device according to an embodiment. The semiconductor device 10 is configured as a NOR-type flash memory and, as shown in Figure 1, includes a memory cell array 11, a row decoder 12, a column decoder 13, a reference potential generation circuit 14, a sense amplifier circuit 15, a data output circuit 16, and a control circuit 17.

[0012] The memory cell array 11 comprises multiple memory cells MC arranged in a grid pattern. Furthermore, the memory cell array includes multiple word lines WL, multiple source lines SL, and multiple bit lines BL.

[0013] In Figure 1, for ease of understanding, only one selected memory cell MC is displayed, and only the word line WL, source line SL, and bit line BL corresponding to that memory cell are shown.

[0014] Here, the memory cell MC includes a memory cell transistor TR, the source terminal of which is connected to the source line SL, the gate terminal of which is connected to the word line WL, and the drain terminal of which is connected to the bit line BL.

[0015] The row decoder 12, under the control of the control circuit 17, enables the word line WL corresponding to the memory cell MC to be read. The column decoder 13, under the control of the control circuit 17, enables the source line SL and bit line BL corresponding to the memory cell MC to be read.

[0016] The reference potential generation circuit 14 generates and supplies a reference potential to the sense amplifier circuit 15. The sense amplifier circuit 15 compares the bit line voltage Vb corresponding to the memory cell MC in the selected state at a predetermined timing with the reference voltage Vref, determines the data of the memory cell MC, and outputs the determination result to the data output circuit 16.

[0017] The data output circuit 16 outputs the read data DOUT based on the output of the sense amplifier circuit 15.

[0018] The control circuit 17 controls the row decoder 12, the column decoder 13, and the sense amplifier circuit 15 to write, read, or erase data to / from the corresponding memory cell MC based on the clock signal CLK, the command data CMD, and the address data ADD from a host device (e.g., MPU) not shown.

[0019] Next, the configuration of the sense amplifier circuit 15 will be described. FIG. 2 is an explanatory diagram of a main part configuration example of the sense amplifier circuit of the embodiment. The sense amplifier circuit 15 includes a latch type sense amplifier section 21, a first isolation gate 22, a second isolation gate 23, a first equivalent capacitance element 24, and a second equivalent capacitance element 25.

[0020] The latch type sense amplifier section 21 includes a sense amplifier enable section 31 and a sense amplifier main body section 32.

[0021] The sense amplifier enable section 31 This is the part of the latch-type sense amplifier section 21 excluding the sense amplifier main body section 32. includes a first P-channel MOS transistor 41, a second P-channel MOS transistor 42, a third P-channel MOS transistor 43, a fourth P-channel MOS transistor 44, and an N-channel MOS transistor 45.

[0022] The first P-channel MOS transistor 41 has a sense amplifier enable signal input to its gate terminal and its source terminal connected to the high potential side power supply VDD. The second P-channel MOS transistor 42 has a sense amplifier enable signal input to its gate terminal and its source terminal connected to the high-potential power supply VDD.

[0023] The third P-channel MOS transistor 43 has a sense amplifier enable signal input to its gate terminal and its source terminal connected to the high-potential power supply VDD. The fourth P-channel MOS transistor 44 has a sense amplifier enable signal input to its gate terminal and its source terminal connected to the high-potential power supply VDD.

[0024] The N-channel MOS transistor 45 has a sense amplifier enable signal input to its gate terminal and its source terminal connected to the low-potential power supply VSS.

[0025] The sense amplifier main unit 32 includes a first P-channel MOS transistor 51, a first N-channel MOS transistor 52, a second P-channel MOS transistor 53, a second N-channel MOS transistor 54, a first input N-channel MOS transistor 55, and a second input N-channel MOS transistor 56.

[0026] The first P-channel MOS transistor 51 has its source terminal connected to the high-potential power supply VDD, its drain terminal connected to the drain terminal of the second P-channel MOS transistor 42 via the first sense amplifier output terminal SAO1, and its gate terminal connected to the second sense amplifier output terminal SAO2.

[0027] The first N-channel MOS transistor 52 is connected in series with the first P-channel MOS transistor 51, with its drain terminal connected to the drain terminal of the first P-channel MOS transistor 41 and its gate terminal connected to the second sense amplifier output terminal SAO2.

[0028] The second P-channel MOS transistor 53 has its source terminal connected to the high-potential power supply VDD, its drain terminal connected to the second sense amplifier output terminal SAO2, ​​and its gate terminal connected to the first sense amplifier output terminal SAO1.

[0029] The second N-channel MOS transistor 54 is directly connected to the second P-channel MOS transistor 53, with its drain terminal connected to the drain terminal of the third P-channel MOS transistor 43, and its gate terminal connected to the output terminal SAO1 of the first sense amplifier.

[0030] The first input N-channel MOS transistor 55 is connected in series between the first N-channel MOS transistor 52 and the N-channel MOS transistor 45, and its gate terminal is connected to the first input terminal Ti1.

[0031] The second input N-channel MOS transistor 56 is connected in series between the second N-channel MOS transistor 54 and the N-channel MOS transistor 45, and its gate terminal is connected to the second input terminal Ti2.

[0032] Furthermore, the first isolation gate 22 receives a sense amplifier enable signal SAE at its gate terminal and is connected between the first input terminal Ti1 and the gate terminal of the first input N-channel MOS transistor 55, electrically disconnecting the latch-type sense amplifier section 21 from the first input terminal Ti1 when sense is enabled.

[0033] The second isolation gate 23 receives a sense amplifier enable signal SAE at its gate terminal and is connected between the second input terminal Ti2 and the gate terminal of the second input N-channel MOS transistor 56, electrically disconnecting the latch-type sense amplifier section 21 from the second input terminal Ti2 when sense is enabled.

[0034] The first equivalent capacitance element 24 is configured as an N-channel MOS transistor, with its gate terminal connected to the gate terminal of the first input N-channel MOS transistor 55, and its source and drain terminals connected to the low-potential power supply VSS, and effectively functions as a capacitance element with a predetermined capacitance.

[0035] Similarly, the second equivalent capacitance element 25 is configured as an N-channel MOS transistor with its gate terminal connected to the gate terminal of the second input N-channel MOS transistor 56, and its source and drain terminals connected to the low-potential power supply VSS, and effectively functions as a capacitance element with a predetermined capacitance.

[0036] Since the first equivalent capacitance element 24 and the second equivalent capacitance element 25 are formed in the same semiconductor manufacturing process with the same configuration and size, they have the same capacitance.

[0037] In the above configuration, the first input terminal Ti1 is connected to the bit line corresponding to the memory cell MC, and the bit line voltage Vb is applied to it. The second input terminal Ti2 is connected to the reference potential generation circuit 14, and the reference voltage Vref is applied to it.

[0038] Next, the operation of the sense amplifier circuit 15 of this embodiment will be described. First, let me explain the conventional problems. In conventional sense amplifier circuits, when complementary inputs are used, the capacitance Cin+ of the bit line side input (Vin+), which is the input to the first input terminal Ti1, and the capacitance Cin- of the reference potential side input (Vin-), which is the input to the second input terminal Ti2, are different from those of the sense amplifier circuit.

[0039] In other words, Cin+ ≠ Cin- That's how it was.

[0040] Therefore, during the operation of the sense amplifier circuit, parasitic capacitance coupling between the gate terminal-source terminal and gate terminal-drain terminal of the pair of input MOS transistors corresponding to the first input N-channel MOS transistor 55 and the second input N-channel MOS transistor 56 of this embodiment generated asymmetric coupling noise at the complementary input, causing misreading.

[0041] Furthermore, because the reference potential has high impedance, if the fluctuations caused by the generated coupling noise are large, the reference voltage will not stabilize by the next cycle, leading to erroneous readings.

[0042] Therefore, conventionally, it has been proposed to add a stabilizing capacitor to each sense amplifier in the complementary pair to suppress coupling noise. However, adding a stabilizing capacitor leads to a decrease in readout speed and an increase in installation area, which increases the circuit area and hinders the miniaturization of the device.

[0043] Furthermore, while it has been proposed to add a noise cancellation circuit to counteract coupling noise, there was a risk that the offset voltage of the sense amplifier circuit would increase due to manufacturing variations in the noise cancellation circuit itself.

[0044] This embodiment reduces the effect of the capacitance difference between the bit line input and the reference potential input without providing a stabilizing capacitor or noise cancellation circuit, thereby increasing the read margin and enabling highly reliable operation.

[0045] More specifically, when sense is enabled (when data is read out by the sense amplifier circuit: sense time), the latch-type sense amplifier section 21 is electrically disconnected from the first input terminal Ti1 and the second input terminal Ti2 by the first equivalent capacitance element 24 and the second equivalent capacitance element 25, so that the capacitance is equivalent in complementary pairs.

[0046] Then, after the data readout by the sense amplifier circuit is complete and the pre-charging of the first equivalent capacitance element 24 and the second equivalent capacitance element 25 is complete, the latch-type sense amplifier section 21 is electrically reconnected to the first input terminal Ti1 and the second input terminal Ti2 by the first isolation gate 22 and the second isolation gate 23, thereby enabling operation without being affected by coupling noise.

[0047] Figure 3 is a flowchart of the operation process of the embodiment. Figure 4 is an explanatory diagram of the signal waveforms for each part. In the following explanation, the sense amplifier enable signal SAE is assumed to be high-active. Furthermore, each part in Figure 4 corresponds to positions A to E in Figure 2.

[0048] The control circuit 17 outputs a "H" level sense amplifier enable signal SAE to the sense amplifier circuit 15, causing it to transition to the sense enable state (step S11). As a result, the P-channel MOS transistors constituting the first isolation gate 22 and the second isolation gate 23 are turned off. Consequently, the first input terminal Ti1 and the second input terminal Ti2 are electrically isolated from the sense amplifier main unit 32 (step S12).

[0049] More specifically, as shown at time t1 in Figure 4, when the sense amplifier enable signal SAE transitions to the "H" level, the P-channel MOS transistors constituting the first isolation gate 22 and the second isolation gate 23 are turned off. As a result, the sense amplifier main unit 32 is not affected by the difference between the capacitance Cin+ of the bit line side input (Vin+), which is the input on the first input terminal Ti1 side, and the capacitance Cin- of the reference potential side input (Vin-), which is the input on the second input terminal Ti2 side.

[0050] Furthermore, the sense amplifier main unit 32 is configured such that a first equivalent capacitance element 24 and a second equivalent capacitance element 25, both having equal capacitance, are connected.

[0051] As a result, although the voltages at points A and B decrease due to coupling noise, the capacitances of the first equivalent capacitance element 24 and the second equivalent capacitance element 25 are the same. Therefore, even if coupling noise occurs, its magnitude is equal to that of a complementary pair, causing them to cancel each other out. Thus, unlike in conventional examples, the system is not affected by coupling noise.

[0052] In this state, the sense amplifier main unit 32 performs a sense operation, and when the sense operation is completed, it outputs the sense result from the first sense amplifier output terminal SAO1 and the second sense amplifier output terminal SAO2 (step S13).

[0053] Therefore, the outputs of the first sense amplifier output terminal SAO1 and the second sense amplifier output terminal SAO2 can have large voltage changes, as shown as the voltages at points D and E in Figure 4, allowing for reliable identification of stored data and obtaining a highly reliable output unaffected by coupling noise.

[0054] Next, after the sense amplifier main unit 32 has finished outputting the sense result, the control circuit 17 outputs a "L" level sense amplifier enable signal SAE to the sense amplifier circuit 15 to switch to the sense disabled state (step S14), and precharges the first equivalent capacitance element 24 and the second equivalent capacitance element 25 (step S15). Here, the pre-charging of the first equivalent capacitance element 24 and the second equivalent capacitance element 25 occurs when the first P-channel MOS transistor 41 and the fourth P-channel MOS transistor 44 are turned on. This pre-charges the drain terminals of the first input N-channel MOS transistor 55 and the second input N-channel MOS transistor 56, and is achieved by capacitive coupling between the drain and gate of the first input N-channel MOS transistor 55 and the second input N-channel MOS transistor 56.

[0055] Pre-charging of the first equivalent capacitance element 24 and the second equivalent capacitance element 25 and at the same time Next, the P-channel MOS transistors constituting the first isolation gate 22 and the second isolation gate 23 are turned ON (step S16), and the sense amplifier main unit 32 transitions to a standby state.

[0056] As described above, according to this embodiment, high-speed operation is possible because a stabilization capacitor is not required, and a sense amplifier with a small area can be realized. Furthermore, because a noise cancellation circuit is unnecessary, the offset voltage can be reduced, enabling high-speed operation.

[0057] Figure 5 illustrates the change in input signal voltage in a conventional example with a stabilized capacitor and in this embodiment. According to this embodiment, as shown in Figure 5, the voltage change of the input signal can be made rapid (for example, in the case of Figure 5, an improvement of about 16% compared to the conventional method), making it possible to achieve faster operation.

[0058] Figure 6 shows the cumulative failure rate in a conventional example with a noise cancellation circuit and in this embodiment. As shown in Figure 6, when compared with the same input potential difference, the cumulative failure rate corresponding to misjudgment can be made significantly lower than in the conventional example, indicating that misjudgment does not occur even with a smaller input potential difference.

[0059] Furthermore, according to this embodiment, fluctuations in the reference potential can be suppressed, which reduces data fluctuations and improves reliability.

[0060] Next, a modified example of the embodiment will be described. Figure 7 is an explanatory diagram of an example of the main components of a modified sense amplifier circuit according to the embodiment. In Figure 7, the same reference numerals are used for parts that are the same as those in Figure 2. In Figure 7, the difference from Figure 2 is that the first isolation gate 22 and the second isolation gate 23 are controlled by a control signal ISO that is different from the sense amplifier enable signal SAE.

[0061] In the above embodiment, since the first isolation gate 22 and the second isolation gate 23 were controlled by the sense amplifier enable signal SAE, depending on the situation, there was a possibility that the system would transition to the data reading state while the first input terminal Ti1 and the second input terminal Ti2 could not be electrically isolated from the sense amplifier main unit 32, as in the conventional system.

[0062] Furthermore, even after the data output was complete, there was a possibility that the sense amplifier main unit 32 would be electrically connected to the first input terminal Ti1 and the second input terminal Ti2 before the system could be reliably returned to its initial state.

[0063] Figure 8 is a timing chart of a modified example of the embodiment. Therefore, in the modified embodiment, at time t1 before transitioning to the sense-enabled state, the control signal ISO is set to the "H" level, and the first isolation gate 22 and the second isolation gate 23 are controlled to reliably transition to the off state.

[0064] Then, at time t2, after the first separation gate 22 and the second separation gate 23 have been reliably turned off, the sense amplifier enable signal SAE is set to the "H" level to switch the sense amplifier main unit 32 to the enabled state.

[0065] Furthermore, when the sense amplifier main unit 32 has finished outputting the sense result and the sense operation has reached a completion state, at time t3, the sense amplifier enable signal SAE is set to "L" level to disable the sense amplifier main unit 32.

[0066] Then, at time t4, after the sense amplifier main unit 32 has completely transitioned to the disabled state, the control signal ISO is set to the "L" level, controlling the first isolation gate 22 and the second isolation gate 23 so that the sense amplifier main unit 32 can output the sense result, reaching the sense operation completion state, and the pre-charging of the first equivalent capacitance element 24 and the second equivalent capacitance element 25 is reliably completed, returning them to their initial state, and the process ends.

[0067] Therefore, according to the modified embodiment, in addition to the effects of the embodiment, more stable operation can be achieved, and further improvements in reliability can be made.

[0068] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0069] 10 Semiconductor Devices 11 memory cell array 12 Raw Decoders 13-column decoder 14. Reference potential generation circuit 15 Sense Amplifier Circuit 16. Data output circuit 17 Control circuits 21 Latch-type sense amplifier section 22. First Separation Gate 23 Second Separation Gate 24 First Equivalent Capacitance Element 25 Second Equivalent Capacitance Element 31 Sense Amplifier Enable Section 32 Sense Amplifier Main Unit 41. First P-channel MOS transistor 42. Second P-channel MOS transistor 43. Third P-channel MOS transistor 44. 4th P-channel MOS transistor 45 N-channel MOS transistors 51. First P-channel MOS transistor 52 First N-channel MOS transistor 53. Second P-channel MOS transistor 54. Second N-channel MOS transistor 55 First Input N-Channel MOS Transistor 56. Second input N-channel MOS transistor ADD Address Data BL bit line ISO Control Signals MC memory cell SAE Sense Amplifier Enable Signal SAO1 First Sense Amplifier Output Terminal SAO2 2nd Sense Amplifier Output Terminal Ti1 First Input Terminal Ti2 Second Input Terminal VDD High potential side power supply VSS Low potential side power supply Vb bit line voltage Vref Reference Voltage

Claims

1. In a complementary, latching sense amplifier circuit in which input signals are input to the sense amplifier main unit from each of a pair of input terminals to the corresponding gate terminals, Prior to the sense amplifier main unit becoming effectively enabled, an isolation gate electrically isolates the input terminal and the corresponding gate terminal, Capacitive elements with equal capacitance connected between the gate terminal and the power supply, Equipped with a sense amplifier circuit.

2. The isolation gate operates in such a way as to electrically isolate the input terminal from the corresponding gate terminal by a sense amplifier enable signal that enables the sense amplifier main unit. The sense amplifier circuit according to claim 1.

3. The isolation gate operates by a control signal separate from the sense amplifier enable signal that enables the sense amplifier main unit, in order to electrically isolate the input terminal and the corresponding gate terminal prior to the sense amplifier main unit being enabled. The sense amplifier circuit according to claim 1.

4. The gate terminal is in a floating state when electrically isolated from the input terminal by the isolation gate. The sense amplifier circuit according to claim 1.

5. The isolation gate, after the sense operation in the sense amplifier main body is completed, electrically connects the input terminal and the corresponding gate terminal at the same time as precharging the capacitive element. The sense amplifier circuit according to claim 1.

6. The isolation gate is composed of a P-channel MOS transistor. The sense amplifier circuit according to claim 1.

7. The aforementioned capacitive element is composed of an N-channel MOS transistor. The sense amplifier circuit according to claim 1.

8. One of the input terminals is connected to the bit line of the corresponding memory cell. The other input terminal is connected to the reference power supply. The sense amplifier circuit according to claim 1.

9. A memory cell that stores data, A bit line for transmitting the signal read from the memory cell, The system includes a sense amplifier circuit that detects data stored in the memory cell based on a signal transmitted on the bit line, The aforementioned sense amplifier circuit is In a complementary, latching sense amplifier circuit in which input signals are input to the sense amplifier main unit from each of a pair of input terminals to the corresponding gate terminals, Prior to the sense amplifier main unit becoming effectively enabled, an isolation gate electrically isolates the input terminal and the corresponding gate terminal, Capacitive elements with equal capacitance connected between the gate terminal and the power supply, Equipped with, Semiconductor memory device.

Images