Power converter

Abstract

To provide a power converter that achieves both low inductance and low noise.SOLUTION: A power converter comprises: an upper arm semiconductor element connected to positive electrode wiring; a lower arm semiconductor connected to negative electrode wiring; first AC wiring that connects the upper arm semiconductor element with the lower arm semiconductor element; and second AC wiring that connects the upper arm semiconductor element with the lower arm semiconductor element. The first AC wiring is formed at a position opposed to the positive electrode wiring and the negative electrode wiring with the upper arm semiconductor element and the lower arm semiconductor element being interposed therebetween. The second AC wiring is formed at a position opposed to the first AC wiring with the upper arm semiconductor and the lower arm semiconductor being interposed therebetween, and is stacked on the positive electrode wiring and the negative electrode wiring.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a power conversion device.

Background Art

[0002] A semiconductor device using a SiC (Silicon Carbide) chip is required to have a configuration in which a large number of chips are mounted in parallel and driven by utilizing the characteristics of high-speed switching and a small chip size. This is a necessary configuration from the viewpoint of improving the yield of the power module included in the power conversion device and facilitating the adjustment of the source inductance. However, in order to connect the power modules of one chip in parallel, it is necessary to achieve low inductance.

[0003] For example, in Patent Document 1 below, a circuit board having AC output terminals on both sides of a lead frame and having a configuration that creates a steep current bypass circuit is disclosed, in which the currents flowing through the upper and lower wiring patterns of the substrate oppose each other and cancel out the magnetic flux.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the conventional structure, when SiC chips are connected in parallel to increase the capacitance, the AC wiring and the signal wiring cross and magnetically couple, resulting in a problem that magnetic coupling noise is generated in the signal circuit due to the generation of a strong magnetic field accompanying the steep transient current flowing through the AC output side during switching. In view of this, an object of the present invention is to provide a power conversion device that achieves both low inductance and low noise.

Means for Solving the Problems

[0006] The power converter includes an upper arm semiconductor element connected to a positive electrode wiring, a lower arm semiconductor element connected to a negative electrode wiring, a first AC wiring connecting the upper arm semiconductor element and the lower arm semiconductor element, and a second AC wiring connecting the upper arm semiconductor element and the lower arm semiconductor element. The first AC wiring is formed with the upper arm semiconductor element and the lower arm semiconductor element in between, and is positioned opposite the positive electrode wiring and the negative electrode wiring. The second AC wiring is formed with the upper arm semiconductor element and the lower arm semiconductor element in between, and is positioned opposite the first AC wiring, and is stacked with the positive electrode wiring and the negative electrode wiring. [Effects of the Invention]

[0007] We can provide a power conversion device that achieves both low inductance and low noise. [Brief explanation of the drawing]

[0008] [Figure 1] Diagram illustrating a semiconductor device constituting a power converter according to one embodiment of the present invention. [Figure 2] An explanatory diagram of the second current path passing through the second AC wiring according to one embodiment of the present invention. [Figure 3] Molded semiconductor device and exploded view of the semiconductor device. [Figure 4] Modified version of Figure 1 [Figure 5] Diagram illustrating the first layer in the case of a three-phase inverter according to one embodiment of the present invention. [Figure 6] Diagram illustrating the second layer in Figure 5.

[0009] Embodiments of the present invention will be described below with reference to the drawings. The following description and drawings are illustrative for illustrating the present invention, and have been omitted and simplified as appropriate for clarity of explanation. The present invention can also be carried out in various other forms. Unless otherwise specified, each component may be singular or plural.

[0010] The positions, sizes, shapes, and ranges of the components shown in the drawings may not represent their actual positions, sizes, shapes, and ranges in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, and ranges disclosed in the drawings.

[0011] (An embodiment of the present invention and the overall configuration of the apparatus) (Figure 1) Figure 1(a) is a perspective view of the semiconductor device 50, and Figure 1(b) is a top view of Figure 1(a). Note that only the main components of the semiconductor device 50 are shown, and the mold and insulating layer of the substrate of the semiconductor device 50 are omitted.

[0012] The semiconductor device 50 has a positive electrode wiring 1 and a negative electrode wiring 2, an upper arm semiconductor device 3a and a lower arm semiconductor device 3b, an AC output wiring 4 (first AC wiring 4) and a second AC wiring 14. The upper arm semiconductor device 3a and the lower arm semiconductor device 3b each have a gate signal terminal 7 and a source signal terminal 8, respectively. The gate signal terminal 7 is connected to the gate signal wiring 9, and the source signal terminal 8 is connected to the source signal wiring 10. The signal wirings 9 and 10, which are connected to the upper arm semiconductor device or the lower arm semiconductor device via terminals 7 and 8, are located on the side where the AC output wiring 4 is formed. The upper arm semiconductor device 3a and the lower arm semiconductor device 3b have drain terminals 5a and 5b and source terminals 6a and 6b.

[0013] The upper arm semiconductor device 3a and the lower arm semiconductor device 3b are equipped with semiconductor elements such as SiC chips. Hereinafter, the semiconductor elements provided in the upper arm semiconductor device 3a will be referred to as upper arm semiconductor elements, and the semiconductor elements provided in the lower arm semiconductor device 3b will be referred to as lower arm semiconductor elements. The upper arm semiconductor elements are connected to the positive electrode wiring 1. The lower arm semiconductor elements are connected to the negative electrode wiring 2.

[0014] Capacitor 13 is, for example, a ceramic capacitor and is connected to the AC output wiring 4 via an upper arm semiconductor element and a lower arm semiconductor element. Capacitor 13 is also connected to the positive electrode wiring 1 and the negative electrode wiring 2. The second AC wiring 14 is formed in a layer below the wiring layer in which the positive electrode wiring 1 and the negative electrode wiring 2 are formed, and is stacked with the positive electrode wiring 1 and the negative electrode wiring 2. In Figure 1, the second AC wiring 14 is structured so that only a portion of it is exposed at the location of capacitor 13 between the positive electrode wiring 1 and the negative electrode wiring 2.

[0015] The AC output wiring 4 is an output phase connected to the wiring of a three-phase motor (not shown). The AC output wiring 4 and the second AC wiring 14 are connected to the upper arm semiconductor element and the lower arm semiconductor element, respectively. The AC output wiring 4 is formed in a position opposite the positive electrode wiring 1 and the negative electrode wiring 2, with the upper arm semiconductor element and the lower arm semiconductor element in between. The second AC wiring 14 is formed in a position opposite the AC output wiring 4, with the upper arm semiconductor element and the lower arm semiconductor element in between.

[0016] (Figure 2) Figure 2(a) is a diagram illustrating the second current path 200 flowing through the semiconductor device 50 according to the present invention, and Figure 2(b) is a cross-sectional view of Figure 2(a) from the direction of arrow R. Conventionally, the AC output wiring 4 was connected to the AC output wiring of the wiring layer in the lower layer of the substrate (not shown) via via 23, and was also connected to the upper arm semiconductor device 3a and the lower arm semiconductor device 3b. However, in this configuration, there was a risk that a steep current would flow through the AC output wiring 4 into the path 100 when the upper arm semiconductor device 3a or the lower arm semiconductor device 3b was switched. Furthermore, the flow of a steep current in the path 100 caused magnetic noise to be generated in the gate signal wiring 9 and source signal wiring 10 wired on top of the AC output wiring 4, which could reduce the reliability of the operation of the semiconductor device 50.

[0017] Therefore, in the present invention, the upper arm semiconductor device 3a and the lower arm semiconductor device 3b are provided with drain terminals 5a, 5b and source terminals 6a, 6b at both ends thereof. Further, a second AC wiring 14 is provided under the positive electrode wiring 1, the negative electrode wiring 2, and the capacitor 13. The second AC wiring 14 is connected to the upper arm semiconductor device 3a and the lower arm semiconductor device 3b via the via 23 and through the drain terminal 5a and the source terminal 6b to the conductor in the upper layer. Note that the wiring 14 connected to the terminals 5a, 6b and the via 23 is connected by solder 19.

[0018] In this way, with the configuration in which the second AC wiring 14 has a laminated structure with respect to the positive electrode wiring 1 and the negative electrode wiring 2, a second current path 200 is formed during switching, and currents flow in opposite directions to each other. That is, the inductance of the positive electrode wiring 1 and the negative electrode wiring 2 is reduced by canceling the magnetic flux due to the steep current generated in the positive electrode wiring 1 and the negative electrode wiring 2 with the magnetic flux due to the steep current generated in the second AC wiring 14.

[0019] Also, a steep current on the AC side flows through the second AC wiring 14, and at the same time, currents also flow in opposite directions to the upper arm semiconductor device 3a and the lower arm semiconductor device 3b. By canceling the magnetic flux of the positive electrode wiring 1 and the negative electrode wiring 2, the inductance of the second AC wiring 14 is also reduced. Further, since a steep current flows through the second AC wiring 14 having such a low inductance, the steep current (the current passing through the first current path 100) flowing through the AC output wiring 4 on the signal wiring 9, 10 side is reduced, and the magnetic noise applied to the reduced signal wiring 9, 10 is reduced. In this way, it is possible to achieve both low inductance and low noise.

[0020] (FIG. 3) FIG. 3(a) is an overall perspective view of the semiconductor device 50 encapsulated with a molding resin, and FIG. 3(b) is an exploded view of the semiconductor device 50. In the semiconductor device 50 encapsulated by the resin 16, a part of the source conductor 15 is exposed. Also, although not shown, a part of the drain conductor 17 is similarly exposed on the surface (back surface) opposite to the side where a part of the source conductor 15 is exposed. Further, the source terminal 6a, gate signal terminal 7, source signal terminal 8, drain terminal 5b, drain terminal 5a, and source terminal 6b protrude outside from the molding part.

[0021] The source terminal 6a and the source terminal 6b are electrically connected to the source conductor 15 via the solder 19. The gate signal terminal 7 and the source signal terminal 8 are electrically connected to the SiC chip 18 via the wire 21. The SiC chip 18 is disposed between the source conductor 15 and the drain conductor 17 and is electrically connected to each conductor by the solder 19.

[0022] An insulating layer is attached to the source conductor 15 and the drain conductor 17 exposed on the surface of the circuit body 40 molded by the resin 16, and a cooling water channel (not shown) is overlapped and contacted with this insulating layer, thereby dissipating heat of the SiC chip 18 of the circuit body 40. On the upper arm semiconductor element side, the source terminal 6b is connected to the second AC wiring 14 via the via 23. Also, on the lower arm semiconductor element side, the drain terminal 5a is connected to the second AC wiring 14 via the via 23 (see FIG. 2). By doing so, a circuit for bypassing a steep current can be formed using the second AC wiring 14.

[0023] As described above, the circuit body 40 includes conductors 15 and 17 connected to the upper arm semiconductor element in the case of a circuit body having an upper arm semiconductor element, and conductors 15 and 17 connected to the lower arm semiconductor element in the case of a circuit body having a lower arm semiconductor element, and the upper arm circuit body and the lower arm circuit body have the same structure. This allows for the common use of components, thereby reducing costs. Furthermore, having the same structure allows for easy adjustment of the number of circuit bodies 40 when they are arranged in parallel, as shown in Figure 4 below, to match the output capacitance.

[0024] (modified version) (Figure 4) Figure 4(a) is a diagram illustrating a semiconductor device 50 in which multiple circuit bodies 40 are connected in parallel, and Figure 4(b) is an overhead view of Figure 4(a). Multiple upper arm semiconductor elements and lower arm semiconductor elements may be connected in parallel, and even when each semiconductor element is connected in parallel in this way, a steep current passes through the second AC wiring 14, so noise in the signal wiring can be reduced. Furthermore, even when connected in parallel, the signal wirings 9 and 10 can be extended in the same direction to reduce noise, and the signal circuit can be consolidated and miniaturized.

[0025] Furthermore, the upper arm semiconductor devices 3a and 3c, each equipped with an upper arm semiconductor element, and the lower arm semiconductor devices 3b and 3d, each equipped with a lower arm semiconductor element, are arranged in a single row. Along this row, cooling water channels (not shown) through which cooling water flows are arranged on both sides of the semiconductor device 50. Figure 4(b) illustrates the cooling water path 30 of the cooling water channel located on the near side of the page.

[0026] Cooling water channels installed on both sides of the semiconductor device 50 contact the upper arm semiconductor devices 3a and 3c and the lower arm semiconductor devices 3b and 3d, respectively, thereby providing thermal cooling to the semiconductor devices 3a to 3d. By arranging the semiconductor devices 3a to 3d in a single line in this way, the width of the cooling area can be reduced, making it possible to increase the current capacity of the semiconductor devices 3a to 3d while simultaneously maintaining the cooling performance of the semiconductor device 50 and achieving miniaturization of the semiconductor device 50.

[0027] Furthermore, the cooling water flow in the cooling water channel may be in opposite directions to the cooling water flow in the opposite direction, thereby achieving well-balanced cooling of the semiconductor device 50.

[0028] (Figure 5) In a three-phase inverter 60 formed by combining three semiconductor devices 50, each having upper and lower arm semiconductor elements, the wiring of the first layer of the substrate will be described. Each single-phase inverter 25 is equipped with a capacitor 13 for absorbing steep currents, a smoothing capacitor 24 for absorbing current ripple associated with carriers, and an upper arm semiconductor device 3a and a lower arm semiconductor device 3b. Three of these single-phase inverters 25 are arranged in a row to form a three-phase inverter 60.

[0029] The AC output wiring 4 of the three-phase inverter 60 is connected to the AC output wiring 4 on the second layer (see Figure 6 below) via via 23, and the three divided negative electrode wirings 2 are also connected to the negative electrode wirings 2 on the second layer via via 23. The positive electrode wiring 1 is connected to terminal 24a, one of the two terminals of the smoothing capacitor 24.

[0030] (Figure 6) Figure 5 shows the second layer of the three-phase inverter 60. The upper arm semiconductor device 3a, the lower arm semiconductor device 3b, and the smoothing capacitor 24 are in the same positions as in the first layer. The negative terminal wiring 2, AC output wiring 4, and second AC wiring 14 of the second layer are connected to the first layer (Figure 5) via vias 23. The three-phase AC output wiring 4 enables the output of three-phase AC. The smoothing capacitor 24 is connected to the first layer via terminal 24b, one of the two terminals 24a and 24b of the smoothing capacitor 24 that is not connected to the positive terminal wiring 1.

[0031] In this way, by having a second AC wiring 14 for each of the three-phase inverters 60, magnetic noise to the signal wiring caused by the steep current generated when each SiC chip switches can be suppressed. Furthermore, as mentioned above, by extending the signal wirings 9 and 10 in one direction, the signal circuits can be mounted together, enabling miniaturization of the signal circuits and the entire three-phase inverter 60. In addition, as mentioned above, by forming a cooling water channel (not shown) in the direction in which the semiconductor devices 50 are lined up, and flowing cooling water from the top to the bottom of the paper in Figures 5 and 6, and similarly forming a cooling water channel on the back of the semiconductor devices 50 and flowing cooling water from the bottom to the top of the paper, the semiconductor devices 50 can be efficiently cooled in a narrow area.

[0032] According to the embodiment of the present invention described above, the following effects are achieved.

[0033] (1) The power converter 60 comprises an upper arm semiconductor element connected to a positive electrode wiring 1, a lower arm semiconductor element connected to a negative electrode wiring 2, a first AC wiring 4 connecting the upper arm semiconductor element and the lower arm semiconductor element, and a second AC wiring 14 connecting the upper arm semiconductor element and the lower arm semiconductor element. The first AC wiring 4 is formed in a position opposite to the positive electrode wiring 1 and the negative electrode wiring 2, with the upper arm semiconductor element and the lower arm semiconductor element in between. The second AC wiring 14 is formed in a position opposite to the first AC wiring 4, with the upper arm semiconductor element and the lower arm semiconductor element in between, and is stacked with the positive electrode wiring 1 and the negative electrode wiring 2. In this way, a power converter 60 that achieves both low inductance and low noise can be provided.

[0034] (2) The signal wirings 9 and 10 connected to the upper arm semiconductor element or the lower arm semiconductor element are arranged on the side where the first AC wiring 4 is formed with respect to the upper arm semiconductor element and the lower arm semiconductor element, and multiple semiconductor elements are connected in parallel in the upper arm semiconductor element and the lower arm semiconductor element, respectively. This makes it possible to achieve low noise.

[0035] (3) The upper arm semiconductor element and the lower arm semiconductor element are arranged in a single line. This arrangement allows for miniaturization when cooling both sides with a cooling water channel.

[0036] (4) The device comprises an upper arm circuit body including an upper arm semiconductor element and conductors 15 and 17 connected to the upper arm semiconductor element, and a lower arm circuit body including a lower arm semiconductor element and a conductor connected to the lower arm semiconductor element, wherein the upper arm circuit body and the lower arm circuit body have the same structure. This makes it possible to reduce costs.

[0037] It should be noted that the present invention is not limited to the embodiments described above, and various modifications and combinations of other configurations can be made without departing from the spirit of the invention. Furthermore, the present invention is not limited to having all the configurations described in the embodiments described above, and may also include configurations in which some of those configurations are omitted. [Explanation of symbols]

[0038] 1. Positive terminal wiring 2 Negative Wiring 3a, 3c Upper arm semiconductor device 3b, 3d lower arm semiconductor device 4. AC output wiring 5a, 5b Drain terminals 6a, 6b Source terminals 7 Gate signal terminal 8. Source signal terminals 9 Gate signal wiring 10 Source signal wiring 13 Capacitors 14 2nd AC wiring 14a Layering range 15 Source conductor 16 resin 17 Drain conductor 18 SiC chips 19 solder 21 wires 23 Beer 24 smoothing capacitors 24a 1st terminal 24b 2nd terminal 25 Inverter (1 phase) 30 Cooling water pathways 40 Circuit body 50 Semiconductor Equipment 60 3-phase inverter 100 First current path 200 Second current path

Claims

1. An upper arm semiconductor element connected to the positive electrode wiring, A lower arm semiconductor element connected to the negative electrode wiring, A first AC wiring that connects the upper arm semiconductor element and the lower arm semiconductor element, The system includes a second AC wiring that connects the upper arm semiconductor element and the lower arm semiconductor element, The first AC wiring is formed with the upper arm semiconductor element and the lower arm semiconductor element in between, and is positioned opposite the positive electrode wiring and the negative electrode wiring. The second AC wiring is formed opposite the first AC wiring, with the upper arm semiconductor element and the lower arm semiconductor element sandwiched between them, and is stacked with the positive electrode wiring and the negative electrode wiring. Power converter.

2. A power conversion device according to claim 1, The signal wiring connected to the upper arm semiconductor element or the lower arm semiconductor element is arranged on the side where the first AC wiring is formed relative to the upper arm semiconductor element and the lower arm semiconductor element. Multiple upper arm semiconductor elements and lower arm semiconductor elements are connected in parallel. Power converter.

3. A power conversion device according to claim 1, The upper arm semiconductor element and the lower arm semiconductor element are arranged in a line. Power converter.

4. A power conversion device according to claim 1, An upper arm circuit body including the upper arm semiconductor element and a conductor connected to the upper arm semiconductor element, The lower arm circuit body includes the lower arm semiconductor element and a conductor connected to the lower arm semiconductor element, The upper arm circuit body and the lower arm circuit body have the same structure. Power converter.

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