Memory system, its operating method, and memory device

Abstract

To provide a memory device which performs recovery operation to improve a reliability deterioration problem in the memory device where program and erasure operation are repeated.SOLUTION: A method for operating a memory system includes the steps in which: a memory controller detects a first memory block having a deterioration count equal to or more than a first reference value in a plurality of memory blocks; the memory controller transfers a first command for the first memory block to a memory device; and the memory device performs recovery operation of applying a first voltage to each of a plurality of word lines connected to the first memory block and applying a second voltage to a bit line of the first memory block in response to the first command. The first voltage is higher than a voltage applied to turn on the memory cell connected to each of the plurality of word lines connected to the first memory block and the second voltage is higher than a voltage applied to the bit line upon program operation, readout operation, or erasure operation for the memory device.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a memory system, and more particularly to a memory system performing a recovery operation, a method of operating the same, and a memory device.

Background Art

[0002] A nonvolatile memory device as a semiconductor memory device includes a plurality of memory cells that store data without volatility. As an example of a nonvolatile memory device, a flash memory system is widely used in USB (universal serial bus) drives, digital cameras, mobile phones, smartphones, tablet PCs, memory cards, and SSDs (solid state drives).

[0003] In the case of a memory system including a nonvolatile memory device, it is possible to increase the capacity, and it is important to improve the reliability of the programmed data. In a nonvolatile memory device, improving the problem of reliability degradation when the program / erase operation is repeated has become a technical issue.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention has been made in view of the above problems in the conventional nonvolatile memory device, and an object of the present invention is to provide a memory device that performs a recovery operation in order to improve the problem of reliability degradation of a memory device in which a program / erase operation is repeated. Specifically, the objective is to provide a memory system, a method of operation thereof, and a memory device that self-cures elements using Joule heat generated by the electric current flowing through the elements. [Means for solving the problem]

[0006] To achieve the above objective, the present invention provides a method for operating a memory system comprising a memory device having a plurality of memory blocks and a memory controller, wherein the method for operating a memory system comprises: the step of the memory controller detecting a first memory block among the plurality of memory blocks having a degradation count equal to or greater than a first reference value; the step of the memory controller transmitting a first command to the first memory block to the memory device; and the step of the memory device performing a recovery operation in which, in response to the first command, it applies a first voltage to any of the plurality of word lines connected to the first memory block and applies a second voltage to the bit line of the first memory block, wherein the first voltage is higher than the voltage applied to turn on memory cells connected to any of the plurality of word lines connected to the first memory block, and the second voltage is higher than the voltage applied to the bit line during a program operation, read operation, or erase operation of the memory device.

[0007] To achieve the above objective, the present invention provides a memory device comprising: a memory cell array including a plurality of memory blocks each having a plurality of memory cells; a plurality of word lines connected to the plurality of memory blocks; and a plurality of bit lines connected to the plurality of memory blocks; and a control circuit that controls the first memory block among the plurality of memory blocks to perform a control operation, wherein, during the control operation, the control circuit copies the data of the first memory block among the plurality of memory blocks to a second memory block among the plurality of memory blocks, erases the data of the first memory block, applies a first voltage to a selected portion of the word lines connected to the first memory block, applies a second voltage to the bit lines of the first memory block, and controls the first voltage to be higher than the voltage applied to turn on the memory cells connected to the selected portion of the word lines connected to the first memory block, and controls the second voltage to be higher than the voltage applied to the bit lines during a program operation, read operation, or erase operation of the memory device.

[0008] To achieve the above objective, the present invention provides a memory device comprising a plurality of memory blocks and a memory controller that transmits commands to control the memory device, wherein the memory device, in response to the command, copies the data of a first memory block among the plurality of memory blocks to a second memory block among the plurality of memory blocks, erases the data of the first memory block, applies a first voltage to any of the plurality of word lines connected to the first memory block, and applies a second voltage to the bit line of the first memory block, wherein the first voltage is higher than the voltage applied to turn on a memory cell connected to any of the plurality of word lines connected to the first memory block, and the second voltage is higher than the voltage applied to the bit line during a precharge operation of the memory device. [Effects of the Invention]

[0009] According to the memory system, operating method thereof, and memory device of the present invention, when the memory device receives a recovery command from the memory controller, a recovery voltage is applied to the word line and bit line of the memory block to be recovered. This causes current to flow through each memory cell in the memory block to be recovered, generating Joule heat and thus producing the recovery effect. Therefore, it is possible to improve the degradation of memory device reliability that occurs as program / erase cycles accumulate in memory blocks. [Brief explanation of the drawing]

[0010] [Figure 1] This block diagram shows a schematic configuration of a memory system according to an exemplary embodiment of the present invention. [Figure 2] This block diagram shows a schematic configuration of a memory device according to an exemplary embodiment of the present invention. [Figure 3] Figure 2 is a perspective view showing an overview of the memory cell array. [Figure 4] This is a perspective view showing an example of the first memory block within the memory block shown in Figure 2. [Figure 5] This is a circuit diagram showing the equivalent circuit of the first memory block in the memory block shown in Figure 2. [Figure 6] This is a cross-sectional view showing the schematic configuration of a non-volatile memory cell according to one embodiment of the present invention. [Figure 7A] This is a cross-sectional view illustrating the recovery operation according to one embodiment of the present invention. [Figure 7B] This is a cross-sectional view illustrating the recovery operation according to one embodiment of the present invention. [Figure 7C] This is a cross-sectional view illustrating the recovery operation according to one embodiment of the present invention. [Figure 8]A flowchart showing each step for explaining an operation method of a memory system performing a recovery operation according to an exemplary embodiment of the present invention. [Figure 9] A flowchart for explaining the specific operation of step S130 in FIG. 8. [Figure 10] A flowchart showing each step for explaining an operation method of a memory system performing a recovery operation according to an exemplary embodiment of the present invention. [Figure 11] A flowchart for explaining an embodiment performed after step S120 in FIG. 8. [Figure 12A] A flowchart for specifically explaining steps S330 to S350 in FIG. 11. [Figure 12B] A flowchart for specifically explaining steps S330 to S350 in FIG. 11. [Figure 12C] A flowchart for specifically explaining steps S330 to S350 in FIG. 11. [Figure 12D] A flowchart for specifically explaining steps S330 to S350 in FIG. 11. [Figure 12E] A flowchart for specifically explaining steps S330 to S350 in FIG. 11. [Figure 13] A flowchart for explaining an embodiment performed after step S120 in FIG. 8. [Figure 14A] A flowchart for specifically explaining steps S430 to S460 in FIG. 13. [Figure 14B] A flowchart for specifically explaining steps S430 to S460 in FIG. 13. [Figure 14C] A flowchart for specifically explaining steps S430 to S460 in FIG. 13. [Figure 14D] ] A flowchart for specifically explaining steps S430 to S460 in FIG. 13. [Figure 14E]This is a flowchart to specifically explain steps S430 to S460 in Figure 13. [Figure 15] This block diagram shows a schematic configuration example in which a memory device according to an exemplary embodiment of the present invention is applied to an SSD system. [Figure 16] This figure illustrates a method for generating a memory cell array according to an exemplary embodiment of the present invention. [Figure 17] This is a cross-sectional view illustrating the schematic configuration of a BVNAND structure applied to one embodiment of the present invention. [Modes for carrying out the invention]

[0011] Next, specific examples of embodiments for implementing the memory system, its operating method, and memory device according to the present invention will be described with reference to the drawings.

[0012] Figure 1 is a block diagram showing a schematic configuration of a memory system according to an exemplary embodiment of the present invention. Referring to Figure 1, the memory system 1 comprises a memory controller 10 and a memory device 100. The memory controller 10 includes a block management module 11 and an ECC engine 12. The memory device 100 includes a memory cell array 110, a row decoder 140, and a recovery control circuit 132.

[0013] In some embodiments, the memory system 1 is embodied in internal memory built into an electronic device, and is, for example, an embedded UFS (Universal Flash Storage) memory device, an eMMC (embedded Multi-Media Card), or an SSD (Solid State Drive). In some embodiments, the memory system 1 is embodied in an external memory that is detachable from the electronic device, such as a UFS memory card, CF (Compact Flash), SD (Secure Digital), Micro-SD (Micro Secure Digital), Mini-SD (Mini Secure Digital), xD (extreme Digital), or Memory Stick (registered trademark).

[0014] The memory controller 10 responds to write / read requests from the host HOST by either reading data stored in the memory device 100 or controlling the memory device 100 to program data into it. As the program / erase cycle is repeated for each memory block in the memory device 100, the reliability of the memory block deteriorates, and the memory controller 10 controls the memory device 100 to restore the deteriorated reliability. Specifically, the memory controller 10 controls the programming, reading, erasing, and recovery operations of the memory device 100 by providing the memory device 100 with the address ADDR, the command CMD, and the control signal CTRL. Furthermore, the data used for programming and the data that has been read are transmitted and received between the memory controller 10 and the memory device 100.

[0015] In an exemplary embodiment, the reliability of a memory block degrades as the number of program / erase cycles of the memory block accumulates. To improve the reliability degradation of memory blocks, memory system 1 performs wear leveling management, bad block management, and recovery operations for self-curing. The memory controller 10 provides the memory device 100 with address ADDR, command CMD, control signal CTRL, and data DATA for wear leveling management, bad block management, and recovery operation. A detailed explanation of the recovery process will be provided later.

[0016] The block management module 11 includes a counter for counting the degradation count of each memory block in the memory cell array 110. The degradation count is the program / erase count for a memory block, the read count for a memory block, or the number of error bits in the data read from the memory block. The embodiments are not limited thereto, and the degradation count can be a variety of information indicating the degradation of a memory block. In an exemplary embodiment, the counter of the block management module 11 updates the degradation count each time an operation is performed to accumulate a degradation count for memory blocks in the memory device 100.

[0017] For example, the degradation count increases each time a program / erase operation is performed on a memory block. For example, the degradation count increases each time a read operation is performed on a memory block. For example, the degradation count increases when the number of error bits detected during read operations on a memory block increases. The degradation count may have a different value for each memory block.

[0018] The block management module 11 compares the first reference value with the degradation count. The memory controller 10 provides the memory device 100 with a recovery command and the address of a memory block so that a recovery operation is performed for memory blocks that have a degradation count of a first reference value or higher. The block management module 11 compares the second reference value with the degradation count. The memory controller 10 manages memory blocks with a degradation count of 2 or higher as bad blocks. The first reference value is smaller than the second reference value.

[0019] In some embodiments, if the degradation count is the number of error bits, the first reference value is the maximum number of error bits that can be corrected by the ECC engine 12. In some embodiments, the first reference value has a different value for each memory block. In some embodiments, the memory system 1 includes additional memory devices in addition to the memory device 100, and the first reference value has a different value for each memory device. In an exemplary embodiment, the memory controller 10 compares a first or second reference value stored in the block management module 11 with a degradation count to determine the extent of bad blocks in the memory blocks within the memory device 100 and whether a recovery operation is necessary to restore the degraded reliability of the memory blocks.

[0020] The ECC engine 12 is configured to detect and correct errors in the data read from the memory device 100 using an Error Correction Code. The ECC engine 12 includes any circuit, system, or device for error correction. When the ECC engine 12 performs error correction, if the number of errors exceeds the error bit correction limit, the error bit correction fails. In an exemplary embodiment, the memory controller 10 performs a recovery operation based on the success or failure of the data correction performed by the ECC engine 12.

[0021] The recovery control circuit 132 controls the memory device 100 to perform a recovery operation in response to a recovery command transmitted from the memory controller 10. In an exemplary embodiment, the recovery control circuit 132 controls the memory device 100 so that voltage is applied to the word line and bit line of the memory block to be recovered. For example, the voltage applied to the word line is the same as, or greater than, the turn-on voltage or pass voltage used to turn on the memory cell. The voltage applied to the bit line may be higher than the voltage applied during pre-charge operation. In an exemplary embodiment, when the recovery control circuit 132 applies voltage to a word line, it controls the memory device 100 so that the voltage is applied to a selected portion of the word lines among a plurality of word lines connected to the memory block to be recovered. In an exemplary embodiment, the recovery control circuit 132 controls the memory device 100 so that when a voltage is applied to a word line, the voltage is applied to any of the multiple word lines connected to the memory block to be recovered.

[0022] Figure 2 is a block diagram showing a schematic configuration of a memory device according to an exemplary embodiment of the present invention. For example, Figure 2 shows an embodiment of the memory device 100 shown in Figure 1. Referring to Figure 2, the memory device 100 comprises a memory cell array 110, a voltage generator 120, control logic 130, a row decoder 140, and a page buffer 150. Although not shown in Figure 2, the memory device 100 may further include a variety of other components related to memory operation, such as data input / output circuits or input / output interfaces.

[0023] The memory cell array 110 comprises multiple memory cells and is connected to a word line WL, a string selection line SSL, a ground selection line GSL, and a bit line BL. The memory cell array 110 may be connected to the row decoder 140 via the word line WL, the string selection line SSL, and the ground selection line GSL, and to the page buffer 150 via the bit line BL. For example, the multiple memory cells included in the memory cell array 110 are non-volatile memory cells that maintain the stored data even when the supplied power is cut off.

[0024] Specifically, when the memory cell is a non-volatile memory cell, the memory device 100 may be an EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory, PRAM (Phase Change Random Access Memory), RRAM (Resistance Random Access Memory), NFGM (Nano Floating Gate Memory), PoRAM (Polymer Random Access Memory), MRAM (Magnetic Random Access Memory), or FRAM (Registered Trademark) (Ferroelectric Random Access Memory). In the following, embodiments of the present invention are described using the case where multiple memory cells are NAND flash memory cells, but it should be understood that the technical concept of the present invention is not limited thereto.

[0025] The memory cell array 110 includes multiple memory blocks (BLK1 to BLKz), and each memory block has either a planar or three-dimensional structure. The memory cell array 110 includes at least one of the following: a single-level cell block containing a single-level cell SLC, a multi-level cell block containing a multi-level cell MLC, a triple-level cell block containing a triple-level cell TLC, and a quad-level cell block containing a quad-level cell. For example, some of the memory blocks (BLK1 to BLKz) are single-level cell blocks, while the others are multi-level cell blocks, triple-level cell blocks, or quad-level cell blocks.

[0026] The voltage generator 120 generates various voltages used within the memory device 100, such as a program voltage provided to the selected word line for program operation, a path voltage provided to the unselected word line, a string selection voltage provided to the string selection line SSL, and a ground selection voltage provided to the ground selection line GSL (not shown). In an exemplary embodiment, the voltage generator 120 generates a first voltage V1 that is provided to the word line of the memory block to be recovered during the recovery operation of the memory device 100. For example, the first voltage V1 is applied simultaneously to any of the multiple word lines connected to the memory block. For example, the first voltage V1 is applied to only a selected portion of the multiple word lines connected to the memory block. In an exemplary embodiment, the voltage generator 120 generates a second voltage V2 provided to the bit line. The second voltage V2 is transmitted to the page buffer 150.

[0027] Based on the command CMD, address ADDR, and control signal CTRL received from the memory controller 10, the control logic 130 outputs various internal control signals to program data into the memory cell array 110 or to read data from the memory cell array 110. For example, the control logic 130 outputs a voltage control signal (CTRL_vol) to control the levels of various voltages generated by the voltage generator 120. In an exemplary embodiment, the control logic 130 outputs a control signal for controlling the voltage level used during a recovery operation to restore a memory block that has become unreliable. The control logic 130 provides the row address (X-ADDR) to the row decoder 140 and the column address (Y-ADDR) to the page buffer 150.

[0028] The row decoder 140 selects at least one word line from the selected memory block in response to the row address (X-ADDR). In an exemplary embodiment, the row decoder 140 provides a first voltage V1 to the word line of the memory block to be recovered in response to the row address (X-ADDR) during recovery operation.

[0029] The page buffer 150 operates in response to the control logic 130. For example, page buffer 150 can function as a write driver or a sense amplifier. In an exemplary embodiment, during program operation, the page buffer 150 acts as a write driver and applies a voltage to the bit line BL corresponding to the data DATA to be stored in the memory cell array 110. In an exemplary embodiment, during a read operation, the page buffer 150 acts as a sensing amplifier to sense the data DATA stored in the memory cell array 110. In an exemplary embodiment, during recovery operation, the page buffer 150 provides a second voltage V2 to the bit line BL in response to the column address (Y-ADDR).

[0030] The control logic 130 includes a recovery control circuit 132. However, the embodiments of the present invention are not limited thereto, and the recovery control circuit 132 may be provided outside the control logic 130. In an exemplary embodiment, the recovery control circuit 132 controls the voltage generator 120, the row decoder 140, and the page buffer 150 so that recovery operations are performed for memory blocks that have become unreliable among the multiple memory blocks included in the memory cell array 110. For example, the memory blocks on which recovery operations are performed are those with a degradation count equal to or greater than the first reference value. The first reference value differs for each memory block. The first reference value differs for each memory device.

[0031] The recovery control circuit 132 restores the data retention characteristics of a degraded memory block by performing a recovery operation on the memory block. In an exemplary embodiment, the recovery control circuit 132 controls the voltage generator 120, the row decoder 140, and the page buffer 150 to apply a first voltage V1 to the word line of the memory block and a second voltage V2 to the bit line of the memory block in order to perform a recovery operation on the memory block. The first voltage V1 and the second voltage V2 are different. For example, the first voltage V1 applied to the word line is the turn-on voltage or pass voltage for turning on the memory cell. The second voltage V2 applied to the bit line may be a higher voltage than the voltage applied during program operation, erase operation, read operation, and precharge operation. For example, the first voltage V1 applied to the word line is a higher voltage than the voltage applied during program operation. The second voltage V2 applied to the bit line may be a higher voltage than the voltage applied during program operation, erase operation, read operation, and precharge operation.

[0032] In an exemplary embodiment, the recovery control circuit 132 controls the memory device 100 so that when a voltage is applied to a word line, the voltage is applied to a selected portion of the word lines among a plurality of word lines connected to the memory block to be recovered. In an exemplary embodiment, the recovery control circuit 132 controls the memory device 100 so that when a voltage is applied to a word line, the voltage is applied to any of the multiple word lines connected to the memory block to be recovered.

[0033] Figure 3 is a perspective view showing an overview of the memory cell array in Figure 2. Referring to Figure 3, the memory cell array 110 includes multiple memory blocks (BLK1 to BLKz). Each memory block (BLK) has a three-dimensional (or vertical) structure. For example, each memory block BLK includes structures that extend along the first to third directions. For example, each memory block BLK comprises multiple NAND strings NS extended along a second direction. For example, multiple NAND strings NS are provided along the first and third directions.

[0034] Each NAND string NS is connected to the bit line BL, string selection line SSL, ground selection line GSL, word line WL, and common source line CSL. In other words, each memory block is connected to multiple bit lines BL, multiple string selection lines SSL, multiple ground selection lines GSL, multiple word lines WL, and a common source line CSL. The memory blocks (BLK1 to BLKz) will be explained in more detail with reference to Figure 4.

[0035] Figure 4 is a perspective view showing an example of the first memory block within the memory block shown in Figure 2. Referring to Figure 4, each memory block included in the memory cell array (for example, reference numeral 110 in Figure 2) is formed perpendicular to the substrate SUB. Figure 4 shows a memory block with two selection lines GSL and SSL, eight word lines (WL1 to WL8), and three bit lines (BL1 to BL3), but in reality, there may be more or fewer of these.

[0036] A common source line CSL is provided, having a first conductivity type (e.g., p-type), extending along a first direction on the substrate SUB, and doped with an impurity of a second conductivity type (e.g., n-type). The substrate SUB may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate for an epitaxial thin film obtained by selective epitaxial growth (SEG). The substrate SUB is made of a semiconductor material and includes at least one of the following: silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof.

[0037] A first memory stack ST1 is provided on the circuit board SUB. In detail, multiple insulating films IL extending along a first direction are provided sequentially along a third direction on a region of the substrate SUB between two adjacent common source lines CSL, with the multiple insulating films IL being separated by a certain distance along the third direction. For example, multiple insulating films (ILs) contain insulating materials such as silicon oxide. Multiple pillars P are provided by etching, sequentially arranged along a first direction and penetrating multiple insulating films IL along a third direction, on a region of the substrate SUB between two adjacent common source lines CSL.

[0038] For example, multiple pillars P penetrate multiple insulating films IL and make contact with the substrate SUB. Specifically, the surface layer S of each pillar P contains a silicon material having a first conductivity type and functions as a channel region. On the other hand, the inner layer I of each pillar P contains an insulating material such as silicon oxide or an air gap.

[0039] In the region between two adjacent common source lines CSL, a charge storage layer CS is provided along the exposed surface of the insulating film IL, pillar P, and substrate SUB. The charge conservation layer CS comprises a gate insulating layer (or "tunneling insulating layer"), a charge trapping layer, and a blocking insulating layer. For example, the charge-conserving layer CS has an ONO (oxide-nitride-oxide) structure. Furthermore, in the region between two adjacent common source lines CSL, gate electrodes GE such as selected lines GSL and SSL and word lines (WL1-WL4) are provided on the exposed surface of the charge conservation layer CS.

[0040] The memory block BLK1 according to the present invention is further provided with a second memory stack ST2 generated by the same method, on top of a first memory stack ST1 generated by the method described above. On each of the multiple pillars P that extend to the second memory stack ST2, drains or drain contacts DR are provided. For example, the drain or drain contact DR contains a silicon material doped with an impurity having a second conductivity type. Above the drain DR, bit lines (BL1 to BL3) are provided, extending in a second direction and spaced a specific distance apart along the first direction.

[0041] Figure 5 is a circuit diagram showing the equivalent circuit of the first memory block in the memory block shown in Figure 2. Referring to Figure 5, the first memory block BLK1 is a vertically structured NAND flash memory, and each memory block (BLK1 to BLKz) shown in Figure 2 is realized as shown in Figure 5. The first memory block BLK1 comprises multiple NAND cell strings (NS11~NS33), multiple word lines (WL1~WL8), multiple bit lines (BL1~BL3), multiple ground selection lines (GSL1~GSL3), multiple string selection lines (SSL1~SSL3), and a common source line CSL. Here, the number of NAND cell strings, word lines, bit lines, ground selection lines, and string selection lines vary considerably depending on the embodiment.

[0042] NAND cell strings (NS11, NS21, NS31) are provided between the first bit line BL1 and the common source line CSL, NAND cell strings (NS12, NS22, NS32) are provided between the second bit line BL2 and the common source line CSL, and NAND cell strings (NS13, NS23, NS33) are provided between the third bit line BL3 and the common source line CSL. Each NAND cell string (e.g., NS11) comprises a string selection transistor SST, multiple memory cells (MC1 to MC8), and a ground selection transistor GST, all connected in series.

[0043] A string of NAND cells connected to a single bitline constitutes a single column. For example, the NAND cell strings (NS11, NS21, NS31) commonly connected to the first bit line BL1 correspond to the first column, the NAND cell strings (NS12, NS22, NS32) commonly connected to the second bit line BL2 correspond to the second column, and the NAND cell strings (NS13, NS23, NS33) commonly connected to the third bit line BL3 correspond to the third column. A NAND cell string connected to a single string selection line constitutes a single row. For example, the NAND cell strings (NS11, NS12, NS13) connected to the first string selection line SSL1 correspond to the first row, the NAND cell strings (NS21, NS22, NS23) connected to the second string selection line SSL2 correspond to the second row, and the NAND cell strings (NS31, NS32, NS33) connected to the third string selection line SSL3 correspond to the third row.

[0044] The string selection transistor SST is connected to the corresponding string selection line (SSL1~SSL3). Multiple memory cells (MC1 to MC8) are connected to their respective word lines (WL1 to WL8). The ground selection transistor GST is connected to the corresponding ground selection line (GSL1~GSL3), and the string selection transistor SST is connected to the corresponding bit line (BL1~BL3). The ground selection transistor GST is connected to the common source line CSL.

[0045] In this embodiment, word lines of the same height (e.g., WL1) are connected in common, string selection lines (SSL1~SSL3) are separated from each other, and ground selection lines (GSL1~GSL3) are also separated from each other. For example, when programming memory cells included in the NAND cell string (NS11, NS12, NS13) connected to the first word line WL1 and corresponding to the first column, the first word line WL1 and the first string selection line SSL1 are selected. However, the present invention is not limited thereto, and in other embodiments, the ground selection lines (GSL1 to GSL3) are connected in common.

[0046] Figure 6 is a cross-sectional view showing a schematic configuration of a non-volatile memory cell according to one embodiment of the present invention. Referring to Figure 6, the non-volatile memory cell 600 comprises a control gate 610, a blocking layer 620, a first semiconductor layer 630, a tunneling layer 640, a source 650, a drain 660, a second semiconductor layer 670, a BOX layer (buried oxide layer) 680, and a substrate 690.

[0047] If the non-volatile memory cell 600 is repeatedly programmed and erased, unwanted trap sites will be formed in the tunneling layer 640. This could cause the charge trapped in the first semiconductor layer 630 to escape through the tunneling layer 640, potentially leading to data loss. This phenomenon is called vertical charge migration, which is charge transfer perpendicular to the channel layer. In a three-dimensional non-volatile memory, multiple cells constituting a single string share the first semiconductor layer 630, which causes charge transfer in the direction of adjacent cells, i.e., lateral charge transfer (lateral charge migration). One problem is that the data retention characteristics of semiconductor devices deteriorate due to the movement of electric charge, leading to a decrease in the reliability of memory elements. In particular, this phenomenon becomes even more pronounced as the manufacturing process becomes more refined, such as when implementing multi-bit technology in a single cell to increase the integration density of elements. Therefore, there is a growing need to improve the current state of reliability degradation of these non-volatile memory elements themselves.

[0048] The non-volatile memory element according to an embodiment of the present invention has a substrate with an SOI (silicon on insulator) structure. Specifically, a bias voltage is applied to the substrate 690 to prevent data (e.g., charge carriers) stored in the second semiconductor layer 670 from leaking out. The BOX layer 680 is formed on top of the substrate 690 and prevents data stored in the second semiconductor layer 670 from leaking. The BOX layer 680 is made of materials with low thermal conductivity, such as SiO2, Al2O3, and HfO2. The second semiconductor layer 670 is also silicon, and in this case, the second semiconductor layer 670 and the BOX layer 680 are SOI.

[0049] The tunneling layer 640 is made of, for example, a silicon oxide film. The first semiconductor layer 630 consists of a silicon nitride film or a high-dielectric film having an even higher dielectric constant. For example, the first semiconductor layer 630 consists of a Si3N4 film, a metal oxide film, a metal nitride film, or a combination thereof. Here, the first semiconductor layer 630 includes trap sites that store charges passing through the tunneling layer 640. The first semiconductor layer 630 can be described as a charge trapping layer.

[0050] The blocking layer 620 prevents electrons from escaping to the control gate 610 during the process of being trapped at the trap site in the first semiconductor layer 630, and also prevents the charge of the control gate 610 from being injected into the first semiconductor layer 630. When the first semiconductor layer 630 is a nitride, the tunneling insulating layer, the first data storage layer, and the blocking insulating layer have an ONO (Oxide-Nitride-Oxide) structure. The control gate 610 is made of at least one material selected from the group consisting of TaN, TiN, W, WN, HfN, and tungsten silicide. The control gate 610 is connected to the word line and a program voltage is applied to it, and the drain 660 is connected to the bit line.

[0051] Figures 7A to 7C are cross-sectional views illustrating the recovery operation according to one embodiment of the present invention. Figure 7A is a cross-sectional view showing a non-volatile memory cell according to one embodiment of the present invention forming a string structure. Figure 7A shows an example of a self-healing operation, i.e., a recovery operation, of a memory element according to one embodiment of the present invention. The memory cell string in Figure 7A represents a portion of a memory block whose reliability has degraded as the degradation count has accumulated.

[0052] Referring to Figure 7A, the memory cell string 700 comprises control gates (711, 712, 713), a blocking layer 720, a first semiconductor layer 730, a tunneling layer 740, a second semiconductor layer 750, and a box layer 760. For example, the first semiconductor layer 730 is a charge trapping layer, and the second semiconductor layer 750 is channel poly or channel polysilicon. Figure 7A will be explained below with reference to Figures 1 and 2.

[0053] In an exemplary embodiment, word line voltages are applied via word lines (WL1, WL2, WLn) connected to control gates (711, 712, 713). A bit line voltage is applied via bit line BL, which is connected to the second semiconductor layer. Figure 7A shows only three word lines (WL1 to WLn), but in reality, there may be more or fewer than this.

[0054] In an exemplary embodiment, the memory device 100 receives a first command from the memory controller 10 and performs a recovery operation. For example, the first command is a recovery command. During recovery, a first voltage V1 is applied to the word lines (WL1 to WLn), and a second voltage V2 is applied to the bit lines. The first voltage V1 and the second voltage V2 cause a recovery current 770 to flow along the channels of the memory cell string. The recovery current of 770 generates Joule heat within the element, and this Joule heat is used to recover from reliability degradation in the memory element. This will be explained later through Figures 7B and 7C.

[0055] In an exemplary embodiment, the first voltage V1 applied to the word line is the same as or higher than the turn-on voltage or pass voltage used to turn on the memory cell, and the same as or higher than the voltage applied during program operation. The second voltage V2 applied to the bit line may be a higher voltage than the voltage applied during program operation, erase operation, read operation, and precharge operation. The first voltage V1 and the second voltage V2 are different. As an example, the memory device 100 performs a recovery operation by applying a first voltage V1 higher than the turn-on voltage to the word line and a second voltage V2 higher than the voltage applied during program operation, read operation, or erase operation to the bit line. As an example, the memory device 100 performs a recovery operation by applying a first voltage V1 higher than the turn-on voltage to the word line and a second voltage V2 higher than the precharge voltage to the bit line.

[0056] Figure 7B shows a portion of the memory string cross-section disclosed in Figure 7A. Figure 7B shows, for example, part A of Figure 7A. In the following explanation of Figure 7B, any overlap with the explanation of Figure 7A will be omitted, and Figure 7B will be explained with reference to Figures 1, 2, and 7A.

[0057] Referring to Figure 7B, as the memory block undergoes repeated program / erase operations, electrons 781 and holes 782 are trapped in the tunneling layer 740. In an exemplary embodiment, a recovery current 770 flows along the second semiconductor layer 750 due to a voltage V1 applied to the word line and a voltage V2 applied to the bit line. The recovery current 770 generates Joule heat, which anneals the trapped electrons 781 and trapped holes 782. The problem of the data retention characteristics of the memory device 100 degrading as the trapped electrons 781 and trapped holes 782 escape the tunneling layer 740 is mitigated.

[0058] Figure 7C shows a portion of the memory string cross-section disclosed in Figure 7A. Figure 7C shows, for example, part A of Figure 7A. In the following explanation of Figure 7C, any overlap with the explanation of Figure 7A will be omitted, and Figure 7C will be explained with reference to Figures 1, 2, and 7A.

[0059] Referring to Figure 7C, it can be seen that as the memory block is repeatedly programmed / erased, unwanted trap sites 783 are formed in the tunneling layer 740. In an exemplary embodiment, a voltage V1 applied to the word line WLn and a voltage V2 applied to the bit line BL cause a recovery current 770 to flow along the second semiconductor layer 750, the recovery current 770 generates Joule heat, and the Joule heat removes the trap site 783. As the trap site 783 is removed, the charge trapped in the first semiconductor layer 730 escapes through the tunneling layer 740, which improves the problem of degraded data retention characteristics of the memory device 100.

[0060] Figure 8 is a step-by-step flowchart illustrating the operation method of a memory system performing a recovery operation according to an exemplary embodiment of the present invention. Figure 8 will be discussed later with reference to Figure 1. In an exemplary embodiment, steps (S100 to S130) are performed when the memory device 100 is in an idle state (idle time). The idle state means that data is either being read from or not programmed onto the memory device 100.

[0061] Referring to Figure 8, in step S100, the memory controller 10 acquires the degradation count for each of the multiple memory blocks of the memory device 100. In an exemplary embodiment, the degradation count is a program / erase count for a memory block, a read count for a memory block, or an error bit count. In this case, the program / erase count represents the number of times a program / erase operation has been performed on the memory block in question. The read count indicates the number of times a read operation has been performed on a memory block. The error bit count is the number of error bits in the data read from the memory block. The embodiments are not limited thereto, and the degradation count can be a variety of information indicating the degradation of a memory block.

[0062] In step S110, the memory controller 10 compares the degradation count with a first reference value to determine the degree of degradation of the memory blocks of the memory device 100. Information regarding the first reference value, which serves as the criterion for determining the degree of deterioration, is stored in the block management module 11. If the degradation count is lower than the first baseline value, no recovery operation will be performed. If the degradation count is equal to or greater than the first reference value, step S120 is performed. However, the present invention is not necessarily limited to this. For example, in one embodiment, step S120 is performed only when it is determined that the number of degradation cycles is greater than the first reference value. If the number of degradation cycles is determined to be the same as the first standard value, step S120 is not performed.

[0063] In step S120, the memory controller 10 transmits a first command to the memory device 100, along with the address of the first memory block, so that the memory device 100 can perform a recovery operation for the memory block. In an exemplary embodiment, the first command is a recovery command. In step S130, the memory device 100 performs a recovery operation in response to a first command received from the memory controller 10. An example of the S130 step for recovering a memory block will be specifically described later in Figure 9.

[0064] Although not shown in the diagram, in some embodiments, the memory controller 10 initializes the memory block degradation count after performing a recovery operation. The memory controller 10 includes count information regarding the number of initializations of a memory block and information regarding the initialization criterion number. As the degradation count of the first memory block is initialized, the memory controller 10 updates the initialization count information. In an exemplary embodiment, when the number of initializations reaches a baseline number, the first memory block is set as a bad block.

[0065] Figure 9 is a flowchart illustrating the specific operation of step S130 in Figure 8. In step S131, the memory device 100 receives a first command from the memory controller 10. In step S132, the memory device 100 applies a first voltage V1 to the word line and a second voltage V2 to the bit line of the first memory block in order to perform a recovery operation for the first memory block. In step S133, the first voltage V1 and the second voltage V2 cause a recovery current 770 to flow along the channels of the memory cell string. In step S134, Joule heat is generated within the element by the recovery current 770, and this Joule heat is used to recover the memory element from reliability degradation. Thus, the degraded reliability of the memory block is restored.

[0066] Figure 10 is a step-by-step flowchart illustrating the operation method of a memory system performing a recovery operation according to an exemplary embodiment of the present invention. In the following explanation of Figure 10, any content that overlaps with Figures 8 and 9 will be omitted, and Figure 10 will be explained with reference to Figures 1, 8, and 9.

[0067] Referring to Figure 10, in step S200, the memory controller 10 checks the program / erase cycle for each of the multiple memory blocks of the memory device 100. In step S210, the memory controller 10 compares the program / erase cycle to a first reference value to determine the degree of degradation of the memory blocks of the memory device 100 and detects any degraded memory blocks. If the program / erase cycle is less than the first reference value, no recovery operation is performed. If the program / erase cycle is equal to or greater than the first reference value, step S220 is performed.

[0068] In step S220, the memory controller 10 transmits a second command to the memory device 100 to count the error bits of memory blocks that have program / erase cycles greater than or equal to a first reference value. In step S230, in response to the second command, the memory device 100 transmits the data stored in the first memory block to the memory controller 10. The ECC engine 12 in the memory controller 10 uses error correction codes to count the error bits of the data read from the memory device 100, detect errors, and correct them. If the number of errors is greater than or equal to the number of error bits that can be corrected, error bit correction fails and step S240 is performed.

[0069] If the number of errors is less than the number of error bits that can be corrected, error correction is successful and no recovery operation is performed. In some embodiments, in step S230, the memory device 100 counts the error bits of the memory block and transmits the number of error bits to the memory controller 10. The memory controller 10 compares the number of error bits with the reference number. In step S240, the memory controller 10 transmits a first command to the memory device 100. In an exemplary embodiment, the first command is a recovery command. In step S250, the memory device 100 performs a recovery operation in response to a first command received from the memory controller 10.

[0070] Figure 11 is a flowchart illustrating one embodiment that takes place after step S120 in Figure 8, and Figures 12A to 12E are flowcharts that specifically illustrate the steps (S330 to S350) in Figure 11. In the following explanation of Figures 11 and 12A-12E, any content that overlaps with Figures 8 and 9 will be omitted. Figure 11 will be explained with reference to Figures 1, 2, and 12A to 12E.

[0071] Referring to Figure 11, the first memory block in step S330 is a block with degraded reliability. For example, referring to Figure 12A, the degradation count of the first memory block BLK1 is above the standard value. Therefore, the memory controller 10 designates the first memory block BLK1 as the memory block that requires recovery operation. Before the recovery operation is performed, data A may be stored in the first memory block BLK1.

[0072] In step S330, the memory device 100 copies the data from the first memory block to the second memory block. For example, referring to Figure 12B, the memory device 100 copies data A from the first memory block BLK1 to the second memory block BLK2. In this case, the second memory block BLK2 represents a normal block whose reliability has not deteriorated. Although not shown in the diagram, the memory controller 10 copies data A from the first memory block BLK1 to the second memory block BLK2, and then updates the mapping table so that the logical address of data A and the physical address to which it is mapped are mapped from the address of the first memory block BLK1 to the physical address of the second memory block BLK2.

[0073] In step S340, the memory device 100 erases the data in the first memory block. For example, referring to Figure 12C, the memory device 100 erases data A in the first memory block BLK1. In step S350, the memory device 100 performs a recovery operation for the first memory block. For example, referring to Figure 12D, the memory device 100 performs a recovery operation for the first memory block BLK1.

[0074] Although not shown in Figure 11, after step S350, the memory device 100 copies the data A stored in the second memory block to the first memory block. For example, referring to Figure 12E, the memory device 100 copies data A, which has been copied to the second memory block BLK2, to the first memory block BLK1, from which the recovery operation has been completed.

[0075] Figure 13 is a flowchart illustrating one embodiment that takes place after step S120 in Figure 8, and Figures 14A to 14E are flowcharts that specifically illustrate steps S430 to S460 in Figure 13. In the following explanation of Figures 13 and 14A-14E, any content that overlaps with Figures 8 and 9 will be omitted. Figure 13 will be explained with reference to Figures 1, 2, and 14A to 14E.

[0076] Referring to Figure 13, the first and third memory blocks in step S430 are blocks with degraded reliability. For example, referring to Figure 14A, the degradation counts of the first memory block BLK1 and the third memory block BLK3 are above the first reference value. The memory controller 10 designates the first memory block BLK1 and the third memory block BLK3 as memory blocks that require recovery operation. Before the recovery operation is performed, data A may be stored in the first memory block BLK1, and data B may be stored in the third memory block BLK3. In step S430, the memory device 100 may copy the data from the first memory block to the second memory block, or copy the data from the third memory block to the fourth memory block.

[0077] For example, referring to Figure 14B, the memory device 100 may copy data A from the first memory block BLK1 to the second memory block BLK2, or copy data B from the third memory block BLK3 to the fourth memory block BLK4. Although not shown in the diagram, the memory controller 10 copies data A from the first memory block BLK1 to the second memory block BLK2, and then updates the mapping table so that the logical address of data A and the physical address to which it is mapped are mapped from the address of the first memory block BLK1 to the physical address of the second memory block BLK2. Similarly, after copying data B from the third memory block BLK3 to the fourth memory block BLK4, the memory controller 10 updates the mapping table so that the logical address of data B and the physical address to which it is mapped are mapped from the address of the third memory block BLK3 to the physical address of the fourth memory block BLK4.

[0078] In step S440, the memory device 100 erases the data in the first memory block. For example, referring to Figure 14C, the memory device 100 erases data A in the first memory block BLK1. In step S450, the memory device 100 performs a recovery operation on the first memory block and simultaneously erases the data in the third memory block. For example, referring to Figure 14D, the memory device 100 performs a recovery operation for the first memory block BLK1. Simultaneously, the memory device 100 erases data B in the third memory block BLK3. In step S460, the memory device 100 performs a recovery operation for the third memory block. For example, referring to Figure 14E, the memory device 100 performs a recovery operation for the third memory block BLK3.

[0079] Figure 15 is a block diagram showing a schematic configuration example in which a memory device according to an exemplary embodiment of the present invention is applied to an SSD system. Referring to Figure 15, the test system 1000 comprises a host 1100 and an SSD 1200.

[0080] The SSD1200 exchanges signals with the host 1100 via a signal connector and receives power via a power connector. The SSD1200 comprises an SSD controller 1210, an auxiliary power supply 1220, and memory devices (1230, 1240, 1250). In this case, the SSD1200 is embodied using the embodiments described above with reference to Figures 1 to 14E. This causes each of the memory devices (1230, 1240, and 1250) to perform a recovery operation. At this time, the first criterion value used to determine whether or not a recovery operation is performed differs for each memory device. Each memory device (1230, 1240, 1250) is equipped with a recovery control circuit 1232, which applies a voltage for recovery operation to the word line and bit line of the memory block to be recovered during a recovery operation. This improves the reliability of the SSD system 1000 in terms of data retention characteristics.

[0081] Figure 16 is a diagram illustrating a method for generating a memory cell array according to an exemplary embodiment of the present invention. More specifically, Figure 16 shows a cross-section obtained by cutting in the direction A-A' in Figure 4. The details mentioned above in Figure 4 are omitted here.

[0082] Referring to Figure 16, the first memory stack ST1 is generated on the multiple layers generated by the method described above in Figure 4 through the first etching Etch1. Furthermore, the second memory stack ST2 is generated on multiple layers generated independently of the first memory stack ST1 through the second etching process Etch2. The first memory stack ST1 and the second memory stack ST2 are stacked so as to share channel holes with each other. The first memory stack ST1 includes a first memory cell MC1 connected to the second word line WL2, and the second memory stack ST2 includes a second memory cell MC2 connected to the sixth word line WL6.

[0083] Since the first memory stack ST1 and the second memory stack ST2 undergo the same manufacturing process, including the same etching process, the channel hole widths W1 and W2 contained in memory cells (e.g., MC1 and MC2) at the same height form similar profiles. For example, the first width W1 of the channel hole in the first memory cell MC1 is the same as or similar to the second width W2 of the channel hole in the second memory cell MC2. Therefore, the various operations of the first memory cell MC1 and the second memory cell MC2 are similar.

[0084] Figure 17 is a cross-sectional view illustrating the schematic configuration of a BVNAND structure applied to one embodiment of the present invention. Referring to Figure 17, the memory device 100 has a C2C (chip to chip) structure. The C2C structure means that an upper chip containing the cell region is fabricated on a first garment, and a lower chip containing the peripheral circuit region (PERI) is fabricated on a second garment different from the first garment, and then the upper and lower chips are connected to each other using a bonding method.

[0085] For example, the bonding method refers to a method of electrically connecting the bonding metal formed on the top metal layer of the upper chip with the bonding metal formed on the top metal layer of the lower chip. For example, if the bonding metal is made of copper (Cu), the bonding method is also a Cu-Cu bonding method, and the bonding metal can also be made of aluminum (Al) or tungsten (W). The peripheral circuit area PERI and the cell area CELL of the memory device 100 each include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0086] The peripheral circuit region (PERI) comprises a first substrate 210, an interlayer insulating layer 215, a plurality of circuit elements (520a, 220b, 220c) formed on the first substrate 210, first metal layers (230a, 230b, 230c) connected to each of the plurality of circuit elements (520a, 220b, 220c), and second metal layers (240a, 240b, 240c) formed on the first metal layers (230a, 230b, 230c). In one embodiment, the first metal layer (230a, 230b, 230c) is formed of tungsten, which has relatively high electrical resistivity, and the second metal layer (240a, 240b, 240c) is formed of copper, which has relatively low electrical resistivity.

[0087] In this specification, only the first metal layer (230a, 230b, 230c) and the second metal layer (240a, 240b, 240c) are shown and described, but the specification is not limited thereto, and at least one more metal layer may be further formed on the second metal layer (240a, 240b, 240c). At least a portion of one or more metal layers formed on top of the second metal layers (240a, 240b, 240c) may also be formed of aluminum or the like, which has an even lower electrical resistivity than the copper forming the second metal layers (240a, 240b, 240c). The interlayer insulating layer 215 is disposed on the first substrate 210 so as to cover a plurality of circuit elements 220a, 220b, 220c, first metal layers 230a, 230b, 230c, and second metal layers 240a, 240b, 240c, and contains an insulating material such as silicon oxide or silicon nitride.

[0088] Lower bonding metals 271b and 272b are formed on the second metal layer 240b of the wordline bonding region WLBA. In the word line bonding region (WLBA), the lower bonding metals 271b and 272b of the peripheral circuit region (PERI) are electrically connected to the upper bonding metals 371b and 372b of the cell region (CELL) by bonding, and the lower bonding metals 271b and 272b and the upper bonding metals 371b and 372b are formed from aluminum, copper, or tungsten, etc.

[0089] The cell region CELL provides at least one memory block. The cell region (CELL) includes a second substrate 310 and a common source line 320. On the second substrate 310, multiple word lines (331-338)(330) are stacked along the upper surface of the second substrate 310 in a direction perpendicular to the Z-axis direction. String selection lines and ground selection lines are arranged at the top and bottom of each wordline 330, and multiple wordlines 330 may be arranged between the string selection line and the ground selection line.

[0090] In the bitline bonding region BLBA, the channel structure CH extends perpendicularly (in the Z-axis direction) to the upper surface of the second substrate 310, passing through the word line 330, the string selection line, and the ground selection line. The channel structure CH comprises a data storage layer, a channel layer, and an embedded insulating layer, the channel layer being electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c is a bit line contact, and the second metal layer 360c is a bit line. In one embodiment, the bit line 360c extends along a first direction (Y-axis direction) parallel to the upper surface of the second substrate 310.

[0091] In one embodiment shown in Figure 17, the region where the channel structure CH and bit line 360c are arranged is defined as the bit line bonding region BLBA. The bit line 360c is electrically connected in the bit line bonding region BLBA to the circuit element 220c that provides the page buffer section 393 in the peripheral circuit region PERI. For example, bit line 360c is connected to upper bonding metals 371c and 372c in the peripheral circuit region PERI, and upper bonding metals 371c and 372c are connected to lower bonding metals 271c and 272c which are connected to circuit element 220c of page buffer section 393.

[0092] In the word line bonding region WLBA, the word line 330 extends along a second direction (X-axis direction) perpendicular to the first direction (Y-axis direction) and parallel to the upper surface of the second substrate 310, and is connected to a plurality of cell contact plugs (341-347)(340). The word line 330 and the cell contact plug 340 are connected to each other by provided pads, with at least a portion of the word line 330 extending to different lengths along the second direction. The first metal layer 350b and the second metal layer 360b are sequentially connected to the top of the cell contact plug 340, which is connected to the word line 330. The cell contact plug 340 is connected to the peripheral circuit area PERI in the word line bonding area WLBA through the upper bonding metals 371b and 372b of the cell area CELL and the lower bonding metals 271b and 272b of the peripheral circuit area PERI.

[0093] The cell contact plug 340 is electrically connected to the circuit element 220b that provides the low decoder 394 in the peripheral circuit area PERI. In one embodiment, the operating voltage of the circuit element 220b forming the row decoder 394 is different from the operating voltage of the circuit element 220c forming the page buffer section 393. For example, the operating voltage of the circuit element 220c that forms the page buffer section 393 is greater than the operating voltage of the circuit element 220b that forms the row decoder 394.

[0094] A common source line contact plug 380 is located in the external pad bonding area PA. The common source line contact plug 380 is made of a conductive material such as metal, a metallic compound, or polysilicon, and is electrically connected to the common source line 320. A first metal layer 350a and a second metal layer 360a are sequentially laminated on the upper part of the common source line contact plug 380. As an example, the region where the common source line contact plug 380, the first metal layer 350a, and the second metal layer 360a are located is defined as the external pad bonding region PA.

[0095] On the other hand, input / output pads 205 and 305 are located in the external pad bonding area PA. Referring to Figure 17, a lower insulating film 201 is formed on the lower part of the first substrate 210, covering the lower surface of the first substrate 210, and the first input / output pad 205 is formed on the lower insulating film 201. The first input / output pad 205 is connected via the first input / output contact plug 203 to at least one of several circuit elements (220a, 220b, 220c) located in the peripheral circuit region PERI, and is isolated from the first substrate 210 by the lower insulating film 201. Furthermore, a side insulating film is placed between the first input / output contact plug 203 and the first substrate 210 to electrically isolate the first input / output contact plug 203 and the first substrate 210.

[0096] In Figure 17, an upper insulating film 301 is formed on the upper part of the second substrate 310, covering the upper surface of the second substrate 310, and the second input / output pad 305 is placed on top of the upper insulating film 301. The second input / output pad 305 is connected via the second input / output contact plug 303 to at least one of several circuit elements (220a, 220b, 220c) located in the peripheral circuit area PERI. In one embodiment, the second input / output pad 305 is electrically connected to the circuit element 220a.

[0097] Depending on the embodiment, the area where the second input / output contact plug 303 is located does not need to include the second substrate 310 and the common source line 320. Furthermore, the second input / output pad 305 does not need to overlap with the word line 330 in the third direction (Z-axis direction). Referring to Figure 17, the second input / output contact plug 303 is separated from the second substrate 310 in a direction parallel to the upper surface of the second substrate 310, penetrates the interlayer insulating layer 315 of the cell region, and is connected to the second input / output pad 305. Depending on the embodiment, the first input / output pad 205 and the second input / output pad 305 may be selectively formed. For example, the memory device 100 may consist only of a first input / output pad 205 located on the upper part of the first substrate 210, or only of a second input / output pad 305 located on the upper part of the second substrate 310. Alternatively, the memory device 100 may include both the first input / output pad 205 and the second input / output pad 305.

[0098] In the external pad bonding region PA and bit line bonding region BLBA, which are included in the cell region CELL and peripheral circuit region PERI respectively, the metal pattern of the top metal layer may exist as a dummy pattern, or the top metal layer may be empty. In the external pad bonding region PA, the memory device 100 forms a lower metal pattern 273a on the uppermost metal layer of the peripheral circuit region PERI, corresponding to the upper metal pattern 372a formed on the uppermost metal layer of the cell region CELL.

[0099] The lower metal pattern 273a, formed on the uppermost metal layer of the peripheral circuit region (PERI), does not need to be connected to any other contacts in the peripheral circuit region (PERI). Similarly, in the external pad bonding region PA, an upper metal pattern 372a having the same form as the lower metal pattern 273a of the peripheral circuit region PERI may be formed on the upper metal layer of the cell region CELL, corresponding to the lower metal pattern 273a formed on the uppermost metal layer of the peripheral circuit region PERI. Lower bonding metals 271b and 272b are formed on the second metal layer 240b of the wordline bonding region WLBA. In the word line bonding region (WLBA), the lower bonding metals 271b and 272b of the peripheral circuit region (PERI) are electrically connected to each other by bonding with the upper bonding metals 371b and 372b of the cell region (CELL).

[0100] Furthermore, in the bit line bonding region BLBA, an upper metal pattern 392 having the same form as the lower metal pattern 252 of the peripheral circuit region PERI may be formed on the uppermost metal layer of the cell region CELL, corresponding to the lower metal pattern 252 formed on the uppermost metal layer of the peripheral circuit region PERI. It is not necessary to form contacts on the upper metal pattern 392 formed on the uppermost metal layer of the cell region.

[0101] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of symbols]

[0102] 1. Memory System 10 Memory Controllers 11 Block Management Module 12 ECC engine 100, 1230, 1240, 1250 memory devices 110 memory cell array 120 Voltage Generator 130 Control Logic 132, 1232 Recovery control circuit 140 Low Decoder 150 page buffer 1000 test systems 1100 hosts 1200 SSD 1210 SSD Controller 1220 Auxiliary power supply

Claims

1. In a method for operating a memory system comprising a memory device having multiple memory blocks and a memory controller, The memory controller includes the step of detecting a first memory block among the plurality of memory blocks that has a degradation count equal to or greater than a first reference value, The memory controller transmits a first command to the first memory block to the memory device, The memory device performs a recovery operation in which, in response to the first command, it applies a first voltage to any of the multiple word lines connected to the first memory block and applies a second voltage to the bit lines of the first memory block. The first voltage is higher than the voltage applied to turn on any of the multiple word lines connected to the first memory block, A method for operating a memory system, characterized in that the second voltage is higher than the voltage applied to the bit line during program operation, read operation, or erase operation of the memory device.

2. The operation method of the memory system according to claim 1, characterized in that the degradation count is a program / erase count for the plurality of memory blocks, or an error bit count obtained from the plurality of memory blocks.

3. The step of detecting a first memory block having a degradation count greater than or equal to the first reference value includes the step of the memory controller transmitting a second command to the memory device requesting the data stored in the first memory block, The memory device transmits the data to the memory controller, The method for operating the memory system according to claim 2, characterized in that the memory controller includes the step of counting error bits of the data.

4. Before performing the recovery operation, the data of the first memory block is copied to the second memory block among the plurality of memory blocks. The method for operating the memory system according to claim 1, further comprising the step of erasing the first memory block.

5. The steps include detecting a third memory block among the plurality of memory blocks that has a degradation count equal to or greater than the first reference value, The steps include copying the data of the third memory block to the fourth memory block among the plurality of memory blocks, The steps include: erasing the third memory block while the recovery operation for the first memory block is performed; The method for operating a memory system according to claim 4, further comprising the step of performing a recovery operation for the third memory block.

6. A memory cell array including multiple memory blocks having multiple memory cells, multiple word lines connected to the multiple memory blocks, and multiple bit lines connected to the multiple memory blocks, The system includes a control circuit that controls the operation of a first memory block among the plurality of memory blocks, During the control operation, the control circuit copies the data from the first memory block among the plurality of memory blocks to the second memory block among the plurality of memory blocks. The data in the aforementioned first memory block is erased, A first voltage is applied to a selected portion of the word lines among the multiple word lines connected to the first memory block. A second voltage is applied to the bit line of the first memory block, The first voltage is higher than the voltage applied to turn on memory cells connected to a selected portion of the word lines among the plurality of word lines connected to the first memory block. The memory device is characterized in that the second voltage is controlled to be higher than the voltage applied to the bit line during program operation, read operation, or erase operation of the memory device.

7. The memory device according to claim 6, characterized in that the memory cell of the memory device has a silicon-on-insulator structure.

8. A memory device having multiple memory blocks, The memory device includes a memory controller that transmits commands to control the memory device, In response to the command, the memory device copies the data of the first memory block among the plurality of memory blocks to the second memory block among the plurality of memory blocks, erases the data of the first memory block, applies a first voltage to any of the plurality of word lines connected to the first memory block, and applies a second voltage to the bit lines of the first memory block. The first voltage is higher than the voltage applied to turn on any of the multiple word lines connected to the first memory block, A memory system characterized in that the second voltage is higher than the voltage applied to the bit line during the pre-charge operation of the memory device.

9. The memory system according to claim 8, characterized in that the memory controller selects a memory block having a degradation count of a certain value or higher from among the plurality of memory blocks as the first memory block, and provides the address of the first memory block to the memory device.

10. The memory system according to claim 9, characterized in that the memory controller detects the first memory block whose degradation cycle is equal to or greater than the reference value, and then determines the error bits of the first memory block.

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