Wiring board and method for manufacturing a wiring board

Abstract

To provide a wiring board that can suppress the degradation of electrical connection reliability.SOLUTION: A wiring board 10 has a wiring layer 32 and an insulating layer 40 covering the top surface of the wiring layer 32. The wiring board 10 has a first through-hole 51 that penetrates the insulating layer 40 in a thickness direction and exposes a portion of the top surface of the wiring layer 32, a second through-hole 52 that is provided adjacent to the first through-hole 51 and also penetrates the insulating layer 40 in a thickness direction to expose a portion of the top surface of the wiring layer 32, and a connecting hole 53 that connects the bottom of the first through-hole 51 and the bottom of the second through-hole 52. The wiring board 10 has via wiring 50V that fills the first through hole 51, the second through hole 52, and the connecting hole 53, and a wiring layer 82 that is formed integrally with the via wiring 50V and formed on the top surface of the insulating layer 40.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a wiring board and a method for manufacturing the wiring board.

Background Art

[0002] Conventionally, wiring boards for mounting electronic components such as semiconductor elements have been proposed in various shapes and structures. As this type of wiring board, a wiring board in which a plurality of wiring layers and a plurality of insulating layers are alternately laminated by a build-up method is known (see, for example, Patent Document 1). The plurality of wiring layers are electrically connected to each other via via wirings formed in through holes penetrating the insulating layer in the thickness direction.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, when heat is applied to the wiring board in a reliability test or the like, cracks may occur at the interface between the via wiring and the wiring layer. When cracks occur at the interface between the via wiring and the wiring layer, there arises a problem that the electrical connection reliability between the via wiring and the wiring layer decreases.

Means for Solving the Problems

[0005] According to one aspect of the present invention, the present invention comprises a first wiring layer, an insulating layer covering the upper surface of the first wiring layer, a first through-hole penetrating the insulating layer in the thickness direction and exposing a part of the upper surface of the first wiring layer, a second through-hole adjacent to the first through-hole and penetrating the insulating layer in the thickness direction and exposing a part of the upper surface of the first wiring layer, a communication hole connecting the bottom of the first through-hole and the bottom of the second through-hole, via wiring filling the first through-hole, the second through-hole and the communication hole, and a second wiring layer formed integrally with the via wiring and formed on the upper surface of the insulating layer. The first wiring layer has a first recess provided on the upper surface of the first wiring layer exposed from the first through hole, and a second recess provided on the upper surface of the first wiring layer exposed from the second through hole, and the communication hole is formed to communicate with the first recess and the second recess, and the first recess is formed continuously with the second recess. . [Effects of the Invention]

[0006] According to one aspect of the present invention, the effect is to suppress the deterioration of electrical connection reliability. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic cross-sectional view showing a wiring board of one embodiment. [Figure 2] This is a schematic cross-sectional view showing an enlarged portion of a wiring board according to one embodiment. [Figure 3] This is a schematic plan view showing an enlarged portion of a wiring board according to one embodiment. [Figure 4] This is a schematic cross-sectional view showing a manufacturing method for a wiring board according to one embodiment. [Figure 5] This is a schematic cross-sectional view showing a manufacturing method for a wiring board according to one embodiment. [Figure 6] This is a schematic cross-sectional view showing a manufacturing method for a wiring board according to one embodiment. [Figure 7] This is a schematic cross-sectional view showing a manufacturing method for a wiring board according to one embodiment. [Figure 8] This is a schematic cross-sectional view showing a manufacturing method for a wiring board according to one embodiment. [Figure 9] This is a schematic cross-sectional view showing a manufacturing method for a wiring board according to one embodiment. [Figure 10] This is a schematic cross-sectional view showing a manufacturing method for a wiring board according to one embodiment. [Figure 11]This is a schematic cross-sectional view showing a manufacturing method for a wiring board according to one embodiment. [Figure 12] This is a schematic cross-sectional view showing a manufacturing method for a wiring board according to one embodiment. [Figure 13] This is a schematic cross-sectional view showing a manufacturing method for a wiring board according to one embodiment. [Figure 14] This is a schematic cross-sectional view showing a magnified portion of the wiring board in the modified example. [Figure 15] This is a schematic cross-sectional view showing a magnified portion of the wiring board in the modified example. [Figure 16] This is a schematic plan view showing a magnified portion of the wiring board in the modified example. [Figure 17] This is a schematic cross-sectional view showing a modified wiring board. [Modes for carrying out the invention]

[0008] An embodiment will be described below with reference to the attached drawings. For convenience, the attached drawings may show enlarged versions of characteristic parts to make the features easier to understand, and the dimensional ratios of each component may differ in each drawing. In addition, in the cross-sectional views, to make the cross-sectional structure of each member easier to understand, the hatching of some members has been replaced with a textured pattern, and the hatching of some members has been omitted. In this specification, "plan view" refers to viewing the object from the vertical direction (up and down direction in the drawing) as shown in Figure 1, and "planar shape" refers to the shape of the object as viewed from the vertical direction as shown in Figure 1. In this specification, "up and down direction" and "left and right direction" refer to the direction in which the symbols indicating each member in each drawing are correctly readable, with the orientation being considered the positive position. In this specification, "parallel," "orthogonal," and "perpendicular" include not only cases where they are strictly parallel, orthogonal, or perpendicular, but also cases where they are approximately parallel, orthogonal, or perpendicular within the range that produces the effects of this embodiment. In this specification, "equal" includes not only cases where they are exactly equal, but also cases where there are slight differences between the comparison objects due to the effects of dimensional tolerances, etc.

[0009] (Overall configuration of the wiring board 10) First, the structure of the wiring board 10 will be described according to FIG. 1. As shown in FIG. 1, the wiring board 10 has, for example, a substrate body 11. On the lower surface of the substrate body 11, a wiring layer 21, an insulating layer 22, a wiring layer 23, and a solder resist layer 24 are laminated in this order. On the upper surface of the substrate body 11, a wiring layer 30, an insulating layer 40, and a wiring layer 80 are laminated in this order.

[0010] As the substrate body 11, for example, a wiring structure in which an insulating resin layer and a wiring layer are alternately laminated can be used. The wiring structure may have, for example, a core substrate or may not have a core substrate. As the material of the insulating resin layer, for example, a thermosetting insulating resin can be used. As the thermosetting insulating resin, for example, an insulating resin such as an epoxy resin, a polyimide resin, or a cyanate resin can be used. Also, as the material of the insulating resin layer, for example, an insulating resin mainly composed of a photosensitive resin such as a phenolic resin or a polyimide resin can be used. The insulating resin layer may contain, for example, fillers such as silica or alumina.

[0011] As the material of the wiring layer of the substrate body 11 and the wiring layers 21, 23, and 30, for example, copper (Cu) or a copper alloy can be used. As the material of the insulating layers 22 and 40, for example, a thermosetting insulating resin can be used. As the thermosetting insulating resin, for example, an insulating resin such as an epoxy resin, a polyimide resin, or a cyanate resin can be used.

[0012] The wiring layer 21 is formed on the lower surface of the substrate body 11. On the lower surface of the substrate body 11, an insulating layer 22 that covers the wiring layer 21 is laminated. On the lower surface of the insulating layer 22, a wiring layer 23 is laminated. The wiring layer 23 is formed integrally with, for example, a via wiring that penetrates the insulating layer 22 in the thickness direction, and is electrically connected to the wiring layer 21 through the via wiring.

[0013] A solder resist layer 24 covering the wiring layer 23 is laminated on the underside of the insulating layer 22. As the material for the solder resist layer 24, for example, an insulating resin mainly composed of a photosensitive resin such as a phenolic resin or a polyimide resin can be used. The solder resist layer 24 may also contain fillers such as silica or alumina. Furthermore, the material for the solder resist layer 24 is not limited to an insulating resin mainly composed of a photosensitive resin; for example, the same insulating resin as the insulating layer 22 may be used. The solder resist layer 24 has multiple openings 24X formed therein to expose a portion of the underside of the wiring layer 23 as an external connection pad 23P. External connection terminals such as solder balls and lead pins used when mounting the wiring board 10 to a mounting board such as a motherboard are connected to the external connection pad 23P.

[0014] A surface treatment layer is formed on the lower surface of the wiring layer 23 exposed at the bottom of the opening 24X, as needed. Examples of surface treatment layers include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer formed by stacking Ni and Au layers in that order), and a Ni layer / palladium (Pd) layer / Au layer (a metal layer formed by stacking Ni, Pd, and Au layers in that order). Here, the Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or a Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy. For these Ni, Au, and Pd layers, for example, metal layers formed by electroless plating, i.e., electroless plated metal layers, can be used. Another example of a surface treatment layer is an OSP (Organic Solderability Preservative) film formed by applying an anti-oxidation treatment such as OSP treatment to the surface of the external connection pad 23P. As the OSP film, an organic coating such as an azole compound or an imidazole compound can be used. Furthermore, if a surface treatment layer is formed on the underside of the wiring layer 23, that surface treatment layer functions as an external connection pad 23P. Alternatively, the wiring layer 23 (or, if a surface treatment layer is formed on the wiring layer 23, that surface treatment layer) exposed at the bottom of the opening 24X may itself be used as an external connection terminal.

[0015] The wiring layer 30 is formed on the upper surface of the substrate body 11. The wiring layer 30 is electrically connected to the wiring layer 21, for example, via wiring layers or through electrodes within the substrate body 11. The thickness of the wiring layer 30 can be, for example, about 5 μm to 20 μm.

[0016] The wiring layer 30 includes, for example, a wiring layer 31 and a wiring layer 32. The wiring layer 31 is, for example, a signal wiring layer. The wiring layer 32 is, for example, a plane layer. Examples of plane layers include a power plane and a GND plane.

[0017] The wiring layer 32 is formed, for example, as a solid block. For example, the planar shape of the wiring layer 32 is larger than the planar shape of the wiring layer 31. For example, the wiring layer 32 is provided on the outer periphery side of the wiring board 10 than the wiring layer 31.

[0018] The insulating layer 40 is laminated on the upper surface of the substrate body 11 so as to cover the upper surface of the wiring layer 30. The insulating layer 40 is formed to cover the sides of the wiring layer 30. The thickness from the upper surface of the wiring layer 30 to the upper surface of the insulating layer 40 can be, for example, about 10 μm to 30 μm.

[0019] The insulating layer 40 has through-holes 41 that penetrate the insulating layer 40 in the thickness direction, exposing a portion of the upper surface of the wiring layer 31. The planar shape of the through-holes 41 can be set to any shape and size. In this example, the planar shape of the through-holes 41 is circular. The depth of the through-holes 41 can be, for example, about 10 μm to 30 μm. In this example, the through-holes 41 are tapered, for example, in Figure 1, with the opening width (opening diameter) decreasing from the top (upper surface side of the insulating layer 40) to the bottom.

[0020] The insulating layer 40 has through-holes 50 that penetrate the insulating layer 40 in the thickness direction and expose a portion of the upper surface of the wiring layer 32. The through-holes 50 include a first through-hole 51, a second through-hole 52 provided adjacent to the first through-hole 51, and a communication hole 53 that connects the bottom of the first through-hole 51 and the bottom of the second through-hole 52. The first through-hole 51 is formed to penetrate the insulating layer 40 in the thickness direction and expose a portion of the upper surface of the wiring layer 32. The second through-hole 52 is formed to penetrate the insulating layer 40 in the thickness direction and expose a portion of the upper surface of the wiring layer 32. The planar shape of the first through-hole 51 and the second through-hole 52 can be set to any shape and size. In this example, the planar shape of the first through-hole 51 and the second through-hole 52 is formed to be circular. The depth of the first through-hole 51 and the second through-hole 52 can be, for example, about 10 μm to 30 μm. Each of the first through-hole 51 and the second through-hole 52 is formed in a tapered shape, for example, in Figure 1, where the opening width (opening diameter) decreases as you move from the top (top surface side of the insulating layer 40) to the bottom.

[0021] A wiring layer 80 is laminated on the upper surface of the insulating layer 40. The wiring layer 80 is the outermost (in this case, the topmost) wiring layer of the wiring board 10. The thickness of the wiring layer 80 can be, for example, about 5 μm to 20 μm.

[0022] The wiring layer 80 includes, for example, a wiring layer 81 and a wiring layer 82. The wiring layer 81 functions as a connection pad for connecting to electronic components such as semiconductor elements. The wiring layer 81 is electrically connected to the wiring layer 31, for example, via via wiring 41V formed in through holes 41 of the insulating layer 40. The wiring layer 81 is formed integrally with the via wiring 41V, for example. The via wiring 41V is formed, for example, to fill the through holes 41. The thickness of the via wiring 41V can be, for example, about 10 μm to 30 μm.

[0023] The wiring layer 82 is electrically connected to the wiring layer 32, for example, via via wiring 50V formed in through holes 50 of the insulating layer 40. The wiring layer 82 is formed continuously and integrally with the via wiring 50V. The via wiring 50V is formed to fill through holes 50, for example. The via wiring 50V is formed to fill the first through hole 51, the second through hole 52, and the communication hole 53, for example. The thickness of the via wiring 50V can be, for example, about 10 μm to 30 μm.

[0024] Next, the structure of the wiring layer 32, insulating layer 40, through-hole 50, via wiring 50V, and wiring layer 82 will be described in detail according to Figures 2 and 3. Figure 3 is a plan view of the wiring board 10 shown in Figure 2, viewed from above, with the insulating layer 40 depicted in perspective.

[0025] As shown in Figure 2, a recess 33 is formed on the upper surface of the wiring layer 32, recessed toward the substrate body 11. The planar shape of the recess 33 can be set to any shape and size. The recess 33 is formed to communicate with, for example, the through hole 50. The recess 33 is formed to communicate with, for example, the first through hole 51 and the second through hole 52. The recess 33 is formed to communicate with, for example, the communication hole 53. The recess 33 is formed to extend from the upper surface of the wiring layer 32 to an intermediate position in the thickness direction of the wiring layer 32. That is, the bottom surface of the recess 33 is formed to be located midway in the thickness direction of the wiring layer 32, and is formed not to penetrate through the thickness direction of the wiring layer 32. The recess 33 is formed to overlap with the entire through hole 50 in a plan view, for example. The recess 33 is formed to extend in the planar direction of the wiring layer 32 (i.e., in a direction perpendicular to the thickness direction of the wiring layer 32 in a cross-sectional view).

[0026] The recess 33 is formed, for example, by connecting two first recesses 34 and a second recess 35. The first recess 34 and the second recess 35 are formed continuously along the first direction D1 (left-right direction in the figure) where the first through hole 51 and the second through hole 52 are aligned.

[0027] The first recess 34 is provided, for example, on the upper surface of the wiring layer 32 exposed from the first through hole 51. The first recess 34 is formed, for example, to communicate directly with the first through hole 51. The first recess 34 is formed, for example, to overlap with the first through hole 51 in a plan view. As shown in Figure 3, the planar shape of the first recess 34 is formed, for example, to be the same shape as the planar shape of the first through hole 51. The planar shape of the first recess 34 is formed, for example, to be circular overall. The planar shape of the first recess 34 is formed, for example, to be concentric with the planar shape of the first through hole 51.

[0028] As shown in Figure 2, the second recess 35 is provided, for example, on the upper surface of the wiring layer 32 exposed from the second through hole 52. The second recess 35 is formed, for example, to communicate directly with the second through hole 52. The second recess 35 is formed, for example, to overlap with the second through hole 52 in a plan view. As shown in Figure 3, the planar shape of the second recess 35 is formed, for example, to be similar in shape to the planar shape of the second through hole 52. The planar shape of the second recess 35 is formed, for example, to be circular overall. The planar shape of the second recess 35 is formed, for example, to be concentric with the planar shape of the second through hole 52.

[0029] The recess 33 is formed such that, for example, in a plan view, a part of the circumferential direction of the first recess 34 and a part of the circumferential direction of the second recess 35 are connected. The planar shape of the recess 33 is formed such that, for example, two circles are connected at parts in the circumferential direction.

[0030] As shown in Figure 2, the cross-sectional shapes of the first recess 34 and the second recess 35 are formed, for example, semicircular or semielliptical. The inner surfaces of the first recess 34 and the second recess 35 are formed as curved surfaces that are curved in an arc shape or an elliptical arc shape in cross-sectional view. The inner surface of the first recess 34 is formed to curve downward as it approaches the center of the plane of the first through hole 51 from the outer edge of the first recess 34. The inner surface of the second recess 35 is formed to curve downward as it approaches the center of the plane of the second through hole 52 from the outer edge of the second recess 35. In this example, the inner surface of the recess 33 is formed in a shape where the semielliptical arc of the first recess 34 and the semielliptical arc of the second recess 35 are continuous along the plane direction in cross-sectional view. The depth of the recess 33 can be, for example, about 1 μm to 5 μm.

[0031] Next, the specific structure of the through-hole 50 will be described. (Specific structure of the first through-hole 51) The first through-hole 51 has a stepped portion midway in the depth direction. The first through-hole 51 has a stepped portion at its bottom. The first through-hole 51 has a first inner wall surface 55 extending downward from the upper surface of the insulating layer 40, and a first recessed portion 56 that recesses outward from the first inner wall surface 55. The first inner wall surface 55 and the first recessed portion 56 form a stepped portion at the bottom of the first through-hole 51.

[0032] The first inner wall surface 55 of the first through hole 51 is formed to extend downward from, for example, the upper opening end 51A (i.e., the upper end) of the first through hole 51 to the first recess 56. The first inner wall surface 55 is formed to slope downward from, for example, the opening end 51A toward the inside of the first through hole 51 (i.e., the center of the plane of the first through hole 51). For example, the first inner wall surface 55 is formed to slope toward the center of the plane of the first through hole 51 as it moves from the upper surface of the insulating layer 40 toward the first recess 56. Note that the first inner wall surface 55 does not need to be a flat surface; part or all of the first inner wall surface 55 may be a convex or concave curved surface. In this example, the first inner wall surface 55 is formed as a plane that slopes to extend in a straight line without any steps in a cross-sectional view.

[0033] The first recess 56 is formed in a continuous manner with the lower end of the first inner wall surface 55. The first recess 56 is formed to widen the opening width (in this example, the opening diameter) at the bottom of the first through hole 51. For example, the first recess 56 is formed to widen the opening width of the first through hole 51 beyond the opening width at the lower end of the first inner wall surface 55. As shown in Figure 3, the first recess 56 is formed in a continuous manner with respect to the entire circumference of the first through hole 51. The first recess 56 is formed in a continuous manner with respect to the entire circumference of the first through hole 51 to widen the opening width at the bottom of the first through hole 51. For example, the first recess 56 is formed to overlap with the first recess 34 in a plan view.

[0034] As shown in Figure 2, the first recess 56 has a first inner end 57 which is the bottom of the first recess 56, and a first inner surface 58 which is formed to extend from the lower end of the first inner wall surface 55 to the first inner end 57. In a plan view, the first inner end 57 is located at the position furthest from the lower end of the first inner wall surface 55 within the first recess 56. The first inner end 57 is connected, for example, to the opening end of the first recess 34. The first inner surface 58 is formed to slope downward, for example, from the lower end of the first inner wall surface 55 toward the outside of the first through hole 51 (i.e., toward the plane away from the center of the first through hole 51). The first inner surface 58 does not have to be a plane; part or all of the first inner surface 58 may be a convex or concave curved surface. In this example, the first inner surface 58 is formed as a plane that slopes to extend in a straight line without any steps in a cross-sectional view.

[0035] The opening width of the first through-hole 51 in the first recess 56 is set to be larger than the opening width of the first through-hole 51 at the lower end of the first inner wall surface 55. The opening width of the first through-hole 51 in the first recess 56 is set to be, for example, equal to the opening width of the first through-hole 51 at the opening end 51A, or larger than the opening width of the first through-hole 51 at the opening end 51A. Specifically, the opening width of the first through-hole 51 at the first inner end 57 is set to be equal to the opening width of the first through-hole 51 at the opening end 51A, or larger than the opening width of the first through-hole 51 at the opening end 51A. In this example, the opening width of the first through-hole 51 at the first inner end 57 is set to be larger than the opening width of the first through-hole 51 at the opening end 51A. That is, in this example, the first inner end 57 is located further inside the insulating layer 40 than the opening end 51A. In other words, in this example, the first inner end portion 57 is located at a position further from the center of the first through-hole 51 in a plan view than the open end portion 51A.

[0036] The opening width of the first through-hole 51 at the open end 51A can be, for example, about 50 μm to 100 μm. The opening width of the first through-hole 51 at the lower end of the first inner wall surface 55 can be, for example, about 30 μm to 80 μm. The opening width of the first through-hole 51 at the first inner end 57 of the first recess 56 can be, for example, about 50 μm to 150 μm.

[0037] (Specific structure of the second through-hole 52) The second through-hole 52 has a stepped portion midway in the depth direction. The second through-hole 52 has a stepped portion at its bottom. The second through-hole 52 has a second inner wall surface 65 extending downward from the upper surface of the insulating layer 40, and a second recessed portion 66 that recesses outward from the second inner wall surface 65. The second inner wall surface 65 and the second recessed portion 66 form a stepped portion at the bottom of the second through-hole 52.

[0038] The second inner wall surface 65 of the second through-hole 52 is formed to extend downward from, for example, the upper opening end 52A (i.e., the upper end) of the second through-hole 52 to the second recess 66. The second inner wall surface 65 is formed to slope downward from, for example, the opening end 52A toward the inside of the second through-hole 52 (i.e., the plane center of the second through-hole 52). For example, the second inner wall surface 65 is formed to slope toward the plane center of the second through-hole 52 as it moves from the upper surface of the insulating layer 40 toward the second recess 66. Note that the second inner wall surface 65 does not need to be a flat surface; part or all of the second inner wall surface 65 may be a convex or concave curved surface. In this example, the second inner wall surface 65 is formed as a plane that slopes to extend in a straight line without any steps in a cross-sectional view.

[0039] The second recess 66 is formed in a continuous manner with the lower end of the second inner wall surface 65. The second recess 66 is formed to widen the opening width (opening diameter in this example) at the bottom of the second through hole 52. For example, the second recess 66 is formed to widen the opening width of the second through hole 52 more than the opening width at the lower end of the second inner wall surface 65 within the second through hole 52. As shown in Figure 3, for example, the second recess 66 is formed continuously around the entire circumference of the second through hole 52. The second recess 66 is formed around the entire circumference of the second through hole 52 to widen the opening width at the bottom of the second through hole 52. For example, the second recess 66 is formed to overlap with the second recess 35 in a plan view.

[0040] As shown in Figure 2, the second recess 66 has a second inner end 67, which is the bottom of the second recess 66, and a second inner surface 68 that is formed to extend from the lower end of the second inner wall surface 65 to the second inner end 67. In a plan view, the second inner end 67 is located at the position furthest from the lower end of the second inner wall surface 65 within the second recess 66. The second inner end 67 is connected, for example, to the opening end of the second recess 35. The second inner surface 68 is formed to slope downward, for example, from the lower end of the second inner wall surface 65 toward the outside of the second through hole 52 (i.e., toward the plane away from the center of the second through hole 52). The second inner surface 68 does not need to be a plane; part or all of the second inner surface 68 may be a convex or concave curved surface. In this example, the second inner surface 68 is formed as a plane that slopes to extend in a straight line without any steps in a cross-sectional view.

[0041] The opening width of the second through-hole 52 in the second recess 66 is set to be larger than the opening width of the second through-hole 52 at the lower end of the second inner wall surface 65. The opening width of the second through-hole 52 in the second recess 66 is set to be, for example, equal to the opening width of the second through-hole 52 at the opening end 52A, or larger than the opening width of the second through-hole 52 at the opening end 52A. Specifically, the opening width of the second through-hole 52 at the second inner end 67 is set to be equal to the opening width of the second through-hole 52 at the opening end 52A, or larger than the opening width of the second through-hole 52 at the opening end 52A. In this example, the opening width of the second through-hole 52 at the second inner end 67 is set to be larger than the opening width of the second through-hole 52 at the opening end 52A. That is, in this example, the second inner end 67 is located further inside the insulating layer 40 than the opening end 52A. In other words, in this example, the second inner end portion 67 is located at a position further from the center of the second through-hole 52 in a plan view than the open end portion 52A.

[0042] The opening width of the second through-hole 52 at the open end 52A can be, for example, about 50 μm to 100 μm. The opening width of the second through-hole 52 at the lower end of the second inner wall surface 65 can be, for example, about 30 μm to 80 μm. The opening width of the second through-hole 52 at the second inner end 67 of the second recess 66 can be, for example, about 50 μm to 150 μm.

[0043] (Specific structure of the communication hole 53) The communication hole 53 is formed to connect the bottom of the first through hole 51 and the bottom of the second through hole 52. The communication hole 53 is formed to widen the opening width at the bottom of the first through hole 51 and also to widen the opening width at the bottom of the second through hole 52. The communication hole 53 is formed, for example, by connecting a part of the first recess 56 and a part of the second recess 66. That is, the communication hole 53 is composed of a part of the first recess 56 and a part of the second recess 66. As shown in Figure 3, the communication hole 53 is formed by connecting a part of the circumferential direction of the first recess 56 and a part of the circumferential direction of the second recess 66.

[0044] As shown in Figure 2, the communication hole 53 is formed to extend from the first inner wall surface 55 of the first through hole 51 to the second inner wall surface 65 of the second through hole 52 in the first direction D1 (left-right direction in the figure) where the first through hole 51 and the second through hole 52 are aligned. The communication hole 53 is formed to penetrate in the first direction D1 through the lower part of the insulating layer 40 provided between the first through hole 51 and the second through hole 52. The communication hole 53 has a depth along the second direction D2 which is perpendicular to the first direction D1, for example. The communication hole 53 is formed such that, for example, the narrowest part A1, i.e., the part with the smallest depth, is at the midpoint of the communication hole 53 in the first direction D1. The communication hole 53 is formed such that, for example, the depth of the communication hole 53 increases from the midpoint of the communication hole 53 in the first direction D1, i.e., the narrowest part A1, toward both opening ends of the communication hole 53. More specifically, the communication hole 53 is formed such that its depth increases as it moves from the narrowest part A1 toward the first through hole 51 (specifically, the lower end of the first inner wall surface 55). Furthermore, the communication hole 53 is formed such that its depth increases as it moves from the narrowest part A1 toward the second through hole 52 (specifically, the lower end of the second inner wall surface 65). In other words, the communication hole 53 is formed such that its opening width decreases as it moves from the first inner wall surface 55 toward the narrowest part A1, and also as it moves from the second inner wall surface 65 toward the narrowest part A1.

[0045] The lower surface of the insulating layer 40 constituting the inner surface of the communication hole 53 is formed as an inclined surface that extends inclined with respect to the first direction D1. The lower surface of the insulating layer 40 constituting the inner surface of the communication hole 53 is formed to slope upward as it moves from the narrowest part A1 toward the lower end of the first inner wall surface 55. The lower surface of the insulating layer 40 constituting the inner surface of the communication hole 53 is formed to slope upward as it moves from the narrowest part A1 toward the lower end of the second inner wall surface 65.

[0046] The communication hole 53 opens, for example, downward, that is, toward the wiring layer 32. The communication hole 53 is formed to communicate directly with, for example, the first recess 34. The communication hole 53 is formed to communicate directly with, for example, the second recess 35. The narrowest part A1 of the communication hole 53 is formed to overlap in a plan view with, for example, the portion where the open end of the first recess 34 and the open end of the second recess 35 are connected.

[0047] Here, in the portion of the first recess 56 that constitutes the communication hole 53, the first inner end portion 57 disappears with the formation of the communication hole 53. In the portion of the second recess 66 that constitutes the communication hole 53, the second inner end portion 67 disappears with the formation of the communication hole 53.

[0048] The length of the communication hole 53 along the first direction D1, that is, the distance along the first direction D1 from the lower end of the first inner wall surface 55 of the first through hole 51 to the lower end of the second inner wall surface 65 of the second through hole 52, can be, for example, about 30 μm to 100 μm. The depth of the communication hole 53, that is, the distance along the second direction D2 from the lower end of the first inner wall surface 55 to the upper surface of the wiring layer 32, can be, for example, about 1 μm to 5 μm.

[0049] (Specific structure of 50V via wiring) The via wiring 50V is formed, for example, to fill the through hole 50 and the recess 33 of the wiring layer 32. The via wiring 50V is formed, for example, to fill the first recess 34 and the second recess 35 of the wiring layer 32. The via wiring 50V is formed to fill the first through hole 51 having a first recess 56 and the second through hole 52 having a second recess 66. The via wiring 50V is formed, for example, to cover the lower surface of the insulating layer 40 that constitutes the inner surface of the communication hole 53. As a result, the via wiring 50V is formed to penetrate below the insulating layer 40 in the communication hole 53. The via wiring 50V is formed, for example, to cover the lower surface of the insulating layer 40 that constitutes the first inner surface 58 of the first recess 56. The via wiring 50V is formed, for example, to cover the lower surface of the insulating layer 40 that constitutes the second inner surface 68 of the second recess 66. As a result, the via wiring 50V is formed in the first recess 56 and the second recess 66 so as to penetrate below the insulating layer 40.

[0050] The via wiring 50V is formed to cover the entire upper surface of the wiring layer 32 exposed from the through hole 50. The via wiring 50V is formed to cover the entire inner surface of the recess 33 exposed from the through hole 50. The via wiring 50V is formed to cover the entire inner surface of the first recess 34 exposed from the through hole 50, and also to cover the entire inner surface of the second recess 35 exposed from the through hole 50.

[0051] The via wiring 50V includes, for example, a seed layer 70 that covers the inner surface of the through hole 50 and the upper surface of the wiring layer 32 exposed from the through hole 50, and a metal layer 71 that fills the through hole 50 and recess 33 inside the seed layer 70.

[0052] The seed layer 70 is formed to continuously cover, for example, the entire inner surface of the through hole 50 and the entire upper surface of the wiring layer 32 exposed from the through hole 50. The seed layer 70 is formed to continuously cover, for example, the upper surface of the insulating layer 40, the entire surface of the first inner wall surface 55, the entire surface of the first inner surface 58, the entire inner surface of the first recess 34, the entire inner surface of the second recess 35, the entire surface of the second inner surface 68, and the entire surface of the second inner wall surface 65. The seed layer 70 is formed to continuously cover, for example, the upper surface of the insulating layer 40, the entire surface of the first inner wall surface 55, the entire lower surface of the insulating layer 40 constituting the inner surface of the communication hole 53, and the entire surface of the second inner wall surface 65. As the material for the seed layer 70, for example, copper or a copper alloy can be used. As the seed layer 70, for example, an electroless plated metal layer formed by an electroless plating method can be used.

[0053] The metal layer 71 is formed to fill, for example, the first through-hole 51 and the first recess 56 located inside the seed layer 70. The metal layer 71 is formed to fill, for example, the second through-hole 52 and the second recess 66 located inside the seed layer 70. The metal layer 71 is formed to fill, for example, the communication hole 53 located inside the seed layer 70. The metal layer 71 is formed to fill, for example, the first recess 34 and the second recess 35 located inside the seed layer 70. Here, the portion of the metal layer 71 that fills the communication hole 53 is provided so as to be sandwiched in the second direction D2 between the seed layer 70 that covers the inner surface of the communication hole 53 and the seed layer 70 that covers the inner surface of the recess 33. As the material for the metal layer 71, for example, copper or a copper alloy can be used. As the metal layer 71, for example, a metal layer formed by an electroplating method, i.e., an electroplated metal layer, can be used.

[0054] The via wiring 50V is formed by the seed layer 70 and the metal layer 71 formed within the through hole 50 and recess 33 as described above. (Specific structure of wiring layer 82) The wiring layer 82 has, for example, a first wiring pattern 83 and a second wiring pattern 84. The first wiring pattern 83 is formed so as to overlap with the first through hole 51 in a plan view. The second wiring pattern 84 is formed so as to overlap with the second through hole 52 in a plan view. The first wiring pattern 83 and the second wiring pattern 84 are not directly connected on the upper surface of the insulating layer 40. That is, on the upper surface of the insulating layer 40, the first wiring pattern 83 and the second wiring pattern 84 are provided apart from each other. However, the first wiring pattern 83 and the second wiring pattern 84 are electrically connected to each other through via wiring 50V.

[0055] Each of the first wiring pattern 83 and the second wiring pattern 84 has, for example, a seed layer 70 formed on the upper surface of the insulating layer 40, and a metal layer 72 formed on the seed layer 70 and via wiring 50V (metal layer 71). The metal layer 72 is formed, for example, to protrude upward from the upper surface of the insulating layer 40. The metal layer 72 is formed, for example, continuously and integrally with the metal layer 71. As the material of the metal layer 72, for example, copper or a copper alloy can be used. As the metal layer 72, for example, an electroplated metal layer formed by an electroplating method can be used.

[0056] As described above, the wiring layer 32 and the wiring layer 82 are electrically connected to each other through via wiring 50V that fills the communication hole 53 and the first through hole 51 and the second through hole 52 which are connected by the communication hole 53.

[0057] In Figure 2, the tips of the first inner end 57, the second inner end 67, and the narrowest part A1 are depicted as pointed. However, in reality, the tips of the first inner end 57, the second inner end 67, and the narrowest part A1 may be formed in a curved shape. In subsequent drawings, as in Figure 2, the tips of the first inner end 57, the second inner end 67, and the narrowest part A1 are depicted as pointed.

[0058] Furthermore, the wiring board 10 can be used upside down or positioned at any angle. Next, the manufacturing method of the wiring board 10 will be described in accordance with Figures 4 to 13. Here, the manufacturing methods of the via wiring 50V and wiring layer 82 of the wiring board 10 will be described in detail. For the sake of clarity, parts that will ultimately become components of the wiring board 10 will be denoted by the reference numerals of their final components.

[0059] First, as shown in Figure 4, a structure is prepared in which a wiring layer 32 is formed on the upper surface of the substrate body 11, and an insulating layer 40 covering the entire surface (top and side) of the wiring layer 32 is formed on the upper surface of the substrate body 11. Since this structure can be manufactured by known manufacturing methods, a detailed explanation is omitted here.

[0060] Next, in the process shown in Figure 5, a first through-hole 51 is formed in the insulating layer 40, exposing a portion of the upper surface of the wiring layer 32, and a second through-hole 52 is formed adjacent to the first through-hole 51, also exposing a portion of the upper surface of the wiring layer 32. These first and second through-holes 51 and 52 can be formed, for example, by irradiating the insulating layer 40 with laser light. In other words, the first and second through-holes 51 and 52 can be formed by a laser processing method. As a laser light source used for irradiating with laser light, for example, a CO2 laser or a UV-YAG laser can be used.

[0061] Here, the intensity (energy) of the laser beam irradiated onto the insulating layer 40 is set to a value sufficient to form a first through-hole 51 (or second through-hole 52) of a desired aperture diameter in one shot, i.e., one irradiation. For example, when forming a first through-hole 51 in an insulating layer 40 containing an inorganic filler, the laser beam with the energy necessary to form a first through-hole 51 in an insulating layer 40 without an inorganic filler is irradiated multiple times (e.g., three or more times). The laser beam used is the sum of the energy of these multiple laser beams, which is then used as the energy for a single irradiation.

[0062] When the insulating layer 40 is irradiated with laser light, the wiring layer 32 is heated by the energy of the laser light. This heat from the wiring layer 32 alters the portion 90 of the insulating layer 40 that is in contact with the upper surface of the wiring layer 32. Hereinafter, for the sake of explanation, the "portion 90" may be referred to as the "altered portion 90". Here, the heat from the wiring layer 32 is transmitted from the portion irradiated with laser light, that is, from the center of the first through hole 51 (or second through hole 52) to the periphery. Therefore, the altered portion 90 is thicker closer to the center of the first through hole 51 (or second through hole 52) and thinner further away from the center. Furthermore, the altered portion 90 is formed around the entire circumference of the first through hole 51 (or second through hole 52). Note that altering portion 90 of the insulating layer 40 includes, for example, thermal decomposition by carbonization of the resin contained in the insulating layer 40, and melting of the resin of the insulating layer 40.

[0063] Next, in the process shown in Figure 6, a first desmear treatment removes the resin smear (resin residue) adhering to the upper surface of the wiring layer 32 exposed at the bottom of the first through-hole 51 and the second through-hole 52. The first desmear treatment can be carried out using, for example, the permanganate method. The first desmear treatment removes a portion of the altered portion 90. Specifically, the first desmear treatment removes a portion of the altered portion 90 from the portion exposed on the first inner wall surface 55 of the first through-hole 51, and a portion of the altered portion 90 from the portion exposed on the second inner wall surface 65 of the second through-hole 52. As a result, the opening width at the bottom of the first through-hole 51 is widened, and the opening width at the bottom of the second through-hole 52 is widened.

[0064] Next, in the process shown in Figure 7, a second desmearing process, different from the first desmearing process, is performed to form a communication hole 53 that connects the bottom of the first through-hole 51 and the bottom of the second through-hole 52. The second desmearing process can be performed using, for example, a permanganate method. The processing conditions, such as the processing time, for the second desmearing process are set to be different from those for the first desmearing process. The second desmearing process in this step further widens the opening width at the bottom of the first through-hole 51 and the opening width at the bottom of the second through-hole 52. Specifically, the second desmearing process removes the remaining altered portion 90 (see Figure 6), thereby widening the opening width at the bottoms of the first through-hole 51 and the second through-hole 52. In this way, the communication hole 53 is formed by widening the opening width at the bottoms of the first through-hole 51 and the second through-hole 52. Furthermore, in this process, the remaining altered portion 90 (see Figure 6) is removed by the second desmear treatment, thereby forming a first recess 56 at the bottom of the first through hole 51 and a second recess 66 at the bottom of the second through hole 52.

[0065] Through the above manufacturing process, a through-hole 50 can be formed in the insulating layer 40, having a structure in which two adjacent first through-holes 51 and second through-holes 52 are connected through a communication hole 53. Next, in the process shown in Figure 8, a recess 33 communicating with the through-hole 50 is formed on the upper surface of the wiring layer 32 exposed through the through-hole 50 of the insulating layer 40. This recess 33 can be formed, for example, by etching the wiring layer 32 using the insulating layer 40 as an etching mask. The recess 33 is formed by connecting a first recess 34 and a second recess 35. The first recess 34 is formed, for example, on the upper surface of the wiring layer 32 exposed at the bottom of the first through-hole 51. The second recess 35 is formed, for example, on the upper surface of the wiring layer 32 exposed at the bottom of the second through-hole 52.

[0066] Next, in the process shown in Figure 9, a seed layer 70 is formed that continuously covers the entire upper surface of the insulating layer 40, the entire inner surface of the through hole 50, and the entire inner surface of the recess 33. The seed layer 70 can be formed, for example, by an electroless plating method. For example, the seed layer 70 can be formed by an electroless copper plating method using a plating solution which is a mixture of copper sulfate, sodium hydroxide, carboxylate, nickel sulfate, and formaldehyde.

[0067] Next, in the process shown in Figure 10, a resist layer 91 having an opening pattern 91X is formed on a seed layer 70 formed on the upper surface of the insulating layer 40. The opening pattern 91X is formed to expose the portion of the seed layer 70 corresponding to the formation areas of the wiring layer 82, i.e., the first wiring pattern 83 and the second wiring pattern 84 (see Figure 2). As the material for the resist layer 91, for example, a material that is resistant to plating in the subsequent electroplating process can be used. For example, as the material for the resist layer 91, a photosensitive dry film resist or a liquid photoresist (for example, a dry film resist or liquid resist such as a novolac resin or acrylic resin) can be used. For example, when using a photosensitive dry film resist, the dry film is laminated to the upper surface of the seed layer 70 by thermocompression, and the dry film is patterned by photolithography to form a resist layer 91 having an opening pattern 91X. Note that when using a liquid photoresist, the resist layer 91 can also be formed through a similar process.

[0068] Next, in the process shown in Figure 11, the resist layer 91 is used as a plating mask, and an electroplating method is applied to the seed layer 70, utilizing the seed layer 70 as a plating power supply layer. That is, an electroplating method (for example, electrolytic copper plating) is applied to the upper surface of the seed layer 70 exposed from the opening pattern 91X of the resist layer 91. In this process, a metal layer 71 is formed that fills the through holes 50 and recesses 33 inside the seed layer 70, and a metal layer 72 is formed within the opening pattern 91X. At this time, the metal layer 71 is formed to fill the first through hole 51 having a first recess 56, the second through hole 52 having a second recess 66, and the communication hole 53. The metal layer 72 is formed integrally with the metal layer 71.

[0069] Next, in the process shown in Figure 12, the resist layer 91 shown in Figure 11 is removed using an alkaline stripping solution (for example, an organic amine-based stripping solution, caustic soda, acetone, or ethanol).

[0070] Next, in the process shown in Figure 13, the metal layer 72 is used as an etching mask to remove the unwanted seed layer 70 by etching. If the seed layer 70 is an electroless copper plating layer, the unwanted seed layer 70 is removed by wet etching using a sulfuric acid-hydrogen peroxide-based etching solution.

[0071] Through the above manufacturing process, via wiring 50V consisting of a seed layer 70 and a metal layer 71 formed within the through-hole 50 and recess 33 is formed. In addition, wiring layer 82 consisting of a seed layer 70 and a metal layer 72 formed on the upper surface of the insulating layer 40 is formed.

[0072] Next, the effects and advantages of this embodiment will be explained. (1) The wiring board 10 has a wiring layer 32, an insulating layer 40 covering the upper surface of the wiring layer 32, and through holes 50 penetrating the insulating layer 40 in the thickness direction. The through holes 50 have a first through hole 51 penetrating the insulating layer 40 in the thickness direction and exposing a part of the upper surface of the wiring layer 32, and a second through hole 52 provided adjacent to the first through hole 51 and penetrating the insulating layer 40 in the thickness direction and exposing a part of the upper surface of the wiring layer 32. The through holes 50 have a communication hole 53 connecting the bottom of the first through hole 51 and the bottom of the second through hole 52. The wiring board 10 has via wiring 50V filling the first through hole 51, the second through hole 52 and the communication hole 53, and a wiring layer 82 formed integrally with the via wiring 50V and formed on the upper surface of the insulating layer 40.

[0073] In this configuration, by providing a communication hole 53 in the through hole 50, the two first through holes 51 and the second through hole 52 are connected through the communication hole 53. The bottom surface of the via wiring 50V is then joined to the upper surface of the wiring layer 32 exposed through the first through hole 51, the second through hole 52, and the communication hole 53. Therefore, compared to, for example, the case where the bottom surface of the via wiring 50V is joined to the upper surface of the wiring layer 32 exposed only through the first through hole 51, the bonding area between the bottom surface of the via wiring 50V and the wiring layer 32 can be increased. This improves the bonding strength between the via wiring 50V and the wiring layer 32, and improves the electrical connection reliability between the via wiring 50V and the wiring layer 32. Furthermore, because the bonding area between the via wiring 50V and the wiring layer 32 can be increased, even if thermal stress is applied to the interface between the via wiring 50V and the wiring layer 32 during reliability tests using thermal cycling, the thermal stress can be suitably distributed. This effectively suppresses the occurrence of cracks at the interface between the via wiring 50V and the wiring layer 32 due to thermal stress. As a result, the electrical connection reliability between the via wiring 50V and the wiring layer 32 can be improved.

[0074] (2) The wiring layer 32 is electrically connected to the wiring layer 82 through both the via wiring 50V filled in the first through hole 51 and the via wiring 50V filled in the second through hole 52. Therefore, even if a crack occurs at the interface between the via wiring 50V and the wiring layer 32 at the bottom of the first through hole 51, for example, the wiring layer 32 and the wiring layer 82 can be suitably electrically connected through the via wiring 50V filled in the second through hole 52. As a result, the reliability of the electrical connection between the via wiring 50V and the wiring layer 32 can be improved.

[0075] (3) Furthermore, the via wiring 50V in the portion that fills the communication hole 53 is formed to cover the lower surface of the insulating layer 40 that constitutes the inner surface of the communication hole 53. This makes it possible to form the via wiring 50V so that it partially overlaps with the insulating layer 40 in a plan view. Therefore, it is possible to effectively suppress the detachment of the via wiring 50V from the insulating layer 40.

[0076] (4) The communication hole 53 is formed to widen the opening width at the bottom of the first through hole 51 and also to widen the opening width at the bottom of the second through hole 52. With this configuration, the opening width at the bottom of the through hole 50 having the first through hole 51, the second through hole 52 and the communication hole 53 can be made larger, so the contact area between the bottom surface of the via wiring 50V and the wiring layer 32 can be suitably increased. As a result, the electrical connection reliability between the via wiring 50V and the wiring layer 32 can be improved.

[0077] (5) The communication hole 53 is formed in a shape in which the depth is smallest at the intermediate position in the first direction D1 where the first through hole 51 and the second through hole 52 are aligned. The communication hole 53 is formed such that the depth increases from the intermediate position toward the first through hole 51 in the first direction D1, and also such that the depth increases from the intermediate position toward the second through hole 52 in the first direction D1. With this configuration, the lower surface of the insulating layer 40 constituting the inner surface of the communication hole 53 is formed as an inclined surface that extends inclined with respect to the first direction D1. Therefore, compared to the case in which the lower surface of the insulating layer 40 constituting the inner surface of the communication hole 53 extends parallel to the first direction D1, the contact area between the lower surface of the insulating layer 40 and the via wiring 50V can be increased. This makes it possible to improve the adhesion strength between the insulating layer 40 and the via wiring 50V.

[0078] (6) The first through-hole 51 has a first inner wall surface 55 extending downward from the upper surface of the insulating layer 40 and a first recessed portion 56 that recesses outward from the first inner wall surface 55 toward the first through-hole 51. The second through-hole 52 has a second inner wall surface 65 extending downward from the upper surface of the insulating layer 40 and a second recessed portion 66 that recesses outward from the second inner wall surface 65 toward the second through-hole 52. The first recessed portion 56 is formed continuously around the entire circumference of the first through-hole 51. The second recessed portion 66 is formed continuously around the entire circumference of the second through-hole 52.

[0079] This configuration allows for a larger opening width at the bottom of the first through-hole 51 and also at the bottom of the second through-hole 52. As a result, a larger opening width can be formed at the bottom of the through-hole 50 having the first through-hole 51, the second through-hole 52, and the communication hole 53, thereby suitably increasing the contact area between the bottom surface of the via wiring 50V and the wiring layer 32. Consequently, the electrical connection reliability between the via wiring 50V and the wiring layer 32 can be improved.

[0080] (7) The upper surface of the wiring layer 32 is provided with a first recess 34 that communicates with the first through hole 51 and a second recess 35 that communicates with the second through hole 52. With this configuration, the contact area between the bottom surface of the via wiring 50V and the wiring layer 32 can be suitably increased compared to the case where the upper surface of the wiring layer 32 exposed from the through hole 50 extends parallel to the planar direction. As a result, the electrical connection reliability between the via wiring 50V and the wiring layer 32 can be improved.

[0081] (Other embodiments) The above embodiment can be implemented with the following modifications. The above embodiment and the following modifications can be combined with each other to the extent that they do not contradict each other technically.

[0082] The opening width of the first recess 34 in the above embodiment is not particularly limited. For example, the opening end of the first recess 34 may be positioned in a plan view at a location further from the plane center of the first through hole 51 than the first inner end 57 of the first recess 56. For example, the opening end of the first recess 34 may be positioned in a plan view at a location closer to the plane center of the first through hole 51 than the first inner end 57 of the first recess 56.

[0083] The opening width of the second recess 35 in the above embodiment is not particularly limited. For example, the opening end of the second recess 35 may be positioned in a plan view at a location further from the plane center of the second through hole 52 than the second inner end 67 of the second recess 66. For example, the opening end of the second recess 35 may be positioned in a plan view at a location closer to the plane center of the second through hole 52 than the second inner end 67 of the second recess 66.

[0084] As shown in Figure 14, the formation of the recess 33 in the wiring layer 32 may be omitted. That is, the formation of the first recess 34 and the second recess 35 in the wiring layer 32 may be omitted. In this case, the upper surface of the wiring layer 32 exposed at the bottom of the through hole 50 is formed as a flat surface, for example. In this case, the via wiring 50V is formed on the upper surface of the wiring layer 32 exposed at the bottom of the through hole 50. The via wiring 50V in this modified example is formed to fill only the through hole 50. In addition, the seed layer 70 in this modified example is formed to cover the entire inner surface of the through hole 50 and the entire upper surface of the wiring layer 32 exposed from the through hole 50.

[0085] In the above embodiment, a first wiring pattern 83 directly connected to the via wiring 50V filled in the first through hole 51, and a second wiring pattern 84 directly connected to the via wiring 50V filled in the second through hole 52, are provided on the upper surface of the insulating layer 40 so as to be separated from each other. In other words, two first wiring patterns 83 and second wiring patterns 84, which are electrically connected to the wiring layer 32 through the via wiring 50V, are provided on the upper surface of the insulating layer 40. However, the embodiment is not limited to this.

[0086] For example, as shown in Figure 15, a single wiring layer 82 may be provided on the upper surface of the insulating layer 40, which is electrically connected to the wiring layer 32 through via wiring 50V. That is, a wiring layer 82 may be provided on the upper surface of the insulating layer 40 that is directly connected to both the via wiring 50V filled in the first through hole 51 and the via wiring 50V filled in the second through hole 52. In other words, the via wiring 50V filled in the first through hole 51 and the via wiring 50V filled in the second through hole 52 may be directly connected to a common wiring layer 82. In this modified example, the wiring layer 82 is formed to connect the upper surface of the via wiring 50V filled in the first through hole 51 and the upper surface of the via wiring 50V filled in the second through hole 52.

[0087] As shown in Figure 16, the wiring layer 82 in this modified example is formed to overlap the entire first through-hole 51 in a plan view, and also to overlap the entire second through-hole 52 in a plan view. The wiring layer 82 in this modified example is formed to overlap the entire communication hole 53 in a plan view. The wiring layer 82 in this modified example is formed to extend, for example, in the first direction D1 where the first through-hole 51 and the second through-hole 52 are aligned. The planar shape of the wiring layer 82 in this modified example is formed as an elongated oval shape in the first direction D1.

[0088] In the above embodiment, the wiring layer 32 is embodied in a plane layer, but the embodiment is not limited to this. For example, the wiring layer 32 may be embodied in a signal wiring. For example, as shown in Figure 16, the wiring layer 32 may be changed to a signal wiring configuration having a pad 37 connected to the wiring layer 82 and a circuit pattern 38 connected to the pad 37. In this modified wiring layer 32, for example, the pad 37 and the circuit pattern 38 are formed continuously and integrally. In this case, the through-hole 50 is formed to expose a part of the upper surface of the pad 37. Specifically, the first through-hole 51 is formed to expose a part of the upper surface of the pad 37, and the second through-hole 52 is formed to expose a part of the upper surface of the pad 37.

[0089] In the above embodiment, the via wiring 50V is embodied as a via wiring connecting the outermost wiring layer 82 and the wiring layer 32 located in an inner layer of the wiring layer 82, but the embodiment is not limited to this.

[0090] For example, as shown in Figure 17, a via wiring V1 connecting a wiring layer 92 located in an inner layer of the outermost wiring layer 82 and a wiring layer 32 located in an inner layer of the wiring layer 92 may be formed in the same structure as the via wiring 50V. The via wiring V1 is formed to penetrate the insulating layer 93 that covers the upper surface of the wiring layer 32. The via wiring V1 is formed continuously and integrally with the wiring layer 92. The via wiring V1 is formed to fill a through-hole 94 that penetrates the insulating layer 93 in the thickness direction. The through-hole 94, like the through-hole 50, has a first through-hole 51, a second through-hole 52, and a communication hole 53.

[0091] In the manufacturing method of the wiring board 10 of the above embodiment, after forming the first through hole 51 and the second through hole 52, a communication hole 53 connecting the first through hole 51 and the second through hole 52 is formed by performing two desmear treatments. However, the method is not limited to this. For example, after forming the first through hole 51 and the second through hole 52, a communication hole 53 connecting the first through hole 51 and the second through hole 52 may be formed by performing one desmear treatment. Furthermore, the method for forming the communication hole 53 is not limited to desmear treatment.

[0092] In the above embodiment of the manufacturing method for the wiring board 10, the first through-hole 51 and the second through-hole 52 are formed by laser processing, but the method is not limited to this. For example, the first through-hole 51 and the second through-hole 52 may be formed by a method other than laser processing.

[0093] The first inner wall surface 55 of the first through hole 51 in the above embodiment may be formed so as to extend perpendicularly to the upper surface of the insulating layer 40 in a cross-sectional view. The second inner wall surface 65 of the second through hole 52 in the above embodiment may be formed so as to extend perpendicularly to the upper surface of the insulating layer 40 in a cross-sectional view.

[0094] In the above embodiment, the seed layer 70 is embodied as a single-layer seed layer, but the seed layer 70 may also be embodied as a multi-layer seed layer (for example, a two-layer structure). An example of a two-layer seed layer 70 is a seed layer having a structure in which a titanium (Ti) layer and a Cu layer are stacked in order.

[0095] The structure of the wiring board 10 in the above embodiment can be modified as appropriate. The wiring board 10 is not particularly limited to any other structure as long as it has a structure having, for example, a wiring layer 32, an insulating layer 40, through holes 50, via wiring 50V, and a wiring layer 82. The wiring board 10 may have, for example, a core substrate or it may be a coreless substrate without a core substrate.

[0096] The wiring board 10 of the above embodiment may be implemented as a wiring board used in packages such as CSP (Chip Size Package) or SON (Small Outline Non-Lead Package). [Explanation of symbols]

[0097] 10 Wiring board 32 Wiring layer (1st wiring layer) 33 Recess 34. First recess 35 Second recess 40 Insulating layer 50 Through holes 50V via wiring 51 First through hole 52 Second through hole 53 Communication hole 55 First Inner Wall Surface 56 First depression 57 1st back end 58 First Inner Surface 65 Second inner wall surface 66 Second depression 67 2nd rear end 68 Second Inner Self 70 seed layer 71 Metal layer 72 Metal layer 82 Wiring layer (2nd wiring layer) 92 Wiring layer 93 Insulating layer 94 Through holes D1 1st direction D2 2nd direction V1 via wiring

Claims

1. The first wiring layer and An insulating layer covering the upper surface of the first wiring layer, A first through-hole penetrates the insulating layer in the thickness direction and exposes a portion of the upper surface of the first wiring layer, A second through-hole is provided adjacent to the first through-hole and penetrates the insulating layer in the thickness direction, exposing a portion of the upper surface of the first wiring layer, A communication hole connecting the bottom of the first through hole and the bottom of the second through hole, Via wiring that fills the first through hole, the second through hole, and the communication hole, It has a second wiring layer formed integrally with the via wiring and formed on the upper surface of the insulating layer, The first wiring layer is, A first recess is provided on the upper surface of the first wiring layer exposed through the first through hole, It has a second recess provided on the upper surface of the first wiring layer that is exposed from the second through hole, The communication hole is formed to communicate with the first recess and also with the second recess. The first recess is formed in a continuous manner with the second recess on the wiring board.

2. The wiring board according to claim 1, wherein the communication hole is formed to widen the opening width at the bottom of the first through hole and to widen the opening width at the bottom of the second through hole.

3. The communication hole is formed such that the depth at the intermediate position in the first direction where the first through hole and the second through hole are aligned is the smallest. The wiring board according to claim 1, wherein the communication holes are formed such that their depth increases from the intermediate position toward the first through-hole in the first direction, and their depth increases from the intermediate position toward the second through-hole in the first direction.

4. The first through-hole has a first inner wall surface extending downward from the upper surface of the insulating layer, and a first recess that extends outward from the first inner wall surface towards the first through-hole. The second through-hole has a second inner wall surface extending downward from the upper surface of the insulating layer, and a second recess that extends outward from the second inner wall surface towards the second through-hole. The wiring board according to claim 1, wherein the communication hole is formed by a part of the first recess and a part of the second recess communicating with each other.

5. The first recess is formed continuously around the entire circumference of the first through hole. The second recess is formed continuously around the entire circumference of the second through hole. The wiring board according to claim 4, wherein the communication hole is formed such that a part of the circumferential direction of the first recess and a part of the circumferential direction of the second recess communicate with each other.

6. The via wiring is A seed layer covering the first inner wall surface of the first through hole, the second inner wall surface of the second through hole, the lower surface of the insulating layer constituting the inner surface of the communication hole, and the upper surface of the first wiring layer exposed from the first through hole, the second through hole, and the communication hole, The wiring board according to claim 1, further comprising a metal layer filling the first through hole located inside the seed layer, the second through hole located inside the seed layer, and the communication hole located inside the seed layer.

7. A step of forming an insulating layer that covers the first wiring layer, The process of forming a first through-hole in the insulating layer that exposes a portion of the upper surface of the first wiring layer, and a second through-hole provided adjacent to the first through-hole that also exposes a portion of the upper surface of the first wiring layer, A step of forming a communication hole that connects the bottom of the first through hole and the bottom of the second through hole, The process includes the steps of forming via wiring to fill the first through hole, the second through hole, and the communication hole, and forming a second wiring layer which is formed integrally with the via wiring and provided on the upper surface of the insulating layer, After the step of forming the communication hole, and before the step of forming the via wiring and the second wiring layer, The process further includes forming a recess on the upper surface of the first wiring layer exposed through the first through hole, the second through hole, and the communication hole, The via wiring is formed to fill the recess in the wiring board.

8. In the step of forming the first through hole and the second through hole, the first through hole and the second through hole are formed by a laser processing method. The process of forming the aforementioned communication hole is as follows: The first desmear treatment widens the opening width at the bottom of the first through hole, and the second desmear treatment widens the opening width at the bottom of the second through hole, A method for manufacturing a wiring board according to claim 7, comprising the step of forming the communication hole by further widening the opening width at the bottom of the first through hole and further widening the opening width at the bottom of the second through hole by a second desmear treatment different from the first desmear treatment.

Images