Semiconductor equipment

Abstract

To improve the performance of a semiconductor device.SOLUTION: The semiconductor device comprises: two die pads DPL, DPH adjacent to each other in a direction Y; a first semiconductor chip CPL and a third semiconductor chip CPC that are arranged on one die pad DPH and adjacent to each other in a direction X; and a second semiconductor chip CPH that is located on the other die pad DPL. The third semiconductor chip CPC includes one or more transformers TR1 for transmission for propagating a signal from the first semiconductor chip CPL to the second semiconductor chip CPH, and one or more transformers TR2, TR3 for reception for propagating a signal from the second semiconductor chip CPH to the first semiconductor chip CPL. The plurality of transformers TR1, TR2, TR3 are arranged along a side CPCb facing the second semiconductor chip CPH in a plan view, and the transformer TR1 for transmission is located closer to the first semiconductor chip CPL than the transformers TR2, TR3 for reception.SELECTED DRAWING: Figure 17

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and can be suitably used, for example, in a semiconductor device incorporating a plurality of semiconductor chips.

Background Art

[0002] A semiconductor device in the form of a semiconductor package can be manufactured by mounting a semiconductor chip on a die pad, electrically connecting the pad electrode of the semiconductor chip and a lead via a wire, and resin-sealing them.

[0003] WO 2015 / 114758 (Patent Document 1) describes a technique for transmitting an electrical signal by inductively coupling two coils in a semiconductor chip.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a semiconductor device incorporating three semiconductor chips and using magnetically coupled coils in one of the other two semiconductor chips to transmit signals between the two semiconductor chips, it is desirable to improve the performance.

[0006] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0007] According to one embodiment, the semiconductor device comprises a first chip mounting section, a second chip mounting section, a first semiconductor chip mounted on the first chip mounting section, a second semiconductor chip mounted on the second chip mounting section, a third semiconductor chip mounted on the first chip mounting section and having a plurality of transformers, and a encapsulant that encapsulates them. The first chip mounting section and the second chip mounting section are adjacent to each other in a first direction, and the first semiconductor chip and the third semiconductor chip are adjacent to each other in a second direction orthogonal to the first direction. The plurality of transformers are arranged along the edge facing the second semiconductor chip in a plan view. The first semiconductor chip has a plurality of first transmitting pads electrically connected to a first transmitting circuit formed within the first semiconductor chip, and a plurality of first receiving pads electrically connected to a first receiving circuit formed within the first semiconductor chip. The second semiconductor chip includes a plurality of second transmitting pads electrically connected to a second transmitting circuit formed within the second semiconductor chip, and a plurality of second receiving pads electrically connected to a second receiving circuit formed within the second semiconductor chip. The plurality of transformers of the third semiconductor chip have one or more first transformers used for transmitting signals from the first semiconductor chip to the second semiconductor chip, and one or more second transformers used for transmitting signals from the second semiconductor chip to the first semiconductor chip. The primary coils of the one or more first transformers are electrically connected to the plurality of first transmitting pads of the first semiconductor chip, and the secondary coils of the one or more first transformers are electrically connected to the plurality of second receiving pads of the second semiconductor chip. The primary coils of the one or more second transformers are electrically connected to the plurality of second transmitting pads of the second semiconductor chip, and the secondary coils of the one or more second transformers are electrically connected to the plurality of first receiving pads of the first semiconductor chip. In a plan view, the one or more first transformers are positioned closer to the first semiconductor chip than the one or more second transformers. The plurality of first transmitting pads are positioned closer to the second semiconductor chip than the plurality of first receiving pads in a plan view. [Effects of the Invention]

[0008] According to one embodiment, the performance of the semiconductor device can be improved. Furthermore, the semiconductor device can be miniaturized. [Brief explanation of the drawing]

[0009] [Figure 1] This is a circuit diagram showing an inverter circuit using a semiconductor device of one embodiment. [Figure 2] This is a top view of a semiconductor device according to one embodiment. [Figure 3] This is a plan view of a semiconductor device according to one embodiment. [Figure 4] This is a plan view of a semiconductor device according to one embodiment. [Figure 5] This is a plan view of a semiconductor device according to one embodiment. [Figure 6] This is a bottom view of a semiconductor device according to one embodiment. [Figure 7] This is a cross-sectional view of a semiconductor device according to one embodiment. [Figure 8] This is a cross-sectional view of a semiconductor device according to one embodiment. [Figure 9] This is a cross-sectional view of a semiconductor device according to one embodiment. [Figure 10] This is a plan view of the manufacturing process of a semiconductor device according to one embodiment. [Figure 11] Figure 10 is a plan view of the manufacturing process of a semiconductor device. [Figure 12] This is a plan view of the manufacturing process of a semiconductor device, following Figure 11. [Figure 13] This is a plan view of the manufacturing process of a semiconductor device, following Figure 12. [Figure 14] This is a cross-sectional view of the same semiconductor device during the manufacturing process as Figure 13. [Figure 15] This is a cross-sectional view of the same semiconductor device during the manufacturing process as Figure 13. [Figure 16] This is a planar perspective view showing an enlarged portion of a semiconductor device according to one embodiment. [Figure 17]It is a plan perspective view of enlarging a part of a semiconductor device according to an embodiment. [Figure 18] It is a cross-sectional view schematically showing a semiconductor chip in a semiconductor device according to an embodiment. [Figure 19] It is a cross-sectional view schematically showing a semiconductor chip in a semiconductor device according to an embodiment. [Figure 20] It is a cross-sectional view schematically showing a semiconductor chip in a semiconductor device according to an embodiment. [Figure 21] It is a plan perspective view of a semiconductor device of a study example. [Figure 22] It is an explanatory view of a semiconductor device of the first modification example. [Figure 23] It is an explanatory view of a semiconductor device of the second modification example. [Figure 24] It is an explanatory view of a semiconductor device of the second modification example. [Figure 25] It is an explanatory view of a semiconductor device of the second modification example. [Figure 26] It is a circuit diagram showing an inverter circuit using a semiconductor device of another embodiment. [Figure 27] It is a plan perspective view of enlarging a part of a semiconductor device of another embodiment. [Figure 28] It is a plan perspective view of enlarging a part of a semiconductor device of another embodiment.

Embodiments for Carrying Out the Invention

[0010] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. Unless otherwise specified, these are not unrelated, and one may be a modification, detail, or supplementary explanation of part or all of the other. Furthermore, when referring to the number of elements, etc. (including number, numerical value, quantity, range, etc.) in the following embodiments, unless otherwise specified or clearly limited to a specific number in principle, it is not limited to that specific number, and may be greater than or less than that number. Moreover, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified or clearly considered essential in principle. Similarly, when referring to the shape, positional relationship, etc. of constituent elements, etc. in the following embodiments, unless otherwise specified or clearly considered not to be so in principle, it shall include those that substantially approximate or resemble that shape, etc. The same applies to the numerical values ​​and ranges mentioned above.

[0011] The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless it is particularly necessary.

[0012] Furthermore, in the drawings used in the embodiments, hatching may be omitted even in cross-sectional views to improve readability. Conversely, hatching may be added to plan views to improve readability.

[0013] (Embodiment 1) <Regarding the circuit configuration> Figure 1 is a circuit diagram showing an inverter circuit using the semiconductor device PKG of this embodiment. In Figure 1, the area enclosed by the dotted line labeled CPH is formed within the semiconductor chip CPH, the area enclosed by the dotted line labeled CPL is formed within the semiconductor chip CPL, the area enclosed by the dotted line labeled CPC is formed within the semiconductor chip CPC, and the area enclosed by the dashed line labeled PKG is formed within the semiconductor device PKG. Two semiconductor device PKGs are used in the inverter circuit shown in Figure 1. In Figure 1, for the sake of simplicity, the circuit configuration of the semiconductor device PKG connected to power transistor TS2 is omitted, but the circuit configuration of the semiconductor device PKG connected to power transistor TS2 is basically the same as the circuit configuration of the semiconductor device PKG connected to power transistor TS1.

[0014] The semiconductor device package used in the inverter circuit shown in Figure 1 comprises semiconductor chips CPC, CPL, and CPH. Within the semiconductor chip CPL, there are transmitting circuits TX1, RX2, and RX3. Within the semiconductor chip CPH, there are receiving circuits RX1, TX2, TX3, and a drive circuit (control circuit) DR. Within the semiconductor chip CPC, there are transformers TR1 consisting of magnetically coupled coils L1a and L1b, transformers TR2 consisting of magnetically coupled coils L2a and L2b, and transformers TR3 consisting of magnetically coupled coils L3a and L3b. Since receiving circuits RX2 and RX3 are formed on the same semiconductor chip CPL, the entire combination of receiving circuits RX2 and RX3 can be considered as a single receiving circuit. Similarly, since transmitting circuits TX2 and TX3 are formed on the same semiconductor chip CPH, the entire combination of transmitting circuits TX2 and TX3 can be considered as a single transmitting circuit. Furthermore, the inverter circuit shown in Figure 1 also includes a control circuit CC, which is formed within a separate semiconductor chip located outside the semiconductor package PKG.

[0015] The transmitting circuit TX1 and receiving circuit RX1 are circuits for transmitting signals from the control circuit CC to the drive circuit DR. The transmitting circuit TX1 converts the signal sent from the control circuit CC to the transmitting circuit TX1 and transmits it to the receiving circuit RX1 via transformer TR1. The receiving circuit RX1 converts the signal received from the transmitting circuit TX1 via transformer TR1 and transmits it to the drive circuit DR. The transmitting circuit TX2 and receiving circuit RX2 are circuits for transmitting signals from the drive circuit DR to the control circuit CC. The transmitting circuit TX2 converts the signal sent from the drive circuit DR to the transmitting circuit TX2 and transmits it to the receiving circuit RX2 via transformer TR2. The receiving circuit RX2 converts the signal received from the transmitting circuit TX2 via transformer TR2 and transmits it to the control circuit CC. The transmitting circuit TX3 and receiving circuit RX3 are circuits for transmitting signals from the drive circuit DR to the control circuit CC. The transmitting circuit TX3 converts the signal sent from the drive circuit DR to the transmitting circuit TX3 and transmits it to the receiving circuit RX3 via transformer TR3. The receiving circuit RX3 converts the signal received from the transmitting circuit TX3 via the transformer TR3 and transmits it to the control circuit CC.

[0016] The inverter circuit shown in Figure 1 has power transistors TS1 and TS2. Power transistor TS1 is a high-side switch (high-potential switch), and power transistor TS2 is a low-side switch (low-potential switch). Power transistors TS1 and TS2 are each formed in separate semiconductor chips located outside the semiconductor package (PKG).

[0017] The following describes the case where power transistors TS1 and TS2 are power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). IGBTs (Insulated Gate Bipolar Transistors) can also be used as power transistors TS1 and TS2; in that case, in the following descriptions of power transistors TS1 and TS2, simply replace "source" with "emitter" and "drain" with "collector".

[0018] Furthermore, in this application, the term MOSFET includes not only MISFETs (Metal Insulator Semiconductor Field Effect Transistors) that use an oxide film (silicon oxide film) as the gate insulating film, but also MISFETs that use insulating films other than oxide films as the gate insulating film.

[0019] Power transistors TS1 and TS2 are connected in series, with the source (S1) of power transistor TS1 connected to the drain (D2) of power transistor TS2. Power potential (voltage) V1 is supplied to the drain (D1) of power transistor TS1 from the power supply (battery) BT1. Power potential (voltage) V2 is supplied to the control circuit CC from the power supply (battery) BT2. The power potential V1 supplied to the drain (D1) of power transistor TS1 is considerably higher than the power potential V2 supplied to the control circuit CC (e.g., several volts to tens of volts), for example, 100V or more (several hundred volts). A reference potential lower than the power potential V1, such as ground potential (GND), is supplied to the source (S2) of power transistor TS2. The gates (G1) of power transistor TS1 and (G2) of power transistor TS2 are each connected to the drive circuit DR.

[0020] In this embodiment, the same number of semiconductor device packages (PKGs) as the number of power transistors TS1 and TS2 are used. In this case, the drive circuit DR of the semiconductor device package provided for power transistor TS1 controls the voltage of the gate (G1) of power transistor TS1, and the drive circuit DR of the semiconductor device package provided for power transistor TS2 controls the voltage of the gate (G2) of power transistor TS2. In another configuration, one semiconductor device package may be used for two power transistors TS1 and TS2. In that case, the drive circuit DR of the common semiconductor device package controls the voltages of the gates (G1, G2) of the two power transistors TS1 and TS2.

[0021] The operation of power transistors TR1 and TR2 can be controlled by controlling the gate voltage supplied from the drive voltage DR to the gates (G1, G2) of each power transistor TS1 and TS2 in accordance with the signal (control signal) supplied from the control circuit CC to the drive circuit via the transmit circuit TX1, transformer TR1, and receive circuit RX1.

[0022] Terminal T1, located between the source (S1) of power transistor TS1 and the drain (D2) of power transistor TS2, is the output terminal of the inverter circuit. Terminal T1 is connected to the load LOD. The load LOD is, for example, the coil of a motor. The DC power supplied to the inverter circuit is converted to AC power by the inverter circuit and supplied to the load LOD.

[0023] A transformer TR1 is interposed between the transmitting circuit TX1 and the receiving circuit RX1, a transformer TR2 is interposed between the transmitting circuit TX2 and the receiving circuit RX2, and a transformer TR3 is interposed between the transmitting circuit TX3 and the receiving circuit RX3. The control circuit CC can transmit signals (control signals) to the drive circuit DR via the transmitting circuit TX1, transformer TR1, and receiving circuit RX1. The drive circuit DR can transmit signals to the control circuit CC via the transmitting circuit TX2, transformer TR2, and receiving circuit RX2, and the drive circuit DR can also transmit signals to the control circuit CC via the transmitting circuit TX3, transformer TR3, and receiving circuit RX3. Coils L1a, L1b, L2a, L2b, L3a, and L3b can each be considered as inductors.

[0024] Transformer TR1 is formed by coils L1a and L1b formed within the semiconductor chip CPC. However, coils L1a and L1b are not connected by a conductor, but are magnetically coupled to each other. Therefore, when current flows through coil L1a, an induced electromotive force is generated in coil L1b in response to the change in that current, causing an induced current to flow. Coil L1a is the primary coil, and coil L1b is the secondary coil. By utilizing this, a signal is sent from the transmitting circuit TX1 to coil L1a (primary coil) of transformer TR1 to cause a current to flow, and the induced current (or induced electromotive force) generated in coil L1b (secondary coil) of transformer TR1 is detected (received) by the receiving circuit RX1. In this way, the receiving circuit RX1 can receive a signal corresponding to the signal sent by the transmitting circuit TX1.

[0025] Furthermore, the transformer TR2 is formed by coils L2a and L2b formed within the semiconductor chip CPC. However, coils L2b and L2a are not connected by a conductor, but are magnetically coupled to each other. Therefore, when current flows through coil L2b, an induced electromotive force is generated in coil L2a in response to the change in that current, causing an induced current to flow. Coil L2b is the primary coil, and coil L2a is the secondary coil. By utilizing this, a signal is sent from the transmitting circuit TX2 to coil L2b (primary coil) of the transformer TR2, causing a current to flow. The induced current (or induced electromotive force) generated in coil L2a (secondary coil) of the transformer TR2 is detected (received) by the receiving circuit RX2, thereby allowing the receiving circuit RX2 to receive a signal corresponding to the signal sent by the transmitting circuit TX2.

[0026] Furthermore, the transformer TR3 is formed by coils L3a and L3b formed within the semiconductor chip CPC. However, coils L3b and L3a are not connected by a conductor, but are magnetically coupled to each other. Therefore, when current flows through coil L3b, an induced electromotive force is generated in coil L3a in response to the change in that current, causing an induced current to flow. Coil L3b is the primary coil, and coil L3a is the secondary coil. By utilizing this, a signal is sent from the transmitting circuit TX3 to coil L3b (primary coil) of the transformer TR3 to cause a current to flow, and the induced current (or induced electromotive force) generated in coil L3a (secondary coil) of the transformer TR3 is detected (received) by the receiving circuit RX3. In this way, the receiving circuit RX3 can receive a signal corresponding to the signal sent by the transmitting circuit TX3.

[0027] Signals can be transmitted between semiconductor chip CPL and semiconductor chip CPH via the following paths: from transmitting circuit TX1 through transformer TR1 to receiving circuit RX1; from transmitting circuit TX2 through transformer TR2 to receiving circuit RX2; and from transmitting circuit TX3 through transformer TR3 to receiving circuit RX3.

[0028] The semiconductor chip CPL and semiconductor chip CPH have different voltage levels. For example, the semiconductor chip CPL is electrically connected to a low-voltage region that has circuits (e.g., control circuit CC) that operate or are driven at low voltages (e.g., a few volts to tens of volts) via wire BW and lead LD (specifically lead LD2), as described later. The semiconductor chip CPH is electrically connected to a high-voltage region that has circuits (e.g., power transistors TS1, TS2) that operate or are driven at voltages higher than the low voltage (e.g., 100V or higher) via wire BW and lead LD (specifically lead LD1), as described later. However, since the transmission of signals between the semiconductor chip CPL and CPH is mediated by transformers TR1, TR2, and TR3, signal transmission between circuits with different voltages is possible.

[0029] Note that while Figure 1 shows the case where the control circuit CC is integrated into a semiconductor chip other than the semiconductor chip CPC, CPH, or CPL, it is also possible to integrate the control circuit CC into the semiconductor chip CPL.

[0030] <About the structure of semiconductor devices> Figure 2 is a top view of the semiconductor device package of this embodiment, Figures 3 to 5 are plan perspective views of the semiconductor device package, Figure 6 is a bottom view (back view) of the semiconductor device package, and Figures 7 to 9 are cross-sectional views of the semiconductor device package. Figure 3 shows a plan perspective view of the top side of the semiconductor device package when the sealing portion MR is viewed through. Figure 4 shows a plan perspective view of the top side of the semiconductor device package when the wire BW is viewed through (omitted) in Figure 3. Figure 5 shows a plan perspective view of the top side of the semiconductor device package when the semiconductor chips CPC, CPH, and CPL are viewed through (omitted) in Figure 4. In Figures 3 to 5, the position of the outer periphery of the sealing portion MR is indicated by a dotted line. Furthermore, the cross-sectional view of the semiconductor device package at the position of line A1-A1 in Figures 2 and 3 roughly corresponds to Figure 7, the cross-sectional view of the semiconductor device package at the position of line A2-A2 in Figures 2 and 3 roughly corresponds to Figure 8, and the cross-sectional view of the semiconductor device package at the position of line A3-A3 in Figures 2 and 3 roughly corresponds to Figure 9. Also, Figures 2 to 6 show the X and Y directions. Here, the X and Y directions are directions that intersect each other, or more specifically, directions that are orthogonal to each other.

[0031] The semiconductor device (semiconductor package) PKG of this embodiment, shown in Figures 2 to 9, is a resin-encapsulated semiconductor package, and in this case, it is a Small Outline Package (SOP) type semiconductor device. The configuration of the semiconductor device PKG will be described below with reference to Figures 2 to 9.

[0032] The semiconductor device package of this embodiment, shown in Figures 2 to 9, includes three semiconductor chips CPC, CPH, and CPL, a die pad DPL on which two semiconductor chips CPC and CPL are mounted, a die pad DPH on which one semiconductor chip CPH is mounted, a plurality of wires (bonding wires) BW, a plurality of leads LD, and a sealing portion MR that seals these together.

[0033] The sealing portion MR, as a sealant, is made of a resin material such as a thermosetting resin material, and may also contain fillers. For example, the sealing portion MR can be formed using an epoxy resin containing fillers.

[0034] The sealing portion MR has an upper surface MRa, which is one of its main surfaces; a lower surface (back surface, bottom surface) MRb, which is the main surface opposite to the upper surface MRa; and sides MRc1, MRc2, MRc3, and MRc4 that intersect the upper surface MRa and the lower surface MRb. Sides MRc1 and MRc3 are approximately parallel to the X direction, and sides MRc2 and MRc4 are approximately parallel to the Y direction. In the sealing portion MR, side MRc1 and side MRc3 are located on opposite sides of each other, side MRc2 and side MRc4 are located on opposite sides of each other, side MRc1 intersects with side MRc2 and MRc4, and side MRc3 intersects with side MRc2 and MRc4. In addition, the upper surface MRa and the lower surface MRb are surfaces that are parallel to both the X and Y directions. The planar shape of the sealing portion MR, that is, the planar shapes of the upper surface MRa and the lower surface MRb of the sealing portion MR, is, for example, rectangular. The sealing portion MR has a corner KD1 where the sides MRc1 and MRc2 of the sealing portion MR intersect, a corner KD2 where the sides MRc2 and MRc3 of the sealing portion MR intersect, a corner KD3 where the sides MRc3 and MRc4 of the sealing portion MR intersect, and a corner KD4 where the sides MRc4 and MRc1 of the sealing portion MR intersect.

[0035] Each of the multiple lead LDs in the semiconductor device package is partially sealed within a sealing portion MR, while the other portion protrudes from the side of the sealing portion MR to the outside. Hereinafter, the portion of the lead LD located within the sealing portion MR will be referred to as the inner lead portion, and the portion of the lead LD located outside the sealing portion MR will be referred to as the outer lead portion. A plating layer (not shown), such as a solder plating layer, can also be formed on the outer lead portion of the lead LD.

[0036] In this embodiment, the semiconductor device package has a structure in which a portion of each lead LD (outer lead portion) protrudes from the side surface of the sealing portion MR. The following description will be based on this structure, but the package is not limited to this structure. For example, a configuration in which each lead LD hardly protrudes from the side surface of the sealing portion MR, and a portion of each lead LD is exposed on the lower surface MRb of the sealing portion MR (SON (Small Outline Nonleaded Package) type configuration) can also be adopted.

[0037] The multiple lead LDs in the semiconductor device package consist of multiple lead LDs arranged on the MRc1 side of the sealing portion MR and multiple lead LDs arranged on the MRc3 side of the sealing portion MR. In the case of Figures 2 to 9, no lead LDs are arranged on the MRc2 and MRc4 sides of the sealing portion MR. Hereafter, the lead LDs arranged on the MRc1 side of the sealing portion MR will be referred to as lead LD1, denoted by the symbol LD1. Similarly, the lead LDs arranged on the MRc3 side of the sealing portion MR will be referred to as lead LD2, denoted by the symbol LD2.

[0038] The outer leads of the multiple lead LDs located on the side MRc1 of the sealing portion MR protrude from the side MRc1 to the outside of the sealing portion MR. Similarly, the outer leads of the multiple lead LDs located on the side MRc3 of the sealing portion MR protrude from the side MRc3 to the outside of the sealing portion MR. The outer leads of each lead LD are bent so that the lower surface near the end of the outer lead is approximately flush with the lower surface MRb of the sealing portion MR. The outer leads of the lead LDs function as external connection terminals (external terminals) for the semiconductor device package.

[0039] The die pad DPL is a chip mounting area on which two semiconductor chips CPC and CPL are mounted, and the die pad DPH is a chip mounting area on which a semiconductor chip CPH is mounted. The die pads DPH and DPL are spaced apart in the Y direction, and a part of the sealing section MR is interposed between them. Of the die pads DPH and DPL, the die pad DPH is positioned closer to the side surface MRc1 of the sealing section MR, and the die pad DPL is positioned closer to the side surface MRc3 of the sealing section MR. That is, in the Y direction, the die pad DPH is positioned between the die pad DPL and the side surface MRc1 of the sealing section MR, and the die pad DPL is positioned between the die pad DPH and the side surface MRc3 of the sealing section MR. Each die pad DPH and DPL is sealed within the sealing section MR and is not exposed from the sealing section MR. That is, the die pads DPH and DPL are not exposed on the upper surface MRa and the lower surface MRb of the sealing section MR.

[0040] The die pads DPH, DPL and the multiple leads LD are made of a conductor, preferably a metallic material such as copper (Cu) or a copper alloy. Furthermore, it is preferable that the die pads DPH, DPL and the multiple leads LD are made of the same material (same metallic material), which makes it easier to fabricate the lead frame LF described later, in which the die pads DPH, DPL and the multiple leads LD are connected, and facilitates the manufacture of semiconductor device packages using the lead frame LF.

[0041] The die pad DPH has an upper surface DPHa, which is the main surface on which the semiconductor chip CPC,CPH is mounted; a lower surface (back surface) DPHb, which is the main surface on the opposite side; and side surfaces DPHc1, DPHc2, DPHc3, and DPHc4 that intersect the upper surface DPHa and the lower surface DPHb. In the die pad DPH, side surface DPHc1 is the side surface located on the side surface MRc1 of the sealing portion MR; side surface DPHc2 is the side surface located on the side surface MRc2 of the sealing portion MR; side surface DPHc3 is the side surface located on the side surface MRc3 of the sealing portion MR; and side surface DPHc4 is the side surface located on the side surface MRc4 of the sealing portion MR. In the die pad DPH, side DPHc1 and side DPHc3 are located on opposite sides of each other, side DPHc2 and side DPHc4 are located on opposite sides of each other, side DPHc1 intersects with side DPHc2 and DPHc4, and side DPHc3 intersects with side DPHc2 and DPHc4.

[0042] Furthermore, the die pad DPL has an upper surface DPLa, which is the main surface on which the semiconductor chip CPL is mounted, a lower surface (back surface) DPLb, which is the main surface on the opposite side, and side surfaces DPLc1, DPLc2, DPLc3, and DPLc4 that intersect the upper surface DPLa and the lower surface DPLb. In the die pad DPL, side surface DPLc1 is the side surface located on the side surface MRc1 side of the sealing portion MR, side surface DPLc2 is the side surface located on the side surface MRc2 side of the sealing portion MR, side surface DPLc3 is the side surface located on the side surface MRc3 side of the sealing portion MR, and side surface DPLc4 is the side surface located on the side surface MRc4 side of the sealing portion MR. In the die pad DPL, side surfaces DPLc1 and DPLc3 are located on opposite sides of each other, side surfaces DPLc2 and DPLc4 are located on opposite sides of each other, side surface DPLc1 intersects with side surfaces DPLc2 and DPLc4, and side surface DPLc3 intersects with side surfaces DPLc2 and DPLc4. The side surface DPHc3 of the die pad DPH and the side surface DPLc1 of the die pad DPL face each other via a portion of the sealing portion MR.

[0043] The sides DPHc1 and DPHc3 of die pad DPH and the sides DPLc1 and DPLc3 of die pad DPL are approximately parallel to the X direction, and the sides DPHc2 and DPHc4 of die pad DPH and the sides DPLc2 and DPLc4 of die pad DPL are approximately parallel to the Y direction. The upper surface DPHa and lower surface DPHb of die pad DPH and the upper surface DPLa and lower surface DPLb of die pad DPL are planes that are approximately parallel to both the X and Y directions. The planar shapes of die pads DPH and DPL are, for example, rectangular.

[0044] Of the multiple leads LD arranged on the side MRc1 of the sealing section MR, the inner lead of lead LD1a is integrally connected to the side DPHc2 of the die pad DPH, and the inner lead of lead LD1b is integrally connected to the side DPHc4 of the die pad DPH. Leads LD1a and LD1b function as suspension leads that support the die pad DPH to the frame of the lead frame during the manufacturing of the semiconductor device package. In addition, of the multiple leads LD arranged on the side MRc3 of the sealing section MR, the inner lead of lead LD2a is integrally connected to the side DPLc2 of the die pad DPL, and the inner lead of lead LD2b is integrally connected to the side DPLc4 of the die pad DPL. Leads LD2a and LD2b function as suspension leads that support the die pad DPL to the frame of the lead frame during the manufacturing of the semiconductor device package. On the MRc1 side of the sealing portion MR, multiple leads LD (LD1) are arranged in the X direction, with leads LD1a and LD1b located at both ends. On the MRc3 side of the sealing portion MR, multiple leads LD (LD2) are arranged in the X direction, with leads LD2a and LD2b located at both ends.

[0045] Each of the semiconductor chips CPC, CPH, and CPL has a primary surface (front) and a primary surface (back) on the opposite side. The semiconductor chip CPH is mounted on the upper surface DPHa of the die pad DPH via a bonding material BDH, with its back surface facing the die pad DPH. Similarly, the semiconductor chip CPC is mounted on the upper surface DPLa of the die pad DPL via a bonding material BDC, with its back surface facing the die pad DPL. The semiconductor chip CPL is mounted on the upper surface DPLa of the die pad DPL via a bonding material BDL, with its back surface facing the die pad DPL. In other words, of the semiconductor chips CPC, CPH, and CPL, the semiconductor chip CPH is mounted on the die pad DPH, while the semiconductor chips CPC and CPL are mounted on the die pad DPL.

[0046] On the upper surface DPLa of the die pad DPL, the area on which the semiconductor chip CPC is mounted and the area on which the semiconductor chip CPL is mounted are spaced apart from each other (specifically, spaced apart in the X direction). In other words, the semiconductor chip CPC and semiconductor chip CPL are not stacked on top of each other, but are arranged side by side in the X direction, spaced apart from each other, on the upper surface DPLa of the die pad DPL. That is, the semiconductor chip CPC and semiconductor chip CPL placed on the upper surface DPLa of the die pad DPL are adjacent to each other in the X direction.

[0047] In a plan view, die pads DPL and DPH are adjacent to each other in the Y direction. Therefore, in a plan view, semiconductor chips CPL and CPH are adjacent to each other in the Y direction. Also, in a plan view, semiconductor chips CPC and CPH are adjacent to each other in the Y direction. In a plan view, semiconductor chips CPC and CPL are contained within the upper surface DPLa of die pad DPL. Also, in a plan view, semiconductor chip CPH is contained within the upper surface DPHa of die pad DPH. The planar shape of each semiconductor chip CPC, CPH, and CPL is, for example, rectangular. The rectangle that constitutes the planar shape of semiconductor chips CPC, CPH, and CPL has two sides that are approximately parallel to the X direction and two sides that are approximately parallel to the Y direction.

[0048] Conductive bonding materials such as silver paste can be used as bonding materials BDC, BDH, and BDL. The back surface of the semiconductor chip CPH is bonded and fixed to the die pad DPH via bonding material BDH, the back surface of the semiconductor chip CPC is bonded and fixed to the die pad DPH via bonding material BDC, and the back surface of the semiconductor chip CPL is bonded and fixed to the die pad DPL via bonding material BDL. The semiconductor chips CPC, CPH, and CPL are sealed within the sealing portion MR and are not exposed from the sealing portion MR.

[0049] Insulating bonding materials can also be used as the bonding materials BDC, BDH, and BDL. However, using conductive bonding materials as the bonding materials BDC, BDH, and BDL offers the advantage of making it easier to conduct heat generated in the semiconductor chip CPC, CPH, and CPL to the die pad DPH and DPL via the bonding materials BDC, BDH, and BDL.

[0050] Multiple pads PH1, PH2, PH3, and PH4 are formed on the surface of the semiconductor chip CPH. Multiple pads PL1, PL2, PL3, and PL4 are formed on the surface of the semiconductor chip CPL. Multiple pads PC1, PC2, PC3, PC4, PC5, and PC6 are formed on the surface of the semiconductor chip CPC. Note that "bonding pad," "bonding pad electrode," "pad electrode," or "electrode" will be simply referred to as "pad."

[0051] Each pad PL1, PL2, PL3, and PL4 of the semiconductor chip CPL is electrically connected to circuits formed within the semiconductor chip CPL (such as the transmit circuit TX1, receive circuit RX2, and receive circuit RX3) through the internal wiring of the semiconductor chip CPL.

[0052] Here, pad PL1 of semiconductor chip CPL is a pad electrically connected to pad PC1 of semiconductor chip CPC via wire BW. Pad PL1 of semiconductor chip CPL is electrically connected to the transmit circuit TX1 within semiconductor chip CPL through the internal wiring of semiconductor chip CPL. Pad PL2 of semiconductor chip CPL is a pad electrically connected to pad PC2 of semiconductor chip CPC via wire BW. Pad PL2 of semiconductor chip CPL is electrically connected to the receive circuit RX2 within semiconductor chip CPL through the internal wiring of semiconductor chip CPL. Pad PL3 of semiconductor chip CPL is a pad electrically connected to pad PC3 of semiconductor chip CPC via wire BW. Pad PL3 of semiconductor chip CPL is electrically connected to the receive circuit RX3 within semiconductor chip CPL through the internal wiring of semiconductor chip CPL. Pad PL4 of semiconductor chip CPL is a pad electrically connected to lead LD2 via wire BW.

[0053] Each pad PH1, PH2, PH3, and PH4 of the semiconductor chip CPH is electrically connected to the circuits formed within the semiconductor chip CPH (such as the receiving circuit RX1, transmitting circuit TX2, transmitting circuit TX3, and driving circuit DR) through the internal wiring of the semiconductor chip CPH.

[0054] Here, pad PH1 of semiconductor chip CPH is a pad electrically connected to pad PC4 of semiconductor chip CPC via wire BW. Pad PH1 of semiconductor chip CPH is electrically connected to the receiving circuit RX1 within semiconductor chip CPH through the internal wiring of semiconductor chip CPH. Also, pad PH2 of semiconductor chip CPH is a pad electrically connected to pad PC5 of semiconductor chip CPC via wire BW. Pad PH2 of semiconductor chip CPH is electrically connected to the transmitting circuit TX2 within semiconductor chip CPH through the internal wiring of semiconductor chip CPH. Also, pad PH3 of semiconductor chip CPH is a pad electrically connected to pad PC6 of semiconductor chip CPC via wire BW. Pad PH3 of semiconductor chip CPH is electrically connected to the transmitting circuit TX3 within semiconductor chip CPH through the internal wiring of semiconductor chip CPH. Also, pad PH4 of semiconductor chip CPH is a pad electrically connected to lead LD1 via wire BW.

[0055] Pad PC1 of the semiconductor chip CPC is a pad electrically connected to the coil L1a formed within the semiconductor chip CPC. Pad PC2 of the semiconductor chip CPC is a pad electrically connected to the coil L2a formed within the semiconductor chip CPC. Pad PC3 of the semiconductor chip CPC is a pad electrically connected to the coil L3a formed within the semiconductor chip CPC. Pad PC4 of the semiconductor chip CPC is a pad electrically connected to the coil L1b formed within the semiconductor chip CPC. Pad PC5 of the semiconductor chip CPC is a pad electrically connected to the coil L2b formed within the semiconductor chip CPC. Pad PC6 of the semiconductor chip CPC is a pad electrically connected to the coil L3b formed within the semiconductor chip CPC.

[0056] Multiple (in this case, two) pads PL1 on the semiconductor chip CPL and multiple (in this case, two) pads PC1 on the semiconductor chip CPC are electrically connected via wire BW. That is, one end of wire BW is connected to each pad PL1 on the semiconductor chip CPL, and the other end of wire BW is connected to pad PC1 on the semiconductor chip CPC. Also, multiple (in this case, two) pads PL2 on the semiconductor chip CPL and multiple (in this case, two) pads PC2 on the semiconductor chip CPC are electrically connected via wire BW. That is, one end of wire BW is connected to each pad PL2 on the semiconductor chip CPL, and the other end of wire BW is connected to pad PC2 on the semiconductor chip CPC. Furthermore, multiple (in this case, two) pads PL3 on the semiconductor chip CPL and multiple (in this case, two) pads PC3 on the semiconductor chip CPC are electrically connected via wire BW. In other words, one end of wire BW is connected to each of the PL3 pads of semiconductor chip CPL, and the other end of wire BW is connected to pad PC3 of semiconductor chip CPC.

[0057] Multiple (in this case, two) pads PH1 of the semiconductor chip CPH and multiple (in this case, two) pads PC4 of the semiconductor chip CPC are electrically connected via wire BW. That is, one end of wire BW is connected to each of the pads PH1 of the semiconductor chip CPH, and the other end of wire BW is connected to pad PC4 of the semiconductor chip CPC. Also, multiple (in this case, two) pads PH2 of the semiconductor chip CPH and multiple (in this case, two) pads PC5 of the semiconductor chip CPC are electrically connected via wire BW. That is, one end of wire BW is connected to each of the pads PH2 of the semiconductor chip CPH, and the other end of wire BW is connected to pad PC5 of the semiconductor chip CPC. Also, multiple (in this case, two) pads PH3 of the semiconductor chip CPH and multiple (in this case, two) pads PC6 of the semiconductor chip CPC are electrically connected via wire BW. In other words, one end of wire BW is connected to each of the pads PH3 of the semiconductor chip CPH, and the other end of wire BW is connected to pad PC6 of the semiconductor chip CPC.

[0058] Furthermore, multiple pads PL4 and multiple leads LD2 of the semiconductor chip CPL are electrically connected via wire BW. That is, one end of wire BW is connected to each of the pads PL4 of the semiconductor chip CPL, and the other end of wire BW is connected to the inner lead portion of the lead LD2.

[0059] Furthermore, multiple pads PH4 and multiple leads LD1 of the semiconductor chip CPH are electrically connected via wire BW. That is, one end of wire BW is connected to each of the pads PH4 of the semiconductor chip CPH, and the other end of wire BW is connected to the inner lead portion of lead LD1.

[0060] The wire (bonding wire) BW is a conductive wire. Specifically, the wire BW is made of metal, but gold (Au) wire, copper (Cu) wire, or aluminum (Al) wire can be suitably used. The wire BW is sealed within the sealing portion MR and is not exposed from the sealing portion MR. In each lead LD, the connection point of the wire BW is the inner lead portion located within the sealing portion MR.

[0061] When the semiconductor device package is in use, the semiconductor chip CPL within the semiconductor device package is electrically connected to an external circuit (specifically, the control circuit CC) via wire BW (specifically, wire BW that electrically connects pad PL4 and lead LD2) and lead LD2. Also, when the semiconductor device package is in use, the semiconductor chip CPH within the semiconductor device package is electrically connected to an external circuit (specifically, an inverter circuit composed of power transistors TS1 and TS2) via wire BW (specifically, wire BW that electrically connects pad PH4 and lead LD1) and lead LD1. The drive circuit DR formed within the semiconductor chip CPH is electrically connected to the receiving circuit RX1, transmitting circuit TX2, and transmitting circuit TX3 formed within the semiconductor chip CPH via internal wiring of the semiconductor chip CPH. Furthermore, when the semiconductor device PKG is in use, the drive circuit DR formed within the semiconductor chip CPH is electrically connected to an external circuit of the semiconductor device PKG (specifically, an inverter circuit composed of power transistors TS1 and TS2) via wire BW (specifically, wire BW that electrically connects pad PH4 and lead LD1) and lead LD1. The power supply potential V1 supplied to the inverter circuit composed of power transistors TS1 and TS2 is higher than the power supply potential V2 supplied to the control circuit CC.

[0062] <Regarding the manufacturing process of semiconductor devices> Next, the manufacturing process (assembly process) of the semiconductor device package of this embodiment will be described with reference to Figures 10 to 15. Figures 10 to 15 are plan views or cross-sectional views of the semiconductor device package during the manufacturing process of this embodiment. Of these, Figures 10 to 13 are plan views, Figure 14 is a cross-sectional view corresponding to Figure 7, and Figure 15 is a cross-sectional view corresponding to Figure 8.

[0063] To manufacture a semiconductor device package, first prepare the lead frame (LF), and then prepare the semiconductor chips (CPC, CPH, CPL). Either the lead frame (LF) or the semiconductor chips (CPC, CPH, CPL) can be prepared first, or they can be prepared simultaneously.

[0064] As shown in Figure 10, the lead frame LF integrally comprises a frame LF1, die pads DPH and DPL, and multiple leads LD. The lead frame LF is made of a metallic material, for example, one mainly composed of copper (Cu), specifically copper (Cu) or a copper (Cu) alloy. Figure 10 shows the region of the lead frame LF from which one semiconductor device package is manufactured. One end of each lead LD is integrally connected to the frame LF1. The die pad DPH is connected to the frame LF1 via leads LD1a and LD1b, and the die pad DPL is connected to the frame LF1 via leads LD2a and LD2b.

[0065] Next, as shown in Figure 11, the semiconductor chip CPH is mounted on the upper surface DPHa of the die pad DPH of the lead frame LF via the bonding material BDH (see Figures 14 and 15), the semiconductor chip CPC is mounted on the upper surface DPLa of the die pad DPL via the bonding material BDC (see Figure 15), and the semiconductor chip CPL is mounted on the upper surface DPLa of the die pad DPL via the bonding material BDL (see Figure 14). At this time, each of the semiconductor chips CPC, CPH, and CPL is mounted with its back surface facing the die pad. Subsequently, the bonding materials BDC, BDH, and BDL are cured by heat treatment or the like.

[0066] Next, as shown in Figure 12, a wire bonding process is performed. In the wire bonding process, the pad PL1 of semiconductor chip CPL and the pad PC1 of semiconductor chip CPC are electrically connected via wire BW, the pad PL2 of semiconductor chip CPL and the pad PC2 of semiconductor chip CPC are electrically connected, and the pad PL3 of semiconductor chip CPL and the pad PC3 of semiconductor chip CPC are electrically connected. Also, the pad PH1 of semiconductor chip CPH and the pad PC4 of semiconductor chip CPC are electrically connected via wire BW, the pad PH2 of semiconductor chip CPH and the pad PC5 of semiconductor chip CPC are electrically connected, and the pad PH3 of semiconductor chip CPH and the pad PC6 of semiconductor chip CPC are electrically connected via wire BW. Furthermore, the pad PH4 of semiconductor chip CPH and the lead LD1, and the pad PL4 of semiconductor chip CPL and the lead LD2 are electrically connected via wire BW.

[0067] Next, a resin encapsulation process (resin molding process) is performed to form a encapsulation portion MR that encapsulates the die pads DPH, DPL, semiconductor chips CPC, CPH, CPL, multiple wires BW, and the inner lead portions of multiple leads LD, as shown in Figures 13 to 15.

[0068] Next, a plating layer (not shown) is formed on the outer lead portion of the lead LD exposed from the sealing portion MR, as needed. Then, outside the sealing portion MR, the lead LD is cut at a predetermined position and separated from the frame LF1 of the lead frame LF.

[0069] Next, the outer lead portion of the lead LD protruding from the sealing portion MR is bent (lead processing, lead forming).

[0070] In this way, the semiconductor device package shown in Figures 2 to 9 above is manufactured.

[0071] <About semiconductor chips> Figures 16 and 17 are enlarged planar perspective views of a portion of the semiconductor device package shown in Figure 3. Figure 16 shows a portion of the semiconductor chip CPC, semiconductor chip CPH, and semiconductor chip CPL within the semiconductor device package when viewed through the encapsulation portion MR. Figure 17 shows a portion of the semiconductor chip CPC, semiconductor chip CPH, and semiconductor chip CPL within the semiconductor device package when viewed through the wire BW (omitted) in Figure 16.

[0072] Figures 18 to 20 are schematic cross-sectional views showing the semiconductor chips CPC, CPH, and CPL within the semiconductor device package. Figure 18 corresponds to the cross-sectional view passing through pads PL1, PC1, PC4, and PH1 in Figure 16; Figure 19 corresponds to the cross-sectional view passing through pads PL2, PC2, PC5, and PH2 in Figure 17; and Figure 20 corresponds to the cross-sectional view passing through pads PL3, PC3, PC6, and PH3 in Figure 16. Figures 18 to 20 show each die pad DPH and DPL, each semiconductor chip CPC, CPH, and CPL, and each wire BW, but the sealing portion MR is omitted from the illustration.

[0073] As shown in Figures 18 to 20, the semiconductor chip CPC comprises a semiconductor substrate SB1, a multilayer wiring structure MW1 formed thereon, and a protective film PA1 formed thereon. The multilayer wiring structure MW1 includes multiple interlayer insulating films and multiple wiring layers. The protective film PA1 is a protective film located on the uppermost layer of the semiconductor chip CPC.

[0074] The semiconductor chip CPC also includes coils L1a, L1b, L2a, L2b, L3a, and L3b, which are formed by the wiring layers that constitute the multilayer wiring structure MW1. Coils L1a and L1b are shown in Figure 18, coils L2a and L2b are shown in Figure 19, and coils L3a and L3b are shown in Figure 20. Figures 16 and 17 show the formation locations (formation regions) of each transformer TR1, TR2, and TR3 within the semiconductor chip CPC with dashed lines. In Figures 16 and 17, coils L1a and L1b that constitute transformer TR1 are formed in the location (region) indicated as transformer TR1, coils L2a and L2b that constitute transformer TR2 are formed in the location (region) indicated as transformer TR2, and coils L3a and L3b that constitute transformer TR3 are formed in the location (region) indicated as transformer TR3. Furthermore, Figures 16 and 17 schematically show the wiring WR1, WR2, and WE3 within the semiconductor chip CPC as seen through the glass.

[0075] Of the coils L1a and L1b that make up transformer TR1, coil L1a is electrically connected to pad PL1 of semiconductor chip CPL via pad PC1 of semiconductor chip CPC and wire BW, and coil L1b is electrically connected to pad PH1 of semiconductor chip CPH via pad PC4 of semiconductor chip CPC and wire BW (see Figure 18). Also, of the coils L2a and L2b that make up transformer TR2, coil L2a is electrically connected to pad PL2 of semiconductor chip CPL via pad PC2 of semiconductor chip CPC and wire BW, and coil L2b is electrically connected to pad PH2 of semiconductor chip CPH via pad PC5 of semiconductor chip CPC and wire BW (see Figure 19). Furthermore, of the coils L3a and L3b that make up transformer TR3, coil L3a is electrically connected to pad PL3 of semiconductor chip CPL via pad PC3 of semiconductor chip CPC and wire BW, and coil L3b is electrically connected to pad PH3 of semiconductor chip CPH via pad PC6 of semiconductor chip CPC and wire BW (see Figure 20).

[0076] In the semiconductor chip CPC, coils L1a and L1b are formed in positions that overlap in a plan view, with coil L1a being formed below coil L1b. Also, in the semiconductor chip CPC, coils L2a and L2b are formed in positions that overlap in a plan view, with coil L2a being formed below coil L2b. Also, in the semiconductor chip CPC, coils L3a and L3b are formed in positions that overlap in a plan view, with coil L3a being formed below coil L3b. Furthermore, within the semiconductor chip CPC, it is preferable that coils L1a, L2a, and L3a are formed in the same layer, and it is also preferable that coils L1b, L2b, and L3b are formed in the same layer. Each of the coils L1a, L1b, L2a, L2b, L3a, and L3b is formed by a spiral-shaped conductor pattern (wiring pattern).

[0077] It is preferable that coils L1b, L2b, and L3b are formed on the uppermost wiring layer among the multiple wiring layers constituting the multilayer wiring structure MW1. In this case, coils L1b, L2b, and L3b are formed on the uppermost interlayer insulating film among the multiple interlayer insulating films constituting the multilayer wiring structure MW1. Coils L1b, L2b, and L3b are covered with a protective film PA1, with pads PC1 connected to both ends of coil L1b, pads PC2 connected to both ends of coil L2b, and pads PC3 connected to both ends of coil L3b.

[0078] Coils L1a, L2a, and L3a are formed in wiring layers below the wiring layers on which coils L1b, L2b, and L3b are formed, among the multiple wiring layers that make up the multilayer wiring structure MW1. Both ends of coil L1a are connected to pad PC1 through the wiring of the multilayer wiring structure MW1 (for example, wiring WR1 in Figures 16, 17, and 18). Both ends of coil L2a are connected to pad PC2 through the wiring of the multilayer wiring structure MW1 (for example, wiring WR2 in Figures 16, 17, and 19). Both ends of coil L3a are connected to pad PC3 through the wiring of the multilayer wiring structure MW1 (for example, wiring WR3 in Figures 16, 17, and 20).

[0079] The pads PC1, PC2, PC3, PC4, PC5, and PC6 of the semiconductor chip CPC are formed on the uppermost wiring layer among the multiple wiring layers that make up the multilayer wiring structure MW1, and are each exposed through openings in the protective film PA1. Wires BW are connected to each of the pads PC1, PC2, PC3, PC4, PC5, and PC6 that are exposed through openings in the protective film PA1.

[0080] No semiconductor elements (i.e., transistors like the MOSFETs mentioned above) are formed within the semiconductor chip CPC. In other words, no semiconductor elements (i.e., transistors like the MOSFETs mentioned above) are formed on the semiconductor substrate SB1 that constitutes the semiconductor chip CPC.

[0081] The semiconductor chip CPH comprises a semiconductor substrate SB2, a multilayer wiring structure MW2 formed thereon, and a protective film PA2 formed thereon. The multilayer wiring structure MW2 includes multiple interlayer insulating films and multiple wiring layers. The protective film PA2 is a protective film located on the uppermost layer of the semiconductor chip CPH.

[0082] Multiple semiconductor elements (not shown), such as transistors, are formed on the semiconductor substrate SB2 that constitutes the semiconductor chip CPH. Pads PH1, PH2, PH3, and PH4 of the semiconductor chip CPH are formed on the uppermost wiring layer among the multiple wiring layers that constitute the multilayer wiring structure MW2, and are exposed through openings in the protective film PA2. Wires BW are connected to pads PH1, PH2, PH3, and PH4 that are exposed through openings in the protective film PA2.

[0083] A semiconductor chip CPL comprises a semiconductor substrate SB3, a multilayer wiring structure MW3 formed thereon, and a protective film PA3 formed thereon. The multilayer wiring structure MW3 includes multiple interlayer insulating films and multiple wiring layers. The protective film PA3 is the uppermost protective film of the semiconductor chip CPL.

[0084] Multiple semiconductor elements (not shown), such as transistors, are formed on the semiconductor substrate SB3 that constitutes the semiconductor chip CPL. Pads PL1, PL2, PL3, and PL4 of the semiconductor chip CPL are formed on the uppermost wiring layer among the multiple wiring layers that constitute the multilayer wiring structure MW3, and are exposed through openings in the protective film PA3. Wires BW are connected to pads PL1, PL2, PL3, and PL4 that are exposed through openings in the protective film PA3.

[0085] Next, we will explain the positional relationship between the die pads (DPH, DPL) and semiconductor chips (CPC, CPL, CPH) within the semiconductor device package in a plan view.

[0086] As can be seen from Figures 3 to 5 above, die pad DPH and die pad DPL are adjacent to each other in the Y direction. That is, die pad DPL is located next to die pad DPH in the Y direction. The semiconductor chip CPH is placed on die pad DPH, and semiconductor chips CPC and CPL are placed on die pad DPL. As can be seen from Figures 3, 5, 16, and 17 above, semiconductor chip CPC and semiconductor chip CPL are adjacent to each other in the X direction. That is, semiconductor chip CPC is located next to semiconductor chip CPL in the X direction. Reflecting the fact that die pad DPH and die pad DPL are adjacent to each other in the Y direction, semiconductor chip CPL and semiconductor chip CPH are adjacent to each other in the X direction, and semiconductor chip CPC and semiconductor chip CPH are adjacent to each other in the X direction.

[0087] In a plan view, the semiconductor chip CPC has an edge CPCa opposite the edge CPLa of the semiconductor chip CPL, and an edge CPCb opposite the edge CPHa of the semiconductor chip CPH. That is, the edge CPLa of the semiconductor chip CPL and the edge CPCa of the semiconductor chip CPC are opposite each other in the X direction, and the edge CPCb of the semiconductor chip CPC and the edge CPHa of the semiconductor chip CPH are opposite each other in the Y direction. Also, the edge CPLb of the semiconductor chip CPL and the edge CPHa of the semiconductor chip CPH are opposite each other in the Y direction. The edge CPLa of the semiconductor chip CPL and the edge CPCa of the semiconductor chip CPC are approximately parallel in the Y direction, and the edge CPHa of the semiconductor chip CPH, the edge CPCb of the semiconductor chip CPC, and the edge CPLb of the semiconductor chip CPL are approximately parallel in the X direction.

[0088] Here, in semiconductor chips CPL and CPH, the pads electrically connected to the transmitting circuit within the semiconductor chip will be referred to as transmitting pads, and the pads electrically connected to the receiving circuit within the semiconductor chip will be referred to as receiving pads. Pad PL1 of semiconductor chip CPL is a transmitting pad, pad PL2 of semiconductor chip CPL is a receiving pad, and pad PL3 of semiconductor chip CPL is a receiving pad. Similarly, pad PH1 of semiconductor chip CPH is a receiving pad, pad PH2 of semiconductor chip CPH is a transmitting pad, and pad PH3 of semiconductor chip CPH is a transmitting pad. Therefore, in the following, pad PL1 may be referred to as transmitting pad PL1, pad PL2 as receiving pad PL2, pad PL3 as receiving pad PL3, pad PH1 as receiving pad PH1, pad PH2 as transmitting pad PH2, and pad PH3 as transmitting pad PH3.

[0089] Furthermore, the transformer used to transmit the signal transmitted by the semiconductor chip CPL to the semiconductor chip CPH will be referred to as the transmitting transformer, and the transformer used to transmit the signal transmitted by the semiconductor chip CPH to the semiconductor chip CPL will be referred to as the receiving transformer. In this embodiment, the transformer TR1 in the semiconductor chip CPC is used to transmit the signal transmitted by the semiconductor chip CPL to the semiconductor chip CPH, and therefore may be referred to as the transmitting transformer TR1 below. Also in this embodiment, the transformers TR2 and TR3 in the semiconductor chip CPC are used to transmit the signal transmitted by the semiconductor chip CPH to the semiconductor chip CPL and receive it at the semiconductor chip CPL, and therefore may be referred to as the receiving transformer TR2 and the receiving transformer TR3 below, respectively.

[0090] The primary coil of the transmitting transformer is electrically connected to multiple transmitting pads of the semiconductor chip CPL, and the secondary coil of the transmitting transformer is electrically connected to multiple receiving pads of the semiconductor chip CPH. Similarly, the primary coil of the receiving transformer is electrically connected to multiple transmitting pads of the semiconductor chip CPH, and the secondary coil of the receiving transformer is electrically connected to multiple receiving pads of the semiconductor chip CPL.

[0091] Furthermore, the wire BW that electrically connects pad PC1 of semiconductor chip CPC to pad PL1 of semiconductor chip CPL is referred to as wire BW1. Furthermore, the wire BW that electrically connects pad PC2 of semiconductor chip CPC to pad PL2 of semiconductor chip CPL is referred to as wire BW2. Furthermore, the wire BW that electrically connects pad PC3 of semiconductor chip CPC to pad PL3 of semiconductor chip CPL is referred to as wire BW3. Furthermore, the wire BW that electrically connects pad PC4 of semiconductor chip CPC to pad PH1 of semiconductor chip CPH is referred to as wire BW4. Furthermore, the wire BW that electrically connects pad PC5 of semiconductor chip CPC to pad PH2 of semiconductor chip CPH is referred to as wire BW5. Furthermore, the wire BW that electrically connects pad PC6 of semiconductor chip CPC to pad PH3 of semiconductor chip CPH is referred to as wire BW6.

[0092] As can be seen from Figures 16 and 17, in the semiconductor chip CPC, transformers TR1, TR2, and TR3 are arranged along the edge CPCb of the semiconductor chip CPC in a plan view. Transformers TR1, TR2, and TR3 do not overlap in a plan view and are spaced apart from each other in a plan view.

[0093] As can be seen from Figures 16 and 17, in a semiconductor chip CPC, the transmitting transformer TR1 is positioned closer to the semiconductor chip CPL than the receiving transformers TR2 and TR3 in a plan view. That is, the distance (spacing) between the transmitting transformer TR1 and the semiconductor chip CPL in the X direction is smaller than the distance (spacing) between the receiving transformer TR2 and the semiconductor chip CPL in the X direction, and also smaller than the distance (spacing) between the receiving transformer TR3 and the semiconductor chip CPL in the X direction. In the case of Figures 16 and 17, of the transformers TR1, TR2, and TR3, the transmitting transformer TR1 is located closest to the semiconductor chip CPL, the receiving transformer TR3 is located furthest from the semiconductor chip CPL, and the receiving transformer TR2 is located between the transmitting transformer TR1 and the receiving transformer TR3. In another configuration, the positions of the receiving transformers TR2 and TR3 can be swapped in a semiconductor chip CPC, but even in that case, of the transformers TR1, TR2, and TR3, the transmitting transformer TR1 is located closest to the semiconductor chip CPL.

[0094] As can be seen from Figures 16 and 17, in the semiconductor chip CPC, pads PC4, PC5, and PC6 are arranged along the edge CPCb of the semiconductor chip CPC in a plan view. In the semiconductor chip CPC, pad PC4 is located closer to the semiconductor chip CPL than pads PC5 and PC6 in a plan view. That is, the distance (spacing) between pad PC4 and the semiconductor chip CPL in the X direction is smaller than the distance (spacing) between pad PC5 and the semiconductor chip CPL in the X direction, and also smaller than the distance (spacing) between pad PC6 and the semiconductor chip CPL in the X direction. In the case of Figures 16 and 17, of pads PC4, PC5, and PC6, pad PC4 is located closest to the semiconductor chip CPL, pad PC6 is located furthest from the semiconductor chip CPL, and pad PC5 is located between pads PC4 and PC6. In another configuration, if the positions of the receiving transformer TR2 and the receiving transformer TR3 are swapped in the semiconductor chip CPC, it is preferable to swap the positions of the pad PC5 and the pad PC6 in the semiconductor chip CPC.

[0095] As can be seen from Figures 16 and 17, in the semiconductor chip CPL, pads PL1, PL2, and PL3 are arranged along the edge CPLa of the semiconductor chip CPL in a plan view. In the semiconductor chip CPL, the transmitting pad PL1 is located closer to the semiconductor chip CPH than the receiving pads PL2 and PL3 in a plan view. That is, the distance (spacing) between the transmitting pad PL1 and the semiconductor chip CPH in the Y direction is smaller than the distance (spacing) between the receiving pad PL2 and the semiconductor chip CPH in the Y direction, and also smaller than the distance (spacing) between the receiving pad PL3 and the semiconductor chip CPH in the Y direction. In the case of Figures 16 and 17, of the pads PL1, PL2, and PL3, the transmitting pad PL1 is located closest to the semiconductor chip CPH, the receiving pad PL3 is located furthest from the semiconductor chip CPH, and the receiving pad PL2 is located between the transmitting pad PL1 and the receiving pad PL3. In another configuration, if the positions of the receiving transformer TR2 and the receiving transformer TR3 are swapped in the semiconductor chip CPC, it is preferable to swap the positions of the receiving pad PL2 and the receiving pad PL3 in the semiconductor chip CPL.

[0096] As can be seen from Figures 16 and 17, in the semiconductor chip CPH, pads PH1, PH2, and PH3 are arranged along the edge CPH of the semiconductor chip CPH in a plan view. In the semiconductor chip CPH, the receiving pad PH1 is located closer to the semiconductor chip CPL than the transmitting pads PH2 and PH3 in a plan view. That is, in a plan view, the distance (spacing) between the receiving pad PH1 and the semiconductor chip CPL in the X direction is smaller than the distance (spacing) between the transmitting pad PH2 and the semiconductor chip CPL in the X direction, and also smaller than the distance (spacing) between the transmitting pad PH3 and the semiconductor chip CPL in the X direction. In the case of Figures 16 and 17, of the pads PH1, PH2, and PH3, the receiving pad PH1 is located closest to the semiconductor chip CPL, the transmitting pad PH3 is located furthest from the semiconductor chip CPL, and the transmitting pad PH2 is located between the receiving pad PH1 and the transmitting pad PH3. In another configuration, if the positions of the receiving transformer TR2 and the receiving transformer TR3 are swapped in the semiconductor chip CPC, it is preferable to swap the positions of the transmitting pad PH2 and the transmitting pad PH3 in the semiconductor chip CPH.

[0097] <Regarding the background of the consideration> Figure 21 is a plan view of a semiconductor device PKG101, an example considered by the inventors, and corresponds to Figure 2 above.

[0098] The semiconductor device PKG101 in the example shown in Figure 21 has die pads DPH101 and DPL101 instead of the die pads DPH and DPL described above. A semiconductor chip CPH101 corresponding to the semiconductor chip CPH is mounted on die pad DPH101, and a semiconductor chip CPL101 corresponding to the semiconductor chip CPL and a semiconductor chip CPC101 corresponding to the semiconductor chip CPC are mounted on die pad DPL101.

[0099] In the semiconductor device PKG101 shown in Figure 21, the three semiconductor chips CPL101, CPC101, and CPH101 are arranged in the Y direction. The inventors' investigations have revealed that the following problems may arise in this case.

[0100] In recent years, due to the increasing functionality of semiconductor devices and the increasing current flowing through the circuits used (such as inverter circuits), the planar dimensions (planar area) of high-voltage semiconductor chips CPH and CPH101 tend to increase compared to the planar dimensions (planar area) of low-voltage semiconductor chips CPL and CPL101.

[0101] As shown in Figure 21, when three semiconductor chips CPL101, CPC101, and CPH101 are arranged in the Y direction, the Y-direction dimension of the semiconductor device PKG101 becomes large. This leads to an increase in the size of the semiconductor device PKG101. To reduce the Y-direction dimension of the semiconductor device PKG101, it is effective to reduce the Y-direction dimension of each semiconductor chip CPL101, CPC101, and CPH101. However, reducing the Y-direction dimension of each semiconductor chip CPL101, CPC101, and CPH101 necessitates increasing the X-direction dimension of each semiconductor chip CPL101, CPC101, and CPH101, thus increasing the aspect ratio (ratio of the X-direction dimension to the Y-direction dimension) of each semiconductor chip CPL101, CPC101, and CPH101. When the aspect ratio of a semiconductor chip increases, cracks are more likely to occur in the semiconductor chip, for example, when cutting the semiconductor wafer to obtain the semiconductor chip or during the transportation of the semiconductor chip. This reduces the manufacturing yield of the semiconductor chip itself, as well as the manufacturing yield of the semiconductor equipment that incorporates the semiconductor chip.

[0102] Furthermore, since the planar dimensions of semiconductor chips CPL101 and CPC101 are smaller than those of semiconductor chip CPH101, if the X-direction dimensions of semiconductor chips CPL101, CPC101, and CPH101 are made the same, the aspect ratios of semiconductor chips CPL101 and CPC101 become considerably larger than those of semiconductor chip CPH101. For this reason, the cracking problem mentioned above is a particular concern for semiconductor chips CPL101 and CPC101, which have a large aspect ratio. On the other hand, if the X-direction dimensions of semiconductor chips CPL101 and CPC101 in semiconductor device PKG101 are made smaller than the X-direction dimensions of semiconductor chip CPH101, the difference between the amount (volume) of encapsulating resin surrounding semiconductor chip CPH101 and the amount (volume) of encapsulating resin surrounding semiconductor chip CPL101 becomes large. As a result, there is a risk that the flatness of the semiconductor device PKG101 will decrease (i.e., the semiconductor device PKG101 may warp).

[0103] <Main Features and Effects> One of the main features of the semiconductor device package of this embodiment is that the semiconductor chip CPH is placed on a die pad DPH, and semiconductor chips CPC and CPL are placed on a die pad DPL located next to the die pad DPH in the Y direction, while the semiconductor chips CPC and CPL are adjacent to each other in the X direction, which is perpendicular to the Y direction. As a result, the dimensions of the semiconductor device package of this embodiment can be reduced in the Y direction without increasing the aspect ratio (ratio of the dimension in the X direction to the dimension in the Y direction) of the semiconductor chips CPC and CPL. Therefore, the semiconductor device can be miniaturized. In addition, because the aspect ratio of the semiconductor chips CPC and CPL can be suppressed, the risk of cracks occurring in the semiconductor chips CPL and CPC can be reduced, for example, when cutting semiconductor wafers to obtain semiconductor chips or when transporting semiconductor chips. Therefore, the manufacturing yield of semiconductor chips CPL and CPC, and the manufacturing yield of the semiconductor device package can be improved. Furthermore, in semiconductor device packages, the semiconductor chips CPH, CPL, and CPC can be arranged in a balanced manner within the sealing portion MR, thereby reducing the difference in the amount (volume) of sealing resin surrounding the semiconductor chip CPH, the semiconductor chip CPL, and the semiconductor chip CPC. As a result, warping of the semiconductor device package can be suppressed or prevented, and the flatness of the semiconductor device package can be improved.

[0104] When such a semiconductor chip CPL, CPC, and CPH layout is adopted, it is not possible to simultaneously arrange multiple transformers (TR1, TR2, TR3) within the semiconductor chip CPC at equidistant distances from the semiconductor chip CPL and arrange multiple transformers (TR1, TR2, TR3) within the semiconductor chip CPC at equidistant distances from the semiconductor chip CPH. Therefore, the inventors' research has shown that optimizing the placement of multiple transformers (TR1, TR2, TR3) within the semiconductor chip CPC, the placement of pads PL1, PL2, PL3 in the semiconductor chip CPL, and the placement of pads PH1, PH2, PH3 in the semiconductor chip CPH is important for improving the performance of the semiconductor device package.

[0105] In other words, a signal is sent from the transmitting circuit to the primary coil of a transformer, causing a current to flow through the primary coil. The induced current (or induced electromotive force) generated in the secondary coil of the transformer is then detected (received) by the receiving circuit, thereby transmitting a signal from the transmitting circuit to the receiving circuit via the transformer. Of the electrical resistance of the conductive path from the transmitting circuit to the primary coil of the transformer and the electrical resistance of the conductive path from the secondary coil of the transformer to the receiving circuit, the electrical resistance of the conductive path from the transmitting circuit to the primary coil of the transformer has the greatest impact on the signal quality when transmitting a signal from the transmitting circuit to the receiving circuit via the transformer. That is, if the resistance loss from the transmitting circuit to the primary coil of the transformer is large, the induced current will not flow properly in the secondary coil of the transformer, and as a result, the signal cannot be accurately transmitted from the transmitting circuit to the receiving circuit via the transformer. For this reason, in order to prevent signal degradation as much as possible when transmitting a signal from the transmitting circuit to the receiving circuit via the transformer, it is important to lower the electrical resistance of the conductive path from the transmitting circuit to the primary coil of the transformer and suppress the resistance loss from the transmitting circuit to the primary coil of the transformer. Compared to the importance of keeping the electrical resistance of the conductive path from the transmitting circuit to the primary coil of the transformer low, it is acceptable for the electrical resistance of the conductive path from the secondary coil of the transformer to the receiving circuit to be somewhat higher.

[0106] Therefore, in order to lower the electrical resistance of the conductive path from the transmitting circuit to the primary coil of the transformer, the following measures are taken.

[0107] The semiconductor device package of this embodiment incorporates semiconductor chips CPC, CPL, and CPH. The semiconductor chip CPC has one or more transmitting transformers (here referred to as transformer TR1) and one or more receiving transformers (here referred to as transformers TR2 and TR3). As described above, the transmitting transformer is used to transmit signals from semiconductor chip CPL to semiconductor chip CPH, and the receiving transformer is used to transmit signals from semiconductor chip CPH to semiconductor chip CPL. The semiconductor chip CPL includes a plurality of transmitting pads PL1 and a plurality of receiving pads PL2 and PL3, and the semiconductor chip CPH includes a plurality of transmitting pads PH2 and PH3 and a plurality of receiving pads PH1. In each of the semiconductor chips CPL and CPH, the transmitting pads are electrically connected to the transmitting circuit within the semiconductor chip, and the receiving pads are electrically connected to the receiving circuit within the semiconductor chip.

[0108] Another key feature of the semiconductor device package of this embodiment is that, in the semiconductor chip CPC, the multiple transformers TR1, TR2, and TR3 are arranged along the edge CPCb of the semiconductor chip CPC (the edge CPCb opposite the edge CPHa of the semiconductor chip CPH) in a plan view, and the transmitting transformer TR1 is positioned closer to the semiconductor chip CPL than the receiving transformers TR2 and TR3 in a plan view. Furthermore, in the semiconductor chip CPL, the multiple transmitting pads PL1 are positioned closer to the semiconductor chip CPH than the multiple receiving pads PL2 and PL3 in a plan view.

[0109] This reduces the distance between the transmitting transformer TR1 of the semiconductor chip CPC and the multiple transmitting pads PL1 of the semiconductor chip CPL in a plan view. As a result, the electrical resistance of the conductive path connecting the multiple transmitting pads PL1 of the semiconductor chip CPL and the primary coil (L1a) of the transmitting transformer TR1 of the semiconductor chip CPC can be reduced. Specifically, the conductive path connecting the transmitting pads PL1 of the semiconductor chip CPL and the primary coil (L1a) of the transmitting transformer TR1 of the semiconductor chip CPC includes wire BW1 and wiring WR1. By reducing the distance between the transmitting transformer TR1 of the semiconductor chip CPC and the multiple transmitting pads PL1 of the semiconductor chip CPL, the length of wire BW1 and the length of wiring WR1 can be reduced. This suppresses signal degradation and ensures accurate signal transmission when transmitting a signal from the transmitting circuit TX1 of the semiconductor chip CPL to the receiving circuit RX1 of the semiconductor chip CPH via the transformer TR1 of the semiconductor chip CPC.

[0110] Furthermore, the distance between the receiving transformer TR2 of the semiconductor chip CPC and the receiving pad PL2 of the semiconductor chip CPL, and the distance between the receiving transformer TR3 of the semiconductor chip CPC and the receiving pad PL2 of the semiconductor chip CPL, are larger than the distance between the transmitting transformer TR1 of the semiconductor chip CPC and the transmitting pad PL1 of the semiconductor chip CPL. As a result, the length of one or both of wire BW2 and wiring WR2 is larger than the length of wire BW1 and wiring WR1, and the length of one or both of wire BW3 and wiring WR3 is also larger. Consequently, the electrical resistance of the conductive path connecting the receiving pad PL2 and the secondary coil (L2a) of the receiving transformer TR2, and the electrical resistance of the conductive path connecting the receiving pad PL3 and the secondary coil (L3a) of the receiving transformer TR3 are larger than the electrical resistance of the conductive path connecting the transmitting pad PL1 and the primary coil (L1a) of the transmitting transformer TR1, but this has little effect on the quality of signal transmission.

[0111] Therefore, in this embodiment, by reducing the distance between the transmitting transformer TR1 of the semiconductor chip CPC and the multiple transmitting pads PL1 of the semiconductor chip CPL, signals can be transmitted more accurately between the semiconductor chip CPL and the semiconductor chip CPH, thereby improving the performance of the semiconductor device.

[0112] Furthermore, in a semiconductor chip CPL, it is preferable that pads PL1, PL2, and PL3 are arranged along the edge CPLa of the semiconductor chip CPL (the edge CPLa opposite to the edge CPCa of the semiconductor chip CPC) in a plan view. This makes it easier to connect each pad PL1, PL2, and PL3 of the semiconductor chip CPL to each pad PC1, PC2, and PC3 of the semiconductor chip CPC with wires BW, and also reduces the length of the wires BW (BW1, BW2, BW3) connecting each pad PL1, PL2, and PL3 of the semiconductor chip CPC to each pad PC1, PC2, and PC3 of the semiconductor chip CPC. As a result, the control of the manufacturing process of the semiconductor device package becomes easier. In addition, the performance of the semiconductor device can be further improved.

[0113] Furthermore, in the semiconductor chip CPH, it is preferable that pads PH1, PH2, and PH3 are arranged along the edge CPHa of the semiconductor chip CPH (the edge CPHa opposite the edge CPCb of the semiconductor chip CPC) in a plan view. This makes it easier to connect each pad PH1, PH2, and PH3 of the semiconductor chip CPH to each pad PC4, PC5, and PC6 of the semiconductor chip CPC with wires BW, and also reduces the length of the wires BW (BW4, BW5, BW6) connecting each pad PH1, PH2, and PH3 of the semiconductor chip CPH to each pad PC4, PC5, and PC6 of the semiconductor chip CPC. As a result, the control of the manufacturing process of the semiconductor device package becomes easier. In addition, the performance of the semiconductor device can be further improved.

[0114] Furthermore, in a semiconductor chip CPH, it is preferable that the multiple receiving pads PH1 are positioned closer to the semiconductor chip CPL than the multiple transmitting pads PH2 and PH3 in a plan view. This makes it possible to reduce the distance between the receiving pad PH1 of the semiconductor chip CPH and the transformer TR1 of the semiconductor chip CPC, the distance between the transmitting pad PH2 of the semiconductor chip CPH and the transformer TR2 of the semiconductor chip CPC, and the distance between the transmitting pad PH3 of the semiconductor chip CPH and the transformer TR3 of the semiconductor chip CPC. As a result, the length of the wires BW (BW4, BW5, BW6) connecting each pad PH1, PH2, PH3 of the semiconductor chip CPH and each pad PC4, PC5, PC6 of the semiconductor chip CPC can be reduced. This makes it possible to further improve the performance of the semiconductor device.

[0115] In this embodiment, the connection paths between the pads PL1, PL2, PL3 of the semiconductor chip CPL and the transformers TR1, TR2, TR3 of the semiconductor chip CPC are designed to prioritize reducing the distance between the pad PL1 of the semiconductor chip CPL and the transformer TR1 of the semiconductor chip CPC, thereby prioritizing the reduction of the electrical resistance of the conductive path connecting the pad PL1 of the semiconductor chip CPL and the transformer TR1 of the semiconductor chip CPC.

[0116] On the other hand, the electrical resistance of the conductive path connecting pad PH1 of semiconductor chip CPH to transformer TR1 of semiconductor chip CPC, the electrical resistance of the conductive path connecting pad PH2 of semiconductor chip CPH to transformer TR2 of semiconductor chip CPC, and the electrical resistance of the conductive path connecting pad PH3 of semiconductor chip CPH to transformer TR3 of semiconductor chip CPC can be made to be approximately the same. The reason for this is as follows: In semiconductor chip CPC, transformers TR1, TR2, and TR3 are arranged along the edge CPCb of semiconductor chip CPC in a plan view, and in semiconductor chip CPH, pads PH1, PH2, and PH3 are arranged along the edge CPH of semiconductor chip CPH in a plan view. This makes it possible to make the distance between pad PH1 and transformer TR1, the distance between pad PH2 and transformer TR2, and the distance between pad PH3 and transformer TR3 to be approximately the same.

[0117] Therefore, the electrical resistance of the conductive path connecting the transmitting pad PL1 of the semiconductor chip CPL and the primary coil (L1a) of the transformer TR1, the electrical resistance of the conductive path connecting the transmitting pad PH2 of the semiconductor chip CPH and the primary coil (L2b) of the transformer TR2, and the electrical resistance of the conductive path connecting the transmitting pad PH3 of the semiconductor chip CPH and the primary coil (L3b) of the transformer TR3 can be suppressed. As a result, the electrical resistance of the conductive path connecting the transmitting circuit TX1 of the semiconductor chip CPL and the primary coil (L1a) of the transformer TR1, the electrical resistance of the conductive path connecting the transmitting circuit TX2 of the semiconductor chip CPH and the primary coil (L2b) of the transformer TR2, and the electrical resistance of the conductive path connecting the transmitting circuit TX3 of the semiconductor chip CPH and the primary coil (L3b) of the transformer TR3 can be suppressed. This allows for accurate signal transmission between the semiconductor chip CPL and the semiconductor chip CPH via transformers TR1, TR2, and TR3, thereby improving the performance of the semiconductor device.

[0118] <First variation> Next, a first modified example of the semiconductor device package of this embodiment will be described.

[0119] Figure 22 is an explanatory diagram showing the semiconductor device package of the first modified example, and shows a cross-sectional view corresponding to Figure 18 above. Hereafter, the semiconductor device package of the first modified example will be referred to as semiconductor device package 1.

[0120] In the first modified semiconductor device PKG1 shown in Figure 22, an insulating bonding material such as a die attach film (DAF) BDC1, which has not only an adhesive (adhesive layer) but also a substrate (tape layer), is used as the bonding material BDC for mounting the semiconductor chip CPC onto the die pad DPL. By interposing an insulating bonding material such as the die attach film BDC1 between the die pad DPL and the semiconductor chip CPC, the withstand voltage between the die pad DPL and the semiconductor chip CPC can be increased compared to conductive bonding materials such as silver paste that do not have a substrate.

[0121] <Second variation> Next, a second modified example of the semiconductor device package of this embodiment will be described.

[0122] Figures 23 to 25 are explanatory diagrams showing a semiconductor device package of a second modified example. Figure 23 shows a cross-sectional view corresponding to Figure 18 above, Figure 24 shows a cross-sectional view corresponding to Figure 19 above, and Figure 25 shows a cross-sectional view corresponding to Figure 20 above. Hereafter, the semiconductor device package of the second modified example will be referred to as semiconductor device package 2.

[0123] The semiconductor device PKG2 of the second modified example shown in Figures 23 to 25 differs from the semiconductor device PKG shown in Figures 18 to 20 in the configuration of transformers TR1, TR2, and TR3 within the semiconductor chip CPC. The differences between the semiconductor device PKG2 of the second modified example shown in Figures 23 to 25 and the semiconductor device PKG shown in Figures 18 to 20 will be explained in detail below.

[0124] In the case of the semiconductor device PKG2 of the second modified example, in the multilayer wiring structure MW1 of the semiconductor chip CPC, coils L1a and L1b constituting the transformer TR1 do not overlap in a plan view and are formed on the same wiring layer (see Figure 23). Furthermore, in the multilayer wiring structure MW1 of the semiconductor chip CPC, coil L1c is provided below coil L1a, and coil L1d is provided below coil L1a (see Figure 23). Coil L1a and the coil L1c below it are not connected by a conductor, but are magnetically coupled to each other. Similarly, coil L1b and the coil L1d below it are not connected by a conductor, but are magnetically coupled to each other. On the other hand, coil L1c and coil L1d are connected by a conductor and are therefore electrically connected. For this reason, coil L1a and coil L1d are magnetically coupled to each other.

[0125] Furthermore, in the multilayer wiring structure MW1 of the semiconductor chip CPC, coils L2a and L2b constituting the transformer TR2 do not overlap in a plan view and are formed on the same wiring layer (see Figure 24). In the multilayer wiring structure MW1 of the semiconductor chip CPC, coil L2c is provided below coil L2a, and coil L2d is provided below coil L2a (see Figure 24). Coil L2a and the coil L2c below it are not connected by a conductor, but are magnetically coupled to each other. Similarly, coil L2b and the coil L2d below it are not connected by a conductor, but are magnetically coupled to each other. On the other hand, coil L2c and coil L2d are connected by a conductor and are therefore electrically connected. For this reason, coil L2a and coil L2d are magnetically coupled to each other.

[0126] Furthermore, in the multilayer wiring structure MW1 of the semiconductor chip CPC, coils L3a and L3b constituting the transformer TR3 do not overlap in a plan view and are formed on the same wiring layer (see Figure 25). In the multilayer wiring structure MW1 of the semiconductor chip CPC, coil L3c is provided below coil L3a, and coil L3d is provided below coil L3a (see Figure 25). Coil L3a and the coil L3c below it are not connected by a conductor, but are magnetically coupled to each other. Similarly, coil L3b and the coil L3d below it are not connected by a conductor, but are magnetically coupled to each other. On the other hand, coil L3c and coil L3d are connected by a conductor and are therefore electrically connected. For this reason, coil L3a and coil L3d are magnetically coupled to each other.

[0127] Transformer TR1 is formed by coils L1a, L1b, L1c, and L1d formed within a semiconductor chip CPC; transformer TR2 is formed by coils L2a, L2b, L2c, and L2d formed within a semiconductor chip CPC; and transformer TR3 is formed by coils L3a, L3b, L3c, and L3d formed within a semiconductor chip CPC. Each of the coils L1a, L1b, L1c, L1d, L2a, L2b, L2c, L2d, L3a, L3b, L3c, and L3d is formed by a spiral-shaped conductor pattern (wiring pattern).

[0128] When a signal is sent from the transmitting circuit TX1 to the coil L1a of the transformer TR1, current flows through coil L1a. In response to the change in this current, an induced electromotive force is generated in coil L1c, causing an induced current to flow. Since coils L1c and L1d are electrically connected, when an induced current flows through coil L1c, current inevitably flows through coil L1d as well. When current flows through coil L1d, an induced electromotive force is generated in coil L1b in response to the change in this current, causing an induced current to flow. In other words, when current flows through coil L1a (primary coil), an induced electromotive force is generated in coil L1b (secondary coil) in response to the change in this current, causing an induced current to flow. For this reason, in the case of the semiconductor device PKG2 of the second modification, coil L1a functions as the primary coil and coil L1b functions as the secondary coil. The same applies to transformers TR2 and TR3, but in the case of transformer TR2, coil L2b functions as the primary coil and coil L2a functions as the secondary coil, and in the case of transformer TR3, coil L3b functions as the primary coil and coil L3a functions as the secondary coil. Furthermore, in the multilayer wiring structure MW1 of the semiconductor chip CPC, it is preferable that coils L1a, L1b, L2a, L2b, L3a, and L3b are formed in the same layer. Also, in the multilayer wiring structure MW1 of the semiconductor chip CPC, it is preferable that coils L1c, L1d, L2c, L2d, L3c, and L3d are formed in the same layer.

[0129] Therefore, in the case of the semiconductor device PKG2 of the second modified example, a signal can be transmitted from the transmitting circuit TX1 to the coil L1a (primary coil) of the transformer TR1, causing a current to flow. The induced current (or induced electromotive force) generated in the coil L1b (secondary coil) of the transformer TR1 in response is detected (received) by the receiving circuit RX1. This allows the signal to be transmitted from the transmitting circuit TX1 to the receiving circuit RX1 via the transformer TR1. Furthermore, a signal can be transmitted from the transmitting circuit TX2 to the receiving circuit RX2 via the transformer TR2. Additionally, a signal can be transmitted from the transmitting circuit TX3 to the receiving circuit RX3 via the transformer TR3.

[0130] Furthermore, in the second modified semiconductor device PKG2 shown in Figures 23 to 25, an insulating bonding material such as a die attach film BDC1 is used as the bonding material BDC for mounting the semiconductor chip CPC onto the die pad DPL. This makes it possible to increase the withstand voltage between the die pad DPL and the semiconductor chip CPC.

[0131] Furthermore, in the case of the semiconductor device PKG2 of the second modified example shown in Figures 23 to 25, it is possible to reduce the thickness of the interlayer insulating film constituting the multilayer wiring structure MW1 of the semiconductor chip CPC (and therefore the thickness of the multilayer wiring structure MW1) compared to the semiconductor device PKG shown in Figures 18 to 20. The reason for this is as follows: In the case of the semiconductor device PKG shown in Figures 18 to 20, it is necessary to increase the thickness of the interlayer insulating film interposed between each coil L1b, L2b, L3b and each coil L1a, L2a, L3a within the semiconductor chip CPC to ensure the breakdown voltage between each coil L1b, L2b, L3b connected to the semiconductor chip CPH and each coil L1a, L2a, L3a connected to the semiconductor chip CPL. In contrast, in the case of the semiconductor device package shown in Figures 23 to 25, the withstand voltage between each coil L1b, L2b, L3b connected to the semiconductor chip CPH and each coil L1a, L2a, L3a connected to the semiconductor chip CPL can be ensured without significantly increasing the thickness of the interlayer insulating film between each coil L1a, L1b, L2a, L2b, L3a, L3b and each coil L1c, L1d, L2c, L2d, L3c, L3d within the semiconductor chip CPC. Therefore, in the case of the semiconductor device package 2 of the second modified example shown in Figures 23 to 25, it is possible to reduce the thickness of the interlayer insulating film constituting the multilayer wiring structure MW1 of the semiconductor chip CPC (and thus the thickness of the multilayer wiring structure MW1). The withstand voltage between the semiconductor chip CPC and the die pad DPL can be ensured by the die attach film BDC1.

[0132] Therefore, compared to the semiconductor device package shown in Figures 18 to 20, the semiconductor device package 2 of the second modified example shown in Figures 23 to 25 allows for a thinner semiconductor chip CPC. Furthermore, in line with the reduction in the thickness of the semiconductor chip CPC, the thicknesses of the semiconductor chips CPL and CPH can also be reduced. Consequently, the semiconductor device package 2 of the second modified example shown in Figures 23 to 25 allows for a thinner semiconductor device package 2.

[0133] Furthermore, in the case of the semiconductor device PKG2 of the second modified example shown in Figures 23 to 25, the thickness of the interlayer insulating film constituting the multilayer wiring structure MW1 of the semiconductor chip CPC can be reduced, making it easier to manufacture the semiconductor chip CPC and improving the manufacturing yield of the semiconductor chip CPC. This is because if the interlayer insulating film formed on the semiconductor wafer is thick, the semiconductor wafer is prone to warping, but if the interlayer insulating film can be made thinner, the warping of the semiconductor wafer can be suppressed.

[0134] (Embodiment 2) Figure 26 is a circuit diagram showing an inverter circuit using the semiconductor device package of this second embodiment, and corresponds to Figure 1 above. Hereafter, the semiconductor device package of this second embodiment will be referred to as semiconductor device package 3. Furthermore, below, the differences between semiconductor device package 3 of this second embodiment and the semiconductor device package of the first embodiment will be mainly described, and the points that are common to semiconductor device package 3 of this second embodiment and the semiconductor device package of the first embodiment will be omitted for brevity.

[0135] The circuit configuration of the semiconductor device PKG3 of this embodiment 2, shown in Figure 26, differs from the circuit configuration of the semiconductor device PKG of embodiment 1, shown in Figure 1, in the following respects. Specifically, in the case of the semiconductor device PKG of embodiment 1, as can be seen from Figure 1, the receiving circuit RX2 was formed on the semiconductor chip CPL, and the transmitting circuit TX2 was formed on the semiconductor chip CPH. In contrast, in the case of the semiconductor device PKG3 of this embodiment 2, as can be seen from Figure 26, the receiving circuit RX2 is formed on the semiconductor chip CPH instead of the semiconductor chip CPL, and the transmitting circuit TX2 is formed on the semiconductor chip CPL instead of the semiconductor chip CPH. Therefore, in the case of the semiconductor device PKG3 of this embodiment 2, the pad PL2 of the semiconductor chip CPL is electrically connected to the transmitting circuit TX1 within the semiconductor chip CPL through the internal wiring of the semiconductor chip CPL, and the pad PH2 of the semiconductor chip CPH is electrically connected to the receiving circuit RX2 within the semiconductor chip CPH through the internal wiring of the semiconductor chip CPH.

[0136] Therefore, in Embodiment 1, transformer TR2 was a receiving transformer used to transmit the signal transmitted by semiconductor chip CPH to semiconductor chip CPL and receive it at semiconductor chip CPL. However, in Embodiment 2, transformer TR2 is a transmitting transformer used to transmit the signal transmitted by semiconductor chip CPL to semiconductor chip CPH. Also, in Embodiment 1, coil L2b of transformer TR2 was the primary coil and coil L2a of transformer TR2 was the secondary coil. However, in Embodiment 2, coil L2a of transformer TR2 is the primary coil and coil L2b of transformer TR2 is the secondary coil. Furthermore, in Embodiment 1, pad PL2 of semiconductor chip CPL was a receiving pad and pad PH2 of semiconductor chip CPH was a transmitting pad. However, in Embodiment 2, pad PL2 of semiconductor chip CPL is a transmitting pad connected to the transmitting circuit TX2, and pad PH2 of semiconductor chip CPH is a receiving pad connected to the receiving circuit RX2.

[0137] Figures 27 and 28 are enlarged planar perspective views of a portion of the semiconductor device PKG3 of this second embodiment. Figure 27 corresponds to Figure 16 and shows a portion of the semiconductor chip CPC, semiconductor chip CPH, and semiconductor chip CPL inside the semiconductor device PKG3 when the sealing portion MR is viewed through. Figure 28 corresponds to Figure 17 and shows a portion of the semiconductor chip CPC, semiconductor chip CPH, and semiconductor chip CPL inside the semiconductor device PKG3 when the wire BW is viewed through (omitted) in Figure 27.

[0138] The wirings WR1a, WR2a, and WR3a shown in Figures 27 and 28 are wirings of the multilayer wiring structure MW1 of the semiconductor chip CPC. Both ends of coil L1b constituting transformer TR1 are connected to pad PC4 via wiring WR1a, both ends of coil L2b constituting transformer TR2 are connected to pad PC5 via wiring WR2a, and both ends of coil L3b constituting transformer TR3 are connected to pad PC6 via wiring WR3a.

[0139] In this second embodiment, as can be seen from Figures 27 and 28, in the semiconductor chip CPC, transformers TR1, TR2, and TR3 are arranged (arranged) along the edge CPCa of the semiconductor chip CPC (the edge CPCa opposite the edge CPLa of the semiconductor chip CPL) in a plan view. Transformers TR1, TR2, and TR3 do not overlap in a plan view and are spaced apart from each other in a plan view.

[0140] Furthermore, in this second embodiment, as can be seen from Figures 27 and 28, in the semiconductor chip CPC, the receiving transformer TR3 is positioned closer to the semiconductor chip CPH than the transmitting transformers TR1 and TR2 in a plan view. That is, the distance (spacing) between the receiving transformer TR3 and the semiconductor chip CPH in the Y direction is smaller than the distance (spacing) between the transmitting transformer TR1 and the semiconductor chip CPH in the Y direction, and also smaller than the distance (spacing) between the receiving transformer TR2 and the semiconductor chip CPH in the Y direction. In the case of Figures 27 and 28, among the transformers TR1, TR2, and TR3, the receiving transformer TR3 is located closest to the semiconductor chip CPH, the transmitting transformer TR1 is located furthest from the semiconductor chip CPH, and the transmitting transformer TR2 is located between the transmitting transformer TR1 and the receiving transformer TR3. In another configuration, the positions of the transmitting transformer TR2 and the transmitting transformer TR1 can be swapped in the semiconductor chip CPC. However, even in this case, the receiving transformer TR3 is located closest to the semiconductor chip CPH among the transformers TR1, TR2, and TR3.

[0141] Furthermore, in this second embodiment, as can be seen from Figures 27 and 28, in the semiconductor chip CPC, pads PC1, PC2, and PC3 are arranged along the edge CPCa of the semiconductor chip CPC in a plan view. In the semiconductor chip CPC, pad PC3 is located closer to the semiconductor chip CPH than pads PC1 and PC2 in a plan view. That is, the distance (spacing) between pad PC3 and the semiconductor chip CPH in the Y direction is smaller than the distance (spacing) between pad PC2 and the semiconductor chip CPH in the Y direction, and also smaller than the distance (spacing) between pad PC1 and the semiconductor chip CPH in the Y direction. In the case of Figures 27 and 28, of pads PC1, PC2, and PC3, pad PC3 is located closest to the semiconductor chip CPH, pad PC1 is located furthest from the semiconductor chip CPH, and pad PC2 is located between pad PC1 and pad PC3. In another configuration, if the positions of the transmitting transformer TR1 and the transmitting transformer TR2 are swapped in the semiconductor chip CPC, it is preferable to swap the positions of the pad PC1 and the pad PC2 in the semiconductor chip CPC.

[0142] Furthermore, in this second embodiment, as can be seen from Figures 27 and 28, in the semiconductor chip CPH, pads PH1, PH2, and PH3 are arranged along the edge CPHa of the semiconductor chip CPH in a plan view. In the semiconductor chip CPH, the transmitting pad PH3 is located closer to the semiconductor chip CPL than the receiving pads PH1 and PH2 in a plan view. That is, the distance (spacing) between the transmitting pad PH3 and the semiconductor chip CPL in the X direction is smaller than the distance (spacing) between the receiving pad PH1 and the semiconductor chip CPL in the X direction, and also smaller than the distance (spacing) between the receiving pad PL2 and the semiconductor chip CPL in the X direction. In the case of Figures 27 and 28, of the pads PH1, PH2, and PH3, the transmitting pad PH3 is located closest to the semiconductor chip CPL, the receiving pad PH1 is located furthest from the semiconductor chip CPL, and the receiving pad PH2 is located between the transmitting pad PH3 and the receiving pad PH1. In another configuration, if the positions of the transmitting transformer TR1 and the transmitting transformer TR2 are swapped in the semiconductor chip CPC, it is preferable to swap the positions of the receiving pad PH1 and the receiving pad PH2 in the semiconductor chip CPH.

[0143] Furthermore, in this second embodiment, as can be seen from Figures 27 and 28, in the semiconductor chip CPL, pads PL1, PL2, and PL3 are arranged along the edge CPLa of the semiconductor chip CPL in a plan view. In the semiconductor chip CPL, the receiving pad PL3 is located closer to the semiconductor chip CPH than the transmitting pads PL1 and PL2 in a plan view. That is, in a plan view, the distance (spacing) between the receiving pad PL3 and the semiconductor chip CPH in the Y direction is smaller than the distance (spacing) between the transmitting pad PL1 and the semiconductor chip CPH in the Y direction, and also smaller than the distance (spacing) between the transmitting pad PL2 and the semiconductor chip CPH in the Y direction. In the case of Figures 27 and 28, of the pads PL1, PL2, and PL3, the receiving pad PL3 is located closest to the semiconductor chip CPH, the transmitting pad PL1 is located furthest from the semiconductor chip CPH, and the transmitting pad PL2 is located between the receiving pad PL3 and the transmitting pad PL1. In another configuration, if the positions of the transmitting transformer TR1 and the transmitting transformer TR2 are swapped in the semiconductor chip CPC, it is preferable to swap the positions of the transmitting pad PL1 and the transmitting pad PL2 in the semiconductor chip CPL.

[0144] Next, the main features and effects of this second embodiment will be described.

[0145] The arrangement of die pads DPL, DPH and semiconductor chips CPC, CPL, CPH is the same for semiconductor device PKG3 of this second embodiment as for semiconductor device PKG of the first embodiment described above.

[0146] Therefore, similar to Embodiment 1 above, in Embodiment 2, the Y-direction dimension of the semiconductor device PKG3 can be reduced without increasing the aspect ratio (ratio of the X-direction dimension to the Y-direction dimension) of the semiconductor chips CPC and CPL. This makes it possible to miniaturize the semiconductor device. Furthermore, since the aspect ratio of the semiconductor chips CPC and CPL can be suppressed, the risk of cracks occurring in the semiconductor chips CPL and CPC can be reduced, for example, when cutting a semiconductor wafer to obtain semiconductor chips or when transporting semiconductor chips. This makes it possible to improve the manufacturing yield of the semiconductor chips CPL and CPC and the manufacturing yield of the semiconductor device PKG3. In addition, in the semiconductor device PKG3, the semiconductor chips CPH, CPL, and CPC can be arranged in a balanced manner within the sealing section MR, so the difference between the amount (volume) of sealing resin located around the semiconductor chip CPH, the amount (volume) of sealing resin located around the semiconductor chip CPL, and the amount (volume) of sealing resin located around the semiconductor chip CPC can be reduced. As a result, warping of the semiconductor device PKG3 can be suppressed or prevented, and the flatness of the semiconductor device PKG3 can be improved.

[0147] The semiconductor device PKG3 of this second embodiment incorporates semiconductor chips CPC, CPL, and CPH. The semiconductor chip CPC has one or more transmitting transformers (here referred to as transformers TR1 and TR2) and one or more receiving transformers (here referred to as transformer TR3). The semiconductor chip CPL includes a plurality of transmitting pads PL1 and PL2 and a plurality of receiving pads PL3, and the semiconductor chip CPH includes a plurality of transmitting pads PH3 and a plurality of receiving pads PH1 and PH2.

[0148] In the semiconductor device PKG3 of this second embodiment, in the semiconductor chip CPC, the multiple transformers TR1, TR2, and TR3 are arranged along the edge CPCa of the semiconductor chip CPC (the edge CPCa opposite the edge CPLa of the semiconductor chip CPL) in a plan view, and the receiving transformer TR3 is positioned closer to the semiconductor chip CPH than the transmitting transformers TR1 and TR2 in a plan view. Furthermore, in the semiconductor chip CPH, the multiple transmitting pads PL3 are positioned closer to the semiconductor chip CPL than the multiple receiving pads PL1 and PL2 in a plan view.

[0149] This reduces the distance between the receiving transformer TR3 of the semiconductor chip CPC and the multiple transmitting pads PH3 of the semiconductor chip CPH in a plan view. As a result, the electrical resistance of the conductive path connecting the multiple transmitting pads PH3 of the semiconductor chip CPH and the primary coil (L3b) of the receiving transformer TR3 of the semiconductor chip CPC can be reduced. Specifically, the conductive path connecting the transmitting pads PH3 of the semiconductor chip CPH and the primary coil (L3b) of the receiving transformer TR3 of the semiconductor chip CPC includes wire BW6 and wiring WR3a. By reducing the distance between the receiving transformer TR3 of the semiconductor chip CPC and the multiple transmitting pads PH3 of the semiconductor chip CPH, the length of wire BW6 and the length of wiring WR3a can be reduced. This suppresses signal degradation and ensures accurate signal transmission when transmitting a signal from the transmitting circuit TX3 of the semiconductor chip CPH to the receiving circuit RX3 of the semiconductor chip CPL via the transformer TR3 of the semiconductor chip CPC.

[0150] Furthermore, the distance between the receiving transformer TR2 of semiconductor chip CPC and the receiving pad PL2 of semiconductor chip CPH, and the distance between the transmitting transformer TR1 of semiconductor chip CPC and the receiving pad PL1 of semiconductor chip CPL are larger than the distance between the receiving transformer TR3 of semiconductor chip CPC and the transmitting pad PL3 of semiconductor chip CPH. As a result, the length of one or both of wire BW5 and wiring WR2a is larger than the length of wire BW6 and wiring WR3a, and the length of one or both of wire BW4 and wiring WR1a is also larger. Consequently, the electrical resistance of the conductive path connecting the receiving pad PH2 and the secondary coil (L2b) of transmitting transformer TR2, and the electrical resistance of the conductive path connecting the receiving pad PH1 and the secondary coil (L1b) of transmitting transformer TR1 are larger than the electrical resistance of the conductive path connecting the transmitting pad PH3 and the primary coil (L3b) of receiving transformer TR3, but this has little effect on the quality of signal transmission.

[0151] Therefore, in this embodiment 2, by reducing the distance between the receiving transformer TR3 of the semiconductor chip CPC and the multiple transmitting pads PH3 of the semiconductor chip CPH, signals can be transmitted more accurately between the semiconductor chip CPH and the semiconductor chip CPL, thereby improving the performance of the semiconductor device.

[0152] Furthermore, in the semiconductor chip CPH, it is preferable that pads PH1, PH2, and PH3 are arranged along the edge CPHa of the semiconductor chip CPH (the edge CPLa opposite the edge CPCb of the semiconductor chip CPC) in a plan view. This makes it easier to connect each pad PH1, PH2, and PH3 of the semiconductor chip CPH to each pad PC4, PC5, and PC6 of the semiconductor chip CPC with wires BW, and also reduces the length of the wires BW (BW4, BW5, BW6) connecting each pad PH1, PH2, and PH3 of the semiconductor chip CPH to each pad PC4, PC5, and PC6 of the semiconductor chip CPC. As a result, control of the semiconductor device manufacturing process becomes easier. In addition, the performance of the semiconductor device can be further improved.

[0153] Furthermore, in a semiconductor chip CPL, it is preferable that pads PL1, PL2, and PL3 are arranged along the edge CPLa of the semiconductor chip CPL (the edge CPLa opposite to the edge CPCa of the semiconductor chip CPC) in a plan view. This makes it easier to connect each pad PL1, PL2, and PL3 of the semiconductor chip CPL to each pad PC1, PC2, and PC3 of the semiconductor chip CPC with wires BW, and also reduces the length of the wires BW (BW1, BW2, BW3) connecting each pad PL1, PL2, and PL3 of the semiconductor chip CPL to each pad PC1, PC2, and PC3 of the semiconductor chip CPC. As a result, control of the semiconductor device manufacturing process becomes easier. In addition, the performance of the semiconductor device can be further improved.

[0154] Furthermore, in a semiconductor chip CPL, it is preferable that the multiple receiving pads PL3 are positioned closer to the semiconductor chip CPH than the multiple transmitting pads PL1 and PL2 in a plan view. This makes it possible to reduce the distance between the receiving pad PL3 of the semiconductor chip CPL and the transformer TR3 of the semiconductor chip CPC, the distance between the transmitting pad PL2 of the semiconductor chip CPL and the transformer TR2 of the semiconductor chip CPC, and the distance between the transmitting pad PL1 of the semiconductor chip CPL and the transformer TR1 of the semiconductor chip CPC. As a result, the length of the wires BW (BW1, BW2, BW3) connecting each pad PL1, PL2, PL3 of the semiconductor chip CPL and each pad PC1, PC2, PC3 of the semiconductor chip CPC can be reduced. This makes it possible to further improve the performance of the semiconductor device.

[0155] In this second embodiment, the connection paths between the pads PH1, PH2, and PH3 of the semiconductor chip CPH and the transformers TR1, TR2, and TR3 of the semiconductor chip CPC are designed to prioritize reducing the distance between the pad PH3 of the semiconductor chip CPH and the transformer TR3 of the semiconductor chip CPC, thereby prioritizing the reduction of the electrical resistance of the conductive path connecting the pad PH3 of the semiconductor chip CPH and the transformer TR3 of the semiconductor chip CPC.

[0156] On the other hand, the electrical resistance of the conductive path connecting pad PL1 of semiconductor chip CPL to transformer TR1 of semiconductor chip CPC, the electrical resistance of the conductive path connecting pad PL2 of semiconductor chip CPL to transformer TR2 of semiconductor chip CPC, and the electrical resistance of the conductive path connecting pad PL3 of semiconductor chip CPL to transformer TR3 of semiconductor chip CPC can be made to be approximately the same. The reason for this is as follows: In semiconductor chip CPC, transformers TR1, TR2, and TR3 are arranged along the edge CPCa of semiconductor chip CPC in a plan view, and in semiconductor chip CPL, pads PL1, PL2, and PL3 are arranged along the edge CPLa of semiconductor chip CPL in a plan view. This makes it possible to make the distance between pad PL1 and transformer TR1, the distance between pad PL2 and transformer TR2, and the distance between pad PL3 and transformer TR3 to be approximately the same.

[0157] Therefore, the electrical resistance of the conductive path connecting the transmitting pad PL1 of the semiconductor chip CPL to the primary coil (L1a) of the transformer TR1, the electrical resistance of the conductive path connecting the transmitting pad PL2 of the semiconductor chip CPL to the primary coil (L2a) of the transformer TR2, and the electrical resistance of the conductive path connecting the transmitting pad PH3 of the semiconductor chip CPH to the primary coil (L3b) of the transformer TR3 can be suppressed. As a result, the electrical resistance of the conductive path connecting the transmitting circuit TX1 of the semiconductor chip CPL to the primary coil (L1a) of the transformer TR1, the electrical resistance of the conductive path connecting the transmitting circuit TX2 of the semiconductor chip CPL to the primary coil (L2a) of the transformer TR2, and the electrical resistance of the conductive path connecting the transmitting circuit TX3 of the semiconductor chip CPH to the primary coil (L3b) of the transformer TR3 can be suppressed. This allows for accurate signal transmission between the semiconductor chip CPL and the semiconductor chip CPH via transformers TR1, TR2, and TR3, thereby improving the performance of the semiconductor device.

[0158] The above embodiment 1 is particularly suitable when the number of receiving transformers in a semiconductor chip CPC is greater than the number of transmitting transformers. In the above embodiment 1, transformer TR1 corresponds to a transmitting transformer, and transformers TR2 and TR3 correspond to receiving transformers.

[0159] This second embodiment is particularly suitable when the number of transmitting transformers in a semiconductor chip CPC is greater than the number of receiving transformers. In this second embodiment, transformers TR1 and TR2 correspond to transmitting transformers, and transformer TR3 corresponds to a receiving transformer.

[0160] Furthermore, the first and second modified examples of Embodiment 1 can be applied to Embodiment 2.

[0161] The present invention has been described in detail above based on its embodiments, but it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0162] BDC,BDH,BDL Bonding material BDC1 Die Touch Film BT1,BT2 power supply BW, BW1, BW2, BW3, BW4, BW5, BW6 Wire CC control circuit CPC, CPC101, CPL, CPL101, CPH, CPH101 semiconductor chips CPCa, CPCb, CPLa, CPHa side DPH, DPH101, DPL, DPL101 Die Pad DPHa,DPLa top surface DPHb, DPLb bottom surface DPHc1, DPHc2, DPHc3, DPHc4 side view DPLc1, DPLc2, DPLc3, DPLc4 Side view DR drive circuit L1a,L1b,L2a,L2b,L3a,L3b Coil LD, LD1, LD1a, LD1b, LD2, LD2a, LD2b Lead LOD load MR sealing part MRa top surface MRb bottom side MRc1, MRc2, MRc3, MRc4 side view MW1,MW2,MW3 Multilayer wiring structure PA,PA2,PA3 Protective film PC1, PC2, PC3, PC4, PC5, PC6 Pad PH1, PH2, PH3, PH4 pads PL1, PL2, PL3, PL4 pads PKG, PKG1, PKG2, PKG3, PKG101 Semiconductor RX1, RX2, RX3 receiving circuits SB1, SB2, SB3 Semiconductor Substrates TS1, TS2 Power Transistors TX1, TX2, TX3 Transmitter Circuit WR1, WR1a, WR2, WR2a, WR3, WR3a wiring

Claims

1. The first chip mounting section and The second chip mounting section, The first semiconductor chip mounted on the first chip mounting section, The second semiconductor chip mounted on the second chip mounting section, A third semiconductor chip mounted on the first chip mounting section and having multiple transformers, A sealing body that seals the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the first chip mounting portion, and the second chip mounting portion, Equipped with, Each of the plurality of transformers has a primary coil and a secondary coil that are magnetically coupled to each other. The first chip mounting section and the second chip mounting section are adjacent to each other in the first direction. The first semiconductor chip and the third semiconductor chip are adjacent to each other in a second direction perpendicular to the first direction, In a plan view, the third semiconductor chip has a third side facing the first side of the first semiconductor chip and a fourth side facing the second side of the second semiconductor chip. The plurality of transformers are arranged along the fourth side of the third semiconductor chip in a plan view. The first semiconductor chip is A plurality of first transmitting pads electrically connected to a first transmitting circuit formed within the first semiconductor chip, A plurality of first receiving pads electrically connected to a first receiving circuit formed within the first semiconductor chip, It has, The second semiconductor chip is A plurality of second transmitting pads electrically connected to a second transmitting circuit formed within the second semiconductor chip, A plurality of second receiving pads electrically connected to a second receiving circuit formed within the second semiconductor chip, It has, The plurality of transformers of the third semiconductor chip are One or more first transformers used for transmitting signals from the first semiconductor chip to the second semiconductor chip, One or more second transformers used for transmitting signals from the second semiconductor chip to the first semiconductor chip, It has, The primary coils of one or more first transformers are electrically connected to the plurality of first transmitting pads of the first semiconductor chip. The secondary coils of one or more first transformers are electrically connected to the plurality of second receiving pads of the second semiconductor chip. The primary coils of one or more second transformers are electrically connected to the plurality of second transmitting pads of the second semiconductor chip. The secondary coils of one or more second transformers are electrically connected to the plurality of first receiving pads of the first semiconductor chip. The one or more first transformers are positioned closer to the first semiconductor chip than the one or more second transformers in a plan view. A semiconductor device wherein the plurality of first transmitting pads are located closer to the second semiconductor chip than the plurality of first receiving pads in a plan view.

2. In the semiconductor device described in claim 1, A semiconductor device in which, in the first semiconductor chip, the plurality of first transmitting pads and the plurality of first receiving pads are arranged along the first side of the first semiconductor chip in a plan view.

3. In the semiconductor device described in claim 2, A semiconductor device in which, in the second semiconductor chip, the plurality of second transmitting pads and the plurality of second receiving pads are arranged along the second side of the second semiconductor chip in a plan view.

4. In the semiconductor device according to claim 3, A semiconductor device wherein, in the second semiconductor chip, the plurality of second receiving pads are located closer to the first semiconductor chip than the plurality of second transmitting pads in a plan view.

5. In the semiconductor device described in claim 1, A semiconductor device wherein the number of second transformers constituting the plurality of transformers is greater than the number of first transformers constituting the plurality of transformers.

6. In the semiconductor device described in claim 1, Multiple leads, Multiple wires, Furthermore, A semiconductor device in which the sealant seals a portion of each of the plurality of leads and the plurality of wires.

7. In the semiconductor device according to claim 6, The third semiconductor chip includes a plurality of first pads electrically connected to the primary coils of one or more first transformers, a plurality of second pads electrically connected to the secondary coils of one or more first transformers, a plurality of third pads electrically connected to the primary coils of one or more second transformers, and a plurality of fourth pads electrically connected to the secondary coils of one or more second transformers. A semiconductor device comprising: a plurality of first wires electrically connecting the plurality of first transmitting pads of the first semiconductor chip and the plurality of first pads of the third semiconductor chip; a plurality of second wires electrically connecting the plurality of second receiving pads of the second semiconductor chip and the plurality of second pads of the third semiconductor chip; a plurality of third wires electrically connecting the plurality of second transmitting pads of the second semiconductor chip and the plurality of third pads of the third semiconductor chip; and a plurality of fourth wires electrically connecting the plurality of first receiving pads of the first semiconductor chip and the plurality of fourth pads of the third semiconductor chip.

8. In the semiconductor device according to claim 7, The first semiconductor chip further has a plurality of fifth pads, The second semiconductor chip further has a plurality of sixth pads, A semiconductor device further comprising: a plurality of fifth wires that electrically connect the plurality of fifth pads of the first semiconductor chip to a plurality of first leads among the plurality of leads; and a plurality of sixth wires that electrically connect the plurality of sixth pads of the second semiconductor chip to a plurality of second leads among the plurality of leads.

9. In the semiconductor device described in claim 1, The plurality of second transmitting pads are each electrically connected to the primary coil of one or more second transformers. A semiconductor device in which the plurality of first receiving pads are each electrically connected to the secondary coils of one or more second transformers.

10. The first chip mounting section and The second chip mounting section, The first semiconductor chip mounted on the first chip mounting section, The second semiconductor chip mounted on the second chip mounting section, A third semiconductor chip mounted on the first chip mounting section and having multiple transformers, A sealing body that seals the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the first chip mounting portion, and the second chip mounting portion, Equipped with, Each of the plurality of transformers has a primary coil and a secondary coil that are magnetically coupled to each other. The first chip mounting section and the second chip mounting section are adjacent to each other in the first direction. The first semiconductor chip and the third semiconductor chip are adjacent to each other in a second direction perpendicular to the first direction, In a plan view, the third semiconductor chip has a third side facing the first side of the first semiconductor chip and a fourth side facing the second side of the second semiconductor chip. The plurality of transformers are arranged along the third side of the third semiconductor chip in a plan view. The first semiconductor chip is A plurality of first transmitting pads electrically connected to a first transmitting circuit formed within the first semiconductor chip, A plurality of first receiving pads electrically connected to a first receiving circuit formed within the first semiconductor chip, It has, The second semiconductor chip is A plurality of second transmitting pads electrically connected to a second transmitting circuit formed within the second semiconductor chip, A plurality of second receiving pads electrically connected to a second receiving circuit formed within the second semiconductor chip, It has, The plurality of transformers of the third semiconductor chip are One or more first transformers used for transmitting signals from the first semiconductor chip to the second semiconductor chip, One or more second transformers used for transmitting signals from the second semiconductor chip to the first semiconductor chip, It has, The primary coils of one or more first transformers are electrically connected to the plurality of first transmitting pads of the first semiconductor chip. The secondary coils of one or more first transformers are electrically connected to the plurality of second receiving pads of the second semiconductor chip. The primary coils of one or more second transformers are electrically connected to the plurality of second transmitting pads of the second semiconductor chip. The secondary coils of one or more second transformers are electrically connected to the plurality of first receiving pads of the first semiconductor chip. The one or more second transformers are positioned closer to the second semiconductor chip than the one or more first transformers in a plan view. A semiconductor device wherein the plurality of second transmitting pads are located closer to the first semiconductor chip than the plurality of second receiving pads in a plan view.

11. In the semiconductor device according to claim 10, A semiconductor device in which, in the second semiconductor chip, the plurality of second transmitting pads and the plurality of second receiving pads are arranged along the second side of the second semiconductor chip in a plan view.

12. In the semiconductor device according to claim 11, A semiconductor device in which, in the first semiconductor chip, the plurality of first transmitting pads and the plurality of first receiving pads are arranged along the first side of the first semiconductor chip in a plan view.

13. In the semiconductor device according to claim 12, A semiconductor device wherein, in the first semiconductor chip, the plurality of first receiving pads are located closer to the second semiconductor chip than the plurality of first transmitting pads in a plan view.

14. In the semiconductor device according to claim 10, A semiconductor device wherein the number of first transformers constituting the plurality of transformers is greater than the number of second transformers constituting the plurality of transformers.

15. In the semiconductor device according to claim 10, Multiple leads, Multiple wires, Furthermore, A semiconductor device in which the sealant seals a portion of each of the plurality of leads and the plurality of wires.

16. In the semiconductor device according to claim 15, The third semiconductor chip includes a plurality of first pads electrically connected to the primary coils of one or more first transformers, a plurality of second pads electrically connected to the secondary coils of one or more first transformers, a plurality of third pads electrically connected to the primary coils of one or more second transformers, and a plurality of fourth pads electrically connected to the secondary coils of one or more second transformers. A semiconductor device comprising: a plurality of first wires electrically connecting the plurality of first transmitting pads of the first semiconductor chip and the plurality of first pads of the third semiconductor chip; a plurality of second wires electrically connecting the plurality of second receiving pads of the second semiconductor chip and the plurality of second pads of the third semiconductor chip; a plurality of third wires electrically connecting the plurality of second transmitting pads of the second semiconductor chip and the plurality of third pads of the third semiconductor chip; and a plurality of fourth wires electrically connecting the plurality of first receiving pads of the first semiconductor chip and the plurality of fourth pads of the third semiconductor chip.

17. In the semiconductor device according to claim 16, The first semiconductor chip further has a plurality of fifth pads, The second semiconductor chip further has a plurality of sixth pads, A semiconductor device further comprising: a plurality of fifth wires that electrically connect the plurality of fifth pads of the first semiconductor chip to a plurality of first leads among the plurality of leads; and a plurality of sixth wires that electrically connect the plurality of sixth pads of the second semiconductor chip to a plurality of second leads among the plurality of leads.

18. In the semiconductor device according to claim 10, Each of the plurality of first transmitting pads is electrically connected to the primary coil of one or more of the first transformers. A semiconductor device in which the plurality of second receiving pads are each electrically connected to the secondary coils of one or more first transformers.

Images