Programmable device having a hardening circuit for a predetermined digital signal processing function

Abstract

An exemplary programmable device includes a configuration memory configured to store configuration data, programmable logic having configurable functions based on the configuration data in the configuration memory, a signal conversion circuit, a digital processing circuit, and an endpoint circuit coupled to the signal conversion circuit via the digital processing circuit, the digital processing circuit including first one or more digital processing functions implemented as hardened circuits each having a predetermined function, and a second one or more processing functions implemented by configurable functions of the programmable logic.

Description

Technical Field

[0001] Technical Field Examples of the present disclosure generally relate to programmable devices, and more particularly to programmable devices having a hardened circuit for a given digital signal processing function.

Background Art

[0002] Background Art Integrated circuits (ICs) can be implemented to perform specific functions. One type of IC is a programmable IC, such as a field programmable gate array (FPGA) or a system on chip (SoC) that includes an FPGA-based programmable fabric. The FPGA fabric typically includes an array of programmable tiles. These programmable tiles can include, for example, input / output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and the like.

[0003] Each programmable tile typically includes both programmable interconnect circuitry and programmable logic circuitry. The programmable interconnect circuitry typically includes a number of interconnect lines of various lengths interconnected by programmable interconnect points (PIPs). The programmable logic circuitry implements user-designed logic using programmable elements that can include, for example, function generators, registers, arithmetic logic, and the like.

[0004] The programmable interconnect circuitry and the programmable logic circuitry are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data may be read from memory (e.g., an external PROM) or written to the FPGA by an external device. Next, the collective state of the individual memory cells determines the function of the FPGA.

[0005] Some applications of programmable ICs involve frequently executed functions. To conserve resources and reduce power consumption within the programmable fabric, it is desirable to provide hardened implementations of such frequently executed functions within the programmable IC, thereby enabling more integration than is possible due to thermal or die size limitations. [Overview of the Initiative] [Means for solving the problem]

[0006] Summary of the Invention A technique for providing a programmable device having a curing circuit is described. In one example, the programmable device comprises a configuration memory configured to store configuration data, a programmable logic having configurable functions based on the configuration data in the configuration memory, a signal conversion circuit, a digital processing circuit, and an endpoint circuit coupled to the signal conversion circuit via the digital processing circuit, wherein the digital processing circuit includes one or more first digital processing functions implemented as curing circuits each having a predetermined function, and one or more second processing functions implemented by the configurable functions of the programmable logic.

[0007] In another example, a programmable device comprises a configuration subsystem, at least one programmable subsystem having a configurable function determined by the configuration subsystem, a signal conversion circuit, a digital processing circuit, and an endpoint circuit coupled to the signal conversion circuit via the digital processing circuit, wherein the digital processing circuit includes at least one conversion circuit or at least one digital front-end (DFE) circuit, each implemented as a hardening circuit having a predetermined function.

[0008] In another example, a programmable device comprises a configuration subsystem, at least one programmable subsystem having a configurable function determined by the configuration subsystem, a signal conversion circuit, a digital processing circuit, and an endpoint circuit coupled to the signal conversion circuit via the digital processing circuit, wherein the digital processing circuit includes one or more first digital processing functions implemented as hardening circuits each having a predetermined function, and one or more second digital processing functions implemented by the configurable functions of at least one programmable subsystem.

[0009] These and other embodiments can be understood by referring to the detailed description below. Brief explanation of the drawing To ensure a detailed understanding of the above features, more specific explanations, which are briefly summarized above, can be obtained by referring to exemplary implementations, some of which are shown in the attached drawings. However, it should be noted that the attached drawings only show typical exemplary implementations and should therefore not be considered limiting in scope. [Brief explanation of the drawing]

[0010] [Figure 1A] Block diagram showing an example of a programmable IC. [Figure 1B] This example demonstrates a field-programmable gate array (FPGA) implementation of a programmable IC. [Figure 1C] A carbon cylinder illustrating a multi-integrated circuit (IC) programmable device. [Figure 2] This block diagram shows a floor plan of a programmable device as an example. [Figure 3] This is a block diagram illustrating a signal processing system implemented in a programmable device. [Figure 4] Block diagram showing a curing circuit as an example. [Figure 5] This is a block diagram illustrating a signal processing system implemented in a programmable device. [Figure 6] This is a block diagram illustrating a signal processing system implemented in a programmable device. [Figure 7] This is a block diagram illustrating a signal processing system implemented in a programmable device. [Figure 8] This is a block diagram illustrating a signal processing system implemented in a programmable device. [Modes for carrying out the invention]

[0011] For ease of understanding, the same reference number is used to indicate identical elements common to multiple figures, where possible. An element from one example may be usefully incorporated into another.

[0012] Detailed explanation Various features are described below with reference to the drawings. Note that the drawings may or may not be drawn to scale, and elements of similar structure or function are represented by the same reference numerals throughout the drawings. Note that the drawings are intended solely to facilitate the description of features. They are not intended as an exhaustive description of the claimed invention or as a limitation on the scope of the claimed invention. Furthermore, illustrated examples do not necessarily have all the embodiments or advantages shown. Embodiments or advantages described in relation to a particular example are not necessarily limited to that example and may be implemented in any other example, even if not shown or explicitly described as such.

[0013] Figure 1A is a block diagram illustrating a programmable device 1 in an example. Programmable device 1 includes programmable logic (PL) 3 (also called programmable fabric), input / output (IO) circuits 68, serial transceiver 67, signal conversion circuit 66, hardening circuit 90, configuration logic 25, and configuration memory 26. Programmable device 1 can be coupled with external circuits such as non-volatile memory 27, dynamic random access memory (DRAM) 28, and other circuits 29. In various examples, programmable device 1 further includes a processing system (PS) 2, network-on-chip (NOC) 55, data processing engine (DPE) array 56, peripheral interconnects 61, peripheral circuits 62, and die-to-die interconnects 64.

[0014] PL3 includes a logic cell 30, a support circuit 31, and a programmable interconnect 32. The logic cell 30 includes a circuit that can be configured to perform common logic functions for multiple inputs. The support circuit 31 includes dedicated circuits such as a digital signal processor and memory. The logic cell and the support circuit 31 can be interconnected using the programmable interconnect 32. Information for programming the logic cell 30, setting the parameters of the support circuit 31, and programming the programmable interconnect 32 is stored in configuration memory 26 by configuration logic 25. Configuration logic 25 can retrieve configuration data from non-volatile memory 27 or from any other source (e.g., DRAM 28 or other circuit 29). In some examples, configuration logic 25 includes a platform management controller (PMC) 72. The PMC 72 is configured to boot and configure subsystems of programmable device 1 such as PL3, PS2, NoC 55, DPE array 56, signal conversion circuit 66, and curing circuit 90.

[0015] The IO circuit 68 provides an external interface for subsystems of programmable device 1, such as PL3 and PS2. In some examples, the IO circuit 68 includes a memory controller 70 configured to interface with external memory (e.g., DRAM 28). Other connectivity circuits may include peripheral interconnects 61, peripheral circuits 62, and die-to-die interconnects 64. Peripheral interconnects 61 include bus interface circuits such as PCIe (Peripheral Component Interconnect Express) circuits. Peripheral circuits 62 include Universal Serial Bus (USB) ports, Ethernet® ports, Universal Asynchronous Transceiver (UART) ports, Serial Peripheral Interface (SPI) ports, General Purpose I / O (GPIO) ports, Serial Advanced Technology Attachment (SATA) ports, etc. Die-to-die interconnects 64 include circuits configured to interface like die-to-die interconnects in other programmable devices (for example, when programmable device 1 is one die in a multi-die integrated circuit package). Serial transceivers 67 include high-speed transmit / receive circuits configured to provide an external IO interface for programmable device 1.

[0016] The PS2 may include a microprocessor, memory, support circuits, I / O circuits, etc. The NOC55 is configured to provide communication between subsystems of the programmable device 1, such as between the PS2, PL3, curing circuit 90, and DPE array 56. The DPE array 56 may include an array of DPEs configured to perform data processing, such as an array of vector processors. The signal conversion circuit 66 includes an ADC (Analog to Digital Converter) and a DAC (Digital to Analog Converter).

[0017] The hardened circuit 90 comprises a circuit having a predetermined function. A given hardened circuit 90 can include one or more predetermined functions. Exemplary hardened circuits 90 include filters, mixers, sample rate converters, conversion circuits (e.g., fast Fourier transform (FFT)), etc. The hardened circuit 90 can be programmable to configure or select from a particular predetermined function. However, in contrast to the circuit of PL3, the hardened circuit 90 cannot be configured or reconfigured with different functions. For example, the hardened circuit 90 can include a filter having two predetermined selectable functions. Neither can a third function be added to the hardened circuit 90 nor can one of the two functions be removed from the hardened circuit 90. In contrast, a filter configured within PL3 can be reconfigured to add one or more additional functions or to remove one or more functions. Also, all of the filters configured within PL3 can be removed and replaced with other circuits. In contrast, the hardened circuit 90 cannot be removed from the programmable device 1 (however, it can be made unused as needed).

[0018] FIG. 1B shows an example of a field programmable gate array (FPGA) implementation of PL3. The PL3 shown in FIG. 1B can be used in any example of the programmable device described herein. PL3 includes a number of different programmable tiles including configurable logic blocks ("CLBs") 33, random access memory blocks ("BRAMs") 34, input / output blocks ("IOBs") 36, configuration and clocking logic ("CONFIG / CLOCKS") 42, digital signal processing blocks ("DSPs") 35, special input / output blocks ("I / O") 41 (e.g., configuration ports and clock ports), and other programmable logic 39 such as digital clock managers, analog-to-digital converters, system monitoring logic, etc.

[0019] In some PLs, each programmable tile can include at least one programmable interconnect element ("INT") 43 that has connections to the input and output terminals 48 of the programmable logic elements within the same tile, as shown by the example included in the upper part of FIG. 1B. Each programmable interconnect element 43 can also include connections for interconnecting segments 49 of adjacent programmable interconnect elements within the same tile or other tiles. Each programmable interconnect element 43 can also include connections for interconnecting segments 50 of general-purpose routing resources between logic blocks (not shown). The general-purpose routing resources can include a routing channel between a logic block (not shown) having tracks of an interconnect segment (e.g., interconnect segment 50) and a switch block (not shown) for connecting the interconnect segments. The interconnect segments of the general-purpose routing resources (e.g., interconnect segment 50) can span one or more logic blocks. The programmable interconnect element 43, together with the general-purpose routing resources, implements a programmable interconnect structure ("programmable interconnect") for the illustrated PL.

[0020] In exemplary implementations, the CLB 33 may include a configurable logic element ("CLE") 44 that can be programmed to implement a single programmable interconnect element ("INT") 43 in addition to user logic. The BRAM 34 may include one or more programmable interconnect elements in addition to BRAM logic elements ("BRL") 45. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the illustrated example, the BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. The DSP tile 35 may include a suitable number of programmable interconnect elements in addition to DSP logic elements ("DSPL") 46. The IOB 36 may include, for example, one instance of a programmable interconnect element 43 in addition to two instances of input / output logic elements ("IOL") 47. As will be apparent to those skilled in the art, the actual I / O pads connected to, for example, the I / O logic element 47 are not typically limited to the area of ​​the input / output logic element 47.

[0021] In the illustrated example, the horizontal region near the center of the die (shown in Figure 1B) is used for configuration, clock, and other control logic. The vertical column 51 extending from this horizontal region or column is used to distribute the clock and configuration signals across the width of the PL.

[0022] Some PLs that utilize the architecture shown in Figure 1B include additional logic blocks that break the regular columnar structure that makes up the majority of the PL. These additional logic blocks can be programmable blocks and / or dedicated logic.

[0023] It should be noted that Figure 1B is intended to show only an illustrative PL architecture. For example, the number of logical blocks in a row, the relative width of the row, the number and order of the rows, the type of logical blocks contained in the row, the relative size of the logical blocks, and the interconnections / logical implementations included in the top of Figure 1B are purely illustrative. For example, in a real PL, multiple adjacent CLB rows are usually included where CLBs appear to facilitate efficient implementation of user logic, but the number of adjacent CLB rows will vary depending on the overall size of the PL.

[0024] Figure 1C is a block diagram illustrating an example of a multi-die programmable device 54. The multi-die programmable device 54 includes a plurality of programmable devices 1, for example, programmable devices 1A, 1B, 1C, and 1D. In one example, each programmable device 1 is an IC die located on an interposer 60. Each programmable device 1 comprises a super-logic area (SLR) 53 of the programmable device 54, for example, SLR 53A, 53B, 53C, and 53D. The programmable devices 1 are interconnected via conductors (called very long wires (SLLs) 52) on the interposer 60 and via die interconnection circuits 64 located within each of the programmable devices 1.

[0025] Figure 2 is a block diagram showing a floor plan 200 of a programmable device 1 according to an example. In this example, the programmable device 1 includes rows of tiles containing the various circuits described above. Some circuits have been omitted for clarity in the example. In this example, the floor plan 200 shows rows of tiles having PL3; rows of tiles having DAC circuit 204; rows of tiles having ADC circuit 206; rows of tiles having die interconnect circuit 64; rows of tiles having curing circuit 90; rows of tiles having serial transceiver 67. The columnar tile structure can be interrupted by several subsystems such as PS2, NOC55, and DPE array 56.

[0026] In the examples described herein, the curing circuit 90 is used to implement a digital processing circuit between the DAC 204 / ADC 206 and endpoint circuits such as the serial transceiver 67 and / or the circuit configured within the PL3. To facilitate the formation of the digital processing circuit, the curing circuit 90 can be connected to the PL3, the signal conversion circuit 66, the NOC 55, the inter-die circuit 54, and the transceiver 67. The connection can be made by direct connection, or by any combination thereof, using the programmable interconnect in the PL3, via the NOC 55. In some examples, the floor plan 200 includes multiple tiles, each tile containing part or all of the curing circuit 90. This allows for scalability based on the number of ADC circuits 206 and DAC circuits 204.

[0027] In various applications, the programmable device 1 can be used to transmit and receive wirelessly received data using various radio frequency (RF) technologies. The ADC 206 is configured to generate a digital signal from an analog signal received from an external antenna (not shown). The resulting digital signal is then processed by some digital processing circuit and supplied to an endpoint circuit, which may be a circuit in PL 3, a transceiver 67, or some other subsystem. Conversely, the digital processing circuit can process the digital signal transmitted from the endpoint circuit and supply it to the DAC 204. The DAC 204 generates an analog signal from the digital signal, which is then transmitted using an external antenna (not shown).

[0028] In some applications, the digital processing circuits used in the aforementioned applications can be formed in PL3. However, this requires the use of PL resources that are not currently available for use by other circuits. Therefore, in some examples, at least a portion of the digital processing circuit is implemented using the curing circuit 90. This frees up PL resources for use by other circuits in the system. However, since the curing circuit 90 includes a connection to PL3, it has the flexibility to implement a portion of the digital processing circuit within PL3. This allows the user to provide custom logic along with the curing circuit 90 to implement the digital processing circuit according to the specific application. The custom logic may also be used to implement the control path of the digital processing circuit, thereby increasing flexibility while maintaining power efficiency when data processing remains in the curing area.

[0029] Figure 3 is a block diagram showing a signal processing system 300 implemented in an example programmable device 1. The signal processing system 300 includes a signal conversion circuit 66, a digital processing circuit 301, and an endpoint circuit 306. The signal conversion circuit 66 performs analog-to-digital conversion and digital-to-analog conversion as described above. The digital processing circuit 301 is configured to process inputs and outputs to the signal conversion circuit 66. In one example, the digital processing circuit 301 includes a first digital processing function implemented as a curing circuit 90, each having a predetermined function, and a second digital processing function implemented by configurable functions of the programmable subsystem 308 (e.g., configurable functions of PL3, DPE array 56, and / or PS2). By implementing several digital processing functions as curing circuits 90, the digital processing circuit 301 saves power and area in the programmable device. The types of digital processing functions that can be cured include common functions across various applications, or common functions used by various standards to which the application conforms (e.g., 4G / 5G wireless communication). Examples include FFT / iFFT conversion, channel filtering, upper and lower sample rate conversion, and crest factor reduction (CFR). The types of digital processing functions that can be programmed using the configurable functions of the programmable subsystem 308 include non-standard or application-specific functions. For example, custom logic 304 may include digital predistortion (DPD) logic (e.g., DPD circuitry), calibration logic (e.g., calibration circuitry), beamforming, automatic gain control (AGC), timing, and synchronization.

[0030] In one example, the digital processing circuit 301 includes a plurality of hardening circuits 90. The hardening circuits 90 may include, for example, one or more conversion circuits 320 (e.g., conversion functions) and one or more digital front-end (DFE) circuits 322 (e.g., DFE functions). The conversion circuits 320 may include conversion and inverse conversion circuits such as FFT and iFFT. The DFE circuits 322 may include filters, sample rate converters, mixers, signal combiners, etc.

[0031] In one example, the digital processing circuit 301 also includes one or more custom logics 304 programmed into at least one programmable subsystem 308 of the device. The programmable subsystem 308 may include, for example, a PL3, a PS2, a DPE array 56, etc. For example, the custom logic 304 may include a custom circuit configured in the PL3. The custom logic 304 may include a custom processor configured in the DPE array 56. The custom logic 304 may include a processor that runs custom software in the PS2. In the example, the custom logic 304 may include a combination of such implementation forms. The programmable subsystem 308 is programmed based on a configuration subsystem comprising a configuration memory 26 and a PMC 72. The configuration memory 26 includes configuration data 302 for the configured custom circuit in the PL3. The PMC 72 provides the configuration data to the DPE array 56 and the PS2, as well as the curing circuit 90. The curing circuit 90 and the custom logic 304 can be connected in any of various serial, parallel, or similar types of arrangements.

[0032] Figure 4 is a block diagram illustrating an example of a curing circuit 90. The curing circuit 90 includes various interfaces, including an interface 402 with one or more other curing circuits 90, an interface 404 with PL3, and an interface 406 with NOC55. Note that a given curing circuit 90 may include all or some of interfaces 402, 404, and 406. In some examples, the curing circuit 90 includes an interface 408 with PMC72 for its configuration. The curing circuit 90 may also include an interface 410 coupled to a specific control circuit (e.g., another curing circuit 90 or custom logic in a programmable subsystem). The control circuit can control the operation of the curing circuit 90 (e.g., the control circuit may be a state machine or a similar type of circuit).

[0033] Figure 5 is a block diagram showing a signal processing system 500 implemented in an example programmable device 1. The signal processing system 500 comprises a signal conversion circuit 66, a plurality of hardening circuits 90, a plurality of custom circuits 304 configured within PL3, and an endpoint circuit 306. The signal conversion circuit 66 performs analog-to-digital conversion and digital-to-analog conversion as described above. Each hardening circuit 90 performs one or more functions such as filtering, sample rate conversion, mixing, carrier coupling / splitting, time-to-frequency conversion, and frequency-to-time conversion. Each hardening circuit 90 may include an interface with PL3. Configuration data 302 loaded into configuration memory 26 configures PL3 using the custom circuits 304. Each custom circuit 304 can be connected to one or more hardening circuits 90. Each custom circuit 304 can be connected to one or more other custom circuits 304. One or more custom circuits 304 can be connected to the endpoint circuit 306. One or more custom circuits 304 can be coupled to the signal conversion circuit 66. One or more curing circuits 90 can be coupled to the endpoint circuit 306.

[0034] The hardening circuit 90 and the custom circuit 304 form a digital processing circuit 301 positioned between the signal conversion circuit 66 and the endpoint circuit 306. Although the endpoint circuit 306 is shown as an external component of the PL3 (e.g., a serial transceiver), the endpoint circuit 306 can be configured within the PL3.

[0035] During operation, the PMC72 receives information for programming the programmable device 1. The PMC72 loads the configuration data of PL3 into the configuration memory 26. The PMC72 also programs one or more curing circuits 90 to initialize, select, and perform other functions. As described above, each curing circuit 90 has one or more predetermined functions that cannot be changed. However, these functions may be programmable, and information for programming them may be received and provided by the PMC72. In contrast to the curing circuits 90, PL3 has configurable functions based on configuration data 302 stored in the configuration memory 26. After programming and configuration, the programmable device 1 implements a digital processing circuit 301 between the signal conversion circuit 66 and the endpoint circuit 306, which includes the curing circuits 90 and custom circuits 304.

[0036] Figure 6 is a block diagram showing a signal processing system 600 implemented in an example programmable device 1. The signal processing system 600 comprises a signal conversion circuit 66, a plurality of hardening circuits 90, a plurality of custom logics 304 configured within a DPE array 56, and an endpoint circuit 306. The signal conversion circuit 66 performs analog-to-digital conversion and digital-to-analog conversion as described above. Each hardening circuit 90 performs one or more functions such as filtering, sample rate conversion, mixing, carrier coupling / splitting, time-to-frequency conversion, and frequency-to-time conversion. Each hardening circuit 90 may include an interface with the DPE array 56 (e.g., via NOC 55). Each custom logic 304 can be connected to one or more hardening circuits 90. Each custom logic 304 can be connected to one or more other custom logics 304. One or more custom logics 304 can be connected to the endpoint circuit 306. One or more custom logics 304 can be coupled to the signal conversion circuit 66. One or more hardening circuits 90 can be coupled to the endpoint circuit 306.

[0037] The hardening circuit 90 and the custom circuit 304 form a digital processing circuit 301 positioned between the signal conversion circuit 66 and the endpoint circuit 306. Although the endpoint circuit 306 is shown as an external component of the PL3 (e.g., a serial transceiver), the endpoint circuit 306 can be configured within the PL3.

[0038] During operation, the PMC72 receives information for programming the programmable device 1. The PMC72 loads configuration data for the DPE array 56. The PMC72 also programs one or more curing circuits 90 to initialize, select, and perform other functions. As described above, each curing circuit 90 has one or more predetermined functions that cannot be changed. However, these functions may be programmable, and information for programming them may be received and provided by the PMC72. In contrast to the curing circuits 90, the DPE array 56 has configurable functions based on configuration data provided by the PMC72. After programming and configuration, the programmable device 1 implements a digital processing circuit 301 between the signal conversion circuit 66 and the endpoint circuit 306, which includes the curing circuits 90 and custom logic 304.

[0039] Figure 7 is a block diagram showing a signal processing system 700 implemented in an example programmable device 1. The signal processing system 700 comprises a signal conversion circuit 66, a plurality of hardening circuits 90, a plurality of custom logics 304 configured within the PS2, and an endpoint circuit 306. The signal conversion circuit 66 performs analog-to-digital conversion and digital-to-analog conversion as described above. Each hardening circuit 90 performs one or more functions such as filtering, sample rate conversion, mixing, carrier coupling / splitting, time-to-frequency conversion, and frequency-to-time conversion. Each hardening circuit 90 may include an interface with the DPE array 56 (e.g., via NOC 55). Each custom logic 304 is implemented by a processor running software within the PS2 and can be connected to one or more hardening circuits 90. Each custom logic 304 can be connected to one or more other custom logics 304. One or more custom logics 304 can be connected to the endpoint circuit 306. One or more custom logics 304 can be coupled to the signal conversion circuit 66. One or more hardening circuits 90 can be coupled to the endpoint circuit 306.

[0040] The hardening circuit 90 and the custom circuit 304 form a digital processing circuit 301 positioned between the signal conversion circuit 66 and the endpoint circuit 306. Although the endpoint circuit 306 is shown as an external component of the PL3 (e.g., a serial transceiver), the endpoint circuit 306 can be configured within the PL3.

[0041] During operation, the PMC72 receives information for programming the programmable device 1. The PMC72 loads configuration data for the PS2. The PMC72 also programs one or more curing circuits 90 to initialize, select, and perform other functions. As described above, each curing circuit 90 has one or more predetermined functions that cannot be changed. However, these functions may be programmable, and information for programming them may be received and provided by the PMC72. In contrast to the curing circuits 90, the PS2 has configurable functions based on configuration data provided by the PMC72. After programming and configuration, the programmable device 1 implements a digital processing circuit 301 between the signal conversion circuit 66 and the endpoint circuit 306, which includes the curing circuits 90 and custom logic 304.

[0042] Figure 8 is a block diagram illustrating an example signal processing circuit 800. The signal processing circuit 800 contains a mix of custom circuits configured within PL3 and hardening circuits 90. The serial transceiver 67 is coupled to a custom frequency-domain processor 802 implemented in PL3. The custom frequency-domain processor 802 performs some custom processing on the transmitted frequency-domain information. The custom frequency-domain processor 802 is coupled to a hardened inverse fast Fourier transform (iFFT) circuit 804, which is implemented using one or more hardening circuits 90. The iFFT circuit 804 converts the frequency-domain information into time-domain information. The iFFT circuit 804 is coupled to a custom time-domain processor 806 configured within PL3. The custom time-domain processor 806 performs some custom processing on the transmitted time-domain information.

[0043] In the reverse direction, the signal processing circuit 800 includes a custom time-domain processor 808, a hardened FFT 810, and a custom frequency-domain processor 812. The custom time-domain processor 808 performs some processing on the received time-domain information and is implemented within PL3. The hardened FFT is implemented using one or more hardening circuits 90 and is configured to convert the time-domain information into frequency-domain information. The custom frequency-domain processor 812 is configured within PL3 and functions to process the frequency-domain information. The frequency-domain processor 812 is coupled to the serial transceiver 67.

[0044] The output of the custom time-domain process 806 and the input of the custom time-domain process 808 are coupled to a switch 814. The switch 814 can be implemented in the PL3 or can be a curing circuit implemented by one or more curing circuits 90. The input / output of the switch 814 are coupled to a custom time-domain process 815. The custom time-domain process 815 is configured within the PL3 and performs some processing on the time-domain information transmitted or received. The custom time-domain process 815 is coupled to a curing filter 816, which is implemented using one or more curing circuits 90. The curing filter 816 may have a programmable length and programmable coefficients. The curing filter 816 can perform any type of filtering operation. The curing filter 816 is coupled to a cured sample rate converter 818, which is implemented using one or more curing circuits 90. The cured sample rate converter 818 functions to upsample or downsample the time-domain information. The curing sample rate converter 818 is coupled to a curing mixer and carrier combiner / splitter 820, which are implemented using one or more curing circuits 90. The curing sample rate converter 818 may be programmable for changes in sample rate depending on the signal bandwidth. The curing mixer and carrier combiner / splitter 820 are configured to modulate / demodulate time-domain information and aggregate or split multiple streams of time-domain signals based on a specific modulation scheme (e.g., orthogonal frequency division multiplexing (OFDM)). The mixer and carrier combiner / splitter 820 are coupled to a switch 822. The switch 822 can be implemented on PL3 or as a curing circuit implemented by one or more curing circuits 90.

[0045] The output of switch 822 is coupled to a hardened wave factor reduction (CFR) circuit 826, which is implemented using one or more hardening circuits 90. The output of the CFR circuit 826 is coupled to a custom DPD circuit 828 implemented in PL3. The output of the DPD circuit 828 is coupled to a DAC 830. The input of switch 822 is coupled to the output of ADC 824. The ADC 824 and DAC 830 are part of the signal conversion circuit 66.

[0046] The signal processing circuit 800 shown in Figure 8 is one specific example of alternative processing between the curing circuit 90 and a custom circuit configured within PL3, which is performed by a specific digital processing circuit between the signal conversion circuit and the endpoint circuit. Those skilled in the art will understand that other configurations are also possible, including configurations that include all signal processing circuit blocks implemented using the curing circuit 90.

[0047] While the above describes specific examples, other and further examples can be devised without deviating from their basic scope, and the scope is determined by the following claims.

Claims

1. Configuration memory configured to store configuration data, A programmable logic having configurable functions based on the configuration data in the configuration memory, Signal conversion circuit and Digital processing circuit and The endpoint circuit is coupled to the signal conversion circuit via the digital processing circuit. Equipped with, The digital processing circuit includes one or more first digital processing functions implemented as fixed function circuits, each having a predetermined function and selectable parameters, and one or more second digital processing functions implemented by the configurable functions of the programmable logic, wherein the predetermined function of the fixed function circuit is determined based on the selectable parameters of each of the predetermined functions, The aforementioned fixed-function circuit is a programmable device that cannot be configured or reconfigured with different functions.

2. The programmable device according to claim 1, wherein the first one or more digital processing functions implemented include the fixed function circuit including a digital front-end (DFE) function or a conversion function, the DFE function comprises at least one of a filter circuit, a sample rate conversion circuit, and a mixer circuit, and the conversion function comprises at least one of a time-frequency domain conversion circuit and a frequency-time domain conversion circuit.

3. The programmable device according to claim 1, wherein the second one or more digital processing functions implemented by the configurable functions of the programmable logic include at least one of a digital predistortion (DPD) circuit and a calibration circuit.

4. The programmable device according to claim 1, wherein the programmable logic comprises a row of programmable tiles and a programmable interconnect, and the fixed function circuit is located in at least one row of fixed function tiles adjacent to or scattered within the row of programmable tiles.

5. The programmable device according to claim 1, wherein the first one or more digital processing functions include one or more common functions that span multiple applications, or one or more common functions used by one or more standards to which the multiple applications conform, and the second one or more digital processing functions include one or more functions that are unique among the multiple applications, or one or more functions that do not conform to the one or more standards.

6. Multiple inter-die interface circuits Furthermore, The fixed function circuit within the digital processing circuit is coupled to the plurality of inter-die interface circuits. The programmable device according to claim 1.

7. Configuration subsystems and A programmable subsystem having a configurable function determined by the configuration subsystem, Signal conversion circuit and Digital processing circuit and The endpoint circuit is coupled to the signal conversion circuit via the digital processing circuit. Equipped with, The digital processing circuit includes at least one conversion circuit or at least one digital front-end (DFE) circuit, each implemented as a fixed-function circuit having a predetermined function and selectable parameters, wherein the predetermined function can be configured based on the selectable parameters. The aforementioned fixed function circuit cannot be configured or reconfigured with different functions. Programmable device.

8. The programmable device according to claim 1 or 7, wherein the signal conversion circuit comprises at least one analog-to-digital converter (ADC) circuit, at least one digital-to-analog converter (DAC) circuit, or at least one ADC and at least one DAC.

9. The programmable device according to claim 7, wherein the at least one programmable subsystem comprises at least one of programmable logic, an array of data processing engines (DPEs), and a processing system.

10. The programmable device according to claim 7, wherein the at least one DFE circuit includes one or more common functions that span multiple applications, or one or more common functions that are used by one or more standards to which the multiple applications conform.

11. The programmable device according to claim 7, wherein the at least one DFE circuit comprises at least one of a filter circuit, a sample rate conversion circuit, and a mixer circuit.

12. The programmable device according to claim 7, wherein the at least one conversion circuit comprises at least one of a time-frequency domain conversion circuit and a frequency-time domain conversion circuit.

13. Configuration subsystems and A programmable subsystem having a configurable function determined by the configuration subsystem, Signal conversion circuit and Digital processing circuit and The endpoint circuit is coupled to the signal conversion circuit via the digital processing circuit. Equipped with, The digital processing circuit includes one or more first digital processing functions implemented as fixed-function circuits, each having a predetermined function and selectable parameters, and one or more second digital processing functions implemented by the configurable functions of the at least one programmable subsystem, wherein the predetermined function of the fixed-function circuit is configurable based on the respective selectable parameters. The aforementioned fixed function circuit cannot be configured or reconfigured with different functions. Programmable device.

14. The programmable device according to claim 13, wherein the at least one programmable subsystem comprises at least one of programmable logic, an array of data processing engines (DPEs), and a processing system.

15. The programmable device according to claim 1 or 13, wherein the first one or more digital processing functions implemented include the fixed function circuit, which includes a digital front-end (DFE) function or a conversion function.

16. The programmable device according to claim 1 or 13, wherein the first one or more digital processing functions include one or more common functions that span multiple applications, or one or more common functions used by one or more standards to which the multiple applications conform.

17. The programmable device according to claim 13, wherein the first one or more digital processing functions include one or more common functions that span multiple applications, or one or more common functions used by one or more standards to which the multiple applications conform, and the second one or more digital processing functions include one or more functions that are unique among the multiple applications, or one or more functions that do not conform to the one or more standards.

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