Information processing system

Abstract

To provide an information processing system capable of improving overall performance while reducing a load applied to a host.SOLUTION: According to an embodiment, an information processing system comprises a host and a plurality of memory systems each of which includes a controller and a non-volatile memory. A first memory system stores first data in a first non-volatile memory. A second memory system stores second data in a second non-volatile memory. The host transmits first update data updated from the first data to the first memory system and second update data updated from the second data to the second memory system. The first memory system subjects at least the first data and first update data to XOR operation to generate first XOR data, and transmits the generated data to the second memory system. The second memory system subjects the second data, second update data, and first XOR data to XOR operation to generate second XOR data, and transmits the generated data to a third memory system.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] Embodiments of the present invention relate to an information processing system including a memory system having a non-volatile memory.

Background Art

[0002] In recent years, memory systems having a non-volatile memory and information processing systems having a host and a plurality of memory systems have been widely spread. As one of such memory systems, a solid state drive (SSD) having a NAND type flash memory is known. The SSD is used as a main storage of various computing devices.

[0003] In order to improve the fault tolerance of an information processing system, Redundant Arrays of Independent (Inexpensive) Disks (RAID) may be used. RAID is a technology that uses a plurality of memory systems for storing data to improve the redundancy and access performance of the stored data. For example, in RAID-5, data to be written and parity (error correction code: ECC) for this data are distributed and stored in a plurality of memory systems. Thereby, for example, even if a memory system in which a part of the data is stored fails, the data stored in the failed memory system can be restored using other data and parity stored in other memory systems.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

[0005] When updating data stored in multiple memory systems that make up a RAID array, or when recovering data stored in a failed memory system and rebuilding the RAID array, the load on the host connected to the multiple memory systems can increase. In such cases, data transfer to a specific memory system may become concentrated. Insufficient bus bandwidth to that specific memory system may degrade the performance of the entire information processing system.

[0006] One embodiment provides an information processing system that can improve overall performance while reducing the load on the host. [Means for solving the problem]

[0007] According to one embodiment, the information processing system comprises a host and a plurality of memory systems, each including a controller and a non-volatile memory. The controller of the first memory system among the plurality of memory systems stores first data in the first non-volatile memory. The controller of the second memory system among the plurality of memory systems stores second data in the second non-volatile memory. The first data and the second data constitute part of a single error correction code frame. When the first data and the second data are updated, the host transmits the first updated data, updated from the first data, to the first memory system and the second updated data, updated from the second data, to the second memory system. The controller of the first memory system generates first exclusive OR data by performing an exclusive OR operation on at least the first data and the first updated data, and transmits the first exclusive OR data to the second memory system. The controller of the second memory system generates the second exclusive OR data by performing an exclusive OR operation between the second data, the second update data, and the first exclusive OR data, and transmits the second exclusive OR data to the third memory system among the multiple memory systems. [Brief explanation of the drawing]

[0008] [Figure 1] A block diagram showing an example configuration of an information processing system according to the first embodiment. [Figure 2] A block diagram showing an example configuration of a memory system included in the information processing system according to the first embodiment. [Figure 3] A diagram showing an example of sequential write operation in the information processing system according to the first embodiment. [Figure 4] A diagram showing the first update operation in the information processing system relating to the comparative example. [Figure 5] A diagram showing the second update operation in the information processing system related to the comparative example. [Figure 6] A diagram showing the third update operation in the information processing system related to the comparative example. [Figure 7] A diagram showing an example of a fourth update operation in the information processing system according to the first embodiment. [Figure 8] A sequence diagram showing a specific example of the fourth update operation in the information processing system according to the first embodiment. [Figure 9] A diagram showing a specific example of the operation of the first memory system within the information processing system according to the first embodiment. [Figure 10] A diagram showing an example of a fifth update operation in the information processing system according to the first embodiment. [Figure 11] A sequence diagram showing a specific example of the fifth update operation in the information processing system according to the first embodiment. [Figure 12] A diagram showing an example of the first rebuild operation in the information processing system according to the second embodiment. [Figure 13] A sequence diagram showing a specific example of the first rebuild operation in the information processing system according to the second embodiment. [Figure 14] A diagram showing an example of a second rebuild operation in the information processing system according to the second embodiment. [Figure 15]Sequence diagram showing a specific example of the second rebuild operation in the information processing system according to the second embodiment. [Figure 16] Diagram showing a specific example of the operation in the first memory system within the information processing system according to the second embodiment.

Modes for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described with reference to the drawings.

[0010] (First Embodiment) First, referring to FIG. 1, the configuration of the information processing system 1 according to the first embodiment will be described. The information processing system 1 includes a host device 2, a plurality of memory systems 3, and a switch, 4.

[0011] The host device 2 may be a storage server that stores a large amount and diverse data in a plurality of memory systems 3, or may be a server or a personal computer. Hereinafter, the host device 2 will also be referred to as the host 2.

[0012] The plurality of memory systems, 3, are memory systems that constitute Redundant Arrays of Independent Disks (RAID). Hereinafter, the case where the plurality of memory systems 3 constitute RAID-5 will be exemplified. Also, in FIG. 1, the case where the plurality of memory systems 3 are four memory systems 3-1, 3-2, 3-3, and 3-4 is shown, but the plurality of memory systems 3 may be, for example, any number of memory systems of three or more. Hereinafter, a specific one of the plurality of memory systems 3 will also be referred to as the memory system 3.

[0013] Memory system 3 is a semiconductor storage device configured to write data to non-volatile memory, such as NAND flash memory, and to read data from non-volatile memory. Memory system 3 is also referred to as a storage device. Memory system 3 can be implemented, for example, as a solid-state drive (SSD).

[0014] The memory system 3 can be used as storage for the host 2. The memory system 3 may be built into the host 2 or it may be connected to the host 2 via a cable or network.

[0015] Switch 4 is a device that interconnects the host 2 and the multiple memory systems 3. Switch 4 includes a control circuit that controls the communication between the host 2 and the multiple memory systems 3.

[0016] The interface for connecting host 2 and multiple memory systems 3 via switch 4 is PCI Express. TM (PCIe TM ), NVM Express TM (NVMe TM It complies with standards such as ). Hereafter, switch 4 will also be referred to as PCIe switch 4.

[0017] The following describes example configurations for Host 2 and Memory System 3.

[0018] (Example configuration for Host 2) Host 2 includes, for example, a central processing unit (CPU) 21 and random access memory (RAM) 22.

[0019] The CPU 21 is, for example, at least one processor. The CPU 21 controls the operation of various components within the host 2. The CPU 21 also controls communication between the host 2 and the memory system 3. The CPU 21 sends various commands to the memory system 3. Commands sent to the memory system 3 include, for example, read commands, write commands, XOR commands, and XOR / write commands. An XOR command is a command that requests an exclusive OR (XOR) operation of two or more data. An XOR / write command is a command that requests an XOR operation of two or more data and the writing of the data. The host 2 may also be provided with a control circuit (interface) that controls communication between the host 2 and the memory system 3. The CPU 21 communicates with the memory system 3 via this control circuit.

[0020] RAM22 is volatile memory. RAM22 can be implemented, for example, as dynamic random access memory (DRAM) or static random access memory (SRAM). The memory area of ​​RAM22 is allocated, for example, as a buffer area where data is temporarily stored. The buffer area stores, for example, data to be written to memory system 3 and data read from memory system 3.

[0021] (Example configuration of memory system 3) Figure 2 is a block diagram showing an example configuration of the memory system 3.

[0022] The memory system 3 includes, for example, a non-volatile memory 5, a DRAM 6, and a controller 7.

[0023] Non-volatile memory 5 is, for example, NAND flash memory. Hereafter, non-volatile memory 5 will be referred to as NAND flash memory 5.

[0024] The NAND flash memory 5 includes multiple blocks B0, B1, B2, ..., Bm-1. Each of the multiple blocks B0, B1, B2, ..., Bm-1 includes multiple pages P0, ..., Pn-1. A block functions as the smallest unit of data erasure operation. A block may also be referred to as an "erasure block" or "physical block". Each of the multiple pages P0, ..., Pn-1 includes multiple memory cells connected to a single word line. A page functions as the unit of data write operation and data read operation. The word line may also function as the unit of data write operation and data read operation.

[0025] There is an upper limit to the number of program / erase cycles (P / E cycles) for each block, which is called the maximum number of P / E cycles. One P / E cycle for a block includes a data erase operation to erase all memory cells in that block, and a data write operation (program operation) to write data to each page of that block.

[0026] DRAM6 is a volatile memory. RAM such as DRAM6 is provided with, for example, a storage area for firmware (FW), a cache area for the logical-physical address translation table 31, and a buffer area for temporarily storing data.

[0027] FW is a program for controlling the operation of controller 7. FW is loaded, for example, from NAND flash memory 5 into DRAM 6.

[0028] The logical-physical address translation table 31 manages the mapping between each logical address and each physical address of the NAND flash memory 5. A logical address is an address used by the host 2 to address the memory system 3. A logical address is, for example, a logical block address (LBA).

[0029] Controller 7 functions as a memory controller configured to control the NAND flash memory 5.

[0030] The controller 7 may function as a flash translation layer (FTL) configured to perform data management and block management of the NAND flash memory 5. The data management performed by this FTL includes (1) managing mapping information that shows the correspondence between each logical address and each physical address of the NAND flash memory 5, and (2) processing to conceal the difference between page-level data read / write operations and block-level data erase operations. Block management includes bad block management, wear leveling, and garbage collection.

[0031] The mapping between each logical address and each physical address is managed using a logical-physical address translation table 31. The controller 7 uses the logical-physical address translation table 31 to manage the mapping between each logical address and each physical address in specific management size units. The physical address corresponding to a given logical address indicates the physical storage location in the NAND flash memory 5 where the data for that logical address is written. The controller 7 uses the logical-physical address translation table 31 to manage the storage area of ​​the NAND flash memory 5 as multiple logically divided storage areas. These multiple storage areas each correspond to multiple logical addresses. In other words, each of these multiple storage areas is identified by a single logical address. The logical-physical address translation table 31 may be loaded from the NAND flash memory 5 into the DRAM 6 when the memory system 3 is started.

[0032] Data can only be written to a single page once per P / E cycle. Therefore, the controller 7 writes the updated data corresponding to a certain logical address to a different physical memory location, rather than to the physical memory location where the previous data corresponding to that logical address is stored. The controller 7 then invalidates the previous data by updating the logical-physical address translation table 31 to associate this logical address with this different physical memory location. Data referenced by the logical-physical address translation table 31 (i.e., data associated with a logical address) is called valid data. Data not associated with any logical address is called invalid data. Valid data is data that may be read by host 2 later. Invalid data is data that can no longer be read by host 2.

[0033] The controller 7 includes, for example, a host interface (host I / F) 11, a NAND interface (NAND I / F) 12, a DRAM interface (DRAM I / F) 13, and a CPU 14. These host I / F 11, NAND I / F 12, DRAM I / F 13, and CPU 14 are connected, for example, via a bus 10.

[0034] The host interface 11 functions as a circuit that receives various commands and data from host 2 via PCIe switch 4. The host interface 11 also functions as a circuit that transmits responses to commands and data to host 2 via PCIe switch 4. Furthermore, the host interface 11 may function as a circuit that receives various commands, data, and responses to commands from another memory system 3 via PCIe switch 4. The host interface 11 may also function as a circuit that transmits commands, data, and responses to commands to another memory system 3 via PCIe switch 4.

[0035] The NAND I / F12 electrically connects the controller 7 and the NAND flash memory 5. The NAND I / F12 supports interface standards such as Toggle DDR and Open NAND Flash Interface (ONFI).

[0036] The NAND I / F 12 functions as a NAND control circuit configured to control the NAND flash memory 5. The NAND I / F 12 may be connected to multiple memory chips within the NAND flash memory 5 via multiple channels. By driving multiple memory chips in parallel, the access to the NAND flash memory 5 can be made wider bandwidth.

[0037] The DRAM I / F13 functions as a DRAM control circuit configured to control access to DRAM6.

[0038] The CPU 14 is a processor configured to control the host I / F 11, NAND I / F 12, and DRAM I / F 13. The CPU 14 performs various processes by executing firmware (FW) loaded from the NAND flash memory 5 into the DRAM 6. The FW is a control program containing a set of instructions that causes the CPU 14 to perform various processes. The CPU 14 can perform command processing and other operations to handle various commands from the host 2. The operation of the CPU 14 is controlled by the FW executed by the CPU 14.

[0039] The functions of each part within the controller 7 may be implemented by dedicated hardware within the controller 7, or by the CPU 14 executing firmware.

[0040] The CPU 14 functions, for example, as a command receiving unit 141, a read processing unit 142, an XOR processing unit 143, and a write processing unit 144. The CPU 14 functions in each of these areas, for example, by executing firmware.

[0041] The command receiving unit 141 receives commands sent from host 2 or another memory system 3. Based on the received commands, the command receiving unit 141 controls the read processing unit 142, the XOR processing unit 143, and the write processing unit 144. Specifically, the command receiving unit 141 instructs the read processing unit 142 to read data from the NAND flash memory 5. The command receiving unit 141 instructs the XOR processing unit 143 to perform an XOR operation on two or more data. The command receiving unit 141 instructs the write processing unit 144 to write data to the NAND flash memory 5. The command receiving unit 141 sends a response to the command to the host 2 or memory system 3 that sent the command. The command receiving unit 141 may also send the command and data to another memory system 3.

[0042] The read processing unit 142 reads data from the NAND flash memory 5 in response to instructions from the command receiving unit 141.

[0043] The XOR processing unit 143 performs an XOR operation on two or more data points in response to instructions from the command receiving unit 141.

[0044] The write processing unit 144 writes data to the NAND flash memory 5 in response to instructions from the command receiving unit 141.

[0045] Specific examples of the operations performed by the command receiving unit 141, read processing unit 142, XOR processing unit 143, and write processing unit 144 will be described later with reference to Figure 9.

[0046] Here, we will explain the sequential write operation in information processing system 1.

[0047] Figure 3 shows an example of sequential write operation in information processing system 1. Sequential write operation is an operation in which host 2 writes data sequentially to all four memory systems 3-1, 3-2, 3-3, and 3-4.

[0048] Host 2's DRAM 22 stores user data 51D that should be written to memory system 3.

[0049] The CPU 21 of host 2 generates an error correction code (ECC) for user data 51D to be written to memory system 3 when the amount of user data 51D to be written reaches a specific unit. This specific unit corresponds, for example, to the total amount of data that can be written in a single data write operation to each of the three memory systems 3. The amount of data that can be written in a single data write operation to one memory system 3 is also called the write unit. The ECC is data used to correct user data that has encountered errors. The ECC is, for example, XOR parity. Below, we will illustrate the case where the ECC is XOR parity. Also, XOR parity will be simply referred to as parity.

[0050] Specifically, the CPU 21 obtains user data 511, 512, and 513 (i.e., first user data 511, second user data 512, and third user data 513) which are three write units obtained by dividing a specific unit of user data 51D. Then, the CPU 21 generates parity 51P by performing an XOR operation on the three user data 511, 512, and 513. The CPU 21 stores the generated parity 51P in, for example, the DRAM 22. The three user data 511, 512, and 513 and the parity 51P have the same data length. The three user data 511, 512, and 513 and the parity 51P constitute one ECC frame 51E. An ECC frame is a data unit that includes parity and the user data protected by the parity. In other words, the three user data 511, 512, and 513 are protected by parity 51P. Parity 51P is updated in response to at least one of the three user data 511, 512, and 513 being updated.

[0051] Next, the CPU 21 writes three user data sets 511, 512, and 513, along with parity 51P, to four memory systems 3-1, 3-2, 3-3, and 3-4, respectively, via the PCIe switch 4.

[0052] Specifically, for example, the CPU 21 sends a write command to the first memory system 3-1 requesting to write the first user data 511 (Figure 3 (1)). The CPU 21 sends a write command to the second memory system 3-2 requesting to write the second user data 512 (Figure 3 (2)). The CPU 21 sends a write command to the third memory system 3-3 requesting to write the third user data 513 (Figure 3 (3)). The CPU 21 sends a write command to the fourth memory system 3-4 requesting to write the parity 51P (Figure 3 (4)). Note that the CPU 21 determines, for example, which of the four memory systems 3-1, 3-2, 3-3, and 3-4 to write the first user data 511, second user data 512, third user data 513, and parity 51P to, according to a specific rule. The destinations for writing the first user data 511, second user data 512, third user data 513, and parity 51P are not limited to the examples described above. For example, the CPU 21 may send write commands such that the first user data 511 is written to the second memory system 3-2, the second user data 512 is written to the third memory system 3-3, the third user data 513 is written to the fourth memory system 3-4, and parity 51P is written to the first memory system 3-1.

[0053] Upon receiving a write command from host 2, the first memory system 3-1 receives the first user data 511 stored in host 2's DRAM 22 via PCIe switch 4. The first memory system 3-1 then writes the first user data 511 to the NAND flash memory 5 within the first memory system 3-1.

[0054] Upon receiving a write command from host 2, the second memory system 3-2 receives the second user data 512 stored in host 2's DRAM 22 via PCIe switch 4. The second memory system 3-2 then writes the second user data 512 to the NAND flash memory 5 within the second memory system 3-2.

[0055] In response to receiving a write command from host 2, the third memory system 3-3 receives the third user data 513 stored in host 2's DRAM 22 via PCIe switch 4. The third memory system 3-3 then writes the third user data 513 to the NAND flash memory 5 within the third memory system 3-3.

[0056] In response to receiving a write command from host 2, the fourth memory system 3-4 receives the parity 51P stored in host 2's DRAM 22 via PCIe switch 4. The fourth memory system 3-4 then writes the parity 51P to the NAND flash memory 5 within the fourth memory system 3-4.

[0057] Through the sequential write operation described above, the information processing system 1 distributes and writes the first user data 511, second user data 512, third user data 513, and parity 51P, which constitute one ECC frame 51E, to four memory systems 3-1, 3-2, 3-3, and 3-4. As a result, even if one of the four memory systems 3-1, 3-2, 3-3, and 3-4 fails, the data stored in the failed memory system 3 can be restored using the data stored in the other memory systems 3.

[0058] During sequential write operation, four input / output (I / O) operations occur between host 2 and memory system 3. These four I / O operations are related to four write operations from host 2 to memory system 3 (Write I / O). The number of I / O operations is an indicator of bus bandwidth usage due to communication between host 2 and memory system 3 via PCIe switch 4. Furthermore, parity 51P is generated using the resources of host 2 (more specifically, CPU 21 and DRAM 22).

[0059] Next, we will describe the operation for updating a portion of the user data 51D written to the memory system 3. The operation for updating a portion of the user data 51D written to the memory system 3 will be called the update operation. The update operation includes a random write operation.

[0060] First, the update operation in the comparative information processing system 1A will be explained with reference to Figures 4 to 6. The comparative information processing system 1A includes a host 2A, multiple memory systems 3A, and a PCIe switch 4A. The host 2A and the multiple memory systems 3A can communicate with each other via the PCIe switch 4A. The host 2A is equipped with a CPU 21A and a DRAM 22A. Each of the multiple memory systems 3A is equipped with NAND flash memory. The multiple memory systems 3A constitute RAID-5. The multiple memory systems 3A include four memory systems 3-1A, 3-2A, 3-3A, and 3-4A. Here, it is assumed that the first user data 511, the second user data 512, the third user data 513, and parity 51P are stored in the four memory systems 3-1A, 3-2A, 3-3A, and 3-4A, respectively, by an operation similar to the sequential write operation described above with reference to Figure 3.

[0061] Figure 4 shows the first update operation in the information processing system 1A of the comparative example. The first update operation is an operation to update the first user data 511 stored in the first memory system 3-1A to the first updated user data 511-U.

[0062] Host 2A's DRAM 22A stores the first updated user data 511-U.

[0063] The CPU 21A of host 2A sends a read command to the first memory system 3-1A requesting to read the first user data 511 (Figure 4 (1)).

[0064] The first memory system 3-1A reads the first user data 511 from the NAND flash memory within the first memory system 3-1A in response to a read command from the host 2A. Then, the first memory system 3-1A transmits the first user data 511 to the host 2A.

[0065] The CPU 21A of the host 21 stores the first user data 511 received from the first memory system 3-1A into the DRAM 22A. The CPU 21A generates the first XOR data 521 by performing an XOR operation between the first user data 511 and the first updated user data 511-U. The first XOR data 521 is stored, for example, in the DRAM 22A. Then, the CPU 21A sends a write command to the first memory system 3-1A requesting that the first updated user data 511-U be written (Figure 4 (2)).

[0066] Upon receiving a write command from host 2A, the first memory system 3-1A receives the first update user data 511-U stored in host 2A's DRAM 22A. The first memory system 3-1A then writes the first update user data 511-U to the NAND flash memory within the first memory system 3-1A.

[0067] Next, the CPU 21A of host 2A sends a read command to the fourth memory system 3-4A requesting to read parity 51P (Figure 4, (3)).

[0068] The fourth memory system 3-4A reads parity 51P from the NAND flash memory within the fourth memory system 3-4A in response to a read command from host 2A. Then, the fourth memory system 3-4A transmits parity 51P to host 2A.

[0069] The CPU 21A of the host 21 stores the parity 51P received from the fourth memory system 3-4A in the DRAM 22A. The CPU 21A generates an updated parity 51P-U by performing an XOR operation between the first XOR data 521 stored in the DRAM 22A and the parity 51P. The updated parity 51P-U is the parity that has been modified in accordance with the update from the first user data 511 to the first updated user data 511-U. In other words, the first updated user data 511-U, the second user data 512, the third user data 513, and the updated parity 51P-U constitute an ECC frame. The CPU 21A sends a write command to the fourth memory system 3-4A requesting that the updated parity 51P-U be written ((4) in Figure 4).

[0070] In response to receiving a write command from host 2A, the fourth memory system 3-4A receives the update parity 51P-U stored in host 2A's DRAM 22A. The fourth memory system 3-4A then writes the update parity 51P-U to the NAND flash memory within the fourth memory system 3-4A.

[0071] As a result of the above first update operation, in the information processing system 1A, the first user data 511 stored in the first memory system 3-1A is updated to the first updated user data 511-U, and the parity 51P stored in the fourth memory system 3-4A is updated to the updated parity 51P-U.

[0072] The first update operation involves four I / O operations from host 2A to memory system 3A. These four I / O operations include two write I / O operations and two read I / O operations (read I / O operations) from host 2A to memory system 3A. The update parity 51P-U is generated using the resources of host 2A (more specifically, CPU 21A and DRAM 22A).

[0073] Figure 5 shows the second update operation in the information processing system 1A of the comparative example. The second update operation is an operation to update the first user data 511 stored in the first memory system 3-1A to the first updated user data 511-U while reducing the resources of the host 2A used.

[0074] Host 2A's DRAM 22A stores the first updated user data 511-U.

[0075] The CPU 21A of host 2A sends a command (XOR / write command) to the first memory system 3-1A requesting an XOR operation and the writing of the first updated user data 511-U (Figure 5 (1)).

[0076] Upon receiving an XOR / write command from host 2A, the first memory system 3-1A receives the first update user data 511-U from host 2A. The first memory system 3-1A also reads the first user data 511 from the NAND flash memory within the first memory system 3-1A. The first memory system 3-1A generates the first XOR data 521 by performing an XOR operation between the first user data 511 and the first update user data 511-U. The first XOR data 521 is stored in the internal buffer 61-1A of the first memory system 3-1A. Then, the first memory system 3-1A writes the first update user data 511-U to the NAND flash memory within the first memory system 3-1A.

[0077] Next, the CPU 21A of host 2A sends an XOR / write command to the fourth memory system 3-4A requesting an XOR operation and the writing of the updated parity 51P-U (Figure 5 (2)).

[0078] In response to receiving an XOR / write command from host 2A, the fourth memory system 3-4A receives the first XOR data 521 from the first memory system 3-1A. The fourth memory system 3-4A reads the parity 51P from the NAND flash memory within the fourth memory system 3-4A. The fourth memory system 3-4A generates an updated parity 51P-U by performing an XOR operation between the first XOR data 521 and the parity 51P. Then, the fourth memory system 3-4A writes the updated parity 51P-U to the NAND flash memory within the fourth memory system 3-4A.

[0079] As a result of the second update operation described above, in the information processing system 1A, the first user data 511 stored in the first memory system 3-1A is updated to the first updated user data 511-U, and the parity 51P stored in the fourth memory system 3-4A is updated to the updated parity 51P-U.

[0080] In the second update operation, two I / O operations are performed from host 2A to memory system 3A. These two I / O operations are two write I / O operations from host 2A to memory system 3A. No read I / O operations occur in the second update operation. Therefore, the number of read I / O operations is reduced in the second update operation compared to the first update operation described above (see Figure 4). In addition, the update parity 51P-U is generated using the resources of memory system 3A. Therefore, the load on host 2A is reduced in the second update operation. In other words, the update operation from host 2A to memory system 3A is offloaded.

[0081] Figure 6 shows the third update operation in the information processing system 1A of the comparative example. The third update operation is performed to update the first user data 511 stored in the first memory system 3-1A to the first updated user data 511-U, and to update the third user data 513 stored in the third memory system 3-3A to the third updated user data 513-U, while reducing the resources of the host 2A being used. In other words, the third update operation updates the two user data 511 and 513 stored in the two memory systems 3-1A and 3-3A, respectively.

[0082] Host 2A's DRAM 22A stores the first update user data 511-U and the third update user data 513-U.

[0083] The CPU 21A of host 2A sends an XOR / write command (first XOR / write command) to the first memory system 3-1A requesting an XOR operation and the writing of the first update user data 511-U (Figure 6, (1-1)). The CPU 21A also sends an XOR / write command (second XOR / write command) to the third memory system 3-3A requesting an XOR operation and the writing of the third update user data 513-U (Figure 6, (1-2)).

[0084] Upon receiving the first XOR / write command from host 2A, the first memory system 3-1A receives the first update user data 511-U from host 2A. The first memory system 3-1A reads the first user data 511 from the NAND flash memory within the first memory system 3-1A. The first memory system 3-1A generates the first XOR data 521 by performing an XOR operation between the first user data 511 and the first update user data 511-U. The first XOR data 521 is stored in the internal buffer 61-1A of the first memory system 3-1A. Then, the first memory system 3-1A writes the first update user data 511-U to the NAND flash memory within the first memory system 3-1A.

[0085] Furthermore, upon receiving the second XOR / write command from host 2A, the third memory system 3-3A receives the third update user data 513-U from host 2A. The third memory system 3-3A reads the third user data 513 from the NAND flash memory within the third memory system 3-3A. The third memory system 3-3A generates the second XOR data 522 by performing an XOR operation between the third user data 513 and the third update user data 513-U. The second XOR data 522 is stored in the internal buffer 61-3A of the third memory system 3-3A. Then, the third memory system 3-3A writes the third update user data 513-U to the NAND flash memory within the third memory system 3-3A.

[0086] Next, the CPU 21A of host 2A sends an XOR / write command (third XOR / write command) to the fourth memory system 3-4A requesting an XOR operation and the writing of pre-XOR data 51P-P, which will be described later (Figure 6, (2-1)). Furthermore, the CPU 21A of host 2A sends an XOR / write command (fourth XOR / write command) to the fourth memory system 3-4A requesting an XOR operation and the writing of updated parity 51P-U (Figure 6, (2-2)). Host 2A may send the fourth XOR / write command to the fourth memory system 3-4A before receiving a response to the third XOR / write command.

[0087] In response to receiving the third XOR / write command from host 2A, the fourth memory system 3-4A receives the first XOR data 521 from the first memory system 3-1A. The fourth memory system 3-4A reads the parity 51P from the NAND flash memory within the fourth memory system 3-4A. The fourth memory system 3-4A generates pre-XOR data 51P-P by performing an XOR operation between the first XOR data 521 and the parity 51P. Then, the fourth memory system 3-4A writes the pre-XOR data 51P-P to the NAND flash memory within the fourth memory system 3-4A.

[0088] In response to receiving the fourth XOR / write command from host 2A, the fourth memory system 3-4A receives the second XOR data 522 from the third memory system 3-3A. The fourth memory system 3-4A reads the pre-XOR data 51P-P from the NAND flash memory within the fourth memory system 3-4A. The fourth memory system 3-4A generates the update parity 51P-U by performing an XOR operation between the pre-XOR data 51P-P and the second XOR data 522. Then, the fourth memory system 3-4A writes the update parity 51P-U to the NAND flash memory within the fourth memory system 3-4A.

[0089] Furthermore, if the fourth memory system 3-4A receives the fourth XOR / write command before the third XOR / write command, it generates pre-XOR data 51P-P by performing an XOR operation between the second XOR data 522 and the parity 51P. In this case, upon receiving the third XOR / write command, the fourth memory system 3-4A generates updated parity 51P-U by performing an XOR operation between the pre-XOR data 51P-P and the first XOR data 522.

[0090] As a result of the third update operation described above, in the information processing system 1A, the first user data 511 stored in the first memory system 3-1A is updated to the first updated user data 511-U, the third user data 513 stored in the third memory system 3-3A is updated to the third updated user data 513-U, and the parity 51P stored in the fourth memory system 3-4A is updated to the updated parity 51P-U.

[0091] In the third update operation, as described in Figure 5, the update parity 51P-U is generated using the resources of the memory system 3A, similar to the second update operation. Therefore, the third update operation achieves offloading the update operation from the host 2A to the memory system 3A.

[0092] However, in the third update operation, the first XOR data 521 is transmitted from the first memory system 3-1A to the fourth memory system 3-4A, and the second XOR data 522 is transmitted from the third memory system 3-3A to the fourth memory system 3-4A. The requests to transmit the first XOR data 521 and the second XOR data 522 to the fourth memory system 3-4A may occur simultaneously. In this case, one transmission request will be held until the transmission of the other transmission request is completed. That is, a concentration of data transfers to the fourth memory system 3-4A, which stores the parity 51P, may occur. Furthermore, the bus connecting each memory system 3A to the PCIe switch 4A has a smaller bus bandwidth than the bus connecting the host 2 to the PCIe switch 4. Therefore, insufficient bus bandwidth for transferring data to the fourth memory system 3-4A may degrade the overall performance of the information processing system 1A.

[0093] On the other hand, the information processing system 1 according to the first embodiment offloads the update operation from the host 2 to the memory system 3 while also avoiding the concentration of data transfer to the memory system 3 that stores the parity 51P. As a result, the information processing system 1 can improve the overall performance of the information processing system 1 while reducing the load on the host 2.

[0094] Referring to Figures 7 to 11, two examples of update operations in the information processing system 1 will be explained.

[0095] Figure 7 shows an example of a fourth update operation in the information processing system 1. The fourth update operation is an operation to update user data stored in each of two or more memory systems 3 while reducing the resources used by the host 2. Here, we illustrate the case where the fourth update operation updates the first user data 511 stored in the first memory system 3-1 to the first updated user data 511-U, and updates the third user data 513 stored in the third memory system 3-3 to the third updated user data 513-U. It is assumed that the four memory systems 3-1, 3-2, 3-3, and 3-4 each store the first user data 511, the second user data 512, the third user data 513, and parity 51P, respectively, by the sequential write operation described above with reference to Figure 3. The first user data 511, the second user data 512, the third user data 513, and parity 51P constitute one ECC frame 51E.

[0096] Host 2's DRAM 22 stores the first update user data 511-U and the third update user data 513-U.

[0097] The CPU 21 of host 2 sends an XOR / write command (first XOR / write command) to the first memory system 3-1 requesting an XOR operation and the writing of the first updated user data 511-U (Figure 7 (1)). The first XOR / write command may include the logical address of the first user data 511.

[0098] In response to receiving the first XOR / write command from host 2, the first memory system 3-1 receives the first updated user data 511-U from host 2. The first memory system 3-1 reads the first user data 511 from the NAND flash memory 5 within the first memory system 3-1. The first memory system 3-1 generates the first XOR data 521 by performing an XOR operation between the first user data 511 and the first updated user data 511-U. The first XOR data 521 is stored in the internal buffer 61-1 of the first memory system 3-1. For example, a portion of the storage area of ​​DRAM 6 is allocated as the internal buffer 61-1. The internal buffer 61-1 is, for example, a controller memory buffer (CMB) that can be accessed by other memory systems 3 via the PCIe switch 4. Since the internal buffer 61-1 is used to store the first XOR data 521, the Write Amplification Factor (WAF) does not increase. WAF is the value obtained by dividing the amount of data actually written to the NAND flash memory 5 by the amount of data written to the NAND flash memory 5 in response to a request from the host 2. The first memory system 3-1 writes the first updated user data 511-U to the NAND flash memory 5 within the first memory system 3-1.

[0099] Next, the CPU 21 of host 2 sends an XOR / write command (second XOR / write command) to the third memory system 3-3 requesting an XOR operation and the writing of the third updated user data 513-U (Figure 7 (2)). The second XOR / write command may include the logical address of the third user data 513 and the identifier (e.g., address) of the internal buffer 61-1 of the first memory system 3-1 (more specifically, the storage location of the first XOR data 521).

[0100] In response to receiving the second XOR / write command from host 2, the third memory system 3-3 receives the third update user data 513-U from host 2 and the first XOR data 521 from the first memory system 3-1. The third memory system 3-3 also reads the third user data 513 from the NAND flash memory 5 within the third memory system 3-3. The third memory system 3-3A generates the third XOR data 523 by performing an XOR operation on the third user data 513, the third update user data 513-U, and the first XOR data 521. The third XOR data 523 is stored in the internal buffer 61-3 of the third memory system 3-3. Then, the third memory system 3-3 writes the third update user data 513-U to the NAND flash memory 5 within the third memory system 3-3.

[0101] Next, the CPU 21 of host 2 sends an XOR / write command (third XOR / write command) to the fourth memory system 3-4 requesting an XOR operation and the writing of the updated parity 51P-U (Figure 7 (3)). The third XOR / write command may include the logical address of the parity 51P and the identifier (e.g., address) of the internal buffer 61-3 of the third memory system 3-3 (more specifically, the storage location of the third XOR data 523).

[0102] In response to receiving the third XOR / write command from host 2, the fourth memory system 3-4 receives the third XOR data 523 from the third memory system 3-3. The fourth memory system 3-4 reads the parity 51P from the NAND flash memory 5 within the fourth memory system 3-4. The fourth memory system 3-4 generates an updated parity 51P-U by performing an XOR operation between the third XOR data 523 and the parity 51P. Then, the fourth memory system 3-4 writes the updated parity 51P-U to the NAND flash memory 5 within the fourth memory system 3-4.

[0103] As a result of the fourth update operation described above, in the information processing system 1, the first user data 511 stored in the first memory system 3-1 is updated to the first updated user data 511-U, the third user data 513 stored in the third memory system 3-3 is updated to the third updated user data 513-U, and the parity 51P stored in the fourth memory system 3-4 is updated to the updated parity 51P-U.

[0104] In the fourth update operation, the update parity 51P-U is generated using the resources of memory system 3. Therefore, the fourth update operation offloads the update operation from host 2 to memory system 3.

[0105] Furthermore, in the fourth update operation, the first XOR data 521 is transmitted from the first memory system 3-1 to the third memory system 3-3, and the third XOR data 523 is transmitted from the third memory system 3-3 to the fourth memory system 3-4. This avoids a concentration of data transfers to the fourth memory system 3-4, which stores the parity 51P.

[0106] Therefore, the information processing system 1 performing the fourth update operation can improve the overall performance of the information processing system 1 while reducing the load on the host 2.

[0107] Figure 8 is a sequence diagram showing a specific example of the fourth update operation in the information processing system 1.

[0108] First, host 2 sends the first XOR / write command and the first update user data 511-U to the first memory system 3-1 (A1). Host 2 may also send the first update user data 511-U to the first memory system 3-1, which has received the first XOR / write command.

[0109] In response to receiving the first XOR / write command and the first updated user data 511-U, the first memory system 3-1 reads the first user data 511 from the NAND flash memory 5 within the first memory system 3-1 (A2). The first memory system 3-1 performs an XOR operation between the first user data 511 and the first updated user data 511-U to generate the first XOR data 521 (A3). The first memory system 3-1 writes the first updated user data 511-U to the NAND flash memory 5 within the first memory system 3-1, thereby invalidating the first user data 511 (A4). Specifically, the first memory system 3-1 updates the logical-physical address translation table 31 so that the logical address corresponding to the first user data 511 is associated with the physical memory location where the first updated user data 511-U is stored, rather than the physical memory location where the first user data 511 is stored. This invalidates the first user data 511.

[0110] The first memory system 3-1 then sends a response to the first XOR / write command to the host 2 (A5). The first memory system 3-1 may send a response to the first XOR / write command to the host 2 not only when the first updated user data 511-U has been written to the NAND flash memory 5, but also when it is guaranteed that the first updated user data 511-U will be non-volatile. Specifically, if the first memory system 3-1 has a power loss protection (PLP) function, it may generate the first XOR data 521 and send a response to the host 2 in response to storing the first updated user data 511-U in a write buffer (e.g., DRAM 6). This allows the first memory system 3-1 to send a response to the host 2 faster than when it sends a response in response to writing the first updated user data 511-U to the NAND flash memory 5. The PLP function is a function that, when the power supplied to the memory system 3 from an external power source is interrupted, uses the energy of the charge stored in the energy storage device within the memory system 3 to write user data and other information stored in the write buffer that has not yet been written to the NAND flash memory 5 to the NAND flash memory 5.

[0111] Next, in response to receiving the response to the first XOR / write command, host 2 sends the second XOR / write command and the third update user data 513-U to the third memory system 3-3 (A6).

[0112] In response to receiving the second XOR / write command and the third update user data 513-U, the third memory system 3-3 receives the first XOR data 521 from the first memory system 3-1 (A7). Specifically, the third memory system 3-3 receives the first XOR data 521 which has been read from, for example, a specific storage area (e.g., internal buffer 61-1) within the first memory system 3-1 and transmitted. The location within the first memory system 3-1 where the first XOR data 521 is stored is, for example, predetermined. The third memory system 3-3 reads the third user data 513 from the NAND flash memory 5 within the third memory system 3-3 (A8). The third memory system 3-3 performs an XOR operation on the third user data 513, the third update user data 513-U, and the first XOR data 521 to generate the third XOR data 523 (A9). The third memory system 3-3 writes the third update user data 513-U to the NAND flash memory 5 within the third memory system 3-3, thereby invalidating the third user data 513 (A10). Then, the third memory system 3-3 sends a response to the second XOR / write command to the host 2 (A11). The third memory system 3-3 may also send a response to the second XOR / write command to the host 2 if it is guaranteed that the third update user data 513-U will be made non-volatile.

[0113] In response to receiving the response to the second XOR / write command, host 2 sends a third XOR / write command to the fourth memory system 3-4 (A12).

[0114] In response to receiving the third XOR / write command, the fourth memory system 3-4 receives the third XOR data 523 from the third memory system 3-3 (A13). The fourth memory system 3-4 reads the parity 51P from the NAND flash memory 5 within the fourth memory system 3-4 (A14). The fourth memory system 3-4 performs an XOR operation on the parity 51P and the third XOR data 523 to generate the updated parity 51P-U (A15). The fourth memory system 3-4 writes the updated parity 51P-U to the NAND flash memory 5 within the fourth memory system 3-4 (A16). Then, the fourth memory system 3-4 sends a response to the third XOR / write command to the host 2 (A17). The fourth memory system 3-4 may also send a response to the third XOR / write command to the host 2 if it is guaranteed that the updated parity 51P-U will be non-volatile.

[0115] The above fourth update operation enables the information processing system 1 to offload the update operation from the host 2 to the memory system 3, and also avoids concentrated data transfers to the fourth memory system 3-4, which stores the parity 51P.

[0116] The operation of each of the first memory system 3-1, the second memory system 3-2, the third memory system 3-3, and the fourth memory system 3-4 is realized by the CPU 14, which functions as the command receiving unit 141, read processing unit 142, XOR processing unit 143, and write processing unit 144, as described above, with reference to Figure 2.

[0117] As an example, the operation in the first memory system 3-1 when the fourth update operation is performed will be described.

[0118] Figure 9 shows an example of the specific operation in the first memory system 3-1 when the fourth update operation is performed.

[0119] The command receiving unit 141 receives the first XOR / write command from host 2 (Figure 9 (1)). In response to receiving the first XOR / write command, the command receiving unit 141 receives the first updated user data 511-U from host 2 (Figure 9 (2)). Based on the first XOR / write command, the command receiving unit 141 sends a read instruction to the read processing unit 142 instructing it to read the first user data 511 (Figure 9 (3)).

[0120] The read processing unit 142 reads the first user data 511 from the NAND flash memory 5 in response to a read instruction (Figure 9 (4)). Then, the read processing unit 142 sends the read first user data 511 to the XOR processing unit 143 (Figure 9 (5)).

[0121] Next, the command receiving unit 141 sends an XOR instruction to the XOR processing unit 143, which instructs the XOR operation to be performed between the first user data 511 and the first updated user data 511-U (Figure 9 (6)).

[0122] The XOR processing unit 143 performs an XOR operation between the first user data 511 and the first updated user data 511-U in response to the XOR instruction to generate the first XOR data 521. The XOR processing unit 143 stores the generated first XOR data 521 in the internal buffer 61-1 ((7) in Figure 9).

[0123] The command receiving unit 141 then sends a write command instructing the writing of the first updated user data 511-U, along with the first updated user data 511-U itself, to the write processing unit 144 (Figure 9 (8)).

[0124] The write processing unit 144 writes the first updated user data 511-U to the NAND flash memory 5 in response to a write instruction (Figure 9 (9)). The write processing unit 144 then updates the logical-to-physical address translation table 31 so that the logical address associated with the physical memory location where the first user data 511 is stored is associated with the physical memory location where the first updated user data 511-U is stored (Figure 9 (10)). As a result, the first user data 511 is invalidated, and the user data corresponding to that logical address is updated with the first updated user data 511-U.

[0125] Then, the command receiving unit 141 sends a response to the first XOR / write command to the host 2 ((11) in Figure 9).

[0126] Similarly, the operations in the second memory system 3-2, the third memory system 3-3, and the fourth memory system 3-4 can also be realized by the CPU 14, which functions as a command receiving unit 141, a read processing unit 142, an XOR processing unit 143, and a write processing unit 144.

[0127] Figure 10 shows an example of a fifth update operation in the information processing system 1. Similar to the fourth update operation, the fifth update operation updates the first user data 511 stored in the first memory system 3-1 to the first updated user data 511-U, and updates the third user data 513 stored in the third memory system 3-3 to the third updated user data 513-U.

[0128] Host 2's DRAM 22 stores the first update user data 511-U and the third update user data 513-U.

[0129] The CPU 21 of host 2 sends a first XOR / write command to the first memory system 3-1 requesting an XOR operation and the writing of the first update user data 511-U ((1-1) in Figure 10). The CPU 21 of host 2 also sends a second XOR / write command to the third memory system 3-3 requesting an XOR operation and the writing of the third update user data 513-U ((1-2) in Figure 10).

[0130] Upon receiving the first XOR / write command from host 2, the first memory system 3-1 receives the first update user data 511-U from host 2. The first memory system 3-1 reads the first user data 511 from the NAND flash memory 5 within the first memory system 3-1. The first memory system 3-1 generates the first XOR data 521 by performing an XOR operation between the first user data 511 and the first update user data 511-U. The first XOR data 521 is stored in the internal buffer 61-1 of the first memory system 3-1. Then, the first memory system 3-1 writes the first update user data 511-U to the NAND flash memory 5 within the first memory system 3-1.

[0131] In response to receiving the second XOR / write command from host 2, the third memory system 3-3 receives the third update user data 513-U from host 2. The third memory system 3-3 reads the third user data 513 from the NAND flash memory 5 within the third memory system 3-3. The third memory system 3-3 generates pre-XOR data 523-P by performing an XOR operation on the third user data 513 and the third update user data 513-U. The pre-XOR data 523-P is stored in the internal buffer 61-3 of the third memory system 3-3. Then, the third memory system 3-3 writes the third update user data 513-U to the NAND flash memory 5 within the third memory system 3-3. The operation by the third memory system 3-3 in response to the second XOR / write command is performed in parallel with, for example, the operation by the first memory system 3-1 in response to the first XOR / write command.

[0132] Next, the CPU 21 of host 2 sends an XOR command to the third memory system 3-3 requesting an XOR operation between the first XOR data 521 and the prior XOR data 523-P (Figure 10 (2)).

[0133] In response to receiving an XOR command from host 2, the third memory system 3-3 receives the first XOR data 521 from the first memory system 3-1. The third memory system 3-3 generates the third XOR data 523 by performing an XOR operation on the first XOR data 521 and the prior XOR data 523-P. The third XOR data 523 is stored in the internal buffer 61-3 of the third memory system 3-3.

[0134] Next, the CPU 21 of host 2 sends a third XOR / write command to the fourth memory system 3-4 requesting an XOR operation and the writing of the updated parity 51P-U ((3) in Figure 10).

[0135] In response to receiving the third XOR / write command from host 2, the fourth memory system 3-4 receives the third XOR data 523 from the third memory system 3-3. The fourth memory system 3-4 reads the parity 51P from the NAND flash memory 5 within the fourth memory system 3-4. The fourth memory system 3-4 generates an updated parity 51P-U by performing an XOR operation between the third XOR data 523 and the parity 51P. Then, the fourth memory system 3-4 writes the updated parity 51P-U to the NAND flash memory 5 within the fourth memory system 3-4.

[0136] As a result of the fifth update operation described above, in the information processing system 1, the first user data 511 stored in the first memory system 3-1 is updated to the first updated user data 511-U, the third user data 513 stored in the third memory system 3-3 is updated to the third updated user data 513-U, and the parity 51P stored in the fourth memory system 3-4 is updated to the updated parity 51P-U.

[0137] In the fifth update operation, the update parity 51P-U is generated using the resources of memory system 3. Therefore, the fifth update operation offloads the update operation from host 2 to memory system 3.

[0138] Furthermore, in the fifth update operation, the first XOR data 521 is transmitted from the first memory system 3-1 to the third memory system 3-3, and the third XOR data 523 is transmitted from the third memory system 3-3 to the fourth memory system 3-4. This avoids a concentration of data transfers to the fourth memory system 3-4, which stores the parity 51P.

[0139] Furthermore, in the fifth update operation, the operation by the first memory system 3-1 in response to the first XOR / write command and the operation by the third memory system 3-3 in response to the second XOR / write command are performed in parallel. This allows for partial parallelization of the operation by the first memory system 3-1 and the operation by the third memory system 3-3. Therefore, in the information processing system 1, the time required for the fifth update operation can be shortened compared to the time required for the fourth update operation.

[0140] In this way, the information processing system 1 that performs the fifth update operation can improve the overall performance of the information processing system 1 while reducing the load on the host 2.

[0141] Figure 11 is a sequence diagram showing a specific example of the fifth update operation in the information processing system 1.

[0142] First, host 2 sends the first XOR / write command and the first update user data 511-U to the first memory system 3-1 (B1). Host 2 may also send the first update user data 511-U to the first memory system 3-1, which has received the first XOR / write command. Host 2 also sends the second XOR / write command and the third update user data 513-U to the third memory system 3-3 (B2). Host 2 may also send the third update user data 513-U to the third memory system 3-3, which has received the second XOR / write command.

[0143] In response to receiving the first XOR / write command and the first update user data 511-U, the first memory system 3-1 reads the first user data 511 from the NAND flash memory 5 within the first memory system 3-1 (B3). The first memory system 3-1 performs an XOR operation between the first user data 511 and the first update user data 511-U to generate the first XOR data 521 and stores it in the internal buffer 61-1 (B4). The first memory system 3-1 writes the first update user data 511-U to the NAND flash memory 5 within the first memory system 3-1, thereby invalidating the first user data 511 (B5). Then, the first memory system 3-1 sends a response to the first XOR / write command to the host 2 (B6).

[0144] In response to receiving the second XOR / write command, the third memory system 3-3 reads the third user data 513 from the NAND flash memory 5 within the third memory system 3-3 (B7). The third memory system 3-3 performs an XOR operation between the third user data 513 and the third updated user data 513-U to generate pre-XOR data 523-P and stores it in the internal buffer 61-3 (B8). The third memory system 3-3 writes the third updated user data 513-U to the NAND flash memory 5 within the third memory system 3-3, invalidating the third user data 513 (B9). Then, the third memory system 3-3 sends a response to the second XOR / write command to the host 2 (B10).

[0145] Next, in response to receiving the responses to the first XOR / write command and the second XOR / write command, host 2 sends an XOR command to the third memory system 3-3 (B11).

[0146] In response to receiving the XOR command, the third memory system 3-3 receives the first XOR data 521 from the first memory system 3-1 (B12). The third memory system 3-3 performs an XOR operation between the first XOR data 521 and the prior XOR data 523-P to generate the third XOR data 523 and stores it in the internal buffer 61-3 (B13). Then, the third memory system 3-3 sends a response to the XOR command to the host 2 (B14). The subsequent operations from B15 to B20 are the same as the operations from A12 to A17 of the fourth update operation described above, referring to Figure 8.

[0147] The fifth update operation described above enables the information processing system 1 to offload the update operation from the host 2 to the memory system 3, and also avoids concentrated data transfer to the fourth memory system 3-4, which stores the parity 51P. Furthermore, by parallelizing the operations in the first memory system 3-1 and a portion of the operations in the third memory system 3-3, the time required for the fifth update operation can be shortened compared to the time required for the fourth update operation.

[0148] (Second Embodiment) In the information processing system 1 according to the first embodiment, when RAID is configured with multiple memory systems 3, an update operation is performed in which at least a portion of the user data 51D constituting one ECC frame 51E is updated across two or more memory systems 3. In contrast, in the information processing system 1 according to the second embodiment, when RAID is configured with multiple memory systems 3, an operation (rebuild operation) is performed to restore the data stored in the failed memory system 3 and rebuild the RAID.

[0149] The configuration of the information processing system 1 according to the second embodiment is the same as that of the information processing system 1 according to the first embodiment. In the second embodiment, the difference is that a rebuild operation is performed in the host 2 and the memory system 3. The differences from the first embodiment will be mainly described below.

[0150] Figure 12 shows an example of the first rebuild operation in the information processing system 1. The first rebuild operation is an operation to restore the data stored in the failed memory system 3 and rebuild the RAID while reducing the resources used by the host 2. Here, we illustrate the case where the second memory system 3-2 fails. The fifth memory system 3-5 is the memory system 3 that replaces the failed second memory system 3-2. In other words, in the information processing system 1, a rebuild operation is performed so that the RAID is rebuilt in the first memory system 3-1, the third memory system 3-3, the fourth memory system 3-4, and the fifth memory system 3-5 in order to deal with the failure of the second memory system 3-2.

[0151] The four memory systems 3-1, 3-2, 3-3, and 3-4 each store the first user data 511, the second user data 512, the third user data 513, and the parity 51P, respectively, through the sequential write operation described above with reference to Figure 3. The first user data 511, the second user data 512, the third user data 513, and the parity 51P constitute a single ECC frame 51E.

[0152] If the second memory system 3-2 fails, host 2 sends an XOR command (first XOR command) requesting an XOR operation to the first memory system 3-1 (Figure 12 (1)). The first XOR command may include the logical address of the first user data 511.

[0153] The first memory system 3-1 reads the first user data 511 from the NAND flash memory 5 within the first memory system 3-1 in response to the first XOR command from the host 2. The first memory system 3-1 generates the fourth XOR data 524 by performing an XOR operation between the first user data 511 and dummy data 531. The fourth XOR data 524 is stored, for example, in the internal buffer 61-1. The dummy data 531 is a data sequence in which all bits are 0. The dummy data 531 and the first user data 511 have the same data length. Since the data sequence of dummy data 531 has all bits set to 0, the fourth XOR data 524 is identical to the first user data 511. Instead of performing an XOR operation between the first user data 511 and dummy data 531, the first memory system 3-1 may store the first user data 511 directly in the internal buffer 61-1.

[0154] Then, host 2 sends a second XOR command to the third memory system 3-3 ((2) in Figure 12). The second XOR command may include the logical address of the third user data 513 and the identifier (e.g., address) of the internal buffer 61-1 of the first memory system 3-1 (more specifically, the storage location of the fourth XOR data 524).

[0155] The third memory system 3-3 receives the fourth XOR data 524 from the first memory system 3-1 in response to the second XOR command from the host 2. The third memory system 3-3 reads the third user data 513 from the NAND flash memory 5 within the third memory system 3-3. The third memory system 3-3 generates the fifth XOR data 525 by performing an XOR operation between the third user data 513 and the fourth XOR data 524. The fifth XOR data 525 is stored, for example, in the internal buffer 61-3.

[0156] Next, host 2 sends a third XOR command to the fourth memory system 3-4 ((3) in Figure 12). The third XOR command may include the logical address of parity 51P and the identifier (e.g., address) of the internal buffer 61-3 of the third memory system 3-3 (more specifically, the storage location of the fifth XOR data 525).

[0157] The fourth memory system 3-4 receives the fifth XOR data 525 from the third memory system 3-3 in response to the third XOR command from the host 2. The fourth memory system 3-4 reads the parity 51P from the NAND flash memory 5 within the fourth memory system 3-4. The fourth memory system 3-4 generates the second user data 512 by performing an XOR operation between the parity 51P and the fifth XOR data 525. In other words, the second user data 512 that was stored in the NAND flash memory 5 within the failed second memory system 3-2 is restored. The generated second user data 512 is stored, for example, in the internal buffer 61-4.

[0158] Then, host 2 sends a write command to the fifth memory system 3-5 requesting to write the second user data 512 ((4) in Figure 12). The write command may include the logical address of the second user data 512 and an identifier (e.g., address) of the internal buffer 61-4 of the fourth memory system 3-3 (more specifically, the storage location of the second user data 512).

[0159] Upon receiving a write command from host 2, the fifth memory system 3-5 receives the second user data 512 from the fourth memory system 3-4. The fifth memory system 3-5 then writes the second user data 512 to the NAND flash memory 5 within the fifth memory system 3-5.

[0160] Through the first rebuild operation described above, the information processing system 1 can recover the second user data 512 that was stored in the failed second memory system 3-2 and store it in the fifth memory system 3-5 that replaces the second memory system 3-2. Then, by repeating the first rebuild operation in the same manner, all the data (i.e., user data and parity) that was stored in the second memory system 3-2 can be recovered and stored in the fifth memory system 3-5. As a result, the information processing system 1 can rebuild the RAID in the first memory system 3-1, the third memory system 3-3, the fourth memory system 3-4, and the fifth memory system 3-5.

[0161] In the first rebuild operation, the second user data 512 is restored using the resources of memory system 3. Therefore, the first rebuild operation achieves offloading the rebuild operation from host 2 to memory system 3.

[0162] Alternatively, to restore the second user data 512, one could consider an operation in which, for example, one of the first memory system 3-1, the third memory system 3-3, the fourth memory system 3-4, and the fifth memory system 3-5 retrieves the first user data 511, the third user data 513, and parity 51P, and then performs an XOR operation to restore the second user data 512. However, this operation would result in a concentration of data transfers to a single memory system 3 that restores the second user data 512.

[0163] In contrast, in the first rebuild operation, the fourth XOR data 524 is sent from the first memory system 3-1 to the third memory system 3-3, the fifth XOR data 525 is sent from the third memory system 3-3 to the fourth memory system 3-4, and the second user data 512 is sent from the fourth memory system 3-4 to the fifth memory system 3-5. This avoids the concentration of data transfer to a specific one of the first memory system 3-1, the third memory system 3-3, the fourth memory system 3-4, and the fifth memory system 3-5.

[0164] Therefore, the information processing system 1 performing the first rebuild operation can improve the overall performance of the information processing system 1 while reducing the load on the host 2.

[0165] Figure 13 is a sequence diagram showing a specific example of the first rebuild operation in information processing system 1.

[0166] First, host 2 sends the first XOR command to the first memory system 3-1 (C1).

[0167] In response to receiving the first XOR command, the first memory system 3-1 reads the first user data 511 from the NAND flash memory 5 within the first memory system 3-1 (C2). The first memory system 3-1 performs an XOR operation between the first user data 511 and dummy data 531 to generate the fourth XOR data 524 (= first user data 511) and stores it in the internal buffer 61-1 (C3). Then, the first memory system 3-1 sends a response to the first XOR command to the host 2 (C4).

[0168] In response to receiving a response to the first XOR command, host 2 sends a second XOR command to the third memory system 3-3 (C5).

[0169] In response to receiving the second XOR command, the third memory system 3-3 receives the fourth XOR data 524 from the first memory system 3-1 (C6). The third memory system 3-3 reads the third user data 513 from the NAND flash memory 5 within the third memory system 3-3 (C7). The third memory system 3-3 performs an XOR operation between the third user data 513 and the fourth XOR data 524 to generate the fifth XOR data 525 and stores it in the internal buffer 61-3 (C8). Then, the third memory system 3-3 sends a response to the second XOR command to the host 2 (C9).

[0170] In response to receiving the response to the second XOR command, host 2 sends a third XOR command to the fourth memory system 3-4 (C10).

[0171] In response to receiving the third XOR command, the fourth memory system 3-4 receives the fifth XOR data 525 from the third memory system 3-3 (C11). The fourth memory system 3-4 reads the parity 51P from the NAND flash memory 5 within the fourth memory system 3-4 (C12). The fourth memory system 3-4 performs an XOR operation between the parity 51P and the fifth XOR data 525 to generate the second user data 512 and stores it in the internal buffer 61-4 (C13). Then, the fourth memory system 3-4 sends a response to the third XOR command to the host 2 (C14).

[0172] Host 2, having received a response to the third XOR command, sends a write command to the fifth memory system 3-5 (C15).

[0173] In response to receiving a write command, the fifth memory system 3-5 receives the second user data 512 from the fourth memory system 3-4 (C16). The fifth memory system 3-5 writes the second user data 512 to the NAND flash memory 5 within the fifth memory system 3-5 (C17). Then, the fifth memory system 3-5 sends a response to the write command to the host 2 (C18).

[0174] Through the first rebuild operation described above, the information processing system 1 can offload the rebuild operation from the host 2 to the memory system 3, and avoid concentrated data transfers to a specific memory system 3.

[0175] Figure 14 shows an example of a second rebuild operation in information processing system 1. The second rebuild operation, like the first rebuild operation, is an operation to rebuild the RAID in the first memory system 3-1, the third memory system 3-3, the fourth memory system 3-4, and the fifth memory system 3-5 in order to address a failure in the second memory system 3-2.

[0176] If the second memory system 3-2 fails, host 2 sends a first XOR command to the first memory system 3-1 ((1) in Figure 14). The first XOR command may further include an identifier for the third memory system 3-3.

[0177] The first memory system 3-1 reads first user data 511 from the NAND flash memory 5 within the first memory system 3-1 in response to a first XOR command from the host 2. The first memory system 3-1 generates fourth XOR data 524 by performing an XOR operation between the first user data 511 and dummy data 531. The fourth XOR data 524 is stored, for example, in an internal buffer 61-1. The first memory system 3-1 then sends a second XOR command to the third memory system 3-3 ((2) in Figure 14). The second XOR command may further include an identifier for the fourth memory system 3-4.

[0178] The third memory system 3-3 receives the fourth XOR data 524 from the first memory system 3-1 in response to the second XOR command from the first memory system 3-1. The third memory system 3-3 reads the third user data 513 from the NAND flash memory 5 within the third memory system 3-3. The third memory system 3-3 generates the fifth XOR data 525 by performing an XOR operation between the third user data 513 and the fourth XOR data 524. The fifth XOR data 525 is stored, for example, in the internal buffer 61-3. The third memory system 3-3 then sends the third XOR command to the fourth memory system 3-4 ((3) in Figure 14). The third XOR command may further include an identifier for the fifth memory system 3-5.

[0179] The fourth memory system 3-4 receives the fifth XOR data 525 from the third memory system 3-3 in response to the third XOR command from the third memory system 3-3. The fourth memory system 3-4 reads the parity 51P from the NAND flash memory 5 within the fourth memory system 3-4. The fourth memory system 3-4 generates the second user data 512 by performing an XOR operation between the parity 51P and the fifth XOR data 525. In other words, the second user data 512 that was stored in the NAND flash memory 5 within the failed second memory system 3-2 is restored. The generated second user data 512 is stored, for example, in the internal buffer 61-4. The fourth memory system 3-4 then sends a write command to the fifth memory system 3-5 requesting that the second user data 512 be written ((4) in Figure 14).

[0180] The fifth memory system 3-5 receives the second user data 512 from the fourth memory system 3-4 in response to a write command from the fourth memory system 3-4. The fifth memory system 3-5 then writes the second user data 512 to the NAND flash memory 5 within the fifth memory system 3-5.

[0181] Through the second rebuild operation described above, the information processing system 1 can recover the second user data 512 that was stored in the failed second memory system 3-2 and store it in the fifth memory system 3-5 that replaces the second memory system 3-2. By repeating this second rebuild operation in the same manner, all the data that was stored in the second memory system 3-2 can be recovered and stored in the fifth memory system 3-5. As a result, the information processing system 1 can rebuild the RAID in the first memory system 3-1, the third memory system 3-3, the fourth memory system 3-4, and the fifth memory system 3-5.

[0182] Furthermore, in the second rebuild operation, the second user data 512 is restored using the resources of memory system 3. In addition, not only data (i.e., the fourth XOR data 524, the fifth XOR data 525, and the second user data 512) but also commands are transmitted between memory systems 3. Therefore, in the second rebuild operation, host 2 only needs to send the first XOR command to the first memory system 3-1. Thus, in the second rebuild operation, the rebuild operation offloading from host 2 to memory system 3 is achieved.

[0183] Furthermore, in the second rebuild operation, the fourth XOR data 524 is sent from the first memory system 3-1 to the third memory system 3-3, the fifth XOR data 525 is sent from the third memory system 3-3 to the fourth memory system 3-4, and the second user data 512 is sent from the fourth memory system 3-4 to the fifth memory system 3-5. This avoids the concentration of data transfers on any one of the first memory system 3-1, the third memory system 3-3, the fourth memory system 3-4, and the fifth memory system 3-5.

[0184] Therefore, the information processing system 1 performing the second rebuild operation can improve the overall performance of the information processing system 1 while reducing the load on the host 2.

[0185] Figure 15 is a sequence diagram showing a specific example of the second rebuild operation in information processing system 1.

[0186] First, host 2 sends the first XOR command to the first memory system 3-1 (D1).

[0187] In response to receiving the first XOR command, the first memory system 3-1 reads the first user data 511 from the NAND flash memory 5 within the first memory system 3-1 (D2). The first memory system 3-1 performs an XOR operation between the first user data 511 and dummy data 531 to generate the fourth XOR data 524 and stores it in the internal buffer 61-1 (D3). Then, the first memory system 3-1 sends the second XOR command and the fourth XOR data 524 to the third memory system 3-3 (D4).

[0188] In response to receiving the second XOR command and the fourth XOR data 524, the third memory system 3-3 reads the third user data 513 from the NAND flash memory 5 within the third memory system 3-3 (D5). The third memory system 3-3 performs an XOR operation on the third user data 513 and the fourth XOR data 524 to generate the fifth XOR data 525 and stores it in the internal buffer 61-3 (D6). Then, the third memory system 3-3 transmits the third XOR command and the fifth XOR data 525 to the fourth memory system 3-4 (D7).

[0189] In response to receiving the third XOR command and the fifth XOR data 525, the fourth memory system 3-4 reads the parity 51P from the NAND flash memory 5 within the fourth memory system 3-4 (D8). The fourth memory system 3-4 performs an XOR operation between the parity 51P and the fifth XOR data 525 to generate the second user data 512 and stores it in the internal buffer 61-4 (D9). Then, the fourth memory system 3-4 sends the write command and the second user data 512 to the fifth memory system 3-5 (D10).

[0190] Upon receiving the write command and the second user data 512, the fifth memory system 3-5 writes the second user data 512 to the NAND flash memory 5 within the fifth memory system 3-5 (D11). Then, the fifth memory system 3-5 sends a response to the write command to the fourth memory system 3-4 (D12).

[0191] Upon receiving a response to the write command, the fourth memory system 3-4 sends a response to the third XOR command to the third memory system 3-3 (D13). Upon receiving a response to the third XOR command, the third memory system 3-3 sends a response to the second XOR command to the first memory system 3-1 (D14). Upon receiving a response to the second XOR command, the first memory system 3-1 sends a response to the first XOR command to host 2 (D15).

[0192] Through the second rebuild operation described above, the information processing system 1 can offload the rebuild operation from the host 2 to the memory system 3, and avoid concentrated data transfers to a specific memory system 3.

[0193] The operation of each of the first memory system 3-1, third memory system 3-3, fourth memory system 3-4, and fifth memory system 3-5 is realized by the CPU 14, which functions as the command receiving unit 141, read processing unit 142, XOR processing unit 143, and write processing unit 144, as described above, for example, with reference to Figure 2.

[0194] As an example, the operation of the first memory system 3-1 when a second rebuild operation is performed will be described.

[0195] Figure 16 shows a specific example of the operation in the first memory system 3-1 when the second rebuild operation is performed.

[0196] The command receiving unit 141 receives the first XOR command from the host 2 ((1) in Figure 16). Based on the first XOR command, the command receiving unit 141 sends a read instruction to the read processing unit 142 instructing it to read the first user data 511 ((2) in Figure 16).

[0197] The read processing unit 142 reads the first user data 511 from the NAND flash memory 5 in response to a read instruction (Figure 16 (3)). Then, the read processing unit 142 sends the read first user data 511 to the XOR processing unit 143 (Figure 16 (4)).

[0198] Next, the command receiving unit 141 sends an XOR instruction to the XOR processing unit 143, which instructs the XOR operation to be performed between the first user data 511 and the dummy data 531, along with the dummy data 531 (5 in Figure 16).

[0199] The XOR processing unit 143 performs an XOR operation between the first user data 511 and the dummy data 531 in response to the XOR instruction to generate the fourth XOR data 524. The XOR processing unit 143 stores the generated fourth XOR data 524 in the internal buffer 61-1 ((6) in Figure 16).

[0200] Next, the command receiving unit 141 sends the second XOR command to the third memory system 3-3 (7 in Figure 16). Subsequently, the command receiving unit 141 receives a response to the second XOR command from the third memory system 3-3 (8 in Figure 16). In response to receiving the response to the second XOR command, the command receiving unit 141 sends a response to the first XOR command to the host 2 (9 in Figure 16).

[0201] Similarly, the operations in the third memory system 3-3, the fourth memory system 3-4, and the fifth memory system 3-5 can also be realized by the CPU 14, which functions as a command receiving unit 141, a read processing unit 142, an XOR processing unit 143, and a write processing unit 144.

[0202] As described above, according to the first and second embodiments, the overall performance can be improved while reducing the load on the host 2.

[0203] In the information processing system 1 according to the first embodiment, the controller 7 of the first memory system 3-1 stores the first user data 511 in the NAND flash memory 5 within the first memory system 3-1. The controller 7 of the third memory system 3-3 stores the third user data 513 in the NAND flash memory 5 within the third memory system 3-3. The first user data 511 and the third user data 513 constitute a part of an error correction code frame 51E. When the first user data 511 and the third user data 513 are updated, the host 2 transmits the first updated user data 511-U, which has been updated from the first user data 511, to the first memory system 3-1, and transmits the third updated user data 513-U, which has been updated from the third user data 513, to the third memory system 3-3. The controller 7 of the first memory system 3-1 generates first XOR data 521 by performing an XOR operation on at least first user data 511 and first updated user data 511-U, and transmits the first XOR data 521 to the third memory system 3-3. The controller 7 of the third memory system 3-3 generates third XOR data 523 by performing an XOR operation on third user data 513, third updated user data 513-U, and first XOR data 521, and transmits the third XOR data 523 to the fourth memory system 3-4.

[0204] This enables the offloading of update operations from host 2 to memory system 3, and also avoids concentrated data transfers to, for example, the fourth memory system 3-4 which stores parity 51P.

[0205] Furthermore, in the information processing system 1 according to the second embodiment, the controller 7 of the second memory system 3-2 stores the second user data 512 in the NAND flash memory 5 within the second memory system 3-2. The controller 7 of the third memory system 3-3 stores the third user data 513 in the NAND flash memory 5 within the third memory system 3-3. The controller 7 of the fourth memory system 3-4 stores the parity 51P in the NAND flash memory 5 within the fourth memory system 3-4. The second user data 512, the third user data 513, and the parity 51P constitute at least a part of one error correction code frame 51E. If the second memory system 3-2 fails, the controller 7 of the third memory system 3-3 generates the fifth XOR data 525 by performing an XOR operation between the fourth XOR data 524 and the third user data 513, and transmits the fifth XOR data 525 to the fourth memory system 3-4. The controller 7 of the fourth memory system 3-4 generates second user data 512 by performing an XOR operation between the fifth XOR data 525 and the parity 51P, and transmits the generated second user data 512 to the fifth memory system 3-5, which is replacing the failed second memory system 3-2.

[0206] This allows the information processing system 1 to offload the rebuild operation from the host 2 to the memory system 3, and also avoid concentrated data transfers to a specific memory system 3.

[0207] Each of the various functions described in the first and second embodiments may be implemented by a circuit (processing circuit). Examples of processing circuits include a programmed processor, such as a central processing unit (CPU). This processor performs each of the described functions by executing computer programs (sets of instructions) stored in memory. This processor may be a microprocessor including electrical circuits. Examples of processing circuits also include digital signal processors (DSPs), application-specific integrated circuits (ASICs), microcontrollers, controllers, and other electrical circuit components. Each of the components other than the CPU described in these embodiments may also be implemented by a processing circuit.

[0208] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0209] 1…Information processing system, 2…Host, 3, 3-1, 3-2, 3-3, 3-4, 3-5…Memory system, 4…Switch, 5…Non-volatile memory, 6…DRAM, 7…Controller, 11…Host I / F, 12…NAND I / F, 13…DRAM I / F, 14, 21...CPU, 22...RAM, 31...Logical-Physical Address Translation Table, 51D...User Data, 511...First User Data, 512...Second User Data, 513...Third User Data, 51P...Parity, 51E...ECC Frame, 511-U...First Update User Data, 513-U...Third Update User Data, 51P-U...Update Parity, 521...First XOR Data, 522...Second XOR Data, 523...Third XOR Data, 524...Fourth XOR Data, 525...Fifth XOR Data, 531...Dummy Data, 523-P...Pre-XOR Data.

Claims

1. An information processing system comprising a host and a plurality of memory systems, each including a controller and non-volatile memory, The controller of the first memory system among the plurality of memory systems stores the first data in the first non-volatile memory. The controller of the second memory system among the plurality of memory systems stores the second data in the second non-volatile memory. The first data and the second data constitute a part of a single error correction code frame. When the first data and the second data are updated, the host The first updated data, which has been updated from the first data, is transmitted to the first memory system. The second updated data, which has been updated from the second data, is transmitted to the second memory system. The controller of the first memory system is By performing an exclusive OR operation on at least the first data and the first update data, the first exclusive OR data is generated. The first exclusive OR data is transmitted to the second memory system. The controller of the second memory system is By performing an exclusive OR operation between the second data, the second updated data, and the first exclusive OR data, the second exclusive OR data is generated. The second exclusive OR data is transmitted to the third memory system among the plurality of memory systems. Information processing system.

2. The controller of the third memory system stores the parity in the third non-volatile memory. The first data, the second data, and the parity constitute at least a part of the error correction code frame. The information processing system according to claim 1.

3. The aforementioned host, When the first data and the second data are updated, the first request and the first updated data are sent to the first memory system. Upon receiving a first response to the first request from the first memory system, the second request and the second update data are transmitted to the second memory system. The controller of the first memory system, upon receiving the first request, The first exclusive OR data is generated, The first response is sent to the host, The first exclusive OR data is transmitted to the second memory system. The controller of the second memory system, upon receiving the second request, The second exclusive OR data is generated, The second response to the second request is sent to the host. The second exclusive OR data is transmitted to the third memory system. The information processing system according to claim 1.

4. The controller of the third memory system stores the parity in the third non-volatile memory. The first data, the second data, and the parity constitute at least a part of the error correction code frame. Upon receiving the second response, the host sends a third request to the third memory system. The controller of the third memory system, upon receiving the third request, generates an updated parity by performing an exclusive OR operation between the parity and the second exclusive OR data. The first update data, the second update data, and the update parity constitute at least a portion of the updated error correction code frame. The information processing system according to claim 3.

5. The aforementioned host, When the first data and the second data are updated, the first request and the first updated data are sent to the first memory system, and the second request and the second updated data are sent to the second memory system. Upon receiving a first response to the first request from the first memory system and a second response to the second request from the second memory system, a third request is transmitted to the second memory system. The controller of the first memory system, upon receiving the first request, The first exclusive OR data is generated, The first response is sent to the host, The controller of the second memory system, upon receiving the second request, By performing an exclusive OR operation between the second data and the second updated data, a third exclusive OR data is generated. The second response is sent to the host, The controller of the second memory system, upon receiving the third request, The first exclusive OR data is received from the first memory system, By performing an exclusive OR operation on the first exclusive OR data and the third exclusive OR data, the second exclusive OR data is generated. The third response to the third request is sent to the host. The second exclusive OR data is transmitted to the third memory system. The information processing system according to claim 1.

6. The controller of the third memory system stores the parity in the third non-volatile memory. The first data, the second data, and the parity constitute at least a part of the error correction code frame. Upon receiving the third response, the host sends a fourth request to the third memory system. Upon receiving the fourth request, the controller of the third memory system generates an updated parity by performing an exclusive OR operation between the parity and the second exclusive OR data. The first update data, the second update data, and the update parity constitute at least a portion of the updated error correction code frame. The information processing system according to claim 5.

7. An information processing system comprising a host and a plurality of memory systems, each including a controller and non-volatile memory, The controller of the first memory system among the plurality of memory systems stores the first data in the first non-volatile memory. The controller of the second memory system among the plurality of memory systems stores the second data in the second non-volatile memory. The controller of the third memory system among the plurality of memory systems stores the parity in the third non-volatile memory. The first data, the second data, and the parity constitute at least a part of one error correction code frame. If the second memory system fails, The controller of the first memory system is By performing an exclusive OR operation between the third data and the first data, the first exclusive OR data is generated. The first exclusive OR data is transmitted to the third memory system. The controller of the third memory system is The second data is generated by performing an exclusive OR operation between the first exclusive OR data and the parity. The generated second data is transmitted from the faulty second memory system to the replacement memory system. Information processing system.

8. The aforementioned host, If the second memory system fails, the first request is sent to the first memory system. Upon receiving a first response to the first request from the first memory system, a second request is transmitted to the third memory system. The controller of the first memory system, upon receiving the first request, By performing an exclusive OR operation between the third data and the first data, the first exclusive OR data is generated. The first response is sent to the host, The first exclusive OR data is transmitted to the third memory system. The controller of the third memory system, upon receiving the second request, The second data is generated by performing an exclusive OR operation between the first exclusive OR data and the parity. The generated second data is transmitted to the memory system that is being replaced from the faulty second memory system. The information processing system according to claim 7.

9. If the second memory system fails, the host sends a first request to the first memory system. The controller of the first memory system, upon receiving the first request, By performing an exclusive OR operation between the third data and the first data, the first exclusive OR data is generated. The second request and the first exclusive OR data are transmitted to the third memory system. The controller of the third memory system, upon receiving the second request, The second data is generated by performing an exclusive OR operation between the first exclusive OR data and the parity. The generated second data is transmitted to the memory system that is being replaced from the faulty second memory system. The information processing system according to claim 7.

10. The controller of the fourth memory system among the plurality of memory systems is: The aforementioned third data is stored in the fourth non-volatile memory, If the second memory system fails, the third data is transmitted to the first memory system. The controller of the first memory system generates the first exclusive OR data by performing an exclusive OR operation between the third data and the first data received from the fourth memory system. The first data, the second data, the third data, and the parity constitute the error correction code frame. The information processing system according to any one of claims 7 to 9.

11. The controller of the fourth memory system among the plurality of memory systems is: The fourth data is stored in the fourth non-volatile memory, If the second memory system fails, The fifth data is received from the fifth memory system among the plurality of memory systems. The third data is generated by performing an exclusive OR operation between the fifth data and the fourth data. The third data is transmitted to the first memory system. The controller of the first memory system generates the first exclusive OR data by performing an exclusive OR operation between the third data and the first data received from the fourth memory system. The first data, the second data, the fourth data, and the parity constitute a part of the error correction code frame. The information processing system according to any one of claims 7 to 9.

12. The third data mentioned above is data in which all bits are 0. The first data, the second data, and the parity constitute the error correction code frame. The information processing system according to any one of claims 7 to 9.

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