Memory system and power control circuit
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- KIOXIA CORP
- Filing Date
- 2023-02-16
- Publication Date
- 2026-08-03
Smart Images
Figure 0007899110000001 
Figure 0007899110000002 
Figure 0007899110000003
Abstract
Description
Technical Field
[0001] Embodiments relate to a memory system and a power control circuit.
Background Art
[0002] A memory system including a non-volatile memory, a memory controller, and a power control circuit is known. The non-volatile memory stores data non-volatily. The memory controller controls the non-volatile memory. The power control circuit supplies power to the non-volatile memory and the memory controller.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Patent Document 2
Patent Document 3
Summary of the Invention
Problems to be Solved by the Invention
[0004] Provide a memory system and a power control circuit that can timely turn off the power while suppressing power consumption.
Means for Solving the Problems
[0005] The memory system of the embodiment comprises a memory controller, a non-volatile memory, and a power control circuit configured to be powered by a main power supply. The power control circuit includes a backup power supply, a first converter configured to supply power to the memory controller based on power supplied from the main power supply or the backup power supply, a second converter configured to supply power to the non-volatile memory based on power supplied from the main power supply or the backup power supply, and a discharge circuit configured to discharge the power remaining in the second converter based on the power remaining in the backup power supply after the power supply from the main power supply and the backup power supply has been stopped. The discharge circuit includes a first resistor having a first terminal connected to the backup power supply, a first transistor connected in series with the first resistor, a second resistor having a first terminal connected between the second converter and the non-volatile memory, and a second transistor connected in series with the second resistor and having a control terminal connected between the first resistor and the first transistor. [Brief explanation of the drawing]
[0006] [Figure 1] A block diagram showing an example of the configuration of an information processing system according to the first embodiment. [Figure 2] A circuit diagram showing an example of the configuration of a discharge circuit according to the first embodiment. [Figure 3] A diagram showing an example of the state before the discharge operation is performed in the discharge circuit according to the first embodiment. [Figure 4] A diagram showing an example of the state in which the discharge operation is performed in the discharge circuit according to the first embodiment. [Figure 5] A waveform diagram showing an example of the power-off operation in the power control circuit according to the first embodiment. [Figure 6] A block diagram showing an example of the configuration of an information processing system according to the second embodiment. [Figure 7] A circuit diagram showing an example of the configuration of a discharge circuit according to the second embodiment. [Figure 8] This figure shows an example of the state before the discharge operation is performed in the discharge circuit according to the second embodiment. [Figure 9] A diagram showing an example of the state in which the discharge operation is performed in the discharge circuit according to the second embodiment. [Figure 10] A waveform diagram showing an example of the power-off operation in the power control circuit according to the second embodiment. [Figure 11] A block diagram showing an example of the configuration of an information processing system according to the third embodiment. [Figure 12] A circuit diagram showing an example of the configuration of a discharge circuit according to the third embodiment. [Figure 13] A diagram showing an example of the state before the discharge operation is performed in the discharge circuit according to the third embodiment. [Figure 14] A diagram showing an example of the state in which the discharge operation is performed in the discharge circuit according to the third embodiment. [Figure 15] A waveform diagram showing an example of the power-off operation in the power control circuit according to the third embodiment. [Modes for carrying out the invention]
[0007] The embodiments will be described below with reference to the drawings. In the description, components having substantially the same function and configuration will be denoted by the same reference numerals. Furthermore, the embodiments shown below are illustrative of the technical concept. The embodiments do not specify the material, shape, structure, arrangement, etc., of the components. Various modifications can be made to the embodiments.
[0008] 1. First Embodiment 1.1 Configuration 1.1.1 Information Processing Systems Figure 1 is a block diagram showing an example of the configuration of an information processing system according to the first embodiment. The information processing system 1 includes a host 2 and a memory system 3. The host 2 and the memory system 3 are connected via a host bus HB. The host bus HB is, for example, SATA (Serial Advanced Technology Attachment) or PCIe TM It is a bus compliant with standards such as PCI Express.
[0009] Host 2 is an electronic device such as a personal computer, a portable information terminal, or a server. Host 2 includes a main power supply 4. The main power supply 4 has power lines L IN Power is supplied to the memory system 3 via this.
[0010] The memory system 3 is a storage medium such as a memory card or an SSD (Solid State Drive). The memory system 3 includes a memory controller 10, a non-volatile memory 20, and a power control circuit 30. The memory controller 10, the non-volatile memory 20, and the power control circuit 30 are mounted on the same circuit board. The memory controller 10 and the non-volatile memory 20 are connected via a memory bus MB. The memory bus MB is a bus compliant with, for example, an SDR (Single data rate) interface, a toggle DDR (Double data rate) interface, or an ONFI (Open NAND flash interface).
[0011] The memory controller 10 is an integrated circuit (IC) chip, such as a system-on-a-chip (SoC). The memory controller 10 controls the non-volatile memory 20 based on the received requests.
[0012] The non-volatile memory 20 is, for example, a NAND flash memory. The non-volatile memory 20 stores data in a non-volatile manner.
[0013] The power control circuit 30 is an IC chip configured to supply power to the memory controller 10 and the non-volatile memory 20.
[0014] 1.1.2 Power Control Circuit Next, the internal configuration of the power control circuit 30 will be explained using Figure 1. The power control circuit 30 comprises a backup power supply 31, a control circuit 32, a converter 33, a converter 34, and a discharge circuit 35.
[0015] The backup power supply 31 is, for example, a battery and / or a capacitor. The backup power supply 31 is connected to the power line L PLP Power is supplied to the control circuit 32 via this.
[0016] The control circuit 32 is a circuit that controls the power supply control circuit 30. When power is supplied from the main power supply 4, the control circuit 32 uses the power supplied from the main power supply 4 to charge the backup power supply 31 and supplies power to the converters 33 and 34 via the power line L B . When power is not supplied from the main power supply 4, the control circuit 32 uses the power charged in the backup power supply 31 to supply power to the converters 33 and 34 via the power line L B .
[0017] The converter 33 is a DC / DC converter. The converter 33 uses the power supplied from the control circuit 32 to supply power to the memory controller 10 via the power line L OUT1 .
[0018] The converter 34 is a DC / DC converter. The converter 34 uses the power supplied from the control circuit 32 to supply power to the non-volatile memory 20 via the power line L OUT2 .
[0019] The discharge circuit 35 is a circuit configured to perform a discharge operation. The discharge operation in the first embodiment is an operation of discharging the remaining power in the converter 34 via the power line L OUT2 . The discharge circuit 35 is driven using the power supplied from the backup power supply 31.
[0020] 1.1.3 Discharge Circuit FIG. 2 is a circuit diagram showing an example of the configuration of the discharge circuit according to the first embodiment. The discharge circuit 35 includes a resistor R1, a resistor R2, a transistor TR1, and a transistor TR2.
[0021] The resistor R1 is, for example, a resistor having a value of 10 kΩ or more and 100 kΩ or less. The resistor R1 has a first end connected to the power line L PLP and a second end connected to the node N1.
[0022] Transistor TR1 is, for example, an N-type field-effect transistor. Transistor TR1 has a first terminal connected to node N1, a second terminal grounded to voltage VSS, and a control terminal to which the signal PG is applied. Voltage VSS is, for example, 0V. Signal PG is generated by the control circuit 32.
[0023] Resistor R2 is a resistor with a value of approximately 100Ω (100Ω to 1kΩ). Resistor R2 is connected to the power line L OUT2 It has a first end connected to the first end of transistor TR2 and a second end connected to the first end of transistor TR2.
[0024] Transistor TR2 is, for example, an N-type field-effect transistor. Transistor TR2 has a first terminal, a second terminal grounded to voltage VSS, and a control terminal connected to node N1.
[0025] 1.2 Operation 1.2.1 Discharge Operation Figure 3 shows an example of the state of the discharge circuit according to the first embodiment before the discharge operation is performed.
[0026] During the period before the discharge operation is performed, the control circuit 32 generates a signal PG at the "H" level. The "H" level signal PG turns on transistor TR1. Consequently, current I1 flows through resistor R1 and transistor TR1. When current I1 flows, the voltage at node N1 is the voltage across the power line L PLP The voltage drops to a level that turns off transistor TR2. Therefore, since transistor TR2 is in the off state, no current flows through resistor R2 and transistor TR2. The power consumed by resistor R1 and transistor TR1 by current I1 is negligibly small.
[0027] Next, the discharge operation in the discharge circuit 35 will be explained using Figure 4. Figure 4 is a diagram showing an example of the state in which the discharge operation in the discharge circuit according to the first embodiment is performed.
[0028] During the discharge operation, the control circuit 32 generates an "L" level signal PG. The "L" level signal PG turns off transistor TR1. As a result, no current I1 flows through resistor R1 and transistor TR1. When no current I1 flows, the voltage at node N1 is the same as the power line L. PLP The voltage will be approximately the same as that of the power line L. PLP The voltage turns on transistor TR2. Consequently, current I2 flows through resistor R2 and transistor TR2. Therefore, the power remaining in converter 34 is supplied to the power line L OUT2 The energy is consumed through resistor R2 and transistor TR2.
[0029] 1.2.2 Power Off Operation Figure 5 is a waveform diagram showing an example of the power-off operation in the power control circuit according to the first embodiment. The power-off operation is the operation that transitions the memory system 3 from the power-on state to the power-off state. In Figure 5, the power line L during the period when the memory system 3 transitions from the power-on state to the power-off state IN , L PLP , L B , L OUT1 , and L OUT2 An example of the voltage and signal PG level waveforms is shown. In the waveform diagram shown in Figure 5, the vertical axis represents voltage. In the waveform diagram shown in Figure 5, the horizontal axis represents time.
[0030] The period during which the memory system 3 transitions from the power-on state to the power-off state includes times T1, T2, and T3. Time T1 is the time when the power supply source to the control circuit 32 switches from the main power supply 4 to the backup power supply 31. Time T2 is the time when the power supply from the backup power supply 31 to the control circuit 32 is stopped. Time T3 is the time when the discharge operation begins.
[0031] Until time T1, the main power supply 4 supplies power to the control circuit 32. Based on the power supplied from the main power supply 4, the control circuit 32 supplies power to converters 33 and 34 while charging the backup power supply 31. Accordingly, the power line L IN The voltage V IN A voltage is applied to the power line L. PLP The voltage V PLP_ON A voltage is applied to the power line L. B The voltage V B_ON A voltage V is applied. IN For example, it is 12V. PLP_ON For example, it is 28V. B_ON For example, the voltage is 12V. The control circuit 32 also turns on converters 33 and 34 with a "H" level signal PG. Converter 33 uses the power supplied from the control circuit 32 to power the memory controller 10. Converter 34 uses the power supplied from the control circuit 32 to power the non-volatile memory 20. Accordingly, the power line L OUT1 The voltage V OUT1_ON A voltage is applied to the power line L. OUT2 The voltage V OUT2_ON A voltage V is applied. OUT1_ON For example, it is 0.8V. OUT2_ON For example, it is 2.6V.
[0032] At time T1, the main power supply 4 stops supplying power to the control circuit 32. Consequently, power line L IN A voltage VSS is applied to it.
[0033] Between time T1 and time T2, the backup power supply 31 supplies power to the control circuit 32. The control circuit 32 uses the power supplied from the backup power supply 31 to supply power to converters 33 and 34. Accordingly, the power line L PLP The voltage V depends on the power consumed by the backup power supply 31. PLP_ON From voltage V PLP_OFF It decreases to L. B The voltage is, B_ONMaintain the voltage V PLP_OFF For example, it is 6V.
[0034] At time T2, power line L PLP The voltage is voltage V PLP_OFF In response to reaching this point, the control circuit 32 stops supplying power to converters 33 and 34. Consequently, the power line L B The voltage is, B_OFF It drops rapidly. Voltage V B_OFF For example, it is 3V. From time T2 onwards, power line L B The voltage is, B_OFF It is maintained between the voltage VSS.
[0035] At time T3, the control circuit 32 turns off converters 33 and 34 with an "L" level signal PG. The discharge circuit 35 is powered by the power line L OUT2 A discharge path is formed in this way. Consequently, the power line L OUT2 The voltage drops rapidly to voltage VSS. Power line L OUT1 The voltage is, OUT1_OFF It drops rapidly. Voltage V OUT1_OFF For example, it is 0.5V. From time T3 onwards, power line L OUT1 The voltage is, OUT1_OFF It is maintained between the voltage VSS.
[0036] 1.3 Effects of the First Embodiment According to the first embodiment, the discharge circuit 35 is configured to discharge the power remaining in the converter 34 using the power remaining in the backup power supply 31 after the power supply from the main power supply 4 has been stopped. This prevents the non-volatile memory 20 from remaining powered on due to the power remaining in the converter 34 after the power-off operation. Therefore, it is possible to suppress the occurrence of errors in communication between the non-volatile memory 20, which remains powered on, and the memory controller 10, which is powered off, during the power-on operation.
[0037] Furthermore, according to the first embodiment, the discharge circuit 35 is composed of two resistors and two transistors. As a result, the manufacturing cost of the discharge circuit 35 can be reduced compared to a discharge circuit having a complex circuit configuration using relays, etc.
[0038] Furthermore, according to the first embodiment, resistor R1 is designed to have high resistance. This makes the power consumed by resistor R1 negligibly small. As a result, the power consumed by the power control circuit 30 can be suppressed.
[0039] Furthermore, according to the first embodiment, resistor R2 is designed to have low resistance. This allows the power remaining in the converter 34 to be discharged quickly.
[0040] 2. Second Embodiment Next, a memory system according to the second embodiment will be described. In the second embodiment, the power line L OUT2 In addition, power line L OUT1 This differs from the first embodiment in that a discharge path is also formed. The following will mainly describe the configuration and operation that differ from the first embodiment. The configuration and operation equivalent to that of the first embodiment will be omitted from the description as appropriate.
[0041] 2.1 Power Control Circuit Figure 6 is a block diagram showing an example of the configuration of an information system according to the second embodiment. Figure 6 corresponds to Figure 1 in the first embodiment.
[0042] The information processing system 1 according to the second embodiment includes a host 2 and a memory system 3. The memory system 3 according to the second embodiment includes a memory controller 10, a non-volatile memory 20, and a power control circuit 30. The power control circuit 30 according to the second embodiment includes a backup power supply 31, a control circuit 32, a converter 33, a converter 34, and a discharge circuit 35A. The configuration of the host 2, memory controller 10, non-volatile memory 20, backup power supply 31, control circuit 32, converter 33, and converter 34 is the same as in the first embodiment.
[0043] The discharge circuit 35A is a circuit configured to perform a discharge operation. In the second embodiment, the discharge operation is performed on the power line L OUT1 The power remaining in the converter 33 is discharged via the power line L OUT2 This operation discharges the power remaining in the converter 34 via the discharge circuit 35A. The discharge circuit 35A is driven based on the power supplied from the backup power supply 31.
[0044] 2.2 Discharge circuit Figure 7 is a circuit diagram showing an example of the configuration of a discharge circuit according to the second embodiment. Figure 7 corresponds to Figure 2 in the first embodiment. The discharge circuit 35A includes resistors R1, R2, R3, transistors TR1, TR2, and TR3. The configuration of resistors R1, R2, transistors TR1, and TR2 is the same as in the first embodiment.
[0045] Resistor R3 is a low resistance resistor, for example, having a value similar to that of resistor R2. Resistor R3 is connected to the power line L OUT1 It has a first end connected to the first end of transistor TR3 and a second end connected to the first end of transistor TR3.
[0046] Transistor TR3 is, for example, an N-type field-effect transistor. Transistor TR3 has a first terminal, a second terminal grounded to the voltage VSS, and a control terminal connected to node N1.
[0047] 2.3 Discharge Operation Figure 8 shows an example of the state before the discharge operation is performed in the discharge circuit according to the second embodiment.
[0048] During the period before the discharge operation is performed, the control circuit 32 generates a signal PG at the "H" level. The "H" level signal PG turns on transistor TR1. Consequently, current I1 flows through resistor R1 and transistor TR1. When current I1 flows, the voltage at node N1 is the voltage across the power line L PLPThe voltage drops to a level that turns off transistors TR2 and TR3. Therefore, since transistors TR2 and TR3 are in the off state, no current flows through resistor R2, transistor TR2, resistor R3, and transistor TR3.
[0049] Next, the discharge operation in the discharge circuit 35A will be explained using Figure 9. Figure 9 is a diagram showing an example of the state in which the discharge operation in the discharge circuit according to the second embodiment is performed.
[0050] During the discharge operation, the control circuit 32 generates an "L" level signal PG. The "L" level signal PG turns off transistor TR1. As a result, no current I1 flows through resistor R1 and transistor TR1. When no current I1 flows, the voltage at node N1 is the same as the power line L. PLP The voltage will be approximately the same as that of the power line L. PLP The voltage turns on transistors TR2 and TR3. Consequently, current I2 flows through resistor R2 and transistor TR2, and current I3 flows through resistor R3 and transistor TR3. Therefore, the power remaining in converter 33 is supplied to the power line L OUT1 The power is consumed by resistor R3 and transistor TR3 via the power line L, and the power remaining in converter 34 is also consumed by the power line L OUT2 The energy is consumed through resistor R2 and transistor TR2.
[0051] 2.4 Power Off Operation Figure 10 is a waveform diagram showing an example of the power-off operation in the power control circuit according to the second embodiment. The vertical axis of the waveform diagram shown in Figure 10 represents voltage. The horizontal axis of the waveform diagram shown in Figure 10 represents time. Figure 10 corresponds to Figure 5 in the first embodiment.
[0052] The power-off operation according to the second embodiment up to time T3 is equivalent to the power-off operation according to the first embodiment.
[0053] At time T3, the control circuit 32 turns off converters 33 and 34 with an "L" level signal PG. The discharge circuit 35 is powered by the power line L OUT1 and power line L OUT2 A discharge path is formed in this way. Consequently, the power line L OUT1 and power line L OUT2 The voltage drops rapidly to voltage VSS.
[0054] 2.5 Effects according to the second embodiment The discharge circuit 35A is configured to discharge the power remaining in the converter 33 using the power remaining in the backup power supply 31 after the power supply from the main power supply 4 and the backup power supply 31 has been stopped. This prevents the memory controller 10 from remaining powered on due to the power remaining in the converter 33 after the power-off operation. Therefore, the possibility of communication errors occurring during the power-on operation can be further suppressed.
[0055] Furthermore, according to the second embodiment, the discharge circuit 35A is composed of three resistors and three transistors. As a result, the manufacturing cost of the discharge circuit 35A can be reduced compared to a discharge circuit with a complex circuit configuration using relays, etc.
[0056] Furthermore, according to the second embodiment, resistor R3 is designed to have low resistance. This allows the power remaining in the converter 33 to be discharged quickly.
[0057] 3. Third Embodiment Next, a memory system according to the third embodiment will be described. In the third embodiment, the power line L OUT2 In addition, power line L B This differs from the first embodiment in that a discharge path is also formed. The following will mainly describe the configuration and operation that differ from the first embodiment. The configuration and operation equivalent to that of the first embodiment will be omitted from the description as appropriate.
[0058] 3.1 Power Control Circuit Figure 11 is a block diagram showing an example of the configuration of an information system according to the third embodiment. Figure 11 corresponds to Figure 1 in the first embodiment.
[0059] The information processing system 1 according to the third embodiment includes a host 2 and a memory system 3. The memory system 3 according to the third embodiment includes a memory controller 10, a non-volatile memory 20, and a power control circuit 30. The power control circuit 30 according to the third embodiment includes a backup power supply 31, a control circuit 32, a converter 33, a converter 34, and a discharge circuit 35B. The configuration of the host 2, memory controller 10, non-volatile memory 20, backup power supply 31, control circuit 32, converter 33, and converter 34 is the same as in the first embodiment.
[0060] The discharge circuit 35B is a circuit configured to perform a discharge operation. In the third embodiment, the discharge operation is performed on the power line L B The power remaining in the control circuit 32 is discharged via the power line L OUT2 This operation discharges the power remaining in the converter 34 via the discharge circuit 35B. The discharge circuit 35B is driven based on the power supplied from the backup power supply 31.
[0061] 3.2 Discharge circuit Figure 12 is a circuit diagram showing an example of the configuration of a discharge circuit according to the third embodiment. Figure 12 corresponds to Figure 2 in the first embodiment. The discharge circuit 35B includes resistors R1, R2, R4, transistors TR1, TR2, and TR4. The configuration of resistors R1, R2, transistors TR1, and TR2 is the same as in the first embodiment.
[0062] Resistor R4 is a low resistance resistor, for example, having a value similar to that of resistor R2. Resistor R4 is connected to the power line L B It has a first terminal connected to the first terminal of transistor TR4 and a second terminal connected to the first terminal of transistor TR4.
[0063] Transistor TR4 is, for example, an N-type field-effect transistor. Transistor TR4 has a first terminal, a second terminal which is grounded to the voltage VSS, and a control terminal which is connected to node N1.
[0064] 3.3 Discharge Operation Figure 13 shows an example of the state of the discharge circuit according to the third embodiment before the discharge operation is performed.
[0065] During the period before the discharge operation is performed, the control circuit 32 generates a signal PG at the "H" level. The "H" level signal PG turns on transistor TR1. Consequently, current I1 flows through resistor R1 and transistor TR1. When current I1 flows, the voltage at node N1 is the voltage across the power line L PLP The voltage drops to a level that turns off transistors TR2 and TR4. As a result, since transistors TR2 and TR4 are in the off state, no current flows through resistor R2, transistor TR2, resistor R4, and transistor TR4.
[0066] Next, the discharge operation in the discharge circuit 35B will be explained using Figure 14. Figure 14 is a diagram showing an example of the state in which the discharge operation in the discharge circuit according to the third embodiment is performed.
[0067] During the discharge operation, the control circuit 32 generates an "L" level signal PG. The "L" level signal PG turns off transistor TR1. As a result, no current I1 flows through resistor R1 and transistor TR1. If no current I1 flows, the voltage at node N1 is the power line L PLP The voltage will be approximately the same as that of the power line L. PLP The voltage turns on transistors TR2 and TR4. Consequently, current I2 flows through resistor R2 and transistor TR2, and current I4 flows through resistor R4 and transistor TR4. Therefore, the power remaining in the control circuit 32 is supplied to the power line L BThe power is consumed by resistor R4 and transistor TR4 via the power line L, and the power remaining in converter 34 is also consumed by the power line L OUT2 The energy is consumed through resistor R3 and transistor TR3.
[0068] 3.4 Power Off Operation Figure 15 is a waveform diagram showing an example of the power-off operation in the power control circuit according to the third embodiment. The vertical axis of the waveform diagram shown in Figure 15 represents voltage. The horizontal axis of the waveform diagram shown in Figure 15 represents time. Figure 15 corresponds to Figure 5 in the first embodiment.
[0069] The power-off operation according to the third embodiment up to time T3 is equivalent to the power-off operation according to the first embodiment.
[0070] At time T3, the control circuit 32 turns off converters 33 and 34 with an "L" level signal PG. The discharge circuit 35 is powered by the power line L B and power line L OUT2 A discharge path is formed in this way. Consequently, the power line L B and power line L OUT2 The voltage drops rapidly to voltage VSS. Power line L OUT1 The voltage is, OUT1_OFF It drops rapidly. After time T3, power line L OUT1 The voltage is, OUT1_OFF It is maintained between the voltage VSS.
[0071] 3.4 Effects of the Third Embodiment The discharge circuit 35B is configured to discharge the power remaining in the control circuit 32 using the power remaining in the backup power supply 31 after the power supply from the main power supply 4 and the backup power supply 31 has been stopped. This prevents the converters 33 and 34 from remaining powered on due to the power remaining in the control circuit 32 after the power-off operation. Therefore, the possibility of communication errors occurring during the power-on operation can be further suppressed.
[0072] Also, according to the third embodiment, the discharge circuit 35B is composed of three resistors and three transistors. Thereby, the manufacturing cost of the discharge circuit 35B can be suppressed compared to a discharge circuit having a complex circuit configuration using a relay or the like.
[0073] Also, according to the third embodiment, the resistor R4 is designed to have a low resistance. Thereby, the power remaining in the control circuit 32 can be discharged promptly.
[0074] The embodiments are illustrative and the scope of the invention is not limited thereto.
Explanation of Reference Numerals
[0075] 1... Information processing system 2... Host 3... Memory system 4... Main power supply 10... Memory controller 20... Non-volatile memory [[ID=2,6]] ... Power control circuit 31... Backup power supply 32... Control circuit 33, 34... Converter 35, 35A, 35B... Discharge circuit HB... Host bus MB... Memory bus L IN , L PLP , L B , L OUT1 , L OUT2 ... Power line R1, R2, R3, R4... Resistor TR1, TR2, TR3, TR4... Transistor PG... Signal
Claims
1. Memory controller and Non-volatile memory and It comprises a power control circuit configured to be supplied with power from the main power supply, The aforementioned power supply control circuit is Backup power supply and A first converter configured to supply power to the memory controller based on power supplied from the main power supply or the backup power supply, A second converter configured to supply power to the non-volatile memory based on power supplied from the main power supply or the backup power supply, A discharge circuit configured to discharge the power remaining in the second converter based on the power remaining in the backup power supply after the power supply from the main power supply and the backup power supply has been stopped, Includes, The aforementioned discharge circuit is A first resistor having a first terminal connected to the backup power supply, A first transistor connected in series with the first resistor, A second resistor having a first terminal is connected between the second converter and the non-volatile memory, A second transistor connected in series with the second resistor and having a control terminal connected between the first resistor and the first transistor, A memory system that includes this.
2. The resistance value of the first resistor is between 10 kΩ and 100 kΩ. The memory system according to claim 1.
3. The resistance value of the second resistor is between 100 Ω and 1 kΩ. The memory system according to claim 1.
4. The discharge circuit is configured to further discharge the power remaining in the first converter based on the power remaining in the backup power supply after the power supply from the main power supply and the backup power supply has been stopped. The memory system according to claim 1.
5. The aforementioned discharge circuit is A third resistor having a first end is connected between the second converter and the memory controller, A third transistor connected in series with the third resistor and having a control terminal connected between the first resistor and the first transistor, The memory system according to claim 4, further comprising:
6. The system further includes a control circuit configured to supply power to the first converter and the second converter based on power supplied from the main power supply or the backup power supply, The discharge circuit is configured to further discharge the power remaining in the control circuit based on the power remaining in the backup power supply after the power supply from the main power supply and the backup power supply has been stopped. The memory system according to claim 1.
7. The aforementioned discharge circuit is A fourth resistor having a first terminal is connected between the control circuit and the first converter and the second converter, A fourth transistor connected in series with the fourth resistor and having a control terminal connected between the first resistor and the first transistor, The memory system according to claim 6, further comprising:
8. Backup power supply and A converter configured to supply power to an external device based on power supplied from an external main power supply or the backup power supply, A discharge circuit configured to discharge the power remaining in the converter based on the power remaining in the backup power supply after the power supply from the main power supply and the backup power supply has been stopped, Includes, The aforementioned discharge circuit is A first resistor having a first terminal connected to the backup power supply, A first transistor connected in series with the first resistor, A second resistor having a first end is connected between the converter and the device, A second transistor connected in series with the second resistor and having a control terminal connected between the first resistor and the first transistor, A power control circuit, including a power supply control circuit.
9. The control circuit is further configured to supply power to the converter based on the power supplied from the main power supply or the backup power supply, The discharge circuit is configured to further discharge the power remaining in the control circuit based on the power remaining in the backup power supply after the power supply from the main power supply and the backup power supply has been stopped. The power supply control circuit according to claim 8.
10. The aforementioned discharge circuit is A fourth resistor having a first end is connected between the control circuit and the converter, A fourth transistor connected in series with the fourth resistor and having a control terminal connected between the first resistor and the first transistor, The power control circuit according to claim 9, further comprising: