Manufacturing method for semiconductor devices

Abstract

To improve the reliability of a semiconductor device.SOLUTION: Inside a trench TR1, a field plate electrode FP is formed through an insulating film IF1. In order to leave a part of the field plate electrode FP as an extraction part FPa, another part of the field plate electrode FP is removed selectively. After the insulating film IF1 is retracted, a protection film PF1 is formed on the insulating film IF1. A gate insulating film GI is formed inside the trench TR1 and an insulating film IF2 is formed so as to cover the field plate electrode FP. On the gate insulating film GI, the insulating film IF2, and the protection film PF1, a conductive film CF2 is formed. By removing the conductive film CF2 existing outside the trench TR1, a gate electrode GE is formed on the field plate electrode FP. At this time, the conductive film CF2 formed on the protection film PF1 and the insulating film IF2 in contact with the extraction part FPa is removed.SELECTED DRAWING: Figure 16

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having a gate electrode and a field plate electrode inside a trench.

Background Art

[0002] In a semiconductor device including a semiconductor element such as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a trench gate structure in which a gate electrode is embedded inside a trench is applied. As one type of trench gate structure, there is a split gate structure in which a field plate electrode is formed at the lower part of a trench and a gate electrode is formed at the upper part of the trench. A source potential is supplied from a source electrode to the field plate electrode. By expanding a depletion layer in a drift region by this field plate electrode, it becomes possible to increase the concentration of the drift region, and it becomes possible to reduce the resistance of the drift region.

[0003] For example, Patent Document 1 discloses a MOSFET having a split gate structure. The field plate electrode and the gate electrode of Patent Document 1 are formed as follows. First, after forming a field plate electrode inside a trench, the upper surface of the field plate electrode is recessed. Next, a conductive film for a gate electrode is deposited on a semiconductor substrate so as to fill the inside of the trench above the field plate electrode. Next, by performing an anisotropic etching process on the conductive film, a gate electrode is formed at the upper part of the trench.

Prior Art Documents

Patent Documents

[0004]

Patent Document Ⅰ

Summary of the Invention

Problems to be Solved by the Invention

[0005] Figure 50 shows a semiconductor device of a study example that the present inventors have examined based on Patent Document 1 and other sources. The field plate electrode FP includes a lead-out portion FPa for electrical connection to the source electrode. The field plate electrode FP of the lead-out portion FPa is formed not only at the bottom of the trench TR1 but also at the top of the trench TR1.

[0006] The field plate electrode FP is formed inside the trench TR1 via a thick insulating film IF1. Next, a portion of the field plate electrode FP is removed, causing it to recede from the top to the bottom of the trench TR1, while the remaining portion of the field plate electrode FP is left as a pull-out portion FPa. Next, a portion of the insulating film IF1 is removed, causing it to recede from the top to the bottom of the trench TR1. Then, a gate insulating film GI is formed inside the trench TR1 on the insulating film IF1, and an insulating film IF2 is formed to cover the field plate electrode FP exposed from the insulating film IF1. Finally, a conductive film CF2 for the gate electrode is deposited.

[0007] Next, an anisotropic etching process is performed on the conductive film CF2 to form a gate electrode on the upper part of the trench TR1. At this time, residue RS of the conductive film CF2 may remain on the side surface of the extraction portion FPa. When the MOSFET is operating, a source potential Vs of, for example, 0V is supplied to the extraction portion FPa, and a drain potential Vd of, for example, 100V is supplied to the drift region NV (semiconductor substrate SUB).

[0008] Normally, the dielectric strength between the lead portion FPa and the drift region NV is maintained by the thickness of the insulating film IF1. However, if electrically floating residue RS is present, a series capacitance is formed by the capacitance between the lead portion FPa and the residue RS (see Figure 50), and the capacitance between the residue RS and the drift region NV (see Figure 50). Since a voltage of 100V is applied to this series capacitance, there is a problem in that the dielectric strength between the lead portion FPa and the drift region NV can no longer be maintained.

[0009] In particular, increasing the thickness of the insulating film IF1 to improve the dielectric strength necessitates a longer isotropic etching time to recede the insulating film IF1, making it easier for residue RS to form at deeper positions. Furthermore, the space between the gate insulating film GI and the insulating film IF2 also widens, making it easier for larger residue RS to form.

[0010] The main objective of this invention is to suppress the generation of such residues RS and improve the reliability of semiconductor devices. Other challenges and novel features will become apparent from the description herein and the accompanying drawings. [Means for solving the problem]

[0011] A brief overview of some of the representative embodiments disclosed in this application is as follows:

[0012] A method for manufacturing a semiconductor device according to one embodiment includes: (a) a step of preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) a step of forming a trench in the semiconductor substrate after step (a) so as to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate; (c) a step of forming a first insulating film on the upper surface of the semiconductor substrate and inside the trench after step (b); (d) a step of forming a first conductive film on the first insulating film so as to fill the inside of the trench after step (c); and (e) a step of forming a first conductive film on the first insulating film after step (d). (f) a step of removing the first conductive film located outside the trench so that the first conductive film remaining inside the trench is formed as a field plate electrode; (g) a step of selectively removing the other part of the field plate electrode after step (e) so that a part of the field plate electrode is left as a pull-out portion; (f) after step (f) the first insulating film located on the upper surface of the semiconductor substrate is removed so that the position of the upper surface of the first insulating film located inside the trench in a cross-sectional view is above the field plate electrode. (h) After step (g), a step of moving the first insulating film located inside the trench toward the bottom of the trench so that it is lower than the position of the surface; (i) After step (h), a step of forming a first protective film on the upper surface of the semiconductor substrate and inside the trench so as to cover the field plate electrode and the first insulating film; (i) After step (h), removing the first protective film on the upper surface of the semiconductor substrate and moving the first protective film inside the trench toward the bottom of the trench so that the position of the upper surface of the first protective film is lower than the position of the upper surface of the field plate electrode. (j) Steps of retracting the protective film toward the bottom of the trench, (i) after step (i), forming a gate insulating film inside the trench located on the first protective film and forming a second insulating film so as to cover the field plate electrode exposed from the first protective film, (k) after step (j), forming a second conductive film on the gate insulating film, the second insulating film and the first protective film so as to fill the inside of the trench, (l) after step (k), removing the second conductive film located outside the trench,The process includes a step of forming the second conductive film remaining inside the trench on the field plate electrode as a gate electrode. The second conductive film formed in step (k) on the first protective film and the second insulating film in contact with the extraction portion is removed in step (l).

[0013] A method for manufacturing a semiconductor device according to one embodiment includes: (a) a step of preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) a step of forming a trench in the semiconductor substrate after step (a) so as to reach a predetermined depth from the upper surface of the semiconductor substrate; (c) a step of forming a first insulating film on the upper surface of the semiconductor substrate and inside the trench after step (b); (d) a step of forming a first conductive film on the first insulating film so as to fill the inside of the trench after step (c); and (e) a step of forming the first conductive film on the outside of the trench after step (d). (f) a step of removing the conductive film to form the first conductive film remaining inside the trench as a field plate electrode; (g) a step of forming a second protective film so as to cover the field plate electrode and the first insulating film on the upper surface of the semiconductor substrate after step (e); (h) a step of forming a first resist pattern on the second protective film after step (f) having a pattern that covers a part of the field plate electrode and leaves the other part of the field plate electrode open; (g) a step of massing the first resist pattern after step (g). (i) After step (h), perform an anisotropic etching process to remove the second protective film formed on the other part of the field plate electrode; (j) After step (i), perform an anisotropic etching process using the first resist pattern as a mask to selectively retract the other part of the field plate electrode so that the part of the field plate electrode remains as a pull-out portion; (k) After step (j), remove the first resist pattern; (l) After step (k), remove the second protective film formed on the pull-out portion and the first insulating film on the upper surface of the semiconductor substrate, and retract the first insulating film inside the trench so that the position of the upper surface of the first insulating film is lower than the position of the upper surface of the field plate electrode; (m) After step (l), fill the inside of the trench with the gate insulating film,The process includes the steps of (n) forming a second conductive film on the second insulating film and the first insulating film, and (m) after step (m), removing the second conductive film on the outside of the trench, thereby forming the second conductive film remaining inside the trench as a gate electrode on the field plate electrode. The second conductive film formed in step (m) on the first insulating film and the second insulating film in contact with the extraction portion is removed in step (n).

[0014] A method for manufacturing a semiconductor device according to one embodiment includes: (a) a step of preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) a step of forming a trench in the semiconductor substrate after step (a) so as to reach a predetermined depth from the upper surface of the semiconductor substrate; (c) a step of forming a first insulating film on the upper surface of the semiconductor substrate and inside the trench after step (b); (d) a step of forming a first conductive film on the first insulating film so as to fill the inside of the trench after step (c); (e) a step of forming the first conductive film remaining inside the trench as a field plate electrode by removing the first conductive film outside the trench after step (d); and (f) a step of forming the semiconductor substrate (g) a step of forming a mask layer on the upper surface of the semiconductor substrate having a pattern that covers a part of the field plate electrode and leaves an opening for the other part of the field plate electrode; (f) a step of selectively retracting the other part of the field plate electrode using the mask layer as a mask after step (f), so that the part of the field plate electrode remains as a pull-out portion; (h) a step of removing the first insulating film on the upper surface of the semiconductor substrate that is exposed from the mask layer using the mask layer as a mask, and retracting the first insulating film inside the trench so that the position of the upper surface of the first insulating film exposed from the mask layer is lower than the position of the upper surface of the field plate electrode. [Effects of the Invention]

[0015] According to one embodiment, the reliability of semiconductor devices can be improved.

Brief Description of the Drawings

[0016] [Figure 1] It is a plan view showing a semiconductor device in Embodiment 1. [Figure 2] It is a plan view of a main part showing a semiconductor device in Embodiment 1. [Figure 3] It is a plan view of a main part showing a semiconductor device in Embodiment 1. [Figure 4] It is a plan view showing the layout of a field plate electrode and a gate electrode in Embodiment 1. [Figure 5] It is a cross-sectional view showing a semiconductor device in Embodiment 1. [Figure 6] It is a cross-sectional view showing the manufacturing process of a semiconductor device in Embodiment 1. [Figure 7] It is a cross-sectional view showing the manufacturing process following FIG. 6. [Figure 8] It is a cross-sectional view showing the manufacturing process following FIG. 7. [Figure 9] It is a cross-sectional view showing the manufacturing process following FIG. 8. [Figure 10] It is a cross-sectional view showing the manufacturing process following FIG. 9. [Figure 11] It is a cross-sectional view showing the manufacturing process following FIG. 10. [Figure 12] It is a cross-sectional view showing the manufacturing process following FIG. 11. [Figure 13] It is a cross-sectional view showing the manufacturing process following FIG. 12. [Figure 14] It is a cross-sectional view showing the manufacturing process following FIG. 13. [Figure 15] It is a cross-sectional view showing the manufacturing process following FIG. 14. [Figure 16] It is a cross-sectional view showing the manufacturing process following FIG. 15. [Figure 17] It is a cross-sectional view showing the manufacturing process following FIG. 16. [Figure 18] It is a cross-sectional view showing the manufacturing process following FIG. 17. [Figure 19] It is a cross-sectional view showing the manufacturing process following FIG. 18. [Figure 20] This is a cross-sectional view showing the manufacturing process following Figure 19. [Figure 21] This is a cross-sectional view showing the manufacturing process following Figure 20. [Figure 22] This is a cross-sectional view showing the manufacturing process of a semiconductor device in Embodiment 2. [Figure 23] This is a cross-sectional view showing the manufacturing process following Figure 22. [Figure 24] This is a cross-sectional view showing the manufacturing process following Figure 23. [Figure 25] This is a cross-sectional view showing the manufacturing process following Figure 24. [Figure 26] This is a cross-sectional view showing a semiconductor device in Embodiment 2. [Figure 27] This is a cross-sectional view showing the manufacturing process of a semiconductor device in modified example 1. [Figure 28] This is a cross-sectional view showing a semiconductor device in a modified example (1). [Figure 29] This is a plan view of the main components of a semiconductor device in modified example 1. [Figure 30] This is a cross-sectional view showing the manufacturing process of a semiconductor device in Embodiment 3. [Figure 31] This is a cross-sectional view showing the manufacturing process following Figure 30. [Figure 32] This is a cross-sectional view showing the manufacturing process following Figure 31. [Figure 33] This is a cross-sectional view showing the manufacturing process following Figure 32. [Figure 34] This is a cross-sectional view showing the manufacturing process following Figure 33. [Figure 35] This is a cross-sectional view showing the manufacturing process of a semiconductor device in modified example 2. [Figure 36] Figure 35 is a cross-sectional view of the main parts showing the manufacturing process in detail. [Figure 37] This is a cross-sectional view showing the manufacturing process following Figure 35. [Figure 38] This is a cross-sectional view showing the manufacturing process following Figure 37. [Figure 39] This is a cross-sectional view showing the manufacturing process following Figure 38. [Figure 40]This is a cross-sectional view showing the manufacturing process following Figure 39. [Figure 41] This is a cross-sectional view showing the manufacturing process following Figure 40. [Figure 42] This is a cross-sectional view showing the manufacturing process of a semiconductor device in Embodiment 4. [Figure 43] This is a cross-sectional view showing the manufacturing process following Figure 42. [Figure 44] This is a cross-sectional view showing the manufacturing process following Figure 43. [Figure 45] This is a cross-sectional view showing the manufacturing process of a semiconductor device in modified example 3. [Figure 46] This is a cross-sectional view showing the manufacturing process following Figure 45. [Figure 47] This is a cross-sectional view showing the manufacturing process following Figure 46. [Figure 48] This is a cross-sectional view showing the manufacturing process following Figure 47. [Figure 49] This is a cross-sectional view showing the manufacturing process following Figure 48. [Figure 50] This is a cross-sectional view showing a semiconductor device in the example under consideration. [Modes for carrying out the invention]

[0017] The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless it is particularly necessary.

[0018] Furthermore, the X, Y, and Z directions described in this application intersect and are orthogonal to each other. In this application, the Z direction is described as the vertical direction, height direction, or thickness direction of a structure. Also, expressions such as "plan view" or "planar view" used in this application mean that the surface formed by the X and Y directions is called a "plane," and this "plane" is viewed from the Z direction.

[0019] (Embodiment 1) <Structure of a semiconductor device> The semiconductor device 100 in Embodiment 1 will be described below with reference to Figures 1 to 5. The semiconductor device 100 includes a trench gate structure MOSFET as a semiconductor element. The MOSFET in Embodiment 1 has a split gate structure comprising a gate electrode GE and a field plate electrode FP.

[0020] Figure 1 is a plan view of a semiconductor chip, which is a semiconductor device 100. Figure 2 is an enlarged plan view of the main part of region 1A shown in Figure 1. Figure 3 shows the lower structure of Figure 2, mainly showing the trench gate structure formed on the semiconductor substrate SUB. The positions of holes CH1 to CH3 shown in Figure 2 coincide with the positions of holes CH1 to CH3 shown in Figure 3. Figure 4 is a plan view showing the layout of the field plate electrode FP and gate electrode GE. Figure 5 is a cross-sectional view along lines AA and BB shown in Figures 2 and 3.

[0021] Figure 1 shows the wiring pattern mainly formed on top of the semiconductor substrate SUB. The semiconductor device 100 has a cell region CR and an outer peripheral region OR that surrounds the cell region CR in a plan view. Multiple main semiconductor elements such as MOSFETs are formed in the cell region CR. The outer peripheral region OR is used for connecting the gate wiring GW to the gate electrode GE and for forming an outer peripheral trench TR2 that functions as a termination region.

[0022] As shown in Figures 1 and 2, the majority of the cell region CR is covered by the source electrode SE. In a plan view, the gate wiring GW surrounds the source electrode SE. Although not shown here, the source electrode SE and gate wiring GW are covered with a protective film such as a polyimide film. An opening is provided in a part of the protective film, and the source electrode SE and gate wiring GW exposed at this opening become the source pad SP and gate pad GP. By connecting external connection members to the source pad SP and gate pad GP, the semiconductor device 100 is electrically connected to other semiconductor chips, lead frames, or wiring boards. The external connection members are, for example, wires made of aluminum, gold, or copper, or clips made of copper plates.

[0023] As shown in Figure 3, multiple trenches TR1 are formed in the semiconductor substrate SUB of the cell region CR. The multiple trenches TR1 are formed in a stripe pattern, each extending in the Y direction and adjacent to one another in the X direction.

[0024] As shown in Figure 5 (a cross-sectional view along line AA shown in Figures 2 and 3), a field plate electrode FP is formed at the bottom of trench TR1, and a gate electrode GE is formed at the top of trench TR1. The field plate electrode FP and the gate electrode GE extend in the Y direction along trench TR1.

[0025] As shown in Figure 5 (a cross-sectional view along the BB line shown in Figures 2 and 3), a portion of the field plate electrode FP forms a lead-out portion FPa. The field plate electrode FP constituting the lead-out portion FPa is formed not only in the lower part of the trench TR1 but also in the upper part of the trench TR1.

[0026] An outer trench TR2 is formed in the semiconductor substrate SUB of the outer peripheral region OR. The outer trench TR2 extends in the Y and X directions so as to surround the cell region CR. The width of trench TR2 is the same as that of trench TR1. A field plate electrode FP (with a lead-out portion FPa) is formed inside trench TR2.

[0027] In the cell region CR, a hole CH3 is formed on the lead portion FPa. The lead portion FPa is electrically connected to the source electrode SE via hole CH3. In the outer region OR, a hole CH2 is formed on the gate electrode GE. The gate electrode GE is electrically connected to the gate wiring GW via hole CH2. Also in the outer region OR, a hole CH3 is formed on a portion of the field plate electrode FP. The field plate electrode FP is electrically connected to the source electrode SE via hole CH3.

[0028] As shown in Figure 5, in trench TR1, the gate electrode GE and the lead portion FPa of the field plate electrode FP are exposed from the semiconductor substrate SUB. In trench TR2, the field plate electrode FP is exposed from the semiconductor substrate SUB. Figure 4 shows the overall layout of the exposed field plate electrode FP and gate electrode GE. In Figure 4, the exposed field plate electrode FP is shown by a solid line, and the exposed gate electrode GE is shown by a dashed line.

[0029] The cross-sectional structure of the semiconductor device 100 will be described below with reference to Figure 5.

[0030] In Embodiment 1, the cross-sectional views along the CC line shown in Figures 2 and 3 are the same as the cross-sectional views along the BB line, except that the trench reference number TR2 is different. Therefore, the explanation of the cross-sectional views along the BB line will also be explained below.

[0031] As shown in Figure 5, the semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS. The semiconductor substrate SUB is made of n-type silicon. The semiconductor substrate SUB has a low-concentration n-type drift region NV. In this embodiment, the n-type semiconductor substrate SUB itself constitutes the drift region NV. The semiconductor substrate SUB may also be a laminate of an n-type silicon substrate and an n-type semiconductor layer grown on the silicon substrate while introducing phosphorus (P) by epitaxial growth. In that case, the low-concentration n-type semiconductor layer constitutes the drift region NV, and the high-concentration n-type silicon substrate constitutes the drain region ND.

[0032] As shown in Figure 5, an n-type drain region ND is formed at the bottom of the semiconductor substrate SUB. The drain region ND has a higher impurity concentration than the drift region NV. A drain electrode DE is formed below the bottom surface BS of the semiconductor substrate SUB. The drain electrode DE consists of a single layer metal film such as an aluminum film, titanium film, nickel film, gold film, or silver film, or a multilayer film formed by appropriately stacking these metal films. The drain region ND and the drain electrode DE are formed across the cell region CR and the outer peripheral region OR. The drain potential is supplied to the semiconductor substrate SUB (drain region ND, drift region NV) from the drain electrode DE.

[0033] Multiple trenches TR1 are formed in the semiconductor substrate SUB, extending from the upper surface TS of the semiconductor substrate SUB to the lower surface BS to a predetermined depth. The depth of each trench TR1 is, for example, 5 μm or more and 7 μm or less. Inside the trench TR1, a field plate electrode FP is formed at the lower part of the trench TR1 via an insulating film IF1 and a protective film PF1. Also inside the trench TR1, a gate electrode GE is formed at the upper part of the trench TR1 via a gate insulating film GI. The field plate electrode FP and the gate electrode GE are each made of, for example, a polycrystalline silicon film into which n-type impurities have been introduced.

[0034] The upper surface of the insulating film IF1 is lower than the upper surface of the field plate electrode FP. The protective film PF1 is formed inside the trench TR1 on the insulating film IF1. The gate insulating film GI is formed inside the trench TR1 on the protective film PF1. The insulating film IF2 is formed to cover the field plate electrode FP that is exposed from the protective film PF1. In addition, the gate electrode GE is also formed between the field plate electrode FP exposed from the protective film PF1 and the semiconductor substrate SUB via the gate insulating film GI and insulating film IF2.

[0035] The insulating film IF1 and protective film PF1 are formed between the semiconductor substrate SUB and the field plate electrode FP. The insulating film IF2 is formed between the gate electrode GE and the field plate electrode FP. The gate insulating film GI is formed between the semiconductor substrate SUB and the gate electrode GE. These films electrically insulate the semiconductor substrate SUB, the gate electrode GE, and the field plate electrode FP from each other. In addition, an insulating film IF3 is formed on the gate electrode GE. The insulating film IF3 is made of, for example, a silicon oxide film.

[0036] The insulating film IF1, protective film PF1, insulating film IF2, and gate insulating film GI are made of, for example, silicon oxide film. The thickness of insulating film IF1 is greater than the thickness of insulating film IF2 and gate insulating film GI, respectively. Inside the trench TR1, the thickness of insulating film IF1 and protective film PF1 is, for example, 400 nm or more and 600 nm or less. Also, inside the trench TR1, the thickness of insulating film IF2 and gate insulating film GI is, for example, 50 nm or more and 70 nm or less. These thicknesses are in the X direction.

[0037] As shown in Figure 5, a p-type body region PB is formed on the upper part of the semiconductor substrate SUB, to a depth shallower than the trench TR1. An n-type source region NS is formed within the body region PB. The source region NS has a higher impurity concentration than the drift region NV.

[0038] An interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB, covering the trench TR1. The interlayer insulating film IL is made of, for example, a silicon oxide film. The thickness of the interlayer insulating film IL is, for example, 700 nm or more and 900 nm or less.

[0039] The interlayer insulating film IL has pores CH1 that penetrate the interlayer insulating film IL and the source region NS, and reach the body region PB. At the bottom of the pores CH1, a high-concentration diffusion region PR is formed in the body region PB. The high-concentration diffusion region PR has a higher impurity concentration than the body region PB.

[0040] A source electrode SE is formed on the interlayer insulating film IL. The source electrode SE is electrically connected to the source region NS, the body region PB, and the high-concentration diffusion region PR via pore CH1, supplying a source potential to these impurity regions.

[0041] As shown in the BB cross-section of Figure 5 (a cross-sectional view along the BB line shown in Figures 2 and 3), a portion of the field plate electrode FP forms the lead-out portion FPa of the field plate electrode FP. The upper surfaces of the insulating film IF1 and protective film PF1 in contact with the lead-out portion FPa are higher than the upper surfaces of the insulating film IF1 and protective film PF1 in contact with the field plate electrode FP other than the lead-out portion FPa.

[0042] An insulating film IF2 is formed on the side surface of the lead portion FPa exposed from the protective film PF1. Additionally, an insulating film IF3 is formed on the protective film PF1. Note that the insulating film IF3 may or may not be formed. Furthermore, a body region PB is formed on the semiconductor substrate SUB adjacent to the lead portion FPa, but the source region NS is not formed within this body region PB.

[0043] The interlayer insulating film IL has holes CH3 that penetrate the interlayer insulating film IL and reach the extraction portion FPa. The source electrode SE is electrically connected to the extraction portion FPa via holes CH3 and supplies the source potential to the field plate electrode FP.

[0044] Although not shown in the diagram, the interlayer insulating film IL has a hole CH2 that penetrates the interlayer insulating film IL and reaches the gate electrode GE. The gate wiring GW is electrically connected to the gate electrode GE via the hole CH2 and supplies the gate potential to the gate electrode GE.

[0045] Plug PGs are embedded inside the holes CH1 to CH3. The plug PGs consist of, for example, a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film consists of a laminated film of a titanium film and a titanium nitride film. The conductive film is, for example, a tungsten film.

[0046] The source electrode SE and gate wiring GW consist, for example, of a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a titanium-tungsten film, and the conductive film is, for example, an aluminum alloy film with copper or silicon added.

[0047] <Main features of Embodiment 1> In Embodiment 1, unlike the example in Figure 50, a protective film PF1 is formed on the insulating film IF1. More specifically, in a cross-sectional view, the protective film PF1 is located between the insulating film IF1 and the insulating film IF2. Therefore, the distance between the upper surface of the extraction portion FPa and the upper surface of the protective film PF1 in a cross-sectional view is closer than the distance in the example. For example, the distance from the upper surface of the extraction portion FPa to the upper surface of the protective film PF1 in a cross-sectional view is 100 nm or less. Consequently, when the conductive film CF2 for the gate electrode GE is etched, the conductive film CF2 formed around the extraction portion FPa is removed.

[0048] In other words, the residue RS shown in the example is less likely to form on the side surface of the FPa in the extraction portion via the insulating film IF2. Therefore, the dielectric strength between the FPa in the extraction portion and the drift region NV can be maintained, thereby improving the reliability of the semiconductor device 100.

[0049] <Manufacturing method for semiconductor devices> The following describes each manufacturing process included in the manufacturing method of the semiconductor device 100, using Figures 6 to 21.

[0050] First, an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS is prepared, as shown in Figure 6. As described above, the semiconductor substrate SUB may be a laminate of an n-type silicon substrate and an n-type semiconductor layer formed on the silicon substrate by an epitaxial growth method.

[0051] Next, as shown in Figure 7, trenches TR1 are formed in the semiconductor substrate SUB to a predetermined depth from the upper surface TS to the lower surface BS of the semiconductor substrate SUB. First, a silicon oxide film is formed on the semiconductor substrate SUB, for example, by CVD (Chemical Vapor Deposition). Next, a hard mask HM is formed by patterning the silicon oxide film using photolithography and anisotropic etching. Then, trenches TR1 are formed in the semiconductor substrate SUB by performing anisotropic etching using the hard mask HM as a mask. After that, the hard mask HM is removed by wet etching using, for example, a solution containing hydrofluoric acid.

[0052] Next, as shown in Figure 8, an insulating film IF1 is first formed inside the trench TR1 and on the upper surface TS of the semiconductor substrate SUB. The insulating film IF1 is, for example, a silicon oxide film formed by thermal oxidation. Note that the insulating film IF1 may be a laminated film of a first silicon oxide film formed by thermal oxidation and a second silicon oxide film formed on the first silicon oxide film by CVD.

[0053] Next, a conductive film CF1 is formed on the insulating film IF1, for example by CVD, so as to fill the inside of the trench TR1. The conductive film CF1 is, for example, an n-type polycrystalline silicon film. In order to properly fill the inside of the trench TR1 with the conductive film CF1, the deposition of the conductive film CF1 may be carried out in multiple steps (for example, two steps: deposition of the first polycrystalline silicon film and deposition of the second polycrystalline silicon film).

[0054] Next, as shown in Figure 9, the conductive film CF1 located outside the trench TR1 is removed, thereby forming the conductive film CF1 remaining inside the trench TR1 as a field plate electrode FP.

[0055] Specifically, first, the conductive film CF1 formed on the outside of the trench TR1 is removed by polishing, for example, using the CMP (Chemical Mechanical Polishing) method. Next, by etching, for example, using SF6 gas, the position of the upper surface of the conductive film CF1 inside the trench TR1 is moved backward toward the bottom of the trench TR1 (i.e., in the direction of the arrow shown in Figure 9). This forms the conductive film CF1 remaining inside the trench TR1 as a field plate electrode FP.

[0056] Next, as shown in Figure 10, the remaining portion of the field plate electrode FP is selectively removed so that a portion of the field plate electrode FP remains as a pull-out portion FPa.

[0057] Specifically, first, a resist pattern RP1 is formed that selectively covers a portion of the field plate electrode FP that will become the extraction portion FPa, as shown in the BB cross section. Next, using the resist pattern RP1 as a mask, an etching process is performed using, for example, SF6 gas to remove a portion of the field plate electrode FP that will not become the extraction portion FPa. That is, as shown in the AA cross section of Figure 10 (a cross section along the AA line shown in Figures 2 and 3), the other portion of the field plate electrode FP that will not become the extraction portion FPa is selectively receded toward the bottom of the trench TR1 (i.e., in the direction of the arrow shown in Figure 10). The portion of the field plate electrode FP that was not receded becomes the extraction portion FPa. After that, the resist pattern RP1 is removed by an ashing process.

[0058] Next, as shown in Figure 11, the insulating film IF1 is subjected to isotropic etching using a hydrofluoric acid solution. This removes the insulating film IF1 located on the upper surface TS of the semiconductor substrate SUB, and also causes the insulating film IF1 located inside the trench TR1 to recede towards the bottom of the trench TR1 (i.e., in the direction of the arrow shown in Figure 11) so that the position of the upper surface of the insulating film IF1 located inside the trench TR1 is lower than the position of the upper surface of the field plate electrode FP in a cross-sectional view.

[0059] At this point, the upper surface of the insulating film IF1 in contact with the field plate electrodes FP other than the lead-out portion FPa is lower than the upper surface of the insulating film IF1 in contact with the field plate electrodes FP of the lead-out portion FPa. Furthermore, by removing the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB, the upper surface of the lead-out portion FPa is higher than the upper surface TS of the semiconductor substrate SUB, as shown in the BB cross section of Figure 11.

[0060] Next, as shown in Figure 12, a protective film PF1 is formed on the upper surface TS of the semiconductor substrate SUB and inside the trench TR1, for example by CVD, so as to cover the field plate electrode FP and the insulating film IF1. The protective film PF1 is an insulating film, for example, a silicon oxide film.

[0061] Furthermore, the thickness of the protective film PF1 formed on the upper surface TS of the semiconductor substrate SUB is thinner than the thickness of the insulating film IF1 formed on the upper surface TS of the semiconductor substrate SUB in the process shown in Figure 8. The thickness of the insulating film IF1 on the upper surface TS in Figure 8 is, for example, 400 nm or more and 600 nm or less. The thickness of the protective film PF1 on the upper surface TS in Figure 12 is, for example, 200 nm or more and 300 nm or less.

[0062] Next, as shown in Figure 13, the protective film PF1 is subjected to isotropic etching using a hydrofluoric acid solution. This removes the protective film PF1 located on the upper surface TS of the semiconductor substrate SUB, and also causes the protective film PF1 located inside the trench TR1 to recede towards the bottom of the trench TR1 (i.e., in the direction of the arrow shown in Figure 13) so that, in a cross-sectional view, the position of the upper surface of the protective film PF1 located inside the trench TR1 is lower than the position of the upper surface of the field plate electrode FP.

[0063] As mentioned above, the thickness of the protective film PF1 formed in the process shown in Figure 12 is thinner than the thickness of the insulating film IF1 formed in the process shown in Figure 8, so the time for the isotropic etching process in Figure 13 is shorter than the time for the isotropic etching process in Figure 11. Therefore, the amount of film removed in the etching process in Figure 13 is easier to adjust (control) than the amount of film removed in the etching process in Figure 11. Consequently, the amount of recession of the protective film PF1 inside the trench TR1 is smaller than the amount of recession of the insulating film IF1. Therefore, as shown in the cross-section of BB, the position of the upper surface of the protective film PF1 can be brought closer to the position of the upper surface TS of the semiconductor substrate SUB and the upper surface of the extraction portion FPa. At this point, the distance from the upper surface of the extraction portion FPa to the upper surface of the protective film PF1 in the cross-sectional view is 100 nm or less.

[0064] Next, by performing a thermal oxidation treatment, a gate insulating film GI is formed inside the trench TR1 located on the protective film PF1, as shown in Figure 14, and an insulating film IF2 is formed to cover the field plate electrode FP exposed from the protective film PF1.

[0065] Next, a conductive film CF2 is formed on the gate insulating film GI, the insulating film IF2, and the protective film PF1, for example by CVD, to fill the inside of the trench TR1. The conductive film CF2 is, for example, an n-type polycrystalline silicon film.

[0066] Next, as shown in Figure 15, the conductive film CF2 is polished using the CMP method. This reduces the thickness of the conductive film CF2 and flattens the upper surface of the conductive film CF2.

[0067] Next, as shown in Figure 16, the conductive film CF2 located outside the trench TR1 is removed by anisotropic etching. This forms the conductive film CF2 remaining inside the trench TR1 on the field plate electrode FP as the gate electrode GE.

[0068] Furthermore, in order to completely remove the conductive film CF2 outside the trench TR1, the anisotropic etching process is performed as over-etching. As a result, as shown in the AA cross-section of Figure 16, the position of the upper surface of the gate electrode GE is slightly lower than the position of the upper surface TS of the semiconductor substrate SUB.

[0069] Furthermore, this anisotropic etching process removes the conductive film CF2 that was formed on the protective film PF1 and the insulating film IF2 in contact with the extraction portion FPa. In other words, as mentioned above, in this embodiment, since the protective film PF1 is formed in advance on the insulating film IF1, it is difficult for residue RS, as in the example under consideration, to form on the side surface of the extraction portion FPa via the insulating film IF2 at the end of the process in Figure 16. As a result, the dielectric strength between the extraction portion FPa and the drift region NV can be maintained, thereby improving the reliability of the semiconductor device 100.

[0070] Next, as shown in Figure 17, an insulating film IF3 is formed on the upper surface TS of the semiconductor substrate SUB and on the gate electrode GE, for example by CVD, so as to cover the trench TR1.

[0071] Next, as shown in Figure 18, an anisotropic etching treatment is performed on the insulating film IF3. As a result, as shown in the AA cross-section, insulating film IF3 remains on the upper surface of a portion of the gate electrode GE, in contact with the gate insulating film GI located inside the trench TR1. Also, as shown in the BB cross-section, insulating film IF3 remains on the side surface of the extraction portion FPa via insulating film IF2. Furthermore, this anisotropic etching treatment also removes the gate insulating film GI on the upper surface TS of the semiconductor substrate SUB and the insulating film IF2 on the upper surface of the extraction portion FPa. Note that, as mentioned above, the gate insulating film GI located inside the trench TR1 is covered by the remaining insulating film IF3, so this anisotropic etching treatment removes the gate insulating film GI located on the upper surface TS of the semiconductor substrate SUB, but the gate insulating film GI located inside the trench TR1 remains, as shown in the AA cross-section.

[0072] Next, as shown in Figure 19, p-type body regions PB are selectively formed on the semiconductor substrate SUB by introducing, for example, boron (B) using photolithography and ion implantation techniques. The body regions PB are formed to be shallower than the depth of the trench TR1.

[0073] Next, using photolithography and ion implantation techniques, for example, arsenic (As) is introduced to selectively form an n-type source region NS within the body region PB of the cell region CR. Note that no source region NS is formed in the body region PB adjacent to the extraction portion FPa. Subsequently, the semiconductor substrate SUB is subjected to heat treatment to diffuse impurities contained in the source region NS and body region PB.

[0074] Next, as shown in Figure 20, an interlayer insulating film IL is first formed on the upper surface TS of the semiconductor substrate SUB, for example by CVD, so as to cover the trench TR1.

[0075] Next, pores CH1 to CH3 are formed in the interlayer insulating film IL. First, a resist pattern is formed on the interlayer insulating film IL, having a pattern that opens up the semiconductor substrate SUB on which the source region NS is formed. Next, anisotropic etching is performed using the resist pattern as a mask to form pores CH1 that penetrate the interlayer insulating film IL and the source region NS and reach the interior of the body region PB. Then, by ion implantation, for example, boron (B) is introduced into the body region PB at the bottom of pores CH1 to form a p-type high-concentration diffusion region PR. After that, the resist pattern is removed by ashing.

[0076] Next, a resist pattern is formed on the interlayer insulating film IL, having a pattern that opens on the extraction portion FPa and the gate electrode GE. Then, anisotropic etching is performed using the resist pattern as a mask to form holes CH3 that penetrate the interlayer insulating film IL and reach the extraction portion FPa. Although not shown here, holes CH2 that penetrate the interlayer insulating film IL and reach the gate electrode GE are also formed in the process of forming holes CH3. After that, the resist pattern is removed by ashing.

[0077] The order in which pores CH1 to CH3 are formed does not matter.

[0078] Next, as shown in Figure 21, plugs PG are formed inside holes CH1 to CH3, and source electrodes SE and gate wiring GW are formed on the interlayer insulating film IL.

[0079] Specifically, first, a first barrier metal film is formed inside the pores CH1 to CH3 and on the interlayer insulating film IL by sputtering or CVD. The first barrier metal film consists of, for example, a laminated film of titanium nitride and titanium. Next, a first conductive film is formed on the first barrier metal film by CVD. The first conductive film consists of, for example, a tungsten film. Next, the first barrier metal film and the first conductive film formed outside the pores CH1 to CH3 are removed by CMP or anisotropic etching. As a result, a plug PG consisting of the first barrier metal film and the first conductive film is formed to fill the inside of the pores CH1 to CH3.

[0080] Next, a second barrier metal film is formed on the interlayer insulating film IL by sputtering. The second barrier metal film is, for example, a titanium-tungsten film. Next, a second conductive film is formed on the second barrier metal film by sputtering. The second conductive film is, for example, an aluminum alloy film with copper or silicon added. Next, the source electrode SE and gate wiring GW are formed by patterning the second barrier metal film and the second conductive film.

[0081] Next, although not shown in the diagram, a protective film made of, for example, a polyimide film is formed on the source electrode SE and gate wiring GW, for example, by a coating method. By forming an opening in a part of the protective film, the regions of the source electrode SE and gate wiring GW that will become the source pad SP and gate pad GP are exposed.

[0082] Subsequently, the structure shown in Figure 5 is obtained through the following manufacturing process. First, the bottom surface BS of the semiconductor substrate SUB is polished as needed. Next, an n-type drain region ND is formed on the bottom surface BS of the semiconductor substrate SUB by introducing, for example, arsenic (As) using an ion implantation method. Note that if the semiconductor substrate SUB is composed of a laminate of an n-type silicon substrate and an n-type semiconductor layer, the high-concentration n-type silicon substrate forms the drain region ND, so the formation of the drain region ND by ion implantation described above can be omitted. Next, a drain electrode DE is formed beneath the bottom surface BS of the semiconductor substrate SUB by sputtering.

[0083] (Embodiment 2) The semiconductor device 100 in Embodiment 2 will be described below with reference to Figures 22 to 26. In the following description, the differences from Embodiment 1 will be mainly explained, and points that overlap with Embodiment 1 will not be explained.

[0084] In Embodiment 1, the generation of residue RS of the conductive film CF2 was suppressed by the protective film PF1, but in Embodiment 2, the residue RS is removed by anisotropic etching using the resist pattern RP2. Figure 22 shows the manufacturing process following Figure 11 of Embodiment 1.

[0085] First, by performing a thermal oxidation treatment, a gate insulating film GI is formed inside the trench TR1 located on the insulating film IF1, as shown in Figure 22, and an insulating film IF2 is formed to cover the field plate electrode FP exposed from the insulating film IF1.

[0086] Next, a conductive film CF2 is formed on the gate insulating film GI, insulating film IF2, and insulating film IF1, for example, by CVD, so as to fill the inside of the trench TR1. Then, the conductive film CF2 is polished using CMP.

[0087] Next, as shown in Figure 23, the conductive film CF2 that was formed on the outside of the trench TR1 is removed by anisotropic etching. This forms the conductive film CF2 remaining inside the trench TR1 on the field plate electrode FP as the gate electrode GE.

[0088] Furthermore, while this anisotropic etching process removes the conductive film CF2 formed on the upper surface of the FPa in the extraction portion via the insulating film IF2, residue RS of the conductive film CF2 may remain on the side surface of the FPa in the extraction portion via the insulating film IF2.

[0089] Next, as shown in Figure 24, a resist pattern RP2 is first formed on the upper surface TS of the semiconductor substrate SUB, having a pattern that selectively opens the lead portion FPa of the field plate electrodes FP. The field plate electrodes FP other than the lead portion FPa are covered by the resist pattern RP2.

[0090] Next, an anisotropic etching process is performed on the conductive film CF2 using the resist pattern RP2 as a mask. This anisotropic etching process is carried out under conditions where the gate insulating film GI and insulating film IF2 are difficult to etch, while the conductive film CF2 is easily etched. As a result, even if residual RS remains on the side surface of the FPa extraction portion via insulating film IF2, the residual RS can be completely removed.

[0091] Next, as shown in Figure 25, an insulating film IF3 is formed on the upper surface of the semiconductor substrate SUB, for example by CVD, so as to cover the trench TR1. Then, an anisotropic etching treatment is performed on the insulating film IF3. As a result, as shown in the cross-section AA, the insulating film IF3 remains on the upper surface of a portion of the gate electrode GE, in contact with the gate insulating film GI. Also, as shown in the cross-section BB, the insulating film IF3 remains on the side surface of the extraction portion FPa via the insulating film IF2. In other words, the region (gap) from which the residue RS was removed in the previous step is sealed by the insulating film IF3.

[0092] Subsequently, by performing the same manufacturing process as shown in Figure 19 and subsequent figures of Embodiment 1, the structure shown in Figure 26 is obtained. In this way, in Embodiment 2 as well, the residue RS of the conductive film CF2 is removed from the side surface of the field plate electrode FP (drawout portion FPa), thereby improving the reliability of the semiconductor device 100.

[0093] Furthermore, the technology of Embodiment 2 can also be applied to each embodiment, such as Embodiment 1. For example, in Embodiment 1, an anisotropic etching treatment may be performed using the resist pattern RP2 shown in Figure 24 of Embodiment 2 after anisotropic etching treatment of the conductive film CF2 (see Figure 16) and before forming the insulating film IF3 (see Figure 17). In this way, even if the conductive film CF2 is not completely removed by anisotropic etching treatment of the conductive film CF2 and residue RS of the conductive film CF2 remains on the side surface of the extraction portion FPa via the insulating film IF2, this residue RS can be removed more reliably by the anisotropic etching treatment shown in Figure 24 of Embodiment 2.

[0094] (Variation 1) The semiconductor device 100 in modified example 1 of Embodiment 2 will be described below with reference to Figures 27 to 29.

[0095] The technology of Embodiment 2 is basically applied to all of the lead-out portions FPa formed on the semiconductor device 100, but in Modification 1, the technology of Embodiment 2 is applied to only some of the lead-out portions FPa.

[0096] Specifically, the technique of Embodiment 2 is applied to the "field plate electrode FP (drawout portion FPa) of the outer trench TR2" shown in Figure 4. That is, the residue RS is removed from the outer trench TR2, as shown in the cross section along the CC line in Figure 3.

[0097] On the other hand, the technology of Embodiment 2 is not applied to the "field plate electrode FP within the cell region CR," the "field plate electrode FP at the end of the cell region CR," and the "field plate electrode FP under the gate pad GP" shown in Figure 4. At least for the "field plate electrode FP within the cell region CR," the technology of Embodiment 2 is not applied, and residue RS is deliberately left behind.

[0098] In Figure 24 of Embodiment 2, the resist pattern RP2 covered the field plate electrodes FP other than the draw-out portions FPa. In Modification 1, as shown in Figure 27, the resist pattern RP2 covers not only the field plate electrodes FP other than the draw-out portions FPa, but also the draw-out portions FPa of the cell region CR, leaving the draw-out portions FPa of the outer peripheral region OR open. In this state, the same anisotropic etching process as in Embodiment 2 is performed on the conductive film CF2 using the resist pattern RP2 as a mask.

[0099] The residue RS formed on the side surface of the field plate electrode FP (extraction portion FPa) of the outer trench TR2 is removed by the anisotropic etching process described above. On the other hand, the residue RS formed on the side surface of the extraction portion FPa of trench TR1 remains as part of the gate electrode GE. As shown in Figure 28, a portion of this remaining gate electrode GE becomes the connecting portion GEa. The connecting portion GEa is formed on both sides of the extraction portion FPa via the insulating film IF2 in the X direction.

[0100] Figure 29 is a partially enlarged plan view of the trench gate in Figure 4, mainly focusing on the gate electrode (GE).

[0101] The gate electrode GE includes a first end in the Y direction and a second end located opposite the first end in the Y direction. The first end is the end of the gate electrode GE located in the upper outer peripheral region OR in the figure, and the second end is the end of the gate electrode GE located in the lower outer peripheral region OR in the figure.

[0102] The lead-out portion FPa is formed inside the trench TR1 located between the gate electrode GE at the first end and the gate electrode GE at the second end. In other words, the gate electrode GE is divided into upper and lower halves by the lead-out portion FPa.

[0103] For example, when forming pore CH2, the pore CH2 may not reach the gate electrode GE due to insufficient etching or other reasons. In other words, there is a risk that either the pore CH2 on the first end side or the second end side will not open. This would cause a problem where the MOSFET that utilizes the gate electrode GE on either the first end side or the second end side will cease to function.

[0104] To address these problems, in Modification 1, a connecting portion GEa is provided on the side surface of the drawer portion FPa. The connecting portion GEa connects the gate electrode GE on the first end side and the gate electrode GE on the second end side within the trench TR1 in which the drawer portion FPa is formed.

[0105] For example, even if the hole CH2 on the second end side is closed and the gate potential is not directly supplied to the gate electrode GE on the second end side, the gate potential is still supplied to the gate electrode GE on the second end side from the gate electrode GE on the first end side via the connecting portion GEa. Therefore, the above-mentioned problem can be resolved.

[0106] Thus, according to Modification 1, the residue RS can be removed in the outer region OR, and the MOSFET utilizing the gate electrode GE can be made to function normally in the cell region CR. Therefore, the reliability of the semiconductor device 100 can be further improved.

[0107] (Embodiment 3) The semiconductor device 100 in Embodiment 3 will be described below with reference to Figures 30 to 34. In the following description, the differences from Embodiment 1 will be mainly explained, and points that overlap with Embodiment 1 will not be explained.

[0108] In Embodiment 3, the formation of residue RS is suppressed by further forming a protective film PF2 on the insulating film IF1 formed on the upper surface TS of the semiconductor substrate SUB. Figure 30 shows the manufacturing process following Figure 9 of Embodiment 1.

[0109] As shown in Figure 30, a protective film PF2 is formed, for example by CVD, to cover the insulating film IF1 on the upper surface TS of the field plate electrode FP and the semiconductor substrate SUB. The protective film PF2 is, for example, a silicon oxide film. The thickness of the protective film PF2 is, for example, 200 nm or more and 550 nm or less, which is thinner than the thickness of the silicon oxide film etched by the isotropic etching process described later.

[0110] As shown in Figure 31, first, a resist pattern RP1 is formed on the protective film PF2, similar to Embodiment 1, to selectively cover a portion of the field plate electrode FP which will become the pull-out portion FPa. Next, the protective film PF2 formed on the rest of the field plate electrode FP is removed by performing anisotropic etching using the resist pattern RP1 as a mask.

[0111] Next, using the resist pattern RP1 as a mask, the field plate electrode FP is subjected to etching using, for example, SF6 gas. This selectively recedes other parts of the field plate electrode FP. The portion of the field plate electrode FP that was not receded becomes the pull-out portion FPa. Subsequently, the resist pattern RP1 is removed by ashing.

[0112] Alternatively, the resist pattern RP1 may be removed after removing the protective film PF2 formed on other parts of the field plate electrode FP. In this case, the anisotropic etching treatment of the field plate electrode FP is performed under conditions in which the protective film PF2 and insulating film IF1 are difficult to etch, and the field plate electrode FP is easily etched.

[0113] As shown in Figure 32, the silicon oxide film (protective film PF2 and insulating film IF1) is subjected to isotropic etching using a hydrofluoric acid-containing solution. This removes the protective film PF2 formed on the extraction portion FPa and the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB. At the same time, the insulating film IF1 inside the trench TR1 is retracted so that the position of the upper surface of the insulating film IF1 is lower than the position of the upper surface of the field plate electrode FP.

[0114] Note that Figure 32 illustrates a case where a small amount of insulating film IF1 remains on the upper surface TS of the semiconductor substrate SUB in the BB cross-section. However, it is also possible for this insulating film IF1 to be completely removed, exposing the upper surface TS of the semiconductor substrate SUB in the BB cross-section.

[0115] Since a protective film PF2 was formed on the lead-out portion FPa, the amount of recession of the insulating film IF1 in contact with the lead-out portion FPa is less than in the example shown in Figure 50, due to the thickness of the protective film PF2. As a result, the position of the upper surface of the lead-out portion FPa and the position of the upper surface of the insulating film IF1 are closer than in the example. For example, the distance between the position of the upper surface of the lead-out portion FPa and the position of the upper surface of the insulating film IF1 is 100 nm or less.

[0116] As shown in Figure 33, the gate insulating film GI and insulating film IF2 are formed using the same method as in Embodiment 1. Next, a conductive film CF2 is formed on the gate insulating film GI, insulating film IF2, and insulating film IF1 so as to fill the inside of the trench TR1. Then, the conductive film CF2 is polished using the CMP method.

[0117] As shown in Figure 34, the conductive film CF2, which was formed on the outside of the trench TR1, is removed by anisotropic etching. This forms the gate electrode GE inside the trench TR1 on the field plate electrode FP.

[0118] The subsequent manufacturing process is the same as the manufacturing process shown in Figure 17 and later in Embodiment 1.

[0119] As described above, in Embodiment 3, the formation of the protective film PF2 brings the upper surface of the extraction portion FPa and the upper surface of the insulating film IF1 closer together. Therefore, the conductive film CF2 formed on the insulating film IF1 and insulating film IF2 in contact with the extraction portion FPa can be easily removed by the anisotropic etching process shown in Figure 34. Thus, the technology of Embodiment 3 can also suppress the formation of residue RS as in the example under consideration.

[0120] (Modification 2) The semiconductor device 100 in modified example 2 of Embodiment 3 will be described below with reference to Figures 35 to 41.

[0121] In the modified example 2, before forming the protective film PF2, a planarization treatment is performed on the field plate electrode FP and the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB.

[0122] Figure 35 shows the planarization process performed after the manufacturing process shown in Figure 8. For example, there are two methods for the planarization process in Modification Example 2, and Figure 36 shows the details of these two methods.

[0123] As shown in Figure 36, in "Planarization Process 1," first, the conductive film CF1 is polished using the CMP method to form a field plate electrode FP. At this time, the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB functions as an etching stopper. Through this polishing process, the upper surfaces of both the field plate electrode FP and the insulating film IF1 become flush.

[0124] Next, an anisotropic etching process is performed on the insulating film IF1 and the field plate electrode FP on the upper surface TS of the semiconductor substrate SUB. This anisotropic etching process is carried out under conditions that make both the insulating film IF1 and the field plate electrode FP easily abrasive.

[0125] As shown in Figure 36, in "Planarization Process 2," first, a field plate electrode FP is formed by polishing the conductive film CF1 using the CMP method. Next, an anisotropic etching process is performed on the field plate electrode FP so that the position of the upper surface of the field plate electrode FP is lower than the position of the upper surface of the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB.

[0126] Next, an anisotropic etching treatment is performed on the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB. This anisotropic etching treatment is carried out under conditions in which the insulating film IF1 is difficult to etch, and the field plate electrode FP (conductive film CF1) is easily etched.

[0127] In the "Planarization Process 2," a small gap is created between the insulating film IF1 and the field plate electrode FP near the top of the field plate electrode FP. This gap is filled by the protective film PF2 in the next process. As a result, the upper surfaces of both the field plate electrode FP and the insulating film IF1 become substantially flush.

[0128] Figure 37 shows the manufacturing process following Figure 35 (Figure 36). As shown in Figure 37, a protective film PF2 is formed, for example by CVD, to cover the insulating film IF1 on the upper surface TS of the field plate electrode FP and the semiconductor substrate SUB.

[0129] As shown in Figure 38, first, a resist pattern RP1 is formed on the protective film PF2. Next, the protective film PF2 formed on other parts of the field plate electrode FP is removed by anisotropic etching using the resist pattern RP1 as a mask. Then, anisotropic etching is performed on the field plate electrode FP using the resist pattern RP1 as a mask. This selectively recedes other parts of the field plate electrode FP. The part of the field plate electrode FP that was not receded becomes the pull-out portion FPa. After that, the resist pattern RP1 is removed by ashing.

[0130] As shown in Figure 39, the protective film PF2 and the insulating film IF1 are subjected to isotropic etching using a hydrofluoric acid-containing solution. This removes the protective film PF2 formed on the extraction portion FPa and the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB. At the same time, the insulating film IF1 inside the trench TR1 is retracted so that the position of the upper surface of the insulating film IF1 is lower than the position of the upper surface of the field plate electrode FP.

[0131] In the modified example 2, the amount of recession of the insulating film IF1 in contact with the extraction portion FPa is less than in the example shown in Figure 50, due to the thickness of the protective film PF2. For example, the distance between the upper surface of the extraction portion FPa and the upper surface of the insulating film IF1 is 50 nm or less.

[0132] As shown in Figure 40, gate insulating film GI and insulating film IF2 are formed. Next, a conductive film CF2 is formed on the gate insulating film GI, insulating film IF2, and insulating film IF1 so as to fill the inside of the trench TR1. Then, the conductive film CF2 is polished using the CMP method.

[0133] As shown in Figure 41, the conductive film CF2, which was formed on the outside of the trench TR1, is removed by anisotropic etching. This forms the gate electrode GE inside the trench TR1 on the field plate electrode FP.

[0134] The subsequent manufacturing process is the same as the manufacturing process shown in Figure 17 and later in Embodiment 1.

[0135] As described above, in Modification 2, as in Embodiment 3, the formation of the protective film PF2 brings the position of the upper surface of the lead-out portion FPa and the position of the upper surface of the insulating film IF1 closer together. Furthermore, in Modification 2, the planarization process eliminates the gap between the insulating film IF1 and the field plate electrode FP near the top of the field plate electrode FP.

[0136] Therefore, as shown in the BB cross section of Figure 39, after the insulating film IF1 is recessed by isotropic etching, the upper surface of the insulating film IF1 becomes almost flat. Consequently, when the conductive film CF2 is formed, the conductive film CF2 does not enter the gap. Therefore, in modified example 2, compared to embodiment 3, it becomes easier to remove the conductive film CF2 on the insulating film IF1 during the anisotropic etching of the conductive film CF2, thus further suppressing the formation of residue RS as in the example under consideration.

[0137] (Embodiment 4) The semiconductor device 100 in Embodiment 4 will be described below with reference to Figures 42 to 44. In the following description, the differences from Embodiment 1 will be mainly explained, and points that overlap with Embodiment 1 will not be explained.

[0138] In Embodiment 4, the same mask layer MK1 is used as a mask, and the steps of retracting the field plate electrode FP and retracting the insulating film IF1 are performed consecutively. Figure 42 shows the manufacturing process following Figure 10 of Embodiment 1.

[0139] As shown in Figure 42, first, the resist pattern RP1 used to retract the field plate electrode FP in Figure 10 is left as the mask layer MK1. Next, using the mask layer MK1 as a mask, the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB that is exposed from the mask layer MK1 is removed. At the same time, the insulating film IF1 inside the trench TR1 is retracted so that the position of the upper surface of the insulating film IF1 exposed from the mask layer MK1 is lower than the position of the upper surface of the field plate electrode FP. After that, the mask layer MK1 (resist pattern RP1) is removed by ashing.

[0140] As shown in Figure 43, the gate insulating film GI and insulating film IF2 are formed. Next, a conductive film CF2 is formed on the gate insulating film GI, insulating film IF2, and insulating film IF1 so as to fill the inside of the trench TR1. Then, the conductive film CF2 is polished using the CMP method.

[0141] As shown in Figure 44, the conductive film CF2, which was formed on the outside of the trench TR1, is removed by anisotropic etching. This forms the gate electrode GE inside the trench TR1 on the field plate electrode FP.

[0142] The subsequent manufacturing process is the same as the manufacturing process shown in Figure 17 and later in Embodiment 1.

[0143] In Embodiment 4, during the process of retracting the insulating film IF1, the insulating film IF1 in contact with the extraction portion FPa is covered by the mask layer MK1 and does not retract. Therefore, the position of the upper surface of the extraction portion FPa and the position of the upper surface of the insulating film IF1 are close together. Consequently, the conductive film CF2 formed on the insulating film IF1 and insulating film IF2 in contact with the extraction portion FPa can be easily removed by the anisotropic etching process shown in Figure 44. Thus, the formation of residue RS as in the example can also be suppressed by the technique of Embodiment 4.

[0144] (Variation 3) The semiconductor device 100 in the modified example 3 of Embodiment 4 will be described below with reference to Figures 45 to 49.

[0145] In the third modified example, a mask layer MK2 different from the resist pattern RP1 is used to continuously perform the steps of receding the field plate electrode FP and receding the insulating film IF1. Figure 45 shows the manufacturing process following Figure 9 of Embodiment 1.

[0146] As shown in Figure 45, a mask layer MK2 is formed, for example by CVD, to cover the insulating film IF1 on the upper surface TS of the field plate electrode FP and the semiconductor substrate SUB. The mask layer MK2 is an insulating film made of a different material from the insulating films IF1 and IF2, the gate insulating film GI, the field plate electrode FP (conductive film CF1), and the gate electrode GE (conductive film CF2), and is, for example, a silicon nitride film. The thickness of the mask layer MK2 is, for example, 50 nm or more and 200 nm or less.

[0147] As shown in Figure 46, first, a resist pattern RP1 similar to that in Embodiment 1 is formed on the mask layer MK2. Next, the mask layer MK2 is patterned by performing anisotropic etching using the resist pattern RP1 as a mask. The mask layer MK2 has an opening pattern corresponding to the opening pattern of the resist pattern RP1. That is, the mask layer MK2 has a pattern that covers a part of the field plate electrode FP and leaves the other part of the field plate electrode FP open.

[0148] Next, using the mask layer MK2 as a mask, the field plate electrode FP is subjected to etching using, for example, SF6 gas. This selectively recedes other parts of the field plate electrode FP. The portion of the field plate electrode FP that was not receded becomes the pull-out portion FPa. After that, the resist pattern RP1 is removed by ashing.

[0149] During this anisotropic etching process, the resist pattern RP1 may be used as a mask along with the mask layer MK2, but the resist pattern RP1 may be removed immediately after patterning the mask layer MK2. In other words, it is also possible to retract the field plate electrode FP using only the mask layer MK2 as a mask.

[0150] As shown in Figure 47, the insulating film IF1 on the upper surface TS of the semiconductor substrate SUB, which is exposed from the mask layer MK2, is removed. At the same time, the insulating film IF1 inside the trench TR1 is retracted so that the position of the upper surface of the insulating film IF1 exposed from the mask layer MK2 is lower than the position of the upper surface of the field plate electrode FP.

[0151] As shown in Figure 48, the gate insulating film GI and insulating film IF2 are formed. Note that the upper surface of the extraction portion FPa is covered by the mask layer MK2, so insulating film IF2 is not formed on the upper surface of the extraction portion FPa. Next, a conductive film CF2 is formed on the gate insulating film GI, insulating film IF2, and insulating film IF1 so as to fill the inside of the trench TR1. Next, the conductive film CF2 is polished using the CMP method.

[0152] As shown in Figure 49, the conductive film CF2, which was formed on the outside of the trench TR1, is removed by anisotropic etching. This forms the gate electrode GE inside the trench TR1 on the field plate electrode FP.

[0153] Subsequently, the mask layer MK2 is removed by anisotropic etching or isotropic etching using a phosphoric acid-containing solution. Note that the removal of the mask layer MK2 may also be performed immediately after the insulating film IF1 inside the trench TR1 shown in Figure 47 has been retracted.

[0154] The subsequent manufacturing process is the same as the manufacturing process shown in Figure 17 and later in Embodiment 1.

[0155] In Modification 3, during the process of retracting the insulating film IF1, the insulating film IF1 in contact with the extraction portion FPa is covered by the mask layer MK2 and does not retract. Therefore, the position of the upper surface of the extraction portion FPa and the position of the upper surface of the insulating film IF1 are close together. Consequently, the conductive film CF2 formed on the mask layer MK2 in contact with the extraction portion FPa can be easily removed by the anisotropic etching process shown in Figure 49. Thus, the formation of residue RS as in the example can also be suppressed by the technique of Modification 3.

[0156] Although the present invention has been specifically described above based on the above embodiments, the present invention is not limited to the above embodiments and can be modified in various ways without departing from the spirit of the invention.

[0157] Some of the details described in the above embodiment are described below.

[0158] [Note 1] (a) A step of preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface, (b) After step (a), a step of forming a trench in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate. (c) After step (b), a step of forming a first insulating film on the upper surface of the semiconductor substrate and inside the trench, (d) After step (c), a step of forming a first conductive film on the first insulating film so as to fill the inside of the trench, (e) After step (d), remove the first conductive film from the outside of the trench, thereby forming the first conductive film remaining inside the trench as a field plate electrode. (f) After step (e), a step of forming a first resist pattern on the upper surface of the semiconductor substrate, having a pattern that covers a part of the field plate electrode and leaves the other part of the field plate electrode open. (g) After step (f), a step of selectively retracting the other part of the field plate electrode by performing an anisotropic etching process using the first resist pattern as a mask, such that the part of the field plate electrode remains as a pull-out portion. (h) After step (g) above, a step to remove the first resist pattern, (i) After step (h) above, remove the first insulating film on the upper surface of the semiconductor substrate, and move the first insulating film inside the trench back so that the position of the upper surface of the first insulating film is lower than the position of the upper surface of the field plate electrode, (j) After step (i) above, a step of forming a gate insulating film inside the trench located on the first insulating film, and forming a second insulating film so as to cover the field plate electrode exposed from the first insulating film, (k) After step (j) above, a step of forming a second conductive film on the gate insulating film, the second insulating film and the first insulating film so as to fill the interior of the trench. (l) After step (k) above, a step of removing the second conductive film on the outside of the trench so that the second conductive film remaining inside the trench is formed as a gate electrode on the field plate electrode, (m) After step (l) above, a step of forming a second resist pattern on the upper surface of the semiconductor substrate, having a pattern that selectively opens the lead portion of the field plate electrode. (n) After step (m), an anisotropic etching process is performed using the second resist pattern as a mask, under conditions that make it difficult to etch the gate insulating film and the second insulating film, and easy to etch the second conductive film. A method for manufacturing a semiconductor device, comprising:

[0159] [Note 2] A method for manufacturing a semiconductor device having a cell region in which a MOSFET is formed and an outer peripheral region surrounding the cell region in a plan view, (a) A step of preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface, (b) After step (a), a step of forming a first trench in the semiconductor substrate in the cell region so as to reach a predetermined depth from the upper surface of the semiconductor substrate, and forming a second trench in the semiconductor substrate in the outer peripheral region, (c) After step (b), a step of forming a first insulating film on the upper surface of the semiconductor substrate, inside the first trench and inside the second trench, (d) After step (c), a step of forming a first conductive film on the first insulating film so as to fill the interior of the first trench and the interior of the second trench, (e) After step (d), remove the first conductive film from the outside of the first trench and the outside of the second trench so that the first conductive film remaining inside the first trench is formed as a first field plate electrode, and the first conductive film remaining inside the second trench is formed as a second field plate electrode. (f) After step (e), a step of forming a first resist pattern on the upper surface of the semiconductor substrate, having a pattern that covers a part of the first field plate electrode and the second field plate electrode, and leaves the other part of the first field plate electrode open. (g) After step (f) above, a step of selectively retracting the other part of the first field plate electrode using the first resist pattern as a mask, such that the part of the first field plate electrode and the second field plate electrode remain as a pull-out portion. (h) After step (g) above, a step to remove the first resist pattern, (i) After step (h), remove the first insulating film on the upper surface of the semiconductor substrate, and retract the first insulating film inside the first trench and the second trench such that the position of the upper surface of the first insulating film is lower than the position of the upper surface of the first field plate electrode and the upper surface of the second field plate electrode. (j) After step (i), a step of forming a gate insulating film inside the first trench and inside the second trench located on the first insulating film, and forming a second insulating film so as to cover the first field plate electrode and the second field plate electrode exposed from the first insulating film, (k) After step (j), a step of forming a second conductive film on the gate insulating film, on the second insulating film and on the first insulating film so as to fill the interior of the first trench and the interior of the second trench. (l) After step (k) above, remove the second conductive film from the outside of the first trench and the outside of the second trench, thereby forming the second conductive film remaining inside the first trench as a gate electrode on the first field plate electrode. (m) After step (l), a step of forming a second resist pattern having a pattern that selectively opens the second field plate electrode on the upper surface of the semiconductor substrate, (n) After step (m), an anisotropic etching process is performed using the second resist pattern as a mask, under conditions that make it difficult to etch the gate insulating film and the second insulating film, and easy to etch the second conductive film. Equipped with, The first trench extends in a first direction in a plan view, The second trench extends in the first direction and in a second direction perpendicular to the first direction in a plan view, so as to surround the cell region. The gate electrode includes a first end in the first direction and a second end located opposite to the first end in the first direction. The lead portion of the first field plate electrode is formed inside the first trench located between the gate electrode on the first end and the gate electrode on the second end, In step (l) above, a connecting portion is formed on the side surface of the lead portion of the first field plate electrode via the second insulating film, connecting the gate electrode on the first end side and the gate electrode on the second end side as part of the gate electrode. In step (l) above, a residue of the second conductive film is formed on the side surface of the second field plate electrode via the second insulating film. The aforementioned residue is removed in step (n), a method for manufacturing a semiconductor device.

[0160] [Note 3] A semiconductor device having a cell region in which a MOSFET is formed and an outer peripheral region surrounding the cell region in a plan view, A first-type conductive semiconductor substrate having an upper surface and a lower surface, A first trench is formed in the semiconductor substrate in the cell region so as to reach a predetermined depth from the upper surface of the semiconductor substrate, A second trench is formed in the semiconductor substrate in the outer peripheral region so as to reach a predetermined depth from the upper surface of the semiconductor substrate, Inside the first trench, a first field plate electrode formed at the lower part of the first trench, Within the first trench, a gate electrode formed at the top of the first trench and electrically insulated from the first field plate electrode, A second field plate electrode formed inside the second trench, Equipped with, The first trench extends in a first direction in a plan view, The second trench extends in the first direction and in a second direction perpendicular to the first direction in a plan view, so as to surround the cell region. The gate electrode includes a first end in the first direction and a second end located opposite to the first end in the first direction. A portion of the first field plate electrode is formed within the first trench located between the gate electrode on the first end and the gate electrode on the second end, not only in the lower part of the first trench but also in the upper part of the first trench, and forms a lead-out portion of the first field plate electrode. The aforementioned extraction portion is formed inside the first trench located between the gate electrode on the first end and the gate electrode on the second end, A connecting portion is formed on the side surface of the lead portion via an insulating film, connecting the gate electrode on the first end and the gate electrode on the second end, as part of the gate electrode. A semiconductor device in which the conductive film constituting the gate electrode and the connecting portion is removed from the side surface of the second field plate electrode. [Explanation of symbols]

[0161] 100 Semiconductor Equipment 1A area BS semiconductor substrate bottom surface CF1, CF2 conductive film CH1, CH2, CH3 holes CR cell area DE drain electrode FP field plate electrode FPa drawer section GE Terminal GEa connecting section GI gate insulating film GP Gate Pad GW gate wiring HM Hard Mask IF1, IF2, IF3 insulating film IL interlayer film MK1, MK2 mask layer ND drain area NS source area NV drift region OR outer area PB Body Area PF1, PF2 protective film PR High-concentration diffusion area RP1, RP2 Resist Pattern RS residue SP Source Pad SUB Semiconductor Substrate SW Source Wiring TR1 Trench TR2 Outer Trench Top surface of TS semiconductor substrate

Claims

1. (a) A step of preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface, (b) After step (a), a step of forming a trench in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate, (c) After step (b), a step of forming a first insulating film on the upper surface of the semiconductor substrate and inside the trench, (d) After step (c), a step of forming a first conductive film on the first insulating film so as to fill the inside of the trench, (e) After step (d), remove the first conductive film located outside the trench, thereby forming the first conductive film remaining inside the trench as a field plate electrode. (f) A step of selectively removing the other part of the field plate electrode after step (e) such that a part of the field plate electrode remains as a pull-out portion. (g) After step (f), remove the first insulating film located on the upper surface of the semiconductor substrate, and move the first insulating film located inside the trench toward the bottom of the trench such that, in a cross-sectional view, the position of the upper surface of the first insulating film located inside the trench is lower than the position of the upper surface of the field plate electrode. (h) After step (g), a step of forming a first protective film on the upper surface of the semiconductor substrate and inside the trench so as to cover the field plate electrode and the first insulating film, (i) After step (h), remove the first protective film located on the upper surface of the semiconductor substrate, and move the first protective film located inside the trench toward the bottom of the trench such that, in a cross-sectional view, the position of the upper surface of the first protective film located inside the trench is lower than the position of the upper surface of the field plate electrode. (j) After step (i), a step of forming a gate insulating film inside the trench located on the first protective film, and forming a second insulating film so as to cover the field plate electrode exposed from the first protective film, (k) After step (j), a step of forming a second conductive film on the gate insulating film, the second insulating film and the first protective film so as to fill the inside of the trench, (l) After step (k), remove the second conductive film located outside the trench, thereby forming the second conductive film remaining inside the trench as a gate electrode on the field plate electrode. Equipped with, A method for manufacturing a semiconductor device, wherein the second conductive film formed in step (k) on the first protective film and the second insulating film in contact with the lead portion is removed in step (l).

2. In the method for manufacturing a semiconductor device according to claim 1, The first insulating film and the first protective film are silicon oxide films. A method for manufacturing a semiconductor device, wherein steps (g) and (i) are performed by isotropic etching using a solution containing hydrofluoric acid.

3. In the method for manufacturing a semiconductor device according to claim 1, A method for manufacturing a semiconductor device, wherein the thickness of the first protective film formed on the upper surface of the semiconductor substrate in step (h) is thinner than the thickness of the first insulating film formed on the upper surface of the semiconductor substrate in step (c).

4. In the method for manufacturing a semiconductor device according to claim 1, (m) After step (l), a step of forming a third insulating film on the upper surface and the gate electrode of the semiconductor substrate, (n) After step (m), a step of removing the third insulating film and the gate insulating film located outside the trench, A method for manufacturing a semiconductor device, further comprising the following features.

5. In the method for manufacturing a semiconductor device according to claim 4, (o) a step after step (l) and before step (m), of forming a resist pattern on the upper surface of the semiconductor substrate having a pattern that selectively opens the drawer portion of the field plate electrode, (p) After step (o) and before step (m), an etching process is performed using the resist pattern as a mask, under conditions that make it difficult to etch the gate insulating film, the second insulating film, and the first protective film, and easy to etch the second conductive film. A method for manufacturing a semiconductor device, further comprising the following features.

6. (a) A step of preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface, (b) After step (a), a step of forming a trench in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate, (c) After step (b), a step of forming a first insulating film on the upper surface of the semiconductor substrate and inside the trench, (d) After step (c), a step of forming a first conductive film on the first insulating film so as to fill the inside of the trench, (e) After step (d), remove the first conductive film located outside the trench, thereby forming the first conductive film remaining inside the trench as a field plate electrode. (f) After step (e), a step of forming a second protective film so as to cover the field plate electrode and the first insulating film on the upper surface of the semiconductor substrate, (g) After step (f), a step of forming a first resist pattern on the second protective film, having a pattern that covers a part of the field plate electrode and leaves the other part of the field plate electrode open. (h) After step (g), a step of removing the second protective film formed on the other part of the field plate electrode by performing an anisotropic etching process using the first resist pattern as a mask. (i) After step (h), a step of selectively retracting the other part of the field plate electrode by performing an etching process using the first resist pattern as a mask, such that the part of the field plate electrode remains as a pull-out portion. (j) After step (i), a step of removing the first resist pattern, (k) After step (j) above, remove the second protective film formed on the drawer portion and the first insulating film on the upper surface of the semiconductor substrate, and move the first insulating film inside the trench back so that the position of the upper surface of the first insulating film is lower than the position of the upper surface of the field plate electrode. (l) After step (k), a step of forming a gate insulating film inside the trench located on the first insulating film, and forming a second insulating film so as to cover the field plate electrode exposed from the first insulating film. (m) After step (l), a step of forming a second conductive film on the gate insulating film, the second insulating film and the first insulating film so as to fill the inside of the trench. (n) After step (m), remove the second conductive film on the outside of the trench, thereby forming the second conductive film remaining inside the trench as a gate electrode on the field plate electrode. Equipped with, A method for manufacturing a semiconductor device, wherein the second conductive film formed in step (m) on the first insulating film and the second insulating film in contact with the lead portion is removed in step (n).

7. In the method for manufacturing a semiconductor device according to claim 6, (o) A step of performing a planarization treatment on the field plate electrode and the first insulating film on the upper surface of the semiconductor substrate before step (f), A method for manufacturing a semiconductor device, further comprising the following features.

8. In the method for manufacturing a semiconductor device according to claim 7, The above step (o) is, (o1) During step (e), a step in which the first insulating film on the upper surface of the semiconductor substrate is used as an etching stopper and the first conductive film is subjected to polishing by the CMP method, (o2) Between step (o1) and step (f), an anisotropic etching process is performed on the first insulating film on the upper surface of the semiconductor substrate and the field plate electrode. A method for manufacturing a semiconductor device, further comprising the following features.

9. In the method for manufacturing a semiconductor device according to claim 7, The above step (o) is, (o3) After step (e), an anisotropic etching process is performed on the first conductive film such that the position of the upper surface of the field plate electrode is lower than the position of the upper surface of the first insulating film on the upper surface of the semiconductor substrate. (o4) Between step (o3) and step (f), a step of performing an anisotropic etching treatment on the first insulating film on the upper surface of the semiconductor substrate, A method for manufacturing a semiconductor device, further comprising the following features.

10. In the method for manufacturing a semiconductor device according to claim 6, The first insulating film and the second protective film are silicon oxide films. The method for manufacturing a semiconductor device, wherein step (k) is performed by isotropic etching using a solution containing hydrofluoric acid.

11. In the method for manufacturing a semiconductor device according to claim 10, A method for manufacturing a semiconductor device, wherein the thickness of the second protective film formed in step (f) is thinner than the thickness of the silicon oxide film etched by the isotropic etching process in step (k).

12. In the method for manufacturing a semiconductor device according to claim 6, (p) After step (n), a step of forming a second resist pattern on the upper surface of the semiconductor substrate, having a pattern that selectively opens the lead portion of the field plate electrode, (q) After step (p), perform an etching process using the second resist pattern as a mask, under conditions that make it difficult to etch the gate insulating film and the second insulating film, and easy to etch the second conductive film. A method for manufacturing a semiconductor device, further comprising the following features.

13. (a) A step of preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface, (b) After step (a), a step of forming a trench in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate, (c) After step (b), a step of forming a first insulating film on the upper surface of the semiconductor substrate and inside the trench, (d) After step (c), a step of forming a first conductive film on the first insulating film so as to fill the inside of the trench, (e) After step (d), remove the first conductive film located outside the trench, thereby forming the first conductive film remaining inside the trench as a field plate electrode. (f) After step (e), a step of forming a mask layer on the upper surface of the semiconductor substrate having a pattern that covers a part of the field plate electrode and leaves the other part of the field plate electrode open. (g) After step (f), using the mask layer as a mask, selectively retract the other part of the field plate electrode so that the part of the field plate electrode remains as a pull-out portion. (h) After step (g) above, using the mask layer as a mask, remove the first insulating film on the upper surface of the semiconductor substrate that is exposed from the mask layer, and retract the first insulating film inside the trench such that the position of the upper surface of the first insulating film exposed from the mask layer is lower than the position of the upper surface of the field plate electrode. (i) After step (h), a step of removing the mask layer, (j) After step (i), a step of forming a gate insulating film inside the trench located on the first insulating film, and forming a second insulating film so as to cover the field plate electrode exposed from the first insulating film, (k) After step (j), a step of forming a second conductive film on the gate insulating film, the second insulating film and the first insulating film so as to fill the interior of the trench. (l) After step (k), remove the second conductive film on the outside of the trench, thereby forming the second conductive film remaining inside the trench as a gate electrode on the field plate electrode. (m) After step (l), a step of forming a second resist pattern on the upper surface of the semiconductor substrate, having a pattern that selectively opens the lead portion of the field plate electrode. (n) After step (m), perform an etching process using the second resist pattern as a mask, under conditions that make it difficult to etch the gate insulating film and the second insulating film, and easy to etch the second conductive film. Equipped with, The mask layer is a first resist pattern, The second conductive film formed in step (k) on the first insulating film and the second insulating film in contact with the drawout portion is removed in step (l). The first insulating film is a silicon oxide film, The method for manufacturing a semiconductor device, wherein step (h) is performed by isotropic etching using a solution containing hydrofluoric acid.

14. (a) A step of preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface, (b) After step (a), a step of forming a trench in the semiconductor substrate so as to reach a predetermined depth from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate, (c) After step (b), a step of forming a first insulating film on the upper surface of the semiconductor substrate and inside the trench, (d) After step (c), a step of forming a first conductive film on the first insulating film so as to fill the inside of the trench, (e) After step (d), remove the first conductive film located outside the trench, thereby forming the first conductive film remaining inside the trench as a field plate electrode. (f) After step (e), a step of forming a mask layer on the upper surface of the semiconductor substrate having a pattern that covers a part of the field plate electrode and leaves the other part of the field plate electrode open. (g) After step (f), using the mask layer as a mask, selectively retract the other part of the field plate electrode so that the part of the field plate electrode remains as a pull-out portion. (h) After step (g) above, using the mask layer as a mask, remove the first insulating film on the upper surface of the semiconductor substrate that is exposed from the mask layer, and retract the first insulating film inside the trench such that the position of the upper surface of the first insulating film exposed from the mask layer is lower than the position of the upper surface of the field plate electrode. (i) After step (h), a step of forming a gate insulating film inside the trench located on the first insulating film, and forming a second insulating film so as to cover the field plate electrode exposed from the first insulating film, (j) After step (i), a step of forming a second conductive film on the gate insulating film, the second insulating film, the first insulating film and the mask layer so as to fill the inside of the trench, (k) After step (j), remove the second conductive film from the outside of the trench, thereby forming the second conductive film remaining inside the trench as a gate electrode on the field plate electrode. (l) After step (k), a step of removing the mask layer, Furthermore, The mask layer is an insulating film made of a different material from the first insulating film, the second insulating film, the gate insulating film, the first conductive film, and the second conductive film. A method for manufacturing a semiconductor device, wherein the second conductive film formed in step (j) on the mask layer in contact with the draw-out portion is removed in step (k).

15. In the method for manufacturing a semiconductor device according to claim 14, The first insulating film is a silicon oxide film, The method for manufacturing a semiconductor device, wherein step (h) is performed by isotropic etching using a solution containing hydrofluoric acid.

16. In the method for manufacturing a semiconductor device according to claim 14, (m) Between step (k) and step (l), a step of forming a resist pattern on the upper surface of the semiconductor substrate, having a pattern that selectively opens the drawer portion of the field plate electrode. (n) After step (m), perform an etching process using the resist pattern as a mask, under conditions that make it difficult to etch the gate insulating film, the second insulating film, and the mask layer, and that make it easy to etch the second conductive film. A method for manufacturing a semiconductor device, further comprising the following features.

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