Input / Output Devices

Abstract

To reduce the number of transistors for a photoelectric conversion element.SOLUTION: A display circuit that becomes a display state according to data of a display data signal, and a plurality of light detection circuits that generate light data according to the illuminance of incident light are included. The light detection circuit includes X (X is a natural number of 2 or more) photoelectric conversion elements, X charge accumulation control transistors in each of which one of a source and a drain is electrically connected to a second current terminal of one of the X photoelectric conversion elements and one of X charge accumulation control signals is input in a gate from a light detection circuit control unit, and an amplification transistor whose gate is electrically connected to one of the source and the drain of each of the X charge accumulation control transistors.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to an input / output device. [Background technology]

[0002] In recent years, devices have been developed that have the function of outputting information and the function of inputting information through the incidence of light. Technological development is underway for input / output devices (also known as input / output devices).

[0003] The input / output device consists of multiple display circuits and multiple light detection circuits (optical sensors) arranged in the matrix direction. The pixel section is equipped with a light sensor (also called a light sensor), and by detecting the illuminance of the light incident on the light sensor, the image A function to detect the coordinates of the object to be read superimposed on the base part (also called a coordinate detection function) and the reading An input / output device having a function to generate image data of the captured object (reading function) can be cited. For example, Patent Document 1). In the input / output device shown in Patent Document 1, a photodiode and an amplification transistor are used. The photodetection circuit is constructed using a zista, an initialization (reset) transistor, and a selection transistor. It has been done. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2010-182064 [Overview of the project] [Problems that the invention aims to solve]

[0005] In conventional input / output devices, an amplification transistor is used for each photodiode, which is a photoelectric conversion element. To provide a reset (photodetection reset) transistor and a selection transistor, one photoelectric There was a problem with the number of transistors relative to the conversion element. For example, reducing the size of pixels is difficult, and the shadow of the transistor's leakage current... The sound also gets louder.

[0006] One aspect of the present invention is to reduce the number of transistors for a single photoelectric conversion element and One or more of the challenges are to reduce the influence of transistor leakage current. do. [Means for solving the problem]

[0007] One aspect of the present invention relates to a photoelectric conversion element, a charge storage control transistor, and an amplification transistor. It includes a photodetection circuit and shares at least an amplification transistor with multiple photoelectric conversion elements. This constitutes a light detection circuit. This allows for a number of transistors in the pixel section. To reduce it.

[0008] Furthermore, one aspect of the present invention includes a photoelectric conversion element, a charge storage control transistor, and an amplification transistor. , and a photodetection circuit comprising an output selection transistor, and at least an amplification transistor and The photodetector circuit is configured by sharing the output selection transistor with multiple photoelectric conversion elements. This reduces the number of transistors in the pixel area.

[0009] Furthermore, one aspect of the present invention includes a photoelectric conversion element, a charge storage control transistor, and an amplification transistor. The optical detection circuit includes an output selection transistor and an optical detection reset transistor, At least an amplification transistor, an output selection transistor, and a photodetection reset transistor. This involves sharing multiple photoelectric conversion elements to form a photodetection circuit. The goal is to reduce the number of transistors in the pixel area.

[0010] Furthermore, in one aspect of the present invention, a charge storage control transistor with low off-current is provided for each photoelectric conversion element. A device is provided to hold an amount of charge corresponding to the illuminance of the light incident on the photoelectric conversion element for a certain period of time. Yes, this reduces the impact on the transistor's leakage current. [Effects of the Invention]

[0011] According to one aspect of the present invention, the number of transistors relative to the number of photoelectric conversion elements can be reduced. This allows for a reduction in the number of transistors in the pixel area. [Brief explanation of the drawing]

[0012] [Figure 1] A diagram illustrating the input / output device in Embodiment 1. [Figure 2] A diagram illustrating an example of a photodetection circuit in Embodiment 2. [Figure 3] A diagram illustrating an example of a photodetection circuit in Embodiment 3. [Figure 4] A diagram illustrating an example of a display circuit in Embodiment 4. [Figure 5] A diagram illustrating an example of a transistor in Embodiment 5. [Figure 6] A schematic cross-sectional diagram illustrating an example of a transistor fabrication method shown in Figure 5(A). [Figure 7] A diagram illustrating the characteristic evaluation circuit. [Figure 8] This figure shows the relationship between the elapsed time (Time) during measurement in SMP4, SMP5, and SMP6, the output voltage (Vout), and the leakage current calculated from the measurement. [Figure 9] A diagram showing the relationship between the voltage and leakage current at node A, as estimated by measurement. [Figure 10] A diagram showing the relationship between the voltage and leakage current at node A, as estimated by measurement. [Figure 11] A diagram showing the relationship between the voltage and leakage current at node A, as estimated by measurement. [Figure 12] A diagram showing the relationship between the voltage and leakage current at node A, as estimated by measurement. [Figure 13] This figure shows an example of the structure of an active matrix substrate in the input / output device of Embodiment 6. [Figure 14] This figure shows an example of the structure of an active matrix substrate in the input / output device of Embodiment 6. [Figure 15] A diagram showing an example of the structure of the input / output device in Embodiment 6. [Figure 16] A diagram showing an example of the structure of the input / output device in Embodiment 6. [Figure 17] A schematic diagram showing an example of the configuration of the electronic device in Embodiment 7. [Figure 18] A diagram illustrating the structure of an oxide material according to one aspect of the present invention. [Figure 19] A diagram illustrating the structure of an oxide material according to one aspect of the present invention. [Figure 20] A diagram illustrating the structure of an oxide material according to one aspect of the present invention. [Figure 21] This figure illustrates the gate voltage dependence of the mobility obtained through calculation. [Figure 22] This figure illustrates the gate voltage dependence of the drain current and mobility obtained through calculations. [Figure 23] This figure illustrates the gate voltage dependence of the drain current and mobility obtained through calculations. [Figure 24] This figure illustrates the gate voltage dependence of the drain current and mobility obtained through calculations. [Figure 25] This is a diagram illustrating the cross-sectional structure of the transistor used in the calculations. [Figure 26] A top view and a cross-sectional view of a transistor according to one aspect of the present invention. [Figure 27] Top view and cross-sectional view showing the structure of transistors corresponding to Sample 1 to Sample 6. [Figure 28]This figure shows the Vg-Id characteristics and field-effect mobility of transistors, which are sample 3 and sample 4. [Figure 29] This figure shows the Vg-Id characteristics and field-effect mobility of transistor sample 1 before and after the BT test. [Figure 30] This figure shows the Vg-Id characteristics and field-effect mobility of transistor sample 4 before and after the BT test. [Figure 31] This figure shows the Vg-Id characteristics and field-effect mobility of the transistor (sample 4) at different measurement temperatures. [Figure 32] This figure shows the temperature characteristics of the threshold voltage and field-effect mobility of the transistor, which is sample 4. [Figure 33] Figure showing the XRD spectrum of an In-Sn-Zn-O film. [Figure 34] A diagram showing the off-current of a transistor using an In-Sn-Zn-O film. [Modes for carrying out the invention]

[0013] An example of an embodiment illustrating the present invention will be described below with reference to the drawings. However, The present invention is not limited to the following description, and without departing from the spirit and scope of the present invention, It will be readily apparent to those skilled in the art that the form and details can be changed in various ways. Therefore, this The invention shall not be construed as being limited to the embodiments described below.

[0014] Furthermore, the contents of each embodiment can be combined with each other as appropriate. The contents of these can be interchanged.

[0015] Furthermore, the use of ordinal numbers such as "1st" and "2nd" is added to avoid confusion between the constituent elements. And each component is not limited to an ordinal number.

[0016] (Embodiment 1) In this embodiment, information can be output by displaying an image, and incident light This section describes an example of an input / output device that allows information to be input.

[0017] An example of an input / output device in this embodiment will be explained with reference to Figure 1. This is a diagram illustrating an example of an input / output device in its configuration.

[0018] First, an example of the configuration of the input / output device in this embodiment will be explained using Figure 1(A). Figure 1(A) is a schematic diagram showing an example of the configuration of the input / output device in this embodiment.

[0019] The input / output device shown in Figure 1(A) consists of a display circuit control unit 101a and a light detection circuit control unit 101b It includes a light source unit 101c and a pixel unit 101d.

[0020] The display circuit control unit 101a includes a display drive circuit (also called DISPDRV) 111 and a display drive It includes a data signal output circuit (also called DDOUT) 112.

[0021] The light detection circuit control unit 101b includes a light detection drive circuit (also called PSDRV) 113 and a readout It includes circuit 116.

[0022] The light source unit 101c includes a light unit (also called LIGHT) 114.

[0023] The pixel section 101d includes multiple display circuits (also called DISPs) 115d and multiple light detection circuits. (Also called PS) 115p and includes. Note that one display circuit 115d is used for one A pixel is formed. Furthermore, one or more light detection circuits 115p may be included in the pixel. Furthermore, multiple display circuits 115d are arranged in the matrix direction in the pixel section 101d. Multiple light detection circuits 115p are arranged in the matrix direction in the pixel section 101d.

[0024] The display drive circuit 111 uses multiple display selection signals (also called signal DSELs), which are pulse signals. It has the function to output [something].

[0025] The display drive circuit 111 includes, for example, a shift register. The display drive circuit 111 includes a shift By outputting a pulse signal from a register, a display selection signal can be output. .

[0026] The display data signal output circuit 112 receives the image signal. 12 is a display data signal (also called signal DD), which is a voltage signal based on the input image signal. It has the function of generating and outputting the generated display data signal.

[0027] The display data signal output circuit 112 includes, for example, a switching transistor.

[0028] In an input / output device, a transistor has two terminals, and the voltage applied to it determines the two terminals. It has a current control terminal that controls the current flowing between the two terminals. In addition, in elements, terminals where the current flowing between them is controlled are also called current terminals. Each of the current terminals is also called the first current terminal and the second current terminal.

[0029] Furthermore, in the input / output device, for example, a field-effect transistor can be used as the transistor. This is possible. In the case of a field-effect transistor, the first current terminals are the source and drain. One of the two current terminals is the other of the source and drain, and the current control terminal is It is a gate.

[0030] In general, voltage refers to the difference in electric potential between two points (also called potential difference). However, voltage and potential values ​​are both expressed in volts (V) in circuit diagrams, etc. Because of this, it is difficult to distinguish between them. Therefore, in this specification, unless otherwise specified, The potential difference between the potential at a given point and a reference potential (also called the reference potential) is defined as the voltage at that point. It may be used in some cases.

[0031] The display data signal output circuit 112 outputs an image signal when the switching transistor is ON. The number data can be output as a display data signal. The switching transistor It can be controlled by inputting a control signal, which is a pulse signal, to the current control terminal. Furthermore, if there are multiple display circuits 115d, multiple switching transistors are used. By selectively turning it on or off, the image signal data can be displayed on multiple display days. It may also be output as a TA signal.

[0032] The light detection drive circuit 113 receives a pulse signal, which is a light detection reset signal (also called signal PRST). ), it has the function of outputting a stored control signal (also called signal TX), which is a pulse signal. If necessary, the photodetection drive circuit 113 outputs a pulse signal which is the output selection signal (signal OSEL and The configuration may also include a function to output (also known as).

[0033] The light detection drive circuit 113 includes, for example, a shift register. 13 outputs a pulse signal from the shift register, thereby providing a light detection reset signal and It outputs a storage control signal, or a light detection reset signal, a storage control signal, and an output selection signal. It is possible.

[0034] The light unit 114 is a light-emitting unit equipped with a light source.

[0035] As a light source, for example, a cold cathode tube or a light-emitting diode can be used. The do has wavelengths in the visible light region (for example, the region where the wavelength of light is between 360 nm and 830 nm). It is a light-emitting diode that emits light. Examples of light-emitting diodes include white light-emitting diodes. LEDs can be used. Note that there may be multiple LEDs of each color. Furthermore, as light-emitting diodes, for example, red light-emitting diodes, green light-emitting diodes, and Blue light-emitting diodes may also be used. Red light-emitting diodes, green light-emitting diodes, and blue light-emitting diodes may also be used. By using color light-emitting diodes, for example, the display selection signal can be followed within a single frame period. This refers to one or more red light-emitting diodes, green light-emitting diodes, and blue light-emitting diodes. A driving method that displays a full-color image by sequentially switching the number of lights to emit light (Phi It can use a (world sequential drive method) and the readable object can be full color. It is possible to read the data.

[0036] Furthermore, for example, a control circuit is provided to control the lighting of a light-emitting diode, and the control is a pulse signal. The illumination of the light-emitting diodes can also be controlled according to the control signals input to the circuit.

[0037] The display circuit 115d is superimposed on the light unit 114. The display circuit 115d has a light Light enters from unit 114. Also, the display circuit 115d receives a pulse signal. A selection signal is input, and a display data signal is input according to the input display selection signal. The display circuit 115d has a function that changes the display state according to the data of the input display data signal. It has.

[0038] The display circuit 115d includes, for example, a display selection transistor and a display element.

[0039] The display selection transistor selects whether or not to input the display data signal to the display element. It has the function of doing so.

[0040] The display element receives data from the display data signal according to the display selection transistor. Furthermore, it has the function of changing the display state according to the data of the display data signal.

[0041] For example, liquid crystal elements can be used as display elements.

[0042] Furthermore, as a display method for input / output devices equipped with liquid crystal elements, TN (Twisted Nem) is used. atic) mode, IPS (In-Plane Switching) mode, STN ( Super Twisted Nematic) mode, VA(Vertical Al ignment) mode, ASM(Axially Symmetric aligne) d Micro-cell) mode, OCB (Optically Compensated) (ed Birefringence) mode, FLC (Ferroelectric L iquix Crystal mode, AFLC (AntiFerroelectric) Liquid Crystal mode, MVA (Multi-Domain Ver.) tical Alignment) mode, PVA(Patterned Vertic) mode Alignment mode, ASV (Advanced Super View) ) mode, or FFS (Fringe Field Switching) mode, etc. You may use it.

[0043] The light detection circuit 115p is superimposed on the light unit 114. For example, when reading the pixel section 101d. If there is an object to be read, the light emitted from the light unit 114 will be reflected by the object to be read. The reflected light is then incident on the light detection circuit 115p. The light detection circuit 115p is equipped with a light detection ring. Set signals and charge storage control signals are input. Additionally, signals for red, green, and blue light are input. A detection circuit 115p can also be provided. For example, red, green, and blue color filters. A light detection circuit for each color is provided via red, green, and blue color filters. 115p generates optical data, and then the multiple generated optical data sets are combined to produce image data. This also allows for the generation of full-color image data.

[0044] The light detection circuit 115p consists of X photoelectric conversion elements (also called PCEs) (where X is a natural number greater than or equal to 2). It comprises at least X charge storage control transistors and amplification transistors.

[0045] Each of the X photoelectric conversion elements has a first current terminal and a second current terminal, and X light Each of the first current terminals of the power conversion element is connected to a unit voltage or X photodetection reset signals. Two different light detection reset signals are input to each other. The photoelectric conversion element is activated when the first light is incident on it. This allows for the flow of an electric current (also called a photocurrent) in accordance with the illuminance of the incident light. Furthermore, when a unit voltage is input to the first current terminal of the photoelectric conversion element, the photoelectric conversion element The value of the unit voltage input to the first current terminal is set as appropriate.

[0046] Each of the first current terminals of the X charge storage control transistors is connected to the X photoelectric conversion elements. Among them, X charge storage devices are electrically connected to the second current terminals of different photoelectric conversion elements. Each of the current control terminals of the control transistor has X charge storage control signals, which are mutually exclusive. Different charge accumulation control signals are input to it.

[0047] A unit voltage is input to one of the first and second current terminals of the amplifying transistor. Optical data is transmitted via the first current terminal and the other of the second current terminal of the amplification transistor. The output signal is a current control terminal of the amplification transistor, and X charge storage control transistors are connected. Each of the second current terminals of the inverter is electrically connected. In other words, X charge storage units One amplification transistor is shared and used by the transistor. The value will be set as appropriate.

[0048] Furthermore, the light detection circuit 115p uses the first current terminal or the second current terminal of the amplification transistor. The optical data is output as an optical data signal via this interface.

[0049] The readout circuit 116 selects the photodetector 115p to read out the optical data, and the selected photodetector It has the function of reading optical data from output circuit 115p.

[0050] The readout circuit 116 is configured using, for example, a selection circuit. For example, the selection circuit is a switch A photodetection circuit 115p is provided with a switching transistor, and the switching transistor is used according to the photodetection circuit 115p Optical data can be read out by inputting an optical data signal.

[0051] Furthermore, an example configuration of the light detection circuit 115p will be explained using Figure 1(B). Figure 1(B) Figure 1(A) is a circuit diagram showing an example of the configuration of the optical detection circuit in the input / output device.

[0052] The photodetection circuit shown in Figure 1(B) includes photoelectric conversion elements 131_1 to 131_Z. Z photoelectric elements (where Z is a natural number greater than or equal to 3), transistor 132, and transistor 1 33 and Z transistors 134_1 through 134_Z It includes 4 and .

[0053] The first current terminal of the photoelectric conversion element 131_K (where K is a natural number from 1 to Z) is connected to a photodetector reset. The signal PRST_K is input.

[0054] Each of the photoelectric conversion elements 131_1 to 131_Z is, for example, a photo Diodes or phototransistors can be used. , one of the anode and cathode of the photodiode is in phase with the first current terminal of the photoelectric conversion element. The other of the anode and cathode of the photodiode is the second current terminal of the photoelectric conversion element. This corresponds to the source and drain of the phototransistor. One end of the circuit corresponds to the first current terminal of the photoelectric conversion element, and the source and the drive of the phototransistor. The other end of the rain corresponds to the second current terminal of the photoelectric conversion element.

[0055] One of the sources and drains of transistor 134_K is the second of photoelectric conversion element 131_K. The current terminal is connected, and the gate of transistor 134_K receives the charge storage control signal TX_ K is input. Note that one of the source and drain of transistor 134_K is connected to the photoelectric conversion. The connection point with element 131_K is also called node N11_K.

[0056] Each of transistors 134_1 through 134_Z is a charge storage control transistor It has a function as a resistor.

[0057] As each of the transistors 134_1 to 134_Z, for example, a transistor including an oxide semiconductor layer in which a channel is formed can be used. The oxide semiconductor layer is a semiconductor layer that is intrinsic (also referred to as type I) or substantially intrinsic, with an extremely small number of carriers, and the carrier concentration is less than 1×10 / cm preferably less than 1×10 / cm more preferably less than 1×10 3 / cm 1 2 and is less than that. 3

[0058]

[0059]

[0060] <000052 , and the off-current of the transistor including the oxide semiconductor layer is 10 aA (1×10 -17 A) or less per 1 μm of channel width, preferably 1 aA (1×10 -18 A) or less, more preferably 10 zA (1×10 -20 A) or less, even more preferably 1 zA (1×10 - 21 A) or less, and even more preferably 100 yA (1×10 -22 A) or less.

[0061]

[0062]

[0063] drain of transistor 132, and the gate of transistor 132 is connected to the sources and

[0064]

[0065]

[0066] <7000564>

[0067]

[0068]

[0069]

[0070] <00 , and the off-current of the transistor including the oxide semiconductor layer is low even when the temperature changes. For example, even when the temperature of the transistor is 150°C, the off-current is 100 zA / μm or less.

[0071] <0>< /

[0072] ]>

[0073]

[0074]

[0075]

[0076]

[0077]

[0078]

[0079]

[0080] <000 , and the gate of transistor 132 is connected to the sources and [[ID=7 , and the gate of transistor 132 is connected to the sources and

[0081]

[0082] <0It is connected to the other end of the drain. Note that the gate of transistor 132 and the transistor The source and the other drain of each of the transistors 134_1 to 134_Z The connection point is also called node N12. The value of voltage V0 is set as appropriate.

[0061] Transistor 132 functions as an amplifying transistor.

[0062] One of the sources and drains of transistor 133 is connected to the source and drain of transistor 132. Connected to the other side of the rain, the signal OSEL is input to the gate of transistor 133. .

[0063] For example, transistors 132 and 133 are formed to form channels. , a semiconductor layer or channel containing a semiconductor (such as silicon) of Group 14 in the periodic table A transistor can be used that includes an oxide semiconductor layer on which a layer is formed. As transistors containing layers, transistors 134_1 to 134_Z A transistor using an applicable oxide semiconductor layer can be used.

[0064] Furthermore, transistors 134_1 to 134_Z and transistor 133 are also included. Using an oxide semiconductor layer in which a channel is formed, the transistor 132 is, for example, a channel A semiconductor is formed containing semiconductors of Group 14 in the periodic table (such as silicon). Body layers can also be used.

[0065] Next, an example of a method for driving the photodetector circuit shown in Figure 1(B) will be explained using Figure 1(C). Figure 1(C) illustrates the timing for an example of a driving method for the photodetector circuit shown in Figure 1(B). This is a chart, and signals PRST_1 to PRST_Z, signals TX_1 to TX_ The states of Z and the signal OSEL are shown. Note that, as an example, a photoelectric converter is used here. Each of the sub-elements 131_1 to 131_Z is a photodiode, and the voltage V This section explains the case where the value of 0 is the same as the reference potential.

[0066] In the example of the light detection circuit driving method shown in Figure 1(B), during period T11, the signal PRST_1 The pulse (also called pls) and the pulse of signal TX_1 are input, and furthermore, during period T12 At this point, the pulses of signal PRST_2 and signal TX_2 are input. Subsequently, During each period, pulses of different signals PRST and TX are input sequentially, and during period T13... Then, pulses of signal PRST_Z and signal TX_Z are input.

[0067] While pulses of signals PRST_K and TX_K are input, the photoelectric conversion element 131_ K enters a state where current flows in the forward direction, and transistor 134_K is turned on. This resets the voltages at nodes N11_K and N12 to a constant value. Therefore, the voltages of nodes N11_1 through N11_Z are reset sequentially, and also The voltage of code N12 is also reset.

[0068] Furthermore, during periods T11 to T13, the pulse width of signal PRST_K is the same as that of signal TX_ It is preferable that the pulse width is longer than that of K, and that the signal TX_K is received when the pulse input has finished. It is preferable that the pulse for PRST_K is still being input.

[0069] Furthermore, during periods T11 to T13, after the pulse of signal PRST_K is input The photoelectric conversion element 131_K will continue to emit the first current until the pulse of signal TX_K is input again. A voltage is applied between the terminal and the second current terminal in the opposite direction to the forward direction. At that time, a current flows through the photoelectric conversion element 131_K in accordance with the illuminance of the incident light, and the photoelectric conversion element The voltage value of node N11_K changes according to the current flowing through child 131_K. During period T13, after the pulse of signal PRST_K is input, the signal TX is input again. The period until a pulse of _K is input is also called the accumulation period.

[0070] Furthermore, during period T14, the pulse of signal TX_1 is input, and during period T15, A pulse of signal OSEL is input. Furthermore, during period T16, a pulse of signal TX_2 is input. A signal is input, and during period T17, a pulse of the signal OSEL is input. After that, a different signal The pulses of the signal PRST are input sequentially, and during the period after the pulses of the signal PRST are input Then, the pulse of signal OSEL is input, and in period T18, the pulse of signal TX_Z The signal OSEL pulse is input during period T19.

[0071] During periods T14 to T19, while the pulse of signal TX_K is input, When ZISTA 134_K is turned on, the voltages at node N11_K and node N12 are It changes. At this time, the voltage at node N11_K and the voltage at node N12 are respectively The value changes according to the added capacitance ratio. When the voltage at node N12 changes, transistor 13 The value of the channel resistance between the source and drain of circuit 2 changes.

[0072] Furthermore, while the signal OSEL pulse is input, transistor 133 remains ON. , the source and drain of transistor 132, and the source and drain of transistor 133 Current flows through the drain. The source and drain of transistor 132, as well as the transistor The current flowing through the source and drain of zista 133 is equal to the voltage at node N12, i.e. This depends on the gate voltage value of transistor 132. Therefore, the so Current flowing through the source and drain of transistor 133, as well as through the source and drain of transistor 133 This value corresponds to the illuminance of the light incident on the photoelectric conversion element 131_K during the storage period. For example, The higher the illuminance of the light incident on the photoelectric conversion element 131_K, the lower the voltage of the optical data. This is also possible. Furthermore, it is not limited to this; the higher the light intensity, the higher the voltage of the optical data. It is also possible. The photodetection circuit shown in Figure 1(B) has the source and drain of transistor 133. The other end outputs optical data as an optical data signal.

[0073] Furthermore, during periods T14 to T19, after the signal OSEL pulse is input, the following Before the pulse of signal TX_M (where M is a natural number from 2 to Z) is input, signals TX_M-1 and If you input the pulse signal PRST_M-1, you can reset node N12 again. In this way, during periods T14 to T19, the pulse of the signal OSEL is input. After that, before the next signal TX_M (where M is a natural number from 2 to Z) pulse is input, signal TX By inputting the pulses of _M-1 and signal PRST_M-1, the reset operation is performed again. Since this process is unnecessary, the reading (also called imaging) cycle can be shortened. This is an example of a driving method for the light detection circuit shown in Figure 1(B).

[0074] Next, as an example of the driving method for the input / output device in this embodiment, the input / output device shown in Figure 1(A) This section describes an example of a drive method for the device.

[0075] In the example of the input / output device drive method shown in Figure 1(A), the display circuit follows the pulse of the display selection signal. A display data signal is input to 115d, and the display circuit 115d displays the input display data signal The display state changes according to the data, and the pixel unit 101d displays the image.

[0076] Furthermore, in the example of the input / output device drive method shown in Figure 1(A), the photodetector explained using Figure 1(C) is used. The output circuit is driven according to the illuminance of the light incident on each of the multiple light detection circuits 115p using the output circuit driving method. It generates multiple optical data points and outputs them sequentially as optical data signals.

[0077] Furthermore, the readout circuit 116 reads the optical data output from multiple photodetector circuits 115p. The data is read sequentially. The read optical data is used, for example, for coordinate detection of the object being read or for image data. It is used for specific processes such as generation.

[0078] Furthermore, an image signal is generated from the optical data generated above, and this image signal is used to create a display data signal. This may also be used to generate a display image that changes according to the light data.

[0079] As explained using Figure 1, an example of the input / output device in this embodiment is a light detection circuit. In this configuration, one amplification transistor and one output selection transistor control multiple charge storage devices. This configuration is shared by a transistor and multiple photoelectric conversion elements. This allows for a reduction in the number of transistors in the pixel area. By reducing the number of transistors, the size of a single pixel can be reduced or the number of photoelectric transistors can be reduced. The size of the child can be increased. For example, the larger the size of the photoelectric conversion element, the larger the input The sensitivity to incoming light improves.

[0080] Furthermore, an example of the input / output device in this embodiment is at least a charge storage control transistor. As such, a transistor with low off-current and containing an oxide semiconductor layer in which a channel is formed is used. This is the configuration to be used. By using the above configuration, the leakage current of the charge storage control transistor Because fluctuations in optical data caused by this can be suppressed, the signal-to-noise ratio can be improved. Furthermore, conventionally, multiple charge storage control transistors are used at the gate of a single amplification transistor. When the other end of the drain and the other end are connected, the leakage current of the charge storage control transistor The voltage fluctuation at the gate of the amplification transistor was large. However, with the above configuration... This suppresses fluctuations in optical data caused by leakage current in the charge storage control transistor. Therefore, multiple charge storage control transistors can be connected to the gate of a single amplification transistor. Even in a configuration where the source and drain are connected, the gate voltage of the amplification transistor This allows for the suppression of fluctuations. Therefore, one amplification transistor can control multiple charge storage devices. In a configuration where transistors and photoelectric conversion elements are used in common, charge storage control transistor As an inverter, it has low off-current and includes a transistor containing an oxide semiconductor layer in which a channel is formed. It is preferable to use a ZISTA.

[0081] (Embodiment 2) This embodiment describes another example of the photodetection circuit in the input / output device of the above embodiment. To clarify, in the example of the light detection circuit in this embodiment, the input and output of the above embodiment For the same part as the light detection circuit in the device, the light in the input / output device of the above embodiment Refer to the explanation of the detection circuit as appropriate.

[0082] An example of the light detection circuit in this embodiment will be explained with reference to Figure 2. This is a diagram illustrating a photodetector circuit in a given configuration.

[0083] First, an example of the configuration of the photodetector circuit in this embodiment will be explained using Figure 2(A). Figure 2(A) is a circuit diagram showing an example of the configuration of the light detection circuit in this embodiment.

[0084] The photodetection circuit shown in Figure 2(A) has the same photoelectric conversion element 13 as the photodetection circuit shown in Figure 1(B). Z photoelectric conversion elements, 1_1 to 131_Z, and a transistor 132. Transistor 133 and Z transistors 134_1 through 134_Z It includes a transistor. Furthermore, the light detection circuit shown in Figure 2(A) includes transistor 135. Prepare.

[0085] In the photodetection circuit shown in Figure 2(A), the first current terminal of the photoelectric conversion element 131_K is connected to: A voltage Vb is input.

[0086] One of the sources and drains of transistor 134_K is the second of photoelectric conversion element 131_K. The current terminal is connected, and the gate of transistor 134_K receives the charge storage control signal TX_ The input is K.

[0087] A voltage V0 is input to either the source or drain of transistor 132, and the transistor The gate of transistor 132 is connected to the sources of transistors 134_1 through 134_Z. It is connected to each of the other ends of the drain.

[0088] One of the sources and drains of transistor 133 is connected to the source and drain of transistor 132. Connected to the other side of the rain, the signal OSEL is input to the gate of transistor 133. .

[0089] A voltage Va is input to either the source or drain of transistor 135, and the transistor The source and drain of transistor 135 are connected to the gate of transistor 132. The gate of the inverter 135 receives the light detection reset signal PRST.

[0090] Transistor 135 resets the voltage at the gate (node ​​N12) of transistor 132. It functions as a light-detection reset transistor.

[0091] Note that one of the voltages Va and Vb is the high power supply voltage Vdd, and the voltages Va and Vb The other is the low power supply voltage Vss. The values ​​of voltages Va and Vb are, for example, those of a transistor. Depending on their polarity, they may be swapped.

[0092] Next, an example of a method for driving the photodetector circuit shown in Figure 2(A) will be explained using Figure 2(B). Figure 2(B) illustrates the timing for an example of a driving method for the photodetector circuit shown in Figure 2(A). This is a chart showing signals PRST, TX_1 through TX_Z, and OSEL. Each state is shown. Here, as an example, the photoelectric conversion element 131_1 to the photoelectric conversion Each element 131_Z is a photodiode, and the voltage Va is the high power supply voltage. This section explains the case where voltage Vb is a low power supply voltage and voltage V0 is the same value as the reference potential. ru.

[0093] In the example of the light detection circuit driving method shown in Figure 2(A), during period T21, the signal TX_1 A signal is input, and then, during period T22, a pulse of signal TX_2 is input. After that, different signal pulses TX are input sequentially for each period, and in period T23, signal T A pulse of X_Z is input. Also, one pulse of signal PRST is in period T21 to period It is entered via T23.

[0094] Transistor 135 is turned on while pulses of signals PRST and TX_K are input. In this state, the photoelectric conversion element 131_K enters a state where current flows in the forward direction, and the transistor ZISTA134_K is turned on. This causes nodes N11_K and N12 to The voltage is reset to a constant value. Therefore, the voltage of nodes N11_1 through N11_Z The voltage is reset sequentially.

[0095] Furthermore, during periods T21 to T23, after the pulse of signal TX_K is input, Until a pulse of the degree signal TX_K is input, the photoelectric conversion element 131_K will turn on the first current terminal A voltage is applied between the first and second current terminals in the opposite direction to the forward direction. In the photoelectric conversion element 131_K, a current flows according to the illuminance of the incident light, and the photoelectric conversion element 1 The voltage value at node N11_K changes according to the current flowing through 31_K. Note that during period T21 During period T23, after the pulse of signal TX_K is input, the pulse of signal TX_K is input again. The period until a "rus" is entered is also called the accumulation period.

[0096] Furthermore, during period T24, a pulse of signal PRST is input, and during period T25, A pulse of signal TX_1 is input, and during period T26, a pulse of signal OSEL is input. Furthermore, during period T27, the pulse of signal PRST is input, and during period T28... Then, the pulse of signal TX_2 is input, and during period T29, the pulse of signal OSEL The signal PRST pulse is input. Subsequently, multiple pulses of the signal PRST are input, and the pulses of the signal PRST Each time an input is received, a pulse of a different signal TX is input during the following period, and the signal TX During the period following the input of the pulse, the signal OSEL pulse is input, and in period T30 In this case, a pulse of signal PRST is input, and in period T31, a pulse of signal TX_Z is During the period T32, the signal OSEL pulse is input.

[0097] During periods T24 through T32, while the pulse of signal PRST is input, node The voltage of N12 is reset.

[0098] Furthermore, during periods T24 to T32, while the pulse of signal TX_K is input, Transistor 134_K turns on, and the voltage at node N11_K and node N12 The voltage changes. At this time, the voltage at node N11_K and the voltage at node N12 are It changes to a value corresponding to the capacitance ratio added to it. When the voltage at node N12 changes, the transistor The channel resistance value between the source and drain of TA132 changes.

[0099] Furthermore, during periods T24 to T32, while the signal OSEL pulse is input, Transistor 133 turns on, and the source and drain of transistor 132, and Current flows through the source and drain of transistor 133. Transistor 132 The source and drain of the transistor 133, and the flow through the source and drain of transistor 133 The current depends on the voltage at node N12, i.e., the gate voltage of transistor 132. Therefore, the source and drain of transistor 132, and the source of transistor 133 The current flowing through the drain is incident on the photoelectric conversion element 131_K during the storage period. The value will depend on the illuminance of the light. For example, if the illuminance of the light incident on the photoelectric conversion element 131_K is high... This also allows for lowering the voltage of the optical data. Furthermore, this is not limited to photoelectric conversion elements. The higher the illuminance of the incident light at 131K, the higher the voltage of the optical data can be. (Figure) The photodetector circuit shown in 2(A) uses light from the source and drain of transistor 133. The data is output as an optical data signal.

[0100] Furthermore, during periods T24 to T32, after the signal OSEL pulse is input, the following Before the pulse of signal TX_M (where M is a natural number from 2 to Z) is input, signals TX_M-1 and If you input the pulse signal PRST_M-1, you can reset node N12 again. In this way, during periods T24 to T32, the pulse of the signal OSEL is input. After that, before the next signal TX_M (where M is a natural number from 2 to Z) pulse is input, signal TX By inputting the pulses of _M-1 and signal PRST_M-1, the reset operation is performed again. Since this process is unnecessary, the reading (also called imaging) cycle can be shortened. This is an example of a driving method for the light detection circuit shown in Figure 2(A).

[0101] As explained using Figure 2, an example of the photodetection circuit in this embodiment is one amplifier A transistor and one output selection transistor, multiple charge storage control transistors and multiple This configuration is shared by the photoelectric conversion element. The number of transistors in the pixel area can be reduced. By reducing the number of pixels, the size of a single pixel can be reduced or the size of the photoelectric conversion element can be increased. This can be achieved. For example, the larger the size of the photoelectric conversion element, the better the sensitivity to incident light. do.

[0102] Furthermore, an example of the photodetection circuit in this embodiment uses the gate voltage of an amplifying transistor. The configuration includes a photodetector reset transistor that allows the user to select whether or not to reset the device. This configuration improves the accuracy of optical data corresponding to the illuminance of light incident on the light detection circuit. It can be done.

[0103] (Embodiment 3) Another example of the photodetection circuit in the input / output device of the above embodiment will be described. In an example of a photodetection circuit in the form of application, the photodetection in the input / output device of the above embodiment For parts that are the same as the circuit, the explanation of the light detection circuit in the input / output device of the above embodiment is appropriate. I will use it.

[0104] An example of the light detection circuit in this embodiment will be explained with reference to Figure 3. This is a diagram illustrating a photodetector circuit in a given configuration.

[0105] First, an example of the configuration of the photodetection circuit in this embodiment will be explained using Figure 3(A). Figure 3(A) is a circuit diagram showing an example of the configuration of the light detection circuit in this embodiment.

[0106] The photodetection circuit shown in Figure 3(A) has a photoelectric conversion element 13, similar to the photodetection circuit shown in Figure 2(A). Z photoelectric conversion elements, 1_1 to 131_Z, and a transistor 132. Z transistors, ranging from transistor 134_1 to transistor 134_Z, and It is equipped with a 135. In addition, the light detection circuit shown in Figure 3(A) and the light detection circuit shown in Figure 2(A) In comparison, the light detection circuit shown in Figure 3(A) does not have transistor 133. .

[0107] In the photodetection circuit shown in Figure 3(A), the first current terminal of the photoelectric conversion element 131_K is connected to: A voltage Vb is input.

[0108] One of the sources and drains of transistor 134_K is the second of photoelectric conversion element 131_K. The current terminal is connected, and the gate of transistor 134_K receives the charge storage control signal TX_ The input is K.

[0109] A voltage V0 is input to either the source or drain of transistor 132, and the transistor The gate of transistor 132 is connected to the sources of transistors 134_1 through 134_Z. It is connected to each of the other ends of the drain.

[0110] One of the sources and drains of transistor 135 is connected to a reset voltage signal (signal VRS and (Also known as) is input, and the source and drain of transistor 135 are connected to the transistor The gate of transistor 132 is connected to the photodetection reset signal PR. ST is entered.

[0111] Next, an example of a method for driving the light detection circuit shown in Figure 3(A) will be explained using Figure 3(B). Figure 3(B) illustrates the timing for an example of a driving method for the photodetector circuit shown in Figure 3(A). This is a chart showing signals PRST, TX_1 through TX_Z, and OSEL. Each state is shown. Here, as an example, the photoelectric conversion element 131_1 to the photoelectric conversion Each element 131_Z is a photodiode, and the voltage Va is the high power supply voltage. This section explains the case where voltage Vb is a low power supply voltage and voltage V0 is the same as the reference potential.

[0112] In the example of the light detection circuit driving method shown in Figure 3(A), during period T41, the signal PRST A signal is input. Also, one pulse of the signal VRS spans from period T41 to period T45. It is entered as follows.

[0113] While pulses of signals PRST and VRS are input, transistor 135 is ON. In this state, the voltage at node N12 is reset to a constant value.

[0114] Furthermore, during period T42, the pulse of signal TX_1 is input, and during period T42, the signal While the pulse of signal PRST is being input, the pulse of signal PRST is input. Furthermore, During period T43, a pulse of signal TX_2 is input, and during period T43, signal TX_2 While the pulse of signal PRST is input, a pulse of signal PRST is input. Then a different signal TX pulses are input sequentially, and while the TX pulse is being input, the PRST pulse A pulse is input, and during period T44, a pulse of signal TX_Z is input, and during period T44 While the pulse signal TX_Z is being input, the pulse signal PRST is input.

[0115] During period T42 to period T44, before the pulse of signal PRST_K is input, while the pulse of signal T X_K is being input, transistor 134_K turns on, and the voltages of node N11_K and node N12 change. At this time, the voltages of node N11_K and node N12 change according to the capacitance ratio added to each. When the voltage of node N1 2 changes, the value of the channel resistance between the source and drain of transistor 132 changes.

[0116] Furthermore, current flows through the source and drain of transistor 132. The current flowing through the source and drain of transistor 132 depends on the voltage of node N12, that is, the value of the voltage of the gate of transistor 132.

[0117] Also, during period T42 to period T44, while the pulses of signal TX_K and signal VRS are being input, the voltage of node N12 is reset and becomes equal to the value of voltage Va.

[0118] Furthermore, after the pulse of signal PRST_K is input during period T42 to period T44, until the pulse of signal TX_K is input again (for example, until the pulse of signal T X_K is input in the next read period), the photoelectric conversion element 131_K is in a state where a voltage is applied in the reverse direction to the forward direction between the first current terminal and the second current terminal. At this time, a current flows through the photoelectric conversion element 131_K according to the illuminance of the incident light, and the value of node N11_K changes according to the current flowing through the photoelectric conversion element 131_ K. Note that after the pulse of signal PRST_K is input during period T42 to period T 44, until the pulse of signal TX_K is input again, 44, while the pulse of signal PRST_K is input, until the pulse of signal TX_K is input again ​​​​The period before data is entered is also called the accumulation period.

[0119] Furthermore, the current flowing through the source and drain of transistor 132 is photoelectric during the storage period. The value corresponds to the illuminance of the light incident on the conversion element 131_K. For example, photoelectric conversion element 131 The higher the illuminance of the incident light at _K, the lower the voltage of the optical data can be. Figure 3(A The photodetector circuit shown in the diagram receives optical data from the source and drain of transistor 132. It outputs an optical data signal.

[0120] Furthermore, during period T45, after the pulse of signal VRS is input, the pulse of signal PRST is input. The character "ス" is entered.

[0121] During period T45, while the pulse of signal PRST is input, transistor 135 It turns ON. At this time, the voltage at node N12 is reset, and the voltage at node N12 is The voltage becomes equal to that of the signal VRS, and transistor 132 turns off. This is shown in Figure 3. (A) is an example of a method for driving the light detection circuit shown.

[0122] As explained using Figure 3, an example of the photodetection circuit in this embodiment is one amplifier The transistor is shared by multiple charge storage control transistors and multiple photoelectric conversion elements. This configuration reduces the number of transistors in the pixel section. This is possible. By reducing the number of transistors in the pixel area, one image can be processed. The size of the basic elements can be reduced or the size of the photoelectric conversion elements can be increased. For example, photoelectric conversion The larger the size of the element, the better its sensitivity to incident light.

[0123] Furthermore, an example of the photodetection circuit in the present embodiment is configured to include a photodetection reset transistor that selects whether to reset the voltage of the gate of the amplification transistor. By adopting the above configuration, the accuracy of the optical data corresponding to the illuminance of the light incident on the photodetection circuit can be improved. As described with reference to FIG. 3, an example of the photodetection circuit in the present embodiment includes a photoelectric conversion element, a charge storage control transistor, an amplification transistor, and a photodetection reset transistor that selects whether to reset the voltage of the gate of the amplification transistor. By adopting the above configuration, while improving the generation accuracy of the optical data corresponding to the illuminance of the light incident on the photodetection circuit, the number of transistors can be reduced because there is no output selection transistor.

[0124] As described with reference to FIG. 3, an example of the photodetection circuit in the present embodiment includes a photoelectric conversion element, a charge storage control transistor, an amplification transistor, and a photodetection reset transistor that selects whether to reset the voltage of the gate of the amplification transistor. By adopting the above configuration, while improving the generation accuracy of the optical data corresponding to the illuminance of the light incident on the photodetection circuit, the number of transistors can be reduced because there is no output selection transistor. As described with reference to FIG. 3, an example of the photodetection circuit in the present embodiment includes a photoelectric conversion element, a charge storage control transistor, an amplification transistor, and a photodetection reset transistor that selects whether to reset the voltage of the gate of the amplification transistor. By adopting the above configuration, while improving the generation accuracy of the optical data corresponding to the illuminance of the light incident on the photodetection circuit, the number of transistors can be reduced because there is no output selection transistor. As described with reference to FIG. 3, an example of the photodetection circuit in the present embodiment includes a photoelectric conversion element, a charge storage control transistor, an amplification transistor, and a photodetection reset transistor that selects whether to reset the voltage of the gate of the amplification transistor. By adopting the above configuration, while improving the generation accuracy of the optical data corresponding to the illuminance of the light incident on the photodetection circuit, the number of transistors can be reduced because there is no output selection transistor.

[0125] (Embodiment 4) In the present embodiment, an example of the display circuit in the input / output device of the above embodiment will be described.

[0126] An example of the display circuit in the present embodiment will be described with reference to FIG. 4. FIG. 4 is a diagram for explaining an example of the display circuit in the present embodiment.

[0127] First, a configuration example of the display circuit in the present embodiment will be described with reference to FIGS. 4(A) and 4(B). FIGS. 4(A) and 4(B) are diagrams showing a configuration example of the display circuit in the present embodiment. FIGS. 4(A) and 4(B) are diagrams showing a configuration example of the display circuit in the present embodiment.

[0128] The display circuit shown in FIG. 4(A) includes a transistor 161a, a liquid crystal element 162a, and a capacitive element 163a.

[0129] In the display circuit shown in Figure 4(A), transistor 161a is a field-effect transistor. He is a star.

[0130] Furthermore, in the input / output device, the liquid crystal element comprises a first display electrode, a second display electrode, and a liquid crystal layer. It is composed of the following. The liquid crystal layer is the voltage applied between the first display electrode and the second display electrode. The light transmittance changes accordingly.

[0131] Furthermore, in the input / output device, the capacitive element comprises a first capacitive electrode, a second capacitive electrode, and a first The capacitive element includes a first capacitive electrode and a dielectric layer superimposed on the second capacitive electrode. Charge is accumulated in accordance with the voltage applied between the first and second capacitive electrodes.

[0132] The signal DD is input to either the source or drain of transistor 161a, and the transistor The signal DSEL is input to the gate of sta161a.

[0133] The first display electrode of the liquid crystal element 162a is connected to the source and drain of the transistor 161a, as well as The two are electrically connected, and a voltage Vc is input to the second display electrode of the liquid crystal element 162a. The voltage Vc value can be set as appropriate.

[0134] The first capacitive electrode of the capacitive element 163a is connected to the source and drain of the transistor 161a, as well as The two capacitive elements are electrically connected, and a voltage Vc is input to the second capacitive electrode of the capacitive element 163a. .

[0135] The display circuit shown in Figure 4(B) consists of a transistor 161b, a liquid crystal element 162b, and a capacitive element. It comprises 163b, a capacitive element 164, a transistor 165, and a transistor 166. ru.

[0136] In the display circuit shown in Figure 4(B), transistor 161b and transistor 165 , and transistor 166 are field-effect transistors.

[0137] The signal DD is input to either the source or drain of transistor 165, and the transistor The gate of the Ta165 has a pulse signal called the write selection signal (also called the WSEL signal) It will be entered.

[0138] The first capacitive electrode of the capacitive element 164 is connected to the source and the other drain of the transistor 165. Electrically connected, a voltage Vc is input to the second capacitive electrode of the capacitive element 164.

[0139] One of the sources and drains of transistor 161b is connected to the source and drain of transistor 165. The other side of the drain is electrically connected, and the gate of transistor 161b has a signal DSEL. The following is entered.

[0140] The first display electrode of the liquid crystal element 162b is connected to the source and drain of the transistor 161b, as well as The two are electrically connected, and a voltage Vc is input to the second display electrode of the liquid crystal element 162b. .

[0141] The first capacitive electrode of the capacitive element 163b is connected to the source and drain of the transistor 161b, as well as The two capacitive elements are electrically connected, and a voltage Vc is input to the second capacitive electrode of the capacitive element 163b. The voltage Vc value is set appropriately according to the specifications of the display circuit.

[0142] A reference voltage is input to either the source or drain of transistor 166. The source and drain of transistor 166, the other of which is the source and drain of transistor 161b. The other side of the input is electrically connected, and the gate of transistor 166 is the output, which is a pulse signal. A reset signal (also known as signal DRST) is input.

[0143] Furthermore, the individual components of the display circuit shown in Figures 4(A) and 4(B) will be explained.

[0144] Transistors 161a and 161b function as display selection transistors. It has.

[0145] The liquid crystal layer in liquid crystal elements 162a and 162b includes the first display electrode and A light-transmitting liquid crystal layer can be used when the voltage applied to the two display electrodes is 0V. For example, electrically controlled birefringent liquid crystals (also called ECB liquid crystals), and liquid crystals with added dichroic dyes (G Using a liquid crystal layer containing a polymer-dispersed liquid crystal (also called H liquid crystal), or a discotic liquid crystal, etc. This is possible. Furthermore, a liquid crystal layer exhibiting a blue phase may be used as the liquid crystal layer. The liquid crystal layer exhibiting a phase is composed of a liquid crystal composition containing, for example, a liquid crystal exhibiting a blue phase and a chiral agent. It is achieved. The liquid crystal exhibiting the blue phase has a short response time of less than 1 msec and is optically isotropic. Therefore, alignment processing is unnecessary, and the viewing angle dependence is small. Thus, the liquid crystal exhibiting the blue phase By using it, the operating speed can be improved.

[0146] Capacitive elements 163a and 163b are connected to transistor 161a or transistor 16 According to 1b, a voltage corresponding to the signal DD is applied between the first and second capacitive electrodes. It has the function of a retaining capacitance. Capacitive elements 163a and 163b are not necessarily Although it is not necessary to provide them, by providing capacitive elements 163a and 163b, the table Suppresses voltage fluctuations applied to liquid crystal elements caused by leakage current of the selective transistor. It is possible.

[0147] The capacitive element 164 is connected between the first and second capacitive electrodes according to the transistor 165. It functions as a holding capacitor to which a voltage corresponding to the signal DD is applied.

[0148] Transistor 165 is a programmer that selects whether or not to input the signal DD to the capacitive element 164. It functions as a selective transistor.

[0149] Transistor 166 selects whether or not to reset the voltage applied to the liquid crystal element 162b. It functions as a selectable display reset selector transistor.

[0150] Note that transistors 161a, 161b, 165, and For example, a channel is formed in ZISTA 166, which is a semiconductor of Group 14 in the periodic table. A transistor is used that includes a semiconductor layer containing a material (such as silicon) or an oxide semiconductor layer. It is possible.

[0151] Next, we will describe an example of a driving method for the display circuit shown in Figures 4(A) and 4(B).

[0152] First, an example of a driving method for the display circuit shown in Figure 4(A) will be explained using Figure 4(C). Figure 4(C) illustrates a timing channel for explaining an example of a driving method for the display circuit shown in Figure 4(A). This shows the state of signals DD and DSEL, respectively.

[0153] In the example of the display circuit driving method shown in Figure 4(A), when the signal DSEL pulse is input, The transistor 161a is turned on.

[0154] When transistor 161a is turned on, the signal DD is input to the display circuit, and the liquid crystal element 1 The voltage across the first indicator electrode of 62a and the first capacitive electrode of the capacitive element 163a is the voltage of signal DD. It will be equivalent to the following value.

[0155] At this time, the liquid crystal element 162a enters a write state (also called state wt) and receives the signal DD. The light transmittance will be adjusted accordingly. As a result, the display circuit will process the data of signal DD (data D1 to The display state will change according to each of the data DQ (where Q is a natural number greater than or equal to 2).

[0156] Subsequently, transistor 161a turns off, and liquid crystal element 162a remains in a held state (state). (Also called hld), the voltage applied between the first and second indicator electrodes is, Next, until the DSEL signal pulse is input, the amount of variation from the initial value will be greater than the reference value. Hold it in a way that prevents it from moving. Also, when the liquid crystal element 162a is in the held state, the input of the above embodiment The light unit in the output device will be illuminated.

[0157] Next, an example of a driving method for the display circuit shown in Figure 4(B) will be explained using Figure 4(D). Figure 4(D) illustrates a timing channel for explaining an example of a driving method for the display circuit shown in Figure 4(B). It is.

[0158] In the example of the display circuit driving method shown in Figure 4(B), when the signal DRST pulse is input, The transistor 166 turns on, and the first display electrode of the liquid crystal element 162b and the capacitive element 1 The voltage across the first capacitive electrode of 63b is reset to the reference voltage.

[0159] Furthermore, when the signal WSEL pulse is input, transistor 165 turns ON, signal When signal DD is input to the display circuit, the first capacitive electrode of the capacitive element 164 becomes equal to the voltage of signal DD. The value will be [value].

[0160] Subsequently, when the signal DSEL pulse is input, transistor 161b turns ON. The voltages of the first display electrode of the liquid crystal element 162b and the first capacitive electrode of the capacitive element 163b are The voltage becomes equivalent to that of the first capacitive electrode of the quantitative element 164.

[0161] At this time, the liquid crystal element 162b enters a writing state, and the light transmittance corresponds to the signal DD. Therefore, the display circuit will receive the data of signal DD (each of data D1 to data DQ). The display state will change according to the corresponding state.

[0162] Subsequently, transistor 161b turns off, and liquid crystal element 162b enters a held state. The voltage applied between the first and second indicator electrodes is then pulsed by the signal DSEL. Until a value is entered, the system will maintain the change from the initial value so that it does not exceed the baseline value. Furthermore, when the liquid crystal element 162b is in the holding state, the light in the input / output device of the above embodiment The unit will light up.

[0163] As explained using Figures 4(A) and 4(B), one of the display circuits in this embodiment The example is a configuration that includes a display selection transistor and a liquid crystal element. By using the above configuration, This allows the display circuit to be set to a display state corresponding to the display data signal.

[0164] Furthermore, as explained using Figure 4(B), an example of the display circuit in this embodiment is shown in the table. In addition to the display selection transistor and liquid crystal element, it also includes a write selection transistor and a capacitive element. This configuration allows the liquid crystal elements to respond to the data of a certain display data signal. While the display is set to the desired state, the data for the next display data signal is written to the capacitive element. This allows for an improvement in the operating speed of the display circuit.

[0165] (Embodiment 5) In this embodiment, the transistor in the input / output device described using the above embodiment is The applicable transistors will be described.

[0166] In the input / output device described using the above embodiment, the transistor is, for example, a transistor. A channel is formed, containing semiconductors of Group 14 in the periodic table (such as silicon). A transistor including a conductive layer or an oxide semiconductor layer can be used. The layer that forms is also called the channel-forming layer.

[0167] The above semiconductor layer may be a single-crystal semiconductor layer, a polycrystalline semiconductor layer, a microcrystalline semiconductor layer, or an amorphous semiconductor layer. A semiconductor layer would also be acceptable.

[0168] Furthermore, in the input / output device described using the above embodiment, the transistor is applied As a transistor containing a possible oxide semiconductor layer, for example, by increasing its purity, A transistor having an oxide semiconductor layer that is made intrinsically (also called type I) or substantially intrinsic It can be used.

[0169] An example of a transistor structure including the above oxide semiconductor layer will be explained using Figure 5. Figure 5 This is a schematic cross-sectional diagram showing an example of the transistor structure in this embodiment.

[0170] The transistor shown in Figure 5(A) is a bottom-gate transistor, and is an inverse transistor. Also known as a hoop-type transistor.

[0171] The transistor shown in Figure 5(A) consists of a conductive layer 401a, an insulating layer 402a, and an oxide semiconductor. It includes layer 403a, conductive layer 405a, and conductive layer 406a.

[0172] The conductive layer 401a is provided on the substrate 400a.

[0173] The insulating layer 402a is provided on top of the conductive layer 401a.

[0174] The oxide semiconductor layer 403a is superimposed on the conductive layer 401a via the insulating layer 402a.

[0175] Each of the conductive layers 405a and 406a is located on a portion of the oxide semiconductor layer 403a. It will be established.

[0176] Furthermore, in Figure 5(A), a portion of the upper surface of the oxide semiconductor layer 403a of the transistor (upper In the portion of the surface where conductive layers 405a and 406a are not provided, the insulating layer 407a To come into contact with.

[0177] Furthermore, the insulating layer 407a is composed of conductive layer 405a, conductive layer 406a, and oxide semiconductor layer 403 It is in contact with the insulating layer 402a in areas where a is not provided.

[0178] The transistor shown in Figure 5(B) includes a conductive layer 408a in addition to the structure shown in Figure 5(A). .

[0179] The conductive layer 408a is superimposed on the oxide semiconductor layer 403a via the insulating layer 407a.

[0180] The transistor shown in Figure 5(C) is a bottom-gate transistor.

[0181] The transistor shown in Figure 5(C) consists of a conductive layer 401b, an insulating layer 402b, and an oxide semiconductor. It includes layer 403b, conductive layer 405b, and conductive layer 406b.

[0182] The conductive layer 401b is provided on the substrate 400b.

[0183] The insulating layer 402b is provided on top of the conductive layer 401b.

[0184] The conductive layer 405b and the conductive layer 406b are provided on a portion of the insulating layer 402b.

[0185] The oxide semiconductor layer 403b is superimposed on the conductive layer 401b via the insulating layer 402b.

[0186] Furthermore, in Figure 5(C), the upper surface of the oxide semiconductor layer 403b in the transistor and The sides are in contact with the insulating layer 407b.

[0187] Furthermore, the insulating layer 407b is composed of conductive layer 405b, conductive layer 406b, and oxide semiconductor layer 403 In areas where b is not provided, it is in contact with the insulating layer 402b.

[0188] In addition, in Figures 5(A) and 5(C), a protective insulating layer may be provided on top of the insulating layer.

[0189] The transistor shown in Figure 5(D) includes the conductive layer 408b in addition to the structure shown in Figure 5(C). .

[0190] The conductive layer 408b is superimposed on the oxide semiconductor layer 403b via the insulating layer 407b.

[0191] The transistor shown in Figure 5(E) is one of the top-gate transistors.

[0192] The transistor shown in Figure 5(E) consists of a conductive layer 401c, an insulating layer 402c, and an oxide semiconductor. It includes layer 403c, conductive layer 405c, and conductive layer 406c.

[0193] The oxide semiconductor layer 403c is provided on the substrate 400c via an insulating layer 447.

[0194] The conductive layer 405c and the conductive layer 406c are provided on the oxide semiconductor layer 403c, respectively. ru.

[0195] The insulating layer 402c is located on top of the oxide semiconductor layer 403c, the conductive layer 405c, and the conductive layer 406c. It will be established in [location].

[0196] The conductive layer 401c is superimposed on the oxide semiconductor layer 403c via the insulating layer 402c.

[0197] Furthermore, we will explain each component shown in Figures 5(A) to 5(E).

[0198] For example, a translucent substrate can be used as the substrate 400a to substrate 400c. For example, a glass substrate or a plastic substrate can be used as a light-transmitting substrate. can.

[0199] Each of the conductive layers 401a to 401c functions as a gate of a transistor. It has. Furthermore, a conductive layer that functions as the gate of a transistor is called the gate or gate. Also called T-wiring.

[0200] Examples of conductive layers 401a to 401c include molybdenum, titanium, chromium, and tan. Metal materials such as tul, tungsten, aluminum, copper, neodymium, or scandium A layer of material, or an alloy material mainly composed of these, can be used. Also, a conductive layer 401 By laminating layers of a material applicable to the formation of conductive layers 401a to conductive layers 401c, It is also possible to construct a 401c electrode layer.

[0201] Each of the insulating layers 402a to 402c serves as a gate insulating layer for the transistor. It has a function.

[0202] Examples of insulating layers 402a to 402c include silicon oxide layer, silicon nitride layer, Silicon oxide nitride layer, silicon oxide nitride layer, aluminum oxide layer, aluminum nitride layer, Using an aluminum oxide nitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer. This can be achieved by laminating layers of materials applicable to insulating layers 402a to 402c. Insulating layers 402a to 402c can also be formed.

[0203] Furthermore, the insulating layers 402a to 402c may be, for example, those from Group 13 of the periodic table. An insulating layer made of a material containing elements and oxygen can also be used. Oxide semiconductor layer 403a When the oxide semiconductor layer 403c contains a group 13 element, the oxide semiconductor layer 403a to acid By using an insulating layer containing a group 13 element as the insulating layer in contact with the ionized semiconductor layer 403c, This allows for a good condition of the interface between the insulating layer and the oxide semiconductor layer.

[0204] Examples of materials containing Group 13 elements include gallium oxide, aluminum oxide, and aluminum oxide. Examples include gallium nium and aluminum gallium oxide. Note that aluminum oxide is also included. Gallium is defined as a substance in which the aluminum content (atomic percentage) is greater than the gallium content (atomic percentage). It refers to a substance, and gallium aluminum oxide is a substance in which the gallium content (atomic %) is high. This refers to substances that contain more than (atomic %) of nium.

[0205] For example, an insulating layer containing gallium oxide can be used as insulating layer 402a to insulating layer 402c. As a result, insulating layer 402a to insulating layer 402c and oxide semiconductor layer 403a to oxide This can reduce the accumulation of hydrogen or hydrogen ions at the interface with the semiconductor layer 403c.

[0206] Furthermore, for example, the insulating layer 402a to insulating layer 402c may contain aluminum oxide. By using layers, insulating layers 402a to 402c and oxide semiconductor layer 403a To reduce the accumulation of hydrogen or hydrogen ions at the interface with the oxide semiconductor layer 403c. This is possible. Also, because the insulating layer containing aluminum oxide is resistant to water, By using an insulating layer containing um, the intrusion of water into the oxide semiconductor layer through the insulating layer is prevented. It can be suppressed.

[0207] Furthermore, the insulating layers 402a to 402c may be, for example, Al2O x (x=3+α, α (where is a value greater than 0 and less than 1), Ga2O x (x=3+α, α is greater than 0 and less than 1) (Value), or Ga x Al 2-x O 3+α (x is a value greater than 0 and less than 2, α is 0) Materials expressed as a value greater than or equal to 1 can also be used. Furthermore, insulating layer 402 By laminating layers of material applicable to a to insulating layer 402c, insulating layer 402a to insulating layer 40 It is also possible to construct 2c. For example, multiple Ga2O x Contains gallium oxide as indicated by Insulating layers 402a to 402c may be formed by laminating layers. x An insulating layer containing gallium oxide and Al2O x Aluminum oxide, as indicated by Insulating layers 402a to 402c may be formed by laminating insulating layers containing the above.

[0208] The insulating layer 447 functions as a base layer that prevents the diffusion of impurity elements from the substrate 400c. It has. Furthermore, the insulating layer 447 is provided in the transistor having the structure shown in Figures 5(A) to 5(D). You can leave it.

[0209] The insulating layer 447 is, for example, a layer of material applicable to insulating layers 402a to 402c. It can be used. Also, layers of material applicable to insulating layers 402a to insulating layers 402c The insulating layer 447 may be formed by lamination.

[0210] Each of the oxide semiconductor layers 403a to 403c is a transistor It functions as a layer on which the NEL is formed. Furthermore, the transistor channel is formed within it. A layer that functions as a layer is also called a channel-forming layer. Oxide semiconductor layer 403a to oxide Applicable oxide semiconductors to the crystalline semiconductor layer 403c include at least indium (In) Alternatively, it is preferable to use an oxide semiconductor containing zinc (Zn). Furthermore, it is preferable to use one containing In and Zn. It is preferable to use an oxide semiconductor. Examples of oxide semiconductors include Sn-based metals. Oxides can also be used. Furthermore, the electrical components of a transistor using the above-mentioned oxide semiconductor... As a stabilizer to reduce variations in characteristics, gallium (G) is added to the above oxide semiconductor. a) is preferable. Also, tin (S) may be added to the oxide semiconductor as a stabilizer. It is preferable to have n). Also, as a stabilizer, the above oxide semiconductor is made of hafniu It is preferable to have (Hf). Also, as a stabilizer, the above oxide semiconductor is It is preferable that it contains luminium (Al).

[0211] Also, other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce, praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Lu The oxide semiconductor may contain one or more types of tecium (Lu).

[0212] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and the oxide of binary metals. These are In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, and Zn-Mg oxides. Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metals In-Ga-Zn oxides (also written as IGZO), In-Al-Zn oxides Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn acids oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides Materials, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, I n-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides which are oxides of quaternary metals, I n-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al- Using Zn-based oxides, In-Sn-Hf-Zn-based oxides, and In-Hf-Al-Zn-based oxides It is possible to do so. Furthermore, metal oxides that can be applied as the above oxide semiconductors include silica oxide. It may contain n.

[0213] For example, an In-Ga-Zn oxide is a material whose main components are In, Ga, and Zn. This means an oxide containing In, Ga, and Zn, and the ratio of In, Ga, and Zn is not specified. It is also acceptable for metal elements other than a and Zn to be present.

[0214] When using in-Zn metal oxides, for example, In:Zn = 50:1 or In:Zn = 1:2 (When converted to a mole ratio, In2O3:ZnO = 25:1 or In2O3:ZnO = 1:4), preferably In:Zn=20:1 to In:Zn=1:1 (convert to mole ratio) This results in In2O3:ZnO=10:1 to In2O3:ZnO=1:2, and more preferably This is In:Zn=15:1 or In:Zn=1.5:1 (which translates to In2O3 in mole ratios). Oxide targets with a composition ratio of ZnO=15:2 to In2O3:ZnO=3:4 A semiconductor layer of In-Zn-based metal oxide can be formed using this method. For example, In-Z The target used for forming n-based oxide semiconductors has an atomic ratio of In:Zn:O=P:U:R In this case, R > 1.5P + U. By increasing the amount of In, the transistor moves This can improve the degree (also called field effect mobility).

[0215] In addition, as an oxide semiconductor, InMO3(ZnO)m (where m is a number greater than 0) It is also possible to use materials such as InMO3(ZnO). m M is Ga, Al, Mn, and This indicates one or more metallic elements selected from Co.

[0216] For example, In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3) or In:Ga In-Ga-Zn system oxidation with an atomic ratio of Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Oxides of the same composition as the substance can be used. Alternatively, In:Sn:Zn=1:1 :1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6 :1 / 2) or In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) number of atoms It is advisable to use In-Sn-Zn oxides with a similar ratio or oxides with a similar composition.

[0217] However, this is not limited to these, and the semiconductor characteristics required (mobility, threshold voltage, and other electrical characteristics) may also be necessary. Depending on the variation in properties, etc., an appropriate composition should be used. To obtain the desired properties, the carrier density, impurity concentration, defect density, and atomic ratio of metal elements to oxygen are measured. It is preferable to set appropriate interatomic bond distances, densities, etc.

[0218] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. However, Furthermore, even with In-Ga-Zn oxides, mobility can be increased by reducing the bulk defect density. It is possible to do so.

[0219] For example, if the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of an oxide with c=1 is such that the atomic ratio is In:Ga:Zn=A:B:C(A+B+C The composition of the oxides in (1) is considered to be in the same vicinity if a, b, and c are (a - A) 2 +(b-B) 2 + (c-C) 2 ≤r 2 This means satisfying the following condition. For example, r can be set to 0.05. The same applies to other oxides.

[0220] Oxide semiconductors can be single crystals or non-single crystals. In the latter case, they can be amorphous or polycrystalline. But that's fine too. Also, even if the structure contains crystalline parts within the amorphous material, it can be non-amorphous. But that's fine.

[0221] Amorphous oxide semiconductors can be made relatively easily to obtain a flat surface, This can reduce interfacial scattering when fabricating transistors, and it can be done relatively easily and relatively high You can obtain a high degree of mobility.

[0222] Furthermore, in crystalline oxide semiconductors, bulk defects can be reduced even further, and surface By improving the flatness, it is possible to obtain mobility higher than that of an amorphous oxide semiconductor. To improve surface flatness, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably Alternatively, it is preferable to form it on a surface with a nm or smaller.

[0223] Note that Ra is the centerline average roughness defined in JIS B0601, applied to the surface. This value is an extension of the three-dimensional model, and is calculated by "averaging the absolute values ​​of the deviations from the reference plane to the specified plane." It can be expressed as "value" and is defined by the following formula.

[0224]

number

[0225] In the above, S0 is the measurement surface (coordinates (x1,y1)(x1,y2)(x2,y1 Z0 refers to the area of ​​the rectangle enclosed by the four points represented by (x2, y2), and Z0 is This refers to the average height of the measurement surface. Ra stands for Atomic Force Microscope (AFM). Evaluation is possible using a microscope. Note that the measurement surface refers to the surface indicated by all measurement data. It consists of three parameters (X, Y, Z) and is expressed as Z = F(X, Y). The range of X (and Y) is 0 to XMAX (and YMAX), and the range of Z is This is ZMIN or ZMAX.

[0226] Furthermore, as an oxide semiconductor, it is c-axis oriented and, when viewed from the direction of the ab plane, surface, or interface, three It has a horn-shaped or hexagonal atomic arrangement, and along the c-axis, the metal atoms are layered or metal atoms and acid Elementary atoms are arranged in layers, and in the ab plane, the orientation of the a axis or b axis is different (the c axis is... (C-axis-aligned crystal) Oxides containing ( ) may also be used. Next, CAAC will be explained.

[0227] CAAC-containing oxides, in a broad sense, are non-single crystals that can be viewed from a direction perpendicular to their ab-plane. The atoms have a triangular, hexagonal, equilateral triangle, or regular hexagonal arrangement, and are perpendicular to the c-axis direction. When viewed from the front, the oxide contains a layered structure of metal atoms, or a layered structure of metal atoms and oxygen atoms. It refers to.

[0228] CAAC is not a single crystal, nor is it entirely amorphous. Furthermore, CAAC has crystalline parts. It contains crystalline parts, but the boundary between one crystalline part and another cannot be clearly distinguished. It is also said.

[0229] If CAAC contains oxygen, some of the oxygen may be replaced with nitrogen. The c-axis of each individual crystal portion that makes up the structure is in a specific direction (for example, the substrate surface on which CAAC is formed). They may be aligned in a direction perpendicular to the surface of the CAAC, etc. Or, each of the components of the CAAC The normal to the ab plane of the crystal portion is in a certain direction (for example, the substrate surface supporting CAAC, CAAC It may be oriented perpendicular to the surface, etc.

[0230] CAAC can be a conductor, a semiconductor, or an insulator, depending on its composition. Depending on its composition, it may be transparent or opaque to visible light. To do.

[0231] An example of such CAAC is one which is formed in a film-like manner and has a surface perpendicular to the film surface or the supporting substrate surface. When observed from the front, a triangular or hexagonal atomic arrangement is observed, and when the cross-section of the film is observed... Examples of crystals in which metal atoms or a layered arrangement of metal atoms and oxygen atoms (or nitrogen atoms) are observed. It is also possible to do so.

[0232] Next, an example of the crystal structure contained in CAAC will be explained in detail using Figures 18 to 20. In addition, unless otherwise specified, in Figures 18 to 20, the upward direction is the c-axis direction. Let the plane perpendicular to it be called plane ab. Note that when we simply refer to the upper half and the lower half, we mean the plane with plane ab as the boundary. This refers to the upper half and lower half of a case.

[0233] Figure 18(A) shows one 6-coordinate In atom and six 4-coordinate oxygen atoms adjacent to the In atom (hereinafter referred to as 4 The structure shows a coordinated O) and . Here, for each metal atom, the metal atom is close to the metal atom. A structure showing only the tangent oxygen atoms is called a small group. The structure in Figure 18(A) is an octahedral structure. However, for simplicity, it is shown as a planar structure. Note that the upper and lower halves of Figure 18(A) are Each group has three oxygen atoms in a 4-coordinate system. The small group shown in Figure 18(A) has a charge of 0.

[0234] Figure 18(B) shows one 5-coordinate Ga atom and three 3-coordinate oxygen atoms adjacent to the Ga atom (hereinafter referred to as 3 The structure shows a coordinated oxygen atom and two 4-coordinate oxygen atoms adjacent to Ga. The 3-coordinate oxygen atom is All of them are located on the ab plane. There are four of them, one in the upper half and one in the lower half of Figure 18(B). There is an oxygen atom at position 1. Also, since In can take on a 5-coordinate state, it can take on the structure shown in Figure 18(B). The subgroup shown in 18(B) has a charge of 0.

[0235] Figure 18(C) shows a structure having one 4-coordinate Zn and four 4-coordinate O adjacent to the Zn. The structure is shown. The upper half of Figure 18(C) has one 4-coordinate oxygen atom, and the lower half has three 4-coordinate oxygen atoms. There is an O. Alternatively, there are three 4-coordinate Os in the upper half of Figure 18(C) and one in the lower half There may be oxygen atoms with 4 coordination. The small group shown in Figure 18(C) has a charge of 0.

[0236] Figure 18(D) shows a structure having one 6-coordinate Sn and six 4-coordinate O adjacent to the Sn. The structure is shown. The upper half of Figure 18(D) has 3 four-coordinate oxygen atoms, and the lower half has 3 four-coordinate oxygen atoms. There is an O. The small group shown in Figure 18(D) has a charge of +1.

[0237] Figure 18(E) shows a small group containing two Zn molecules. The upper half of Figure 18(E) shows one There is a 4-coordinate oxygen atom, and the lower half has one 4-coordinate oxygen atom. The small group shown in Figure 18(E) The charge becomes -1.

[0238] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is This is called a large group (also known as a unit cell).

[0239] Here, we will explain the rules by which these subgroups combine. These rules are shown in Figure 18(A). The three oxygen atoms in the upper half of the 6-coordinate In each have three adjacent oxygen atoms in the lower half, and the three oxygen atoms in the lower half... Each oxygen atom has three adjacent in atoms in the upward direction. The single oxygen atom in the upper half of the 5-coordinate Ga is One adjacent Ga is located downwards, and one O in the lower half has one adjacent Ga located upwards. The single oxygen atom in the upper half of the 4-coordinate Zn has one adjacent Zn atom below it, and the three oxygen atoms in the lower half are Each atom has three adjacent Zn atoms in the upward direction. Thus, the metal atom has four-coordinate oxygen atoms in the upward direction. The number of atoms is equal to the number of nearby metal atoms below that O, and similarly, the number of metal atoms below the 4 The number of oxygen atoms in coordination is equal to the number of nearby metal atoms above that oxygen atom. Since oxygen is 4-coordinate, The sum of the number of nearby metal atoms below and the number of nearby metal atoms above is 4. Therefore, The number of 4-coordinate oxygen atoms above a metal atom and the number of 4-coordinate oxygen atoms below another metal atom When the sum of the number of atoms is 4, two small groups of metal atoms can bond together. For example, a 6-coordinate metal atom (In or Sn) is bonded via a 4-coordinate oxygen atom in the lower half. In this case, since there are three 4-coordinate oxygen atoms, a 5-coordinate metal atom (Ga or In) or a 4-coordinate gold atom is required. It will bond with one of the group atoms (Zn).

[0240] Metal atoms with these coordination numbers are bonded in the c-axis direction via 4-coordinate oxygen atoms. In addition, multiple small groups combine in such a way that the total charge of the layered structure becomes zero. Form a group.

[0241] Figure 19(A) shows a model diagram of the intermediate groups that constitute the layered structure of the In-Sn-Zn-O system. Figure 19(B) shows the large group, which is composed of three subgroups. C) shows the atomic arrangement when the layer structure of Figure 19(B) is observed from the c-axis direction.

[0242] In Figure 19(A), for simplicity, three-coordinate oxygen atoms are omitted, and only the number of four-coordinate oxygen atoms is shown. For example, the upper and lower halves of Sn each contain three 4-coordinate oxygen atoms, as shown in the circle. It is shown as 3. Similarly, in Figure 19(A), the upper and lower halves of In are shown as 3. Each of these has one O with 4 coordination, which is shown as 1 in the circle. Similarly, Figure 19(A In this case, the lower half has one 4-coordinate oxygen atom, and the upper half has three 4-coordinate oxygen atoms. n and Zn, which has one 4-coordinate oxygen atom in the upper half and three 4-coordinate oxygen atoms in the lower half. It is showing.

[0243] In Figure 19(A), the middle group constituting the layered structure of the In-Sn-Zn-O system is from the top In order, Sn has three 4-coordinate oxygen atoms in the upper half and three in the lower half, and one 4-coordinate oxygen atom in the upper half. It bonds with In in the lower half, and that In bonds with Zn which has three 4-coordinate O atoms in the upper half. Bonded, and through one four-coordinate oxygen atom in the lower half of the Zn, three four-coordinate oxygen atoms are bonded to the upper half and It bonds with In in the lower half, and that In then bonds with two Zn atoms that have one 4-coordinate O in the upper half. It combines with a small group, and through one 4-coordinate O in the lower half of this small group, a 4-coordinate O The structure consists of three oxygen atoms bonded to Sn atoms in the upper half and three in the lower half. Multiple groups are combined to form a larger group.

[0244] Here, in the case of 3-coordinate oxygen and 4-coordinate oxygen, the charge per bond is -0.66, respectively. 7, can be considered as -0.5. For example, In (6-coordinate or 5-coordinate), Zn (4-coordinate) The charges of ) and Sn (5-coordinate or 6-coordinate) are +3, +2, and +4, respectively. Therefore, S The small group containing n has a charge of +1. Therefore, in order to form a layered structure containing Sn Therefore, a charge of -1 is needed to cancel out the charge of +1. As an example of a structure that takes on a charge of -1, see Figure 18(E As shown in ( ), a small group containing two Zn is an example. For example, a small group containing Sn If there is one small group containing two Zn atoms for each single Zn atom, the charges cancel each other out. The total charge of the layered structure can be set to 0.

[0245] Specifically, the large groups shown in Figure 19(B) are repeated, resulting in In-Sn- A Zn-O-based crystal (In2SnZn3O8) can be obtained. The layered structure of the Sn-Zn-O system is In2SnZn2O7(ZnO) m (m is 0 or a natural number) It can be represented by the following empirical formula:

[0246] In addition, there are other oxides of quaternary metals, such as In-Sn-Ga-Zn oxides, and ternary metals. In-Ga-Zn oxides (also written as IGZO), which are oxides of metals, In-A l-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-Al -Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides, In-Ce -Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm- Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Z n-based oxides, In-Dy-Zn-based oxides, In-Ho-Zn-based oxides, In-Er-Zn In-Tm-Zn oxides, In-Yb-Zn oxides, In-Lu-Zn ​​oxides Oxides, and oxides of binary metals such as In-Zn oxides, Sn-Zn oxides, and Al- Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, and In - The same applies when using Ga-based oxides, etc.

[0247] For example, Figure 20(A) shows the intermediate group that constitutes the layered structure of the In-Ga-Zn-O system. A diagram is shown.

[0248] In Figure 20(A), the middle group constituting the layered structure of the In-Ga-Zn-O system is from the top In order, the in atoms have three 4-coordinate oxygen atoms in the upper half and three in the lower half, while the in atoms have one 4-coordinate oxygen atom in the upper half. It bonds with a Zn atom, and through the three 4-coordinate oxygen atoms in the lower half of that Zn atom, one 4-coordinate oxygen atom is bonded to each of them. It bonds with Ga in the upper and lower halves, and via one 4-coordinate O in the lower half of that Ga In this configuration, three 4-coordinate oxygen atoms are bonded to the in atoms in the upper and lower halves. Multiple groups combine to form a larger group.

[0249] Figure 20(B) shows the large group, which is composed of three medium groups. Figure 20(C) is Figure 20(B) shows the atomic arrangement when the layer structure is observed from the c-axis direction.

[0250] Here, the charges of In (6-coordinate or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are as follows: Since the values ​​are +3, +2, and +3, the subgroup containing any of In, Zn, and Ga is electric. The load becomes 0. Therefore, with these combinations of small groups, the sum of the medium groups is The charge is always 0.

[0251] Furthermore, the intermediate groups that constitute the layered structure of the In-Ga-Zn-O system are shown in Figure 20(A). Not limited to medium groups, but combining medium groups with different arrangements of In, Ga, and Zn. It could also be a group.

[0252] The above is an example of a crystal structure contained in CAAC.

[0253] Furthermore, conductive layers 405a to 405c and conductive layers 406a to 4 shown in Figure 5 Each of the 06c elements functions as either the source or drain of a transistor. The conductive layer that functions as the source of a transistor is also called the source electrode or source wiring. A conductive layer that functions as the drain of a transistor is used as the drain electrode or drain wiring. It is also said that.

[0254] Examples of conductive layers 405a to 405c and conductive layers 406a to 406c include For example, aluminum, chromium, copper, tantalum, titanium, molybdenum, or tungsten. Layers of metallic materials such as these, or alloy materials mainly composed of these metallic materials, can be used. Furthermore, conductive layers 405a to 405c, and conductive layers 406a to 406c By laminating layers of materials applicable to the conductive layer 405a to conductive layer 405c, and conductive layer 4 It is also possible to form 06a to conductive layer 406c.

[0255] Furthermore, conductive layers 405a to 405c and conductive layers 406a to 406c A layer containing a conductive metal oxide can also be used. Examples of conductive metal oxides include: For example, indium oxide, tin oxide, zinc oxide, indium oxide tin oxide alloy, or zinc oxide A zinc oxide alloy can be used. And conductive metal oxides applicable to conductive layers 406a to 406c are silicone oxide. It may contain n.

[0256] The insulating layers 407a and 407b are the same as the insulating layers 402a to 402c. For example, an insulating layer made of a material containing Group 13 elements and oxygen in the periodic table can be used. This can be done. Also, for insulating layer 407a and insulating layer 407b, for example, Al2O x , Ga2O x , or Ga x Al 2-x O 3+α You can also use materials that are indicated as follows.

[0257] For example, insulating layers 402a to 402c and insulating layers 407a and 407b Ga2O x It may also be composed of an insulating layer containing gallium oxide as indicated by . Layers 402a to insulating layer 402c, and one of insulating layer 407a and insulating layer 407b, G a2O x It is composed of an insulating layer containing gallium oxide as indicated by, and insulating layer 402a to insulating Layer 402c, and the other of insulating layer 407a and insulating layer 407b are made of Al2O x It is written as It may also be composed of an insulating layer containing aluminum oxide.

[0258] Conductive layer 408a and conductive layer 408b each function as the gate of a transistor. It has. In addition, if the transistor has a structure having conductive layer 408a and conductive layer 408b In addition, either conductive layer 401a and conductive layer 408a, or conductive layer 401b and conductive layer 408b One of them is also called the back gate, back gate electrode, or back gate wiring. By providing multiple layers having the function of a transistor via a channel forming layer, The threshold voltage can be controlled.

[0259] Examples of conductive layers 408a and 408b include aluminum, chromium, copper, and tantalum. Metal materials such as titanium, molybdenum, or tungsten, or these metal materials A layer of alloy material having as its main component can be used. Also, conductive layer 408a and conductive layer 4 By laminating layers of material applicable to 08b, each of the conductive layer 408a and conductive layer 408b It can also be configured as follows:

[0260] Furthermore, conductive layers 408a and 408b are layers containing conductive metal oxides. It is also possible to do so. Examples of conductive metal oxides include indium oxide, tin oxide, and oxide. Zinc, indium oxide tin oxide alloy, or indium oxide zinc oxide alloy can be used. It is possible. Note that the conductive metal oxide applicable to conductive layer 408a and conductive layer 408b is acid It may contain silicon dioxide.

[0261] Furthermore, the transistor of this embodiment is an oxide semiconductor having the function of a channel formation layer. A insulating layer is included on a portion of the body layer, and the insulating layer is superimposed on the oxide semiconductor layer, The structure may include a conductive layer that functions as a drain or a suction layer. In this case, the insulating layer is a layer that protects the channel formation layer of the transistor (also called the channel protection layer). It has the function of a channel protection layer. An insulating layer that has the function of a channel protection layer is, for example, A layer of material applicable to insulating layers 402a to 402c can be used. A channel protection layer is formed by laminating layers of a material applicable to insulating layers 402a to 402c. An insulating layer having the function of [this] may be constructed.

[0262] Furthermore, as shown in Figures 5(A) to 5(E), the transistor in this embodiment is not necessarily... Furthermore, the entire oxide semiconductor layer is superimposed on a conductive layer that functions as a gate electrode. It is not necessary, but the entire oxide semiconductor layer is superimposed on a conductive layer that functions as a gate electrode. By adopting this structure, the incidence of light into the oxide semiconductor layer can be suppressed.

[0263] Furthermore, the field effect transfer of insulated gate transistors, which is not limited to oxide semiconductors, is actually measured. Mobility can be lower than its actual mobility for various reasons. Factors that reduce mobility include In some cases, defects exist within the semiconductor or at the interface between the semiconductor and the insulating film, but the Levinson model Using this method, we can theoretically derive the field-effect mobility assuming there are no defects inside the semiconductor. I can do it.

[0264] Let μ0 be the intrinsic mobility of the semiconductor, and μ be the measured field-effect mobility. Assuming the existence of tactical barriers (such as grain boundaries), the following equation can be used to express this.

[0265]

number

[0266] Here, E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. Furthermore, assuming that the potential barrier originates from a defect, the Levinson model... Therefore, E is expressed by the following formula.

[0267]

number

[0268] Here, e is the elementary charge, N is the average defect density per unit area in the channel, and ε is the semiconductor's Dielectric constant, n is the number of carriers in the channel per unit area, Cox is per unit area The capacitance is Vg, the gate voltage is Vg, and the channel thickness is t. Note that semiconductors with a thickness of 30 nm or less If it is a body layer, the channel thickness can be considered the same as the semiconductor layer thickness. Also, linear The drain current Id in the region is expressed by the following formula:

[0269]

number

[0270] Here, L is the channel length and W is the channel width, and in this case, L = W = 10 μm. Also, Vd is the drain voltage. Dividing both sides of the above equation by Vg and then taking the logarithm of both sides, we obtain the following equation.

[0271]

number

[0272] The right-hand side (the rightmost part) of equation 5 is a function of Vg. As can be seen from this equation, the vertical axis is ln (Id / Vg), the slope of the straight line in the graph obtained by plotting the measured values ​​with 1 / Vg on the horizontal axis. The defect density N can be determined from the Id-Vg characteristics of the transistor. The degree can be evaluated. Oxide semiconductors include indium (In), tin (Sn), and zinc (Z). If the ratio of n) is In:Sn:Zn=1:1:1, the defect density N is 1 × 10⁻¹⁰ 12 / c m2 It is to that extent.

[0273] Based on the defect density and other factors determined in this way, we can use equations 2 and 3 to conclude that μ0 = 120 cm². 2 / Vs This is derived. The mobility measured in defective In-Sn-Zn oxide is 40 cm². 2 / V It is approximately s. However, oxide semiconductors without defects inside the semiconductor and at the interface between the semiconductor and the insulating film... Body mobility μ0 is 120 cm 2 It can be expected that the result will be / Vs.

[0274] However, even if there are no defects inside the semiconductor, scattering at the interface between the channel and the gate insulating layer can cause problems. The transport characteristics of the transistor are affected, specifically at the interface between the channel and the gate insulating layer. The mobility μ1 at a distance x from the point is expressed by the following formula:

[0275]

number

[0276] Here, D is the electric field in the gate direction, and B and l are constants. B and l are derived from actual measurement results. It can be calculated, and from the above measurement results, B = 4.75 × 10 7 cm / s, l=10n m is the depth to which interfacial scattering occurs. When D increases (i.e., the gate voltage increases) Since the second term of equation 6 increases, it can be seen that the mobility μ1 decreases.

[0277] Transistor mobility using an ideal oxide semiconductor channel with no defects inside the semiconductor. The results of the calculation of μ2 are shown in Figure 21. Note that the calculation was performed using a Synopsys device simulator. Using Sentaurus Device, a bandgap in oxide semiconductors. The top, electron affinity, relative permittivity, and thickness were measured at 2.8 electron volts and 4.7 electron volts, respectively. The values ​​were set to 15 nm and 15 nm. These values ​​were obtained by measuring thin films formed by the sputtering method. This was obtained through [method / method].

[0278] Furthermore, the work functions of the gate, source, and drain were set to 5.5 electron volts and 4.6 electron volts, respectively. The voltage was set to 4.6 electron volts. The gate insulating layer thickness was 100 nm, and the relative permittivity was set to 4.6 electron volts. The specification was set to 4.1. Both the channel length and channel width were 10 μm, and the drain voltage Vd was 0. It is 1V.

[0279] As shown in Figure 21, with a gate voltage of 1V, the mobility is 100cm. 2 / Vs or greater, gate As the voltage increases further, interfacial scattering increases, and mobility decreases. To reduce this, the semiconductor layer surface must be made atomically flat (Atomic Lay (Flatness) is desirable.

[0280] When a miniature transistor is fabricated using an oxide semiconductor with such mobility, The results of the calculations are shown in Figures 22 to 24. Note that the cross-sectional structure of the transistor used in the calculations is shown. The structure is shown in Figure 25. The transistor shown in Figure 25 has an oxide semiconductor layer with n + It exhibits the following conductivity type. It has semiconductor region 703a and semiconductor region 703c. The resistivity of region 703c is 2 × 10⁻⁶. -3 Let it be Ωcm.

[0281] The transistor shown in Figure 25(A) is embedded in the base insulating layer 701 and the base insulating layer 701. Formed on top of an embedded insulator 702 made of aluminum oxide that is formed to be The transistor consists of semiconductor region 703a, semiconductor region 703c, and the channel sandwiched between them. The gate electrode has an intrinsic semiconductor region 703b that forms a region for forming a gate, and a gate electrode 705. The width of 705 is set to 33 nm.

[0282] A gate insulating layer 704 is provided between the gate electrode 705 and the semiconductor region 703b, and also On both sides of the electrode 705 are side wall insulators 706a and 706b, and the gate electrode 7 An insulator 707 is placed on top of 05 to prevent short circuits between the gate electrode 705 and other wiring. It has. The width of the side wall insulator shall be 5 nm. Also, semiconductor region 703a and semiconductor region 70 It has a source electrode 708a and a drain electrode 708b in contact with 3c. Note that Figure 25( The channel width of the transistor shown in A) is set to 40 nm.

[0283] The transistor shown in Figure 25(B) consists of a base insulating layer 701 and an embedded aluminum oxide layer. It is formed on the embedded insulator 702, and has a semiconductor region 703a, a semiconductor region 703c, and The intrinsic semiconductor region 703b sandwiched between them, the gate electrode 705 with a width of 33 nm, and the gate insulating Edge layer 704, side wall insulators 706a and 706b, insulator 707, source The transistor shown in Figure 25(A) includes electrode 708a and drain electrode 708b. It is the same as this.

[0284] The difference between the transistor shown in Figure 25(A) and the transistor shown in Figure 25(B) is the side wall insulation. This is the conductivity type of the semiconductor region below the edge material 706a and the side wall insulator 706b. Figure 25(A) In the transistor shown, the semiconductor region below the side wall insulators 706a and 706b is n +Semiconductor regions 703a and 703c exhibit the conductivity type shown in Figure 25(B In the transistor shown in Figure 25(B), the intrinsic semiconductor region is 703b. In the semiconductor layer shown, semiconductor region 703a (semiconductor region 703c) and gate electrode 70 A region is created where 5 does not overlap with Loff. This region is called the offset region, and The width Loff is called the offset length. As is clear from the diagram, the offset length is the side wall insulator. It is the same width as 706a (side wall insulator 706b).

[0285] Other parameters used in the calculations are as described above. The calculations were performed using a Synopsys device. The simulation software, Sentaurus Device, was used. Figure 22 shows The drain current (Id, solid line) and mobility (μ) of the transistor structure shown in Figure 25(A) The dotted line shows the gate voltage (Vg) dependence. The drain current Id is calculated by changing the drain voltage to +1V. The mobility μ was calculated assuming a drain voltage of +0.1V.

[0286] Figure 22(A) shows the case when the gate insulating layer thickness is 15 nm, and Figure 22(B) shows the gate This figure shows the case where the thickness of the gate insulating layer is 10 nm, and Figure 22(C) shows the thickness of the gate insulating layer. This diagram shows the case when the thickness is set to 5 nm. The thinner the gate insulating layer, the greater the dray effect, especially in the off state. The on-current Id (off-current) decreases significantly. On the other hand, the peak value of mobility μ and the on-state decrease. There is no significant change in the drain current Id (on-current). At a gate voltage of around 1V, the drain The current was shown to exceed 10 μA.

[0287] Figure 23 shows a transistor with the structure shown in Figure 25(B), where the offset length Loff is 5n Dependence of drain current Id (solid line) and mobility μ (dotted line) on gate voltage Vg when m is the drain current Id. This figure shows the result. Note that the drain current Id is calculated assuming a drain voltage of +1V, and the drain voltage is +1V. The mobility μ was calculated with a voltage of +0.1V. Figure 23(A) shows the thickness of the gate insulating layer. The first figure shows the case where the thickness is 15 nm, while Figure 23(B) shows the case where the gate insulating layer thickness is 10 nm. The diagram shows the case where the gate insulating layer thickness is 5 nm, and Figure 23(C) shows the case where the gate insulating layer thickness is 5 nm.

[0288] Furthermore, Figure 24 shows a transistor with the structure shown in Figure 25(B), where the offset length Loff is 1 Gate voltage dependence of drain current Id (solid line) and mobility μ (dotted line) when the wavelength is 5 nm. This figure shows the result. Note that the drain current Id is calculated assuming a drain voltage of +1V, and the drain voltage is +1V. The mobility μ was calculated with a voltage of +0.1V. Figure 24(A) shows the thickness of the gate insulating layer. The first figure shows the case where the thickness is 15 nm, while Figure 24(B) shows the case where the gate insulating layer thickness is 10 nm. The diagram shows the case where the gate insulating layer thickness is 5 nm, and Figure 24(C) shows the case where the gate insulating layer thickness is 5 nm.

[0289] In both cases, the thinner the gate insulating layer, the more significantly the off-current decreases, while the mobility μ is reduced. There are no significant changes in the quelcher value or on-current.

[0290] Note that the peak of mobility μ is at 80 cm in Figure 22. 2 It is approximately / Vs, but in Figure 23 it is 60 cm 2 Approximately / Vs, 40cm in Figure 24 2 / Vs is approximately, and the offset length Loff increases. The mobility μ decreases as the value decreases. Similarly, the off-current also tends to decrease. On the other hand, the on-current The current decreases with increasing offset length Loff, but this is less significant than the decrease in off-current. It is much gentler. Also, in both cases, the gate voltage is around 1V and the drain current is 10μA. It was shown that it could be surpassed.

[0291] Furthermore, a transient with an oxide semiconductor mainly composed of In, Sn, and Zn as the channel formation region In the process of forming the oxide semiconductor, the substrate is heated to deposit the film, or the oxide semiconductor Good properties can be obtained by heat treatment after forming the conductive layer. A component refers to an element that makes up 5 atomic percent or more of the composition.

[0292] The process involves intentionally heating the substrate after depositing an oxide semiconductor layer mainly composed of In, Sn, and Zn. This makes it possible to improve the field-effect mobility of the transistor. By shifting the threshold voltage of the sta function positively, it becomes possible to normally turn it off.

[0293] For example, Figure 28 shows a channel with In, Sn, and Zn as the main components, with a channel length L of 3 μm and a channel width A transient is used with an oxide semiconductor layer with a thickness of 10 μm and a gate insulating layer with a thickness of 100 nm. This diagram shows the characteristics of the sta. Note that Vd is set to 10V in this case.

[0294] Figure 28(A) shows the process of sputtering In, Sn, and Zn onto a substrate without intentionally heating it. This figure shows the transistor characteristics when an oxide semiconductor layer is formed. The field-effect mobility is 18.8 cm. 2 / Vsec. On the other hand, the substrate is intentionally heated and I Forming an oxide semiconductor layer mainly composed of n, Sn, and Zn improves field-effect mobility. This becomes possible. Figure 28(B) shows the substrate heated to 200°C to form mainly In, Sn, and Zn. This figure shows the transistor characteristics when an oxide semiconductor layer is formed. The field-effect mobility is 32.2 cm. 2 It is / Vsec.

[0295] The field-effect mobility is determined by the thermal treatment of an oxide semiconductor layer mainly composed of In, Sn, and Zn. By doing so, it can be further improved. Figure 28(C) shows In, Sn, and Zn. An oxide semiconductor layer mainly composed of [component name] is deposited by sputtering at 200°C, and then heat-treated at 650°C. This diagram shows the transistor characteristics when the process is performed. At this time, the field-effect mobility is 34. 5cm 2 It is / Vsec.

[0296] By intentionally heating the substrate, moisture during sputtering deposition is absorbed into the oxide semiconductor layer. The amount of acid incorporated can be reduced. Also, by heat treatment after film formation, the acid can be reduced. Hydrogen, hydroxyl groups, or water can be released and removed from the ionized semiconductor layer, as described above. This can improve the field effect mobility. Such improvement in field effect mobility leads to dehydration. In addition to the removal of impurities through chemical and dehydrogenation, the interatomic distance is shortened due to increased density. It is also presumed that crystals are formed by removing impurities from oxide semiconductors to increase their purity. This allows for purification. In this way, the highly purified non-single-crystal oxide semiconductor is, ideally, 100cm 2 It is estimated that it will also be possible to achieve field effect mobility exceeding / Vsec. ru.

[0297] Oxygen ions are implanted into an oxide semiconductor mainly composed of In, Sn, and Zn, and then heat-treated to remove the acid By releasing hydrogen, hydroxyl groups, or water contained in the ion semiconductor, and simultaneously with the heat treatment or The oxide semiconductor may be crystallized by subsequent heat treatment. By performing a crystallization treatment, non-single-crystal oxide semiconductors with good crystallinity can be obtained.

[0298] The effect of intentionally heating the substrate to form a film and / or heat treating it after film formation is due to the electric field. In addition to improving effective mobility, it also contributes to enabling normally-off transistors. It exists. Oxide semiconductors mainly composed of In, Sn, and Zn formed without intentionally heating the substrate. In transistors where the conductor layer is used as the channel formation region, the threshold voltage shifts to the negative. There is a tendency for this to happen. However, when using an oxide semiconductor layer formed by intentionally heating the substrate, This negative shift in the threshold voltage is eliminated. In other words, the threshold voltage is no longer affected by the transistor. The movement is moving in the direction of Mari-off. This trend can be seen from the comparison between Figure 28(A) and Figure 28(B). This can also be confirmed.

[0299] Furthermore, the threshold voltage can also be controlled by changing the ratio of In, Sn, and Zn. Therefore, by setting the composition ratio to In:Sn:Zn=2:1:3, the transistor can be made It can be made easier to normalize. Also, the target composition ratio In:Sn: By setting Zn=2:1:3, a highly crystalline oxide semiconductor layer can be obtained.

[0300] The intentional substrate heating temperature or heat treatment temperature is 150°C or higher, preferably 200°C or higher. More preferably 400°C or higher, and by forming the film or heat treating at a higher temperature, the traction is reduced. This makes it possible to normally disable the generator.

[0301] Furthermore, by intentionally heating the substrate during film formation and / or performing heat treatment after film formation, the gate It can improve stability against bias stress. For example, 2 MV / cm, 15 Under the conditions of 0°C and 1 hour of application, the threshold voltage drift is less than ±1.5V each. Preferably, a voltage of less than 1.0V can be obtained.

[0302] In fact, sample 1, which has not undergone heat treatment after oxide semiconductor layer deposition, and sample 1, which has undergone heat treatment at 650°C. A BT test was performed on the transistor of sample 2.

[0303] First, the substrate temperature was set to 25°C and Vd to 10V, and the Vg-Id characteristics of the transistor were measured. I did that. Next, I set the substrate temperature to 150°C and Vd (voltage between drain and source) to 0.1 Let V be the value. Next, the electric field strength applied to the gate insulating layer 608 is set to 2 MV / cm. A voltage of 20V was applied to Vg (the voltage between the gate and source) and held for 1 hour. Next, Vg was set to 0V. Next, the substrate temperature was set to 25°C, Vd to 10V, and the Vg of the transistor was set to 0V. -Id measurement was performed. This is called the PlusBT test.

[0304] Similarly, first set the substrate temperature to 25°C and Vd to 10V, and then the Vg-Id characteristics of the transistor. The following measurements were taken. Next, the substrate temperature was set to 150°C and Vd to 0.1V. Next, the gate -20V is applied to Vg so that the electric field strength applied to the insulating layer 608 is -2MV / cm. Then, it was held in that state for 1 hour. Next, Vg was set to 0V. Next, the substrate temperature was set to 25°C, and V We set d to 10V and measured the Vg-Id of the transistor. This is called the negative BT test. cormorant.

[0305] The results of the positive BT test for sample 1 are shown in Figure 29(A), and the results of the negative BT test are shown in Figure 29(B). The results of the positive BT test for sample 2 are shown in Figure 30(A), and the results of the negative BT test are shown in Figure 30(A). The results are shown in Figure 30(B).

[0306] The threshold voltage fluctuations obtained from the positive BT test and negative BT test of sample 1 were 1.8, respectively. The values ​​were 0V and -0.42V. In addition, the positive BT test and negative BT test of sample 2 were performed. The threshold voltage fluctuations were 0.79V and 0.76V, respectively. Both Sample 1 and Sample 2 showed small fluctuations in threshold voltage before and after the BT test, indicating reliability. It's clear that it's expensive.

[0307] Heat treatment can be carried out in an oxygen atmosphere, but first use nitrogen or an inert gas, or under reduced pressure. The heat treatment may be performed in an oxygen-containing atmosphere first. By adding oxygen to the oxide semiconductor after the initial ionization process, the effect of the heat treatment can be further enhanced. This can be done. Also, to add oxygen later, oxygen ions can be accelerated by an electric field to form an oxide semiconductor. A method of injecting into layers may also be applied.

[0308] Defects due to oxygen vacancies exist in the oxide semiconductor and at the interface with the film stacked on the oxide semiconductor. Although it is easily formed, the heat treatment involves introducing an excess of oxygen into the oxide semiconductor. This makes it possible to compensate for the oxygen deficiency that is constantly generated by excess oxygen. The primary element is oxygen present in the interlattice space, and its oxygen concentration is 1 × 10⁻¹⁶ 16 / cm 3 The above 2 x 1 0 20 / cm 3 The following method allows the crystal to be incorporated into the oxide semiconductor without causing any distortion. It is possible.

[0309] Furthermore, the heat treatment is used to ensure that at least some of the oxide semiconductor contains crystals. A more stable oxide semiconductor layer can be obtained. For example, a composition ratio of In:Sn:Zn = 1 Using a 1:1 target, an oxide film was deposited by sputtering without intentionally heating the substrate. The semiconductor layer has a halo pattern, which can be detected by X-ray diffraction (XRD). A n is observed. This deposited oxide semiconductor layer is then heat-treated to induce crystallization. This can be done. The heat treatment temperature is arbitrary, but for example, by performing a heat treatment at 650°C, Clear diffraction peaks can be observed using X-ray diffraction.

[0310] In fact, we performed XRD analysis on the In-Sn-Zn-O film. For the XRD analysis, we used Bruker Using the AXS D8 ADVANCE X-ray diffractometer, the Out-of-Plane method was used. It was measured.

[0311] Sample A and Sample B were prepared for XRD analysis. Samples A and B are shown below. The method for making it will be explained.

[0312] First, an In-Sn-Zn-O film with a thickness of 100 nm is formed on a dehydrogenated quartz substrate. It formed a membrane.

[0313] The In-Sn-Zn-O film was formed using a sputtering apparatus in an oxygen atmosphere with a power of 100W. The film was deposited as DC. The target was I with an atomic ratio of In:Sn:Zn = 1:1:1. An n-Sn-Zn-O target was used. The substrate heating temperature during film deposition was 200°C. The sample prepared in this manner was designated as Sample A.

[0314] Next, a sample prepared in the same manner as sample A was subjected to heat treatment at a temperature of 650°C. The heat treatment involves first heating in a nitrogen atmosphere for 1 hour, and then, without lowering the temperature, in an oxygen atmosphere. The sample prepared in this manner was subjected to a further heat treatment for one hour.

[0315] Figure 33 shows the XRD spectra of sample A and sample B. In sample A, the peak originating from the crystal is Although not observed, in sample B, 2θ was near 35 degrees and between 37 and 38 degrees. A peak originating from the crystal was observed.

[0316] Thus, oxide semiconductors mainly composed of In, Sn, and Zn can be formed by intentionally adding material to the substrate during film deposition. By heating and / or heat-treating after film formation, the characteristics of the transistor can be improved. It is possible.

[0317] This substrate heating and heat treatment removes hydrogen and hydroxyl groups, which are harmful impurities for oxide semiconductors, from the film. It has the effect of preventing it from being included or removing it from the film. In other words, oxide semi By removing hydrogen, which acts as a donor impurity in the conductor, the purity can be increased, This allows for the normal-off operation of transistors, and the oxide semiconductor can be made highly pure. By doing so, the off-current can be reduced to 1 aA / μm or less. Here, the off-current The unit of the value indicates the current value per 1 μm of channel width.

[0318] Specifically, as shown in Figure 34, when the substrate temperature is 125°C, the ratio is 1 aA / μm(1×1 0 -18 (A / μm) or less, at 85℃ it is 100zA / μm (1×10 -19 A / μm ) Below this, at room temperature (27℃), it is 1 zA / μm (1 × 10⁻⁶). -21 (A / μm) should be less than or equal to the specified limit. This is possible. Preferably, at 125°C, 100 zA / μm (1 × 10⁻⁶ -19 A / μ m) or less, at 85°C, 10 zA / μm (1 × 10 -20 A / μm) or less, at room temperature At 0.1 zA / μm (1 × 10⁻⁶ -22 It can be reduced to less than A / μm.

[0319] However, to prevent hydrogen and moisture from entering the film during the deposition of the oxide semiconductor layer, the outside of the deposition chamber is used. This aims to sufficiently suppress leaks from outside and degassing from the inner walls of the deposition chamber, thereby increasing the purity of the sputtering gas. Preferably, the sputtering gas has a dew point of -70°C or lower so that moisture is not contained in the film. It is preferable to use the gas shown below. Also, the target itself should contain hydrogen, water, and other impurities. It is preferable to use a highly purified target so that it does not contain any pure substances. Oxide semiconductors, mainly composed of In, Sn, and Zn, can have moisture removed from the film through heat treatment. However, compared to oxide semiconductors mainly composed of In, Ga, and Zn, the moisture release temperature is Because of the high moisture content, it is preferable to form a film that does not contain moisture from the beginning.

[0320] Furthermore, transistors using samples that underwent a 650°C heat treatment after oxide semiconductor layer deposition were also developed. In this study, the relationship between substrate temperature and electrical characteristics was evaluated.

[0321] The transistor used for the measurement had a channel length L of 3 μm, a channel width W of 10 μm, and Lov The thickness is 3 μm on each side (6 μm total), and dW is 0 μm. Vd was set to 10 V. The substrate temperature was set at -40°C, -25°C, 25°C, 75°C, 125°C, and 150°C. In a transistor, the overlapping width between the gate electrode and the pair of electrodes is called Lov, and acid The overhang of a pair of electrodes relative to the semiconductor layer is called dW.

[0322] Figure 31 shows the Vg dependence of Id (solid line) and field-effect mobility (dotted line). Also, Figure 32 Figure (A) shows the relationship between substrate temperature and threshold voltage, and Figure 32(B) shows the relationship between substrate temperature and field effect mobility. This indicates.

[0323] Figure 32(A) shows that the threshold voltage decreases as the substrate temperature increases. The ambient temperature range was -40°C to 150°C, with voltages ranging from 0.38V to -1.08V.

[0324] Furthermore, Figure 32(B) shows that the field-effect mobility decreases as the substrate temperature increases. The temperature range is -40°C to 150°C, and the depth is 37.4 cm. 2 / Vs~33.4cm 2 / Vs Yes, it was. Therefore, it can be seen that the variation in electrical characteristics is small within the temperature range mentioned above.

[0325] The above-mentioned oxide semiconductor, mainly composed of In, Sn, and Zn, is used as the channel formation region. According to Rangista, the off-current is kept below 1 aA / μm while the field-effect mobility is 30c. m 2 / Vsec or greater, preferably 40cm 2 / Vsec or more, more preferably 60cm 2 It can be set to / Vsec or higher, satisfying the on-current value required by the LSI. For example, For a FET with L / W = 33nm / 40nm, gate voltage 2.7V, drain voltage 1.0V It can sometimes supply an on-current of 12 μA or more. Furthermore, it meets the requirements for transistor operation. Sufficient electrical characteristics can be ensured even within the temperature range. For example, transistors made of oxide semiconductors are embedded within integrated circuits made of Si semiconductors. Even so, it is possible to realize integrated circuits with new functions without sacrificing operating speed. Cut.

[0326] Next, we will discuss an example of a transistor using an In-Sn-Zn-O film as the oxide semiconductor layer. This will be explained using Figure 26 and other diagrams.

[0327] Figure 26 shows the top gate, top contact structure of a coplanar transistor. These are top views and cross-sectional views. Figure 26(A) shows a top view of the transistor. Also, Figure 26(B) Figure 26(A) shows the cross-section AB corresponding to the dashed line AB.

[0328] The transistor shown in Figure 26(B) consists of a substrate 750 and an insulating base provided on the substrate 750. Layer 752, protective insulating layer 754 provided around the base insulating layer 752, and base insulating layer 75 2 and a high-resistance region 756a and a low-resistance region 756b provided on the protective insulating layer 754 An oxide semiconductor layer 756 and a gate insulating layer 758 provided on the oxide semiconductor layer 756 The gate electrode is provided superimposed on the oxide semiconductor layer 756 via the gate insulating layer 758. 760, a side wall insulator 762 provided in contact with the side surface of the gate electrode 760, and at least A pair of electrodes 764 provided in contact with the low-resistance region 756b, and at least an oxide semiconductor layer 756, an interlayer insulating layer 766 provided covering the gate electrode 760 and the pair of electrodes 764, , contact with at least one of the pair of electrodes 764 through an opening provided in the interlayer insulating layer 766. It has a wiring 768 that is provided in succession.

[0329] Although not shown in the diagram, it also has a protective film covering the interlayer insulating layer 766 and the wiring 768. It is acceptable if it is provided. By providing the protective film, surface conduction of the interlayer insulating layer 766 is prevented. This reduces the minute leakage current that occurs, thereby reducing the transistor's off-current. It is possible.

[0330] Next, a transistor using a different In-Sn-Zn-O film as the oxide semiconductor layer. Here is another example.

[0331] Figure 27 is a top view and a cross-sectional view showing the structure of the transistor fabricated in this embodiment. Figure 27(A) is a top view of the transistor. Figure 27(B) is a single point view of Figure 27(A). This is a cross-sectional view corresponding to the dashed line AB.

[0332] The transistor shown in Figure 27(B) consists of a substrate 600 and an insulating base provided on the substrate 600. Layer 602, an oxide semiconductor layer 606 provided on the underlying insulating layer 602, and an oxide semiconductor layer A pair of electrodes 614 in contact with 606, and provided on the oxide semiconductor layer 606 and the pair of electrodes 614 The gate insulating layer 608 is superimposed on the oxide semiconductor layer 606 via the gate insulating layer 608. The gate electrode 610 is provided in a folded manner, and the gate insulating layer 608 and the gate electrode 610 are covered An interlayer insulating layer 616 is provided, and a pair of openings provided in the interlayer insulating layer 616 are connected. A wiring 618 that connects to the electrode 614, and an interlayer insulating layer 616 and a component that covers the wiring 618 are provided. It has a protective film 620 and

[0333] As the substrate 600, a glass substrate is used, and as the underlying insulating layer 602, a silicon oxide film is used. The semiconductor layer 606 is an In-Sn-Zn-O film, and the pair of electrodes 614 are tungsten As the tene film, a silicon oxide film is used as the gate insulating layer 608, and as the gate electrode 610, a silicon oxide film is used. The laminated structure of the tantalum oxide film and the tungsten film is configured such that the interlayer insulating layer 616 is silica oxide nitride. The laminated structure of the condenser film and the polyimide film is used for the wiring 618, which consists of a titanium film, an aluminum film, The titanium film is formed in this order in a laminated structure, and the protective film 620 is a polyimide film, They used them.

[0334] In the transistor with the structure shown in Figure 27(A), the gate electrode 610 and the pair of electrodes are... The width of the overlap with 614 is called Lov. Similarly, a pair of electrons with respect to the oxide semiconductor layer 606 The overhang of the 614 pole is called dW.

[0335] Furthermore, as an example of the transistor fabrication method in this embodiment, the transistor shown in Figure 5(A) An example of a method for manufacturing a generator will be explained using Figures 6(A) to 6(E). Figure 6(A Figures 6(E) through 5(A) show cross-sections illustrating an example of a transistor fabrication method. This is a schematic diagram.

[0336] First, as shown in Figure 6(A), prepare a substrate 400a, and place the first conductive material on the substrate 400a. A conductive layer 401a is formed by forming a film and etching a portion of the first conductive film. .

[0337] For example, forming a film of a material applicable to the conductive layer 401a using a sputtering method. This allows for the formation of a first conductive film. Furthermore, the materials applicable to the conductive layer 401a are also described. It is also possible to form a first conductive film by stacking films.

[0338] Furthermore, impurities such as hydrogen, water, hydroxyl groups, or hydrides may be used as the sputtering gas. By using a highly purified gas from which impurities have been removed, the concentration of the above-mentioned impurities in the formed film is reduced. It is possible.

[0339] Before forming the film using the sputtering method, the preheating chamber of the sputtering apparatus is used. Preheating treatment may be performed. By performing the above preheating treatment, hydrogen, moisture, etc. Impurities can be removed.

[0340] Furthermore, before forming the film using the sputtering method, for example, argon, nitrogen, helium, Alternatively, in an oxygen atmosphere, without applying voltage to the target side, apply voltage to the substrate side using an RF power supply. A process is performed to modify the surface to be formed by applying a plasma (also called reverse sputtering). This is also good. By performing reverse sputtering, powdery material (particles) adhering to the surface to be formed can be removed. It can remove (also called garbage).

[0341] Furthermore, when forming a film using the sputtering method, an adsorption-type vacuum pump is used, It can remove residual moisture in the film deposition chamber where the film is formed. For example, using a cryopump, ion pump, or titanium sublimation pump. This can be done. In addition, a turbomolecular pump equipped with a cold trap can be used to control the temperature inside the deposition chamber. It can also remove residual moisture.

[0342] Furthermore, as in the method for forming the conductive layer 401a described above, the construction of the transistor in this embodiment In the example of the manufacturing method, when a layer is formed by etching a part of the film, for example, photolithography A resist mask is formed on a portion of the film by the roughing process, and the film is then processed using the resist mask. Layers can be formed by etching. In this case, after layer formation... Remove the resist mask.

[0343] Alternatively, a resist mask may be formed using an inkjet method. By using this method, photomasks become unnecessary, thus reducing manufacturing costs. Furthermore, by using an exposure mask (also called a multi-tone mask) that has multiple regions with different transmittances... A resist mask may be formed. By using a multi-gradation mask, regions of different thicknesses can be formed. A resist mask with a region can be formed, and the resist used in the fabrication of transistors The number of tomasks can be reduced.

[0344] Next, as shown in Figure 6(B), by forming a first insulating film on the conductive layer 401a, An insulating layer 402a is formed.

[0345] For example, methods such as sputtering and plasma CVD can be applied to the insulating layer 402a. A first insulating film can be formed by forming a film of the material. Also, insulating layer 40 A first insulating film can also be formed by laminating films of a material applicable to 2a. Furthermore, high-density plasma CVD (for example, μ-wave (for example, μ-wave with a frequency of 2.45 GHz)) A film of a material applicable to the insulating layer 402a is formed using a high-density plasma CVD method. By doing so, the insulating layer 402a can be made denser, and the dielectric strength of the insulating layer 402a can be increased. It can be improved.

[0346] Next, as shown in Figure 6(C), an oxide semiconductor layer is formed on the insulating layer 402a, and then An oxide semiconductor layer 403a is formed by etching a portion of the oxide semiconductor layer.

[0347] For example, an oxide semiconductor material applicable to the oxide semiconductor layer 403a using the sputtering method An oxide semiconductor layer can be formed by forming a film of material. The oxide semiconductor layer may be formed under gas, an oxygen atmosphere, or a mixed atmosphere of a noble gas and oxygen. stomach.

[0348] Also, as a sputtering target, In2O3:Ga2O3:ZnO=1:1:1 Forming an oxide semiconductor layer using an oxide target with a composition ratio of [molar ratio]. This is possible. Also, for example, In2O3:Ga2O3:ZnO = 1:1:2 [molar ratio] An oxide semiconductor layer may be formed using an oxide target with the following composition ratio.

[0349] Furthermore, when using an In-Sn-Zn-O system material as an oxide semiconductor, the target used The composition ratio of the t is In:Sn:Zn in atomic ratio, which is 1:2:2, 2:1:3, 1:1:1. Alternatively, an oxide target with a ratio such as 20:45:35 is used. Note that the In-Sn-Zn system The oxide can be called ITZO.

[0350] Furthermore, when forming an oxide semiconductor layer using the sputtering method, the substrate 400a is subjected to reduced pressure. The substrate 400a is then heated to a temperature of 100°C to 600°C, preferably 200°C to 400°C. The substrate 400a may be heated downwards. By heating the substrate 400a, the above impurities in the oxide semiconductor layer are removed. The concentration can be reduced, and damage to the oxide semiconductor layer by the sputtering method can be minimized. It is possible.

[0351] Next, as shown in Figure 6(D), a second layer is applied on the insulating layer 402a and the oxide semiconductor layer 403a. A conductive film is formed, and a part of the second conductive film is etched to form a conductive layer 405a and A conductive layer 406a is formed.

[0352] For example, a method such as sputtering can be applied to conductive layers 405a and 406a. A second conductive film can be formed by forming a film of the material. Also, conductive layer 40 A second conductive film is formed by laminating a film of a material applicable to 5a and the conductive layer 406a. It is possible to achieve this.

[0353] Next, as shown in Figure 6(E), an insulating layer 407a is placed in contact with the oxide semiconductor layer 403a. It forms.

[0354] For example, under a noble gas (typically argon) atmosphere, under an oxygen atmosphere, or a mixture of noble gas and oxygen To form a film applicable to the insulating layer 407a using the sputtering method under a suitable atmosphere. This allows for the formation of an insulating layer 407a. Using the sputtering method, the insulating layer 40 By forming 7a, the oxide has the function of a transistor back channel. The decrease in resistance in the semiconductor layer 403a can be suppressed. Also, the insulating layer 407a The substrate temperature during formation is preferably between room temperature and 300°C.

[0355] Furthermore, before forming the insulating layer 407a, a plasma gas such as N2O, N2, or Ar is used. The surface treatment is performed to remove adsorbed water and other substances adhering to the surface of the exposed oxide semiconductor layer 403a. This may be done. If plasma treatment is performed, the insulating layer 407 may be treated without being exposed to the atmosphere afterward. It is preferable to form a.

[0356] Furthermore, in one example of the transistor fabrication method shown in Figure 5(A), for example, 400°C or more and 75°C Heat treatment is performed at a temperature below 0°C, or above 400°C but below the strain point of the substrate. For example, oxide After forming the semiconductor layer, a portion of the oxide semiconductor layer is etched, and then a second conductive film is formed. After that, after etching a portion of the second conductive film, or after forming the insulating layer 407a, The following heat treatment is performed.

[0357] The heat treatment apparatus used for the above heat treatment may include an electric furnace or a heat source such as a resistance heating element. A device can be used that heats the object to be processed by heat conduction or thermal radiation, for example, GR TA (Gas Rapid Thermal Annealing) device or LRTA ( RTA (Ra) devices such as Lamp Rapid Thermal Annealing (RA) A pid (thermal annealing) device can be used. LRTA device Examples of lamps include halogen lamps, metal halide lamps, xenon arc lamps, and carbon Light emitted from lamps such as arc lamps, high-pressure sodium lamps, or high-pressure mercury lamps ( It is a device that heats the object to be processed by radiation (electromagnetic waves). Furthermore, the GRTA device is a high-temperature device. This is a device that performs heat treatment using gas. Examples of high-temperature gases include noble gases, or heating gases. An inert gas (such as nitrogen) that does not react with the material being treated during the process can be used.

[0358] Furthermore, after the above heat treatment, the temperature is maintained or reduced from that temperature. In the process, high-purity oxygen gas and high-purity N2O gas are introduced into the same furnace in which the above heat treatment was performed. Alternatively, an extremely dry air (an atmosphere with a dew point of -40°C or lower, preferably -60°C or lower) may be introduced. Good. In this case, it is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, etc. Furthermore, the purity of the oxygen gas or N2O gas introduced into the heating apparatus should be 6N or higher, preferably. Preferably, the impurity concentration in oxygen gas or N2O gas should be 7N or higher, i.e., 1 ppm or less. It is preferable that the concentration be 0.1 ppm or less. Oxidation occurs due to the action of oxygen gas or N2O gas. Oxygen is supplied to the material semiconductor layer 403a, and oxygen deficiency in the oxide semiconductor layer 403a occurs. Defects can be reduced.

[0359] Furthermore, separate from the above heat treatment, after forming the insulating layer 407a, under an inert gas atmosphere, Alternatively, heat treatment under an oxygen gas atmosphere (preferably 200°C to 400°C, for example 250°C) You may perform the procedure at temperatures between 350°C and 350°C.

[0360] Furthermore, after the formation of the insulating layer 402a and the oxide semiconductor layer, the source electrode or drain electrode is formed. After forming a conductive layer, after forming an insulating layer, or after heat treatment, oxygen doping treatment with oxygen plasma is performed. It is permissible to perform the following: For example, oxygen doping treatment using a high-density plasma at 2.45 GHz. It is permissible to do this. In addition, oxygen doping treatment using ion implantation or ion doping may be performed. It is permissible to do so. By performing oxygen doping, the electrical characteristics of the transistors produced will be Variations in properties can be reduced. For example, by performing oxygen doping treatment, the insulating layer 40 Either or both of 2a and the insulating layer 407a are made to have a higher oxygen content than the stoichiometric composition ratio. This makes it easier for excess oxygen in the insulating layer to be supplied to the oxide semiconductor layer 403a. Therefore, in the oxide semiconductor layer 403a, or in either the insulating layer 402a or the insulating layer 407a or Because both can reduce oxygen vacancies at the interface with the oxide semiconductor layer 403a. This allows for a further reduction in the carrier concentration of the oxide semiconductor layer 403a.

[0361] For example, one or both of the insulating layer 402a and the insulating layer 407a may contain gallium oxide. When forming an insulating layer, oxygen is supplied to the insulating layer, and the composition of gallium oxide is Ga2O x Nisu It is possible.

[0362] Furthermore, one or both of the insulating layer 402a and the insulating layer 407a may contain aluminum oxide. When forming an insulating layer, oxygen is supplied to the insulating layer, and the composition of aluminum oxide is Al2O x It can be done.

[0363] Furthermore, gallium oxide aluminum may be used as one or both of the insulating layer 402a and the insulating layer 407a. When forming an insulating layer containing aluminum or aluminum gallium oxide, oxygen is supplied to the insulating layer. The composition of gallium aluminum oxide or aluminum gallium oxide is Ga x Al 2-x O 3+α It can be done this way.

[0364] Through the above process, hydrogen, water, hydroxyl groups, or hydrides (water) are extracted from the oxide semiconductor layer 403a. This process removes impurities such as elementary compounds and supplies oxygen to the oxide semiconductor layer 403a. This allows for higher purity of the oxide semiconductor layer.

[0365] Although Figure 5(A) shows an example of a transistor fabrication method, it is not limited to this, for example... In each component shown in Figures 5(B) to 5(E), the names are the same as the components shown in Figure 5(A). Even if the elements are the same and at least part of their function is the same as each component shown in Figure 5(A) In this case, the explanation of the example transistor fabrication method shown in Figure 5(A) can be appropriately referenced.

[0366] As explained using Figures 5 and 6, an example of a transistor in this embodiment is a G A conductive layer that functions as a gate, an insulating layer that functions as a gate insulating layer, and A conductive layer that functions as a gate is superimposed via an insulating layer that functions as an insulating layer. And, an oxide semiconductor layer in which a channel is formed, and electrically connected to the oxide semiconductor layer, A conductive layer having the function of either a drain or a suction layer, and electrically connected to an oxide semiconductor layer. The structure includes a conductive layer that functions as both a source and a drain.

[0367] Furthermore, an example of a transistor in this embodiment is an oxide semiconductor layer, a source and a drain. A conductive layer having the function of one of the sources and drains, and the other function of the source and drain. In areas where a conductive layer is not provided, the insulating layer in contact with the oxide semiconductor layer is gate insulating It has a structure that is in contact with an insulating layer that functions as a border layer. By adopting the above structure, oxidation A material semiconductor layer, a conductive layer having the function of either a source or a drain, and a source and An insulating layer and gate in which a conductive layer, which functions as the other side of a drain, is in contact with an oxide semiconductor layer. Because it is surrounded by an insulating layer that functions as an insulating layer, the oxide semiconductor layer, source and dray A conductive layer having the function of one of the sources and drains, and the other function of the source and drain. This can suppress the penetration of impurities into the conductive layer.

[0368] Furthermore, the concentration of alkali metals in the oxide semiconductor layer where the channel is formed is low. Preferably. For example, if sodium is included in the oxide semiconductor layer in which the channel is formed, The concentration of sodium in the oxide semiconductor layer where the channel is formed is 5 × 10 16 / cm 3 Hereinafter, furthermore, 1×10 16 / cm 3 Hereinafter, furthermore, 1×10 15 / cm 3 or less is preferable. Also, for example, when lithium is contained in the oxide semiconductor layer in which the channel is formed, the concentration of lithium contained in the oxide semiconductor layer in which the channel is formed is 5×10 or less, furthermore, 1×10 / cm 15 or less is preferable. Also, 3 for example, when potassium is contained in the oxide semiconductor layer in which the channel is formed, the concentration of potassium contained in the oxide semiconductor layer in which the channel is formed is 5×10 15 / cm 3 or less, furthermore, is preferably 1×10 / cm 15 or less, furthermore, 3 is preferably 1×10 / cm 15 [[ID=�4]]or less. For example, when the insulating layer in contact with the oxide semiconductor layer is an oxide, sodium enters the oxide insulating layer, causing deterioration of the transistor characteristics (for example, shift of the threshold voltage, decrease in mobility, etc.). Furthermore, it also causes variations in characteristics between a plurality of transistors. Therefore, by reducing the concentration of alkali metal contained in the oxide semiconductor layer in which the channel is formed, deterioration of the transistor characteristics caused by the alkali metal can be suppressed. 3 As described above, the oxide semiconductor layer in which the channel is formed is an oxide semiconductor layer that has been purified to type I or substantially type I. By purifying the oxide semiconductor layer, the carrier concentration of the oxide semiconductor layer is made less than 1×10 / cm , preferably less than 1×1 0 / cm

[0369] As described above, the oxide semiconductor layer in which the channel is formed is an oxide semiconductor layer that has been purified to type I or substantially type I. By purifying the oxide semiconductor layer, the carrier concentration of the oxide semiconductor layer is made less than 1×10<0002 / cm / cm 14 / cm 3 less, preferably 1×1 0 12 / cm​3 Less than, more preferably 1×10 11 / cm 3 It can be made less than, and the characteristic change due to temperature change can be suppressed. Further, by adopting the above structure, the off-current per 1 μm of channel width can be made 10 aA (1×10 A) or less, more preferably the off-current per 1 μm of channel width can be made 1 aA (1×10 A) or less, still more preferably the off-current per 1 μm of channel width can be made 10 zA (1×10 -17 A) or less, still more preferably the off-current per 1 μm of channel width can be made 1 zA (1×10 A) or less, still more preferably the off-current per 1 μm of channel width can be made 100 yA (1×10 -18 A) or less. The lower the off-current of the transistor, the better. However, the lower limit of the off-current of the transistor in the present embodiment is estimated to be about 10 A / μm. -20 By using the transistor including the oxide semiconductor layer of the present embodiment in one or more of, for example, the display circuit, display selection signal output circuit, display data signal output circuit, photodetection circuit, photodetection reset signal output circuit, and output selection signal output circuit of the input / output device in the above embodiment, the reliability of the input / output device can be improved. Furthermore, an example of calculating the value of the off-current in an example of the transistor including the oxide semiconductor layer in the present embodiment using leak current measurement by a characteristic evaluation circuit will be described below. -21 The leak current measurement by the characteristic evaluation circuit will be described with reference to FIG. 7. FIG. 7 is a characteristic evaluation

[0370] -30 A / μm.

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[0372] This is a diagram illustrating the value circuit.

[0373] First, the circuit configuration of the characteristic evaluation circuit will be explained using Figure 7(A). Figure 7(A) is This is a circuit diagram showing the circuit configuration of the characteristic evaluation circuit.

[0374] The characteristic evaluation circuit shown in Figure 7(A) comprises multiple measurement systems 801. These are connected in parallel to each other. Here, as an example, eight measurement systems 801 are connected in parallel. The configuration will allow for multiple measurements to be performed simultaneously by using multiple measurement systems 801. It is possible.

[0375] The measurement system 801 consists of transistor 811, transistor 812, capacitive element 813, and It includes transistor 814 and transistor 815.

[0376] Transistors 811, 812, 814, and 81 5 is an N-type field-effect transistor.

[0377] A voltage V1 is input to either the source or drain of transistor 811, and the transistor A voltage Vext_a is input to the gate of transistor 811. Transistor 811 is charged This is a transistor that is needed.

[0378] One of the sources and drains of transistor 812 is connected to the source and drain of transistor 811. Connected to the other side of the rain, the voltage V is connected to the other side of the source and drain of transistor 812. A value of 2 is input, and the voltage Vext_b is input to the gate of transistor 812. The transistor 812 is used for evaluating leakage current. This refers to the leakage current, including the transistor's off-current.

[0379] The first capacitive electrode of the capacitive element 813 is connected to the source and drain of the transistor 811. The connection is established, and a voltage V2 is input to the second capacitive electrode of the capacitive element 813. Therefore, the voltage V2 is 0V.

[0380] A voltage V3 is input to either the source or drain of transistor 814, and the transistor The gate of transistor 814 is connected to the other side of the source and drain of transistor 811. Oh, the gate of transistor 814 and the other side of the source and drain of transistor 811, The source and drain of transistor 812, and the first electrode of capacitive element 813 The connection point is also called node A. Note that in this case, voltage V3 is 5V.

[0381] One of the sources and drains of transistor 815 is connected to the source and drain of transistor 814. The other side of the rain is connected, and the voltage V is connected to the other side of the source and drain of transistor 815. When the input is 4, the voltage Vext_c is input to the gate of transistor 815. In this case, the voltage Vext_c is 0.5V.

[0382] Furthermore, the measurement system 801 connects the source and drain of transistor 814 to the other side of the transistor The voltage at the connection point between the source and drain of the 815 is output as the output voltage Vout. To exert force.

[0383] Here, as an example of transistor 811, it includes an oxide semiconductor layer and has a channel length L=1 A transistor with a channel width of 0 μm and channel width W = 10 μm is used.

[0384] Furthermore, as an example of transistors 814 and 815, an oxide semiconductor layer is included. A transistor with a channel length L = 3 μm and a channel width W = 100 μm is used.

[0385] Furthermore, the structure of transistor 812 is shown in Figure 7(B). Figure 7(B) shows the transistor This is a schematic cross-sectional diagram showing the structure of the sta.

[0386] As shown in Figure 7(B), transistor 812 has a conductive layer 9 that functions as a gate. 01, an insulating layer 902 that functions as a gate insulating layer, and a conductive layer 902. An oxide semiconductor layer 903 provided on layer 901 and having the function of a channel-forming layer a conductive layer in contact with the oxide semiconductor layer 903, which functions as either a source or a drain. It includes a conductive layer 905 and a conductive layer 906 that functions as the other of source and drain. Furthermore, transistor 812 has an oxide semiconductor layer 903, a conductive layer 905, and a conductive layer 906 An insulating layer 907 and a planar layer 908 are laminated on top of the planar layer 908, with openings between them. The conductive layer 909 that is in contact with the conductive layer 905 and the conductive layer that is in contact with the conductive layer 906 through the opening 910 is provided, and conductive layers 905 and 906 and conductive layer 901 do not overlap, width 1 It has an offset region of μm. By providing an offset region, the parasitic capacity is reduced. Furthermore, the transistor 812 has a channel length L and a channel width W. We use six different transistor samples (also called SMPs) (see Table 1).

[0387] [Table 1]

[0388] Next, the method for fabricating transistor 812 will be explained below.

[0389] First, a glass substrate to be used as the substrate 900 is prepared, and an insulating layer 927 is formed on the substrate 900. Here, a silicon nitride film with a thickness of 100 nm is formed on the substrate 900, and the silicon nitride By forming a silicon oxidizride film with a thickness of 150 nm on the film, an insulating layer 927 It forms.

[0390] Next, a conductive layer 901 is formed on the substrate 900 via an insulating layer 927. Here, the insulating layer 901 is formed on the substrate 900 via an insulating layer 927. A layer 927 is used on the substrate 900 by sputtering to create a layer 100 nm thick. A tungsten film is formed, and a portion of the tungsten film is etched to create a conductive layer 901. It forms.

[0391] Next, an insulating layer 902 is formed on the conductive layer 901 and the insulating layer 927. Here, the conductive layer On top of layer 901 and the insulating layer 927, silicon oxide nitride with a thickness of 100 nm is applied by CVD. An insulating layer 902 is formed by creating a film.

[0392] Next, an oxide semiconductor layer 903 is formed on the conductive layer 901 via the insulating layer 902. Then, an oxide semiconductor is formed on the conductive layer 901 via the insulating layer 902 by sputtering. A layer is formed, and a portion of the oxide semiconductor layer is etched to form an oxide semiconductor layer 903 This forms the oxide semiconductor layer. Using a 1:1:2 [mol] metal oxide target, with a substrate temperature of 200°C, spat The pressure inside the chamber in the sputtering apparatus is set to 0.6 Pa, and in the sputtering apparatus The DC power supply is set to 5kV, and the film deposition atmosphere is a mixed atmosphere of oxygen and argon (oxygen flow rate 50s). The above oxide semiconductor layer is formed at ccm and an argon flow rate of 50 sccm.

[0393] Next, heat treatment was performed at 450°C for 1 hour in a mixed atmosphere of nitrogen and oxygen (80% nitrogen, 20% oxygen). Perform the process.

[0394] Next, a portion of the insulating layer 902 is etched to form an opening that penetrates the conductive layer 901.

[0395] Next, conductive layers 905 and 906 are formed on the oxide semiconductor layer 903. By sputtering, a 100 nm thick titanium film is applied to the oxide semiconductor layer 903. Form a titanium film, and then form an aluminum film with a thickness of 200 nm on the titanium film. A titanium film with a thickness of 100 nm is formed on an aluminum film, and the titanium film, aluminum film, and titanium film are used. Conductive layers 905 and 906 are formed by etching a portion of the stacked tan film. ru.

[0396] Next, the material is subjected to heat treatment at 300°C for 1 hour under a nitrogen atmosphere.

[0397] Next, on the insulating layer 902, the oxide semiconductor layer 903, the conductive layer 905, and the conductive layer 906, An insulating layer 907 is formed. Here, an insulating layer 902, an oxide semiconductor layer 903, and a conductive layer 90 5. By forming a silicon oxide film with a thickness of 300 nm on the conductive layer 906. An insulating layer 907 is formed.

[0398] Next, by etching a portion of the insulating layer 907, an opening is created that penetrates the conductive layer 905. And an opening is formed that penetrates the conductive layer 906.

[0399] Next, a planarization layer 908 is formed on the insulating layer 907. Here, a thickness of 1.5 μm is formed. A planarization layer 908 is formed by applying an acrylic layer and exposing a portion of the acrylic layer to light. .

[0400] Furthermore, a heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere.

[0401] Next, on the planarized layer 908, a conductive layer 909 and a conductive layer 906 are placed in contact with the conductive layer 905. A conductive layer 910 is formed. Here, by sputtering, on the planarization layer 908 A titanium film with a thickness of 200 nm is formed, and a portion of the titanium film is etched by A conductive layer 909 and a conductive layer 910 are formed.

[0402] Next, a heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. This completes the construction of transistor 812. This is the manufacturing method.

[0403] As shown in Figure 7(A), a transistor for charge injection and a transistor for leakage current evaluation By providing separate transistors for the leakage current evaluation during charge injection, the transistor for leakage current evaluation is always... It can be kept in the off state.

[0404] Furthermore, separate transistors are provided for charge injection and leakage current evaluation. This allows each transistor to be made to an appropriate size. Also, leakage The channel width W of the current evaluation transistor is different from the channel width W of the charge injection transistor. By increasing the size, the characteristics of the transistor used for leakage current evaluation other than leakage current can be evaluated. The leakage current component of the circuit can be made relatively small. As a result, for leakage current evaluation It is possible to measure the leakage current of a transistor with high precision. At the same time, during charge injection... Since it is not necessary to turn on the transistor used for leakage current evaluation, leakage current evaluation A portion of the charge in the channel formation region of the transistor flows into node A. There is no influence from voltage fluctuations at A.

[0405] Next, regarding the leakage current measurement method for the characteristic evaluation circuit shown in Figure 7(A), we will use Figure 7(C). Let me explain. Figure 7(C) shows the leakage current measurement method using the characteristic evaluation circuit shown in Figure 7(A). This is a timing chart to explain [the situation].

[0406] The leakage current measurement method using the characteristic evaluation circuit shown in Figure 7(A) is for the writing period and the retention period. It can be divided into two parts. The actions during each period are described below.

[0407] During the writing period, the voltage Vext_b is set so that transistor 812 is in the OFF state. Input a voltage VL (-3V). Also, input the writing voltage Vw as voltage V1. Furthermore, the voltage Vext_a is a voltage that keeps transistor 811 ON for a certain period of time. Input VH (5V). This causes charge to accumulate at node A, and the voltage at node A is The writing voltage Vw will be equal to the value of the transistor. Then, the voltage Vext_a will be used as the transistor. Input a voltage VL such that 811 is turned off. Then, set the voltage VS as voltage V1. Input S (0V).

[0408] Furthermore, during the holding period, the voltage of node A is affected by the change in the amount of charge held by node A. The change in voltage is measured. From the change in voltage, the source electrode and drain of transistor 812 are measured. The value of the current flowing between the electrode can be calculated. Therefore, the charge accumulation at node A can be determined. This allows for the measurement of the change in voltage at node A.

[0409] At this time, the accumulation of charge at node A and the change in voltage at node A are measured (accumulation and measurement operation). (Also known as) is repeated. First, the first accumulation and measurement operation is repeated 15 times. During the accumulation and measurement operation, a voltage of 5V is input as the write voltage Vw during the write period. The data is held for one hour during the retention period. Next, the second accumulation and measurement operation is repeated twice. In the storage and measurement operation of step 2, a voltage of 3.5V is applied as the write voltage Vw during the write period. Then, hold the data for 50 hours during the holding period. Next, perform the third accumulation and measurement operation once. In the storage and measurement operation of step 3, a voltage of 4.5V is applied as the write voltage Vw during the write period. The system is then subjected to a 10-hour holding period. By repeatedly performing the accumulation and measurement operations, This allows us to confirm that the measured current value is the value under steady-state conditions. And the current I flowing through node A A Of these, transient current (decreases over time from the start of measurement) This allows for the removal of the current component (which is being removed). As a result, leakage current can be measured with higher accuracy. It is possible.

[0410] Generally, the voltage V at node A A It can be expressed as a function of the output voltage Vout as follows: .

[0411]

number

[0412] Also, the charge Q at node A. A The voltage V at node A is A Capacity C connected to node A A , fixed Using a constant (const), it can be expressed as follows:

[0413]

number

[0414] Here, capacity C is connected to node A. A This refers to the capacitance of the capacitive element 813 and the capacitance of elements other than the capacitive element 813. It is the sum of the volume components.

[0415] Current I at node A A This is when the charge flows into node A (or out of node A). Since it is an intermediate derivative, the current I at node A A It can be expressed as follows:

[0416]

number

[0417] For this example, let's assume Δt is approximately 54,000 seconds. Thus, node A Capacity C connected to A Then, from the output voltage Vout, the leakage current at node A, I, is calculated. A Since this can be determined, the leakage current of the characteristic evaluation circuit can be determined.

[0418] Next, the measurement results of the output voltage obtained by the measurement method using the above characteristic evaluation circuit and the results of said measurement The calculated leakage current value of the characteristic evaluation circuit will be explained using Figure 8.

[0419] Figure 8(A) shows, as an example, the transistors in SMP4, SMP5, and SMP6. The elapsed time Time related to the above measurement (first accumulation and measurement operation) and the output voltage Vout The relationship is shown in Figure 8(B), which shows the elapsed time (Time) related to the above measurement and the value calculated by the measurement. Current I A This shows the relationship. The output voltage Vout has been fluctuating since the start of measurement, and the steady state It appears that it takes more than 10 hours to reach that state.

[0420] Furthermore, Figure 9 shows the values ​​estimated from the measurements obtained above for SMP1 to SMP6. The relationship between the voltage and leakage current at node A is shown. In Figure 9, for example, in SMP4, When the voltage at A is 3.0V, the leakage current is 28yA / μm. Since the off-current of transistor 812 is also included, the off-current of transistor 812 is also 28yA / It can be considered to be less than or equal to a micrometer (μm).

[0421] Furthermore, Figures 10, 11, and 12 show the above measurements at 85°C, 125°C, and 150°C. Relationship between voltage and leakage current at node A in SMP1 to SMP6, as estimated by the standard. This is shown. As shown in Figures 10 to 12, even at 150°C, the leakage current is 1 It can be seen that it is less than 00 zA / μm.

[0422] As described above, it contains a highly purified oxide semiconductor layer that functions as a channel-forming layer. In a characteristic evaluation circuit using a transistor, the leakage current is sufficiently low, It can be seen that the off-current of the transistor is sufficiently small. Also, the off-current of the above transistor is This shows that the temperature remains sufficiently low even when it rises.

[0423] (Embodiment 6) This embodiment describes an example of the structure of the input / output device in the above embodiment.

[0424] The input / output device in this embodiment is a first that is provided with semiconductor elements such as transistors. A substrate (active matrix substrate), a second substrate, and between the first substrate and the second substrate. Includes a provided liquid crystal layer.

[0425] First, regarding an example of the structure of the active matrix substrate in the input / output device of this embodiment, This will be explained using Figures 13 and 14. Figures 13 and 14 show the input / output device of this embodiment. This figure shows an example of the structure of an active matrix substrate, and Figure 13(A) is a schematic plan view. Therefore, Figure 13(B) is a schematic cross-sectional view of line segment AB in Figure 13(A), and Figure 14 (A) is a schematic plan view, and Figure 14(B) is a cross-section of line segment CD in Figure 14(A). This is a schematic diagram. Note that Figure 14 shows an example of a light detection circuit with the configuration shown in Figure 1(B). This example shows a case using a detection circuit, and as an example, two photoelectric conversion elements and two charge storage control transistors. The amplifier transistor and output selection transistor are shown. Also, Figures 13 and 1 In section 4, we will use a transistor with the structure described in Figure 5(A) as an example of a transistor. This indicates the case where it exists.

[0426] The active matrix substrate shown in Figures 13 and 14 comprises a substrate 500 and a conductive layer 501a. A conductive layer 501k, an insulating layer 502, semiconductor layers 503a to 503e, and a conductive layer Layer 504a to conductive layer 504n, insulating layer 505, semiconductor layer 506a, and semiconductor layer 50 6b, semiconductor layer 507a, semiconductor layer 507b, semiconductor layer 508a, semiconductor layer 50 It includes 8b, an insulating layer 509, and conductive layers 510a to 510c.

[0427] Each of the conductive layers 501a to 501k is provided on one plane of the substrate 500.

[0428] The conductive layer 501a functions as the gate of the display selection transistor in the display circuit. ru.

[0429] The conductive layer 501b functions as the first capacitive electrode of the retaining capacitance in the display circuit. Furthermore, the layer that functions as the first capacitive electrode of the capacitive element (holding capacitance) is referred to as the first capacitive electrode. It is also said that.

[0430] The conductive layer 501c functions as a wiring to which the first photodetection reset signal is input. Furthermore, layers that function as wiring are also called wiring.

[0431] The conductive layer 501d functions as a wiring to which a second photodetection reset signal is input.

[0432] The conductive layer 501e serves as the gate of the first charge storage control transistor in the photodetector circuit. It has a function.

[0433] The conductive layer 501f serves as the gate of the second charge storage control transistor in the photodetector circuit. It has a function.

[0434] The conductive layer 501g functions as a signal line to which the first charge accumulation control signal is input. Layers that function as signal lines are also called signal lines.

[0435] The conductive layer 501h functions as a signal line to which a second charge storage control signal is input.

[0436] The conductive layer 501i functions as the gate of the output selection transistor in the photodetector circuit. do.

[0437] The conductive layer 501j functions as the gate of the amplification transistor in the photodetector circuit. .

[0438] The conductive layer 501k functions as a wiring to which the voltage V0 is input.

[0439] The insulating layer 502 is provided on one plane of the substrate 500 via conductive layers 501a to 501k. It is possible.

[0440] The insulating layer 502 is the gate insulating layer of the display selection transistor in the display circuit, and in the display circuit The dielectric layer with a retaining capacitance, and each of the X charge storage control transistors in the photodetector circuit The gate insulating layer, the gate insulating layer of the amplification transistor in the photodetector circuit, and the photodetector It functions as a gate insulating layer for the output selection transistor in the circuit.

[0441] The semiconductor layer 503a is superimposed on the conductive layer 501a via the insulating layer 502. 'a' functions as a channel formation layer for the display selection transistor in the display circuit.

[0442] The semiconductor layer 503b is superimposed on the conductive layer 501d via the insulating layer 502. b is a channel formation layer for the first charge storage control transistor in the photodetector circuit. To have the ability.

[0443] The semiconductor layer 503c is superimposed on the conductive layer 501f via the insulating layer 502. c is a channel formation layer for the second charge storage control transistor in the photodetector circuit. To have the ability.

[0444] The semiconductor layer 503d is superimposed on the conductive layer 501i via the insulating layer 502. d functions as a channel formation layer for the output selection transistor in the photodetector circuit. .

[0445] The semiconductor layer 503e is superimposed on the conductive layer 501j via the insulating layer 502. j functions as a channel formation layer for the amplification transistor in the photodetector circuit.

[0446] The conductive layer 504a is electrically connected to the semiconductor layer 503a. The conductive layer 504a is displayed It functions as either the source or the drain of the indicator selection transistor in the circuit.

[0447] The conductive layer 504b is electrically connected to the conductive layer 501b and the semiconductor layer 503a. 504b is the other of the source and drain of the display selection transistor in the display circuit. It has a function.

[0448] The conductive layer 504c is superimposed on the conductive layer 501b via the insulating layer 502. The conductive layer 504c It functions as a second capacitance electrode for the holding capacitance in the display circuit.

[0449] The conductive layer 504d is electrically in contact with the conductive layer 501c at an opening that penetrates the insulating layer 502. The conductive layer 504d is the first current terminal of the first photoelectric conversion element in the photodetector circuit. It also functions as one of the second current terminals.

[0450] The conductive layer 504e is electrically in contact with the conductive layer 501d at an opening that penetrates the insulating layer 502. The conductive layer 504e is the first current terminal of the second photoelectric conversion element in the photodetector circuit. It also functions as one of the second current terminals.

[0451] The conductive layer 504f is electrically connected to the semiconductor layer 503b. The conductive layer 504f is used for light detection. Function as one of the source and drain of the first charge storage control transistor in the circuit. It holds.

[0452] The conductive layer 504g is electrically connected to the semiconductor layer 503c. The conductive layer 504g is used for light detection. Functioning as either the source or drain of the second charge storage control transistor in the circuit. It holds.

[0453] The conductive layer 504h penetrates the insulating layer 502 through the openings of the conductive layer 501e and the conductive layer 5 It is electrically connected to 01g. The conductive layer 504h receives the first charge storage control signal. It functions as a signal line.

[0454] The conductive layer 504i penetrates the insulating layer 502 through an opening where it connects the conductive layer 501f and the conductive layer 5 It is electrically connected to 01h. The conductive layer 504i receives the second charge storage control signal. It functions as a signal line.

[0455] The conductive layer 504j is electrically connected to the semiconductor layer 503b and the semiconductor layer 503c, and is also insulating. The conductive layer 501j is electrically connected at the opening that penetrates the edge layer 502. 4j is a first charge storage control transistor and a second charge storage control transistor in the photodetector circuit. It functions as both the source and the other drain of a transistor.

[0456] The conductive layer 504k is electrically connected to the semiconductor layer 503d. The conductive layer 504k is used for light detection. It functions as either the source or the drain of an output selection transistor in a circuit.

[0457] The conductive layer 504l is electrically connected to the semiconductor layer 503d and the semiconductor layer 503e. Layer 504l is the source and drain of the output selection transistor in the photodetector circuit. Furthermore, the function of an amplifying transistor as either the source or the drain in a photodetector circuit. To possess.

[0458] The conductive layer 504m is electrically connected to the semiconductor layer 503e and has an opening that penetrates the insulating layer 502. In this part, it is electrically connected to the conductive layer 501k. The conductive layer 504m is in the photodetector circuit. It functions as both the source and the other drain of an amplifying transistor.

[0459] The conductive layer 504n is electrically in contact with the conductive layer 501k at an opening that penetrates the insulating layer 502. The conductive layer 504n functions as a wire to which voltage V0 is input.

[0460] The insulating layer 505 is connected to the semiconductor layer 503a to the semiconductor layer 504k via the conductive layer 504a to the conductive layer 504k. It is in contact with layer 503d.

[0461] The semiconductor layer 506a has an opening that penetrates the insulating layer 505, through which the conductive layer 504d It is electrically connected to it.

[0462] The semiconductor layer 506b has an opening that penetrates the insulating layer 505, through which the conductive layer 504e It is electrically connected to it.

[0463] The semiconductor layer 507a is in contact with the semiconductor layer 506a.

[0464] The semiconductor layer 507b is in contact with the semiconductor layer 506b.

[0465] The semiconductor layer 508a is in contact with the semiconductor layer 507a.

[0466] Semiconductor layer 508b is in contact with semiconductor layer 507b.

[0467] The insulating layer 509 consists of insulating layer 505, semiconductor layer 506a, semiconductor layer 506b, and semiconductor layer 507. a, superimposed on semiconductor layer 507b, semiconductor layer 508a, and semiconductor layer 508b. Insulating layer 5 09 functions as a planar insulating layer in the display circuit and the light detection circuit. It is not necessary to provide the insulating layer 509.

[0468] The conductive layer 510a has an opening that penetrates the insulating layer 505 and the insulating layer 509, and the conductive layer 50 It is electrically connected to 4b. Also, the conductive layer 510a is superimposed on the conductive layer 501a. This prevents light leakage. The conductive layer 510a is a display element in the display circuit. It functions as a pixel electrode. Furthermore, the layer that functions as a pixel electrode is called the pixel electrode. Also said.

[0469] The conductive layer 510b has an opening that penetrates the insulating layer 505 and the insulating layer 509, and the conductive layer 50 A semiconductor is electrically connected to 4f and has an opening that penetrates the insulating layer 505 and the insulating layer 509. It is electrically connected to body layer 508a.

[0470] The conductive layer 510c has an opening that penetrates the insulating layer 505 and the insulating layer 509, and the conductive layer 50 A semiconductor is electrically connected to 4g and has an opening that penetrates the insulating layer 505 and the insulating layer 509. It is electrically connected to body layer 508b.

[0471] Furthermore, an example of the structure of the input / output device in this embodiment is shown using Figures 15 and 16. Let me explain. Figures 15 and 16 use the active matrix substrate shown in Figures 13 and 14. This is a diagram showing an example of the structure of an input / output device, and Figure 15(A) is a schematic plan view, and Figure 15( Figure B) is a schematic cross-sectional view of line segment AB in Figure 15(A), and Figure 16(A) is a plan view. This is a diagram, and Figure 16(B) is a schematic cross-sectional view of the line segment CD in Figure 16(A). For example, the photoelectric conversion element is a photodiode, and the display element is a liquid crystal element.

[0472] The input / output devices shown in Figures 15 and 16 are based on the active matrix base shown in Figures 13 and 14. In addition to the board, there is a substrate 512, a light-shielding layer 513, an insulating layer 516, a conductive layer 517, and a liquid crystal layer 5 Includes 18 and . Note that in Figures 15(A) and 16(A), for convenience, conductive layer 517 Omit it.

[0473] The light-shielding layer 513 is provided on a part of one plane of the substrate 512. For example, the light-shielding layer 513 is photoelectric It is provided on one plane of the substrate 512, excluding the portion where the conversion element is formed.

[0474] The insulating layer 516 is provided on one plane of the substrate 512 via the light-shielding layer 513.

[0475] The conductive layer 517 is provided on one plane of the substrate 512. The conductive layer 517 is in the display circuit It functions as a common electrode. Note that in the photodetection circuit, the conductive layer 517 is not necessarily provided. It's okay if you don't get kicked.

[0476] The liquid crystal layer 518 is provided between the conductive layer 510a and the conductive layer 517, and is connected via the insulating layer 509. It is then superimposed on the semiconductor layer 508.

[0477] The conductive layer 510a, the liquid crystal layer 518, and the conductive layer 517 are display elements in the display circuit. It functions as such.

[0478] Furthermore, the various components of the input / output device shown in Figures 15 and 16 will be described.

[0479] Substrates 500 and 512 are substrates applicable to substrate 400a in Figure 5(A). You can use it.

[0480] The conductive layers 501a to 501k are applied to the conductive layer 401a in Figure 5(A). A layer of the applicable material can be used. In addition, a layer of the applicable material can be added to the conductive layer 401a. The conductive layers 501a to 501k may be formed by layering them.

[0481] As the insulating layer 502, a layer of material applicable to the insulating layer 402a in Figure 5(A) is used. It is possible to laminate an insulating layer 402a with a layer of an applicable material to create an insulating layer 502. It may be structured as is.

[0482] The semiconductor layers 503a to 503e are the oxide semiconductor layers 40 shown in Figure 5(A). A layer of material applicable to 3a can be used.

[0483] The conductive layers 504a to 504n are the conductive layer 405a in Figure 5(A) or the conductive layer 504n. A layer of material applicable to the electrical layer 406a can be used. Alternatively, a conductive layer 405a or a conductive layer can be used. A layer of a material applicable to the conductive layer 406a is laminated to form conductive layers 504a to 504n. You may do so.

[0484] As the insulating layer 505, a layer of material applicable to the insulating layer 407a in Figure 5(A) is used. It is possible to do so. In addition, an insulating layer 505 can be formed by laminating an applicable layer onto the insulating layer 407a. That's fine.

[0485] Semiconductor layer 506a and semiconductor layer 506b are single-conductivity semiconductor layers (either P-type or N-type). The semiconductor layer 506a and semiconductor layer 506b are, for example, semiconductors containing silicon. A conductive layer can be used.

[0486] Semiconductor layer 507a and semiconductor layer 507b are semiconductor layers with higher resistance than semiconductor layer 506. For example, semiconductor layers 507a and 507b may be semiconductors containing silicon. Layers can be used.

[0487] Semiconductor layer 508a and semiconductor layer 508b have different conductivity types (P-type and This is the other type of semiconductor layer (of type N). For example, semiconductor layers 508a and 508b are... A semiconductor layer containing silicon can be used.

[0488] For example, the insulating layer 509 and insulating layer 516 can be made of polyimide, acrylic, benzocyclob A layer of organic material such as tene can be used. Furthermore, as the insulating layer 509, a low dielectric constant can be used. Layers of material (also called low-k material) can also be used.

[0489] The conductive layers 510 to 510c and the conductive layer 517 may be, for example, transparent conductive materials. A layer of electrical material can be used, and a transparent conductive material such as indium tin can be used. Oxides, metal oxides (IZO: indium zi) are a mixture of indium oxide and zinc oxide. (Also known as nc oxide), a conductive material made by mixing indium oxide with silicon oxide (SiO2). Indium oxides containing organic indium, organotin, tungsten oxide, and tungsten oxide. Indium zinc oxide containing stainless steel, indium oxide containing titanium oxide, or titanium oxide Indium tin oxide containing nitrile can be used.

[0490] Furthermore, a conductive composition containing a conductive polymer (also called a conductive polymer) is used to create a conductive layer 51 It is also possible to form conductive layers 0a to 510c and conductive layer 517. Using a conductive composition The conductive layer formed by this process has a sheet resistance of 10,000 Ω / □ or less and is transparent at a wavelength of 550 nm. It is preferable that the photometricity is 70% or higher. Also, the conductive polymer contained in the conductive composition The resistivity is preferably 0.1 Ω·cm or less.

[0491] As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. Examples of conjugated conductive polymers include polyaniline or its derivatives, and polypyrrole. or derivatives thereof, polythiophene or derivatives thereof, or aniline, pyrrole and Examples include copolymers of two or more thiophenes or derivatives thereof.

[0492] Furthermore, conductive layers 510a to 510c and conductive layer 517 are formed using graphene. It is also possible.

[0493] For example, a layer of metal material can be used as the light-shielding layer 513.

[0494] Examples of liquid crystal layer 518 include TN LCD, OCB LCD, STN LCD, VA LCD, and ECB type. Using a layer containing liquid crystal, GH liquid crystal, polymer-dispersed liquid crystal, or discotic liquid crystal. This can be done. Furthermore, the liquid crystal layer 518 is the electrical charge applied to the conductive layer 510c and the conductive layer 517. It is preferable to use a liquid crystal that transmits light when the pressure is 0V.

[0495] As explained with reference to Figures 13 to 16, the structure of the input / output device in this embodiment is an example. an active matrix substrate including transistors, pixel electrodes, and photoelectric conversion elements, and opposite A structure including a substrate and a liquid crystal layer having liquid crystal between an active matrix substrate and a counter substrate. This is the structure. By adopting the above structure, the display circuit and light detection circuit are mounted on the same substrate using the same process. Because circuits can be fabricated, manufacturing costs can be reduced.

[0496] Furthermore, as explained with reference to Figures 13 to 16, the configuration of the input / output device in this embodiment The example shows a structure in which a light-shielding layer is provided except for the part that transmits light. This suppresses the incidence of light on transistors provided on an active matrix substrate, for example. Because it can be controlled, the electrical characteristics of a transistor (e.g., threshold voltage) can be controlled by light. It is possible to suppress fluctuations.

[0497] Furthermore, in the input / output device of this embodiment, the display circuit and the light detection circuit are on the same board. A display drive circuit and a light detection drive circuit may be provided. In this case, the display drive circuit The structure of transistors in circuits such as the light detection drive circuit is used in the display circuit and the light detection circuit. It may be the same as the structure of a transistor.

[0498] (Embodiment 7) This embodiment describes an example of an electronic device equipped with the input / output device described above. I will reveal it.

[0499] An example of the configuration of the electronic device in this embodiment is shown using Figures 17(A) to 17(D). Let me explain. Figures 17(A) to 17(D) show examples of the configuration of electronic equipment in this embodiment. This is a schematic diagram to explain [the concept].

[0500] The electronic device shown in Figure 17(A) is an example of a portable information terminal. The end comprises a housing 1001a and a display unit 1002a provided on the housing 1001a. .

[0501] Furthermore, the side 1003a of the housing 1001a has connection terminals for connecting to external devices, and the figure One or more buttons for operating the portable information terminal shown in 17(A) may be provided. .

[0502] The portable information terminal shown in Figure 17(A) has a CPU and main memory inside the casing 1001a. This includes an interface for sending and receiving signals between external devices and the CPU and main memory, and It is equipped with an antenna for transmitting and receiving signals with the equipment. Furthermore, inside the housing 1001a, One or more integrated circuits with specific functions may be provided.

[0503] The portable information terminals shown in Figure 17(A) include, for example, telephones, e-readers, and personal computers. It has the function of a game machine, and one or more game machines.

[0504] The electronic device shown in Figure 17(B) is an example of a foldable portable information terminal. The portable information terminal shown comprises a housing 1001b and a display unit 100 provided on the housing 1001b. 2b, housing 1004, display unit 1005 provided in housing 1004, and housing 1001b The system also includes a shaft portion 1006 for connecting the housing 1004.

[0505] Furthermore, in the portable information terminal shown in Figure 17(B), the shaft portion 1006 connects to the housing 1001b or By moving the enclosure 1004, the enclosure 1001b can be superimposed on the enclosure 1004. Cut.

[0506] Furthermore, external devices can be connected to the side 1003b of the housing 1001b or the side 1007 of the housing 1004. Connection terminals for connecting, and buttons for operating the portable information terminal shown in Figure 17(B) You may provide one or more of these.

[0507] Furthermore, the display unit 1002b and the display unit 1005 may display different images or a continuous image. It may be shown. Note that the display unit 1005 does not necessarily have to be provided, and the display unit 1005 Alternatively, a keyboard, which serves as an input device, may be provided.

[0508] The portable information terminal shown in Figure 17(B) has a CPU inside either the casing 1001b or the casing 1004. And, the main memory, and the interface that transmits and receives signals between external devices, the CPU and the main memory. - It has a face and, in addition, a specific function is provided within housing 1001b or housing 1004. One or more integrated circuits may be provided. Also, the portable information terminal shown in Figure 17(B) An antenna for transmitting and receiving signals to and from the outside may be provided.

[0509] The portable information terminals shown in Figure 17(B) include, for example, telephones, e-readers, and personal computers. It has the function of a game machine, and one or more game machines.

[0510] The electronic device shown in Figure 17(C) is an example of a stationary information terminal. The information terminal comprises a housing 1001c and a display unit 1002c provided on the housing 1001c. To prepare.

[0511] The display unit 1002c can also be provided on the deck portion 1008 of the housing 1001c. ru.

[0512] Furthermore, the stationary information terminal shown in Figure 17(C) has a CPU and a main unit inside the enclosure 1001c. Memory and an interface for sending and receiving signals between external devices, the CPU, and main memory. The enclosure 1001c contains one or more integrated circuits having specific functions. You may install several of them. Also, the stationary information terminal shown in Figure 17(C) can send and receive signals with the outside. An antenna may be provided for this purpose.

[0513] Furthermore, in the stationary information terminal shown in Figure 17(C), on the side 1003c of the housing 1001c The device may be provided with one or more ticket output units for printing tickets, coin slots, and banknote insertion units. .

[0514] The stationary information terminal shown in Figure 17(C) is, for example, an ATM or ticket machine. It functions as an information and communication terminal (also called a multimedia station) or as a gaming machine. It holds.

[0515] Figure 17(D) shows an example of a stationary information terminal. The stationary information terminal shown in Figure 17(D) is housed in a casing. It comprises a body 1001d and a display unit 1002d provided on the housing 1001d. A support base may be provided to support the housing 1001d.

[0516] Furthermore, the side 1003d of the housing 1001d has connection terminals for connecting to external devices, and the figure One or more buttons for operating the stationary information terminal shown in 17(D) may be provided. .

[0517] Furthermore, the stationary information terminal shown in Figure 17(D) has a CPU and a main unit inside the enclosure 1001d. Memory and an interface for sending and receiving signals between external devices, the CPU, and main memory. It may also include one integrated circuit having a specific function within the housing 1001d. Alternatively, multiple units may be provided. In addition, the stationary information terminal shown in Figure 17(D) can transmit signals to the outside. An antenna for receiving signals may be provided.

[0518] The stationary information terminal shown in Figure 17(D) is, for example, a digital photo frame, an input / output monitor, Alternatively, it may function as a television device.

[0519] The input / output device of the above embodiment can be used, for example, as a display unit for an electronic device, as shown in Figure 17. (A) to Figure 17(D) are used as display units 1002a to 1002d. Furthermore, the input / output device of the above embodiment is used as the display unit 1005 shown in Figure 17(B). That's good too.

[0520] As explained with reference to Figure 17, an example of the electronic device in this embodiment is the above-described embodiment The configuration includes an input / output section that uses an input / output device in the state. This allows, for example, the use of a finger or pen to operate an electronic device or input information into an electronic device. It is possible.

[0521] Furthermore, in an example of the electronic device in this embodiment, the housing is powered according to the incident illuminance. The system includes one or more of the following: a photoelectric conversion unit that generates pressure, and an operating unit that operates the input / output device. It is also possible to do so. For example, by providing a photoelectric conversion unit, an external power supply becomes unnecessary, so an external power supply is not required. The above electronic devices can be used for extended periods even in locations without a power source. [Explanation of Symbols]

[0522] 101a Display circuit control unit 101b Photodetection circuit control unit 101c Light source section 101d Pixel section 111 Display drive circuit 112 Display data signal output circuit 113 Light detection drive circuit 114 Light Unit 115d display circuit 115p light detection circuit 116 Readout Circuit 131 Photoelectric conversion element 132 transistors 133 transistors 134 transistors 135 transistors 161a Transistor 161b Transistor 162a Liquid crystal element 162b Liquid crystal element 163a Capacitive element 163b Capacitive element 164 Capacitive elements 165 transistors 166 transistors 400a substrate 400b circuit board 400c circuit board 401a Conductive layer 401b Conductive layer 401c conductive layer 402a Insulating layer 402b Insulating layer 402c insulating layer 403a Oxide Semiconductor Layer 403b oxide semiconductor layer 403c oxide semiconductor layer 405a conductive layer 405b conductive layer 405c conductive layer 406a conductive layer 406b Conductive layer 406c conductive layer 407a Insulating layer 407b Insulating layer 408a conductive layer 408b Conductive layer 447 Insulating layer 500 circuit boards 501a conductive layer 501b conductive layer 501c conductive layer 501d conductive layer 501e conductive layer 501f conductive layer 501g conductive layer 501h conductive layer 501i conductive layer 501j conductive layer 501k conductive layer 502 Insulating layer 503a Semiconductor layer 503b Semiconductor layer 503c semiconductor layer 503d semiconductor layer 503e semiconductor layer 503j semiconductor layer 504a conductive layer 504b conductive layer 504c conductive layer 504d conductive layer 504e conductive layer 504f conductive layer 504g conductive layer 504h conductive layer 504i conductive layer 504j conductive layer 504k conductive layer 504l conductive layer 504m conductive layer 504n conductive layer 505 Insulating layer 506 Semiconductor layer 506a Semiconductor layer 506b Semiconductor layer 507a Semiconductor layer 507b Semiconductor layer 508 Semiconductor layer 508a Semiconductor layer 508b Semiconductor layer 509 Insulating layer 510 Conductive layer 510a conductive layer 510b Conductive layer 510c conductive layer 512 circuit boards 513 Light blocking layer 516 Insulating layer 517 Conductive layer 518 Liquid crystal layer 600 circuit boards 602 Underlayment Insulation Layer 606 oxide semiconductor layer 608 Gate Insulation Layer 610 Guard Station 614 Electrode 616 Interlayer insulating layer 618 Wiring 620 Protective film 701 Underlayment Insulation Layer 702 Insulators 703a Semiconductor Domain 703b Semiconductor Domain 703c Semiconductor Domain 704 Gate Insulation Layer 705 Gate 706a Sidewall insulation 706b Sidewall insulation 707 Insulators 708a Source electrode 708b Drain electrode 750 circuit boards 752 Underlayment insulation layer 754 Protective insulating layer 756 Oxide Semiconductor Layer 756a High resistance area 756b Low resistance region 758 Gate Insulation Layer 760 Gate 762 Sidewall insulation 764 Electrode 766 Interlayer insulating layer 768 Wiring 801 Measurement System 811 Transistors 812 transistors 813 Capacitive element 814 Transistors 815 Transistors 900 circuit boards 901 Conductive layer 902 Insulating layer 903 Oxide semiconductor layer 905 Conductive layer 906 Conductive layer 907 Insulating layer 908 Planarization layer 909 Conductive layer 910 Conductive layer 927 Insulating layer 1001a Enclosure 1001b enclosure 1001c enclosure 1001d enclosure 1002a Display section 1002b Display section 1002c Display section 1002d Display section 1003a side 1003b Side 1003c side 1003d side 1004 cabinet 1005 Display section 1006 Shaft 1007 Side view 1008 Deck section

Claims

1. It comprises first to sixth transistors, first to third photodiodes, a first insulating layer, a second insulating layer, and a light-shielding layer. Either the source or the drain of the first transistor is electrically connected to the cathode of the first photodiode. The anode of the first photodiode is electrically connected to the first conductive layer. The first conductive layer is electrically connected to the second conductive layer. The source or drain of the first transistor, the other of which is electrically connected to the third conductive layer, The source or drain of the first transistor is electrically connected to the gate of the fourth transistor and to either the source or drain of the sixth transistor. The source or drain of the second transistor, the other of which is electrically connected to the cathode of the second photodiode, Either the source or drain of the third transistor is electrically connected to the cathode of the third photodiode. The anode of the third photodiode is electrically connected to the fourth conductive layer. The fourth conductive layer is electrically connected to the fifth conductive layer. The source or drain of the third transistor, the other of which is electrically connected to the third conductive layer, Either the source or drain of the fourth transistor is electrically connected to either the source or drain of the fifth transistor. The source or drain of the fourth transistor, the other of which is electrically connected to the sixth conductive layer, The sixth conductive layer is electrically connected to the seventh conductive layer. A data signal is output from the other of the source or drain of the fifth transistor. In a plan view, the direction in which the first conductive layer extends intersects with the direction in which the third conductive layer extends. In a plan view, the direction in which the third conductive layer extends intersects with the direction in which the fourth conductive layer extends. The first conductive layer and the second conductive layer are electrically connected via the first contact hole. The fourth conductive layer and the fifth conductive layer are electrically connected via the second contact hole. In a cross-sectional view, the light-shielding layer is provided via the first insulating layer in the region overlapping with the first to third photodiodes and in the region not overlapping with them. The input / output device wherein the second insulating layer has a region that covers the sides of the first to third photodiodes.

2. In claim 1, An input / output device in which, when a first voltage is input to the other side of the sixth transistor, a reset signal is input to the gate of the sixth transistor, and the voltage at the gate of the fourth transistor is reset.

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