Semiconductor package design with terminals for connecting to an external capacitor

Abstract

To provide a semiconductor package having a contact point to achieve low parasitic inductance for connection to an external capacitor, and a manufacturing method for the semiconductor package.SOLUTION: In a circuit assembly 100A, a packaged semiconductor component 110 includes a semiconductor die including a field effect transistor, side source terminals 132A and 132B that are positioned to a first side part of the packaged semiconductor component and connected to a source of the field effect transistor, and a drain terminal 122 that is positioned to a second side part of the packaged semiconductor component and connected to a drain of the field effect transistor. The first side part is adjacent to the second side part. A capacitor 150 is electrically connected between the side source terminal and the drain terminal.SELECTED DRAWING: Figure 1A

Description

Technical Field

[0001] [Cross - Reference to Related Applications] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 550,927, filed on February 7, 2024, entitled "SEMICONDUCTOR PACKAGE DESIGN WITH CONTACTS FOR CONNECTING TO EXTERNAL CAPACITOR", the disclosure of which is hereby incorporated by reference in its entirety for all purposes.

[0002] This disclosure relates to semiconductor packages. In particular, embodiments of the present disclosure relate to semiconductor packages having contacts for achieving low parasitic inductance for connection to an external capacitor and related manufacturing methods.

Background Art

[0003] Semiconductor devices are used in a wide variety of applications. In some applications, semiconductor devices can incorporate multiple electrical components that are electrically connected to each other. Such electrical connections can introduce unwanted parasitic inductance. There can be technical problems associated with parasitic inductance, such as distortion of electrical signals between components.

Summary of the Invention

Means for Solving the Problems

[0004] The technical innovations described in the claims each have several aspects, and no single one of them alone bears the desirable attributes. Without limiting the claims, some of the prominent features of the present disclosure are briefly described here.

[0005] One aspect of the present disclosure is a circuit assembly comprising a packaged semiconductor component and a capacitor. The packaged semiconductor component includes a semiconductor die containing a field-effect transistor, a side-source terminal located on a first side of the packaged semiconductor component and connected to the source of the field-effect transistor, and a drain terminal located on a second side of the packaged semiconductor component and connected to the drain of the field-effect transistor. The capacitor is electrically connected between the source terminal and the drain terminal. The first side is adjacent to the second side. The capacitor is located outside the packaged semiconductor component and is electrically connected between the source terminal and the drain terminal.

[0006] In one embodiment, the circuit assembly further includes a printed circuit board. Packaged semiconductor components and capacitors are positioned on the printed circuit board, and the packaged semiconductor components further include a heat spreader facing the printed circuit board. In addition, side source terminals provide mechanical support points for the heat spreader.

[0007] In one embodiment, the packaged semiconductor component further includes a plurality of additional drain terminals located on a second side and connected to the drain of a field-effect transistor, and a plurality of source terminals located on a third side of the packaged semiconductor component and connected to the source of a field-effect transistor, the third side being opposite to the second side. In one embodiment, the packaged semiconductor component further includes a second side source terminal on the side opposite the first side.

[0008] In one embodiment, each of the first and second sides of the packaged semiconductor component includes a lead frame.

[0009] In one embodiment, the circuit assembly further includes a second packaged semiconductor component and a second capacitor electrically connected between the side-source terminal and the drain terminal of the second packaged semiconductor component. The second packaged semiconductor component is rotated 180 degrees relative to the packaged semiconductor component.

[0010] In one embodiment, the circuit assembly further includes a printed circuit board. The printed circuit board includes traces, and a capacitor is connected to one of the traces.

[0011] Another aspect of the present disclosure is a packaged semiconductor component. The packaged semiconductor component includes a semiconductor die comprising a field-effect transistor having a source, a gate, and a drain; a plurality of drain terminals located on a first side of the packaged semiconductor component and connected to the drain; a side-source terminal located on a second side of the packaged semiconductor component and connected to the source; and a plurality of source terminals located on a third side of the packaged semiconductor component and connected to the side-source terminal within the packaged semiconductor component. The third side is opposite the first side, and the second side is adjacent to both the first and third sides. In addition, the side-source terminals are located closer to the first side than to the third side.

[0012] In one embodiment, the packaged semiconductor component further includes a surface configured to be bonded to a printed circuit board and a heat spreader facing that surface. In addition, side source terminals provide mechanical support for the heat spreader. Furthermore, the heat spreader has notches around the side source terminals.

[0013] In one embodiment, each of the first and second sides of the packaged semiconductor component includes a lead frame. In addition, the lead frame includes a punched flat end.

[0014] In one embodiment, the gate is positioned on a third side of the packaged semiconductor component. In one embodiment, the packaged semiconductor component further includes a gate terminal positioned on a third side of the packaged semiconductor component.

[0015] Another aspect of the present disclosure is a circuit assembly comprising a packaged semiconductor component. The packaged semiconductor component comprises a semiconductor die including a field-effect transistor having a source, gate, and drain, a drain terminal connected to the drain, and a source terminal connected to the source, the drain terminal and the source terminal being on the same side of the packaged semiconductor component. The circuit assembly further comprises a capacitor located outside the packaged semiconductor component, the capacitor being electrically connected between the source terminal and the drain terminal.

[0016] In one embodiment, the circuit assembly further includes a second capacitor located outside the packaged semiconductor component, the packaged semiconductor component including a second source terminal on the same side as the drain and source terminals of the packaged semiconductor component. In addition, the second capacitor is electrically connected between the second source terminal and the drain. In one embodiment, the circuit assembly further includes a printed circuit board, and packaged semiconductor components and capacitors are positioned on the printed circuit board. In addition, the packaged semiconductor components further include a heat spreader facing the printed circuit board. In one embodiment, the packaged semiconductor component includes a gate terminal and a Kelvin source terminal on a side opposite to the same side where the drain terminal and source terminal are located. In one embodiment, the packaged semiconductor component includes a plurality of additional source terminals on a side opposite to the same side where the drain terminal and source terminal are located. In one embodiment, the packaged semiconductor component includes at least one additional drain terminal on the same side as the drain and source terminals, and the at least one additional drain terminal is electrically connected to a capacitor located outside the packaged semiconductor component.

[0017] Another aspect of the present disclosure is a circuit assembly comprising a packaged semiconductor component. The packaged semiconductor component comprises a semiconductor die comprising a field-effect transistor having a source, gate, and drain; a plurality of drain terminals located on a first side of the packaged semiconductor component and connected to the drain; a side-source terminal located on a second side of the packaged semiconductor component and connected to the source; and a plurality of source terminals located on a third side of the packaged semiconductor component and connected to the side-source terminal within the packaged semiconductor component. The first side is opposite to the second side, and the third side is perpendicular to the first and second sides. The circuit assembly further comprises a printed circuit board, where the packaged semiconductor component is positioned on the printed circuit board, and a capacitor is positioned on the printed circuit board. The capacitor is electrically connected between one of the plurality of drain terminals and the side-source terminal.

[0018] In one embodiment, the packaged semiconductor component further includes a heat spreader facing the printed circuit board. In addition, the heat spreader has notches around the side source terminals. Furthermore, the side source terminals provide mechanical support for the heat spreader.

[0019] In one embodiment, each of the first and second sides of the packaged semiconductor component includes a lead frame, the lead frame further including a punched flat end.

[0020] For the purpose of summarizing the present disclosure, certain aspects of the technological innovation, advantages, and novel features are described herein. It should be understood that not all of such advantages may necessarily be achieved according to any particular embodiment. Thus, the technological innovation may be embodied or implemented to achieve or optimize one advantage or group of advantages as taught herein without necessarily achieving other advantages that may be taught or suggested herein.

Brief Description of the Drawings

[0021] These and other features, aspects, and advantages of the present disclosure are described with reference to the drawings of particular embodiments. It should be understood that the accompanying drawings, which are incorporated herein and form a part of this specification, are for the purpose of illustrating the concepts disclosed herein and are not to scale.

[0022] [Figure 1A] FIG. is a diagram showing an example of a circuit assembly according to some embodiments.

[0023] [Figure 1B] FIG. 1A is a diagram showing an example of a schematic circuit diagram of the circuit assembly and an external capacitor.

[0024] [Figure 1C] FIG. is a diagram showing another example of a circuit assembly according to some embodiments.

[0025] [Figure 2A] FIG. is a diagram showing an example of a top view of a semiconductor component according to an embodiment of the present disclosure.

[0026] [Figure 2B] FIG. 2A is a diagram showing an example of a bottom view of the semiconductor component.

[0027] [Figure 3A] FIG. is a diagram showing an example of an exploded view of a packaged semiconductor component according to an embodiment of the present disclosure.

[0028] [Figure 3B] This figure shows an example of an array assembly of packaged semiconductor components according to an embodiment of the present disclosure.

[0029] [Figure 4] This figure shows an example of a cross-sectional view of a semiconductor component according to an embodiment of the present disclosure.

[0030] [Figure 5] This figure shows an example of a circuit assembly system having two semiconductor packages according to an embodiment of the present disclosure.

[0031] [Figure 6] This figure shows an example of a circuit assembly system in which a capacitor is mounted on top of the circuit assembly system according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0032] The following detailed descriptions of several embodiments present various descriptions of specific embodiments. However, the technological innovations described herein can be embodied in numerous different ways, for example, as defined and encompassed by the claims. In this description, similar reference numbers and / or terms may refer to drawings that represent identical or functionally similar elements. It will be understood that the elements shown in the drawings are not necessarily drawn to scale. Furthermore, it will be understood that some embodiments may include more elements and / or subsets of elements shown in the drawings than those shown. In addition, in some embodiments, any suitable combination of features from two or more drawings can be integrated. The headings provided herein are for convenience only and do not necessarily affect the claims or their meaning. Introduction

[0033] Electronic components comprising one or more integrated circuit (IC) dies can be deployed in a wide variety of applications and under a wide variety of environmental conditions. For example, such components can form part of a power electronics system. In some cases, a power electronics system can be used to power an electric vehicle. In some applications, a power electronics system can be part of a fixed energy storage system, such as a system for storing solar energy or a system for supplying power to a destination. These are just examples, and there are many other applications for such systems. In some cases, the component may include diode switches, field-effect transistors (FETs) such as metal-oxide-semiconductor FETs (MOSFETs) (e.g., silicon MOSFETs, GaN MOSFETs, etc.), insulated-gate bipolar transistors (IGBTs), other bipolar transistors, similar, or any suitable combination thereof. Such switches may be included in inverters. In certain applications, switches within packaged semiconductor components disclosed herein can switch voltages within a range of 1 volt (V) to 150 V, for example, within a range of 12 V to 150 V.

[0034] Snubber capacitors may be used in certain switching components to reduce and / or eliminate voltage transients and / or ringing associated with switching. It may be desirable to reduce and / or minimize the parasitic inductance associated with snubber capacitors connected between the terminals of a switching device. Embodiments of this disclosure can provide low parasitic inductance associated with snubber capacitors connected between the terminals of a switching device and associated packaged components for connecting to the snubber capacitors.

[0035] Power electronics systems can generate a considerable amount of heat. Such heat can present significant problems. For example, excessive heat can lead to reduced performance, decreased reliability, and shortened lifespan. For instance, excessive thermal stress can weaken solder joints, damage semiconductor components, or both. In some applications, surge loads can result in rapid temperature increases. High surge loads can be encountered in a variety of applications, such as when starting portable compressors, HVAC systems, refrigeration systems, electric motors, and power converters. In certain semiconductor package designs, a cooling solution may be implemented within the semiconductor package to dissipate heat. In some cases, the semiconductor package may be designed to dissipate heat through a printed circuit board (PCB). For example, top-side cooling may be used to cool an IC, as described in U.S. Patent No. 10,658,276, entitled “Device with top-side base plate,” the entire disclosure of which is incorporated herein by reference for all purposes.

[0036] Certain semiconductor packages (e.g., semiconductor component packages) may include die connection terminals (e.g., contact terminals) such as the source, drain, and gate of a field-effect transistor semiconductor component. The source and drain terminals may be mounted at both ends of the body of the semiconductor component. For example, the switching terminals of a semiconductor component may be arranged with the source and drain mounted facing each other. Some semiconductor components may include an exposed heat spreader facing downward to the surface of a carrier such as a PCB. In an upper cooling device with an exposed heat spreader at drain potential, the terminals on the side of the device adjacent to the side with the source terminal and the side with the drain terminal do not need to be electrically in contact with the PCB. The source and drain terminals can be electrically in contact with other components via traces embedded and / or etched on the printed circuit board (PCB). For example, these terminals can be electrically connected via PCB traces to a power generation component that provides a high-frequency switching input power signal (e.g., a signal used in a digital-to-analog converter and / or analog-to-digital converter). However, these traces may introduce parasitic effects such as parasitic inductance. Such parasitic inductance can lead to signal distortion, impedance mismatch, signal noise, or any combination thereof in high-speed switching signals.

[0037] The shape and height of conductive elements in semiconductor packages can also have harmful parasitic inductances at certain switching frequencies. Therefore, die packaging that can facilitate operation with relatively low parasitic effects, such as parasitic inductance, is needed. Such semiconductor chip packaging can be designed using low-profile, PCB-like internal elements when mounted. Package design

[0038] Aspects of this disclosure relate to semiconductor chip packages (e.g., semiconductor packages) having lead frames and electrical components that can reduce and / or minimize parasitic effects. In particular, semiconductor chip packages may include various traces for electrically connecting the integrated components of the semiconductor chip package. Such traces may generate undesirable parasitic inductances, and electrical components may be integrated into the semiconductor chip package to mitigate these undesirable parasitic inductances. In addition, each semiconductor component includes a lead frame on which the electrical components can be mounted. Such lead frames can be formed into a desired shape and can provide a heating solution for the semiconductor package. In some cases, the lead frame also provides electrical connections between the terminals of the semiconductor component. For example, the lead frame can provide electrical connections to the back surface of the die and the top surface of the semiconductor die. The lead frame can also be in a formable shape (e.g., a pre-formed lead frame) and can be mounted as a pre-positioned or positioned conductor of a desired shape during the assembly process.

[0039] In some cases, electrical components can be implemented to reduce and / or minimize parasitic effects. For example, capacitors and their connections to semiconductor packages can be positioned to achieve low parasitic inductance. When high-speed switching signals are applied to the inputs of semiconductor components, parasitic inductance can occur between carrier traces, such as those on a PCB. To reduce and / or minimize parasitic inductance, capacitors, such as snubber capacitors, can be implemented between the traces.

[0040] In embodiments disclosed herein, a capacitor can be mounted with the source and drain terminals to reduce and / or minimize parasitic inductance. The source and drain terminals of a semiconductor package can be connected via a capacitor. The arrangement of the source and drain leads of the semiconductor package allows for a compact connection between the capacitor and the source and drain leads. This capacitor connected between the source and drain of a switching device may be commonly referred to in this disclosure as a “snubber capacitor.” During the operation of a semiconductor component, such as high-speed switching, the source and drain leads can be connected by a snubber capacitor component via PCB traces. Source-capacitor-drain influence ringing or voltage overshoot in the semiconductor switch waveform can form a tight current path and / or “triangle” loop region. Experiments in mounting a snubber capacitor on a semiconductor package to directly bridge the drain and source showed reduced parasitic inductance. In some embodiments, two source lead frames can be extended to both sides of the semiconductor component by providing a snubber capacitor positioned on either side for PCB layout.

[0041] In embodiments disclosed herein, heat transfer can be concentrated on the upper side of the semiconductor package. Upper cooling may be desirable in certain applications, for example, due to considerations of the lower mounting surface temperature, PCB layout, and / or features. The techniques disclosed herein can be applied to double-sided cooled semiconductor packages. Certain designs may have conductive elements exposed on the top and bottom and may have design features to maintain their position during assembly and mold encapsulation. This allows for control of molding flash and resin bleed. Thus, the need for grinding can be reduced or eliminated.

[0042] Figure 1A shows a circuit assembly 100A according to an embodiment of the present disclosure. For illustrative purposes, the circuit assembly 100A is shown in a package of a single packaged semiconductor component 110. However, the circuit assembly 100A may include multiple packaged semiconductor components 110, and the present disclosure does not limit the number of packaged semiconductor components 110. As shown in Figure 1A, the circuit assembly 100A may include the packaged semiconductor component 110, traces 120, 130, 140, and a capacitor 150. The packaged semiconductor component 110 may be mounted on a carrier such as a PCB (not shown in Figure 1A). The packaged semiconductor component 110 may be electrically connected to other components, such as other power supply components, other semiconductor components, etc. via the PCB. For example, traces 120, 130, 140 may be etched onto the PCB and configured to provide an electrical contact area or line between the packaged semiconductor component 110 and other components. Each of the traces 120, 130, 140 may have any shape and / or area suitable for a particular application.

[0043] Trace 120 can provide electrical contact to a designated terminal (e.g., the drain terminal 122 of the packaged semiconductor component 110). Trace 130 can provide electrical contact to a designated terminal of another group (e.g., the source terminal 132 of the packaged semiconductor component 110). Trace 140 can provide electrical contact to a designated terminal (e.g., the gate terminal 142 of the packaged semiconductor component 110). In some cases, trace 135 can be combined with trace 130 to provide a contact area for the source of the packaged semiconductor component 110. Alternatively, terminals 134 and trace 135 can be arranged as a Kelvin source. These configurations are provided as examples, and the configuration can be modified based on a specific application.

[0044] As further shown in Figure 1A, the capacitor 150 may have ends connected to each trace. For example, traces 120 and 130 can be capacitively coupled via the capacitor 150. Such a capacitor 150 may be referred to as a snubber capacitor. The capacitor 150 can be used to mitigate undesirable signals generated by parasitic effects such as voltage spikes that may occur during high-speed switching operation of a circuit assembly (e.g., parasitic inductance caused by the inductive coupling of traces 120 and 130). For example, parasitic inductance caused by two close traces, such as between trace 120 and trace 130, can cause parasitic inductance. In embodiments of this disclosure, these parasitic effects caused by the inductive coupling between traces can be mitigated by the capacitor 150. For example, the capacitor 150 can absorb energy associated with a voltage spike. In some cases, the capacitor 150 can be soldered onto traces 120 and 130. The capacitance value of the capacitor 150 can be determined based on the applied input signal (e.g., one or more of the applied voltage, frequency, or waveform) and the distance between the traces. Capacitor 150 can be any capacitor suitable for the specifications of circuit assembly 100A.

[0045] Figure 1B shows a schematic circuit diagram of the circuit assembly 100A and capacitor 150 of Figure 1A. The drain terminal 122, source terminals 132 (including 132A and 132B), gate terminal 142, and Kelvin source 134 of the packaged semiconductor component 110 may correspond to points 122, 132, 142, and 134 in the schematic diagram of Figure 1B, respectively. In addition, traces 120, 130, 140, and 135 in Figure 1A are shown with the same numerical notation in Figure 1B. As shown in Figure 1B, capacitor 150 can be connected between the drain terminal 122 and source terminal 132 of the packaged semiconductor component 110. As further shown in Figure 1A, the packaged semiconductor component 110 may also have source terminals 132A and 132B on both sides of the packaged semiconductor component 110.

[0046] Figure 1C shows a circuit assembly 100B according to an embodiment of the present disclosure. As shown in Figure 1C, circuit assembly 100B includes an additional capacitor 155 compared to circuit assembly 100A shown in Figure 1A. Traces 120 and 130 of circuit assembly 100B are also shaped and configured to connect the additional capacitor 155 between the source terminal 132 and drain terminal 122 of the packaged semiconductor component 110. Similar components of circuit assembly 100B may function similarly to or in the same way as similar components of circuit assembly 100A in Figure 1A. For illustrative purposes, circuit assembly 100B is shown in a package of a single packaged semiconductor component 110. However, circuit assembly 100B may include multiple packaged semiconductor components 110, and the present disclosure does not limit the number of packaged semiconductor components 110.

[0047] As shown in Figure 1C, each of capacitor 150 and the additional capacitor 155 may have an end connected to its respective trace. For example, traces 120 and 130 can be capacitively coupled via capacitor 150 and the additional capacitor 155 located on opposing sides of the packaged semiconductor component 110. Each of capacitor 150 and the additional capacitor 155 can mitigate undesirable signals generated by parasitic effects such as voltage spikes that may occur during the high-speed switching operation of the circuit assembly 100B (e.g., parasitic inductance caused by the inductive coupling of traces 120 and 130). For example, parasitic inductance caused by two nearby traces, such as between trace 120 and trace 130, can cause parasitic inductance. In embodiments of this disclosure, these parasitic effects caused by the inductive coupling between traces can be mitigated by capacitor 150 and the additional capacitor 155. For example, each of capacitor 150 and the additional capacitor 155 can absorb the energy associated with a voltage spike. In some cases, capacitor 150 and additional capacitor 155 can each be soldered onto traces 120 and 130. Having two capacitors 150 and 155 in parallel with each other may be advantageous in mitigating parasitic effects in certain applications. The capacitance values ​​of each of capacitor 150 and additional capacitor 155 can be determined based on the applied input signal (e.g., one or more of the applied voltage, frequency, or waveform) and the distance between the traces. Each of capacitor 150 and additional capacitor 155 can be any capacitor suitable for the specifications of circuit assembly 100B.

[0048] Figure 2A shows a top view of the packaged semiconductor component 110 of Figure 1A according to one embodiment. The packaged semiconductor component 110 may include a package structure 310 that can surround the packaged semiconductor component 110. The package structure 310 may be made of a rigid molded resin. The package structure 310 may be disposed on top of a die paddle 320. The die paddle 320 may be referred to as a “clip”. The die paddle 320 may function as a heat spreader in any suitable embodiment disclosed herein. In some cases, the heat spreader may be an upper heat spreader having a relatively large area. The die paddle 320 may be used to provide an electrical connection to the top surface of the packaged semiconductor component 110 and may function as a heat spreader. In some examples, the semiconductor package assembly or manufacturing orientation may prefer that the die paddle 320 be assembled last on top of the die, in which case this may be referred to as a “clip”. The package structure may also include a molding material. The packaged semiconductor component 110 may include a bottom side with punched leads. The punched lead can be flat.

[0049] Figure 2B shows a bottom view of the packaged semiconductor component 110 of Figure 1A according to one embodiment. The packaged semiconductor component 110 may include a drain terminal 122, source terminals 132 (including 132A and 132B), a gate terminal 142, and a Kelvin source terminal 134. The packaged semiconductor component 110 can be assembled on top of a PCB, where the top of the PCB provides various traces such as traces 120, 130, 140, and / or 135, as shown in Figure 1A. In some embodiments, each of the drain terminal 122, source terminals 132 (including 132A and 132B), gate terminal 142, and Kelvin source terminal 134 can be electrically connected to one of the traces by assembling the packaged semiconductor component 110 on top of the PCB. For example, each of the drain terminal 122, source terminal 132 (including 132A and 132B), gate terminal 142, and Kelvin source terminal 134 can provide contacts for monitoring the packaged semiconductor component 110 (e.g., contacts for temperature sensors such as thermocouples) by contacting their corresponding traces. In some embodiments, the drain terminal 122, source terminal 132 (including 132A and 132B), gate terminal 142, and Kelvin source terminal 134 can extend beyond the bulk of the packaged semiconductor component 110 by contacting their corresponding traces. In some embodiments, the drain terminal 122, source terminal 132 (including 132A and 132B), gate terminal 142, and Kelvin source terminal 134 can be coplanar with the outer surface of the packaged semiconductor component 110 by contacting their corresponding traces. In some embodiments, the drain terminal 122, source terminals 132 (including 132A and 132B), gate terminal 142, and Kelvin source terminal 134 may be recessed in one or more directions from the outer surface of the packaged semiconductor component 110 by contacting their corresponding traces. The Kelvin source terminal 134 may be provided as a terminal for separating current paths (e.g., control current path and load current path).In some embodiments, the Kelvin source terminal 134 can be combined with the source 132 (for example, to form a signal strip).

[0050] The packaged semiconductor component 110 may include side-source terminals 132A and 132B. These side-source terminals 132A and 132B can be electrically connected to a common trace with the source terminal 132 within the packaged semiconductor component 110. For example, the trace 130 may be molded to cover the areas of the side-source terminals 132A and 132B as well as the source terminal 132. As shown, the side-source terminals 132A and 132B are positioned on the side of the packaged semiconductor component 110, while the other source terminal 132 and drain terminal 122 are positioned on the other respective sides of the packaged semiconductor component 110. The molding material and die paddle 320 may have notches around the side-source terminals 132A and 132B, respectively. These notches may help to recess the terminals to make them less conspicuous for handling or proximity spacing between other components in the PCB layout. The shape and position of these notches can provide sufficient electrical surface creepage distance to mitigate and / or prevent arc discharge to adjacent terminals of different voltages or functions. The side source terminals 132A and 132B are located on the side of the packaged semiconductor component 110, adjacent to the other source terminal 132 and also adjacent to the drain terminal 122. The side source terminals 132A and 132B are located closer to the nearest drain terminal 122 than to the nearest other source terminal 132. The side source terminals 132A and 132B can also provide mechanical support for the packaged semiconductor component 110. For example, when the packaged semiconductor component 110 is assembled, these side source terminals 132A and 132B can provide mechanical support for the packaged semiconductor component 110, including the die paddle 320, during and / or after the manufacturing process.

[0051] In some embodiments, the packaged semiconductor component 110 may include frames 352, 310, 230, and 240. These frames may be conductive frames, such as lead frames, of the packaged semiconductor component 110. These frames may be mounted with patterns that can provide electrical contact with terminals of the die, such as drain, source, and gate (not shown in Figure 2B). For example, the drain frame 352, source frame 310, gate frame 230, and Kelvin source frame 240 may be positioned based on the drain, source, gate, and Kelvin source terminals of the die, respectively. Thus, the source terminal 132 (including 132A and 132B), drain terminal 122, gate terminal 142, and Kelvin source 134 of the packaged semiconductor component 110 may be electrically connected to the drain frame 352, source frame 310, gate frame 230, and Kelvin source frame 240, respectively.

[0052] In this disclosure, source contacts, drain contacts, and gate contacts are referred to, but these are for illustrative purposes only. Generally, punched leads can be used to provide source terminals, gate terminals, drain terminals, Kelvin source terminals, control terminals, input terminals, output terminals, sensor terminals, base terminals, emitter terminals, collector terminals, ground terminals, reference terminals, short-circuit terminals, or any other suitable electrical terminals.

[0053] Figures 3A and 3B show exemplary embodiments of semiconductor components and assemblies in an array structure.

[0054] Figure 3A shows an exploded view of a packaged semiconductor component 110 according to several embodiments. Each packaged semiconductor component 110 can be mounted on a frame 352 and assembled with other semiconductor components. In some embodiments, the frame 352 can provide mechanical support and electrical contact within the assembly.

[0055] As shown in Figure 3A, the packaged semiconductor component 110 may include a layer of bonding material 312, a die 314, a layer of die attach material 316, and a packaging structure 310, as well as a die paddle 320 (e.g., a die clip). In some examples, the layer of bonding material 312 may be formed based on a pattern that includes multiple regions for providing electrical connections to corresponding die connection terminals (e.g., contact terminals) such as the source (including the Kelvin source), drain, and gate of the semiconductor component. For example, die attach pads 312A, 312B, 312C, and 312D may provide electrical connections to the drain terminal, source terminal, gate terminal, and Kelvin source terminal of the die connection terminal, respectively. In some examples, the layer of die attach material 312 may be formed from a conductive material such as solder or conductive epoxy.

[0056] Referring further to Figure 3A, in some examples, a field-effect transistor (FET), such as a metal-oxide-semiconductor field-effect transistor (MOSFET) (e.g., a GaN MOSFET), can be mounted on the die 314. Thus, the die 314 can include terminals such as a drain, source (and Kelvin source), and gate. In some cases, a layer of die attach material 316 can be assembled (e.g., bonded) on top of the die 314. In some examples, the layer of die attach material 316 can cover the top surface of the die 314. In addition, the layer of die attach material 316 can be configured to bond the die 314 to the packaging structure 310. The layers of bonding material 314 and die attach material 316 can be formed from the same type of bonding material (e.g., a conductive bonding material). In some cases, the structure of the packaged semiconductor component 110 can be modified so that the die paddle 320 can be on top of the layer of die attach material 316. In some assembly processes, the die paddle 320 can be assembled after the layers of die 314 and die attach material 316 have been assembled. In these assembly processes, the die paddle 320 may be referred to as a "clip".

[0057] Figure 3B shows an example of an array assembly 350 of packaged semiconductor components 110. As shown in Figure 3B, the die paddles or clips 320 can be mounted on each device lead frame unit 352 of the array assembly 350. In some embodiments, the packaged semiconductor components 110 can be assembled or mounted in different orientations. During the assembly process of the array assembly 350, the device lead frame units 352 can alternatively be mounted on top of each die paddle or clip 320.

[0058] Figure 4 shows a cross-sectional view of the packaged semiconductor component 110 of Figure 1A. As shown in Figure 4, the packaged semiconductor component 110 may include a die paddle or clip 320, a die attach structure 420, a die 314, a lead attach structure 440, a drain lead frame 312A, a source lead frame 312B, a side source terminal 132A (side source terminal 132B is not shown), and a source terminal 132 (other side source terminals 132, a Kelvin source terminal 134, and a gate terminal 142 are not shown in Figure 4). The die paddle 320 can function as a heat spreader. The die paddle 320 can also be used to provide an electrical connection to the top surface of the packaged semiconductor component 110. The die attach structure 420 can be used to mount the die 314 and the die paddle 320. The die 314 can be implemented as a field-effect transistor (FET), such as a metal-oxide-semiconductor field-effect transistor (MOSFET) (e.g., a Si MOSFET or a GaN MOSFET), and therefore the die 314 can include terminals such as drain, source, and gate. The lead attachment structure 440 allows the die 314 to be attached to lead frames 312A and 312B (lead frames 312C and 312D are not shown in Figure 4).

[0059] In some embodiments, lead frame 312A can be connected to drain terminal 122, and lead frame 312B can be connected to source terminal 132 and side source terminals 132A and 132B (side source terminal 132 is not shown in Figure 4). These lead frames 312A and 312B can be connected to other semiconductor components or any electrical components by connecting to the corresponding terminals 122, 132, and 132A, the drain, source, and gate terminals of the die. For example, the drain terminal of die 314 can be connected to lead frame 312A and drain terminal 122. Then, drain terminal 122 can be electrically coupled to trace 120, as described with reference to Figures 1A and 1B. Similarly, the source terminal of die 314 can be connected to lead frame 312B and source terminal 132. Then, source terminal 132 can be electrically coupled to trace 130, as described with reference to Figures 1A and 1B. Similarly, the gate terminal of die 314 can also be connected to trace 140 via lead frame 312D (shown in Figure 3), gate terminal 135 (shown in Figure 1A), and trace 140 (shown in Figure 1A).

[0060] The side source terminals 132A and 132B shown in Figures 1A and 2 are implemented to provide proximity to the drain terminal 122. For example, since the drain terminal 122 and the side source terminal 132A are in close proximity to each other, traces 120 and 130 can also be implemented in close proximity to each trace, as shown in Figure 1A. Accordingly, according to the embodiments disclosed herein, an electronic component 150 such as a capacitor can be implemented between traces 120 and 130.

[0061] In some embodiments, the drain terminal 122 and source terminal 132 can provide mechanical support points when mounting the packaged semiconductor component 110 onto a carrier such as a PCB, or to support the lead frames 312A and 312B at desired positions within the lead frame array during assembly. In some embodiments, the side terminals 132A and 132B can provide additional mechanical support points.

[0062] Figure 5 shows a circuit assembly 500 incorporating two packaged semiconductor components 110A and 110B. Each of these components can be packaged in a similar manner to that of semiconductor package 110, as shown in Figures 1A and 2B, respectively. Figure 5 demonstrates that semiconductor components 110A and 110B can be assembled with each rotated 180 degrees relative to the other. For example, semiconductor component 110A is oriented in the opposite direction and rotated 180 degrees relative to semiconductor component 110B. For example, the drain terminal 122A of semiconductor component 110A is positioned on the upper side (e.g., the upper side in Figure 5), and the source terminal 132AA, Kelvin source terminal 134A, and gate terminal 142A are positioned on the lower side (e.g., the lower side in Figure 5). Semiconductor component 110B can be assembled in the opposite direction to semiconductor component 110A. For example, the drain terminal 122B of semiconductor component 110B is positioned on the lower side (e.g., the lower side in Figure 5), while the source terminal 132BB, Kelvin source terminal 134B, and gate terminal 142B are positioned on the upper side (e.g., the upper side in Figure 5). As further shown in Figure 5, the side source terminals 132A1 and 132B1 of semiconductor component 110A may be positioned above the side source terminals 132A2 and 132B2 of semiconductor component 110B. Thus, capacitors 150A and 150B can be mounted while minimizing the form factor of the circuit assembly 500.

[0063] Capacitor 150A is connected to packaged semiconductor component 110A via traces (not shown in Figure 5) connected to the drain and source terminals of the component. Similarly, capacitor 150B is connected to semiconductor component 110B via traces (also not shown in Figure 5) attached to its drain and source terminals. The integration of capacitors 150A and 150B creates capacitor loops 514 and 524, respectively. In certain designs, it is possible to mount three or more semiconductor components. For example, an array containing multiple semiconductor components can be created by rotating each component 180 degrees relative to its adjacent components.

[0064] Figure 6 shows a circuit assembly system 600 by mounting capacitors on top of the circuit assembly system 600 according to an embodiment of the present disclosure. The circuit assembly system 600 includes a packaged semiconductor component 650 and capacitors 680 and 690 on a PCB. The packaged semiconductor component 650 includes source and drain terminals on a common side. This allows the snubber capacitor 680 to be electrically connected between source terminal 632A and drain terminal 622A by traces with low parasitic inductance. Similarly, the snubber capacitor 690 can be electrically connected between source terminal 632B and drain terminal 622C by traces with low parasitic inductance. The location of the terminals on the packaged semiconductor component 650 allows the snubber capacitors to be connected between the source and drain in a compact layout with low parasitic inductance.

[0065] For illustrative purposes, Figure 6 shows a bottom view of a packaged semiconductor component 650 and two capacitors 680 and 690, without showing the PCB, but showing a portion of the traces on the PCB. The packaged semiconductor component 650 and capacitors 680, 690 can be mounted on the PCB, for example, as described in one or more of the embodiments above. Capacitors 680 and / or 690 can be electrically connected between source and drain in any suitable manner. As shown in Figure 6, the PCB may include traces 660A, 660B, and 670 (for example, only a portion of the PCB traces are shown in Figure 6) which are shown as being connected to source terminal 632A, source terminal 632B, and drain terminals 622A-C, respectively. Gate terminal 642, other source terminal 632, and Kelvin source terminal 634 may be connected to PCB traces not shown in Figure 6. In some embodiments, source terminal 632A and drain terminals 622A-622C can be coupled by implementing a capacitor 680 between trace 660A and trace 670. In some cases, source terminal 632B and drain terminals 622A-622C can be coupled by implementing a capacitor 690 between trace 660B and trace 670. In some embodiments, traces 660A and 660B can be formed within the same trace.

[0066] The layout of the source frame 610, drain frame 620, gate frame 630, and Kelvin source frame 640 can be arranged as shown in Figure 6. In some implementations, the layout can be determined based on the layout of the die terminals (e.g., drain, source (and Kelvin source), and gate). For example, as shown in Figure 6, the source frame 610 can be patterned to cover the source terminals of the die so that the source terminals of the die are electrically connected to the terminals on the opposing sides of the packaged semiconductor component 650. In the packaged semiconductor component 650, the source terminals of the die are electrically connected to source terminals 632A and 632B and source terminal 632. Furthermore, the drain frame 620 can be patterned to cover the drain terminal of the die. The drain frame 620 can electrically connect the drain terminal of the die to drain terminals 622A to 622C, as shown in Figure 6. In addition, the gate frame 630 and Kelvin source frame 640 can electrically connect the terminals of the die to gate terminal 642 and Kelvin source terminal 634, respectively.

[0067] In some embodiments, the circuit assembly system 600 may include two capacitors 680 and 690. These capacitors 680 and 690 can be mounted between the source and drain terminals via source traces 660A and 660B (only a portion of the source traces is shown in Figure 6 for illustrative purposes) and a drain trace 670. For example, as shown in Figure 6, source terminal 632A is electrically connected to source trace 660A, and the other source terminal 632B is electrically connected to source trace 660B. In addition, drain terminals 622A to 622C can be connected to the drain trace 670. Thus, capacitor 680 can be electrically connected between source terminal 632A and drain terminals 622A to 622C by a short trace. Furthermore, capacitor 690 can be electrically connected between source terminal 632B and drain terminals 622A to 622C by a short trace. The traces shown in Figure 6 may represent only a portion of the traces. In some embodiments, either capacitor 680 or 690 can be mounted in the circuit assembly system 600. In other embodiments, both capacitors 680 and 690 can be mounted in the circuit assembly system 600. Additional Embodiments

[0068] The above specification describes this disclosure with reference to specific embodiments. However, it will be apparent that various modifications and changes can be made without departing from the broader spirit and scope of this disclosure. Accordingly, this specification and the drawings should be considered illustrative rather than restrictive.

[0069] In fact, while this disclosure is in the context of specific embodiments and examples, it will be understood by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or the use of the present invention and its equivalents. In addition, while several variations of the embodiments have been shown and described in detail, other modifications within the scope of this disclosure will be readily apparent to those skilled in the art based on this disclosure. Furthermore, various combinations or partial combinations of specific features and aspects of the embodiments may be made and may still be included within the scope of this disclosure. It should be understood that various features and aspects of the disclosed embodiments may be combined with or substituted for each other to form various forms of the embodiments disclosed herein. None of the methods disclosed herein have to be performed in the order listed. Accordingly, it is intended that the scope of this disclosure should not be limited by the specific embodiments described above.

[0070] Each of the systems and methods disclosed herein has several innovative aspects, and it will be understood that not just one of them alone can or is required to fulfill the desired attributes disclosed herein. The various features and processes described above may be used independently of each other or in various combinations. All possible combinations and partial combinations are intended to fall within the scope of this disclosure.

[0071] Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable partial combination. Furthermore, features may be described above as acting in a particular combination and may even be initially claimed as such, but one or more features from a claimed combination may, in some cases, be removed from the combination, and the claimed combination may cover a partial combination or a variation of a partial combination. No single feature or group of features is required or essential to any embodiment.

[0072] It will also be understood that the conditional language used herein, in particular "can," "could," "might," "may," and "e.g.," is generally intended to convey that a particular embodiment includes certain features, elements, and / or steps, but other embodiments do not, unless otherwise specified or understood in the context in which they are used. Therefore, such conditional language is not generally intended to mean that features, elements, and / or steps are required in some way in one or more embodiments, or that one or more embodiments necessarily include logic for determining whether these features, elements, and / or steps should be included in or performed in any particular embodiment, with or without input or prompting from the author. Terms such as "equip," "include," and "have" are synonymous and are used in a comprehensive, open-ended manner, not excluding additional elements, features, actions, behaviors, etc. In addition, the term “or” is used in its inclusive sense (and not its exclusive sense), and therefore, for example, when used to connect a list of elements, the term “or” means one, some, or all of the elements in the list. Furthermore, the articles “a,” “an,” and “the” used in this application and the attached claims should be interpreted as meaning “one or more” or “at least one” unless otherwise specified. Similarly, while actions may be shown in drawings in a particular order, it should be recognized that such actions do not need to be performed in a particular order or sequential order shown, or that not all shown actions need to be performed, in order to achieve the desired result. Furthermore, drawings may schematically illustrate one or more exemplary processes in the form of flowcharts. However, other actions not illustrated may be incorporated into the exemplary methods and processes schematically shown. For example, one or more additional actions may be performed before, after, simultaneously with, or in between any of the illustrated actions. Furthermore, actions may be rearranged or reordered in other embodiments.In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and the described program components and systems may generally be integrated together in a single software product or packaged in multiple software products. Further embodiments are within the scope of the following claims. In some cases, the actions described in the claims may be performed in a different order and still achieve the desired results.

[0073] Furthermore, the methods and devices described herein may be subject to various modifications and alternative forms, specific examples of which are shown in the drawings and described in detail herein. However, it should be understood that this disclosure is not limited to any particular form or method disclosed, but rather encompasses all modifications, equivalents, and alternatives that fall within the spirit and scope of the various implementations described and the accompanying claims. Furthermore, any particular features, aspects, methods, characteristics, properties, qualities, attributes, elements, etc., disclosed herein relating to an implementation or embodiment may be used in all other implementations or embodiments described herein. None of the methods disclosed herein have to be performed in the order listed. The methods disclosed herein may include specific actions performed by practitioners, but the methods may also include any third-party instructions for such actions, expressly or implicitly. The scope disclosed herein also includes any overlaps, sub-scopes, and combinations thereof. Language such as “up to,” “at least,” “greater than,” “less than,” and “between” includes the numbers listed. Numbers preceded by terms such as "approximately" or "about" should include the listed numbers and be interpreted in context (e.g., as accurately as reasonably possible under the circumstances, e.g., ±5%, ±10%, ±15%). Phrases preceded by terms such as "substantially" should include the listed phrases and be interpreted in context (e.g., as accurately as reasonably possible under the circumstances). For example, "substantially constant" includes "constant." Unless otherwise specified, all measurements are taken under standard conditions, including temperature and pressure.

[0074] Where used herein, the phrase “at least one” in a list of items refers to any combination of those items, including a single member. For example, “at least one of A, B, or C” is intended to include A, B, C, A and B, A and C, B and C, and A, B, and C. Connecting language such as the phrase “at least one of X, Y, and Z” is understood separately in the context in which it is commonly used to convey that an item, term, etc., may be at least one of X, Y, or Z, unless otherwise specified. Thus, such connecting language is not generally intended to mean that a particular embodiment requires the presence of at least one of X, at least one of Y, and at least one of Z, respectively. Headings provided herein, where present, are for convenience only and do not necessarily affect the scope or meaning of the devices and methods disclosed herein.

[0075] Therefore, the claims are intended to be limited to the embodiments shown herein. This does not mean that the disclosures, principles, and novel features disclosed herein are consistent with the most accurate representations. They should also be given a wide range. (Note) [Configuration 1] A packaged semiconductor component comprising: a semiconductor die including a field-effect transistor; a side-source terminal positioned on a first side of the packaged semiconductor component and connected to the source of the field-effect transistor; and a drain terminal positioned on a second side of the packaged semiconductor component and connected to the drain of the field-effect transistor, wherein the first side is adjacent to the second side of the packaged semiconductor component. A capacitor located outside the packaged semiconductor component and electrically connected between the source terminal and the drain terminal, A circuit assembly comprising: [Configuration 2] The circuit assembly according to configuration 1, further comprising a printed circuit board, wherein the packaged semiconductor component and the capacitor are positioned on the printed circuit board, and the packaged semiconductor component further includes a heat spreader facing the printed circuit board. [Configuration 3] The circuit assembly according to configuration 2, wherein the side source terminals provide mechanical support points for the heat spreader. [Structure 4] The aforementioned packaged semiconductor component is A plurality of additional drain terminals located on the second side and connected to the drain of the field-effect transistor, The circuit assembly according to configuration 1, further comprising a plurality of source terminals located on a third side of the packaged semiconductor component and connected to the source of the field-effect transistor, wherein the third side is opposite to the second side. [Composition 5] The circuit assembly according to configuration 1, wherein the packaged semiconductor component further comprises a second side source terminal on a side facing the first side. [Composition 6] The circuit assembly according to configuration 1, wherein each of the first and second sides of the packaged semiconductor component includes a lead frame. [Composition 7] The circuit assembly according to configuration 1, further comprising a second packaged semiconductor component and a second capacitor electrically connected between the side source terminal and the drain terminal of the second packaged semiconductor component, wherein the second packaged semiconductor component is rotated 180 degrees relative to the packaged semiconductor component. [Structure 8] The circuit assembly according to configuration 1, further comprising a printed circuit board, wherein the printed circuit board includes traces, and the capacitor is connected to one of the traces. [Composition 9] Packaged semiconductor components, A semiconductor die comprising a field-effect transistor having a source, gate, and drain, Located on the first side of the packaged semiconductor component, there are a plurality of drain terminals connected to the drain, Located on the second side of the packaged semiconductor component, and connected to the source, A plurality of source terminals located on the third side of the packaged semiconductor component and connected to the side source terminal within the packaged semiconductor component, Equipped with, A packaged semiconductor component in which the third side is on the opposite side of the first side, the second side is adjacent to both the first and third sides, and the side source terminal is located closer to the first side than to the third side. [Configuration 10] A surface configured to be bonded to a printed circuit board, A heat spreader facing the surface, A packaged semiconductor component as described in configuration 9, further comprising: [Composition 11] The packaged semiconductor component according to configuration 10, wherein the side source terminals provide mechanical support for the heat spreader. [Composition 12] The packaged semiconductor component according to configuration 10, wherein the heat spreader has a notch around the side source terminal. [Composition 13] The packaged semiconductor component according to configuration 9, wherein each of the first and second sides of the packaged semiconductor component includes a lead frame. [Composition 14] The packaged semiconductor component according to configuration 13, wherein the lead frame includes punched flat ends. [Composition 15] The packaged semiconductor component according to configuration 9, further comprising a gate terminal positioned on the third side of the packaged semiconductor component. [Composition 16] A packaged semiconductor component, wherein the packaged semiconductor component is A semiconductor die comprising a field-effect transistor having a source, gate, and drain, The drain terminal connected to the drain, A packaged semiconductor component comprising a source terminal connected to the source, wherein the drain terminal and the source terminal are on the same side of the packaged semiconductor component, A capacitor located outside the packaged semiconductor component and electrically connected between the source terminal and the drain terminal, A circuit assembly comprising: [Composition 17] The circuit assembly according to configuration 16, further comprising a second capacitor located outside the packaged semiconductor component, wherein the packaged semiconductor component includes a second source terminal on the same side as the drain terminal and the source terminal of the packaged semiconductor component, and the second capacitor is electrically connected between the second source terminal and the drain. [Composition 18] The circuit assembly according to configuration 16, further comprising a printed circuit board, wherein the packaged semiconductor component and the capacitor are positioned on the printed circuit board, and the packaged semiconductor component further comprises a heat spreader facing the printed circuit board. [Composition 19] The circuit assembly according to configuration 16, wherein the packaged semiconductor component has a plurality of additional source terminals on a side opposite to the same side where the drain terminal and the source terminal are located. [Configuration 20] The circuit assembly according to configuration 16, wherein the packaged semiconductor component has at least one additional drain terminal on the same side as the drain terminal and the source terminal, and the at least one additional drain terminal is electrically connected to the capacitor located outside the packaged semiconductor component.

Claims

1. A packaged semiconductor component comprising: a semiconductor die including a field-effect transistor; a side-source terminal positioned on a first side of the packaged semiconductor component and connected to the source of the field-effect transistor; and a drain terminal positioned on a second side of the packaged semiconductor component and connected to the drain of the field-effect transistor, wherein the first side is adjacent to the second side of the packaged semiconductor component. A capacitor located outside the packaged semiconductor component and electrically connected between the side source terminal and the drain terminal, A circuit assembly comprising:

2. The circuit assembly according to claim 1, further comprising a printed circuit board, wherein the packaged semiconductor component and the capacitor are positioned on the printed circuit board, and the packaged semiconductor component further includes a heat spreader facing the printed circuit board.

3. The circuit assembly according to claim 2, wherein the side source terminals provide mechanical support points for the heat spreader.

4. The aforementioned packaged semiconductor component is A plurality of additional drain terminals located on the second side and connected to the drain of the field-effect transistor, The circuit assembly according to claim 1, further comprising a plurality of additional source terminals located on a third side of the packaged semiconductor component and connected to the source of the field-effect transistor, wherein the third side is opposite to the second side.

5. The circuit assembly according to claim 1, wherein the packaged semiconductor component further comprises a second side source terminal on a side facing the first side.

6. The circuit assembly according to claim 1, wherein each of the first and second sides of the packaged semiconductor component includes a lead frame.

7. The circuit assembly according to claim 1, further comprising a second packaged semiconductor component and a second capacitor electrically connected between the side source terminal and the drain terminal of the second packaged semiconductor component, wherein the second packaged semiconductor component is rotated 180 degrees relative to the packaged semiconductor component.

8. The circuit assembly according to claim 1, further comprising a printed circuit board, wherein the printed circuit board includes traces, and the capacitor is connected to one of the traces.

9. The circuit assembly according to claim 1, further comprising a source terminal on a third side of the packaged semiconductor component, wherein the third side is opposite to the second side.

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