Memory device

Abstract

To provide a highly reliable storage device.SOLUTION: A storage device comprises a first conductor, a second conductor above the first conductor, a third conductor above the second conductor, a fourth conductor above the third conductor, a fifth conductor above the fourth conductor, a sixth conductor above the fifth conductor, a seventh conductor, a first insulator, a second insulator, a first semiconductor and a second semiconductor. At least the third conductor and the fourth conductor have an opening. The first insulator, the first semiconductor, the second insulator, and the second semiconductor are sequentially arranged in this order from the inner lateral surface of the opening. The seventh conductor is arranged between the first semiconductor and the second insulator in a region between the third conductor and the second insulator. The first semiconductor is electrically connected to the second conductor and the fifth conductor. The second semiconductor is electrically connected to the first conductor and the sixth conductor.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the same.

[0002] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed herein relates to a product, method, or method of manufacture. Alternatively, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter.

[0003] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Therefore, semiconductor elements such as transistors and diodes, and circuits containing semiconductor elements, are semiconductor devices. Display devices, light-emitting devices, illumination devices, electro-optical devices, memory devices, imaging devices, communication devices, and electronic devices may also include semiconductor elements or semiconductor circuits. Display devices, light-emitting devices, illumination devices, electro-optical devices, memory devices, imaging devices, communication devices, and electronic devices may also be referred to as semiconductor devices. One aspect of the present invention relates particularly to a memory device and a method for manufacturing the same. [Background technology]

[0004] In recent years, with the increasing amount of data being handled, there has been a demand for semiconductor devices with larger storage capacities. To increase the storage capacity per unit area, it is effective to form memory cells by stacking them (see Patent Documents 1 and 2). By stacking memory cells, the storage capacity per unit area can be increased in proportion to the number of stacked memory cells. Patent Documents 3 and 4 disclose memory devices using oxide semiconductors. Patent Document 5 discloses a semiconductor memory using an oxide semiconductor as a charge storage layer.

[0005] Furthermore, Non-Patent Document 1 discloses CAAC-IGZO as a crystalline oxide semiconductor. Non-Patent Document 1 also discloses the growth mechanism of CAAC-IGZO.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Non - Patent Documents

[0007]

Non - Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] In Patent Document 1 and Patent Document 2, a plurality of memory elements (also referred to as memory cells) are stacked, and by connecting them in series, a memory cell array having a three - dimensional structure (also referred to as a memory string) is configured.

[0009] In Patent Document 1, a columnar semiconductor is in contact with an insulator having a charge storage layer. In Patent Document 2, a columnar semiconductor is in contact with an insulator that functions as a tunnel dielectric. In both Patent Document 1 and Patent Document 2, information is written to the memory cell by the extraction and injection of charge through the insulator. In this case, trap centers may be formed at the interface where the semiconductor and the insulator are in contact. Trap centers can capture electrons and cause fluctuations in the threshold voltage of the transistor. Furthermore, the extraction and injection of charge may cause deterioration of one or both of the inside of the insulator and the interface where the semiconductor and the insulator are in contact, causing the charge held in the charge storage layer to leak and disappear. Therefore, this may adversely affect the reliability of the memory device.

[0010] Therefore, one embodiment of the present invention aims to provide a highly reliable storage device. Another embodiment of the present invention aims to provide a storage device with a large storage capacity. Another embodiment of the present invention aims to provide a storage device with a small footprint. Another embodiment of the present invention aims to provide a storage device with low manufacturing costs. Another embodiment of the present invention aims to provide a highly reliable semiconductor device. Another embodiment of the present invention aims to provide a semiconductor device with low manufacturing costs. Another embodiment of the present invention aims to provide a novel semiconductor device.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. Moreover, one aspect of the present invention does not need to solve all of these problems. Other problems will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims. [Means for solving the problem]

[0012] One aspect of the present invention is a memory device comprising a first conductor, a second conductor above the first conductor, a third conductor above the second conductor, a fourth conductor above the third conductor, a fifth conductor above the fourth conductor, a sixth conductor above the fifth conductor, a seventh conductor, a first insulator, a second insulator, a first semiconductor, and a second semiconductor, wherein at least the third and fourth conductors have openings, and the first insulator, first semiconductor, second insulator, and second semiconductor are provided in order from the inner side surface of the opening, and in the region between the third conductor and the second insulator, a seventh conductor is provided between the first semiconductor and the second insulator, the first semiconductor is electrically connected to the second conductor and the fifth conductor, and the second semiconductor is electrically connected to the first conductor and the sixth conductor.

[0013] In the above, it is preferable that the first insulator, the first semiconductor, the seventh conductor, the second insulator, and the second semiconductor are each provided as concentric layers inside the opening of the third conductor.

[0014] In the above, it is preferable that the first insulator, the first semiconductor, the second insulator, and the second semiconductor are each provided as concentric layers inside the opening of the fourth conductor.

[0015] In the above, it is preferable that the first semiconductor is a first oxide semiconductor.

[0016] In the above, the first oxide semiconductor preferably comprises indium, element M (where element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0017] In the above, it is preferable that the second semiconductor is a second oxide semiconductor.

[0018] In the above, the first oxide semiconductor preferably comprises indium, element M (where element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0019] In the above, it is preferable that the openings are also provided in the second conductor and the fifth conductor, that a second insulator is provided between the second conductor and the second semiconductor, and that a second insulator is provided between the fifth conductor and the second semiconductor.

[0020] Another aspect of the present invention is a method for manufacturing a memory device comprising the steps of forming a first conductor, forming a second conductor above the first conductor, forming a first semiconductor electrically connected to the second conductor, forming openings in the first semiconductor and the second conductor, forming an insulator within the openings that covers the sides of the first semiconductor and the sides of the second conductor, forming a second semiconductor electrically connected to the first conductor, wherein an insulator is provided between the first semiconductor and the second semiconductor, and an insulator is provided between the second conductor and the second semiconductor.

[0021] In the above, it is preferable that the first semiconductor is a first oxide semiconductor.

[0022] In the above, the first oxide semiconductor preferably comprises indium, element M (where element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0023] In the above, it is preferable that the second semiconductor is a second oxide semiconductor.

[0024] In the above, the second oxide semiconductor preferably comprises indium, element M (where element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0025] Another aspect of the present invention is a method for manufacturing a memory device, comprising the steps of forming a first conductor, forming a second conductor above the first conductor, processing the first and second conductors such that the width of the second conductor is shorter than the width of the first conductor, forming a third conductor above the second conductor, forming openings in the third conductor, the second conductor, and the first conductor, forming an insulator in the openings, and forming a semiconductor in the openings, wherein an insulator is provided between the first conductor and the semiconductor, and an insulator is provided between the second conductor and the semiconductor.

[0026] In the above, the semiconductor is preferably an oxide semiconductor.

[0027] In the above, the oxide semiconductor preferably contains indium, element M (where element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc. [Effects of the Invention]

[0028] In the fabrication of a three-dimensional memory cell array in which multiple memory elements are stacked and connected in series, it is preferable that the total number of steps be less than the product of the number of stacked memory elements and the number of steps required to fabricate one memory element. In other words, the number of steps required to fabricate the above memory cell array is not proportional to the number of stacked memory elements. For example, when comparing the number of steps required to fabricate a memory cell array A having 4 layers of memory elements with the number of steps required to fabricate a memory cell array B having 32 layers of memory elements, the number of steps required to fabricate memory cell array B can be significantly less than eight times the number of steps required to fabricate memory cell array A, even though the number of stacked memory elements is eight times greater.

[0029] One embodiment of the present invention can provide a highly reliable storage device. Another embodiment of the present invention can provide a storage device with a large storage capacity. Another embodiment of the present invention can provide a storage device with a small footprint. Another embodiment of the present invention can provide a storage device with low manufacturing costs. Another embodiment of the present invention can provide a highly reliable semiconductor device. Another embodiment of the present invention can provide a semiconductor device with low manufacturing costs. Another embodiment of the present invention can provide a novel semiconductor device.

[0030] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one embodiment of the present invention does not need to possess all of these effects. Other effects will naturally become apparent from the description in the specification, drawings, and claims, and it is possible to extract other effects from the description in the specification, drawings, and claims. [Brief explanation of the drawing]

[0031] [Figure 1] Figures 1A and 1B are perspective views of the storage device. [Figure 2] Figure 2 is a cross-sectional view of the memory device. [Figure 3] Figure 3 is a cross-sectional view of a memory string. [Figure 4] Figure 4 is a circuit diagram of the memory string. [Figure 5] Figures 5A and 5B are cross-sectional views of the memory string. [Figure 6] Figure 6 is a cross-sectional view of the memory element. [Figure 7] Figures 7A and 7B are cross-sectional views of the memory string. [Figure 8] Figure 8 is a cross-sectional view of a memory string. [Figure 9] Figure 9A is a diagram illustrating the classification of crystal structures. Figure 9B is a diagram illustrating the XRD spectrum of the CAAC-IGZO film. Figure 9C is a diagram illustrating the micro-electron diffraction pattern of the CAAC-IGZO film. [Figure 10] Figures 10A to 10C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 11] Figures 11A to 11C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 12] Figures 12A to 12C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 13] Figures 13A to 13C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 14] Figures 14A to 14C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 15] Figures 15A to 15C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 16] Figures 16A to 16C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 17] Figures 17A to 17C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 18] Figures 18A to 18C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 19] Figures 19A to 19C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 20] Figures 20A to 20C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 21] Figures 21A to 21C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 22] Figures 22A to 22C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 23] Figures 23A to 23C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 24] Figures 24A to 24C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 25] Figures 25A to 25C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 26] Figures 26A to 26C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 27] Figures 27A to 27C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 28] Figures 28A to 28C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 29] Figures 29A to 29C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 30] Figures 30A to 30C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 31] Figures 31A to 31C are cross-sectional views illustrating the manufacturing process of a semiconductor device according to one aspect of the present invention. [Figure 32] Figure 32A is a schematic diagram of a multi-chamber type film deposition apparatus. Figure 32B is a cross-sectional view of the film deposition chamber. [Figure 33] Figures 33A to 33C illustrate an example of the configuration of an ALD device. [Figure 34] Figure 34 illustrates an example of a memory string circuit configuration. [Figure 35] Figure 35 illustrates an example of a memory string circuit configuration. [Figure 36] Figure 36 illustrates an example of a memory string circuit configuration. [Figure 37] Figure 37 illustrates an example of a memory string circuit configuration. [Figure 38] Figure 38 illustrates an example of a memory string circuit configuration. [Figure 39]Figure 39 is a timing chart illustrating an example of a memory string write operation. [Figure 40] Figures 40A and 40B are circuit diagrams illustrating an example of memory string writing operation. [Figure 41] Figures 41A and 41B are circuit diagrams illustrating an example of memory string writing operation. [Figure 42] Figure 42 is a timing chart illustrating an example of a memory string read operation. [Figure 43] Figures 43A and 43B are circuit diagrams illustrating an example of memory string read operation. [Figure 44] Figures 44A and 44B are circuit diagrams illustrating an example of memory string read operation. [Figure 45] Figure 45 is a circuit diagram illustrating an example of memory string read operation. [Figure 46] Figure 46 is a block diagram illustrating an example of a semiconductor device configuration. [Figure 47] Figures 47A to 47C are perspective views illustrating an example of a semiconductor device configuration. [Figure 48] Figure 48 is a cross-sectional view illustrating a semiconductor device according to one aspect of the present invention. [Figure 49] Figure 49 is a cross-sectional view illustrating a semiconductor device according to one aspect of the present invention. [Figure 50] Figure 50A is a perspective view illustrating an example of a computer configuration, and Figure 50B is a perspective view illustrating a monolithic IC. [Figure 51] Figures 51A and 51B illustrate the memory hierarchy of a computer and a monolithic IC, respectively. [Figure 52] Figure 52A is a schematic diagram of a semiconductor device. Figure 52B is a perspective view of the semiconductor device. [Figure 53] Figures 53A to 53E are diagrams illustrating an example of a storage device. [Figure 54] Figures 54A to 54G are diagrams illustrating an example of an electronic device. [Modes for carrying out the invention]

[0032] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the invention. Accordingly, the present invention is not to be interpreted as being limited to the contents of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are used in common across different drawings for the same parts or parts having similar functions, and the repetition of their descriptions is omitted.

[0033] Furthermore, the position, size, and scope of each component shown in the drawings may not represent the actual position, size, and scope in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings. For example, in the actual manufacturing process, resist masks and other materials may be unintentionally reduced due to processes such as etching, but this may not be reflected in the drawings for the sake of ease of understanding.

[0034] Furthermore, in drawings and other diagrams, descriptions of some components may be omitted to make the explanation easier to understand.

[0035] Furthermore, in this specification, the terms "electrode" and "wiring" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Moreover, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wiring" are formed as a single unit.

[0036] Furthermore, in this specification, the term "terminal" in an electrical circuit refers to a part where current is input or output, voltage is input or output, or a signal is received or transmitted. Therefore, a part of the wiring or electrode may function as a terminal.

[0037] In this specification, the terms "above" and "below" do not necessarily mean that the relative positions of the components are directly above or below each other and that they are in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0038] Furthermore, the functions of source and drain can be interchanged depending on operating conditions, such as when transistors of different polarities are used or when the direction of current changes during circuit operation, making it difficult to definitively determine which is the source and which is the drain. For this reason, in this specification, the terms source and drain may be used interchangeably.

[0039] Furthermore, in this specification, "electrically connected" includes both direct connections and connections made via "something that has some electrical function." Here, "something that has some electrical function" is not particularly limited as long as it enables the exchange of electrical signals between the connected objects. Therefore, even when it is expressed as "electrically connected," in a real circuit there may be no physical connection point, and only wiring may extend.

[0040] Furthermore, in this specification, "parallel" refers to a state in which, for example, two straight lines are positioned at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular" and "orthogonal" refer to a state in which, for example, two straight lines are positioned at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0041] In this specification and other documents, when referring to count values ​​and measured values, or to objects, methods, and events that can be converted to count values ​​or measured values, terms such as "identical," "same," "equal," or "uniform" shall include an error margin of plus or minus 20%, unless otherwise explicitly stated.

[0042] Furthermore, voltage often refers to the potential difference between a given potential and a reference potential (e.g., ground potential or source potential). Therefore, voltage and potential are often interchangeable. In this specification, unless otherwise specified, voltage and potential are considered interchangeable.

[0043] Even when the term "semiconductor" is used, if, for example, its conductivity is sufficiently low, it will possess the properties of an "insulator." Therefore, it is possible to replace "semiconductor" with "insulator." In this case, the boundary between "semiconductor" and "insulator" is ambiguous, and a strict distinction between the two is difficult. Consequently, "semiconductor" and "insulator" as used herein may be interchangeable.

[0044] Furthermore, even when the term "semiconductor" is used, if, for example, its conductivity is sufficiently high, it will possess the properties of a "conductor." Therefore, it is possible to replace "semiconductor" with "conductor." In this case, the boundary between "semiconductor" and "conductor" is ambiguous, and a strict distinction between the two is difficult. Consequently, "semiconductor" and "conductor" as used herein may be interchangeable.

[0045] Furthermore, ordinal numbers such as "first," "second," etc., in this specification are added to avoid confusion of constituent elements and do not indicate any order or rank, such as process order or layering order. In addition, even if an ordinal number is not used for a term in this specification, an ordinal number may be used in the claims to avoid confusion of constituent elements. In addition, even if an ordinal number is used for a term in this specification, a different ordinal number may be used in the claims. In addition, even if an ordinal number is used for a term in this specification, the ordinal number may be omitted in the claims, etc.

[0046] In this specification, the "on state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be electrically short-circuited (also called the "conducting state"). The "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be electrically disconnected (also called the "non-conducting state").

[0047] Furthermore, in this specification, "on-current" may refer to the current flowing between the source and drain when the transistor is in the "on" state. Also, "off-current" may refer to the current flowing between the source and drain when the transistor is in the "off" state.

[0048] Furthermore, in this specification, the high power supply potential VDD (hereinafter also simply referred to as "VDD," "H potential," or "H") refers to a power supply potential that is higher than the low power supply potential VSS (hereinafter also simply referred to as "VSS," "L potential," or "L"). Also, VSS refers to a power supply potential that is lower than VDD. In addition, the ground potential (hereinafter also simply referred to as "GND" or "GND potential") can be used as VDD or VSS. For example, if VDD is the ground potential, then VSS is a potential lower than the ground potential, and if VSS is the ground potential, then VDD is a potential higher than the ground potential.

[0049] Furthermore, unless otherwise specified, the transistors described herein are enhancement-type (normally-off type) n-channel field-effect transistors. Therefore, their threshold voltage (also called "Vth") shall be greater than 0V. Also, unless otherwise specified, "supplying a high potential to the gate of the transistor" may be synonymous with "turning the transistor ON." Also, unless otherwise specified, "supplying a low potential to the gate of the transistor" may be synonymous with "turning the transistor OFF."

[0050] Furthermore, in this specification, "gate" refers to the gate electrode and part or all of the gate wiring. Gate wiring refers to wiring that electrically connects the gate electrode of at least one transistor to another electrode or another wire.

[0051] Furthermore, in this specification, "source" refers to a source region, a source electrode, and part or all of the source wiring. The source region refers to a region of the semiconductor layer whose resistivity is below a certain value. The source electrode refers to the conductive layer in the portion connected to the source region. The source wiring refers to wiring used to electrically connect the source electrode of at least one transistor to another electrode or another wiring.

[0052] Furthermore, in this specification, "drain" refers to a drain region, a drain electrode, and part or all of the drain wiring. The drain region refers to a region of the semiconductor layer whose resistivity is below a certain value. The drain electrode refers to the conductive layer in the portion connected to the drain region. The drain wiring refers to wiring used to electrically connect the drain electrode of at least one transistor to another electrode or another wiring.

[0053] Furthermore, in drawings and other diagrams, to make the potential of wiring and electrodes easier to understand, a "H" indicating a high potential or a "L" indicating a low potential may be added adjacent to the wiring and electrodes. In addition, a "H" or "L" enclosed in a box may be added to wiring and electrodes where a potential change has occurred. Also, if a transistor is in the off state, an "×" symbol may be added superimposed on the transistor.

[0054] Furthermore, generally speaking, a "capacitance" has a configuration in which two electrodes face each other with an insulator (dielectric) in between. In this specification, the term "capacitive element" includes the case of the aforementioned "capacitance." That is, in this specification, the term "capacitive element" includes cases in which two electrodes face each other with an insulator in between, cases in which two wires face each other with an insulator in between, or cases in which two wires are arranged with an insulator in between.

[0055] Furthermore, in this specification, when the same reference numeral is used for multiple elements, and it is particularly necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "_2", "[n]", or "[m,n]". For example, the second conductor WWL may be described as conductor WWL[2].

[0056] (Embodiment 1) Figure 1A shows a perspective view of a semiconductor device 200 having a storage device 100 and a drive circuit 2000 according to one aspect of the present invention. The storage device 100 is a storage device having a three-dimensional stacked structure.

[0057] The drive circuit 2000 includes a WSL driver 2001, a WBL driver 2002, an RSL driver 2003, an RBL driver 2004, a WWL driver 2005, an RWL driver 2006, a SEL driver 2007, etc. The RBL driver 2004 may also function as a sense amplifier. Furthermore, the RSL driver 2003 may be connected to ground.

[0058] The WSL driver 2001 connects to the storage device 100 via wiring WSL_A. The WBL driver 2002 connects to the storage device 100 via wiring WBL_A. The RSL driver 2003 connects to the storage device 100 via wiring RSL_A. The RBL driver 2004 connects to the storage device 100 via wiring RBL_A. The WWL driver 2005 connects to the storage device 100 via either wiring WWL_A or wiring SG_A, or both. The RWL driver 2006 connects to the storage device 100 via wiring RWL_A. The SEL driver 2007 connects to the storage device 100 via wiring SEL_A. Additionally, wiring BG_A connects to the back gate of the storage device 100.

[0059] The memory device 100 is preferably provided above the layer on which the drive circuit 2000 is provided. Furthermore, as shown in Figure 1B, it is preferable to provide the memory device 100 so as to overlap with a part of the drive circuit, as this reduces the area occupied by the semiconductor device 200. When the memory device 100 and the drive circuit are overlapped, the entire drive circuit may overlap with the memory device 100, or only a part of the drive circuit may overlap. Alternatively, the memory device 100 may overlap with a specific circuit of the drive circuit. For example, the sense amplifier can be positioned so that the memory device 100 overlaps with the sense amplifier.

[0060] One aspect of the present invention is a semiconductor device 200 that has a wiring WSL_A that functions as a source line for writing and a wiring RSL_A that functions as a source line for reading, but is not limited to this. Wiring WSL_A and wiring RSL_A may be connected to each other and connected to a drive circuit that functions as a source line driver.

[0061] One aspect of the present invention is a semiconductor device 200 that includes a wiring WBL_A that functions as a bit line for writing and a wiring RBL_A that functions as a bit line for reading, but is not limited to this. Wirings WBL_A and RBL_A may be connected to each other and connected to a drive circuit that functions as a bit line driver.

[0062] Note that in Figure 1A and other diagrams, arrows indicating the X, Y, and Z directions may be included. The X, Y, and Z directions are all orthogonal to each other. In this specification, one of the X, Y, or Z directions may be referred to as the "first direction" or "first direction." Another may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction." In this specification, the direction perpendicular to the upper surface of the base 121, which will be described later, is defined as the Z direction.

[0063] Figure 2 shows a cross-section in the XZ plane. Figure 2 is a cross-sectional view of the area A1-A2, indicated by the dashed line in Figure 1, and the connection point between the conductor SEL and the wiring. As mentioned above, some components may be omitted in Figures 1 and 2, etc., for the sake of clarity.

[0064] <Example of a storage device configuration> A storage device 100 according to one aspect of the present invention has a memory cell array 110. The memory cell array 110 has a plurality of memory strings 120. The memory strings 120 extend in the Z direction and are arranged in a matrix on the XY plane.

[0065] Figure 3 shows an example of a cross-sectional configuration of a memory string 120 according to one aspect of the present invention, and Figure 4 shows the corresponding circuit diagram. The memory string 120 has a configuration in which multiple memory elements MC (also called "memory cells") are connected in series. In this embodiment, the case in which five memory elements MC are connected in series is shown, but the number of memory elements MC in the memory string 120 is not limited to five. If the number of memory elements MC in the memory string 120 is n, then n can be an integer of 2 or more.

[0066] Furthermore, the memory string 120 has multiple conductors WWL, multiple conductors RWL, conductor SG, and conductor SEL. Note that the conductor WWL functions as part of wiring WWL_A, the conductor RWL functions as part of wiring RWL_A, the conductor SG functions as part of wiring SG_A, and the conductor SEL functions as part of wiring SEL_A. The multiple conductors WWL and multiple conductors RWL are arranged alternately in layers via an insulator 123. The conductor SG is provided in a lower layer than the multiple conductors WWL and multiple conductors RWL. Below the conductor SG, a conductor WSL is provided, and below the conductor WSL, a conductor RSL is provided. The conductor SEL is provided in a higher layer than the multiple conductors WWL and multiple conductors RWL. Above the conductor SEL, a conductor WBL is provided, and above the conductor WBL, a conductor RBL is provided.

[0067] In Figures 3 and 4, the five memory elements MC are shown as memory element MC[1] through memory element MC[5]. When describing things common to memory elements MC[1] through memory element MC[5], they are simply referred to as "memory element MC". The same applies to other components such as the conductor WWL, conductor RWL, and insulator 123.

[0068] The memory string 120 has a transistor STr1 connected to the memory element MC[1] and a transistor STr2 connected to the memory element MC[5].

[0069] Conductors WWL, RWL, SG, and SEL extend beyond the memory cell array 110 in the X-axis direction. Furthermore, conductors WWL, RWL, SG, and SEL are stacked in a stepped manner outside the memory cell array 110 (see Figures 1 and 2). Meanwhile, conductors WSL, RSL, WBL, and RBL extend beyond the memory cell array 110 in the Y-axis direction (see Figures 1 and 3).

[0070] Figure 5A shows a cross-section of the XY plane, including the region B1-B2 indicated by the dashed-dotted line in Figure 3, viewed from the Z direction. Figure 5B shows a cross-section of the XY plane, including the region C1-C2 indicated by the dashed-dotted line in Figure 3, viewed from the Z direction. Figure 6 shows an enlarged view of region 105, indicated by the double-dotted-dotted line in Figure 3. Figure 6 corresponds to a cross-sectional view of the memory element MC.

[0071] The memory string 120 has a conductive RSL on the base 121 that functions as part of the wiring RSL_A, and a conductive WSL on the conductive RSL that functions as part of the wiring WSL_A via an insulator 118. For the base 121, an insulator may be used, for example. Furthermore, the conductive WSL has insulator 123[1], conductive SG, insulator 123[2], conductive RWL[1], insulator 123[3], conductive WWL[1], insulator 123[4], conductive RWL[2], insulator 123[5], conductive WWL[2], insulator 123[6], conductive RWL[3], insulator 123[7], conductive WWL[3], insulator 123[8], conductive RWL[4], insulator 123[9], conductive WWL[4], insulator 123

[10] , conductive RWL[5], insulator 123

[11] , conductive WWL[5], insulator 123

[12] , and conductive SEL (see Figure 3). Furthermore, the conductive SEL has a conductive WBL that functions as part of the wiring WBL_A via an insulator 138, and the conductive RBL that functions as part of the wiring RBL_A via an insulator 186.

[0072] Furthermore, the memory string 120 consists of insulator 118, conductor WSL, insulator 123[1], conductor SG, insulator 123[2], conductor RWL[1], insulator 123[3], conductor WWL[1], insulator 123[4], conductor RWL[2], insulator 123[5], conductor WWL[2], insulator 123[6], conductor RWL[3], insulator 123[7], conductor WWL[3], insulator 123[8], conductor RWL[4], insulator 123[9], conductor WWL[4], insulator 123

[10] , conductor RWL[5], insulator 123

[11] , conductor WWL[5], insulator 123

[12] , conductor SEL, insulator 138, and conductor WBL. It has an opening 141 formed by removing a portion of the insulator 186 and the conductor RBL, respectively.

[0073] The opening 141 extends in the Z direction and reaches the conductor WSL and the conductor RSL. Furthermore, in the opening 141, the diameter of the region 142 overlapping with the conductor RWL is larger than the diameter of the region 143 overlapping with the conductor WWL. Therefore, the side surface of the opening 141 has an uneven shape.

[0074] Furthermore, an insulator 124 and a semiconductor 125 are provided along the side surface of the opening 141. The semiconductor 125 has a region that overlaps with the side surface of the opening 141 via the insulator 124.

[0075] Furthermore, the memory string 120 has a conductor 130 extending in the Z direction. The conductor 130 is located at or near the center of the opening 141. In addition, an insulator 129, a semiconductor 127, and an insulator 126 are provided in the region of the conductor 130 that overlaps with the side surface of the opening 141. The semiconductor 127 has a region that overlaps with the side surface of the conductor 130 via the insulator 129. The insulator 126 has a region that overlaps with the side surface of the conductor 130 via the insulator 129 and the semiconductor 127. Furthermore, at the bottom of the opening 141, the semiconductor 127 has a region that is electrically connected to the conductor RSL, and at the top of the opening 141, the semiconductor 127 has a region that is electrically connected to the conductor RBL. Furthermore, at the bottom of the opening 141, the semiconductor 125 has a region that is electrically connected to the conductor WSL, and at the top of the opening 141, the semiconductor 125 has a region that is electrically connected to the conductor WBL. Furthermore, at the bottom of the opening 141, the conductor 130 has a region that overlaps with the conductor RSL via the insulator 129 and the semiconductor 127. In addition, in the region where the conductor RWL and the conductor 130 overlap, a conductor 128 is provided between the semiconductor 125 and the insulator 126.

[0076] Between the conductor WWL and the conductor 130, insulators 124, semiconductor 125, insulator 126, semiconductor 127, and insulator 129 are provided in order from the conductor WWL side (see Figure 5A). Between the conductor RWL and the conductor 130, insulators 124, semiconductor 125, conductor 128, insulator 126, semiconductor 127, and insulator 129 are provided in order from the conductor RWL side (see Figure 5B).

[0077] The memory element MC has a transistor WTr and a transistor RTr (see Figure 6). The region where the conductor WWL and the conductor 130 overlap functions as the transistor WTr. The conductor WWL functions as the gate electrode of the transistor WTr, and the conductor 130 functions as the back gate electrode of the transistor WTr. In addition, a part of the semiconductor 125 functions as the semiconductor layer in which the channel of the transistor WTr is formed. The semiconductor layer in which the channel of the transistor WTr is formed overlaps with the gate electrode (conductor WWL) via a part of the insulator 124. In this embodiment, an example is shown in which a part of the conductor WWL functions as the gate electrode, but the gate electrode and the conductor WWL may be provided independently and electrically connected to each other.

[0078] The region where conductor 128, conductor RWL, and conductor 130 overlap functions as transistor RTr. Conductor RWL functions as the gate electrode of transistor RTr. Conductor 130 also functions as the back gate electrode of transistor RTr. A portion of semiconductor 127 functions as the semiconductor layer where the channel of transistor RTr is formed. The semiconductor layer where the channel of transistor RTr is formed overlaps with the gate electrode (conductor RWL) via portions of insulator 126, conductor 128, semiconductor 125, and insulator 124. The semiconductor layer where the channel of transistor RTr is formed overlaps with the back gate electrode (conductor 130) via a portion of insulator 129.

[0079] One source and drain of transistor STr1 is electrically connected to semiconductor 125 of transistor WTr. The other source and drain of transistor STr1 is electrically connected to conductor WSL. Also, one source and drain of transistor STr2 is electrically connected to semiconductor 127 of transistor RTr. The other source and drain of transistor STr2 is electrically connected to conductor RBL. Also, one source and drain of transistor STr3 is electrically connected to semiconductor 125 of transistor WTr. The other source and drain of transistor STr3 is electrically connected to conductor WBL. Here, conductor SEL functions as the gate of transistors STr2 and STr3 (see Figures 3 and 4). Furthermore, a portion of semiconductor 127 functions as the semiconductor layer in which the channel of transistor STr2 is formed, and a portion of semiconductor 125 functions as the semiconductor layer in which the channel of transistor STr3 is formed.

[0080] Here, let's explain the back gate. The gate and back gate are positioned to overlap via the channel formation region of the semiconductor layer. The back gate can function similarly to the gate. Furthermore, the threshold voltage of the transistor can be changed by changing the potential of the back gate. One of the gate or back gate is sometimes referred to as the "first gate" or "first gate," and the other as the "second gate" or "second gate."

[0081] Since the gate and back gate are formed from conductive layers or semiconductor layers with low resistivity, they have the function of preventing electric fields generated outside the transistor from acting on the semiconductor layer where the channel is formed (particularly an electrostatic shielding function against static electricity). In other words, it is possible to prevent the electrical characteristics of the transistor from fluctuating due to the influence of external electric fields such as static electricity.

[0082] Furthermore, the threshold voltage of the transistor can be controlled by controlling the potential of the back gate. The potential of the back gate may be the same as the gate potential, or it may be the ground potential (GND potential) or any other potential.

[0083] The semiconductor layer in which the channels of transistors WTr and RTr are formed can be single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors, either individually or in combination. Examples of semiconductor materials include silicon and germanium. Compound semiconductors such as silicon-germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors may also be used. The same applies to transistors STr1, STr2, and STr3.

[0084] Furthermore, the semiconductor layers used in the transistor may be stacked. When stacking semiconductor layers, semiconductors having different crystalline states may be used for each layer, or different semiconductor materials may be used for each layer.

[0085] The semiconductor layer used in transistors WTr, RTr, STr1, STr2, and STr3 is preferably an oxide semiconductor containing a metal oxide. Transistors using a metal oxide as the semiconductor layer exhibit higher field-effect mobility compared to transistors using amorphous silicon as the semiconductor layer. Furthermore, in transistors using polycrystalline silicon as the semiconductor layer, there is a risk of grain boundaries forming in the semiconductor layer. At grain boundaries, carriers can be trapped, which is likely to cause a decrease in the transistor's on-current and field-effect mobility. On the other hand, as will be described in detail later, oxide semiconductors can realize crystal structures in which no clear grain boundaries are observed, or crystal structures with extremely few grain boundaries. Using such an oxide semiconductor as the semiconductor layer is preferable because it enables the realization of transistors with good electrical characteristics, such as high on-current and field-effect mobility.

[0086] In this embodiment, an oxide semiconductor is used with a composition of In:Ga:Zn=1:3:4 [atomic ratio] or nearby, In:Ga:Zn=4:2:3 [atomic ratio] or nearby, In:Ga:Zn=1:1:1 [atomic ratio] or nearby, or In:Ga:Zn=1:1:0.5 [atomic ratio] or nearby.

[0087] Furthermore, oxide semiconductors, particularly crystalline oxide semiconductors like CAAC-IGZO, possess a characteristic structure in which nanoclusters of several nanometers (e.g., 1-3 nm) are interconnected, with the c-axis oriented perpendicular to the surface being formed. Therefore, it is possible to form a crystalline structure in which no clear grain boundaries are observed, even within openings extending in the Z direction.

[0088] In particular, the transistor WTr is preferably a transistor (also called an "OS transistor") that uses an oxide semiconductor, a type of metal oxide, in the semiconductor layer where the channel is formed. Since oxide semiconductors have a band gap of 2 eV or more, the off-current is remarkably low. Here, the node ND is defined as the node where the conductor 128 and either the source or drain of the transistor WTr are electrically connected. When an OS transistor is used for the transistor WTr, the charge written to node ND can be retained for a long period of time. When an OS transistor is used for the transistor constituting the memory element MC, the memory element MC can be called an "OS memory". The memory string 120 including the memory element MC can also be called an "OS memory". The storage device 100 can also be called an "OS memory".

[0089] OS memory can retain information written to it for more than a year, or even more than 10 years, even when the power supply is cut off. Therefore, OS memory can be considered non-volatile memory.

[0090] Furthermore, because the amount of charge written to OS memory does not change easily over a long period of time, OS memory can store not only binary (1-bit) information but also multi-level (multi-bit) information.

[0091] Furthermore, because OS memory writes charge to nodes via transistors, it does not require the high voltage necessary for conventional flash memory, enabling high-speed writing operations. Also, the erase operation performed before data rewriting, which is necessary for flash memory, is unnecessary for OS memory. In addition, since no charge injection or extraction is performed to the floating gate or charge trapping layer, OS memory can write and read data virtually an unlimited number of times. Compared to conventional flash memory, OS memory exhibits less degradation and offers high reliability.

[0092] Furthermore, OS memory does not involve structural changes at the atomic level, unlike magnetoresistive memory (MRAM) or resistive random-access memory (ReRAM). Therefore, OS memory has superior rewrite endurance compared to magnetoresistive memory and resistive random-access memory.

[0093] Furthermore, OS transistors exhibit almost no increase in off-current even in high-temperature environments. Specifically, the off-current hardly increases even at ambient temperatures between room temperature and 200°C. Additionally, the on-current does not easily decrease even in high-temperature environments. Memory devices including OS memory operate stably and with high reliability even in high-temperature environments. OS transistors also have high dielectric strength between the source and drain. By using OS transistors in semiconductor devices, stable and highly reliable semiconductor devices can be realized even in high-temperature environments.

[0094] It is preferable that semiconductor 127 is an n-type semiconductor. Furthermore, it is preferable that the region of semiconductor 125 that overlaps with the conductor WWL is an i-type or substantially i-type semiconductor. In this case, transistor WTr is an enhancement-type (normally-off) transistor, and transistor RTr is a depletion-type (normally-on) transistor.

[0095] Furthermore, semiconductors 125 and 127 may be made of the same material or different materials. For example, semiconductors 125 and 127 may each be oxide semiconductors. Alternatively, semiconductors 125 and 127 may each be silicon-containing semiconductors. Alternatively, semiconductor 125 may be an oxide semiconductor and semiconductor 127 may be a silicon-containing semiconductor. Alternatively, semiconductor 125 may be a silicon-containing semiconductor and semiconductor 127 may be an oxide semiconductor.

[0096] Figure 5A corresponds to the XY plane at or near the center of transistor WTr, and Figure 5B corresponds to the XY plane at or near the center of transistor RTr. In Figures 5A and 5B, when the cross-sectional shape of the conductor 130 is circular, the insulator 129 is provided as a concentric layer on the outside of the conductor 130, the semiconductor 127 is provided as a concentric layer on the outside of the insulator 129, the insulator 126 is provided as a concentric layer on the outside of the semiconductor 127, the semiconductor 125 is provided as a concentric layer on the outside of the insulator 126, and the insulator 124 is provided as a concentric layer on the outside of the semiconductor 125. In addition, the conductor 128 is provided as a concentric layer between the insulator 126 and the semiconductor 125.

[0097] Furthermore, the cross-sectional shape of the conductor 130 is not limited to a circle. As shown in Figure 7A, the cross-sectional shape of the conductor 130 may be rectangular. Also, as shown in Figure 7B, the cross-sectional shape of the conductor 130 may be triangular.

[0098] Furthermore, although the above example shows semiconductor 125 electrically connected to conductor WSL and semiconductor 127 electrically connected to conductor RSL at the bottom of memory string 120, this embodiment is not limited to this.

[0099] As shown in Figure 8, two adjacent memory strings in the Y-axis direction can be electrically connected to form a single memory string 120A. In memory string 120A, memory string 120_1 and memory string 120_2 are electrically connected by conductors 119 and 122.

[0100] At the top of memory string 120_1, semiconductor 125 and conductor WSL are electrically connected, and semiconductor 127 and conductor RSL are electrically connected. At the top of memory string 120_2, semiconductor 125 and conductor WBL are electrically connected, and semiconductor 127 and conductor RBL are electrically connected. At the bottom of memory strings 120_1 and 120_2, each semiconductor 125 is electrically connected via conductor 119, and each semiconductor 127 is electrically connected via conductor 122.

[0101] The memory string 120A has memory elements MC[1] to MC

[10] extending from the conductor WSL and conductor RSL side toward the conductor WBL and conductor RBL side. Memory elements MC[5] and MC[6] are electrically connected via conductors 119 and 122.

[0102] Furthermore, the memory string 120 can also be referred to as a memory device, and the memory element MC can also be referred to as a memory device.

[0103] [Materials used in semiconductor devices] Next, we will describe the constituent materials that can be used in the memory device 100.

[0104] [substrate] The memory device 100 is provided on a substrate 121. The substrate 121 can be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there may be substrates containing metal nitrides or metal oxides. Furthermore, there are substrates in which a conductor or semiconductor is provided on an insulating substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates on which elements are provided may be used. Elements provided on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0105] [Insulator] Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0106] In this specification, "oxide nitride" refers to a material in which the oxygen content is higher than the nitrogen content as the main component. For example, "silicon oxide nitride" refers to a material containing silicon, nitrogen, and oxygen in which the oxygen content is higher than the nitrogen content. Also, in this specification, "nitride oxide" refers to a material in which the nitrogen content is higher than the oxygen content as the main component. For example, "aluminum oxide nitride" refers to a material containing aluminum, nitrogen, and oxygen in which the nitrogen content is higher than the oxygen content.

[0107] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0108] Furthermore, examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0109] Insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, or resins.

[0110] Furthermore, the electrical properties of an OS transistor can be stabilized by surrounding it with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride, and silicon nitride can be used.

[0111] Furthermore, when an oxide semiconductor is used for semiconductor 125 and / or semiconductor 127, the insulator that functions as a gate insulator is preferably an insulator that has a region containing oxygen that is desorbed by heating. For example, by making a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating is in contact with semiconductor 125 and / or semiconductor 127, the oxygen vacancies in semiconductor 125 and / or semiconductor 127 can be compensated for.

[0112] [conductor] As the conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0113] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0114] Furthermore, when using an oxide semiconductor, a type of metal oxide, in the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0115] In particular, it is preferable to use a conductive material containing a metal element in the oxide semiconductor in which the channel is formed, and oxygen, as the conductor functioning as the gate electrode. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-doped indium tin oxide may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the oxide semiconductor in which the channel is formed. Alternatively, it may be possible to capture hydrogen introduced from an external insulator or the like.

[0116] [Oxide Semiconductors] It is preferable to use metal oxides (oxide semiconductors) that function as semiconductors as semiconductor 125 and semiconductor 127. The following describes oxide semiconductors applicable to semiconductor 125 and semiconductor 127.

[0117] The oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable that it contains indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0118] Here, we consider the case where the oxide semiconductor is an In-M-Zn oxide containing indium, element M, and zinc. Element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc. Other elements that can be used for element M include boron, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, in some cases, multiple elements from the aforementioned list may be combined as element M.

[0119] In this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be called metal oxynitrides.

[0120] [Classification of crystal structures] First, we will explain the classification of crystal structures in oxide semiconductors using Figure 9A. Figure 9A is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO (a metal oxide containing In, Ga, and Zn).

[0121] As shown in Figure 9A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous materials. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite) (excluding single crystal and polycrystal). Note that single crystal, polycrystal, and completely amorphous materials are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal materials.

[0122] The structure within the thick frame shown in Figure 9A represents an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from the energetically unstable "Amorphous" and "Crystal" states.

[0123] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 9B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 9B will simply be referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 9B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 9B is 500 nm.

[0124] As shown in Figure 9B, the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ=31°. As shown in Figure 9B, the peak near 2θ=31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0125] Furthermore, the crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 9C. Figure 9C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 9C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0126] As shown in Figure 9C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0127] [Structure of oxide semiconductors] Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 9A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0128] Next, we will explain the details of the aforementioned CAAC-OS, nc-OS, and a-like OS.

[0129] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0130] Each of the multiple crystalline regions described above is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of that crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0131] Furthermore, in In-M-Zn oxides, CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Also, the In layer may contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0132] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the c-axis orientation peak (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0133] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0134] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction, and the bond distance between atoms changes due to the substitution of metal atoms.

[0135] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more than In oxide.

[0136] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities or the generation of defects, CAAC-OS can be considered an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0137] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0138] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0139] [Oxide semiconductor configuration] Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0140] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing these metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0141] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0142] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0143] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0144] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0145] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0146] When using CAC-OS in a transistor, the conductivity caused by the first region and the insulating property caused by the second region act complementarily, enabling the function of switching (On / Off function) to be imparted to the CAC-OS. That is, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and has a semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximally enhanced. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), a high field-effect mobility (μ), and a good switching operation can be achieved.

[0147] Oxide semiconductors have various structures and each has different characteristics. The oxide semiconductor of one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0148] [Transistor having an oxide semiconductor] Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0149] By using the above oxide semiconductor in a transistor, a transistor with a high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0150] It is preferable to use an oxide semiconductor with a low carrier concentration in the channel formation region of the transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is preferably 1×10 18 cm -3 or less, more preferably 1×10 17 cm -3 or less, even more preferably 1×10 16 cm -3 or less, even more preferably 1×10 13 cm -3 or less, even more preferably 1×10 12 cm-3 It is even more preferable that the value be less than [value]. When the carrier concentration of an oxide semiconductor film is reduced, the impurity concentration in the oxide semiconductor film is reduced to lower the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Furthermore, an oxide semiconductor with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Also, high-purity intrinsic or substantially high-purity intrinsic may be referred to as type i or substantially type i.

[0151] Furthermore, oxide semiconductor films that are highly pure or substantially highly pure have a low defect level density, which may result in a low trap level density.

[0152] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0153] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of the transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0154] 〔impurities〕 Here, we will explain the effects of various impurities in oxide semiconductors.

[0155] In oxide semiconductors, the presence of silicon or carbon, which are Group 14 elements, leads to the formation of defect levels in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon near the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are compared by 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0156] Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0157] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm3 Do the following:

[0158] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. When hydrogen fills these oxygen vacancies, electrons, which act as carriers, may be generated. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to minimize the amount of hydrogen in the channel formation region of the oxide semiconductor. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 5 × 10 19 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0159] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0160] [Other semiconductor materials] The semiconductor materials that can be used for semiconductors 125 and 127 are not limited to the oxide semiconductors described above. Semiconductor materials having a band gap (semiconductor materials that are not zero-gap semiconductors) may be used as semiconductors 125 and 127. For example, semiconductors of single elements such as silicon, compound semiconductors such as gallium arsenide, and layered materials that function as semiconductors (also called atomic layer materials, two-dimensional materials, etc.) may be used as semiconductor materials. In particular, it is preferable to use layered materials that function as semiconductors as semiconductor materials.

[0161] In this specification, "layered material" refers to a general term for materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked via weaker bonds than covalent or ionic bonds, such as van der Waals forces. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, it is possible to provide a transistor with a large on-current.

[0162] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens. Chalcogens are a general term for elements belonging to Group 16, and include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0163] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as semiconductor 125 and semiconductor 127. Specific examples of transition metal chalcogenides applicable as semiconductor 125 and semiconductor 127 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0164] <Example of a method for manufacturing a storage device> Next, an example of a method for manufacturing a memory device according to the present invention will be described with reference to Figures 10A to 31C. In Figures 10A to 31C, A is a top view seen from the Z direction, B is a cross-sectional view of the area indicated by the dashed line A1-A2 in A, and C is a cross-sectional view of the area indicated by the dashed line A3-A4 in A. In this manufacturing method, an example is shown in which two memory strings 120 having two (also called "two-stage") memory elements MC are manufactured, but this embodiment is not limited to this. The memory string 120 may have three or more stages of memory elements MC. For example, it is preferable that the memory string 120 has 32 or more stages of memory elements MC, preferably 64 or more stages, more preferably 128 or more stages, and even more preferably 256 or more stages of memory elements MC.

[0165] First, a conductor 122 is formed on a substrate 121 having an insulating surface, and an insulator 132 is formed around the conductor 122 (see Figures 10A to 10C).

[0166] Specifically, a conductive film is formed, and the conductive film is processed using lithography to form a conductor 122. Next, an insulating film is formed on the substrate 121 so as to cover the conductor 122. Next, it is preferable to perform a planarization treatment on the insulating film. In this planarization treatment, it is preferable to polish the insulating film until the surface of the conductor 122 is exposed. An insulator 132 can be formed by the above method. However, the method of forming the conductor 122 and the insulator 132 is not limited to this. An insulator 132 may be formed on the substrate 121, and grooves or openings may be formed by removing unnecessary parts of the insulator 132, and the conductor 122 may be embedded in these grooves or openings. Such a method of forming a conductor is sometimes called the damascene method (single damascene method, dual damascene method). The structure shown in Figures 10A to 10C can be obtained by the above method.

[0167] The conductor 122 and the insulator 132 can be formed using methods such as sputtering, CVD, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or atomic layer deposition (ALD).

[0168] Furthermore, CVD methods can be classified into plasma-enhanced CVD (PECVD), which utilizes plasma; thermal CVD (TCVD), which utilizes heat; and photo-CVD (Photo-CVD), which utilizes light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD) depending on the source gas used.

[0169] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and elements (transistors, capacitive elements, etc.) contained in semiconductor devices can be charged up by receiving charge from the plasma. In this case, the accumulated charge can destroy the wiring, electrodes, and elements contained in the semiconductor device. In contrast, thermal CVD, which does not use plasma, does not cause such plasma damage, thus increasing the yield of semiconductor devices. Furthermore, because thermal CVD does not cause plasma damage during film formation, films with fewer defects can be obtained.

[0170] ALD methods include thermal ALD, which uses only thermal energy to carry out the reaction between the precursor and reactant, and PEALD (Plasma Enhanced ALD), which uses plasma-excited reactants.

[0171] Furthermore, the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, resulting in advantages such as the ability to deposit extremely thin films, deposit films on structures with high aspect ratios, deposit films with fewer defects such as pinholes, deposit films with excellent coverage, and deposit films at low temperatures. In the PEALD method, the use of plasma allows for even lower temperature deposits, which can be preferable in some cases.

[0172] Unlike film deposition methods where particles emitted from a target or other source are deposited, CVD and ALD methods form films through reactions on the surface of the workpiece. Therefore, they are less affected by the shape of the workpiece and offer good step-level coverage. In particular, the ALD method is suitable for coating the surface of openings with high aspect ratios due to its excellent step-level coverage and uniform thickness. However, because the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods that have a faster deposition rate, such as the CVD method.

[0173] The CVD method allows for control over the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, CVD allows for the deposition of films with any desired composition by changing the flow rate ratio of the source gases. Furthermore, CVD allows for the deposition of films with continuously changing compositions by varying the flow rate ratio of the source gases during deposition. When deposition is carried out while varying the flow rate ratio of the source gases, the deposition time can be reduced compared to deposition using multiple deposition chambers by eliminating the time required for transport and pressure adjustment. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0174] Furthermore, the ALD method allows for the deposition of films of any desired composition by simultaneously introducing multiple precursors of different compositions, or by controlling the number of cycles for each precursor.

[0175] In lithography, the resist is first exposed through a photomask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, the conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask. For example, the resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Alternatively, immersion technology can be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, electron beams or ion beams can be used instead of the aforementioned light. When using electron beams or ion beams, a photomask is not required. For removing the resist mask, dry etching such as ashing, wet etching, or a combination of dry etching and wet etching can be used. When using a combination of dry etching and wet etching, the wet etching may be performed after the dry etching, or the dry etching may be performed after the wet etching.

[0176] Alternatively, a hard mask made of an insulator or conductor may be used instead of a resist mask. When using a hard mask, an insulating film or conductive film that will serve as the hard mask material is formed on a conductive film, a resist mask is formed on top of that, and the hard mask material is etched to form a hard mask of the desired shape.

[0177] The above processing can be performed using either dry etching or wet etching methods. Dry etching is suitable for microfabrication.

[0178] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency power supply to one of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency power supplies to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high-frequency power supply of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency power supplies of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. A dry etching apparatus having a high-density plasma source may be, for example, an inductively coupled plasma (ICP) etching apparatus.

[0179] When a hard mask is used for etching a conductive film, the etching process may be performed either after removing the resist mask used to form the hard mask, or with the resist mask still in place. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching the conductive film. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not always necessary to remove the hard mask.

[0180] The conductive film that forms the conductor 122 is preferably formed by sputtering, creating a conductive film containing metal elements. Alternatively, it can be formed using CVD.

[0181] Preferably, the surface of the insulator 132 is planarized as needed. Chemical mechanical polishing (CMP) or reflow can be used for the planarization process.

[0182] An insulator 118 is formed on the conductor 122 and the insulator 132. The insulator 118 is a material that can be used for the insulator 132 and can be formed using a method that can be used for forming the insulator 132.

[0183] Conductors 119 and insulators 117 are formed on the insulator 118 (see Figures 10A to 10C). Conductors 119 and insulators 117 are materials that can be used for conductors 122 and insulators 132, respectively, and can be formed using methods that can be used for forming conductors 122 and insulators 132.

[0184] An insulating film 123A, a conductive film 134A, and a conductive film 136A are alternately laminated on a conductor 119 and an insulator 117. In this embodiment, an example is shown in which the insulating film 123A is formed on the conductor 119 and the insulator 117, the conductive film 134A is formed on the insulating film 123A, the insulating film 123A is formed on the conductive film 134A, and the conductive film 136A is formed on the insulating film 123A (see Figures 10A to 10C). CVD can be used to form the conductive film 134A, the conductive film 136A, and the insulating film 123A. Alternatively, sputtering may be used.

[0185] As conductor 122, conductor 119, conductive film 134A, and conductive film 136A, conductive materials such as silicon with impurities added or metals can be used. Since conductor 136 needs to be selectively etched against conductors 119 and conductor 134 in a subsequent process, it is preferable that conductive film 136A is made of a different material from conductor 122, conductor 119, and conductive film 134A. On the other hand, conductor 122, conductor 119, and conductive film 134A may be made of the same material or different materials. When silicon with impurities added is used as conductor 122, conductor 119, conductive film 134A, or conductive film 136A, amorphous silicon or polysilicon can be used. Furthermore, p-type impurities or n-type impurities can be used as impurities added to silicon. Furthermore, as a conductive material containing silicon, silicides containing titanium, cobalt, or nickel can be used as conductor 122, conductive film 134A, or conductive film 136A. In addition, when a metallic material is used as conductor 122, conductive film 134A, or conductive film 136A, a material containing one or more metallic elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used.

[0186] Alternatively, one of the conductive films 134A and 136A may be used as a dummy layer. The dummy layer is preferably made of a material that can selectively etch the conductor 122, insulator 118, conductor 119, insulator 123, and the other conductive film 134A and 136A. For example, silicon nitride or silicon oxide nitride can be used. In a subsequent process, the dummy layer can be removed, and a conductor can be formed in the area where the dummy layer was removed, thereby forming one of the conductors 134 and 136.

[0187] As insulators 132, 118, 117, and insulating film 123A, insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, metal nitride oxides, etc., can be used. Silicon oxide, silicon oxidized nitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, porous silicon oxide or resin, aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium can be used.

[0188] Since the conductor 136 needs to be selectively etched with respect to the conductor 137, conductor 134, conductor 119, insulator 138, and insulator 123 in a subsequent process, it is preferable that the conductive film 136A is made of a material that allows selective etching with respect to the conductive film 134A, the conductive film 134A, the insulator 138, and the insulating film 123A. For example, it is preferable that the conductive film 136A is made of a different material from the conductive film 134A, and that the insulator 138 and the insulating film 123A are made of silicon oxide or silicon oxynitride.

[0189] Furthermore, although this embodiment shows an example in which 6 layers of insulating film 123A, 3 layers of conductive film 134A, and 2 layers of conductive film 136A are formed, the number of layers is not limited to this. They can be formed according to the required performance of the semiconductor device. Here, if the number of layers of conductive film 134A is m (where m is an integer of 2 or more), then the number of layers of insulating film 123A is 2 × m, and the number of layers of conductive film 136A is m-1. For example, m can be 33 or more, preferably 65 or more, more preferably 129 or more, and even more preferably 257 or more.

[0190] A conductive film 137A is formed on the uppermost insulating film 123A, and an insulating film 138A is formed on the conductive film 137A. The conductive film 137A can be formed using the same method and materials as the conductive film 134A. Similarly, the insulating film 138A can be formed using the same method and materials as the insulating film 123A.

[0191] Next, the insulating film 138A, conductive film 137A, insulating film 123A, conductive film 134A, and conductive film 136A are processed to form stepped insulators 138B, conductors 137B, insulators 123B, conductors 134B, and conductors 136B as shown in Figure 11B (see Figures 11A to 11C). In processing the insulating film 138A, conductive film 137A, insulating film 123A, conductive film 134A, and conductive film 136A, the stepped insulators 138B, conductors 137B, conductive film 137A, insulating film 123A, conductive film 134A, and conductive film 136A are processed alternately with mask slimming to form the stepped insulators 138B, conductors 137B, insulators 123B, conductors 134B, and conductors 136B.

[0192] Next, the insulator 150 is formed (see Figures 11A to 11C). The insulator 150 can be formed using the CVD method. Preferably, the insulator 150 is planarized using the CMP method or the reflow method.

[0193] Next, insulators 150, 138B, 137B, 123B, 134B, and 136B are processed to form grooves, thereby obtaining insulators 138, 137, 123, 134, and 136. (See Figures 12A to 12C.)

[0194] In this case, if a dummy layer is used in either the conductive film 134A or the conductive film 136A, the dummy layer may be removed from the side surface exposed by the above processing, and a conductor may be formed in the area where the dummy layer was removed. In this case, if a conductor is also formed inside the groove, this conductor is removed. Note that the removal of the dummy layer and the formation of the conductor may be carried out in a later step.

[0195] Next, an insulator 152 is formed to fill the groove portion (see Figures 12A to 12C). The insulator 152 can be formed using CVD or ALD. In particular, the ALD method is preferred because it can form a film of uniform thickness even for grooves and openings with a large aspect ratio. Alternatively, the insulator 152 may be formed by combining the ALD method and the CVD method. It is preferable that the insulator 152 be planarized using CMP or reflow.

[0196] Next, conductors 184 and 185 are formed on insulators 138, 150, and 152 (see Figures 13A to 13C). Conductors 184 and 185 are materials that can be used for conductors 122 and 132, respectively, and can be formed using methods that can be used to form conductors 122 and 132.

[0197] Next, an insulator 186 is formed on the conductor 184 and the insulator 185 (see Figures 14A to 14C). The insulator 186 is made of a material that can be used for the insulator 132 and can be formed using a method that can be used for forming the insulator 132.

[0198] Next, a conductor 187 and an insulator 188 are formed on the insulator 186 (see Figures 14A to 14C). The conductor 187 and the insulator 188 are materials that can be used for the conductor 122 and the insulator 132, respectively, and can be formed using methods that can be used for forming the conductor 122 and the insulator 132.

[0199] Next, an insulator 189 is formed on the conductor 187 and the insulator 188 (see Figures 14A to 14C). The insulator 189 is made of a material that can be used for the insulator 132 and can be formed using a method that can be used for forming the insulator 132.

[0200] Next, a mask is formed on the insulator 189, and the insulator 189, conductor 187, insulator 186, conductor 184, insulator 138, conductor 137, insulator 123, conductor 134, and conductor 136 are processed using lithography to form a first opening that exposes the conductor 119 (see Figures 15A to 15C).

[0201] In this case, if a dummy layer is used for one of the conductors 134 and 136, the dummy layer may be removed from the side surface exposed by the above processing, and a conductor may be formed in the area from which the dummy layer was removed. In this case, if a conductor is also formed inside the first opening, this conductor is removed.

[0202] Next, isotropic etching is performed on the conductor 136 to enlarge the diameter of the opening of the conductor 136 (see Figures 16A to 16C). As a result of this process, the diameter of the opening of the conductor 136 becomes larger than the diameters of the openings of the insulators 138, conductor 137, insulator 123, and conductor 134. Furthermore, it can be said that the conductor 136 has a recess relative to the side surface of the insulator 138, conductor 137, insulator 123, or conductor 134 located above or below it. For such processing, isotropic etching by dry etching using gas, radicals, plasma, etc., or isotropic etching by wet etching using a liquid can be used. The liquid used in wet etching is sometimes called an etchant. When performing isotropic etching using dry etching, a gas, radical, plasma, etc. containing at least one of chlorine, bromine, and fluorine can be used. It is preferable to perform isotropic etching without removing the mask used to form the first opening. The first opening obtained by the above process corresponds to the opening 141 shown in Figure 3.

[0203] Next, an insulating film 124A is formed on the insulator 189 and inside the first opening (see Figures 17A to 17C). Although not shown, the insulating film 124A may have a multilayer structure. The insulating film 124A can be formed using CVD or ALD. In particular, the ALD method is preferred because it can form a film of uniform thickness even in grooves and openings with large aspect ratios. In particular, the PEALD method is preferred because it can be used to form films at lower temperatures by utilizing plasma. Alternatively, the insulating film 124A may be formed by combining the ALD method and the CVD method. If the insulating film 124A has a multilayer structure, each insulating film may be formed using the same deposition apparatus or using different deposition apparatuses.

[0204] The insulating film 124A formed by the above method has good coverage, and can be formed even on recesses in the conductor 136. That is, the insulating film 124A can be formed so as to be in contact not only with the sides of the insulator 123, conductor 134, and conductor 136, but also with a portion of the upper surface and a portion of the lower surface of the insulator 123.

[0205] Next, the insulating film 124A formed at the bottom of the first opening is removed to obtain an insulator 124B. Anisotropic etching is preferably used to remove the insulating film 124A. At this time, the insulating film 124A on the insulator 189 is also removed, so the insulator 124B is provided only on the side wall of the first opening (see Figures 18A to 18C). By removing the insulating film 124A at the bottom of the first opening, the conductor 119 is exposed again.

[0206] Next, in the XY plane shown in Figures 18A to 18C, the conductor 184 and the insulator 124B overlapping with the conductor 187 are removed. To remove the insulator 124B, first, a material 180 (also called a sacrificial layer) that can be easily removed in a later process is formed inside the first opening, and then removed by etching or the like to a desired depth inside the first opening (see Figures 19A to 19C). Next, the material 180 is used as a mask to remove the insulator 124B exposed by the etching, and insulator 124 is obtained (see Figures 20A to 20C). After the removal of the insulator 124B, the material 180 is removed.

[0207] Next, a semiconductor film 125A and a conductive film 128A are formed on the insulator 189 and inside the first opening (see Figures 21A to 21C). Preferably, the semiconductor film 125A is provided inside the first opening so as to be in contact with at least the conductor 119, the insulator 124, and the conductor 184.

[0208] The semiconductor film 125A can be formed using CVD or ALD. In particular, the ALD method is preferred because it allows for the formation of a film with uniform thickness even in grooves and openings with large aspect ratios. In particular, the PEALD method is preferred because it allows for film formation at lower temperatures by utilizing plasma. Alternatively, the semiconductor film 125A may be formed by combining the ALD method and the CVD method. The semiconductor film 125A is preferably an oxide semiconductor having a CAAC structure. When the semiconductor film 125A is an oxide semiconductor having a CAAC structure, the c-axis of the semiconductor film 125A is oriented in the direction normal to the surface to be formed within the first opening. At this time, the c-axis of the semiconductor film 125A located on the sides of the insulator 138, conductor 137, insulator 123, conductor 134, and conductor 136 via the insulator 124 is oriented toward the axis 178 shown in Figures 21B and 21C from the surface to be formed. The axis 178 can be called the central axis of the first opening. As a result, the c-axis of the semiconductor 125 located above is oriented toward axis 178 from the surface to be formed.

[0209] Here, when forming a metal oxide as the semiconductor film 125A using the ALD method, it is preferable to form an In-Ga-Zn oxide using an indium-containing precursor, a gallium-containing precursor, and a zinc-containing precursor.

[0210] Indium-containing precursors include triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, and indium(III) chloride. Gallium-containing precursors include trimethylgallium, triethylgallium, tris(dimethylamide)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride. Zinc-containing precursors include dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionic acid)zinc, and zinc chloride.

[0211] The conductive film 128A only needs to be formed to fill the recesses of the conductor 136 via at least the insulator 124 and the semiconductor film 125A, and does not necessarily need to fill the entire interior of the first opening. The conductive film 128A can be formed using CVD or ALD. In particular, the ALD method is preferred because it can form a film of uniform thickness even in grooves and openings with large aspect ratios. In particular, the PEALD method is preferable because it can be used to form films at lower temperatures by utilizing plasma. Alternatively, the conductive film 128A may be formed by combining the ALD method and the CVD method.

[0212] Next, the conductive film 128A is processed to form the conductor 128 (see Figures 22A to 22C). Isotropic etching or anisotropic etching can be used to process the conductive film 128A. In forming the conductive film 128A, as shown in Figures 21A to 21C, if the conductive film 128A fills the recesses and the first opening is not completely filled, it is preferable to use isotropic etching for processing the conductive film 128A. On the other hand, if the conductive film 128A is formed to fill the recesses and the first opening, it is preferable to use anisotropic etching. Through the above processing, the conductor 128 can be formed inside the recesses.

[0213] Next, material 181 is formed inside the first opening (see Figures 22A to 22C). Material 181 is used as a sacrificial layer to protect the semiconductor film 125A in the processing of the semiconductor film 125A, conductor 119, insulator 118, etc. It is preferable that material 181 be formed from an insulating material, but this embodiment is not limited to this. Material 181 may also be a conductive material. Material 181 is a material that can be used for the insulating film 124A and can be formed using a method that can be used for forming the insulating film 124A.

[0214] Next, it is preferable to use the conductor 128 as a mask to increase the resistance of a portion of the semiconductor film 125A and form a high-resistance region (Type I region). As a method for forming the high-resistance region, the semiconductor film 125A can be irradiated with microwaves to remove hydrogen contained in the semiconductor film 125A. Furthermore, it is preferable to perform the microwave irradiation in an oxygen-containing atmosphere so that oxygen is supplied to the semiconductor film 125A. In this embodiment, a portion of the semiconductor film 125A is irradiated with microwaves in an atmosphere containing oxygen and argon to increase the resistance of a first region of the semiconductor film 125A that is not covered by the conductor 128.

[0215] Heat treatment may be performed at this point. The heat treatment is preferably carried out in a nitrogen-containing atmosphere at a temperature of 200°C to 500°C, preferably 300°C to 400°C. The atmosphere for the heat treatment is not limited to the above, but may be an atmosphere containing at least one of nitrogen, oxygen, and argon. Furthermore, the heat treatment may be carried out in a reduced pressure atmosphere or in an atmospheric pressure atmosphere.

[0216] By heat treatment, the second region of the semiconductor film 125A in contact with the conductor 128 becomes less resistive, and a low-resistance region (N-type region) can be formed. When heat treatment is performed with the semiconductor film 125A and the conductor 128 in contact, a metal compound layer containing the metal elements of the conductor 128 and the components of the semiconductor film 125A may be formed at the interface between the conductor 128 and the semiconductor film 125A. The formation of this metal compound layer is preferable because it reduces the resistance of the semiconductor film 125A in the region in contact with the conductor 128. In addition, the conductor 128 may absorb oxygen contained in the semiconductor film 125A. When heat treatment is performed with the semiconductor film 125A and the conductor 128 in contact, the resistance of the semiconductor film 125A becomes even lower. This heat treatment may be performed before microwave treatment. The second region, whose resistance has been reduced by heat treatment, is covered by the conductor 128, and therefore is not affected by microwaves, maintaining a low resistance value even after microwave treatment.

[0217] The carrier concentration in the first region after the above microwave treatment and heat treatment is 1 × 10⁻⁶ 18 / cm 3 Less than, preferably 1 × 10 17 / cm 3 More preferably, 1 × 10 16 / cm 3 The following is preferable. Also, the carrier concentration in the second region is 1 × 10⁻⁶. 18 / cm 3 Preferably, 1 × 10 19 / cm 3 More preferably, 1 × 10 20 / cm 3 It is preferable that the above conditions are met.

[0218] Furthermore, the process of performing the high-resistance treatment on the semiconductor film 125A is not limited to after the formation of material 181. The high-resistance treatment may be performed before the formation of material 181. In addition, the high-resistance treatment may be performed before the formation of the insulating film 126A, which will be described later, or after the formation of the insulating film 126A.

[0219] Next, the material 181, semiconductor film 125A, conductor 119, and insulator 118 formed at the bottom of the first opening are removed to obtain semiconductor 125B. Anisotropic etching is preferably used to remove the semiconductor film 125A, material 181, conductor 119, and insulator 118. At this time, the semiconductor film 125A and material 181 on the insulator 189 are also removed, so semiconductor 125B is provided only on the side wall of the first opening (see Figures 23A to 23C). By removing the semiconductor film 125A, material 181, conductor 119, and insulator 118 from the bottom of the first opening, the conductor 122 is exposed.

[0220] Next, in the XY plane shown in Figures 24A to 24C, the material 181 and semiconductor 125B that overlap with the conductor 187 are removed. To remove semiconductor 125B, first, a material 182 (also called a sacrificial layer) that can be easily removed in a later process is formed inside the first opening and removed by etching or the like to a desired depth inside the first opening (see Figures 24A to 24C). Next, using material 182 as a mask, the material 181 and semiconductor 125B exposed by the etching are removed to obtain semiconductor 125 (see Figures 24A to 24C). After removing semiconductor 125B, material 182 and material 181 are removed.

[0221] Next, an insulating film 126A is formed on the insulator 189 and inside the first opening (see Figures 25A to 25C). Although not shown, the insulating film 126A may have a multilayer structure. The insulating film 126A can be formed using CVD or ALD. In particular, the ALD method is preferred because it can form a film of uniform thickness even in grooves and openings with large aspect ratios. In particular, the PEALD method is preferred because it can be used to form films at lower temperatures by utilizing plasma. Alternatively, the insulating film 126A may be formed by combining the ALD method and the CVD method. If the insulating film 126A has a multilayer structure, each insulating film may be formed using the same deposition apparatus or using different deposition apparatuses.

[0222] Next, the insulating film 126A formed at the bottom of the first opening is removed to obtain an insulator 126B. It is preferable to use anisotropic etching to remove the insulating film 126A. At this time, the insulating film 126A on the insulator 189 is also removed, so the insulator 126B is provided only on the side wall of the first opening (see Figures 26A to 26C). By removing the insulating film 126A at the bottom of the first opening, the conductor 122 is exposed again.

[0223] Next, in the XY plane shown in Figures 27A to 27C, the insulator 126B that overlaps with the conductor 187 is removed. To remove the insulator 126B, first, a material 183 (also called a sacrificial layer) that can be easily removed in a later process is formed inside the first opening, and then removed by etching or the like to a desired depth inside the first opening (see Figures 27A to 27C). Next, the material 183 is used as a mask to remove the insulator 126B exposed by the etching, and an insulator 126 is obtained (see Figures 27A to 27C). After the removal of the insulator 126B, the material 183 is removed.

[0224] Next, a semiconductor film 127A is formed inside the first opening so as to be in contact with the conductor 122 (see Figures 28A to 28C). The semiconductor film 127A can be formed using CVD or ALD. In particular, the ALD method is preferred because it can form a film of uniform thickness even in grooves and openings with large aspect ratios. In particular, the PEALD method is preferred because it can be used to form a film at a lower temperature by utilizing plasma. Alternatively, the semiconductor film 127A may be formed by combining the ALD method and the CVD method. In this case, it is preferable that the semiconductor film 127A is formed so as to be in contact with the conductor 187. Furthermore, it is preferable that the semiconductor film 127A is an oxide semiconductor having a CAAC structure. When the semiconductor film 127A is an oxide semiconductor having a CAAC structure, the c-axis of the semiconductor film 127A is oriented in the direction normal to the surface to be formed inside the first opening. At this time, the c-axis of the semiconductor film 127A located on the side of the first opening is oriented toward the axis 178 shown in Figures 28B and 28C from the surface to be formed. As a result, the c-axis of the semiconductor 127 located above is oriented toward the axis 178 from the surface to be formed.

[0225] Here, when forming a metal oxide as the semiconductor film 127A using the ALD method, it is preferable to form an In-Ga-Zn oxide using an indium-containing precursor, a gallium-containing precursor, and a zinc-containing precursor.

[0226] As precursors containing indium, triethylindium, indium tris(2,2,6,6-tetramethyl-3,5-heptanedionate), cyclopentadienylindium, indium(III) chloride, etc. can be used. Also, as precursors containing gallium, trimethylgallium, triethylgallium, tris(dimethylamide)gallium, gallium(III) acetylacetonate, gallium tris(2,2,6,6-tetramethyl-3,5-heptanedionate), dimethylchlorogallium, diethylchlorogallium, gallium(III) chloride, etc. can be used. Further, as precursors containing zinc, dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0227] Next, the semiconductor film 127A formed on the insulator 189 is removed. To remove the semiconductor film 127A, first, inside the first opening, a material 179 (also called a sacrificial layer) that can be easily removed in a later process is formed so as to fill the inside of the semiconductor film 127A. Next, using the material 179 as a mask, the semiconductor film 127A is removed to obtain the semiconductor 127 (see FIGS. 29A to 29C). For removing the semiconductor film 127A, etching, CMP method, etc. can be used. When removing the semiconductor film 127A by etching, dry etching or wet etching may be used. After removing the semiconductor film 127A, the material 179 is removed.

[0228] Next, an insulator 129 is formed on the insulator 189 and inside the semiconductor 127, and a conductor 130 is formed inside the insulator 129 (see FIGS. 30A to 30C). The insulator 129 and the conductor 130 can be formed using a CVD method or an ALD method. By using the CVD method or the ALD method, a film with a uniform thickness can be formed even for grooves and openings with a large aspect ratio, which is preferable. Alternatively, it may be formed by combining the ALD method and the CVD method. Also, different film formation methods and film formation apparatuses may be used for each film to be formed. For example, the insulator 129 can be made of a material that can be used for the insulating film 124A and can be formed by a method that can be used for forming the insulating film 124A. Also, the conductor 130 can be made of a material that can be used for the conductive film 128A and can be formed by a method that can be used for forming the conductive film 128A.

[0229] Here, a high-resistance treatment similar to that performed on the semiconductor film 125A may be performed on the semiconductor 127. When performing a high-resistance treatment on the semiconductor 127, it is preferable to perform the high-resistance treatment before forming the conductor 130 or before forming the insulator 129. Also, if the high-resistance treatment of the first region of the semiconductor 125 can be performed by performing a high-resistance treatment on the semiconductor film 127A, the high-resistance treatment in the previous step may be omitted.

[0230] Next, a heat treatment is performed. The heat treatment is preferably performed in an atmosphere containing nitrogen at 200°C or higher and 500°C or lower, preferably 300°C or higher and 400°C or lower. The atmosphere for performing the heat treatment is not limited to the above, and may be performed in an atmosphere containing at least one of nitrogen, oxygen, and argon. Also, the heat treatment may be performed in a reduced-pressure atmosphere or in an atmospheric-pressure atmosphere.

[0231] The conductor 130 can be obtained by forming a conductive film on the insulator 129 and inside the insulator 129, and removing the conductive film using a CMP method or the like until the surface of the insulator 129 is exposed (see FIGS. 30A to 30C). Note that the above-described heat treatment may be performed after forming the conductor 130.

[0232] Next, an insulator 156 is formed on the conductor 130 and the insulator 129 (see Figures 31A to 31C). The insulator 156 can be formed using methods such as CVD, ALD, or sputtering.

[0233] Next, insulators 156, 129, 189, 188, 186, 185, 138, 150, and 123 are processed using lithography to form second openings that expose conductors 134, 136, 130, and 137. The second openings are formed for each of the stepped conductors 134 and 136 (see Figures 31A to 31C). Although not shown, openings that expose conductors 184 and 187, and openings that expose conductors 119 and 122 may also be formed in the above process.

[0234] Next, conductors 161, 162, 163, and 164 are formed to be embedded in the second opening, electrically connected to conductor 134, conductor 162, conductor 136, conductor 130, and conductor 137 (see Figures 31A to 31C). Conductors 161, 162, 163, and 164 can be formed using CVD or ALD methods. In particular, the ALD method is preferred because it can form a film of uniform thickness even in grooves and openings with large aspect ratios. Alternatively, the above conductors may be formed by combining the ALD method and the CVD method. Furthermore, conductors 161, 162, 163, and 164 may have a laminated structure consisting of multiple layers. Conductors 161, 162, 163, and 164 can be formed by forming a conductive film on the insulator 156 and inside the second opening, and then removing the unnecessary conductive film using a CMP method or the like. Although not shown, conductors that are electrically connected to conductors 184, 187, 119, and 122 may also be formed in the above process.

[0235] Next, conductors 171, 172, 173, and 174 are formed, which are electrically connected to conductor 161, conductor 162, conductor 173, and conductor 164 (see Figures 31A to 31C). Conductors 171, 172, 173, and 174 can be formed by forming a conductive film on the insulator 156 and processing it using lithography. This processing can be done using dry etching or wet etching. Dry etching is suitable for microfabrication.

[0236] Conductors 171, 161, and 134 can function as conductor SG or conductor WWL. Conductors 172, 162, and 136 can function as conductor RWL. Conductors 173, 163, and 130 can function as conductor BG. Conductors 174, 164, and 137 can function as conductor SEL. Conductor 184 can function as conductor WBL. Conductor 187 can function as conductor RBL. Through the above process, it is possible to fabricate transistor STr1 having a semiconductor 125 that functions as a channel formation region and a conductor 134 that functions as a gate; transistor STr2 having a semiconductor 127 that functions as a channel formation region and a conductor 137 that functions as a gate; transistor STr3 having a semiconductor 125 that functions as a channel formation region and a conductor 137 that functions as a gate; transistor WTr having a semiconductor 125 that functions as a channel formation region and a conductor 134 that functions as a gate; and transistor RTr having a semiconductor 127 that functions as a channel formation region, a conductor 136 that functions as a gate, a conductor 130 that functions as a back gate, and a conductor 128 between semiconductor 127 and conductor 136. Furthermore, it is possible to fabricate a memory device having transistors STr1, STr2, STr3, WTr, and RTr.

[0237] <Example of a film deposition apparatus configuration> Here, as an example of a device capable of forming films using the ALD method, the configuration of the film deposition apparatus 4000 will be explained using Figures 32A and 32B. Figure 32A is a schematic diagram of the multi-chamber type film deposition apparatus 4000, and Figure 32B is a cross-sectional view of the ALD apparatus that can be used with the film deposition apparatus 4000.

[0238] The film deposition apparatus 4000 includes an input / output chamber 4002, an input / output chamber 4004, a transport chamber 4006, a film deposition chamber 4008, a film deposition chamber 4009, a film deposition chamber 4010, and a transport arm 4014. Here, the input / output chambers 4002, 4004, and film deposition chambers 4008 to 4010 are independently connected to the transport chamber 4006. This allows for continuous film deposition in film deposition chambers 4008 to 4010 without exposure to the atmosphere, preventing the incorporation of impurities into the film. Furthermore, contamination of the interface between the substrate and the film, and the interfaces between each film, is reduced, resulting in clean interfaces.

[0239] Furthermore, it is preferable to fill loading / unloading rooms 4002, 4004, transport room 4006, and film deposition rooms 4008 to 4010 with an inert gas (such as nitrogen gas) with a controlled dew point to prevent moisture from adhering to them, and it is desirable to maintain a reduced pressure.

[0240] In addition, an ALD apparatus can be used in the film formation chambers 4008 to 4010. Also, a configuration in which a film formation apparatus other than the ALD apparatus is used in any one of the film formation chambers 4008 to 4010 may be adopted. Examples of the film formation apparatus that can be used in the film formation chambers 4008 to 4010 include a sputtering apparatus, a plasma CVD (PECVD: Plasma Enhanced CVD) apparatus, a thermal CVD (TCVD: Thermal CVD) apparatus, a photo CVD apparatus, a metal CVD (MCVD: Metal CVD) apparatus, a metal organic CVD (MOCVD: Metal Organic CVD) apparatus, and the like. Further, a device having a function other than the film formation apparatus may be provided in any one or more of the film formation chambers 4008 to 4010. Examples of such a device include a heating device (typically, a vacuum heating device), a plasma generation device (typically, a microwave plasma generation device), and the like.

[0241] For example, when the film formation chamber 4008 is an ALD apparatus, the film formation chamber 4009 is a PECVD apparatus, and the film formation chamber 4010 is a metal CVD apparatus, a metal oxide can be formed in the film formation chamber 4008, an insulating film that functions as a gate insulating film can be formed in the film formation chamber 4009, and a conductive film that functions as a gate electrode can be formed in the film formation chamber 4010. At this time, the metal oxide, the insulating film thereon, and the conductive film thereon can be continuously formed without exposing them to the atmosphere.

[0242] Further, although the film formation apparatus 4000 is configured to include a loading / unloading chamber 4002, a loading / unloading chamber 4004, and film formation chambers 4008 to 4010, the present invention is not limited thereto. The film formation apparatus 4000 may be configured to have four or more film formation chambers. Also, the film formation apparatus 4000 may be a single wafer type or a batch type in which a plurality of substrates are film-formed collectively.

[0243] <ALD apparatus> Next, the configuration of the ALD apparatus that can be used in the film deposition apparatus 4000 will be explained using Figure 32B. The ALD apparatus has a film deposition chamber (chamber 4020), a raw material supply unit 4021 (raw material supply units 4021a and 4021b), a raw material supply unit 4031, a high-speed valve 4022 (high-speed valves 4022a and 4022b) which is an introduction amount controller, a raw material inlet 4023 (raw material inlet 4023a and 4023b), a raw material inlet 4033, a raw material outlet 4024, and an exhaust device 4025. The raw material inlets 4023a, 4023b, and 4033 installed in the chamber 4020 are connected to the raw material supply units 4021a, 4021b, and 4031, respectively, via supply pipes and valves, and the raw material outlet 4024 is connected to the exhaust device 4025 via an exhaust pipe, valve and pressure regulator.

[0244] Furthermore, as shown in Figure 32B, by connecting a plasma generator 4028 to the chamber 4020, film deposition can be performed using the plasma ALD method in addition to the thermal ALD method. The plasma generator 4028 is preferably an ICP-type plasma generator using a coil 4029 connected to a high-frequency power supply. The high-frequency power supply can output power with a frequency of 10 kHz to 100 MHz, preferably 1 MHz to 60 MHz, and more preferably 10 MHz to 60 MHz. For example, it can output power with frequencies of 13.56 MHz and 60 MHz. Since the plasma ALD method allows film deposition without reducing the deposition rate even at low temperatures, it is suitable for use with single-wafer film deposition equipment, which typically has low deposition efficiency.

[0245] A substrate holder 4026 is located inside the chamber, and a substrate 4030 is placed on the substrate holder 4026. The substrate holder 4026 may be provided with a mechanism for applying a constant potential or high frequency. Alternatively, the substrate holder 4026 may be floating or grounded. A heater 4027 is provided on the outer wall of the chamber, which can control the temperature of the inside of the chamber 4020, the substrate holder 4026, and the surface of the substrate 4030. Preferably, the heater 4027 can control the temperature of the substrate 4030 surface between 100°C and 500°C, more preferably between 200°C and 400°C, and preferably the temperature of the heater 4027 itself can be set to between 100°C and 500°C.

[0246] In the raw material supply units 4021a, 4021b, and 4031, raw material gas is formed from solid or liquid raw materials using a vaporizer, heating means, etc. Alternatively, the raw material supply units 4021a, 4021b, and 4031 may be configured to supply gaseous raw material gas.

[0247] Furthermore, Figure 32B shows an example in which two raw material supply units 4021 and one raw material supply unit 4031 are provided, but this embodiment is not limited to this. One or more raw material supply units 4021 may be provided. Also, two or more raw material supply units 4031 may be provided. In addition, the high-speed valves 4022a and 4022b can be precisely controlled by time and are configured to control the supply of raw material gas supplied from raw material supply unit 4021a and raw material gas supplied from raw material supply unit 4021b.

[0248] In the film-forming apparatus shown in FIG. 32B, the substrate 4030 is carried onto the substrate holder 4026. After the chamber 4020 is sealed, the substrate 4030 is heated by the heater 4027 to a desired temperature (for example, 100°C or higher and 500°C or lower, preferably 200°C or higher and 400°C or lower). Then, the supply of the source gas supplied from the source gas supply unit 4021a, the evacuation by the evacuation device 4025, the supply of the source gas supplied from the source gas supply unit 4031, and the evacuation by the evacuation device 4025 are repeated to form a thin film on the surface of the substrate. Further, in the formation of the thin film, the supply of the source gas supplied from the source gas supply unit 4021b and the evacuation by the evacuation device 4025 may be performed. The temperature of the heater 4027 may be appropriately determined according to the film type to be formed, the source gas, the desired film quality, the substrate, and the heat resistance of the film and elements provided thereon. For example, the film may be formed by setting the temperature of the heater 4027 to 200°C or higher and 300°C or lower, or by setting it to 300°C or higher and 500°C or lower.

[0249] By forming the film while heating the substrate 4030 using the heater 4027, the heat treatment of the substrate 4030 required in the subsequent process can be omitted. That is, by using the chamber 4020 provided with the heater 4027 or the film-forming apparatus 4000, the formation of the film on the substrate 4030 and the heat treatment of the substrate 4030 can be combined.

[0250] In the film deposition apparatus shown in Figure 32B, metal oxides can be formed by appropriately selecting the raw materials (such as volatile organometallic compounds) used in the raw material supply units 4021 and 4031. When forming In-Ga-Zn oxide containing indium, gallium, and zinc as the metal oxide, it is preferable to use a film deposition apparatus equipped with at least three raw material supply units 4021 and at least one raw material supply unit 4031. It is preferable that a precursor containing indium is supplied from the first raw material supply unit 4021, a precursor containing gallium is supplied from the second raw material supply unit 4021, and a precursor containing zinc is supplied from the third raw material supply unit 4021. When precursors containing gallium and zinc are used for the formation of the metal oxide, at least two raw material supply units 4021 are sufficient. The precursors described above can be used as the precursors containing indium, gallium, and zinc, respectively.

[0251] Furthermore, a reactant is supplied from the raw material supply unit 4031. As the reactant, an oxidizing agent containing at least one of ozone, oxygen, and water can be used.

[0252] Furthermore, by appropriately selecting the raw materials (such as volatile organometallic compounds) used in the raw material supply units 4021a, 4021b, and 4031, it is possible to form insulating layers composed of oxides (including composite oxides) containing one or more elements selected from hafnium, aluminum, tantalum, zirconium, etc. Specifically, insulating layers composed of hafnium oxide, insulating layers composed of aluminum oxide, insulating layers composed of hafnium silicate, or insulating layers composed of aluminum silicate can be formed. In addition, by appropriately selecting the raw materials (such as volatile organometallic compounds) used in the raw material supply units 4021a, 4021b, and 4031, it is also possible to form thin films such as metal layers such as tungsten layers and titanium layers, or nitride layers such as titanium nitride layers.

[0253] For example, when forming a hafnium oxide layer using an ALD apparatus, a first raw material gas is used, which is obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (such as hafnium alkoxide or hafnium amides like tetrakisdimethylamide hafnium (TDMAHf)), and a second raw material gas is used, consisting of ozone (O3) and oxygen (O2) as oxidizing agents. In this case, the first raw material gas supplied from raw material supply unit 4021a is TDMAHf, and the second raw material gas supplied from raw material supply unit 4031 is ozone and oxygen. The chemical formula for tetrakisdimethylamide hafnium is Hf[N(CH3)2]4. Other material liquids include tetrakis(ethylmethylamide)hafnium. Water can also be used as the second raw material gas.

[0254] When forming an aluminum oxide layer using an ALD apparatus, a first raw material gas is used, which is obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as TMA: trimethylaluminum), and a second raw material gas is used, which contains ozone (O3) and oxygen (O2) as oxidizing agents. In this case, the first raw material gas supplied from raw material supply unit 4021a is TMA, and the second raw material gas supplied from raw material supply unit 4031 is ozone and oxygen. The chemical formula for trimethylaluminum is Al(CH3)3. Other raw material liquids include tris(dimethylamide)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate). Water can also be used as the second raw material gas.

[0255] Figures 33A to 33C illustrate the different configurations of the ALD apparatus that can be used with the film deposition apparatus 4000. Note that detailed explanations of configurations and functions similar to those of the ALD apparatus shown in Figure 32B may be omitted.

[0256] Figure 33A is a schematic diagram showing one embodiment of a plasma ALD apparatus. The plasma ALD apparatus 4100 has a reaction chamber 4120 and a plasma generation chamber 4111 above the reaction chamber 4120. The reaction chamber 4120 can be called a chamber. Alternatively, the reaction chamber 4120 and the plasma generation chamber 4111 together can be called a chamber. The reaction chamber 4120 has a raw material inlet 4123 and a raw material outlet 4124, and the plasma generation chamber 4111 has a raw material inlet 4133. Furthermore, a plasma generator 4128 can apply high-frequency waves such as RF or microwaves to the gas introduced into the plasma generation chamber 4111 to generate plasma 4131 within the plasma generation chamber 4111. When generating plasma 4131 using microwaves, microwaves with a frequency of 2.45 GHz are typically used. Plasma generated using such microwaves is sometimes called ECR (Electron Cyclotron Resonance) plasma. Furthermore, the reaction chamber 4120 has a substrate holder 4126 on which the substrate 4130 is placed. The raw material gas introduced from the raw material inlet 4123 is decomposed by heat from a heater provided in the reaction chamber 4120 and deposited on the substrate 4130. The raw material gas introduced from the raw material inlet 4133 is converted into a plasma state by the plasma generator 4128. The raw material gas in the plasma state recombines with electrons and other molecules before reaching the surface of the substrate 4130, becoming a radical state and reaching the substrate 4130. An ALD apparatus that performs film deposition using radicals in this way is sometimes called a radical-enhanced ALD apparatus. Furthermore, although the plasma ALD apparatus 4100 shows a configuration in which the plasma generator 4111 is provided on top of the reaction chamber 4120, this embodiment is not limited to this. The plasma generator 4111 may be provided adjacent to the side of the reaction chamber 4120.

[0257] Figure 33B is a schematic diagram showing one embodiment of a plasma ALD apparatus. The plasma ALD apparatus 4200 has a chamber 4220. The chamber 4220 has an electrode 4213, a raw material outlet 4224, and a substrate holder 4226, on which a substrate 4230 is placed. The electrode 4213 has a raw material inlet 4223 and a shower head 4214 that supplies the introduced raw material gas into the chamber 4220. A power supply 4215 capable of applying high frequency via a capacitor 4217 is connected to the electrode 4213. The substrate holder 4226 may be provided with a mechanism for applying a constant potential or high frequency. Alternatively, the substrate holder 4226 may be floating or grounded. The electrode 4213 and the substrate holder 4226 function as an upper electrode and a lower electrode for generating plasma 4231, respectively. The raw material gas introduced from the raw material inlet 4223 is decomposed by heat from a heater in the chamber 4220 and deposited on the substrate 4230. Alternatively, the raw material gas introduced from the raw material inlet 4223 becomes a plasma between the electrode 4213 and the substrate holder 4226. The raw material gas in the plasma state is incident on the substrate 4230 due to the potential difference (also called an ion sheath) that arises between the plasma 4231 and the substrate 4230.

[0258] Figure 33C is a schematic diagram showing one embodiment of a plasma ALD apparatus different from that of Figure 33B. The plasma ALD apparatus 4300 has a chamber 4320. The chamber 4320 has an electrode 4313, a raw material outlet 4324, and a substrate holder 4326, on which a substrate 4330 is placed. The electrode 4313 has a raw material inlet 4323 and a shower head 4314 that supplies the introduced raw material gas into the chamber 4320. A power supply 4315 that can apply high frequency via a capacitor 4317 is connected to the electrode 4313. The substrate holder 4326 may be provided with a mechanism for applying a constant potential or high frequency. Alternatively, the substrate holder 4326 may be floating or grounded. The electrode 4313 and the substrate holder 4326 function as an upper electrode and a lower electrode for generating plasma 4331, respectively. The plasma ALD apparatus 4300 differs from the plasma ALD apparatus 4200 in that it has a mesh 4319 between the electrode 4313 and the substrate holder 4326, to which a power supply 4321 capable of applying high frequency via a capacitor 4322 is connected. By providing the mesh 4319, the plasma 4231 can be separated from the substrate 4130. The raw material gas introduced from the raw material inlet 4323 is decomposed by heat from a heater provided in the chamber 4320 and deposited on the substrate 4330. Alternatively, the raw material gas introduced from the raw material inlet 4323 becomes a plasma between the electrode 4313 and the substrate holder 4326. The raw material gas in the plasma state has its charge removed by the mesh 4319 and reaches the substrate 4130 in an electrically neutral state such as radicals. Therefore, film deposition can be performed with suppressed ion incidence and plasma damage.

[0259] By forming semiconductor 125 or semiconductor 127 using the ALD method, it may be possible to form a metal oxide with a CAAC structure in which the c-axis is oriented approximately parallel to the normal direction of the film-deposited surface.

[0260] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0261] (Embodiment 2) In this embodiment, the circuit configuration and operation of the memory string 120, which is a storage device, will be described. Figure 34 shows an example of the circuit configuration of the memory string 120. Figure 35 shows an equivalent circuit diagram of the memory element MC.

[0262] Furthermore, in drawings and other diagrams, to make the potential of wiring, electrodes, or conductors easier to understand, a "H" indicating a high potential or a "L" indicating a low potential may be added adjacent to the wiring, electrodes, or conductors. In addition, a "H" or "L" enclosed in a box may be added to wiring, electrodes, or conductors where a potential change has occurred. Also, if a transistor is in the off state, an "×" symbol may be added superimposed on the transistor.

[0263] <Example of a memory string circuit configuration> Figure 34 shows an example circuit configuration of a memory string 120 having five memory elements MC. Each memory element MC has a transistor WTr and a transistor RTr. In Figure 34, the transistor WTr included in memory element MC[1] is shown as transistor WTr[1], and the transistor RTr included in memory element MC[1] is shown as transistor RTr[1]. Therefore, the memory string 120 shown in Figure 34 has transistors WTr[1] to WTr[5], and transistors RTr[1] to RTr[5]. The memory string 120 shown in Figure 34 also has transistors STr1, STr2, and STr3. The memory string 120 is a NAND type memory device.

[0264] In equivalent circuit diagrams and other diagrams, the designation "OS" may be added to the transistor's circuit symbol to indicate that it is an OS transistor. Similarly, the designation "Si" may be added to the transistor's circuit symbol to indicate that it is a Si transistor (a transistor that uses silicon in the semiconductor layer where the channel is formed). Figure 34 shows that transistors WTr and RTr are OS transistors.

[0265] A NAND-type storage device that includes OS memory is also called an "OS NAND type" or "OS NAND type storage device." Furthermore, an OS NAND type storage device having a configuration in which multiple OS memories are stacked in the Z direction is also called a "3D OS NAND type" or "3D OS NAND type storage device."

[0266] Transistor WTr is a normally-off type transistor, and transistor RTr is a normally-on type transistor. Furthermore, as described in the above embodiment, transistor RTr includes a conductor 128 between the gate and the semiconductor layer. The conductor 128 can function as a floating gate of transistor RTr. For example, the conductor 128 included in transistor RTr[1] is called conductor 128[1].

[0267] Furthermore, the node where the conductor 128 and either the source or drain of the transistor WTr are electrically connected is called node ND. For example, the node where the conductor 128[1] and either the source or drain of the transistor WTr[1] are electrically connected is called node ND[1].

[0268] One source or drain of transistor RTr[1] is electrically connected to conductor RSL, and the other is electrically connected to one source or drain of transistor RTr[2]. The gate of transistor RTr[1] is electrically connected to conductor RWL[1]. The back gate of transistor RTr[1] is electrically connected to conductor BG. One source or drain of transistor WTr[1] is electrically connected to conductor 128[1], and the other is electrically connected to conductor 128[2]. The gate of transistor WTr[1] is electrically connected to conductor WWL[1]. Also, one source or drain of transistor STr1 is electrically connected to conductor WSL, the other is electrically connected to conductor 128[1], and the gate is electrically connected to conductor SG.

[0269] Here, as shown in Figure 35, transistor RTr can be represented by replacing it with a capacitor Cs and transistor Tr. The gate of transistor Tr is electrically connected to the conductor RWL via the capacitor Cs.

[0270] Furthermore, one source or drain of transistor RTr[5] is electrically connected to the other source or drain of transistor RTr[4], and the other is electrically connected to one source or drain of transistor STr2. The gate of transistor RTr[5] is electrically connected to conductor RWL[5]. The back gate of transistor RTr[5] is electrically connected to conductor BG. One source or drain of transistor WTr[5] is electrically connected to conductor 128[5], and the other is electrically connected to one source or drain of transistor STr3. The gate of transistor WTr[5] is electrically connected to conductor WWL[5]. Furthermore, the other source or drain of transistor STr2 is electrically connected to conductor RBL, and its gate is electrically connected to conductor SEL. Furthermore, the other source or drain of transistor STr3 is electrically connected to conductor WBL, and its gate is electrically connected to conductor SEL.

[0271] If the memory string 120 has n memory elements MC (where n is an integer greater than or equal to 1), then in the i-th memory element MC[i] (where i is an integer between 2 and n-1), excluding the 1st and nth memory elements MC, one source or drain of transistor RTr[i] is electrically connected to the other source or drain of transistor RTr[i-1], and the other is electrically connected to one source or drain of transistor RTr[i+1]. The gate of transistor RTr[i] is electrically connected to conductor RWL[i]. The back gate of transistor RTr[i] is electrically connected to conductor BG. One source or drain of transistor WTr[i] is electrically connected to conductor 128[i], and the other is electrically connected to conductor 128[i+1]. The gate of transistor WTr[i] is electrically connected to conductor WWL[i]. The connection relationships between the first and nth memory elements MC and other elements and conductors can be found by referring to the connection relationships described in memory elements MC[1] and MC[5] above.

[0272] Transistors STr1, STr2, and STr3 may be, for example, OS transistors or Si transistors. At least one of transistors STr1, STr2, and STr3 may be an OS transistor, and the others may be Si transistors. When both transistors WTr and RTr are formed from OS transistors, it is preferable that transistors STr1, STr2, and STr3 are also formed from OS transistors. By standardizing the semiconductor materials used for transistors, the productivity of semiconductor devices can be increased.

[0273] Alternatively, an OS transistor may be used for transistor WTr and a Si transistor for transistor RTr. Figure 36 shows the equivalent circuit diagram of memory string 120 when an OS transistor is used as transistor WTr and a Si transistor is used as transistor RTr.

[0274] When transistor RTr is formed using a Si transistor, for example, polycrystalline silicon can be used for semiconductor 125. When transistor WTr is formed using an OS transistor, for example, CAAC-IGZO can be used for semiconductor 127. In this case, it is preferable to use OS transistors for transistors STr1 and STr3, and a Si transistor for transistor STr2.

[0275] As shown in Figure 37, depending on the purpose or application, a Si transistor may be used as transistor WTr and an OS transistor as transistor RTr. In this case, it is preferable to use Si transistors for transistors STr1 and STr3 and an OS transistor for transistor STr2. Also, as shown in Figure 38, depending on the purpose or application, Si transistors may be used for both transistor WTr and transistor RTr. When using Si transistors for both transistor WTr and transistor RTr, it is preferable to also use Si transistors for transistors STr1, STr2, and STr3.

[0276] <Example of memory string operation> Next, we will explain an example of the operation of the memory string 120 shown in Figure 34.

[0277] [Writing operation] This section describes an example of operation when writing a high potential or low potential to a memory element MC. Figure 39 is a timing chart illustrating the writing operation. Figures 40A to 41B are circuit diagrams illustrating the writing operation.

[0278] Initially, it is assumed that memory elements MC[1] to MC[5] have an L potential written to them. Furthermore, it is assumed that conductors WWL[1] to WWL[5], RWL[1] to RWL[5], SEL, BG, WBL, RBL, SG, WSL, and RSL are supplied with an L potential. Note that conductor BG can control the threshold voltage of transistor RTr. The potential supplied to conductor BG may be adjusted as appropriate so that transistor RTr becomes a desired normally-on type transistor. Note that conductor SEL is described as a common conductor serving as the gate for transistors STr2 and STr3, but it may be a different conductor.

[0279] [Period T1] During period T1, while conductor WWL[3] remains at L potential, conductors WWL[1], WWL[2], WWL[4], WWL[5], conductor SG, and conductor SEL are supplied with H potential (see Figure 40A). Additionally, conductors WSL and WBL are supplied with either H potential or L potential, respectively. As a result, the potential of conductor WSL is supplied to nodes ND[1] through ND[3], and the potential of conductor WBL is supplied to nodes ND[4] and ND[5].

[0280] [Period T2] During period T2, an L potential is supplied to conductors WWL[2] and WWL[4] (see Figure 40B). As a result, transistors WTr[2] and WTr[4] are turned off, and the charge written to nodes ND[3] and ND[4] is retained.

[0281] [Period T3] During period T3, the potential of conductor WSL is supplied to nodes ND[1] and ND[2], and the potential of conductor WBL is supplied to node ND[5]. (See Figure 40B.)

[0282] [Period T4] During period T4, an L potential is supplied to conductors WWL[1] and WWL[5] (see Figure 41A). As a result, transistors WTr[1] and WTr[5] are turned off, and the charges written to nodes ND[2] and ND[5] are retained.

[0283] [Period T5] During period T5, the potential of the conductor WSL is supplied to node ND[1]. (See Figure 41A.)

[0284] [Period T6] During period T6, an L potential is supplied to the conductor SG (see Figure 41B). This turns off transistor STr1, and the charge written to node ND[1] is retained. At this time, an L potential may also be supplied to the conductor SEL.

[0285] In this way, information can be written to the memory element MC.

[0286] The memory string 120 allows information to be written from both the conductive WSL and the conductive WBL. That is, it can write to memory elements MC[3] and MC[4] simultaneously. Furthermore, after writing to memory elements MC[3] and MC[4], it can write to memory elements MC[2] and MC[5] simultaneously. In this way, since it is possible to write to multiple memory elements MC within one memory string 120 simultaneously, the information writing speed can be increased. In addition, the supply of charge corresponding to the information to be written can be made more reliable.

[0287] Furthermore, when writing information to the i-th memory element MC, if i is close to n, the information can be written from the conductor WBL side, thereby omitting the information writing operation for the 1st to i-1th memory elements MC. Also, if i is close to 1, the information can be written from the conductor WSL side, thereby omitting the information writing operation for the i+1th to nth memory elements MC. In the memory string 120, the time required for writing operations and power consumption can be reduced.

[0288] In this embodiment, an example is shown in which, during the writing operation, an L potential is constantly supplied to the conductor WWL[3], and writing to memory elements MC[1] to MC[3] is performed from the conductor WSL side, while writing to memory elements MC[4] and MC[5] is performed from the conductor WBL side. However, the present invention is not limited to this. Alternatively, writing to memory elements MC[1] to MC[i] may be performed from the conductor WSL side, and writing to memory elements MC[i+1] to MC[n] may be performed from the conductor WBL side, with an arbitrary conductor WWL[i] as the boundary. Furthermore, writing to memory elements MC[1] to MC[n] may be performed from the conductor WSL side, or writing to memory elements MC[1] to MC[n] may be performed from the conductor WBL side.

[0289] [Read operation] An example of the read operation of the memory string 120 with the above circuit configuration will be described. As an initial state, it is assumed that an L potential is supplied to conductors WWL[1] to WWL[5], RWL[1] to RWL[5], SG, SEL, BG, WSL, RSL, WBL, and RBL. Figure 42 is a timing chart illustrating the read operation. Figures 43A to 45 are circuit diagrams illustrating the read operation.

[0290] In this embodiment, the operation of sequentially reading memory elements MC[1] to MC[5] will be described.

[0291] [Period T7] During period T7, a high potential is supplied to conductors RWL[2] through RWL[5], conductor SEL, and conductor RSL (see Figure 43A). As a result, transistors RTr[2] through RTr[5] turn on. Transistor STr2 also turns on, and semiconductor 127 of transistor RTr conducts through conductor RBL.

[0292] In this case, if a high potential is held at node ND[1] of memory element MC[1], transistor RTr[1] will be ON even if the potential supplied to conductor RWL[1] is a low potential. Therefore, conductor RSL and conductor RBL will be conductive via transistors RTr[1] to RTr[5], and the high potential supplied to conductor RSL can be detected on the conductor RBL side. In other words, it is possible to detect that the potential held at node ND[1] of memory element MC[1] is a high potential. It is preferable that conductor RBL be functionally connected to an RBL driver 2004 equipped with a sense amplifier or the like (see Figures 1A and 1B).

[0293] On the other hand, when an L potential is maintained at node ND[1] of memory element MC[1], the potential supplied to conductor RWL[1] is an L potential, and therefore transistor RTr[1] is in the off state. Consequently, conductor RSL and conductor RBL do not conduct, and the H potential supplied to conductor RSL cannot be detected on the conductor RBL side. Therefore, it can be detected on the conductor RBL side that an L potential is maintained at node ND[1] of memory element MC[1].

[0294] [Period T8] Next, during period T8, a high potential is supplied to conductor RWL[1] and a low potential is supplied to conductor RWL[2] (see Figure 43B). At this time, if a high potential is held at node ND[2] of memory element MC[2], transistor RTr[2] will be ON even if the potential supplied to conductor RWL[2] is a low potential. Therefore, conductor RSL and conductor RBL become conductive via transistors RTr[1] to RTr[5], and the high potential supplied to conductor RSL can be detected on the conductor RBL side. In other words, it can be detected that the potential held at node ND[2] of memory element MC[2] is a high potential.

[0295] On the other hand, when an L potential is maintained at node ND[2] of memory element MC[2], the potential supplied to conductor RWL[2] is an L potential, and therefore transistor RTr[2] is in the off state. Consequently, conductor RSL and conductor RBL do not conduct, and the H potential supplied to conductor RSL cannot be detected on the conductor RBL side. Therefore, it can be detected on the conductor RBL side that an L potential is maintained at node ND[2] of memory element MC[2].

[0296] [Period T9] Next, during period T9, a high potential is supplied to conductor RWL[2] and a low potential is supplied to conductor RWL[3] (see Figure 44A). At this time, if a high potential is held at node ND[3] of memory element MC[3], transistor RTr[3] will be ON even if the potential supplied to conductor RWL[3] is a low potential. Therefore, conductor RSL and conductor RBL become conductive via transistors RTr[1] to RTr[5], and the high potential supplied to conductor RSL can be detected on the conductor RBL side. In other words, it can be detected that the potential held at node ND[3] of memory element MC[3] is a high potential.

[0297] On the other hand, when an L potential is maintained at node ND[3] of memory element MC[3], the potential supplied to conductor RWL[3] is an L potential, and therefore transistor RTr[3] is in the off state. Consequently, conductor RSL and conductor RBL do not conduct, and the H potential supplied to conductor RSL cannot be detected on the conductor RBL side. Therefore, it can be detected on the conductor RBL side that an L potential is maintained at node ND[3] of memory element MC[3].

[0298] [Period T10] Next, during period T10, a high potential is supplied to conductor RWL[3] and a low potential is supplied to conductor RWL[4] (see Figure 44B). At this time, if a high potential is held at node ND[4] of memory element MC[4], transistor RTr[4] will be ON even if the potential supplied to conductor RWL[4] is a low potential. Therefore, conductor RSL and conductor RBL become conductive via transistors RTr[1] to RTr[5], and the high potential supplied to conductor RSL can be detected on the conductor RBL side. In other words, it can be detected that the potential held at node ND[4] of memory element MC[4] is a high potential.

[0299] On the other hand, when an L potential is maintained at node ND[4] of memory element MC[4], the potential supplied to conductor RWL[4] is an L potential, and therefore transistor RTr[4] is in the off state. Consequently, conductor RSL and conductor RBL do not conduct, and the H potential supplied to conductor RSL cannot be detected on the conductor RBL side. Therefore, it can be detected on the conductor RBL side that an L potential is maintained at node ND[4] of memory element MC[4].

[0300] [Period T11] Next, during period T11, a high potential is supplied to conductor RWL[4] and a low potential is supplied to conductor RWL[5] (see Figure 45). At this time, if a high potential is held at node ND[5] of memory element MC[5], transistor RTr[5] will be ON even if the potential supplied to conductor RWL[5] is a low potential. Therefore, conductor RSL and conductor RBL become conductive via transistors RTr[1] to RTr[5], and the high potential supplied to conductor RSL can be detected on the conductor RBL side. In other words, it can be detected that the potential held at node ND[5] of memory element MC[5] is a high potential.

[0301] On the other hand, when an L potential is maintained at node ND[5] of memory element MC[5], the potential supplied to conductor RWL[5] is an L potential, and therefore transistor RTr[5] is in the off state. Consequently, conductor RSL and conductor RBL do not conduct, and the H potential supplied to conductor RSL cannot be detected on the conductor RBL side. Therefore, it can be detected on the conductor RBL side that an L potential is maintained at node ND[5] of memory element MC[5].

[0302] In this way, by detecting the potentials held in nodes ND[1] to ND[5], the information in memory elements MC[1] to MC[5] can be read. In this embodiment, an example is shown in which information is read sequentially from memory element MC[1] to memory element MC[5], but this is not the only example. Information may also be read sequentially from memory element MC[5] to memory element MC[1].

[0303] Furthermore, it is not always necessary to read the information from memory elements MC[1] through MC[5]; the information from any memory element MC[i] can be read. In this case, an L potential is supplied to conductor RWL[i], and an H potential is supplied to the other conductor RWLs. By determining whether the potential of conductor RSL can be detected on the conductor RBL side, the potential held at node ND[i] of memory element MC[i] can be detected, and the information from memory element MC[i] can be read.

[0304] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0305] (Embodiment 3) In this embodiment, an example configuration of a semiconductor device 200 including a storage device 100 will be described.

[0306] Figure 46 shows a block diagram illustrating an example configuration of a semiconductor device 200 according to one aspect of the present invention. The semiconductor device 200 shown in Figure 46 includes a drive circuit 210 and a memory array 220. The memory array 220 has one or more storage devices 100. Figure 46 shows an example in which the memory array 220 has a plurality of storage devices 100 arranged in a matrix.

[0307] The drive circuit 210 includes a PSW 241 (power switch), a PSW 242, and a peripheral circuit 215. The peripheral circuit 215 includes a peripheral circuit 211, a control circuit 212, and a voltage generation circuit 228. The semiconductor device 200 includes various functional elements or circuits such as a memory array 220, PSWs 241 and 242, peripheral circuit 211, control circuit 212, and voltage generation circuit 228. Therefore, the semiconductor device 200 may be referred to as a system or subsystem.

[0308] In the semiconductor device 200, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0309] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data, and signal RDA is the read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may also be generated by the control circuit 212.

[0310] The control circuit 212 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 200. For example, the control circuit performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 200 (e.g., write operation, read operation). Alternatively, the control circuit 212 generates control signals for the peripheral circuit 211 so that this operating mode is executed.

[0311] The voltage generation circuit 228 has the function of generating a negative voltage. The WAKE signal has the function of controlling the input of the CLK signal to the voltage generation circuit 228. For example, when a high-level signal is given as the WAKE signal, the CLK signal is input to the voltage generation circuit 228, and the voltage generation circuit 228 generates a negative voltage.

[0312] The peripheral circuit 211 is a circuit for writing and reading data to and from the storage device 100. The peripheral circuit 211 includes a row decoder 221, a column decoder 222, a row driver 223, a column driver 224, an input circuit 225, an output circuit 226, and a sense amplifier 227.

[0313] The row decoder 221 and column decoder 222 have the function of decoding the signal ADDR. The row decoder 221 is a circuit for specifying the row to access, and the column decoder 222 is a circuit for specifying the column to access. The row driver 223 has the function of selecting the conductor WWL specified by the row decoder 221. The column driver 224 has the function of writing data to the storage device 100, reading data from the storage device 100, and holding the read data.

[0314] The input circuit 225 has the function of holding the signal WDA. The data held by the input circuit 225 is output to the column driver 224. The output data of the input circuit 225 is the data (Din) to be written to the storage device 100. The data (Dout) read by the column driver 224 from the storage device 100 is output to the output circuit 226. The output circuit 226 has the function of holding Dout. In addition, the output circuit 226 has the function of outputting Dout to the outside of the semiconductor device 200. The data output from the output circuit 226 is the signal RDA.

[0315] PSW241 provides V to peripheral circuit 215 DD It has the function of controlling the supply. PSW242 has the function of V to line driver 223. HM It has a function to control the supply of power. Here, the high power supply voltage of the semiconductor device 200 is V DD Therefore, the low power supply voltage is GND (ground potential). Also, V HM This is a high power supply voltage used to raise the word line to a high level, V DD It is higher than. The on / off state of PSW241 is controlled by signal PON1, and the on / off state of PSW242 is controlled by signal PON2. In Figure 46, in peripheral circuit 215, V DD The number of power domains supplied is set to 1, but it can be multiple. In this case, a power switch should be provided for each power domain.

[0316] The drive circuit 210 and the memory array 220 may be provided on the same plane. Alternatively, as shown in Figure 47A, the drive circuit 210 and the memory array 220 may be stacked on top of each other. Stacking the drive circuit 210 and the memory array 220 can shorten the signal propagation distance. Furthermore, as shown in Figure 47B, multiple layers of the memory array 220 may be stacked on top of the drive circuit 210.

[0317] Furthermore, as shown in Figure 47C, memory arrays 220 may be provided on the upper and lower layers of the drive circuit 210. Figure 47C shows an example in which one memory array 220 is provided on both the upper and lower layers of the drive circuit 210. By arranging multiple memory arrays 220 to sandwich the drive circuit 210, the signal propagation distance can be further shortened. Note that the number of memory arrays 220 stacked on the upper layer of the drive circuit 210 and the number of memory arrays 220 stacked on the lower layer of the drive circuit 210 may be one or more. It is preferable that the number of memory arrays 220 stacked on the upper layer of the drive circuit 210 is equal to the number of memory arrays 220 stacked on the lower layer of the drive circuit 210.

[0318] <Example of cross-sectional configuration of semiconductor device 200> Figure 48 shows an example of the cross-sectional configuration of the semiconductor device 200 shown in Figure 47A. Figure 48 shows a part of the semiconductor device 200 shown in Figure 47A.

[0319] Figure 48 shows transistors 301, 302, and 303 included in the drive circuit 210. Transistors 301 and 302 function as part of the sense amplifier 227. Transistor 303 functions as a column selection switch. Specifically, the conductor RBL included in the memory array 220 is electrically connected to one of the source and drain of transistor 301, the gate of transistor 301 is electrically connected to one of the source and drain of transistor 302, and the gate of transistor 302 is electrically connected to one of the source and drain of transistor 301. In addition, one of the source and drain of transistor 301 and the gate of transistor 302 are electrically connected to one of the source and drain of transistor 303, which functions as a column selection switch. This reduces the layout area of ​​the semiconductor device 200. Figure 48 shows an example in which five memory elements MC are provided per memory string. However, the number of memory elements MC provided in one memory string is not limited to this. For example, the number of memory elements MC provided in one memory string may be 32, 64, 128, or 200 or more.

[0320] The conductor RBL of the memory array 220 is electrically connected to the sense amplifier 227 and the transistor 303, which functions as a row selection switch, via a conductor 752 that is embedded in conductors 715, 714, 705, and insulators 726, 722, etc. Note that the circuits and transistors of the drive circuit 210 are just examples and are not limited to their circuit configuration or transistor structure. In addition to the above, appropriate circuits and transistors such as control circuits, row decoders, row drivers, source line drivers, and input / output circuits can be provided depending on the configuration of the semiconductor device 200 and its driving method.

[0321] Transistors 301, 302, and 303 are provided on a substrate 311 and each has a conductor 316, an insulator 315, a semiconductor region 313 consisting of a part of the substrate 311, and low-resistance regions 314a and 314b that function as source or drain regions. As shown in Figure 48, one low-resistance region may be shared by transistors 301 and 302 as the source or drain region of one of them and the source or drain region of the other.

[0322] Transistors 301, 302, and 303 have a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, the sides and top surface of the semiconductor region 313 are covered by a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. Such transistors 301, 302, and 303 are also called FIN type transistors because they utilize the convex portion of the semiconductor substrate. An insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. In addition, although the case of forming the convex portion by processing a part of the semiconductor substrate is shown here, a semiconductor film with a convex shape may be formed by processing an SOI substrate.

[0323] Transistors 301, 302, and 303 may each be either p-channel or n-channel. Furthermore, transistors 301 and 302 may have the same polarity or different polarities.

[0324] In the low-resistance regions 314a and 314b, which form the channel region of the semiconductor region 313, the region near the channel, the source region, or the drain region, it is preferable that a semiconductor such as a silicon-based semiconductor is included, and it is preferable that single-crystal silicon is included. Alternatively, it may be formed from a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing is also possible. Alternatively, transistors 301, 302, and 303 may be made into HEMTs (High Electron Mobility Transistors) by using GaAs and GaAlAs, etc.

[0325] The low-resistance regions 314a and 314b include, in addition to the semiconductor material applied to the semiconductor region 313, elements that impart n-type conductivity, such as arsenic and phosphorus, or elements that impart p-type conductivity, such as boron.

[0326] The insulator 315 functions as a gate insulating film for transistors 301, 302, and 303.

[0327] The conductor 316, which functions as the gate electrode, can be made of a conductive material such as silicon, a semiconductor material, a metallic material, an alloy material, or a metal oxide material, which contains an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0328] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride or tantalum nitride as the conductor. In addition, in order to achieve both conductivity and embedding properties, it is preferable to use metallic materials such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0329] Furthermore, it is preferable to provide an insulator 317 above the conductor 316 that functions as an etch stopper. It is also preferable to provide an insulator 318 on the side surface of the insulator 315 that functions as a spacer. By providing insulators 317 and 318, the areas where the low-resistance regions 314a and 314b and the conductor 328 are electrically connected can be self-aligned. Therefore, even if misalignment occurs when forming an opening to expose a part of the low-resistance regions 314a and 314b, an opening can be formed to expose the intended area. By forming the conductor 328 in the opening thus formed, good contact with reduced contact resistance can be obtained between the low-resistance regions 314a and 314b and the conductor 328. The contact between the low-resistance regions 314a and 314b and the conductor 328 formed in this way is sometimes called a self-aligned contact. Furthermore, a conductor 329 may be provided that is electrically connected to the conductor 316 so as to be embedded in the insulators 317 and 322.

[0330] Insulators 320, 322, 324, 326, and 327 are layered in order to cover transistors 301, 302, and 303.

[0331] For insulators 320, 322, 324, 326, and 327, for example, silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, aluminum nitride, etc. may be used.

[0332] The insulators 320 and 322 may function as planarizing films that flatten steps caused by transistors 301 or the like located below them. For example, the upper surfaces of one or both of the insulators 320 and 322 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve flatness.

[0333] Furthermore, it is preferable to use a film for the insulator 324 that has barrier properties to prevent hydrogen and impurities from diffusing from the substrate 311 or the transistor 301, etc., into the region where the memory array 220 is provided.

[0334] As an example of a film having hydrogen barrier properties, silicon nitride formed by the CVD method can be used. However, when hydrogen diffuses into a semiconductor element having an oxide semiconductor, such as a memory element MC, the properties of the semiconductor element may deteriorate. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the memory element MC and the transistor 301, etc. Specifically, a film that suppresses hydrogen diffusion is a film that has a low hydrogen desorption rate.

[0335] The amount of hydrogen desorption can be analyzed, for example, using a thermal desorption gas analysis (TDS) method. For example, in TDS analysis, the amount of hydrogen desorption from insulator 324, when the film surface temperature is in the range of 50°C to 500°C, is calculated as 10 × 10¹⁶ hydrogen atoms per unit area of ​​insulator 324. 15 atoms / cm 2 The following is preferably 5 × 10 15 atoms / cm 2 The following is acceptable.

[0336] Furthermore, it is preferable that insulators 326 and 327 have a lower relative permittivity than insulator 324. For example, the relative permittivity of insulators 326 and 327 is preferably less than 4, and more preferably less than 3. Also, for example, the relative permittivity of insulators 326 and 327 is preferably 0.7 times or less, and more preferably 0.6 times or less, than the relative permittivity of insulator 324. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced.

[0337] Furthermore, insulators 320, 322, 324, 326, and 327 have embedded conductors 328, 329, and 330, etc., which are electrically connected to the memory array 220. Conductors 328, 329, and 330 function as plugs or wiring. Conductors that function as plugs or wiring may be grouped together and assigned the same reference numeral. In this specification, the wiring and the plug that electrically connects to the wiring may be an integrated unit. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0338] The plugs and wiring (conductors 328, 329, and 330, etc.) can be made from conductive materials such as metals, alloys, metal nitrides, or metal oxides, either in a single layer or in a laminated configuration. It is preferable to use high-melting-point materials such as tungsten or molybdenum, which offer both heat resistance and conductivity, with tungsten being preferable. Alternatively, it is preferable to form them from low-resistance conductive materials such as aluminum or copper. Using low-resistance conductive materials can reduce wiring resistance.

[0339] A wiring layer may be provided on the insulator 327 and the conductor 330. For example, in Figure 48, insulators 350, 352, and 354 are stacked in order. Conductors 356 are formed on insulators 350, 352, and 354. Conductors 356 function as plugs or wiring. Conductors 356 can be provided using the same material as conductors 328, 329, and 330.

[0340] For example, it is preferable that the insulator 350, like the insulator 324, be an insulator that has barrier properties against hydrogen. It is also preferable that the conductor 356 includes a conductor that has barrier properties against hydrogen. In particular, a conductor that has barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 350. With this configuration, the transistor 301 and the memory element MC can be separated by the barrier layer, and the diffusion of hydrogen from the transistor 301 to the memory element MC can be suppressed.

[0341] For example, tantalum nitride may be used as the conductor that has barrier properties against hydrogen. Furthermore, by laminating tantalum nitride with highly conductive tungsten, it is possible to suppress the diffusion of hydrogen from transistors 301 and the like while maintaining conductivity as wiring. In this case, it is preferable that the tantalum nitride layer, which has barrier properties against hydrogen, is in contact with the insulator 350, which also has barrier properties against hydrogen.

[0342] A wiring layer may be provided on the insulator 354 and the conductor 356. For example, in Figure 48, insulators 360, 362, and 364 are stacked in order. Conductors 366 are formed on insulators 360, 362, and 364. Conductors 366 function as a plug or wiring. Conductors 366 can be provided using the same material as conductors 328, 329, and 330.

[0343] For example, it is preferable that the insulator 360, like the insulator 324, be an insulator having barrier properties against hydrogen. It is also preferable that the conductor 366 includes a conductor having barrier properties against hydrogen. In particular, a conductor having barrier properties against hydrogen is formed in the openings of the hydrogen barrier insulator 360. With this configuration, the transistor 301 and the memory element MC can be separated by the barrier layer, and the diffusion of hydrogen from the transistor 301 to the memory element MC can be suppressed.

[0344] An insulator 722 is provided on the insulator 364 and the conductor 366, and a memory array 220 is provided above the insulator 722. A barrier film made of the same material as the insulator 324 may be provided between the insulator 364 and the insulator 722.

[0345] Although the above example shows the storage device 100 having a memory string 120, this embodiment is not limited to this. As shown in Figure 49, the storage device 100 may have a memory string 120A as described in Figure 8.

[0346] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0347] (Embodiment 4) This embodiment describes an application example of an information processing device according to one aspect of the present invention.

[0348] Generally, a computer consists of components such as a processor, main memory, and storage on a motherboard, and each component is electrically connected, for example, by bus wiring. Therefore, the longer the bus wiring, the greater the parasitic resistance, and thus the higher the power consumption required to transmit signals.

[0349] Specifically, the computer would have a configuration like that shown in Figure 50A. The computer has a motherboard BD, on which are the processing unit (processor, CPU, etc.) 10, main memory (DRAM (Dynamic Random Access Memory), etc.) 30, storage (three-dimensional NAND type storage device, 3D OS NAND type storage device, etc.) 40, and interfaces 60. Although Figure 50 also shows SRAM (Static Random Access Memory) 20 which functions as main memory, it does not necessarily have to be placed on the motherboard BD.

[0350] Figure 50 illustrates a configuration in which the arithmetic processing unit 10 has registers 11.

[0351] In Figure 50A, the arithmetic processing unit 10 is electrically connected to the SRAM 20, the main memory 30, the storage 40, and the interface 60. The main memory 30 is also electrically connected to the SRAM 20 and the storage 40.

[0352] Note that each component of the computer in Figure 50A is electrically connected by bus wiring (BSH). In other words, as the number of computer components increases, or as the size of the motherboard (BD) increases, the length of the bus wiring (BSH) becomes longer, and therefore the power consumption required for transmission increases.

[0353] Incidentally, the computer in Figure 50A may be configured by integrating all of its components onto a single chip, forming a monolithic IC (Integrated Circuit). In this case, the information processing device described in the above embodiment can be used as the main memory 30 and storage 40. Figure 50B shows the computer in Figure 50A configured as a monolithic IC.

[0354] The monolithic IC in Figure 50B has a circuit layer LGC on a semiconductor substrate containing Si. A memory layer STR is located above the circuit layer LGC, and a circuit layer OSC is located above the memory layer STR.

[0355] The circuit layer LGC has multiple circuits, including Si transistors formed on a semiconductor substrate SBT having Si, for example. Parts of these multiple circuits can include, for example, the arithmetic processing unit 10 and SRAM 20 shown in Figure 50A. Furthermore, when the information processing unit is used as the main memory 30 and storage 40, a controller 1197 included in the information processing unit 50 can be part of these multiple circuits.

[0356] In particular, SRAM20 can achieve a higher operating frequency by using Si transistors, for example.

[0357] The memory layer STR functions as a memory unit having Si transistors and / or OS transistors. The memory layer STR can be, for example, a three-dimensional NAND type memory circuit, a 3D OS NAND type memory circuit, etc. Therefore, the memory layer STR includes the memory unit 1196 in the information processing device, the storage 40 in Figure 50A, etc.

[0358] Furthermore, by using a 3D OS NAND type memory circuit, the power consumption of the monolithic IC shown in Figure 50B can be reduced.

[0359] The circuit layer OSC has, for example, multiple circuits including OS transistors. Some of these multiple circuits may be different from the circuits included in the circuit layer LGC, such as the arithmetic processing unit 10 and SRAM 20.

[0360] In the monolithic IC shown in Figure 50B, there is no bus wiring (BSH) for routing on the motherboard, resulting in shorter wiring for electrically connecting each component. This allows for lower power consumption required for signal transmission.

[0361] Furthermore, the monolithic IC in Figure 50B includes an information processing unit 50. Therefore, the information processing unit 50 functions as both the storage 40 and the main memory 30 in Figure 50A. Consequently, in the monolithic IC of Figure 50B, the storage unit 1196 of the storage layer STR can have the function of the main memory 30.

[0362] By not including a bus wiring BSH and using a storage unit 1196 as a substitute for the main memory 30, the monolithic IC in Figure 50B can reduce the circuit area compared to the computer in Figure 50A.

[0363] Next, examples of the memory hierarchy of the computer in Figure 50A and the monolithic IC in Figure 50B are shown in Figures 51A and 51B, respectively.

[0364] Generally, in a memory hierarchy, higher-level memory devices require faster operating speeds, while lower-level memory devices require larger storage capacity and higher recording density. As an example, Figure 51A shows, from the top down, the registers included in the CPU (arithmetic processing unit 10), the SRAM, the DRAM included in the main memory 30, and the three-dimensional NAND-type memory circuit included in the storage 40.

[0365] The registers and SRAM included in the arithmetic processing unit 10 are frequently accessed by the arithmetic processing unit 10 because they are used for temporary storage of calculation results, etc. Therefore, a faster operating speed than the storage capacity is required. In addition, the registers also have the function of holding configuration information of the arithmetic processing unit.

[0366] The DRAM included in the main memory 30 has the function of holding programs and data read from the storage 40, for example. The recording density of the DRAM is approximately 0.1 to 0.3 Gbit / mm². 2 That is the case.

[0367] Storage 40 has the function of holding data that needs to be stored long-term, as well as various programs used by the processing unit. Therefore, storage 40 requires a larger storage capacity and higher recording density than operating speed. The recording density of the memory device used in storage 40 is approximately 0.6 to 6.0 Gbit / mm². 2 Therefore, storage 40 can be a three-dimensional NAND type memory circuit, a hard disk drive (HDD), or the like.

[0368] Incidentally, since the monolithic IC in Figure 50B has the roles of storage 40 and main memory 30 in Figure 50A, the storage hierarchy of the monolithic IC in Figure 50B is as shown in Figure 51B.

[0369] In other words, in the monolithic IC of Figure 50B, the memory cells included in the storage unit of the information processing device 50 can be treated not only as the cache memory of the storage unit, but also as the main memory 30 in the computer of Figure 50A. Therefore, in the monolithic IC of Figure 50B, there is no need to provide a main memory 30 such as DRAM, which reduces the circuit area of ​​the monolithic IC of Figure 50B and also reduces the power consumption required to operate the main memory 30 such as DRAM.

[0370] Note that the configuration of the monolithic IC shown in Figure 50B is just one example and is not limited to one aspect of the present invention. The configuration of the monolithic IC shown in Figure 50B may be changed depending on the circumstances. For example, in the monolithic IC of Figure 50B, if a high-speed memory of 1 GHz or more is required as SRAM, the SRAM may be integrated into the arithmetic processing unit.

[0371] This embodiment can be appropriately combined with other embodiments shown in this specification.

[0372] (Embodiment 5) In this embodiment, Figures 52A and 52B show an example of a chip 1200, a type of semiconductor device on which the memory device of the present invention is mounted. Multiple circuits (systems) are mounted on the chip 1200. This technology of integrating multiple circuits (systems) onto a single chip is sometimes called a System on Chip (SoC).

[0373] As shown in Figure 52A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0374] The chip 1200 is provided with bumps (not shown) and connects to the first surface of the printed circuit board (PCB) 1201, as shown in Figure 52B. In addition, multiple bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and connect to the motherboard 1203.

[0375] The motherboard 1203 may also be equipped with a sensor 1221, a power supply circuit 1222, and the like.

[0376] The CPU 1211 preferably has multiple CPU cores. Similarly, the GPU 1212 preferably has multiple GPU cores. The CPU 1211 and GPU 1212 may each have memory for temporarily storing data. Alternatively, a memory common to both the CPU 1211 and GPU 1212 may be provided on the chip 1200. The GPU 1212 is suitable for parallel computation of large amounts of data and can be used for image processing and multiply-accumulate operations. By providing image processing circuits and multiply-accumulate operation circuits on the GPU 1212, it becomes possible to perform image processing and multiply-accumulate operations with low power consumption.

[0377] Furthermore, because the CPU 1211 and GPU 1212 are located on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculations have been performed on the GPU 1212.

[0378] The analog arithmetic unit 1213 includes one or both an A / D (analog-to-digital) conversion circuit and a D / A (digital-to-analog) conversion circuit. Alternatively, the analog arithmetic unit 1213 may also be provided with the above-mentioned sum-of-accumulate circuit.

[0379] The memory controller 1214 has a circuit that functions as a controller and interface for a storage device according to one aspect of the present invention.

[0380] Interface 1215 has interface circuits for connecting to external devices such as display devices, speakers, microphones, cameras, and controllers. Controllers include mice, keyboards, and game controllers. Such interfaces can include USB (Universal Serial Bus) and HDMI (High-Definition Multimedia Interface).

[0381] The network circuit 1216 has a network circuit for connecting to a LAN (Local Area Network), etc. It may also have a circuit for network security.

[0382] The above-mentioned circuits (systems) can be formed on chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, there is no need to increase the number of manufacturing processes, and chip 1200 can be manufactured at a low cost.

[0383] A motherboard 1203, which is equipped with a PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a sensor 1221, and a power supply circuit 1222, can be called a GPU module 1204.

[0384] The GPU module 1204 has a chip 1200 that uses SoC technology, which allows for a smaller size. Furthermore, its excellent image processing capabilities make it suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable game consoles. Additionally, the multiply-accumulate circuit using the GPU 1212 enables the execution of techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), allowing the chip 1200 to be used as an AI chip, or the GPU module 1204 as an AI system module.

[0385] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0386] (Embodiment 6) This embodiment describes application examples of a semiconductor device using the storage device shown in the previous embodiment. The storage device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memory, and SSDs (solid-state drives). Figures 53A to 53E schematically show some configuration examples of removable storage devices. For example, the semiconductor device shown in the previous embodiment can be processed into a packaged memory chip and used in various storage devices and removable memory.

[0387] Figure 53A is a schematic diagram of a USB memory device. The USB memory device 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a circuit board 1104. The circuit board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the circuit board 1104. A storage device or semiconductor device as shown in the above embodiment can be incorporated into the memory chip 1105, etc.

[0388] Figure 53B is a schematic diagram of the external appearance of an SD card, and Figure 53C is a schematic diagram of the internal structure of an SD card. The SD card 1110 has a housing 1111, a connector 1112, and a circuit board 1113. The circuit board 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the circuit board 1113. By providing a memory chip 1114 on the back side of the circuit board 1113, the capacity of the SD card 1110 can be increased. Alternatively, a wireless chip with wireless communication functionality may be provided on the circuit board 1113. This allows for reading and writing data to the memory chip 1114 via wireless communication between the host device and the SD card 1110. The memory chip 1114 and other components can be incorporated into the storage device or semiconductor device shown in the above embodiment.

[0389] Figure 53D is a schematic diagram of the external appearance of the SSD, and Figure 53E is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a circuit board 1153. The circuit board 1153 is housed in the housing 1151. For example, memory chips 1154, 1155, and a controller chip 1156 are mounted on the circuit board 1153. Memory chip 1155 is the work memory for the controller chip 1156, and for example, a DOSRAM chip can be used. The capacity of the SSD 1150 can be increased by also providing memory chips 1154 on the back side of the circuit board 1153. The storage device or semiconductor device shown in the above embodiment can be incorporated into the memory chip 1154, etc.

[0390] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0391] (Embodiment 7) Figures 54A to 54G show specific examples of electronic devices equipped with a storage device or semiconductor device according to one aspect of the present invention.

[0392] <Electronic Equipment and Systems> A storage device or semiconductor device according to one aspect of the present invention can be mounted on various electronic devices. Examples of electronic devices include, for example, information terminals, computers, smartphones, e-book readers, television equipment, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, recording and playback devices, navigation systems, and sound playback devices. Here, "computer" includes not only tablet computers, notebook computers, and desktop computers, but also large computers such as server systems.

[0393] An electronic device according to one aspect of the present invention may have an antenna. By receiving a signal with the antenna, the display unit can display images, information, etc. Furthermore, if the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0394] An electronic device according to one aspect of the present invention may have sensors (including those with the function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0395] An electronic device according to one aspect of the present invention can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0396] [Information terminal] A memory device or semiconductor device according to one aspect of the present invention can be used to form a memory device for holding the program of a microcontroller. Therefore, according to one aspect of the present invention, the microcontroller chip can be made smaller.

[0397] Figure 54A illustrates a mobile phone (smartphone), a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102. A touch panel is provided on the display unit 5102 as an input interface, and buttons are provided on the housing 5101. By using a miniaturized microcontroller according to one aspect of the present invention, the limited space inside the mobile phone can be effectively utilized. Furthermore, a storage device according to one aspect of the present invention may be used for the storage of the mobile phone. This makes it possible to increase the storage capacity per unit area of ​​the storage device.

[0398] Figure 54B illustrates a notebook-type information terminal 5200. The notebook-type information terminal 5200 comprises a terminal body 5201, a display unit 5202, and a keyboard 5203. By using a miniaturized microcontroller according to one aspect of the present invention, the limited space inside the notebook-type information terminal can be effectively utilized. Furthermore, a storage device according to one aspect of the present invention may be used for the storage of the notebook-type information terminal. This makes it possible to increase the storage capacity per unit area of ​​the storage device.

[0399] In the above, smartphones and notebook computers were used as examples of electronic devices, illustrated in Figures 54A and 54B, respectively. However, other types of information terminals can also be used. Examples of other types of information terminals include PDAs (Personal Digital Assistants), desktop computers, and workstations.

[0400] [Game console] Figure 54C shows a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, operation keys 5306, etc. Housings 5302 and 5303 can be detached from housing 5301. By attaching the connection unit 5305 provided on housing 5301 to another housing (not shown), the video output from the display unit 5304 can be output to another video device (not shown). At this time, housings 5302 and 5303 can each function as operation units. This allows multiple players to play the game simultaneously. A memory device or semiconductor device according to one aspect of the present invention can be incorporated into chips or the like provided on the circuit boards of housings 5301, 5302, and 5303.

[0401] Figure 54D also shows a home console 5400, which is an example of a game console. A controller 5402 is connected to the home console 5400 either wirelessly or via a wired connection.

[0402] By using a miniaturized microcontroller according to one aspect of the present invention in game consoles such as the portable game console 5300 and the home game console 5400, the limited space inside the game console can be effectively utilized. Furthermore, a storage device or semiconductor device according to one aspect of the present invention may be used for the storage of the portable game console. This makes it possible to increase the storage capacity per unit area of ​​the storage device.

[0403] Figures 54C and 54D illustrate a portable game console and a home game console as examples of game consoles, but the game consoles to which the microcontroller according to one aspect of the present invention is applied are not limited to these. Examples of game consoles to which the microcontroller according to one aspect of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0404] [Large computer] A storage device or semiconductor device according to one aspect of the present invention can be applied to a large-scale computer.

[0405] Figure 54E shows the supercomputer 5500, an example of a large-scale computer. Figure 54F shows the rack-mount computer 5502, which is part of the supercomputer 5500.

[0406] The supercomputer 5500 comprises a rack 5501 and a plurality of rack-mount type computers 5502. The plurality of computers 5502 are housed in the rack 5501. Furthermore, each computer 5502 is provided with a plurality of circuit boards 5504, on which a microcontroller according to one aspect of the present invention can be mounted. By using a miniaturized microcontroller according to one aspect of the present invention, the limited space of the large computer can be effectively utilized. Additionally, a storage device or semiconductor device according to one aspect of the present invention may be used for the storage of the large computer. This increases the storage capacity per unit area of ​​the storage device.

[0407] Figures 54E and 54F illustrate a supercomputer as an example of a large computer, but the large computers to which the microcontroller according to one aspect of the present invention is applied are not limited to this. Examples of large computers to which the microcontroller according to one aspect of the present invention is applied include service-providing computers (servers) and large general-purpose computers (mainframes).

[0408] [electric appliances] Figure 54G shows an example of an electrical appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a casing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0409] A storage device or semiconductor device according to one aspect of the present invention can also be applied to an electric refrigerator 5800. For example, by applying a miniaturized microcontroller according to one aspect of the present invention to the electric refrigerator 5800, the limited space of the electric refrigerator can be effectively utilized.

[0410] While electric refrigerators and freezers were described as an example of electrical appliances, other examples of electrical appliances include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cooktops, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0411] The electronic devices described in this embodiment, their functions, and their effects can be appropriately combined with descriptions of other electronic devices.

[0412] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. [Explanation of symbols]

[0413] 100 Memory device, 110 Memory cell array, 117 Insulator, 118 Insulator, 119 Conductor, 120 Memory string, 121 Substrate, 122 Conductor, 123 Insulator, 124 Insulator, 125 Semiconductor, 126 Insulator, 127 Semiconductor, 128 Conductor, 129 Insulator, 130 Conductor, 132 Insulator, 134 Conductor, 136 Conductor, 137 Conductor, 138 Insulator, 141 Aperture, 150 Insulator, 152 Insulator, 156 Insulator, 161 Conductor, 162 Conductor, 163 Conductor, 1 64 Conductors, 171 Conductors, 172 Conductors, 173 Conductors, 174 Conductors, 179 Materials, 180 Materials, 181 Materials, 182 Materials, 183 Materials, 184 Conductors, 185 Insulators, 186 Insulators, 187 Conductors, 188 Insulators, 189 Insulators, 200 Semiconductor Devices, 2000 Drive Circuits, 2001 WSL Driver, 2002 WBL Driver, 2003 RSL Driver, 2004 RBL Driver, 2005 WWL Driver, 2006 RWL Driver, 2007 SEL Driver

Claims

1. First conductor and, The first insulator above the first conductor, The second conductor above the first insulator, The second insulator above the second conductor, The third conductor above the second insulator, The third insulator above the third conductor, The fourth conductor above the third insulator, The fourth insulator above the fourth conductor, The fifth conductor above the fourth insulator, The sixth conductor above the fifth conductor, The sixth insulator above the sixth conductor, The seventh conductor above the sixth insulator, The eighth conductor and, The seventh insulator and, The eighth insulator and, First semiconductor and, It has a second semiconductor, At least the fourth conductor and the fifth conductor each have an opening, In each of the openings, the seventh insulator, the first semiconductor, the eighth insulator, and the second semiconductor are provided in order from the inner side surface. In the region between the fourth conductor and the eighth insulator, the eighth conductor is provided between the first semiconductor and the eighth insulator. The first semiconductor is in contact with the upper surface of the second conductor and the side surface of the sixth conductor. The second semiconductor is in contact with the upper surface of the first conductor and the side surface of the seventh conductor. The third conductor has a region that overlaps with the fourth conductor and a region that does not overlap with the fourth conductor. The fourth conductor has a region that overlaps with the fifth conductor and a region that does not overlap with the fifth conductor. The fifth conductor has a region that overlaps with the sixth conductor and a region that does not overlap with the sixth conductor. The sixth conductor has a region that overlaps with the seventh conductor and a region that does not overlap with the seventh conductor. The fourth conductor functions as the gate electrode of the first transistor. The second semiconductor has a region in which the channel of the first transistor is formed, The fifth conductor functions as the gate electrode of the second transistor. The first semiconductor is a memory device having a region in which the channel of the second transistor is formed.

2. In claim 1, A memory device in which the seventh insulator, the first semiconductor, the eighth conductor, the eighth insulator, and the second semiconductor are each provided as concentric layers inside the opening of the fourth conductor.

3. In claim 1 or claim 2, A memory device in which the seventh insulator, the first semiconductor, the eighth insulator, and the second semiconductor are each provided as concentric layers inside the opening of the fifth conductor.

4. In any one of claims 1 to 3, A memory device in which the first semiconductor is a first oxide semiconductor.

5. In claim 4, The first oxide semiconductor is a memory device comprising indium, element M (where element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

6. In any one of claims 1 to 5, A memory device in which the second semiconductor is a second oxide semiconductor.

7. In claim 6, The memory device comprising the second oxide semiconductor indium, element M (where element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

8. In any one of claims 1 to 7, The opening is also provided in the second conductor and the sixth conductor. The eighth insulator is provided between the second conductor and the second semiconductor. A memory device in which the eighth insulator is provided between the sixth conductor and the second semiconductor.

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