Interfaces, electronic devices, communication systems

Abstract

To provide an interface, an electronic device, and a communication system that fully utilize the performance of an optical module.SOLUTION: An interface includes a general-purpose functional unit and one or more specialized functional units, the general-purpose functional unit includes one or more general-purpose functional modules and performs processing dependent on a media access control (MAC) rate, and the specialized functional unit includes one or more specific functional modules and performs processing independent of the MAC rate.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] This application is This is a divisional application of Japanese Patent Application No. 2024-081258, filed on March 17, 2024, and this application is a divisional application of Japanese Patent Application No. 2022-581367 filed on December 28, 2022, issue and claims priority from Chinese Patent Application No. 202010605324.3 filed on June 29, 2020, and Chinese Patent Application No. 202110049548.5 filed on January 14, 2021. All of the above-mentioned patent applications are incorporated herein by reference in their entirety. is 2 This application relates to an interface, an electronic device, and a communication system.

[0002]

Background Art

[0003] In the current evolution process of Ethernet interfaces, the speed of new interfaces needs to be compatible with previous electrical interfaces and previous optical interfaces having multiple speeds. However, in the solution of the logical layer of Ethernet interfaces, the utilization rate of the performance of the transmission medium is low.

Summary of the Invention

[0004] Embodiments of this application provide an interface, an electronic device, and a communication system. According to the technical solution in the embodiments of this application, the performance of the optical module can be fully utilized. According to a first aspect, the interface includes a functional part 1 and a functional part 2. The functional part 1 is configured to perform processing that depends on the Media Access Control (MAC) rate, and the functional part 2 is configured to perform processing independent of the MAC rate.

[0005] In some embodiments, the interface is an Ethernet interface.

[0006] In some embodiments, the functional part 1 includes a Media Independent Interface.

[0007] In some embodiments, functional unit 1 includes a MAC module, a reconciliation sublayer (RS) module, and coding and rate matching modules in a physical coding sublayer (PCS).

[0008] In some embodiments, the functional unit 2 includes one or more functional units, one or more of which include a first functional unit, the first functional unit including a transcoding module, a scrambling module, an alignment marker insertion module, a forward error correction (FEC) module, a physical media connection sublayer (PMA) module, and a physical media dependency (PMD) module.

[0009] In some embodiments, the functional unit 2 includes one PMA / PMD module and one or more functional units, one or more of which include a second functional unit, the second functional unit including a transcoding module, a scrambling module, an alignment marker insertion module, and a forward error correction (FEC) module, and the second functional unit is coupled to the PMA / PMD module.

[0010] In some embodiments, the functional unit 2 includes a linked first-level functional unit and a second-level functional unit. The first-level functional unit includes one or more first-level subunits, at least one of which includes a transcoding module, a scrambling module, an alignment marker insertion module, a forward error correction (FEC) module, and a PMA module. The second-level functional unit includes one or more second-level subunits, at least one of which includes a PCS / FEC / PMA module and a PMD module.

[0011] In some embodiments, the data output by the FECs of multiple functional units 2 is interleaved in the PMA layer.

[0012] In some embodiments, an FEC module included in at least one first-level subunit within a first-level functional unit is configured to perform Reed-Solomon (RS)(544,514) FEC coding and / or decoding, and an FEC module included in at least one second-level subunit within a second-level functional unit is configured to perform BCH FEC coding and / or decoding, Reed-Solomon forward error correction (RS FEC) coding and / or decoding, polar FEC coding and / or decoding, low-density parity-check forward error correction (LDPC FEC) coding and / or decoding, concatenated forward error correction (CFEC) coding and / or decoding, open forward error correction (OFEC) coding and / or decoding, or turbo product code (TPC FEC) coding and / or decoding. Optionally, an FEC module included in a first-level subunit is an external code FEC module.

[0013] In some embodiments, the interface includes an optical digital signal processor (oDSP).

[0014] In some embodiments, the FEC module is a concatenated FEC module, and the second-level functional unit further includes an inner-code encoding module configured to perform concatenated inner-code encoding on the data entering the second-level functional unit. Optionally, the second-level functional unit further includes a decoding module configured to perform concatenated FEC inner-code decoding on the data entering the second-level functional unit.

[0015] In some embodiments, functional unit 1 includes a MAC module, an RS module, an encoding and rate matching module in the physical coding sublayer (PCS), and a transcoding module.

[0016] In some embodiments, the functional unit 2 includes one or more functional units, one or more of which include a third functional unit, the third functional unit including a scrambling module, an alignment marker insertion module, a forward error correction (FEC) module, and a physical media connection sublayer (PMA) / physical media dependency (PMD) module.

[0017] In some embodiments, the functional unit 2 includes one or more functional units, one or more of which include a fourth functional unit, the fourth functional unit including a transcoding module, a scrambling module, an alignment marker insertion module, a forward error correction (FEC) module, a physical media connection sublayer (PMA) module, and a physical media dependency (PMD) module.

[0018] In some embodiments, functional unit 1 includes a MAC module, an RS module, an encoding and rate matching module in the physical coding sublayer (PCS), a transcoding module, and a scrambling module.

[0019] In some embodiments, the functional unit 2 includes one or more functional units, one or more of which include a fifth functional unit, the fifth functional unit including an alignment marker insertion module, a forward error correction (FEC) module, and a physical media connection sublayer (PMA) / physical media dependency (PMD) module.

[0020] In some embodiments, the interface is an Ethernet interface with a speed of 800 Gb / s or 1.6 Tb / s.

[0021] In some embodiments, the transcoding is a 64B / 66B to 256B / 257B transcoding compliant with IEEE802.3-2018.

[0022] In some embodiments, the number of functional units included in functional portion 2 is 1, 2, 3, 4, 5, 8, or 16.

[0023] In some embodiments, functional portion 2 is coupled to functional portion 1 via a data block allocation module.

[0024] According to another aspect, the electronic device includes an interface according to any one of the foregoing embodiments.

[0025] According to another aspect, the communication system includes a transmitting device and a receiving device. The transmitting device and / or the receiving device is an electronic device.

[0026] In some embodiments, the interface includes general-purpose functional units and one or more special-purpose functional units. The general-purpose functional units include one or more general-purpose functional modules. The special-purpose functional units include one or more specific functional modules.

[0027] In some embodiments, the interface is an Ethernet interface.

[0028] In some embodiments, the general-purpose functional units include functional modules that closely depend on the media access control (MAC) rate.

[0029] In some embodiments, the special-purpose functional units include functional portions that depend on speed. [[ID=​​​​In some embodiments, the general-purpose function unit includes a media access control (MAC) unit, an adjustment sublayer (RS) unit, and coding and rate matching modules in the PCS layer.

[0032] In some embodiments, the special function unit includes a transcoding unit, a scrambling unit, an alignment lock unit, a forward error correction (FEC) encoding / decoding unit, and a physical medium connection sublayer (PMA) / physical medium dependency (PMD) unit.

[0033] In some embodiments, the special function unit includes a plurality of function subunits and one PMA / PMD unit. Each function subunit includes a transcoding subunit, a scrambling subunit, an alignment lock processing subunit, and an FEC subunit. The plurality of function subunits are coupled to the PMA / PMD unit.

[0034] In some embodiments, the special function unit includes a first level and a second level. The first level includes one or more first level subunits, each first level subunit including a transcode subunit, a scramble subunit, an alignment lock subunit, an FEC subunit, and a PMA subunit. The second level includes one or more second level subunits, each second level subunit including a PCS / FEC / PMA subunit and a PMD subunit.

[0035] In some embodiments, the data output by the FECs of multiple special function units is interleaved in the PMA layer.

[0036] In some embodiments, the first level FEC is configured to perform RS(544,514)FEC coding, and the second level FEC is configured to perform BCH FEC, polar FEC, LDPC FEC, CFEC, OFEC, or TPC FEC coding.

[0037] In some embodiments, the interface includes an optical digital signal processor (oDSP).

[0038] In some embodiments, the FEC is a concatenated FEC, and the second level further includes an internal code decoding unit configured to perform concatenated code internal code decoding on the data entering the second level (decoding is primarily an error correction function, and overhead occurs by removing the internal code encoding after decoding is complete).

[0039] In some embodiments, the second level PCS / FEC / PMA is PCS / CFEC / OFEC / PMA.

[0040] In some embodiments, the general-purpose function unit includes coding and rate matching modules for the MAC, RS, and PCS layers, and a transcoding module.

[0041] In some embodiments, the special function unit includes scrambling, AM, FEC, and PMA / PMD.

[0042] In some embodiments, the special function unit includes a plurality of function subunits, each function subunit including a scramble subunit, an alignment lock subunit, an FEC subunit, a PMA subunit, and a PMD subunit.

[0043] In some embodiments, the general-purpose function unit includes a MAC unit, an RS unit, coding and rate matching modules in the PCS layer, a transcoding module, and a scrambling module.

[0044] In some embodiments, the special function unit includes an alignment lock unit, an FEC unit, and a PMA / PMD unit.

[0045] In some embodiments, the FEC subunit is an 800 Gb / s Ethernet interface.

[0046] An interface according to any one of claims 1 to 20, wherein the transcoding is 64B / 66B to 256B / 257B transcoding compliant with IEEE 802.3-2018.

[0047] In some embodiments, the number of special function units included in the interface is 1, 2, 4, 5, 8, or 16.

[0048] In some embodiments, a general-purpose function unit is coupled to a special function unit via a data block distribution module.

[0049] In another embodiment, the electronic device includes an interface according to one of the embodiments described above.

[0050] In another embodiment, the network system includes a transmitting device and a receiving device. The transmitting device and / or the receiving device are electronic devices.

[0051] In another embodiment, the computer-readable storage medium includes a computer-readable program or instruction. When the computer-readable program or instruction is executed, the device becomes capable of performing the interface function according to any one of the embodiments described above.

[0052] In another embodiment, the computer program product includes a computer-readable program or instruction. When the computer-readable program or instruction is executed, the device becomes capable of performing the functions of the interface according to any one of the embodiments described above.

[0053] In another embodiment, the transmission method includes a functional step of an interface according to any one of the embodiments described above. [Brief explanation of the drawing]

[0054] [Figure 1] This is a schematic diagram of the interface configuration and communication. [Figure 2A] This is a schematic diagram of other interface configurations and communications. [Figure 2B-1] This is a schematic diagram of other interface configurations and communications. [Figure 2B-2] This is a schematic diagram of other interface configurations and communications. [Figure 3] This is a schematic diagram of the interface architecture according to one embodiment. [Figure 4A] This is a schematic diagram of the interface architecture according to another embodiment. [Figure 4B] This is a schematic diagram of the interface architecture according to another embodiment. [Figure 4C] Figure 4A is a schematic diagram of the communication system including the interface. [Figure 4D] Figure 4B is a schematic diagram of the communication system including the interface. [Figure 4E] This is a schematic diagram of a communication system including a transmitter-side device having the interface shown in Figure 4A and a receiver-side device having the IEEE 802.3 standard interface. [Figure 4F] This is a schematic diagram of a communication system including a transmitter-side device having the interface shown in Figure 4B and a receiver-side device having the IEEE 802.3 standard interface. [Figure 4G] This is a schematic diagram of the interface architecture according to yet another embodiment. [Figure 5A] This is a schematic diagram of the interface architecture according to yet another embodiment. [Figure 5B] Figure 5A is a schematic diagram of the communication system including the interface. [Figure 6A] This is a schematic diagram of the interface architecture according to yet another embodiment. [Figure 6B] Figure 6A is a schematic diagram of the communication system including the interface. [Figure 6C]This is a schematic diagram of the interface architecture according to yet another embodiment. [Figure 6D] Figure 6C is a schematic diagram of the communication system including the interface. [Figure 7A] This is a schematic diagram of the interface architecture according to yet another embodiment. [Figure 7B] Figure 7A is a schematic diagram of the communication system including the interface. [Figure 7C] This is a schematic diagram of the interface architecture according to yet another embodiment. [Figure 8] This is a schematic diagram of the interface architecture according to Embodiment 1. [Figure 9] This is a schematic diagram of the interface architecture according to Embodiment 2. [Figure 10] This is a schematic diagram of the interface architecture according to Embodiment 3. [Figure 11] This is a schematic diagram of the interface architecture according to Embodiment 4. [Figure 12A] This is a schematic diagram of the interface architecture according to Embodiment 5. [Figure 12B] This is a schematic diagram of a communication system including a receiving device having an interface corresponding to the interface in Figure 4A and a transmitting device having an IEEE 802.3 standard interface. [Figure 12C] This is a schematic diagram of another communication system, including a receiving device having an interface corresponding to the interface in Figure 4B, and a transmitting device having an IEEE 802.3 standard interface. [Figure 12D] This is a schematic diagram of another communication system, including a receiving device having an interface corresponding to the interface in Figure 5A, and a transmitting device having an IEEE 802.3 standard interface. [Figure 12E] This is a schematic diagram of another communication system, including a receiving device having an interface corresponding to the interface in Figure 6A, and a transmitting device having an IEEE 802.3 standard interface. [Figure 12F] This is a schematic diagram of another communication system, including a receiving device having an interface corresponding to the interface in Figure 6C, and a transmitting device having an IEEE 802.3 standard interface. [Figure 12G] This is a schematic diagram of another communication system, including a receiving device having an interface corresponding to the interface in Figure 7A, and a transmitting device having an IEEE 802.3 standard interface. [Figure 13] This is a schematic diagram of the structure of the device according to one embodiment. [Figure 14] This is a schematic diagram of the structure of the device according to one embodiment. [Modes for carrying out the invention]

[0055] In an embodiment, "functional part 1" is also called a "general-purpose functional part" or "general-purpose functional unit," "functional part 2" is also called a "special functional part," and "functional unit 2" is also called a "special functional part." Multiple functional units in "functional part 2" are also called "special functional units." For example, "functional part 2" includes N functional units: a first functional unit, a second functional unit, ..., the nth functional unit, where the i-th functional unit is also called the i-th special functional unit, where i is a positive integer and n is a positive integer greater than 1, and 1 <= i <= n.

[0056] In this application, the media independent interface for 10 Mb / s operation and 100 Mb / s operation is referred to as MII, the media independent interface for 1000 Mb / s operation is referred to as GMII, and the media independent interface for 10 Gb / s operation is referred to as XGMII. In this application, xMII refers to RMII (reduced MII), serial MII (SMII), serial sync MII (SSMII), source synchronous SMII (S3MII), Gigabit MII (GMII), RGMII (Reduced GMII), serial GMII (SGMII), 10-bit interface (TBI), RTBI (Reduced TBI), 10 Gigabit MII (XGMII), 25 Gigabit MII, 40 Gigabit MII, 50 Gigabit MII, 100 Gb / s MII (CGMII), 200 Gb / s MII (200 GB / s MII) It can include multiple types of Ethernet interfaces, such as 200 Gb / s MII, 400 Gb / s MII (400 Gb / s MII, 400 Gb / s MII), 800 Gb / s MII, and 1.6 terabit MII.

[0057] The 200GbE / 400GbE speed standard implements a new generation of Ethernet speed standards based on single-lane electrical interface 50G four-level pulse amplitude modulation (PAM4) technology. Consideration of the next-generation 800GbE / 1.6TbE standard will increase the single-lane electrical interface speed to 100G PAM4 or 200G PAM-N (using N-level pulse amplitude modulation PAM-N, N=4, 6, or 8), so the next-generation speeds may support electrical interface speeds and may require compatibility with the 50Gb / s of the standard lane electrical interface generation. The evolutionary path of optical interfaces has many possibilities, each with a different speed per wavelength. For example, each wavelength can carry rates of 50Gb / s, 100Gb / s, 200Gb / s, 400Gb / s, or 800Gb / s.

[0058] In current solutions for the logical layers of Ethernet interfaces, the logical layers of interfaces with different rates have certain common characteristics and distinct differences. These differences make it difficult to share hardware resources between interfaces of different rates or to implement interworking by combining multiple low-speed Ethernet interfaces into a single high-speed interface module. For example, the logical layer architecture shown in Figure 1 is used for 200GbE / 400GbE interfaces. In Figure 1, the device interface includes a medium access control (MAC) layer, a reconciliation sublayer (RS), a physical coding sublayer (PCS), a forward error correction (FEC), a physical medium attachment sublayer (PMA), and a physical medium dependent (PMD) layer. Data from the transmitting device is processed, then sent from the PMD to the receiving device's PMD, processed by multiple submodules, and then reaches the MAC layer. The PCS is configured to perform functions such as 64B / 66B encoding and decoding, transcoding, scrambling, alignment marker (AM) insertion, and FEC encoding and decoding. The PMA sublayer is configured to perform functions such as clock recovery, carrier detection, and PAM4 modulation / demodulation. The PMD sublayer is configured to perform parallel-to-serial / serial-to-parallel conversion on the received data and modulate the digital signal for transmission.In the PCS layer's FEC sublayer, the introduction of new interleaving FECs (e.g., Reed-Solomon RS (544, 514)FECs) results in significant differences between the logic layer of the new interleaving FECs and the 100GbE solution, leading to a greater workload for redevelopment. As another example, the logic layer defined for 400G-ZR uses the architecture shown in Figures 2A, 2B-1, and 2B-2. In this logic layer architecture, optical modules supporting 400G-ZR (80km) cannot support 2*200GbE interfaces because the host-side interface is fixed to 400G AUI (Attachment unit interface, AUI).

[0059] Research has shown that the logical layer changes caused by cross-generation Ethernet speeds are primarily due to the functionality of the PCS. Above the PCS, the data output by the RS is very similar. Distinguishing similar parts from dissimilar parts and modularizing the dissimilar parts in a direction parallel to the direction of data flow enables advanced resource reuse, reduces development costs, and provides economic benefits. According to embodiments of the present invention, the current Ethernet architecture is divided into two parts, Functional Part 1 and Functional Part 2, based on functional parts that depend on a specific rate and functional parts that depend on a subrate corresponding to a specific PMD. See Figure 3. Functional Part 1 is a general-purpose functional part and includes functional modules that are closely dependent on the MAC rate, such as an RS module and modules required for rate matching. In some embodiments, Functional Part 1 further includes an xMII interface that is directly dependent on the rate. Functional Part 2 includes rate-independent functional parts. For example, Functional Part 2 includes one or more functional units: functional unit 1, functional unit 2, ..., and functional unit n. Functional part 2 may include PCS / PMA layer functions that perform data flow-based processing. The PMD may be media-dependent and used as part of functional part 2 based on a particular embodiment, or it may be protocol-independent and used as a functional component independent of functional parts 1 and 2.

[0060] Here, the reference criteria for selecting the boundary point between the two functional parts may include one or more of the following: (1) Save costs by making a downward selection as much as possible so that as many general-purpose functional parts exist after the cross-generation rate emerges. (2) Simplify the design of data distribution between the two functional parts as much as possible and use small units for data block distribution. (3) Ensure that the units of functional part 2 have as complete functionality as possible, including verification functions necessary to ensure reliability. (4) Achieve the optimal design by comprehensively considering the complexity of the specific embodiment and the control of chip resources. Regarding (4), in some scenarios, such as ultra-high-speed connection scenarios, it is not appropriate to use a conventional parallel media independent interface as the connection function interface.

[0061] As shown in Figure 4A, in one embodiment, the interface includes a functional unit 1, a functional unit 2, and a data block distribution module located between functional unit 1 and functional unit 2. Functional unit 1 includes a MAC module, an RS module, and an encode and rate matching module in the PCS layer. Functional unit 2 includes one or more functional units. Each of the one or more functional units includes multiple functional submodules, such as a transcode module, a scramble module, an alignment marker insertion (AM Insertion) module, an FEC module, and a PMA / PMD module.

[0062] For example, assume that each functional unit in functional section 2 can process MAC data flows at a corresponding speed of 200 Gbps. In the case of an 800 Gb / s Ethernet (officially known as 800 Gigabit Ethernet) MAC, functional section 2 may include four functional units, each capable of processing MAC data flows at a corresponding speed of 200 Gbps. The four functional units may be integrated or arranged separately. In the case of a MAC module with a speed of 1 Tbps, functional section 2 may include five functional units, each capable of processing MAC data flows at a corresponding speed of 200 Gbps. The five functional units may be integrated or arranged separately. In the case of a MAC module with a speed of 1.6 Tbps, functional section 2 may include eight functional units, each capable of processing MAC data flows at a corresponding speed of 200 Gbps. The eight functional units may be integrated or arranged separately.

[0063] In some embodiments, each functional unit of functional part 2 can process the corresponding MAC data flow at a different speed, for example, 5Gbps, 10Gbps, 20Gbps, 25Gbps, 100Gbps, 400Gbps, 800Gbps, 1Tbps, or 1.6Tbps.

[0064] In some other embodiments, functional unit 2 includes M functional units, of which N functional units are active and configured to transmit data from the current MAC module. The N functional units include first and second functional units, where the rate of the corresponding MAC data flow that the first functional unit can process is the same as or different from the rate of the corresponding MAC data flow that the second functional unit can process. For example, in the case of an 800 GbE / sec Ethernet MAC, functional unit 2 may include eight functional units a, b, c, d, e, f, g, and h. Functional units a, b, c, and d are activated, and each of functional units a, b, c, and d can process the corresponding MAC data flow at a speed of 200 Gbps. Alternatively, while functional units a, b, c, d, g, and h are inactive, functional units d, e, and f may be active, and functional units d, e, and f may process the corresponding MAC data flows at speeds of 200 Gbps, 200 Gbps, and 400 Gbps, respectively. M and N are positive integers, and M=>N=>1.

[0065] From top to bottom, the data obtained through encoding (such as 64B / 66B or 256B / 257B encoding) and rate matching is the first appropriate boundary point because the data distributed at the boundary point is in the form of data blocks. Unlike the xMII interface, which achieves synchronous transmission by using data and clock, the data block itself has a sync header. Also, the transmission rate of the data block obtained through rate matching is a fixed value, and the encoded data blocks can be distributed regularly. After performing round-robin distribution, it is possible to ensure that the processing speed of the functional units activated in functional part 2 is constant, so there is no need to perform rate matching operations in functional part 2. To perform rate matching on an Ethernet interface, it is necessary to identify the data flow format, find packet boundaries, and insert or remove idle code blocks into or from the MAC inter-frame gap (IFG, inter-frame gap, IPG, also called inter-packet gap) for rate adjustment. The rate matching function is moved to functional part 1. The part that depends on the MAC rate is distinguished from the part that depends only on the intermediate rate but is independent of the MAC rate.

[0066] In the interface shown in Figure 4A, the PMA / PMD does not identify a protocol or data format, so the PMA / PMD can exist across functional parts. The interface is shown in Figure 4B. For example, in functional parts 2 that are active and configured to process the data flow from the current MAC module, N functional units out of M functional units share one PMA / PMD module. In some embodiments, some of the N functional units may share a first PMA / PMD module, some may share a second PMA / PMD module, or some of the N functional units may share a first PMA / PMD module, while each of the other functional units uses a separate PMA / PMD module.

[0067] Figure 4G corresponds to one embodiment. The oDSP (Optical Digital Signal Processor) is integrated and encapsulated on the host chip. The data flow or data frame flow output by the oDSP is sent to a PMD, processed by the PMD, and then enters the laser, or the data flow or data frame flow output by the oDSP is modulated and used as a drive signal for the laser. Modulation can be completed by the oDSP or another modulator.

[0068] Optionally, functional part 2 may further include a new FEC encoding function (FEC encoding x) for encoding data processed by the oDSP. The FEC encoding is RS FEC encoding. Secondary FEC encoding is performed after processing by the oDSP. Secondary FEC encoding may be BCH FEC or RS FEC encoding. FEC encoding x may be configured in the oDSP or independently.

[0069] In some embodiments, functional parts 1 and 2 in Figure 4A, Figure 4B, or Figure 4G may be integrated into the same chip.

[0070] In some embodiments, the communication system includes a transmitting device and a receiving device. The transmitting device includes the interface shown in Figure 4G, and the interface included in the receiving device is an interface of any architecture. For example, in some embodiments, the communication system includes a transmitting device and a receiving device, the transmitting device includes the interface shown in Figure 7C, and the interface included in the receiving device is an interface of any architecture, such as the interfaces in Figures 4A, 4B, 4G, 5A, 6A, 7A, 7C, 8, 9, 10, 11, or 12A, or an IEEE 802.3 standard Ethernet interface.

[0071] For example, the interface of the transmitting device has the architecture shown in Figure 4B. See Figure 4D. The communication system includes a transmitting device and a receiving device.

[0072] Packets received by the transmitting device's interface enter into functional part 1 of the transmitting device's interface.

[0073] In this embodiment, the functional part 1 of the transmitting device's interface includes a MAC module, an RS module, and an encode and rate matching module. Packets are processed by the MAC module, RS module, and encode and rate matching module and then enter into a data block distribution module. Specifically, the data frame obtained by processing by the MAC module is converted by the RS module into data of the corresponding bit width (the width varies depending on the rate), and the data is sent to the encode and rate matching module via the media-independent interface MII for processing, and the encode and rate matching module processes the data sent from the MII to generate 64B / 66B blocks.

[0074] In one embodiment, the input data for the 100GbE PCS is parallel data in the 100G Ethernet Media Independent Interface (CGMII) format at the Coordination Sublayer (RS). The 400G Ethernet (abbreviated as 400GbE) interface converts the input data to the corresponding CDGMII format. The data format of the CDGMII interface is specifically described as follows: The bit width of the CDGMII interface is (64+8+2), and the CDGMII interface format consists of 64 data information bits, 8 control information index bits, and two clocks corresponding to transmission and reception. The 8 control information bits indicate whether the 64 bits, or 8 bytes, of data represent data or control information. The data from the CDGMII is transmitted to a 64B / 66B encoding module for encoding.

[0075] After receiving the data blocks processed by the encoding and rate matching modules, the data block distribution module in the transmitting device distributes the data blocks to N functional units in the functional section 2 of the transmitting device.

[0076] In this embodiment, each of the N functional units includes one or more PCS lanes. In some embodiments, each of the N functional units includes one or more PCS lanes.

[0077] In this embodiment, the data block distribution module distributes the 64B / 66B blocks generated by the coding and rate matching modules to N functional units. In some embodiments, the data block distribution module distributes the 64B / 66B blocks to the N functional units one by one in a round-robin mode. For example, the data block distribution module distributes the first 64B / 66B block it receives to the first functional unit of the N functional units, the second 64B / 66B block it receives to the second functional unit of the N functional units, ..., and distributes the Nth 64B / 66B block it receives to the Nth functional unit of the N functional units.

[0078] In this embodiment, each of the N functional units includes a transcode module, a scramble module, an AM module, an FEC coding module, and a PMA / PMD module. The transcode module, scramble module, AM module, and FEC coding module within each functional unit perform corresponding processing on the data blocks entering the functional unit. For example, the i-th functional unit of the N functional units sequentially performs transcoding, scrambling, AM insertion, and FEC coding on the data received from the data block distribution module, and sends the processed data to the receiving device via the PMA / PMD and media (e.g., backplane or optical fiber). For example, a block obtained by performing 64B / 66B coding on a data flow is transcoded. Specific formats of data transcoded by the transcode module include 256B / 257B, 512B / 513B, 256B / 258B, or 512B / 514B. Specific transcoding schemes are not limited herein.

[0079] Specifically, the scramble module scrambles the transcoded data flow. In some embodiments, whole or partial scrambling can be performed at a specific granularity. Self-synchronizing scrambling (also called multiplicative scrambling) may be performed on the entire integrated data flow, synchronous scrambling (also called appending scrambling) may be performed at the FEC granularity, or self-synchronizing or synchronous scrambling may be performed at the PCS lane granularity. In the case of synchronous scrambling, the initial values ​​of the scramble module and the descramble module may be set to ensure the performance of the entire system.

[0080] After the alignment marker insertion module inserts alignment markers (AM) into the scrambled data flow, the data flow enters the FEC coding module for FEC coding. In some embodiments, the FEC coding module can process the received data flow based on one or more coding schemes such as Reed-Solomon (RS) (544,514) FEC, Bose-Chaudhuri-Hocquenghem (BCH) FEC, polarity FEC, LDPC FEC, CFEC FEC, OFEC FEC, or TPC FEC. The data processed by the FEC coding module then passes through the PMA module and PMD module in sequence to reach the transmission medium. The PMA module and PMD module may be integrated into a single functional module or arranged separately. The PMA module performs serial-to-parallel conversion on the received data and sends the converted data to the PMD module. The PMD module then converts the received signal to the corresponding transmission medium.

[0081] As shown in Figure 4D, in one embodiment, the interface architecture of the receiving device corresponds to the interface structure shown in Figure 4A. In this case, N data flows processed by the functional part 2 of the transmitting device enter the functional part 2 of the interface of the receiving device via a medium, and the N functional units in the functional part 2 of the interface of the receiving device correspond one-to-one with the N functional units in the functional part 2 of the interface of the transmitting device. Each of the N functional units in the functional part 2 of the interface of the receiving device receives the data transmitted by the N functional units in the functional part 2. Each of the N functional units in the functional part 2 includes a reverse transcode module, a descramble module, an alignment marker removal (AM removal) module, an FEC decoding module, and an alignment lock module. For example, the i-th functional unit of the N functional units sequentially performs alignment locking of alignment markers, FEC decoding, alignment marker removal, descrambling, and reverse transcoding on the data received from the PMA / PMD module, and the N processed data flows enter the data block distribution module of the receiving device's interface. The data block distribution module of the receiving device's interface sends the N data flows to functional part 1 of the receiving device's interface. Functional part 1 of the receiving device's interface includes a MAC module, an RS module, and a decoding and rate matching module. The decoding and rate matching module of the receiving device's interface decodes the N data flows distributed by the data block distribution module, performs rate matching, and sends the data obtained by rate matching to the RS module. The data is processed by the RS module and reaches the MAC module of the receiving device's interface.Optionally, the receiving device's interface decoding and rate matching module performs rate matching on N data flows, and the data obtained through rate matching reaches the receiving device's interface RS module via xMII.

[0082] Please refer to Figure 4C. The communication system includes a transmitting device and a receiving device. The interface architecture of the transmitting device is shown in Figure 4A. The interface architecture of the receiving device corresponds to the interface architecture in Figure 4A. The process by which the transmitting device's interface processes data and then transmits the processed data to the receiving device's interface, and the process by which the receiving device's interface processes the received data, are the same as the processes between the transmitting device's interface and the receiving device's interface in the communication system shown in Figure 4D. Further details will not be explained here.

[0083] Refer to Figure 4E. The communication system includes a transmitting device and a receiving device. The transmitting device includes the interface shown in Figure 4A, and the receiving device's interface is an IEEE 802.3 standard Ethernet interface. The process by which the transmitting device's interface processes the data to be transmitted is similar to the operation of the transmitting device's interface in Figure 4C. Details will not be explained again here. After the transmitting device's interface has processed the data, the N data flows processed by the functional part 2 of the transmitting device enter the receiving device's interface via the medium. The receiving device's interface is an IEEE 802.3 Ethernet interface and includes a MAC module, RS module, decoding and rate matching module, data block distribution module, reverse transcoding module, descramble module, alignment marker removal module, FEC decoding module, and PMA / PMD module. After the receiving device's interface receives the data flow from the transmitting device via the medium, PMD / PMA processing, alignment locking of alignment markers, FEC decoding, alignment marker removal, descrambling, and reverse transcoding are performed sequentially on the data flow, and the processed data flow then reaches the data block distribution module. The data block distribution module processes the received data flow. Decoding and rate matching, and RS processing are performed sequentially on the data flow, and the processed data flow then reaches the MAC module. The MAC module processes the data flow to generate Ethernet frames.

[0084] Please refer to Figure 4F. The communication system includes a transmitting device and a receiving device. The transmitting device includes the interface shown in Figure 4B, and the receiving device's interface is an IEEE 802.3 standard Ethernet interface. The process by which the transmitting device's interface processes the data to be transmitted is the same as the operation of the transmitting device's interface in Figure 4D. Details will not be explained again here. The process by which the receiving device's interface processes the received data is the same as the processing process of the receiving device's interface in Figure 4E. Details will not be explained again here.

[0085] As shown in Figure 5A, in one embodiment, the Ethernet interface includes a functional unit 1, a functional unit 2, and a data block distribution module located between functional unit 1 and functional unit 2. Functional unit 1 includes a MAC module, a coordination module, and a coding and rate matching module. Functional unit 2 includes a plurality of functional units. For example, each functional unit includes a plurality of flows of PCS functions. The data block distribution module is located between functional unit 1 and functional unit 2. The data block distribution module accesses the plurality of functional units in functional unit 2. The plurality of functional units in functional unit 2 provide outputs via a PMA / PMD. In some embodiments, the plurality of functional units in functional unit 2 may be connected to a shared PMA / PMD.

[0086] Please refer to Figure 5B. The communication system includes a transmitting device and a receiving device. The transmitting device includes the interface shown in Figure 5A, and the receiving device includes an interface corresponding to the interface shown in Figure 5A. The processing method of each module in functional part 1 of the interface shown in Figure 5A is the same as the processing method of functional part 1 in Figure 4A. Details will not be explained again here. Functional part 2 of Figure 5A includes m flows of PCS functionality, where m is an integer greater than or equal to 1. Each flow of PCS functionality includes a transcoding module, a scrambling module, an alignment marker insertion module, and an FEC coding module. The processing methods of these modules are the same as the processing methods of the corresponding modules in Figure 4A. The data block distribution module distributes data blocks from the coding and rate matching modules to the m flows of PCS functionality. After the m flows of PCS functionality perform their corresponding processing, they send the data of the m flows of PCS functionality to one PMA module. The data processed by the PMA module is distributed to one or more PMD modules, processed by the PMD modules, and then sent to the transmission medium. In the solution shown in Figure 5A, functional unit 2 individually houses only the transcoding module, scrambling module, alignment marker insertion module, and FEC coding module, and the data output by the m flows of the PCS function is processed by a separate PMA module, thereby allowing for more flexible data processing. The m data flows processed by functional unit 2 of the transmitting device enter functional unit 2 of the receiving device via a medium. Functional unit 2 of the receiving device includes the m flows of the PCS function and the PMA and PMD shared by the m flows of the PCS function. The m data flows processed by functional unit 2 of the transmitting device enter functional unit 2 via a medium, are processed by the PMA and PMD of the receiving device, and then enter each of the m flows of the PCS function of the receiving device.The m flows of the PCS function in the functional part 2 of the receiving device correspond one-to-one with the m flows of the functional unit in the functional part 2 of the transmitting device, and each flow of the functional unit includes a reverse transcoding module, a descramble module, an alignment marker removal module, an FEC decoding module, and an alignment lock module. The m flows of the PCS function in the functional part 2 of the receiving device each receive the data transmitted by the m flows of the PCS function in the functional part 2 of the transmitting device. For example, the i-th flow of the PCS function among the m flows of the PCS function performs PCS processing on the data received from the PMA. The data output after processing by the m flows of the PCS function in the functional part 2 of the receiving device is processed by the data block distribution module and then enters the functional part 1 of the receiving device. The functional part 1 of the receiving device sequentially performs decoding, rate matching, adjustment, and MAC processing on the data from the data block distribution module to obtain an Ethernet frame.

[0087] In some embodiments, the data distribution location within the interface may differ, as shown in Figures 6A and 6B. Transcoded data is used as the distribution boundary. In this case, the data is distributed at the transcoded granularity (e.g., 257 bits), and functional part 2 processes the data flow at a 257-bit granularity. In Figure 6A, the interface includes functional part 1, functional part 2, and a data block distribution module located between functional part 1 and functional part 2. Functional part 1 includes a MAC module, an RS module, an encode and rate matching module at the PCS layer, and a transcode module. Functional part 2 includes multiple functional units, each of which includes a scramble module, an alignment marker insertion (AM insertion) module, an FEC encoding module, and a PMA / PMD module. Functional part 1 is coupled to functional part 2 via the data block distribution module and communicates with functional part 2. The Ethernet interface structure in Figure 6A can be applied to the transmitting device. The functions of the functional modules in Figure 6A, namely the MAC module, RS module, coding and rate matching module, transcode module, data block distribution module, scramble module, FEC module, PMA module, and PMD module, are the same as those of the corresponding modules in Figure 4A. Further details will not be explained here. In Figure 6A, functional unit 1 includes the MAC module, RS module, and transcode module. In the case of a transmitting device, after the transmitting device receives a packet, that packet enters functional unit 1 of the transmitting device. The MAC module in functional unit 1 processes the packet to form a data frame. The RS module converts the data frame into data of the corresponding bit width and sends that data to the coding and rate matching module. The coding and rate matching module processes the received data to generate 64B / 66B blocks. The 64B / 66B blocks are then forwarded to the transcode module.The transcoding module transcodes the received data block, for example, by performing 64B / 66B encoding on the data flow. Specific formats of data transcoded by the transcoding module include 256B / 257B, 512B / 513B, 256B / 258B, or 512B / 514B. Specific transcoding schemes are not limited herein.

[0088] The data block distribution module distributes the transcoded data flow to m flows of functional units contained in functional section 2, each of which includes a scramble module, an alignment marker insertion module, an FEC coding module, a PMA module, and a PMD module. The functions and operations of the scramble module, alignment marker insertion module, FEC coding module, PMA module, and PMD module as described herein are the same as the functions of the corresponding functional modules in Figure 4A. Details will not be described again here. The distribution of the transcoded data flow to m flows of functional units contained in functional section 2 by the data block distribution module particularly includes the distribution of the transcoded data flow to m flows of functional units contained in functional section 2 in a round-robin mode.

[0089] In some embodiments, in the functional unit 2 of Figure 6A, each of the m flows of the functional unit includes a scrambling module, an alignment lock module, and an FEC coding module. The FEC coding module in the m flows of the functional unit sends the FEC-processed data to one or more PMA modules. The data is processed by one or more PMA modules and then sent to one or more PMD modules for further processing. One or more PMD modules send the processed data to the receiving device via a transmission medium.

[0090] As shown in Figure 6B, the communication system includes a transmitting device and a receiving device. The transmitting device includes the interface shown in Figure 6A, and the receiving device includes an interface corresponding to the interface shown in Figure 6A. The receiving device's interface includes functional unit 1, functional unit 2, and a data block distribution module located between functional unit 1 and functional unit 2. Functional unit 1 includes a MAC module, an RS module, a decode and rate matching module at the PCS layer, and a transcode module. Functional unit 2 includes multiple functional units, each of which includes a descramble module, an alignment marker removal (AM Removal) module, an FEC decoding module, an alignment lock module, and a PMA / PMD module. Functional unit 1 is coupled to functional unit 2 via the data block distribution module and communicates with functional unit 2. The functions of the modules in the receiving device interface shown in Figure 6B—namely, the MAC module, RS module, decoding and rate matching module, reverse transcode module, data block distribution module, descramble module, alignment marker removal (AM Removal) module, FEC decoding module, alignment lock module, PMA module, and PMD module—are the same as those of the corresponding modules in Figure 4C. Further details will not be explained here.

[0091] In some embodiments, functional parts 1 and 2 of Figure 6A can be integrated into the same chip.

[0092] Refer to Figure 6C. In an alternative interface structure, data may be distributed at multiple granularities, e.g., 1-bit and 10-bit, when scrambling is used as the distribution boundary. The interface includes functional part 1, functional part 2, and a data block distribution module located between functional part 1 and functional part 2. Functional part 1 is coupled to and communicates with functional part 2 via data block distribution. Functional part 1 includes a MAC module, an RS module, an encode and rate matching module in the PCS layer, a transcode module, and a scramble module. Functional part 2 includes an AM insertion module, an FEC encoding module, and a PMA / PMD module. Functional part 2 includes m flows of functional units, each of which includes an alignment marker insertion module, an FEC module, and a PMA / PMD module.

[0093] As shown in Figure 6D, the communication system includes a transmitting device and a receiving device. The transmitting device includes the interface shown in Figure 6C, and the receiving device includes an interface corresponding to the interface shown in Figure 6C. The receiving device's interface includes functional unit 1, functional unit 2, and a data block distribution module located between functional unit 1 and functional unit 2. Functional unit 1 includes a MAC module, an RS module, a decode and rate matching module at the PCS layer, a detranscode module, and a descramble module. Functional unit 2 includes multiple functional units, each functional unit including an alignment marker removal (AM Removal) module, an FEC decoding module, an alignment lock module, and a PMA / PMD module. Functional unit 1 is coupled to functional unit 2 via the data block distribution module and communicates with functional unit 2. The functions of the receiving device's functional modules in Figure 6D, namely the MAC module, RS module, decoding and rate matching module, inverse transcoding module, data block distribution module, descramble module, alignment marker removal (AM Removal) module, FEC decoding module, alignment lock module, PMA module, and PMD module, are the same as those of the corresponding modules in Figure 4C. Further details will not be explained here. In the transmitting device, the MAC module processes the received packet to obtain a data frame and forwards that data frame to the RS module. The RS module converts the received data frame into data of the corresponding bit width and sends the converted data to the encoding and rate matching module. The encoding and rate matching module processes the data to generate 64B / 66B blocks. The transcoding module receives the data blocks processed by the encoding and rate matching module and transcodes the data blocks.Specific formats for data transcoded by the transcode module include 256B / 257B, 512B / 513B, 256B / 258B, or 512B / 514B. The specific transcoding scheme is not limited herein. The data flow transcoded by the transcode module is scrambled by the scrambling module and then sent to the data block distribution module. The data block distribution module distributes the received data flow into m flows of a functional unit within the functional part 2 of the transmitting device, where m is an integer greater than or equal to 1. Each of the m flows of the functional unit has an alignment marker insertion (AM) module that adds an alignment marker (AM) to the received data flow and then sends the data flow to the FEC encoding module. The FEC encoding module performs FEC encoding on the received data flow and then sends the processed data flow to the PMA module. The data flow is sent to the transmission medium via the PMA module and the PMD module. The processing performed on the data flow by the alignment marker insertion module of the transmitting device is the insertion of alignment markers, known as AM insertion. The distribution of the received data flow to m flows of functional units within the functional part 2 of the transmitting device by the data block distribution module particularly includes the distribution of the received data flow to m flows of functional units within the functional part 2 of the transmitting device by performing round-robin distribution on data flows scrambled at a specific granularity (e.g., 1 bit, 2 bits, 8 bits, or 10 bits).

[0094] In the receiving device, the receiving device receives data flows transmitted by the transmitting device, including the interface shown in Figure 6C, via the transmitting medium. The m data flows transmitted from the transmitting device each enter into m flows in the functional unit of the functional part 2 of the receiving device. For each of the m flows in the functional unit of the receiving device, the PMD module converts the received data, which conforms to the transmission format of the transmitting medium, into data conforming to the receiving device's format, and sends that data to the PMA module. The PMA module performs parallel-to-serial conversion on the received data and sends the converted data to the alignment lock module. The aligned data enters the FEC decoding module. The FEC decoding module performs FEC decoding on the data, removes alignment markers, and then sends the data to the data block distribution module. The data block distribution module sends the m received data flows to the descramble module of the functional part 1 of the receiving device's interface. The descramble module performs descrambling on the received data and then sends that data to the transcode module. The transcoding module performs reverse transcoding on the received data, transcoding data in formats such as 256B / 257B, 512B / 513B, 256B / 258B, and 512B / 514B into 64B / 66B code blocks. The reverse transcoding module sends the generated 64B / 66B code blocks to the decoding and rate matching module. The decoding and rate matching module processes the 64B / 66B blocks to obtain data of the corresponding bit width and sends that data to the RS module. The RS module processes the data of the corresponding bit width to obtain a data frame and sends that data frame to the MAC module for processing. The MAC module processes the data frame to obtain the packets transmitted by the transmitting device.The process by which the receiving device's alignment marker removal (AM Removal) module removes alignment markers from the received data flow is also called AM removal; the process performed by the receiving device's RS module on data of the corresponding bit width is called reconciliation; and the process by which the receiving device's FEC decoding module performs FEC decoding on the data flow is called FEC decoding.

[0095] In some embodiments, the transmitter device includes the interface shown in Figure 6A or Figure 6C, and the receiver device includes the IEEE 802.3 standard interface. m data flows processed by the transmitter device enter the receiver device via a medium. The PMA interface of the receiver device converts the received m data flows into data. The data is sent to the alignment marker removal module after the PMA module performs serial-to-parallel / parallel-to-serial conversion on the data. The aligned data enters the FEC decoding module. The FEC decoding module performs FEC decoding on the received data and sends the data to the descramble module. The descramble module descrambles the received data and sends the data to the transcode module. The transcode module transcodes the received data. Specific formats of the data transcoded by the transcode module include 256B / 257B, 512B / 513B, 256B / 258B, or 512B / 514B schemes. Specific transcoding schemes are not limited herein. The blocks obtained by reverse transcoding are processed sequentially by the data block distribution module, the decoding and rate matching module, and the RS module, and then reach the MAC module. In some embodiments, the RS module is connected to the decoding and rate matching module via the MII.

[0096] In some embodiments, in the m flows of the functional unit in the functional section 2 of Figures 6A to 6D, each flow of the functional unit does not necessarily have to include a PMA module or a PMD module, and the m flows of the functional unit share one PMA module and one PMD module.

[0097] In some embodiments, the functional part 2 of the interface in the embodiments of the present invention can be extended, and the functional part 2 may include two or more levels of functional part 2. For example, in Figure 7A, two levels of functional part 2 are used to achieve FEC coupling and extend the transmission distance. Functional part 1 includes an encode and rate matching functional unit at the MAC, RS, and PCS layers. Functional part 2 includes two levels. The first level includes a plurality of first-level functional units. Each first-level functional unit includes a transcode module, a scramble module, an alignment marker insertion module, an FEC encoding module, and a PMA module. The second level includes a plurality of second-level functional units, each of which corresponds one-to-one with a first-level functional unit. Each second-level functional unit includes a PCS / FEC / PMA module and a PMD module. Functional part 1 is coupled to functional part 2 via a data block distribution module and communicates with functional part 2.

[0098] The interface shown in Figure 7A includes Functional Unit 1, Functional Unit 2, and a Data Block Distribution Module. Functional Unit 2 includes m flows of first-level functional units and m flows of second-level functional units, with the m flows of the second-level functional units corresponding one-to-one with the m flows of the first-level functional units. Functional Unit 1 includes a MAC module, an RS module, and a coding and rate matching module. Each first-level functional unit includes a transcoding module, a scrambling module, an alignment lock module, an FEC coding module, and a PMA module. Each second-level functional unit includes a PCS module, an FEC module, and a PMA / PMD module.

[0099] As shown in Figure 7B, the communication system includes a transmitting device and a receiving device. The transmitting device includes the interface shown in Figure 7A, and the receiving device includes the interface corresponding to the interface in Figure 7A. In the transmitting device, a MAC module processes the received packet flow to obtain a data frame and forwards the data frame to an RS module. The RS module converts the received data frame into data of the corresponding bit width and sends the converted data to an encoding and rate matching module. The encoding and rate matching module processes the data to generate a data block, for example, a 64B / 66B block, and sends the data block to a data block distribution module. The data block distribution module receives the data block processed by the encoding and rate matching module and distributes the data block to m flows of the first-level functional unit in the functional part 2 of the transmitting device, where m is a positive integer greater than or equal to 1. The method by which the data block distribution module distributes the data block to the m flows of the first-level functional unit in the functional part 2 and to the functions of each module in each flow of the first-level functional unit is the same as in the previously described embodiment. Details will not be explained again here. The m data flows processed by the transmitting device enter the receiving device via the medium. The second-level functional unit, first-level functional unit, data block distribution module, decoding and rate matching module, RS module, and MAC module of the receiving device's interface sequentially process the received m data flows to obtain an Ethernet frame. Specifically, the data of the m flows processed by the transmitting device reaches the m flows of the second-level functional unit corresponding to the transmitting device's interface within the second-level functional unit via the medium. The PMD module and PCS / FEC / PMA module within each flow of the functional unit convert the received data into data. The data enters the corresponding flows of the first-level functional unit within the first-level functional unit.Each PMA module within the flow of the first-level functional unit performs serial-to-parallel / parallel-to-serial conversion on the received data and sends the converted data to the FEC decoding module. The FEC decoding module performs FEC decoding on the received data. The data obtained by FEC decoding is processed sequentially by the alignment marker removal (AM removal) module, the descramble module, and the transcode module, and then reaches the data block distribution module. The alignment marker removal module removes alignment markers from the data. The descramble module descrambles the data from which the alignment markers have been removed. The descrambled data reaches the reverse transcode module. The reverse transcode module performs reverse transcoding on the received data. Specific formats of data transcoded by the transcode module include 256B / 257B, 512B / 513B, 256B / 258B, or 512B / 514B. Specific transcoding schemes are not limited in this application. The transcoded blocks are processed sequentially by the data block distribution module, the decoding and rate matching module, and the RS module, before reaching the MAC module. In some embodiments, the RS module is connected to the decoding and rate matching module via the MII.

[0100] Refer to Figure 7C. The second-level functional unit further includes an integrated package oDSP (Optical Digital Signal Processor). The output of the PMA from the second-level functional unit enters the oDSP. The data flow or data frame flow output after processing by the oDSP is sent to the PMD, processed by the PMD, and then enters the laser. Alternatively, the data flow or data frame flow output by the oDSP can be used as a laser drive signal without the need to modulate and pass it through the PMD module. Modulation can be completed by the oDSP or another modulator.

[0101] Optionally, the oDSP may include additional new FEC encoding functions (FEC encoding x) for encoding data processed by the oDSP. The FEC encoding at the first level of the functional unit is RS FEC encoding. Secondary FEC encoding is performed after processing by the oDSP. Secondary FEC encoding may be BCH FEC or RS FEC encoding.

[0102] Optionally, the second-level functional unit may further include an FEC decoding module. The FEC decoding module decodes the data flow or data frame flow encoded by the FEC encoding module in the first-level functional unit, and the decoded data flow enters the FEC encoding x of the oDSP in the second-level functional unit for secondary FEC encoding. The FEC decoding module is located in either the first-level or second-level functional unit. The FEC encoding x may be configured in the oDSP or independently.

[0103] In some embodiments, the communication system includes a transmitting device and a receiving device. The transmitting device includes the interface shown in Figure 7C, and the interface included in the receiving device is an interface of any architecture, for example, the interface shown in Figures 4A, 4B, 7A, or 7B, or an IEEE 802.3 standard Ethernet interface.

[0104] In some embodiments, the communication system includes a transmitting device and a receiving device. The transmitting device includes the interface shown in Figure 7C, and the interface included in the receiving device is an interface of any architecture, for example, Figures 4A, 4B, 4G, 5A, 6A, 7A, 7C, 8, 9, 10, 11, or 12A, or an IEEE 802.3 standard Ethernet interface.

[0105] In Figures 3 to 7, in the diagrams of each group of functional units within Functional Unit 2, each block diagram represents only the function and not the number of circuits and modules that perform the function. For example, the FEC function may include multiple FEC encoders / decoders. Data obtained by FEC coding is not necessarily output through a single lane, but rather through multiple virtual lanes (or PCS lanes).

[0106] The following describes in detail the technical solutions in embodiments of the present invention based on a specific MAC rate.

[0107] Embodiment 1: Functional part 2 includes a group of functional units that support a MAC rate of 800 Gb / s.

[0108] Figure 8 is a schematic diagram of a possible 800GE interface structure. The interface includes a functional section 1, a functional section 2, and a data block distribution joule located between functional section 1 and functional section 2. Functional section 1 includes a MAC module, an RS module, and a coding and rate matching module. Functional section 2 includes a transcode module, a scramble module, an alignment lock module, an FEC coding module, a PMA module, and a PMD module. The FEC coding module is configured to perform FEC coding on the data flow. It outputs 66-bit data blocks coded based on 64B / 66B. These data blocks enter functional section 2 in their original order via data block distribution, and the processing steps of functional section 2 are performed one by one. Functional section 2 includes one or more groups of functional units. Each group of functional units includes a transcode module, a scramble module, an AM insertion module, an 800G FEC module, a PMA module, and a PMD module. The transcoding described herein may be 64B / 66B to 256B / 257B transcoding, the same as IEEE 802.3-2018. AM insertion may be an AM insertion scheme similar to that of 200GE / 400GE interfaces. FEC coding may be Reed-Solomon RS-FEC, which performs coding and interleaving of multiple code blocks. After coding, the data is interleaved based on FEC symbols (10-bit symbols) and distributed to multiple PCS lanes, and then adapted to multiple types of PMDs via Bit-mux (bit multiplexing) at the PMA layer.

[0109] In some embodiments, the functional unit 2 may include a plurality of functional units, each functional unit including a transcoding module, a scrambling module, an alignment marker insertion module, an FEC coding module, a PMA module, and a PMD module. For specific embodiments, please refer to the embodiments described above. The interface shown in Figure 8 can be applied to the transmitting device. For the data processing method of the transmitting device, please refer to the embodiments described above.

[0110] Embodiment 2: Functional part 2 includes two groups of functional units, and the 1.6TbE interface is implemented using the technology of Embodiment 1.

[0111] Based on the interface architecture shown in Figure 8, a 1.6 Tb / s Ethernet MAC can be supported by implementing functional units in two groups within functional section 2, as shown in Figure 9. The MAC module, RS module, coding, and rate matching modules are located in functional section 1 and are functionally similar to Embodiment 1, but with double the rate. The data block distribution module distributes the coded 66-bit data blocks to two groups of functional units within functional section 2 in round-robin mode. Thus, the execution rate and execution method of each group of functional units are the same as in Embodiment 1. The PMA layer can perform simple bit-level operations across the functional units, i.e., it can perform bit-muxing on two parts of the data to support multiple types of PMDs.

[0112] Embodiment 3: Functional unit 2 is connected in order to perform FEC linking.

[0113] In Figure 10, Functional Unit 1 includes MAC, RS, coding, and rate matching functions. It outputs 66-bit data blocks coded based on 64B / 66B. These data blocks enter Functional Unit 2 in their original order via data block distribution, and the processing steps of Functional Unit 2 are performed one by one. Functional Unit 2 includes a first level and a second level, with the functional units at the two levels being distinct. For example, the first level of "Functional Unit 2" includes multiple groups of functional units, each group of functional units containing multiple functional submodules such as a transcode submodule, scramble submodule, alignment marker insertion submodule, FEC coding submodule, and PMA submodule. The data processed by the first level enters the second level. "Concatenated Functional Unit 2," i.e., the second level, can perform second-level FEC coding operations on the output data flow from the upper layer. The second level contains functional units that correspond one-to-one with those of the first level, each functional unit containing PCS / FEC / PMA and PMD. The two levels of functionality of functional part 2 are to process data transmitted from the upper layers of the two levels without functional part 1 needing to sense the MAC data protocol. A typical scenario of the present invention may be one in which a host chip (host ASIC) is externally connected to an optical digital signal processor (oDSP). The second level functional part 2 does not terminate the FEC of the upper layers, but can directly perform FEC coding at the second level. For example, the first level FEC is RS(544,514) FEC coding, and the second level FEC may be one or more of BCH code (Bose-Chaudhuri-Hocquenghem code) FEC, polarity FEC, low density parity check (LDPC) FEC, concatenated FEC (CFEC), open FEC (OFEC), turbo product code (TPC) FEC, and source coding FEC (SCFEC).

[0114] Embodiment 4: Functional unit 2 is connected in order to perform FEC linkage.

[0115] As shown in Figure 11, similar to Embodiment 3, in some scenarios stronger FEC protection may be required between the two functional parts 2. As shown in Figure 11, the upper layer functional part 2 already includes a concatenated FEC, and RS+BCH concatenation is used. However, in the concatenated functional part 2, due to data overhead limitations and SerDes rate limitations, it may be necessary to first remove the internal code of the concatenated FEC, and then encapsulation is performed by a stronger FEC frame in the oDSP. In this case, the concatenated functional part 2 does not need to perform operations on data flows corresponding to the MAC rate of functional part 1, and only processes data flows corresponding to the rate of one functional unit in the upper layer functional part 2.

[0116] According to the technical solution of this invention, multi-flow parallel processing of functional unit 2 allows one flow of a functional unit to be replicated to multiple flows of functional units, any rate can be achieved by the combination of functional units, ultimately enabling the reuse of investment (operation) in functional units and significantly reducing the cost of the Ethernet interface.

[0117] In some embodiments, an Ethernet interface is divided from the logical layer architecture into two functional layers: Functional layer 1, which processes based on the total data rate of a particular interface, and Functional layer 2, which processes based on a subset (a portion of the total data rate) of the particular interface speed. Functional layer 2 includes at least one functional unit. In some embodiments, functional layer 2 includes two or more functional units.

[0118] In some embodiments, functional unit 1 completes data processing based on a specific total data rate and includes a MAC sublayer and RS sublayer in the current Ethernet standard, as well as a 64 / 66B encoding / decoding sublayer subordinate to the PCS sublayer. Functional unit 1 may further include a transcoding sublayer, a scrambling / descrambling sublayer, or a full PCS / FEC / PMA sublayer for a specific total data rate, depending on different embodiments.

[0119] In some embodiments, functional unit 1 distributes data to functional units subordinate to functional unit 2 in a round-robin mode based on specific rules or sequences, and data blocks that do not reflect the contents of a packet format at a particular interface speed are obtained by the distribution. The granularity of the data blocks may be bits, 64 / 66B, transcoded 256 / 257B, another different transcoded data format, FEC symbols, or a combination thereof.

[0120] In some embodiments, each functional unit of functional section 2 performs PCS / FEC / PMA layer processing on data blocks from functional section 1 as necessary for further data transmission. However, panoramic information of the specific interface speed of functional section 1 does not need to be known for processing. In short, it is understood that each functional unit considers only the information about the data received from the functional unit, performs re-interleaving and recombination to form data blocks, and then performs PCS / FEC / PMA layer processing based on the data blocks. Content information that can be reflected simply by sensing the total data rate data of functional section 1 does not need to be processed in composite processing, and processing is performed without the need to recover or sense specific information (Idle and Preamble / SFD) of the Ethernet data frames of functional section 1. Furthermore, only bit-level data recombination or interleaving and distribution is optionally performed between different functional units in the PMA layer, and interaction based on sensing information obtained through multi-bit combinations does not need to be performed between multiple functional units.

[0121] In some embodiments, each functional unit of functional unit 2 operates independently and no longer needs to recover some or all of the functions of functional unit 1 at a particular interface speed. For example, functional unit 2 no longer performs unified adjustment of Idle insertion or deletion in functional unit 1, or no longer performs AM identification in functional unit 1, or no longer recovers the corresponding data after realignment.

[0122] In some embodiments, each functional unit in functional section 2 corresponds to a PMD physical layer dependent on that functional unit. In this way, theoretically, multiple functional units can be combined in any number to form the physical layer solution required by an Ethernet interface matching a specific rate, thereby realizing a rate-independent Ethernet architecture.

[0123] In some embodiments, the interface in the embodiments of the present invention is an independent chip or functional module located on another device.

[0124] In some embodiments, the interface in the embodiments of the present invention is located in a network device, workstation, storage device, or server.

[0125] In some embodiments, the workstation may be various types of devices such as a host, terminal, server, or virtual machine. The network device may be a device configured to forward packets in a communication network, such as a switch or router. Furthermore, network devices within the same communication network may be the same network device or different network devices. For example, all network devices within the same communication network may be routers, some network devices may be routers, and others may be switches.

[0126] In the non-breakout scenarios shown in Figures 1 to 11 of this application, collaborative insertion (e.g., insertion based on bit intervals or code block intervals) between multiple functional units is required in the process of inserting alignment markers. In this way, the receiving side can perform data block recovery operations based on the distribution sequence of the transmitting side's distribution unit.

[0127] Embodiment 5: Breakout Scenario

[0128] In a breakout scenario, a high-capacity port is isolated via a physical channel to support multiple low-speed ports or interfaces. For example, a 400GbE port supporting breakout in a switch can support four 100GbE ports or eight 50GbE ports via breakout cables, fanout cables, or modules. The present invention has the inherent advantage of supporting breakout scenarios because functional part 2 naturally supports multi-flow parallelism. For example, if functional part 1 already has a 1.6TbE MAC and functional part 2 has eight flows of functional units, each flow supporting a data processing capacity of 200Gb / s, then 2*800GbE breakout can be implemented in the architecture with minor modifications, as shown in Figure 12A. In this case, functional part 1 includes a 1.6TbE functional unit that is divided into two 800GbE functional units, each unit being a standard 800GbE MAC. The eight functional units of functional part 2 remain unchanged. Only the final data aggregation mode is changed. One output flow is changed to two output flows. Each flow is a standard 800GbE physical port.

[0129] In a breakout scenario, each unit carries its own Ethernet data flow. The alignment marker insertion process is adaptive; joint insertion between multiple functional units is not required. In other words, data block recovery operations can be performed on the receiver side based on the distribution sequence of the transmitter-side distribution unit.

[0130] Refer to Figure 12B. In some embodiments, the communication system includes a receiving device and multiple transmitting devices. The transmitting device interface is an IEEE 802.3 standard Ethernet interface. The receiving device includes an interface corresponding to the interface shown in Figure 4A, but further includes an alignment lock module between the PMA module and the FEC module. The scramble module in Figure 4A is replaced with a descramble module, and the alignment marker insertion (AM Insertion) module in Figure 4A is replaced with an alignment marker removal (AM Removal) module. The transmitting device interface processes the data to be transmitted using the IEEE 802.3 Ethernet interface processing method and then transmits the processed data to the receiving device via a medium. The receiving device interface receives data from the transmitting device. In a breakout scenario, the receiving device interface distributes the data from the multiple transmitting device interfaces to one or more functional units located within the receiving device interface and corresponding to the speed of the transmitting device interfaces. For example, four IEEE 802.3 standard Ethernet interfaces with a rate of 200 Gbps send data to the interface shown in Figure 4A. The interface shown in Figure 4A receives the four data flows at a speed of 200 Gbps, and in the functional part 2 of the interface, it maps the four data flows at a speed of 200 Gbps to four functional units at a speed of 200 Gbps, performs processing in functional part 2, then performs processing in functional part 1, and acquires the data transmitted by the four transmitting devices.

[0131] Refer to Figure 12C. The communication system includes a receiving device and multiple transmitting devices. The transmitting device interface is an IEEE 802.3 standard Ethernet interface. The receiving device includes an interface corresponding to the interface shown in Figure 4B, but further includes an alignment lock module between the PMA module and the FEC module. The scramble module in Figure 4B is replaced with a descramble module, and the alignment marker insertion (AM Insertion) module in Figure 4B is replaced with an alignment marker removal (AM Removal) module. The process by which the transmitting device interface processes the data to be transmitted is similar to the operation of the transmitting device interface in Figure 12B. Details will not be described again here.

[0132] Refer to Figure 12D. The communication system includes a receiving device and multiple transmitting devices. The transmitting device interface is an IEEE 802.3 standard Ethernet interface. The receiving device includes an interface corresponding to the interface shown in Figure 5A, but further includes an alignment lock module between the PMA module and the FEC module. The scramble module in Figure 5A is replaced with a descramble module, and the alignment marker insertion (AM Insertion) module in Figure 5A is replaced with an alignment marker removal (AM Removal) module. The process by which the transmitting device interface processes the data to be transmitted is similar to the operation of the transmitting device interface in Figure 12B. Details will not be described again here.

[0133] Refer to Figure 12E. The communication system includes a receiving device and multiple transmitting devices. The transmitting device interface is an IEEE 802.3 standard Ethernet interface. The receiving device includes an interface corresponding to the interface shown in Figure 6A, but further includes an alignment lock module between the PMA module and the FEC module. The scramble module in Figure 6A is replaced with a descramble module, and the alignment marker insertion (AM Insertion) module in Figure 6A is replaced with an alignment marker removal (AM Removal) module. The process by which the transmitting device interface processes the data to be transmitted is similar to the operation of the transmitting device interface in Figure 12B. Details will not be described again here.

[0134] Refer to Figure 12F. The communication system includes a receiving device and multiple transmitting devices. The transmitting device interface is an IEEE 802.3 standard Ethernet interface. The receiving device includes an interface corresponding to the interface shown in Figure 6C, but further includes an alignment lock module between the PMA module and the FEC module. The scramble module in Figure 6C is replaced with a descramble module, and the alignment marker insertion (AM Insertion) module in Figure 6C is replaced with an alignment marker removal (AM Removal) module. The process by which the transmitting device interface processes the data to be transmitted is similar to the operation of the transmitting device interface in Figure 12B. Details will not be described again here.

[0135] Refer to Figure 12G. The communication system includes a receiving device and multiple transmitting devices. The transmitting device interface is an IEEE 802.3 standard Ethernet interface. The receiving device includes an interface corresponding to the interface shown in Figure 7A, but further includes an alignment lock module between the PMA module and the FEC module. The scramble module in Figure 7A is replaced with a descramble module, and the alignment marker insertion (AM Insertion) module in Figure 7A is replaced with an alignment marker removal (AM Removal) module. The process by which the transmitting device interface processes the data to be transmitted is similar to the operation of the transmitting device interface in Figure 12B. Details will not be described again here.

[0136] In the functional unit of the functional part 2 of the interface of the receiving device in the embodiment of the present invention, if there is only one PCS lane, only alignment lock needs to be performed. Alternatively, if there are multiple PCS lanes, lane deskew needs to be performed between the lanes after alignment lock.

[0137] In some embodiments, the functional units of the functional section 2 of the receiving device's interface can share an FEC decoding module. Specifically, multiple functional units or all functional units within the functional section 2 share the same FEC decoding module, and the same FEC decoding module performs FEC decoding on data from other modules within the multiple functional units or all functional units.

[0138] Figure 13 is a schematic diagram of the structure of device 2100 according to an exemplary embodiment of the present application. Device 2100 is, for example, a switch or a router, and device 2100 may be implemented using a bus architecture.

[0139] As shown in Figure 13, the device 2100 includes a main control board 2110 and an interface board 2130. The interface board 2130 includes any interface shown in Figures 3 to 12.

[0140] The main control board is also called the main processing unit (MPU) or route processor card. The main control board 2110 is configured to control and manage the components within the device 2100, including route calculation, device management, device maintenance, and protocol-based processing. The main control board 2110 includes a central processing unit 2111 and memory 2112.

[0141] The interface board 2130 is also called a line processing unit (LPU), line card, or service board. The interface board 2130 is configured to provide various service interfaces and forward data packets. These service interfaces include, but are not limited to, Ethernet interfaces and POS (Packet over SONET / SDH) interfaces. An example of an Ethernet interface is a Flexible Ethernet Client (FlexE Client). The interface board 2130 includes a central processing unit 2131, a network processor 2132, a forwarding entry memory 2134, and a physical interface card (PIC) 2133.

[0142] The central processing unit 2131 on the interface board 2130 is configured to control and manage the interface board 2130 and to communicate with the central processing unit 2111 on the main control board 2110.

[0143] The network processor 2132 is configured to forward packets. The form of the network processor 2132 may be a forwarding chip. The forwarding chip may be a network processor (NP). In some embodiments, the forwarding chip may be implemented using an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Specifically, the network processor 2132 is configured to forward received packets based on a forwarding table stored in the forwarding entry memory 2134. If the destination address of a packet is the address of device 2100, the network processor 2132 sends the packet to the CPU (e.g., the central processing unit 2131) for processing. If the destination address of a packet is not the address of device 2100, the network processor 2132 looks up the next hop and outbound interface corresponding to the destination address in the forwarding table based on the destination address and forwards the packet to the outbound interface corresponding to the destination address. Processing of uplink packets may include processing at the packet entry interface and forwarding table lookups, while processing of downlink packets may include forwarding table lookups, etc. In some embodiments, the central processing unit may also perform the functions of a forwarding chip, for example, software forwarding can be implemented based on a general-purpose CPU. Therefore, a forwarding chip is not required on the interface board.

[0144] The physical interface card 2133 is configured to perform physical layer interconnection functions. Original traffic enters the interface board 2130 from the physical interface card 2133, and processed packets are sent out from the physical interface card 2133. The physical interface card 2133, also called a subcard, can be mounted on the interface board 2130 and is responsible for converting optical / electrical signals into packets, performing packet validity checks, and forwarding packets to the network processor 2132 for processing. In some embodiments, the central processing unit 2131 can also perform the functions of the network processor 2132, for example, by performing software forwarding based on a general-purpose CPU. Therefore, the physical interface card 2133 does not require the network processor 2132.

[0145] Optionally, the device 2100 includes multiple interface boards. For example, the device 2100 further includes an interface board 2140, which includes a central processing unit 2141, a network processor 2142, a forwarding entry memory 2144, and a physical interface card 2143. The functions and embodiments of the components of interface board 2140 are identical or similar to those of interface board 2130 and will not be described again in detail here. The interface board includes one or more interfaces as described in the embodiments described above.

[0146] Optionally, the device 2100 further includes a switching board 2120. The switching board 2120 may also be called a switch fabric unit (SFU). When the device has multiple interface boards, the switching board 2120 is configured to complete data exchange between the interface boards. For example, interface boards 2130 and 2140 can communicate with each other via the switching board 2120.

[0147] The main control board 2110 is coupled to the interface boards. For example, the main control board 2110, interface board 2130, interface board 2140, and switching board 2120 are connected to the system backplane via a system bus to enable interworking. In possible embodiments, inter-process communication (IPC) channels are established between the main control board 2110 and interface board 2130, and between the main control board 2110 and interface board 2140, and the main control board 2110 communicates with interface boards 2130 and 2140 via the IPC channels.

[0148] Logically, the device 2100 includes a control plane and a forwarding plane. The control plane includes a main control board 2110 and a central processing unit 2111. The forwarding plane includes components used for forwarding, such as a forwarding entry memory 2134, a physical interface card 2133, and a network processor 2132. The control plane performs functions such as routing, generating forwarding tables, signaling and processing protocol packets, and configuring and maintaining the device status. The control plane distributes the generated forwarding tables to the forwarding plane. In the forwarding plane, the network processor 2132 looks up the forwarding tables distributed by the control plane and forwards packets received by the physical interface card 2133. The forwarding tables distributed by the control plane may be stored in the forwarding entry memory 2134. In some embodiments, the control plane and the forwarding plane may be completely separate and not on the same device.

[0149] There may be one or more main control boards, and if there are multiple main control boards, note that the main control boards may include a primary main control board and a secondary main control board. There may be one or more interface boards, and the more interface boards provided, the more powerful the device's data processing capabilities become. Interface boards may contain one or more physical interface cards. Switching boards, or one or more switching boards, may not be present. If there are multiple switching boards, they can work together to perform load balancing and redundant backup. In a centralized forwarding architecture, switching boards are not required within the device, and interface boards provide the functionality to process service data for the entire system. In a distributed forwarding architecture, a device may have at least one switching board, and data exchange between multiple interface boards is performed using the switching board, providing high-capacity data exchange and processing capabilities. Therefore, the data access and processing capabilities of a distributed architecture device are superior to those of a centralized architecture device. Optionally, the device may alternatively consist of only one card. Specifically, there is no switching board, and the functions of the interface board and main control board are integrated into a single card. In this case, the central processing unit on the interface board and the central processing unit on the main control board are combined to form a single central processing unit on the card, and the functions obtained by combining the two central processing units can be performed. Devices of this form (e.g., low-end switches or routers) have weak data exchange and processing capabilities. The specific architecture to be used depends on the specific network deployment scenario, and is not limited herein.

[0150] Please understand that the processor may be a Central Processing Unit (CPU), or it may be another general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), another programmable logic unit, a discrete gate or transistor logic unit, or a discrete hardware component, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. Note that the processor is one that supports the Advanced Reduced Instruction Set Computing Machine (ARM) architecture.

[0151] Furthermore, in optional embodiments, the memory may include read-only memory and random-access memory that can provide instructions and data to the processor. The memory may further include non-volatile random-access memory. For example, the memory may further store information about the device type.

[0152] The memory may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically erasable programmable read-only memory (electrically EPROM, EEPROM), or flash memory. Volatile memory may be random access memory (RAM) used as an external cache. Rather than being limited, many forms of RAM can be used, such as static random access memory (static RAM, SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (synchronous DRAM, SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, ESDRAM), synchlink dynamic random access memory (synchlink DRAM, SLDRAM), and direct rambus random access memory (direct rambus RAM, DR RAM).

[0153] Figure 14 is a schematic diagram of the structure of device 4000 according to an exemplary embodiment of the present application. Device 4000 shown in Figure 14 is configured to perform operations related to the functions of the interface shown in any one of Figures 3 to 12. Device 4000 may be, for example, a switch, router, controller, or a server, storage device, or network device. Device 4000 may be implemented using a bus architecture.

[0154] As shown in Figure 14, the device 4000 includes at least one processor 4001 and at least one communication interface 4004. In some embodiments, the processor 4001 is coupled to a memory 4003.

[0155] The processor 4001 is, for example, a general-purpose central processing unit (CPU), digital signal processor (DSP), network processor (NP), graphics processing unit (GPU), neural network processing unit (NPU), data processing unit (DPU), microprocessor, or one or more integrated circuits configured to realize the solution of the present invention. For example, the processor 4001 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or another programmable logic device, a transistor logic device, a hardware component, or any combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The processor 4001 can implement or execute various logic block modules and circuits described with reference to the embodiments disclosed in the present invention. Alternatively, the processor may be a combination of processors that perform computing functions, for example, a combination of one or more microprocessors, or a combination of a DSP and a microprocessor.

[0156] Optionally, device 4000 may further include buses. These buses are configured to transmit information between components within device 4000. Buses may be peripheral component interconnect (PCI) buses, extended industry standard architecture (EISA) buses, etc. Buses can be classified into address buses, data buses, control buses, etc. For ease of representation, only a single thick line is used to represent the buses in Figure 14; however, this does not mean that there is only one bus or only one type of bus.

[0157] Memory 4003 is, for example, read-only memory (ROM) or another type of static storage device capable of storing static information and instructions, random access memory (RAM) or another type of dynamic storage device capable of storing information and instructions, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or another compact disc storage device, optical disc storage device (including compact discs, laser discs, optical discs, digital versatile discs, or Blu-ray discs, etc.), magnetic disk storage medium or another magnetic storage device, or any other medium that can be used to transport or store expected program code in the form of instructions or data structures and that is accessible by a computer. For example, memory 4003 may exist independently and be connected to processor 4001 via a bus. Alternatively, memory 4003 may be integrated with processor 4001.

[0158] The communication interface 4004 is any device, such as a transceiver, and is configured to communicate with another device or communication network. The communication network may be Ethernet, a wireless access network (RAN), or a wireless local area network (WAN), etc. The communication interface 4004 may include a wired communication interface and may further include a wireless communication interface. Specifically, the communication interface 4004 may be an Ethernet interface, a Fast Ethernet (FE) interface, a Gigabit Ethernet (GE) interface, an Asynchronous Transfer Mode (ATM) interface, a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof. The Ethernet interface may be an optical interface, an electrical interface, or a combination thereof. In this embodiment of the present application, the communication interface 4004 may be used by device 4000 to communicate with another device.

[0159] In certain embodiments, the processor 4001 may include one or more CPUs, for example, CPU0 and CPU1 shown in Figure 14. Each processor may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. A processor as used herein may be one or more devices, circuits, and / or processing cores configured to process data (e.g., computer program instructions).

[0160] In certain embodiments, the device 4000 may include a plurality of processors, for example, processors 4001 and 4005 shown in Figure 14. Each processor may be a single-core processor (single CPU) or a multi-core processor (multi-CPU). A processor as used herein may be one or more devices, circuits, and / or processing cores configured to process data (e.g., computer program instructions).

[0161] In certain embodiments, the device 4000 may further include an output device and an input device. The output device communicates with the processor 4001 and can display information in multiple ways. For example, the output device may be a liquid crystal display (LCD), a light-emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 4001 and can receive input from the user in multiple ways. For example, the input device may be a mouse, a keyboard, a touchscreen device, or a sensor device.

[0162] In some embodiments, memory 4003 is configured to store program code 4010 for executing the solution of the present invention, and processor 4001 can execute the program code 4010 stored in memory 4003. In other words, device 4000 can use processor 4001 and the program code 4010 in memory 4003 to implement the functions of the interface shown in any one of Figures 3 to 12. The program code 4010 may include one or more software modules. Optionally, processor 4001 may instead store program code or instructions for executing the solution of the present invention.

[0163] In some embodiments, the communication interface 4004 is configured to perform operations related to the functionality of the interface shown in any one of Figures 3 to 12.

[0164] One embodiment of the present invention further provides a computer-readable storage medium. The storage medium stores at least one instruction, which is loaded and executed by a processor to realize the functionality of an interface shown in any one of Figures 3 to 12.

[0165] One embodiment of the present invention provides a computer program (product). When the computer program is executed by a computer, the processor or computer may be able to perform the functions of the interface shown in any one of Figures 3 to 12.

[0166] One embodiment of the present invention provides a chip including a processor configured to call and execute instructions stored in memory, wherein a communication device on which this chip is installed performs the functions of an interface shown in any one of Figures 3 to 12.

[0167] One embodiment of the present invention further provides another chip including an input interface, an output interface, a processor, and memory. The input interface, output interface, processor, and memory are connected to each other via an internal connection path. The processor is configured to execute code in memory. Once the code is executed, the processor is configured to perform the functions of the interface shown in any one of Figures 3 to 12.

[0168] In the embodiment described above, if the functional part 2 includes m flows of functional units and the rate of the corresponding MAC data flow that can be processed by each functional unit is R, then the maximum rate of the functional part 1 that can be supported by the functional part 2 is m*R. Typically, the value of m is an integer power of 2, for example, m=2 kHere, k = 0, 1, 2, ... The value of R is typically 5 Gbps, 10 Gbps, 25 Gbps, 50 Gbps, 100 Gbps, 200 Gbps, or 400 Gbps, etc.

[0169] In some embodiments, the actual output rates can exceed the nominal 100Gbps and 200Gbps by introducing functions such as coding, transcoding, and FEC to each functional unit. For example, in the case of a 100Gbps MAC data flow, if 64B / 66B coding and 256B / 257B transcoding are used and RS(544,514) FEC coding is added, the data flow rate becomes 106.25Gbps. Alternatively, if the FEC is RS(528,514), the coded rate is 103.125Gbps. Generally, the rate is referred to as 100G in the industry. The same applies to other rates.

[0170] When the number of functional units within functional part 1 is n, the corresponding n*2 k Functional unit 2 can be used for support.

[0171] All or part of the embodiments described above can be implemented by software, hardware, firmware, or any combination thereof. When an embodiment is implemented using software, all or part of the embodiment may be implemented in the form of a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded into a computer and executed, all or part of the procedures or functions of the present application are generated. The computer may be a general-purpose computer, a dedicated computer, a computer network, or another programmable device. The computer instructions may be stored in a computer-readable storage medium and may be transmitted from one computer-readable storage medium to another. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, or digital subscriber line) or wireless (infrared, radio waves, microwave, etc.). The computer-readable storage medium may be any available medium accessible by a computer, or a data storage device such as a server or data center that integrates one or more available media. The usable media may be magnetic media (e.g., floppy disks, hard disks, or magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0172] The specific embodiments described above provide further details of the object, technical solution, and beneficial effects of the present application. It should be understood that the above descriptions represent only specific embodiments of the present application and are not intended to limit the scope of protection. Any modifications, equivalent replacements, improvements, etc., made based on the technical solution of the present application shall be within the scope of protection.

[0173] Those skilled in the art will recognize that the method steps and modules described with reference to the embodiments disclosed herein may be implemented by software, hardware, firmware, or a combination thereof. To clearly illustrate the compatibility between hardware and software, the steps and configurations of each embodiment have been generally described above according to their function. Whether a function is performed in hardware or software depends on the specific application and the design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such embodiments should not be considered beyond the scope of the Application.

[0174] Those skilled in the art will understand that all or part of the steps of the embodiment may be carried out by a program that instructs hardware or related hardware. The program may be stored in a computer-readable storage medium, which may be read-only memory, a magnetic disk, or an optical disk, etc.

[0175] When an embodiment is implemented using software, all or part of the embodiment may be implemented in the form of a computer program product. A computer program product includes one or more computer program instructions. For example, the method in the embodiment of this application can be described in the context of machine-executable instructions. Machine-executable instructions are contained in program modules that are executed, for example, on a component on a target real or virtual processor. Generally, a program module includes routines, programs, libraries, objects, classes, components, and data structures, etc., that perform a specific task or implement a specific abstract data structure. In various embodiments, the functionality of program modules may be combined or divided among the described program modules. The machine-executable instructions of a program module may be executed locally or in a distributed device. In a distributed device, program modules may reside on both local and remote storage media.

[0176] The computer program code used to carry out the method in the embodiments of this application may be written in one or more programming languages. The computer program code may be provided to a processor of a general-purpose computer, a dedicated computer, or another programmable data processing device, and when the program code is executed by the computer or the other programmable data processing device, the functions / operations specified in the flowchart and / or block diagram are performed. All of the program code may be executed on a computer, or some may be executed on a computer as a standalone software package, or some may be executed on a computer while some is executed on a remote computer, or all of the program code may be executed on a remote computer or server.

[0177] In the context of the embodiments of the present application, computer program code or related data may be carried by any suitable carrier so that a device, instrument, or processor can perform the various processes and operations described above. Examples of carriers include signals and computer-readable media.

[0178] Examples of signals may include electrical signals, optical signals, radio signals, audio signals, or other forms of propagated signals such as carrier waves and infrared signals.

[0179] A machine-readable medium can be any tangible medium containing or storing programs used in or associated with an instruction execution system, device, or apparatus. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any suitable combination thereof. More specific examples of machine-readable storage media include electrical connections using one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical memory, magnetic memory, or any suitable combination thereof.

[0180] For the sake of a simple and concise explanation, it will be readily apparent to those skilled in the art that the detailed operating processes of the aforementioned systems, devices, and modules will be described by referring to the corresponding processes in the embodiments of the methods described above. Further details will not be provided here.

[0181] In some embodiments provided herein, it should be understood that the disclosed systems, apparatus, and methods can be implemented in other ways. For example, the embodiments of the apparatus described are merely examples. For example, modularization is merely a logical functional division, and in actual embodiments, there may be other divisions. For example, multiple modules or components may be combined or integrated into another system, or some functions may be ignored or not performed. Furthermore, the mutual coupling, direct coupling, or communication connection shown or discussed may be implemented through some interfaces. Indirect coupling or communication connection between apparatuses or modules may be electrical, mechanical, or other forms of connection.

[0182] Modules described as separate components may or may not be physically separated, and components represented as modules may or may not be physical modules, may be located in one place, or may be distributed across multiple network modules. To achieve the objectives of the solutions in the embodiments of this application, some or all of the modules may be selected according to the actual requirements.

[0183] Furthermore, the functional modules in the embodiments of the present invention may be integrated into a single processing module, or each module may exist physically independently, or two or more modules may be integrated into a single module. The integrated module may be implemented in hardware form or in the form of a software functional module.

[0184] When the integrated module is implemented in the form of a software function module and sold or used as an independent product, the integrated unit may be stored on a computer-readable storage medium. Based on this understanding, the technical solution of the present application, that is, the part that contributes to the prior art, or all or part of the technical solution, can be implemented in the form of a software product. The computer software product is stored on a storage medium and includes several instructions for instructing a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in the embodiments of the present application. The aforementioned storage medium includes any medium capable of storing program code, such as a USB flash drive, removable hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0185] In this application, terms such as "first" and "second" are used to distinguish between identical or similar items that have essentially the same effect and function. It should be understood that there is no logical or chronological dependency between "first," "second," and "nth (n-th)," and that the quantity and execution order are not limited. While terms such as "first" and "second" are used in the following descriptions to explain various elements, it should be further understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without deviating from the range of various examples, the first image can be called the second image, and similarly, the second image can be called the first image. Both the first and second images may be images, or in some cases, they may be separate and distinct images.

[0186] It should be further understood that the process sequence number does not imply the execution sequence in the various embodiments of the present application. The execution sequence of a process should be determined based on the function and internal logic of the process and should not be interpreted as any limitation on the implementation process of the embodiments of the present application.

[0187] In this application, the term "at least one" means one or more, and the term "multiple" means two or more. For example, "multiple second packets" means two or more second packets. The terms "system" and "network" may be used interchangeably in this specification.

[0188] It should be understood that the terms used in the descriptions of the various examples in this specification are intended to illustrate specific examples and not to constitute limitations. The singular terms “one” ("a" and “an") and “the” used in the descriptions of the various examples and in the appended claims are also intended to include plural forms unless otherwise explicitly specified in the context.

[0189] As used herein, the term “include” (also referred to as “includes,” “including,” “comprises,” and / or “comprising”) specifies the presence of the described feature, integer step, operation, element, and / or component in conjunction with or in addition to one or more other features, integers, steps, operations, elements, and / or components, and / or without excluding those components.

[0190] It should be further understood that the term "if" can be interpreted as "when" ("when" or "upon"), "in response to a decision," or "in response to detection." Similarly, depending on the context, the phrases "if it is determined that" or "if (the stated state or event) is detected" may be interpreted as "if it is determined that" or "in response to the determination that," or "when (the stated state or event) is detected" or "in response to the detection of (the stated state or event)."

[0191] Please understand that determining B based on A does not mean that B is determined solely on A; alternatively, B may be determined based on A and / or other information.

[0192] It should be further understood that any “one embodiment,” “embodiment,” or “possible embodiment” referred to throughout this specification means that a particular feature, structure, or characteristic associated with an embodiment is included in at least one embodiment of the present application. Therefore, “one embodiment,” “in an embodiment,” or “possible embodiment” appearing throughout this specification do not necessarily mean the same embodiment. Furthermore, these particular features, structures, or characteristics can be combined in one or more embodiments using any suitable method.

[0193] The foregoing description is merely an optional embodiment of the present application and is not intended to limit it. Any modifications, equivalent substitutions, or improvements made without departing from the principles of the present application should fall within the scope of protection.

Claims

1. A transmitting device comprising an encoding and rate matching module, a data block distribution module, a first module group, a second module group, and a physical media connection (PMA) layer, The encoding and rate matching module is coupled to the data block distribution module, and the data block distribution module is coupled to the first module group and the second module group. The first module group is coupled to the PMA layer, and the second module group is coupled to the PMA layer, and the PMA layer is configured to perform bit multiplexing (Bit-mux) across the first module group and the second module group. The first module group includes a first transcoding module, a first scrambling module, a first alignment marker insertion module, and a first forward error correction (FEC) coding module. The second module group includes a second transcoding module, a second scrambling module, a second alignment marker insertion module, and a second FEC coding module. Transmitter.

2. The transmitting device according to claim 1, comprising a physical coding sublayer (PCS) configured to perform interleaving on first data based on FEC symbols to obtain first symbol-interleaved data, and configured to perform interleaving on second data based on the FEC symbols to obtain second symbol-interleaved data, wherein the first data is output by the first FEC coding module and the second data is output by the second FEC coding module.

3. The PMA layer, configured to perform the bit multiplexing across the first module group and the second module group, The transmitting device according to claim 2, wherein the PMA layer includes performing the bit multiplexing of the first symbol-interleaved data and the second symbol-interleaved data across the first module group and the second module group.

4. The transmitting device according to claim 1, wherein the first FEC coding module is a first-level FEC coding module in a linked FEC coding module.

5. The transmitter according to claim 4, wherein the first level FEC coding module is configured to perform Reed-Solomon (RS) FEC.

6. The transmitting apparatus according to any one of claims 1 to 5, further comprising an adjustment sublayer (RS) module, the RS module being coupled to the encoding and rate matching module via a media-independent interface (MII).

7. The transmitting device according to claim 1, wherein the data block distribution module is configured to distribute data to the first module group and the second module group at a granularity of 66 bits.

8. The transmitting apparatus according to any one of claims 1 to 5, wherein the sum of the rates of the first module group and the rates of the second module group matches the media access control (MAC) rate of the coding and rate matching module.

9. The transmitting device according to claim 8, wherein the MAC rate is 800 Gb / s, the rate of the first module group is 400 Gb / s, and the rate of the second module group is 400 Gb / s.

10. The transmitting device according to any one of claims 1 to 5, wherein the rate of the first FEC coding module is 400 Gb / s and the rate of the second FEC coding module is 400 Gb / s.

11. The transmitting device according to any one of claims 1 to 5, wherein the first transcoding module is configured to perform transcoding from 64B / 66B to 256B / 257B.

12. A receiving device comprising a decoding and rate matching module, a data block distribution module, a first module group, a second module group, and a physical media connection (PMA) layer, The decoding and rate matching module is coupled to the data block distribution module, and the data block distribution module is coupled to the first module group and the second module group. The first module group is coupled to the PMA layer, the second module group is coupled to the PMA layer, and the PMA layer is configured to perform bit-demuxing across the first module group and the second module group. The first module group includes a first inverse transcoding module, a first descrambling module, a first alignment marker removal module, and a first forward error correction (FEC) decoding module. The second module group includes a second inverse transcoding module, a second descrambling module, a second alignment marker removal module, and a second FEC decoding module. Receiving device.

13. The receiving device according to claim 12, wherein the first FEC decoding module is a first-level FEC decoding module in a series of linked FEC decoding modules.

14. The receiving device according to claim 12, further comprising an adjustment sublayer (RS) module, the RS module being coupled to the decoding and rate matching module via a media-independent interface (MII).

15. The receiving device according to any one of claims 12 to 14, wherein the sum of the rates of the first module group and the rates of the second module group matches the media access control (MAC) rate of the decoding and rate matching module.

16. The receiving device according to claim 15, wherein the MAC rate is 800 Gb / s, the rate of the first module group is 400 Gb / s, and the rate of the second module group is 400 Gb / s.

17. The receiving device according to any one of claims 12 to 14, wherein the rate of the first FEC decoding module is 400 Gb / s and the rate of the second FEC decoding module is 400 Gb / s.

18. The receiving device according to any one of claims 12 to 14, wherein the first inverse transcoding module is configured to perform inverse transcoding from 256B / 257B to 64B / 66B, and the second inverse transcoding module is configured to perform inverse transcoding from 256B / 257B to 64B / 66B.

19. A transmission method, said method is The steps include: performing encoding and rate matching on the first data to obtain the second data; The first module group transcodes a first portion of the second data to obtain the first transcoded data, The first module group scrambles the first transcoded data to obtain the first scrambled data, The first module group includes the step of inserting first alignment marks into the first scrambled data to obtain first alignment data, The first module group encodes the first alignment data according to a forward error correction (FEC) code to obtain first processed data, The second module group transcodes a second portion of the second data to obtain second transcoded data, The second module group scrambles the second transcoded data to obtain the second scrambled data, The second module group includes the step of inserting a second alignment mark into the second scrambled data to obtain second alignment data, The second module group encodes the second alignment data according to the FEC code to obtain the second processed data, The process includes the step of performing bit multiplexing on the first processed data and the second processed data across the first module group and the second module group in the physical media connection (PMA) layer, method.

20. The first module group encodes the first alignment data according to a forward error correction (FEC) code to obtain the first processed data, The first module group encodes the first alignment data according to the FEC code to obtain the first encoded data, The first module group particularly includes the step of performing interleaving on the first encoded data in a physical coding sublayer (PCS) based on FEC symbols to obtain the first processed data, The step of the second module group encoding the second alignment data according to the FEC code to obtain the second processed data is: The second module group encodes the second alignment data according to the FEC code to obtain the second encoded data, The method according to claim 19, further comprising the step of the second module group performing interleaving on the second encoded data in the PCS based on the FEC symbols to obtain the second processed data.

21. The method according to claim 19, wherein the first FEC coding process is a first-level FEC coding process in a concatenated FEC coding process.

22. The method according to claim 21, wherein the first level of FEC coding is configured to perform Reed-Solomon (RS) FEC.

23. The method according to any one of claims 19 to 22, wherein the sum of the rates of the first module group and the rates of the second module group matches the media access control (MAC) rate of the coding and rate matching module.

24. The method according to claim 23, wherein the MAC rate is 800 Gb / s, the rate of the first module group is 400 Gb / s, and the rate of the second module group is 400 Gb / s.

25. The method according to any one of claims 19 to 22, wherein the transcoding step is configured to perform transcoding from 64B / 66B to 256B / 257B.

26. A receiving method, wherein the method is Steps include: performing bit demultiplexing on third data across a first module group and a second module group in the Physical Media Attachment (PMA) layer to obtain first processed data and second processed data, wherein the third data is data from the Physical Media Dependency (PMD) layer; The first module group decodes the first processed data according to a forward error correction (FEC) code to obtain the first decoded data, The first module group performs the steps of removing the first alignment marks from the first decoded data to obtain the first alignment-deleted data, The first module group descrambles the first alignment deletion data to obtain the first descrambled data, The first module group decodes the first descrambled data to obtain a first portion of the second data, The second module group decodes the second processed data according to the FEC code to obtain the second decoded data, The second module group includes the step of removing the second alignment marks from the second decoded data to obtain the second alignment-deleted data, The second module group descrambles the second alignment deletion data to obtain the second descrambled data, The second module group performs the steps of de-transcoding the second descrambled data to obtain a second portion of the second data, The process includes the step of performing decoding and rate matching on the first portion of the second data and the second portion of the second data to obtain the first data, method.

27. The first module group decodes the first processed data according to a forward error correction (FEC) code to obtain the first decoded data, The first module group performs deinterleaving on the first processed data in the physical coding sublayer (PCS) based on FEC symbols to obtain the first desymbolized interleaved data, The first module group particularly includes the step of decoding the first desymbolized interleaved data according to the FEC code to obtain the first decoded data, The step of the second module group decoding the second processed data according to the FEC code to obtain the second decoded data is: The second module group performs deinterleaving on the second processed data in the PCS based on the FEC symbol to obtain the second desymbolized interleaved data, The method according to claim 26, further comprising the step of the second module group decoding the second desymbolized interleaved data according to the FEC code to obtain the second decoded data.

28. The method according to claim 26, wherein the first FEC decoding process is a first-level FEC decoding process in a concatenated FEC decoding process.

29. The method according to any one of claims 26 to 28, wherein the sum of the rates of the first module group and the rates of the second module group matches the media access control (MAC) rate of the decoding and rate matching module.

30. The method according to claim 29, wherein the MAC rate is 800 Gb / s, the rate of the first module group is 400 Gb / s, and the rate of the second module group is 400 Gb / s.

31. The method according to any one of claims 26 to 28, wherein the step of reverse transcoding is configured to perform reverse transcoding from 256B / 257B to 64B / 66B.

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