1.5 Non-volatile memory with pass programming

Abstract

The present invention provides a non-volatile storage device, method, and non-volatile memory system that can increase the speed of programming. [Solution] A storage system 100, which is a solid-state drive (SSD), uses a two-pass programming process to program some word lines and a one-pass programming process to program other word lines. [Effect] It is possible to program a large number of bits per memory cell at a faster speed than conventional systems.

Description

Technical Field

[0001] This disclosure relates to non-volatile storage.

[0002] Semiconductor memories are widely used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, servers, solid state drives, non-mobile computing devices, and other devices. A semiconductor memory may include a non-volatile memory or a volatile memory. A non-volatile memory enables information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery). An example of a non-volatile memory is a flash memory (e.g., NAND-type and NOR-type flash memories).

[0003] A user of a non-volatile memory can program (e.g., write) data to the non-volatile memory and later read that data. For example, a digital camera can take a photo and store the photo in a non-volatile memory. Later, the user of the digital camera can view the photo by having the digital camera read the photo from the non-volatile memory. Since a user of a non-volatile memory does not want to wait for the non-volatile memory to complete a memory operation, it is desirable for the non-volatile memory to have high performance.

Brief Description of the Drawings

[0004] Elements with the same reference numerals refer to common components in different drawings. [Figure 1] A block diagram depicting one embodiment of a storage system. [Figure 2A] A block diagram of one embodiment of a memory die. [Figure 2B] A block diagram of one embodiment of an integrated memory assembly (also referred to as a memory die). [Figure 3A] Depicting different embodiments of an integrated memory assembly. [Figure 3B] Different embodiments of the integrated memory assembly are illustrated. [Figure 4] This is a perspective view of a portion of one embodiment of a monolithic three-dimensional memory structure. [Figure 4A] This is a block diagram of one embodiment of a memory structure having two planes. [Figure 4B] A top view of a portion of one embodiment of a memory cell block is shown. [Figure 4C] A cross-sectional view of a portion of one embodiment of a memory cell block is shown. [Figure 4D] A cross-sectional view of a portion of one embodiment of a memory cell block is shown. [Figure 4E] This is a cross-sectional view of one embodiment of a vertical array of memory cells. [Figure 4F] This is a schematic diagram of multiple NAND strings in multiple regions of the same block. [Figure 5A] The threshold voltage distribution is plotted. [Figure 5B] The threshold voltage distribution is plotted. [Figure 5C] The threshold voltage distribution is plotted. [Figure 5D] The threshold voltage distribution is plotted. [Figure 6] This is a flowchart illustrating one embodiment of the process for programming non-volatile memory. [Figure 7] This illustrates a one-pass programming process. [Figure 8A] This illustrates a two-pass programming process. [Figure 8B] This illustrates a two-pass programming process. [Figure 8C] This illustrates a two-pass programming process. [Figure 9] This diagram illustrates the control circuit connected to a block of non-volatile memory cells. [Figure 10]This flowchart illustrates one embodiment of a programming process using several word lines that employ a two-pass programming process and other word lines that employ a one-pass programming process. [Figure 11] This document describes one exemplary implementation of a process for programming using several word lines that employ a two-pass programming process and other word lines that employ a one-pass programming process. [Figure 12] This explains cross-referencing of adjacent word lines. [Figure 13] This explains cross-referencing of adjacent word lines. [Modes for carrying out the invention]

[0005] Users of non-volatile memory desire large memory capacity for storing large amounts of data. One way to increase the capacity of non-volatile memory is to increase the number of bits stored by each memory cell. However, increasing the number of bits stored by each memory cell leads to a slower programming process. To increase the speed of the programming process for volatile memory where the number of bits stored by each memory cell is increasing, it is proposed to use a two-pass programming process for some word lines and a one-pass programming process for other word lines.

[0006] Figure 1 is a block diagram of one embodiment of a storage system 100 implementing the proposed technology described herein. In one embodiment, the storage system 100 is a solid-state drive ("solid-state drive, SSD"). The storage system 100 may also be a memory card, a USB drive, or another type of storage system. The proposed technology is not limited to any one type of memory system. The storage system 100 is connected to a host 102, which may be a computer, a server, an electronic device (e.g., a smartphone, tablet, or other mobile device), an electrical appliance, or another device that uses memory and has data processing capabilities. In some embodiments, the host 102 is separate from the storage system 100 but connected to it. In other embodiments, the memory system 100 is integrated into the host 102.

[0007] The components of the memory system 100 depicted in Figure 1 are electrical circuits. The storage system 100 includes a memory controller 120 connected to non-volatile memory 130 and local high-speed volatile memory 140 (e.g., DRAM). The local high-speed volatile memory 140 is used by the memory controller 120 to perform specific functions. For example, the local high-speed volatile memory 140 stores a logical address-to-physical address translation table ("L2P table").

[0008] The memory controller 120 is connected to and communicates with the host 102 and includes a host interface 152. In one embodiment, the host interface 152 implements NVM Express (NVMe) over PCI Express (PCIe). Other interfaces such as SCSI and SATA can also be used. The host interface 152 is also connected to a network-on-chip (NOC) 154. The NOC is a communication subsystem on an integrated circuit. The NOC can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NOC technology applies networking theory and methods to on-chip communication, resulting in a significant improvement over conventional bus and crossbar interconnects. Compared to other designs, NOCs improve the scalability of systems on a chip (SoC) and the power efficiency of complex SoCs. The wiring and links of the NOC are shared by many signals. A high level of parallelism is achieved because all links within the NOC can operate simultaneously for different data packets. Therefore, as the complexity of the integrated subsystem continues to increase, the NOC provides improved performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signaling wiring, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 can be replaced by a bus. The NOC 154 is connected to and communicates with a processor 156, an ECC engine 158, a memory interface 160, and a DRAM controller 164. The DRAM controller 164 is used to operate and communicate with a local high-speed volatile memory 140 (e.g., DRAM). In other embodiments, the local high-speed volatile memory 140 may be SRAM or another type of volatile memory.

[0009] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding according to the implemented ECC technology. In one embodiment, the ECC engine 158 is a software-programmed electrical circuit. For example, the ECC engine 158 can be a programmable processor. In another embodiment, the ECC engine 158 is a custom, dedicated hardware circuit without any software. In yet another embodiment, the functions of the ECC engine 158 are performed by a processor 156.

[0010] Processor 156 performs various controller memory operations such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a custom dedicated hardware circuit without software. Processor 156 also implements the conversion module as a software / firmware process or as a dedicated hardware circuit. In many systems, non-volatile memory is internally addressed to the storage system using physical addresses associated with one or more memory dies. However, the host system addresses various memory locations using logical addresses. This allows the host to assign data to contiguous logical addresses, while the storage system can freely store the data whenever the storage system desires among the locations of one or more memory dies. To implement this system, memory controller 120 (e.g., the conversion module) performs an address conversion between the logical addresses used by the host and the physical addresses used by the memory die. One exemplary implementation is to maintain a table (i.e., the L2P table mentioned above) that identifies the current conversion between logical and physical addresses. Entries in the L2P table may include the identification of the logical address and the corresponding physical address. Tables from logical addresses to physical addresses (or L2P tables) include the word "table", but they do not have to be literal tables. Rather, tables from logical addresses to physical addresses (or L2P tables) can be any type of data structure. In some examples, the memory space of the storage system is so large that local memory 140 cannot hold all of the L2P table. In such cases, the entire set of L2P tables is stored in memory die 130, and a subset of the L2P tables is cached in local volatile memory 140 (L2P cache).

[0011] The memory interface 160 communicates with the non-volatile memory 130. In one embodiment, the memory interface provides a toggle-mode interface. Other interfaces may also be used. In some exemplary implementations, the memory interface 160 (or another part of the controller 120) implements a scheduler and buffers for sending data to and receiving data from one or more memory dices.

[0012] In one embodiment, the non-volatile memory 130 includes one or more memory dies. FIG. 2A is a functional block diagram of one embodiment of a memory die 200 that includes the non-volatile memory 130. Each of the one or more memory dies of the non-volatile memory 130 can be implemented as the memory die 200 of FIG. 2A. The components depicted in FIG. 2A are electrical circuits. The memory die 200 includes a memory array 202 that can include non-volatile memory cells, as will be described in more detail below. The array terminal lines of the memory array 202 include various layers of word lines organized as rows and various layers of bit lines organized as columns. However, other orientations can also be implemented. The memory die 200 includes a row control circuit 220, the output 208 of which is connected to each word line of the memory array 202. The row control circuit 220 receives a group of M row address signals and one or more various control signals from the system control logic circuit 260, and typically includes circuits such as a row decoder 222, an array terminal driver 224, and a block selection circuit 226 for both read and write (programming) operations. The row control circuit 220 can also include a read / write circuit. The memory die 200 also includes a column control circuit 210 that includes a sense amplifier 230 with an input / output 206 connected to each bit line of the memory array 202. Although only a single block of the memory array 202 is shown, the memory die can include multiple arrays that can be individually accessed. The column control circuit 210 receives a group of N column address signals and one or more various control signals from the system control 260, and typically includes circuits such as a column decoder 212, an array terminal receiver or driver circuit 214, a block selection circuit 216, and a read / write circuit, and an I / O multiplexer.

[0013] The system control logic 260 receives data and commands from the memory controller 120 and provides output data and status to the host. In some embodiments, the system control logic 260 (comprising one or more electrical circuits) includes a state machine 262 that provides die-level control of memory operation. In one embodiment, the state machine 262 is programmable by software. In other embodiments, the state machine 262 is implemented entirely in hardware (e.g., electrical circuits) without the use of software. In yet another embodiment, the state machine 262 is replaced by a microcontroller or microprocessor located either on or off the memory chip. The system control logic 262 may also include a power control module 264 that controls the power and voltage supplied to the rows and columns of the memory structure 202 during memory operation, and may include charge pump and regulator circuits for generating regulated voltages. The system control logic 262 includes storage 366 (e.g., RAM, registers, latches, etc.) which may be used to store parameters for operating the memory array 202.

[0014] Commands and data are transferred between the memory controller 120 and the memory die 200 via the memory controller interface 268 (also referred to as the "communication interface"). The memory controller interface 268 is an electrical interface for communicating with the memory controller 120 and includes one or more input / output ("Input / Output, I / O") circuits. Examples of the memory controller interface 268 include a toggle-mode interface and an Open NAND Flash Interface (ONFI). Other I / O interfaces may also be used.

[0015] In some embodiments, all elements of the memory die 200, including the system control logic 260, may be formed as part of a single die. In other embodiments, some or all of the system control logic 260 may be formed on different dies.

[0016] In one embodiment, the memory structure 202 comprises a three-dimensional memory array of non-volatile memory cells, where multiple memory levels are formed on a single substrate such as a wafer. The memory structure may comprise any type of non-volatile memory monolithically formed on one or more physical levels of memory cells having active regions disposed on a silicon (or other type) substrate. In one example, the non-volatile memory cells comprise a vertical NAND string with a charge trap layer.

[0017] In another embodiment, the memory structure 302 comprises a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR flash memory) can also be used.

[0018] The exact type of memory array architecture or memory cell included in the memory structure 202 is not limited to the examples given above. Many different types of memory array architectures or memory technologies can be used to form the memory structure 202. No specific non-volatile memory technology is required for the purposes of the newly claimed embodiments proposed herein. Other examples of suitable technologies for the memory cells of the memory structure 202 include ReRAM memory (resistive random-access memory), magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, and phase-change memory (e.g., phase change memory, PCM). Examples of suitable technologies for the memory cell architecture of the memory structure 202 include two-dimensional arrays, three-dimensional arrays, crosspoint arrays, stacked two-dimensional arrays, and vertical bit-line arrays.

[0019] An example of a ReRAM crosspoint memory includes a reversible resistive switching element arranged in a crosspoint array accessed by X-rays and Y-rays (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may be referred to as a programmable metallization cell. The conductive bridge memory element can be used as a state change element based on the physical rearrangement of ions in a solid electrolyte. In some cases, the conductive bridge memory element may include two solid metal electrodes, one of which is relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As the temperature increases, the mobility of ions also increases, reducing the programming threshold of the conductive bridge memory cell. Thus, the conductive bridge memory element may have a wide programming threshold with respect to temperature.

[0020] Another example is magnetoresistive random access memory (MRAM), which stores data using magnetic memory elements. The elements are formed from two ferromagnetic layers, each capable of holding a magnetization separated by a thin insulating layer. One of the two layers is a permanent magnet set to a specific polarity, and the magnetization of the other layer can be changed to match the magnetization of an external magnetic field for memory storage. The memory device is constructed from a grid of such memory cells. In one embodiment for programming, each memory cell is positioned perpendicular to each other, parallel to the cell, with one above the cell and one below the cell, between a pair of write lines. An induced magnetic field is generated when current passes through them. Embodiments of MRAM-based memory are discussed in more detail below.

[0021] Phase-change memory (PCM) utilizes the inherent behavior of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve a non-thermal phase change by simply changing the coordination state of germanium atoms using a laser pulse (or a light pulse from another source). Thus, the programming dose is a laser pulse. The memory cell can be blocked by blocking the memory cell from receiving light. In other embodiments of PCM, the memory cell is programmed by a current pulse. Note that the use of “pulse” herein does not require a square pulse, but includes (continuous or discontinuous) oscillations of sound, current, voltage, light, or another wave. Individual selectable memory cells or these memory elements within a bit may include further series elements, such as an obonic threshold switch or a selector such as a metal-insulating substrate.

[0022] Those skilled in the art will recognize that the techniques described herein are not limited to a single specific memory structure, memory configuration, or material composition, but rather cover many related memory structures within the spirit and scope of the techniques described herein and understood by those skilled in the art.

[0023] The elements in Figure 2A can be grouped into two parts: (1) the memory structure 202 and (2) the peripheral circuitry, which includes all other components depicted in Figure 2A. A key characteristic of the memory circuitry is its capacity, which can be increased by increasing the area of ​​the memory die of the storage system 100 allocated to the memory structure 202; however, this reduces the area of ​​the memory die available for the peripheral circuitry. This can impose very strict limitations on the elements of these peripheral circuits. For example, the need to fit a sensitivity amplifier circuit within the available area can be a significant constraint on the sensitivity amplifier design architecture. With respect to the system control logic 260, the reduction in area availability can limit the available functions that can be implemented on-chip. Therefore, the fundamental trade-off in the design of the memory die for the storage system 100 is the amount of area allocated to the memory structure 202 and the amount of area allocated to the peripheral circuitry.

[0024] Another area where the memory structure 202 and peripheral circuits often conflict lies in the processing involved in forming these areas, as these areas often involve different processing techniques and trade-offs in having different techniques on a single die. For example, if the memory structure 202 is NAND flash, it is an NMOS structure, while the peripheral circuits are often CMOS-based. For example, elements such as sensitivity amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in system control logic 260 often use PMOS devices. The processing operations for manufacturing CMOS dies differ in many ways from the processing operations optimized for NMOS flash NAND memory or other memory cell technologies.

[0025] To improve upon these limitations, the embodiments described below allow the elements of Figure 2A to be separated onto separately formed dies, which are then joined together. More specifically, the memory structure 202 can be formed on one die (referred to as the memory array die), and some or all of the peripheral circuit elements, including one or more control circuits, can be formed on a separate die (referred to as the control die). For example, the memory array die can be formed solely from memory elements such as flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or an array of memory cells of other memory types. Some or all of the peripheral circuits can further include elements such as decoders and sensitivity amplifiers, which can then be moved to a separate control die. This allows each memory array die to be individually optimized according to its technology. For example, a NAND memory array die can be optimized for CMOS processing, without having to worry about the CMOS elements now moved onto the control die. This allows for more space for peripheral elements and can incorporate additional capabilities that could not be easily incorporated when limited to the margins of the same die holding the memory cell array. Subsequently, the two dies can be joined together in a joined multi-die integrated memory circuit, with the array on one die connected to the peripheral elements on the other die. The following focuses on a joined memory circuit with one memory array die and one control die, but other embodiments may use more dies, such as two memory array dies and one control die.

[0026] Figure 2B shows an alternative arrangement to the arrangement in Figure 2A, which may be implemented using wafer-to-wafer bonding to provide bonded die pairs. Figure 2B depicts a functional block diagram of one embodiment of an integrated memory assembly 207, which is another example of a memory die. One or more integrated memory assemblies (one or more memory dies) 207 may be used to implement non-volatile memory 130 of a storage system 100. The integrated memory assembly (or memory die) 207 includes two types of semiconductor dies (or more simply, “dies”). The memory array die 201 includes a memory structure 202. The memory structure 202 includes non-volatile memory cells. The control die 211 includes control circuits 260, 210, and 220 (as described above). In some embodiments, the control die 211 is configured to connect to the memory structure 202 within the memory array die 201. In some embodiments, the memory array die 201 and the control die 211 are bonded together.

[0027] Figure 2B shows an example of peripheral circuits, including peripheral circuits coupled to a memory structure 202 formed within a memory array die 201, or control circuits formed within a control die 211. Common components are labeled as in Figure 2A. The system control logic 260, row control circuit 220, and column control circuit 210 are located within the control die 211. In some embodiments, part or all of the column control circuit 210 and all or part of the row control circuit 220 are located on the memory array die 201. In some embodiments, some of the circuits within the system control logic 260 are located on the memory array die 201.

[0028] The system control logic 260, row control circuit 220, and column control circuit 210 may be formed by a common process (e.g., a CMOS process), and as a result, additional elements and functions, such as ECCs more typically found on the memory controller 120, may require little or no additional process steps (i.e., the same process steps used to manufacture the controller 120 may be used to manufacture the system control logic 260, row control circuit 220, and column control circuit 210). Therefore, moving such circuits from a die such as the memory 2 die 201 may reduce the number of steps required to manufacture such a die, while adding such circuits to a die such as the control die 211 may require no additional process steps at all. The control die 211 may also be referred to as a CMOS die due to the use of CMOS technology to implement some or all of the control circuits 260, 210, and 220.

[0029] Figure 2B shows a column control circuit 210, which includes a sensitivity amplifier 230 on a control die 211 coupled to a memory structure 202 on a memory array die 201 via an electrical path 206. For example, the electrical path 206 may provide electrical connections between a column decoder 212, a driver circuit 214, a block selector 216, and the bit lines of the memory structure 202. The electrical path may extend from the column control circuit 210 in the control die 211 through pads on the control die 211 that are bonded to corresponding pads on the memory array die 201 connected to the bit lines of the memory structure 202. Each bit line of the memory structure 202 may have a corresponding electrical path in the electrical path 206, which includes a pair of bonded pads connected to the column control circuit 210. Similarly, a row control circuit 220, which includes a row decoder 222, an array driver 224, and a block selector 226, is coupled to the memory structure 202 via an electrical path 208. Each of the electrical paths 208 may correspond to a word line, a dummy word line, or a select gate line. An additional electrical path may be provided between the control die 211 and the memory array die 201.

[0030] For the purposes of this specification, the phrase “control circuit” or “one or more control circuits” may include any one or any combination of the memory controller 120, the state machine 262, all or part of the system control logic 260, all or part of the row control circuit 220, all or part of the column control circuit 210, a microcontroller, a microprocessor, and / or other similar functional circuits. A control circuit may include hardware only, or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. A control circuit may include a processor, FGA, ASIC, integrated circuit, or other type of circuit.

[0031] Some embodiments include a stack of multiple memory dies (e.g., multiple control dies 211 and multiple memory array dies 201). Figure 3A shows a side view of an embodiment of a stack of multiple memory dies on a substrate 271 (e.g., a stack including control dies 211 and memory array dies 201). The depicted stack has three control dies 211 and three memory array dies 201. In some embodiments, there are more than three memory array dies 201 and more than three control dies 211.

[0032] Each control die 211 is attached to (e.g., bonded to) at least one of the memory array dies 201. Some of the bonding pads 282 / 284 are depicted. More bonding pads may be present. The space between the two dies 201, 211 that are bonded together is filled with a solid layer 280 which may be formed from epoxy or other resin or polymer. This solid layer 280 protects the electrical connection between the dies 201, 211 and further fixes the dies together. Various materials can be used as the solid layer 280, but in this embodiment it may be Hysol epoxy resin from Henkel, Inc., which has offices in California, USA.

[0033] The memory dies 207 may be stacked, for example, with a stepped offset, such that the bonding pads at each level are not covered and are accessible from above. Wire joints 270 connected to the bonding pads connect the control dies 211 to the substrate 271. Several such wire joints may be formed across the width of each control die 211 (i.e., into the pages of Figure 3A).

[0034] A through-silicon via (TSV) 276 can be used to route signals through the memory array die 201. A through-silicon via (TSV) 278 can be used to route signals through the control die 211. The TSVs 276 and 278 can be formed before, during, or after the formation of the integrated circuit within the semiconductor dies 201 and 211. The TSVs can be formed by etching holes that penetrate the wafer. The holes can then be backed with a barrier against metal diffusion. This barrier layer can then be backed with a seed layer, which can be plated with a conductor such as copper, but other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof may be used.

[0035] The solder balls 272 may optionally be attached to the contact pads 274 on the underside of the substrate 271. The solder balls 272 may be used to electrically and mechanically couple the integrated memory assembly (memory die) 207 to a host device such as a printed circuit board. If the integrated memory assembly (memory die) 207 can be used as an LGA package, the solder balls 272 may be omitted. The solder balls 272 may form part of the interface between the integrated memory assembly (memory die) 207 and the memory controller 120.

[0036] Figure 3B shows a side view of another embodiment of memory dies stacked on a substrate 271. The depicted stack includes three control dies 211 and three memory array dies 201. In some embodiments, there are more than three memory array dies 201 and more than three control dies 211. In this example, each control die 211 is bonded to at least one memory array die 201. Optionally, a control die 211 may be bonded to two or more memory array dies 201.

[0037] Some of the bonding pads 282 and 284 are depicted. More bonding pads may be present. The space between the two dies 201 and 211 that are bonded together is filled with a solid layer 280 which may be formed from epoxy or other resin or polymer. In contrast to the example in Figure 3A, the stack in Figure 3B does not have a stepped offset. A through-die silicon via (TSV) 276 may be used to route signals through the memory array die 201. A through-die silicon via (TSV) 278 may be used to route signals through the control die 211.

[0038] As briefly discussed above, the control die 211 and the memory array die 201 can be joined together. Bonding pads on each die 201, 211 can be used to join the two dies together. In some embodiments, the bonding pads are joined directly to each other without solder or other additional materials in a so-called Cu-to-Cu bonding process. In the Cu-to-Cu bonding process, the bonding pads are controlled to be highly flat and formed in a highly controlled environment with little ambient particulate matter that could otherwise settle on the bonding pads and hinder close bonding. Under such well-controlled conditions, the bonding pads are aligned and pressed against each other to form a bond based on surface tension. Such a bond can be formed at room temperature, but heat can also be applied. In embodiments using Cu-Cu bonding, the bonding pads may be about 5 μm square and spaced apart from each other at a pitch of 5 μm to 5 μm. This process is referred to herein as Cu-Cu bonding, but this term may also apply when the bonding pads are formed of a material other than Cu.

[0039] When the area of ​​the bonding pads is small, it can be difficult to bond semiconductor dies together. The size of the bonding pads and the pitch between them can be further reduced by providing a thin film layer on the surface of the semiconductor die containing the bonding pads. This thin film layer is provided around the bonding pads. When the dies are joined together, the bonding pads can bond to each other, and the thin film layers on each die can bond to each other. Such a bonding technique may be called hybrid bonding. In embodiments using hybrid bonding, the bonding pads are approximately 5 μm square and can be spaced apart from each other with a pitch of 1 μm to 5 μm. Bonding techniques can be used to provide bonding pads with even smaller (or larger) sizes and pitches.

[0040] In some embodiments, a thin film may be included on the surfaces of dies 201, 211. If such a thin film is not initially provided, the space between the dies may be underfilled with epoxy or other resins or polymers. The underfill material may be applied as a liquid, and the liquid may then be cured into a solid layer. This underfill step protects the electrical connections between dies 201, 211 and further fixes the dies together. Various materials can be used as the underfill material, but in embodiments, it may be Hysol epoxy resin from Henkel, Inc., which has offices in California, USA.

[0041] In a stack of control die 211 and memory array die 201 (for example, as depicted in Figure 3A or Figure 3B), TSVs from various dies in the stack can be shorted together to form a single bus, or they can operate in parallel with each other so that each die can operate and communicate independently.

[0042] Figure 4 is a perspective view of a portion of one exemplary embodiment of a monolithic three-dimensional memory array / structure, which may comprise a memory structure 202 including multiple non-volatile memory cells arranged as a vertical NAND string. For example, Figure 4 shows a portion of one block 400 of the memory. The depicted structure includes a set of bit lines BL positioned above a stack of alternating dielectric and conductive layers 401. For illustrative purposes, one of the dielectric layers is marked as D, and one of the conductive layers (also called word line layers) is marked as W. The number of alternating dielectric and conductive layers may vary based on specific implementation requirements. As described below, in one embodiment, the alternating dielectric and conductive layers are divided into four or five (or a different number) regions by isolation regions IR. Figure 4 shows one isolation region IR separating two regions. Below the alternating dielectric and word line layers are source line layers SL. Memory holes are formed within the stack of alternating dielectric and conductive layers. For example, one of the memory holes is marked as MH. Note that in Figure 4, the dielectric layer is depicted as translucent so that the reader can see the memory holes positioned within the stack of alternating dielectric and conductive layers. In one embodiment, a NAND string is formed by filling the memory holes with a material containing charge trapping material to create a vertical column of memory cells. Each memory cell can store one or more bits of data. Thus, non-volatile memory cells are positioned within the memory holes. Further details of the three-dimensional monolithic memory array including the memory structure 202 are provided below.

[0043] Figure 4A is a block diagram illustrating one exemplary organization of a memory structure 202 divided into four planes 402, 403, 404, and 405. Each plane is then divided into M blocks. In one example, each plane has approximately 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, a block of memory cells is a unit of erasure; that is, all memory cells in a block are erased together. In other embodiments, a block is divided into subblocks, and those subblocks can be units of erasure. Memory cells can also be grouped into blocks for other reasons, such as to organize the memory structure to enable signaling and selection circuits. In some embodiments, a block represents a group of connected memory cells, such that the memory cells in the block share a common set of word lines. For example, all word lines in a block are connected to all of the vertical NAND strings in that block. Figure 4A shows four planes, but more or fewer planes can be implemented. In some embodiments, the memory structure 202 includes eight planes.

[0044] Figures 4B to 4G illustrate exemplary three-dimensional ("3D") NAND structures that correspond to the structure in Figure 4 and can be used to implement the memory structure 202 in Figures 2A and 2B. Figure 4B is a block diagram showing a top view of a portion 406 of block 2 in plan 402. As can be seen from Figure 4B, the block depicted in Figure 4B extends in the direction 432. In one embodiment, the memory array has many layers, but Figure 4B shows only the top layer.

[0045] Figure 4B depicts multiple circles representing memory holes, also known as vertical columns. Each memory hole / vertical column contains multiple selection transistors (also known as selection gates) and multiple memory cells. In one embodiment, each memory hole / vertical column implements a NAND string. For example, Figure 4B labels a subset of memory holes / vertical columns / NAND strings 432, 436, 446, 456, 462, 466, 472, 474, and 476.

[0046] Figure 4B also depicts a set of bit lines 415, including bit lines 411, 412, 413, 414, ... 419. Because only a portion of the block is depicted, Figure 4B shows 24 bit lines. It is intended that more than 24 bit lines connect to the block's memory holes / vertical columns. Each circle representing a memory hole / vertical column has an "x" to indicate its connection to a single bit line. For example, bit line 411 connects to memory holes / vertical columns 436, 446, 456, 466, and 476.

[0047] The block depicted in Figure 4B includes a set of isolation regions 482, 484, 486, and 488 formed of SiO2, although other dielectric materials may also be used. The isolation regions 482, 484, 486, and 488 serve to divide the top layer of the block into five regions. For example, the top layer depicted in Figure 4B is divided into regions 430, 440, 450, 460, and 470. In one embodiment, the isolation regions merely divide the layer used to implement the selection gate so that NAND strings in different regions can be selected independently. In one exemplary implementation, the bit line connects to one memory hole / vertical column / NAND string in each of regions 430, 440, 450, 460, and 470. In that implementation, each block has 24 rows of active columns, and each bit line connects to 5 rows within each block. In one embodiment, all five memory holes / vertical columns / NAND strings connected to a common bit line are connected to the same set of word lines. Thus, the system uses a drain-side selection line to select one (or another subset) of the five memory to undergo a memory operation (programming, verification, reading, and / or erasing).

[0048] Figure 4B also shows the line interconnection LI, which is a metal connection from above the memory array to the source line SL. This line interconnection LI is located adjacent to regions 430 and 470.

[0049] Figure 4B shows regions 430, 440, 450, 460, and 470, each having 4 rows of memory holes / vertical columns, 5 regions, and 24 rows of memory holes / vertical columns within a block; however, these exact numbers are illustrative implementations. Other embodiments may include more or fewer regions per block, more or fewer rows of memory holes / vertical columns per region, and more or fewer rows of vertical columns per block. Figure 4B also shows alternating arrangements of memory holes / vertical columns. Other embodiments may use different patterns of alternating arrangements. In some embodiments, the memory holes / vertical columns are not arranged alternately.

[0050] Figure 4C depicts a portion of one embodiment of a three-dimensional memory structure 202, showing a cross-sectional view along line AA in Figure 4B. This cross-sectional view cuts through memory holes / vertical rows (NAND strings) 472 and 474 in region 470 (see Figure 4B). The structure in Figure 4C includes two drain-side selective layers SGD0 and SGD, two source-side selective layers SGS0 and SGS1, two drain-side GIDL-generating transistor layers SGDT0 and SGDT1, two source-side GIDL-generating transistor layers SGSB0 and SGSB1, two drain-side dummy word line layers DD0 and DD1, two source-side dummy word line layers DS0 and DS1, dummy word line layers DU and DL, 162 word line layers WL0 to WL161 for connecting to data memory cells, and a dielectric layer DL. Other embodiments may implement more or fewer numbers than those described above for Figure 4C. In one embodiment, SGD0 and SGD1 are connected together, and SGS0 and SGS1 are connected together. In other embodiments, a greater or lesser number of SGDs (more or less than 2) are connected together, and a greater or lesser number of SGSs (more or less than 2) are connected together.

[0051] In one embodiment, erasing a memory cell is performed using gate-induced drain leakage (GIDL), which involves generating charge carriers in a GIDL generating transistor, which are then injected into the charge trap layer of the NAND string to alter the threshold voltage of the memory cell. Figure 4C shows two GIDL generating transistors at each end of the NAND string, although other embodiments may have more or fewer than three. Embodiments using GIDL on both sides of the NAND string may have GIDL generating transistors on both sides. Embodiments using GIDL only on the drain side of the NAND string may have GIDL generating transistors only on the drain side. Embodiments using GIDL only on the source side of the NAND string may have GIDL generating transistors only on the source side.

[0052] Figure 4C shows two GIDL generating transistors at each end of a NAND string. Charge carriers are most likely to be generated by GIDL only in one of the two GIDL generating transistors at each end of the NAND string. Based on process variations during manufacturing, one of the two GIDL generating transistors at the end of the NAND string is most likely to be best suited for GIDL. For example, a GIDL generating transistor has a steep pn junction for generating charge carriers for GIDL, and phosphorus diffusion occurs in the polysilicon channel of the GIDL generating transistor during fabrication. In some cases, the GIDL generating transistor with the shallowest phosphorus diffusion is the one that generates charge carriers during erasure. However, in some embodiments, charge carriers may be generated by GIDL in multiple GIDL generating transistors on a particular side of the NAND string.

[0053] Memory holes / vertical rows 472 and 474 are depicted protruding through the drain-side selection layer, source-side selection layer, dummy word line layer, GIDL generation transistor layer, and word line layer. In one embodiment, each memory hole / vertical row contains a vertical NAND string. Beneath the memory holes / vertical rows and the layers listed below are the substrate 453, the insulating film 454 on the substrate, and the source line SL. The NAND string of memory hole / vertical row 472 has its source end at the bottom of the stack and its drain end at the top of the stack. To coincide with Figure 4B, Figure 4C shows the vertical memory hole / row 472 connected to the bit line 414 via a connector 417.

[0054] For ease of reference, the drain-side selective layer, source-side selective layer, dummy word line layer, GIDL-generating transistor layer, and data word line layer are collectively referred to as conductive layers. In one embodiment, the conductive layers are made from a combination of TiN and tungsten. In other embodiments, the conductive layers can be formed using other materials such as doped polysilicon, metals such as tungsten, metal silicides such as nickel silicide, tungsten silicide, aluminum silicide, or combinations thereof. In some embodiments, different conductive layers may be made from different materials. Between the conductive layers is a dielectric layer DL. In one embodiment, the dielectric layer is made from SiO2. In other embodiments, other dielectric materials can be used to form the dielectric layer.

[0055] Non-volatile memory cells are formed along memory holes / vertical columns extending through alternating conductive and dielectric layers within a stack. In one embodiment, memory cells are located within a NAND string. Word line layers WL0 to WL161 connect to memory cells (also called data memory cells). Dummy word line layers connect to dummy memory cells. Dummy memory cells do not store, and are not qualified to store, host data (data provided by the host, such as data from the host's user), whereas data memory cells are qualified to store host data. In some embodiments, data memory cells and dummy memory cells may have the same structure. Drain-side selective layers SGD0 and SGD1 are used to electrically connect and disconnect the NAND string to the bit lines. Source-side selective layers SGS0 and SGS1 are used to electrically connect and disconnect the NAND string to the source line SL.

[0056] Figure 4C shows that the memory array is implemented as a two-layer architecture, with the layers separated by a seam region. In one embodiment, etching a large number of word line layers mixed with the dielectric layer is expensive and / or difficult. To alleviate this burden, one embodiment includes laying a first stack of word line layers (e.g., WL0-WL80) alternately with the dielectric layer, laying a seam region, and laying a second stack of word line layers (e.g., WL81-WL161) alternately with the dielectric layer. The seam region is located between the first and second stacks. In one embodiment, the seam region is made from the same material as the word line layer. In other embodiments, there may be no seam region, or there may be multiple seam regions.

[0057] Figure 4D depicts a portion of an embodiment of a three-dimensional memory structure 202, showing a cross-sectional view along line BB in Figure 4B. This cross-sectional view cuts through memory holes / vertical rows (NAND strings) 432 and 434 in region 430 (see Figure 4B). Figure 4D shows the same alternating conductive and dielectric layers as in Figure 4C. Figure 4D also shows a delimited region 482. The delimited regions (e.g., 482, 484, 486, and 488) occupy the space that was used for portions of the memory holes / vertical rows / NAND strings. For example, delimited region 482 occupies the space that was used for portions of the memory holes / vertical row 434. More specifically, portions of the vertical row 434 (e.g., half of its diameter) are removed in layers SGDT0, SGDT1, SGD0, and SGD1 to accommodate the delimited region 482. Therefore, most of the vertical column 434 is cylindrical (having a circular cross-section), but portions of the vertical column 434 within layers SGDT0, SGDT1, SGD0, and SGD1 have a semicircular cross-section. In one embodiment, after a stack of alternating conductive and dielectric layers is formed, the stack is etched to create spaces for separation regions, which are then filled with SiO2. This structure allows for separate control of SGDT0, SGDT1, SGD0, and SGD1 for regions 430, 440, 450, 460, and 470.

[0058] Figure 4E depicts a cross-sectional view of region 429 of Figure 4C, which includes a portion of the memory holes / vertical rows 472. In one embodiment, the memory holes / vertical rows are circular, but in other embodiments, other shapes can be used. In one embodiment, the memory holes / vertical rows 472 include an inner core layer 490 made of a dielectric such as SiO2. Other materials can also be used. Surrounding the inner core 490 is a polysilicon channel 491. Materials other than polysilicon can also be used. Note that the channel 491 is connected to the bit lines and source lines. Surrounding the channel 491 is a tunnel dielectric 492. In one embodiment, the tunnel dielectric 492 has an ONO engine. Surrounding the tunnel dielectric 492 is a charge trap layer 493, such as silicon nitride (for example). Other memory materials and structures can also be used. The techniques described herein are not limited to any particular number of materials or structures.

[0059] Figure 4E depicts the dielectric layer DL, as well as the word line layers WL160, WL159, WL158, WL157, and WL156. Each word line layer includes a word line region 496 surrounded by an aluminum oxide layer 497, the aluminum oxide layer being surrounded by a blocking oxide layer 498. In other embodiments, this blocking oxide layer may be a parallel and adjacent vertical layer to the charge trap layer 493. The physical interaction between the word line layers and the vertical columns forms a memory cell. Thus, in one embodiment, the memory cell comprises a channel 491, a tunnel dielectric 492, a charge trap layer 493, a blocking oxide layer 498, an aluminum oxide layer 497, and a word line region 496. For example, the word line layer WL160 and a portion of the memory hole / vertical column 472 include a memory cell MC1. The word line layer WL159 and a portion of the memory hole / vertical column 472 include a memory cell MC2. The word line layer WL158 and a portion of the memory hole / vertical column 472 contain memory cell MC3. The word line layer WL157 and a portion of the memory hole / vertical column 472 contain memory cell MC4. The word line layer WL156 and a portion of the memory hole / vertical column 472 contain memory cell MC5. In other architectures, memory cells may have a different structure, but they are still storage units.

[0060] When a memory cell is programmed, electrons are accumulated in a portion of the charge trap layer 493 associated with the memory cell. These electrons are drawn from the channel 491 into the charge trap layer 493 via the tunnel dielectric 492 in response to a suitable voltage on the word line region 496. The threshold voltage (Vth) of the memory cell increases proportionally to the amount of charge accumulated. In one embodiment, programming is achieved by Fowler-Nordheim tunneling of electrons into the charge trap layer. During the erase operation, electrons either return to the channel or are recombined with electrons by the injection of holes into the charge trap layer. In one embodiment, erasure is achieved using hole injection into the charge trap layer via a physical mechanism such as GIDL.

[0061] Figure 4F is a schematic diagram of a portion of the three-dimensional memory array 202 depicted in Figures 4 to 4E. Figure 4F shows the physical data word lines WL0 to WL161 running across the entire block. The structure of Figure 4F corresponds to a portion 406 of block 2 in Figure 4A, which includes bit line 411. Within the block, in one embodiment, each bit line is connected to five NAND strings, one each for regions 430, 440, 450, 460, and 470. Thus, Figure 4F shows bit line 411 connected to NAND string NS0 (corresponding to memory hole / vertical column 436 in region 430), NAND string NS1 (corresponding to memory hole / vertical column 446 in region 440), NAND string NS2 (corresponding to vertical column 456 in region 450), NAND string NS3 (corresponding to memory hole / vertical column 466 in region 460), and NAND string NS4 (corresponding to memory hole / vertical column 476 in region 470).

[0062] The drain-side select line / layer SGD0 is separately connected to regions 430, 440, 450, 460, and 470, and is separated by isolation regions 482, 484, 486, and 488 to control them independently, forming SGD0-s0, SGD0-s1, SGD0-s2, SGD0-s3, and SGD0-s4. Similarly, the drain-side select line / layer SGD1 is separately connected to regions 430, 440, 450, 460, and 470, and is separated by isolation regions 482, 484, 486, and 488 to control them independently, forming SGD1-s0, SGD1-s1, SGD1-s2, SGD1-s3, and SGD1-s4, and the drain-side GIDL generating transistor control line / layer SGDT0 is separately connected to regions 430, 440, 450, 460, and 470, and is separated by isolation regions 482, 484, 486, and 488 to control them independently. Separated by regions 4, 486, and 488, the drain-side GIDL generating transistor control lines / layers SGDT1 are separately connected to regions 430, 440, 450, 460, and 470, and are separated by isolation regions 482, 484, 486, and 488 to independently control them, forming SGDT1-s0, SGDT1-s1, SGDT1-s2, SGDT1-s3, and SGDT1-s4.

[0063] Figure 4F shows only the NAND string connected to bit line 411. However, the full schematic diagram of the block shows each bit line and the five vertical NAND strings connected to each bit line (in separate regions).

[0064] The exemplary memories in Figures 4 to 4F are three-dimensional memory structures that include vertical NAND strings with charge-trapping material, but other (2D and 3D) memory structures can also be used using the techniques described herein.

[0065] The memory system discussed above is erasable, programmed, and readable. At the end of the programming process, the threshold voltage of a memory cell should, as necessary, fall within one or more distributions of threshold voltages for programmed memory cells, or within the distribution of threshold voltages for erased memory cells. Figure 5A is a graph of threshold voltage versus number of memory cells illustrating an example of threshold voltage distribution for a memory array when each memory cell stores 1 bit of data per memory cell. A memory cell that stores 1 bit of data per memory cell is called a single-level cell ("SLC"). The data stored in an SLC memory cell is called SLC data, and therefore SLC data contains 1 bit per memory cell. The data stored as 1 bit per memory cell is SLC data. Figure 5A shows two threshold voltage distributions E and P. Threshold voltage distribution E corresponds to the erased data state. Threshold voltage distribution P corresponds to the programmed data state. Therefore, a memory cell with a threshold voltage within threshold voltage distribution E is in the erased data state (e.g., erased). Therefore, memory cells having a threshold voltage within the threshold voltage distribution P are in a programmed data state (e.g., they are programmed). In one embodiment, an erased memory cell stores the data "1", and a programmed memory cell stores the data "0". Figure 5A illustrates the read reference voltage Vr. By testing whether the threshold voltage of a given memory cell is higher or lower than Vr (e.g., by performing one or more sense operations), the system can determine whether the memory cell is erased (state E) or programmed (state P). To test whether the threshold voltage of a given memory cell is higher or lower than Vr, the system applies Vr to selected word lines (word lines connected to memory cells selected for reading) and Vread to unselected word lines (word lines not connected to memory cells selected for reading).Vread is an example of an overdrive voltage because it is high enough to turn on a memory cell regardless of which data state the memory cell is programmed to. For example, Figure 5A illustrates Vread, which is higher in magnitude than any of the threshold voltages associated with the threshold voltage distribution for a data state P. In some memory systems, Vread is set to 6-8 volts (e.g., one or more overdrive voltages). Figure 5A also illustrates a verification reference voltage Vv. In some embodiments, when programming memory cells to a data state P, the system tests whether those memory cells have a threshold voltage greater than or equal to Vv. To test whether the threshold voltage of a given memory cell is higher or lower than Vv, the system applies Vv to selected word lines (word lines connected to memory cells selected for programming) and Vread to unselected word lines (word lines not connected to memory cells selected for programming).

[0066] Figures 5B to 5D illustrate exemplary threshold voltage distributions for a memory array when each memory cell stores multiple bits per memory cell data. Memory cells that store multiple bits per memory cell data are called multi-level cells ("multi-level cells, MLCs"). Data stored in MLC memory cells is called MLC data, and therefore MLC data contains multiple bits per memory cell. Data stored as multiple bits per memory cell is MLC data. In the exemplary embodiment of Figure 5B, each memory cell stores 2 bits of data. Other embodiments may use other data capacities per memory cell (e.g., 3, 4, or 5 bits of data per memory cell).

[0067] Figure 5B shows a first threshold voltage distribution E for an erased memory cell. Three threshold voltage distributions A, B, and C for programmed memory cells are also depicted. In one embodiment, the threshold voltage of distribution E is negative, and the threshold voltages of distributions A, B, and C are positive. Each distinct threshold voltage distribution in Figure 5B corresponds to a default value for a set of data bits. In one embodiment, the data for each bit of two bits of data stored in the memory cell resides in different logical pages referred to as the lower page (LP) and the upper page (UP). In other embodiments, all bits of data stored in the memory cell reside in a common logical page. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme employed for those cells. Table 1 provides exemplary encoding schemes.

[0068] [Table 1]

[0069] In one known embodiment of full-sequence programming, memory cells can be programmed directly from erase data state E to program data states A, B, or C using the process shown in Figure 6 (discussed below). For example, a group of memory cells to be programmed may first be erased so that all memory cells in the group are in erase data state E. Then, the programming process is used to directly program the memory cells to data states A, B, and / or C. For example, while some memory cells are programmed from data state E to data state A, other memory cells are programmed from data state E to data state B and / or from data state E to data state C. The arrows in Figure 5B represent full-sequence programming. In some embodiments, data states A-C may overlap, as the memory controller 120 (or control die 211) relies on error correction to identify the correct data being stored.

[0070] Figure 5C illustrates exemplary threshold voltage distributions for memory cells, each of which stores 3 bits of data per memory cell (another example of MLC data). Figure 5C shows eight threshold voltage distributions corresponding to eight data states. The first threshold voltage distribution (data state) Er represents a memory cell being erased. The other seven threshold voltage distributions (data states) A-G represent programmed memory cells and are therefore also called programming states. Each threshold voltage distribution (data state) corresponds to a default value for a set of data bits. The specific relationship between the data programmed into a memory cell and the threshold voltage level of the cell depends on the data encoding scheme employed for those cells. In one embodiment, data values ​​are assigned to threshold voltage ranges using Gray code assignment such that only one bit is affected if the memory threshold voltage is incorrectly shifted to its adjacent physical state. Table 2 provides examples of encoding schemes for embodiments in which the data for each bit of the 3 bits of data stored in a memory cell resides on different logical pages referred to as the lower page (LP), middle page (MP), and upper page (UP).

[0071] [Table 2]

[0072] Figure 5C shows seven read reference voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG for reading data from a memory cell. By testing whether the threshold voltage of a given memory cell is higher or lower than the seven read reference voltages (e.g., performing a sense operation), the system can determine which data state (i.e., A, B, C, D, ...) the memory cell is in.

[0073] Figure 5C also shows seven verification reference voltages VvA, VvB, VvC, VvD, VvE, VvF, and VvG. In some embodiments, when programming memory cells to data state A, the system will test whether those memory cells have a threshold voltage of VvA or higher. When programming memory cells to data state B, the system will test whether the memory cells have a threshold voltage of VvB or higher. When programming memory cells to data state C, the system will determine whether the memory cells have a threshold voltage of VvC or higher. When programming memory cells to data state D, the system will test whether those memory cells have a threshold voltage of VvD or higher. When programming memory cells to data state E, the system will test whether those memory cells have a threshold voltage of VvE or higher. When programming memory cells to data state F, the system will test whether those memory cells have a threshold voltage of VvF or higher. When programming memory cells to data state G, the system will test whether those memory cells have a threshold voltage of VvG or higher. Figure 5C also shows Vev, the erase verification reference voltage used to test whether the memory cells have been properly erased.

[0074] In embodiments utilizing full-sequence programming, memory cells can be directly programmed from the erased data state Er to one of the programmed data states A-G using the process shown in Figure 6 (discussed below). For example, a group of memory cells to be programmed may first be erased so that all memory cells in the group are in the erased data state Er. Then, the programming process is used to directly program the memory cells to data states A, B, C, D, E, F, and / or G. For example, while some memory cells are programmed from data state Er to data state A, other memory cells are programmed from data state Er to data state B, and / or from data state Er to data state C, and so on. The arrows in Figure 5C represent full-sequence programming. In some embodiments, data states A-G may overlap, as the control die 211 and / or memory controller 120 rely on error correction to identify the correct data being stored. Note that in some embodiments, instead of using full-sequence programming, the system may use multi-path programming processes known in the art.

[0075] Generally, during verification and read operations, the selected word line is connected to a voltage (an example of a reference signal), the level of which is specified for each read operation (e.g., see read comparison voltages / levels VrA, VrB, VrC, VrD, VrE, VrF, and VrG in Figure 5C) or verification operation (e.g., see verification target voltages / levels VvA, VvB, VvC, VvD, VvE, VvF, and VvG in Figure 5C) to determine whether the threshold voltage of the memory cell in question has reached that level. After applying the word line voltage, the conduction current of the memory cell is measured to determine whether the memory cell has turned on in response to the voltage applied to the word line (conduction current). If the conduction current is measured to be greater than a certain value, the memory cell is turned on, and the voltage applied to the word line is considered to be greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than a certain value, the memory cell is not turned on, and the voltage applied to the word line is considered to be less than the threshold voltage of the memory cell. During the read or verify process, unselected memory cells are provided with one or more read path voltages (also referred to as bypass voltages) at their control gates so that these memory cells act as pass gates (e.g., conduct current whether programmed or erased).

[0076] There are many methods for measuring the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured by the rate at which a dedicated capacitor in a sensitivity amplifier discharges or charges. In another example, the conduction current of a selected memory cell allows (or prevents) the NAND string containing the memory cell to discharge the corresponding bit line. The voltage on the bit line is measured after a period of time to see if it has discharged. It should be noted that the techniques described herein can be used in conjunction with different methods known in the art for verification / readout. Other read and verification techniques known in the art can also be used.

[0077] Figure 5D illustrates the threshold voltage distribution when each memory cell stores 4 bits of data, which is another example of MLC data. Figure 5D illustrates that there may be some overlap in the threshold voltage distribution (data states) S0 to S15. This overlap may occur due to factors such as the memory cell losing charge (and therefore the threshold voltage decreasing). Program failures may unintentionally increase the threshold voltage of a memory cell. Similarly, read failures may unintentionally increase the threshold voltage of a memory cell. Over time, the position of the threshold voltage distribution may change. Such changes may increase the bit error rate, thereby increasing the decoding time or even making decoding impossible. Changing the read reference voltage may help mitigate such effects. Errors and ambiguities can be corrected by using ECC during the read process. Note that in some embodiments, the threshold voltage distributions for a group of memory cells storing 4 bits of data per memory cell are non-overlapping and isolated from one another. The threshold voltage distribution in Figure 5D includes the read reference voltage and the verification reference voltage, as discussed above.

[0078] When using 4 bits per memory cell, the memory can be programmed using the full-sequence programming discussed above, or using multi-pass programming processes known in the art. Each threshold voltage distribution (data state) in Figure 5D corresponds to a default value for a set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme employed for those cells. Table 3 provides examples of encoding schemes for several embodiments in which the data of each bit of the 4-bit data stored in the memory cell resides in different logical pages referred to as the lower page (LP), middle page (MP), upper page (UP), and top page (TP).

[0079] [Table 3]

[0080] Figure 6 is a flowchart illustrating one embodiment of a process for programming memory cells. For the purposes of this specification, the terms program and programming are synonymous with write and writing. In one exemplary embodiment, the process in Figure 6 is performed on the memory array 202 using one or more control circuits considered above (e.g., system control logic 260, column control circuit 210, row control circuit 220). In one exemplary embodiment, the process in Figure 6 is performed by the memory die using one or more control circuits of the control die 211 (e.g., system control logic 260, column control circuit 210, row control circuit 220) to program memory cells on the memory array die 201. This process includes multiple loops, each of which includes a programming stage and a verification stage. The process in Figure 6 is performed to implement full-sequence programming, as well as other programming methods, including multi-stage programming. When implementing multi-stage programming, the process in Figure 6 is used to implement any / each stage of the multi-stage programming process.

[0081] Typically, the program voltage applied to the control gate (via the selected data word line) during program operation is applied as a series of program voltage pulses. Between the program voltage pulses is a set of verification pulses (e.g., voltage pulses) for performing verification. In many implementations, the magnitude of the program voltage pulses increases by a predetermined step size with each successive pulse. In step 602 of Figure 6, the programming voltage signal (Vpgm) is initialized to a starting magnitude (e.g., about 12-16V or another preferred level), and the program counter PC, maintained by the state machine 262, is initialized to 1. In one embodiment, a group of memory cells selected to be programmed (hereinafter referred to as selected memory cells) are programmed simultaneously and all connected to the same word line (selected word line). It is likely that there are other memory cells (unselected memory cells) that are not selected for programming and are also connected to the selected word line. That is, the selected word line will also be connected to memory cells that are to be prevented from being programmed. In addition, when a memory cell reaches its intended target data state, it will be prevented from being programmed further. NAND strings containing memory cells connected to selected word lines that will prevent programming (e.g., unselected NAND strings) boost their channels to prevent programming. When the channels have a boosted voltage, the voltage difference between the channels and the word lines is not large enough to cause programming. To assist in boosting, in step 604, the control die pre-charges the channels of the NAND strings containing memory cells connected to selected word lines that will prevent programming. In step 606, NAND strings containing memory cells connected to selected word lines that will prevent programming boost their channels to prevent programming. Such NAND strings are referred to herein as “unselected NAND strings”.In one embodiment, the unselected word line receives one or more boost voltages (e.g., about 7-11 volts) to perform a boost scheme. A program stop voltage is applied to the bit line coupled to the unselected NAND string.

[0082] In step 608, a program voltage pulse of the programming voltage signal Vpgm is applied to the selected word line (the word line selected for programming). If a memory cell on the NAND string is to be programmed, the corresponding bit line is biased with the program active voltage. In step 608, the program pulse is applied simultaneously to all memory cells connected to the selected word line, and as a result, all memory cells connected to the selected word line are programmed simultaneously (unless their programming is prevented). That is, they are programmed simultaneously or during overlapping time periods (both are considered simultaneous). In this way, all memory cells connected to the selected word line will change their threshold voltages simultaneously, unless their programming is prevented.

[0083] In step 610, program verification is performed, which includes testing whether the programmed memory cells have successfully reached their target data states. Memory cells that have reached their target states are protected from further programming by the control die. Step 610 includes performing programming verification by sensing one or more verification criterion levels. In one embodiment, the verification process is performed by testing whether the threshold voltage of the memory cell selected for programming has reached an appropriate verification criterion voltage. After it has been verified (by testing Vt) that the memory cell has reached its target state in step 610, the memory cell may be protected.

[0084] In one embodiment of step 610, smart verification techniques are used so that the system verifies only a subset of data states during the program loop (steps 604-628). For example, a first program loop includes verifying data state A (see Figure 5C), and depending on the result of the verification operation, a second program loop may perform verification for data states A and B, and depending on the result of the verification operation, a third program loop may perform verification for data states B and C, and so on.

[0085] In step 616, the number of memory cells that have not yet reached their respective target threshold voltage distributions is counted. That is, the number of memory cells that have not yet reached the target state is counted. This count can be performed by the state machine 262, the memory controller 120, or another circuit. In one embodiment, there is a single total count, which reflects the total number of currently programmed memory cells that failed the last verification step. In another embodiment, a separate count is maintained for each data state.

[0086] In step 617, the system determines whether the verification operation in the most recent run of step 610 included verifying the last data state (e.g., data state G in Figure 5C). If so, in step 618, it is determined whether the count from step 616 is less than or equal to a default limit. In one embodiment, the default limit is the number of bits that can be corrected by the error correction code (ECC) during the read process for a page of memory cells. If the number of failed cells is less than or equal to the default limit, the programming process can be stopped, and a "pass" status is reported in step 614. In this situation, enough memory cells are correctly programmed so that a small number of remaining memory cells that are not fully programmed can be corrected using ECC during the read process. In some embodiments, the default limit used in step 618 is less than the number of bits that can be corrected by the error correction code (ECC) during the read process to allow for future / additional errors. When programming fewer memory cells than all of the memory cells for a page, the default limit may be a portion (proportional or inproportional) of the number of bits that can be corrected by ECC during the read process for a page of memory cells. In some embodiments, the limit is not defined. Instead, the limit varies based on the number of errors already counted for a page, the number of program-erase cycles performed, or other criteria.

[0087] In step 617, if it is determined that the verification operation in the most recent run of step 610 does not include verifying the last data state, or in step 618, if it is determined that the number of failed memory cells is greater than or equal to a predetermined limit, then in step 619, the data state to be verified in the next run of step 610 (the next program loop) is adjusted according to the smart verification scheme discussed above. In step 620, the program counter PC is checked against the program limit value (PL). Examples of program limit values ​​include 6, 12, 16, 19, 20, and 30, but other values ​​may also be used. If the program counter PC is greater than or equal to the program limit value PL, the program process is considered failed, and in step 624, a FAIL status is reported. If the program counter PC is less than the program limit value PL, the process proceeds to step 626, during which the program counter PC is incremented by 1, and the programming voltage signal Vpgm is stepped up to the next magnitude. For example, the next pulse has a magnitude greater than the previous pulse by a step size ΔVpgm (e.g., a step size of 0.1 to 1.0 volts). After step 626, the process proceeds to step 604, where another program pulse is applied to a selected word line (by the control die), resulting in the execution of another program loop of the programming process (steps 604 to 626) shown in Figure 6.

[0088] In one embodiment, memory cells are erased before programming. Erasing is the process of changing the threshold voltage of one or more memory cells from a data state to be programmed to a data state to be erased. For example, this involves changing the threshold voltage of one or more memory cells from state P to state E in Figure 5A, from states A / B / C to state E in Figure 5B, from states A to G to state Er in Figure 5C, or from states S1 to S15 to state S0 in Figure 5D. In one embodiment, the control circuit is configured to program the memory cells in the direction from the erased data state to the highest data state (e.g., from data state Er to data state G) and erase the memory cells in the direction from the highest data state to the erased data state (e.g., from data state G to data state Er).

[0089] One technique for erasing memory cells in some memory devices is to charge the NAND channel by biasing a p-well (or other type of) substrate to a high voltage. While the NAND channel is at the high voltage for erasing the memory cell, an erase-effective voltage (e.g., a low voltage) is applied to the control gate of the memory cell. This is referred to herein as p-well erasure.

[0090] Another approach to erasing a memory cell is to charge the NAND string channel by generating a gate-induced drain leakage ("GIDL") current. An erasure effective voltage is applied to the control gate of the memory cell while maintaining the NAND string channel potential for erasing the memory cell. This is referred to herein as GIDL erasure. Both p-well erasure and GIDL erasure can be used to reduce the threshold voltage (Vt) of a memory cell.

[0091] In one embodiment, the GIDL current is generated by creating a drain-gate voltage in the GIDL generating transistors (e.g., transistors connected to SGDT0, SGDT1, SGSB0, and SGSB1). In some embodiments, a selection gate (e.g., SGD or SGS) can be used as the GIDL generating transistor. The drain-gate voltage of the transistor generating the GIDL current is referred to herein as the GIDL voltage. The GIDL current can occur when the drain voltage of the GIDL generating transistor is significantly higher than the control gate voltage of the GIDL generating transistor. The GIDL current is the result of carrier generation, i.e., electron-hole pair generation resulting from interband tunneling and / or trap-assisted generation. In one embodiment, the GIDL current can result in one type of carrier (also referred to as charge carrier), e.g., holes, moving mostly into the NAND channel, thereby raising or changing the potential of the channel. Other types of carriers, e.g., electrons, are extracted from the channel by an electric field in the direction of the bit line or source line. During erasure, holes can tunnel from the channel to the charge storage region of the memory cell (e.g., the charge trap layer 493), where they can recombine with electrons and lower the threshold voltage of the memory cell.

[0092] A GIDL current can be generated at either end (or both ends) of a NAND string. A first GIDL voltage can be generated between two terminals of a GIDL generating transistor (e.g., connected to SGDT0, SGDT1) connected to or near the bit line to generate a first GIDL current. A second GIDL voltage can be generated between two terminals of a GIDL generating transistor (e.g., SGSB0, SGSB1) connected to or near the source line to generate a second GIDL current. Erasing based on a GIDL current at only one end of a NAND string is referred to as a one-sided GIDL erase. Erasing based on a GIDL current at both ends of a NAND string is referred to as a two-sided GIDL erase. The techniques described herein can be used together with one-sided and two-sided GIDL erases.

[0093] Tables 1, 2, and 3 (above) describe data encoding for memories that store multiple bits of data per memory cell. The more bits of data stored per memory cell, the larger the memory capacity. Therefore, a memory designed to have the highest possible capacity among embodiments with 2 bits per memory cell, 3 bits per memory cell, or 4 bits per memory cell is implemented with 4 bits per memory cell.

[0094] The programming process can be implemented as a one-pass programming process or a two-pass programming process. A one-pass programming process functions to program a set of data into a set of memory cells using one pass of the programming process. In other words, the memory system will program a set of data into a set of memory cells in one process without interruption to program other memory cells in the same block. For example, the process in Figure 6 is executed once to program a set of data into a set of memory cells. An example of a one-pass programming process is the full-sequence programming discussed above, in which a set of memory cells is programmed directly from the erase state to their final target data state. Figure 7 shows full-sequence programming for memory cells that store 4 bits of data per memory cell. All memory cells are initially in the erase data state S0. During full-sequence programming (as indicated by the arrows), the group of memory cells is programmed directly from the erase state S0 to their final target data state (e.g., one of S1-S15) without first being programmed into an intermediate data state.

[0095] In a two-pass programming process, the memory system begins (but does not complete) programming a first set of data into a first set of memory cells, then programs (or partially programs) a different set of data into other memory cells within the same block, and then returns to complete programming the first set of data into the first set of memory cells. An example of a two-pass programming process is foggy fine programming, where the first pass is a foggy pass (foggy programming) and the second pass is a fine pass (fine programming). The foggy pass approximates the final programming. The fine pass results in the final programming (the memory cells are in their target threshold voltage distribution or data state). Between the foggy pass and the fine pass, the memory system can work on programming other memory cells. In some embodiments, both the fine pass and the foggy pass result in the threshold voltage distribution. Figures 8A–8C illustrate foggy fine programming for memory cells storing 4 bits of data per memory cell. Figure 8A depicts a group of memory cells all starting in the erased data state S0 after an erase process. The first pass (foggy pass) programs the memory cell to a set of intermediate threshold voltage distributions S1'~S15', where the intermediate threshold voltage distributions S1'~S15' are broader and the voltages are shifted down compared to the final target threshold voltage distributions S1~S15. That is, the foggy pass includes programming the memory cell from a state as depicted in Figure 8A to a state as depicted in Figure 8B. In one embodiment, the foggy pass is performed by executing the process in Figure 6. The second pass (fine pass) programs the memory cell from the set of intermediate threshold voltage distributions S1'~S15' to the final target threshold voltage distributions S1~S15. That is, the fine pass includes programming the memory cell from a state as depicted in Figure 8B to a state as depicted in Figure 8C. In one embodiment, the fine pass is performed by executing the process in Figure 6.

[0096] One reason for implementing a two-pass programming process compared to a one-pass programming process is to address adjacent word line interference, which occurs when memory cells connected to a first word line appear to have their threshold voltages altered due to electromagnetic fields or capacitive coupling from memory cells programmed after being connected to an adjacent word line. For example, consider, referring to Figure 4F, the case where the memory system first programs a memory cell connected to word line WL1. Subsequently, the memory system programs a memory cell connected to word line WL2. After completing the programming of the memory cell connected to word line WL2, the threshold voltage of the memory cell connected to WL1 may appear to have shifted, which can lead to errors during readout.

[0097] One way to reduce the effects of adjacent word line interference is to perform a two-pass programming process. In the example above, the memory system first performs the first pass of the programming process (e.g., a foggy pass) on the memory cell connected to WL1, then the first pass of the programming process on the memory cell connected to WL2, then the second pass of the programming process (e.g., a fine pass) on the memory cell connected to WL1, and then the second pass of the programming process on the memory cell connected to WL2. In this way, the memory cell connected to WL1 will experience only a very small amount of adjacent word line interference because the programming for WL2 after programming for WL1 is only the second pass (e.g., a fine pass).

[0098] The two-pass programming process reduces adjacent word line interference but is slower than the one-pass programming process. To address this performance issue and increase programming speed, it is proposed to program some word lines using the two-pass programming process and other word lines using the one-pass programming process (e.g., a 1.5-pass programming process).

[0099] Figure 9 illustrates a portion of a non-volatile memory system in which some word lines are programmed using a two-pass programming process and other word lines are programmed using a one-pass programming process. For example, Figure 9 shows a control circuit 902 connected to a block of memory cells 904. The control circuit 902 may be one of the one or more control circuits discussed above. Next to (to the right of) each word line WL0 to WL161 is either "1P" or "2P". "1P" indicates a word line that will be programmed using a one-pass programming process. "2P" indicates a word line that will be programmed using a two-pass programming process. Thus, in the embodiment of Figure 9, the memory cells connected to word lines WL0, WL2, WL4, WL6, WL8, ..., WL158, and WL160 will be programmed using a two-pass programming process (e.g., Figures 8A to 8C), and the memory cells connected to word lines WL1, WL3, WL5, WL7, WL9, ..., WL159, and WL161 will be programmed using a one-pass programming process (e.g., Figure 7).

[0100] In the example in Figure 9, half of the word lines will be programmed using a two-pass programming process (e.g., foggy fine programming), and the other half will be programmed using a one-pass programming process (e.g., full sequence programming). Figure 9 also shows that the word lines subject to two-pass programming (e.g., WL0, WL2, WL4, ...) are mixed with the word lines subject to one-pass programming (e.g., WL1, WL3, WL5, ...) when the two sets of word lines are mixed together. In the exemplary implementation in Figure 9, the word lines subject to two-pass programming (e.g., WL0, WL2, WL4, ...) are alternate word lines, and the word lines subject to one-pass programming (e.g., WL1, WL3, WL5, ...) are alternate word lines alternating between the word lines subject to two-pass programming (e.g., WL0, WL2, WL4, ...). In other embodiments, other arrangements can be implemented to divide the word lines into word lines subject to one-pass programming and word lines subject to two-pass programming.

[0101] Figure 10 is a flowchart illustrating the operation of the structure in Figure 9 for programming some word lines using a two-pass programming process and other word lines using a one-pass programming process. The process in Figure 10 is performed by one of the control circuits described above. In step 1002, the control circuit programs the memory cell connected to word line WL0 using a two-pass programming process, such as foggy fine programming in Figures 8A-8C. Other two-pass programming processes may also be used. In step 1004, the control circuit programs the memory cell connected to word line WL1 using a one-pass programming process, such as full sequence programming in Figure 7. Other one-pass programming processes may also be used. In step 1006, the control circuit programs the memory cell connected to word line WL2 using a two-pass programming process. In step 1008, the control circuit programs the memory cell connected to word line W3 using a one-pass programming process. As depicted in Figure 9, WL1 is located between WL0 and WL2, and WL2 is located between WL1 and WL3. In step 1010, the control circuit programs the memory cell connected to word line WL4 using a two-pass programming process. In step 1012, the control circuit programs the memory cell connected to word line W5 using a one-pass programming process. In step 1014, the control circuit programs the memory cell connected to word line WL6 using a two-pass programming process. In step 1016, the control circuit programs the memory cell connected to word line W7 using a one-pass programming process. This process continues until all word lines in the block have been programmed.

[0102] Figure 11 is a table illustrating the programming sequence when programming some word lines using the foggy / fine programming (two-pass programming process) of Figures 8A-8C and programming other word lines using the full sequence programming (one-pass programming process) of Figure 7. Figure 11 illustrates an exemplary implementation of the process of Figure 10, performed using the structure of Figure 9. Figure 11 shows the programming for nine word lines, namely WLn-3, WLn-2, ​​WLn-1, WLn, WLn+1, WLn+2, WLn+3, WLn+4, and WLn+5. In this example, the memory cells connected to WLn-3, WLn-1, WLn+1, WLn+3, and WLn+5 undergo foggy fine programming, while the memory cells connected to WLn-2, ​​WLn, WLn+2, and WLn+4 undergo full sequence programming. Word line WLn can be any of the word lines WL3-WL156.

[0103] Figure 11 shows the 12 steps (Steps 1-12) that are executed sequentially from Step 1 to Step 12 (for example, Step 8 is executed after Step 7 and before Step 9). In Step 1, the control circuit programs the memory cell connected to word line WLn-1 using the foggy pass of foggy fine programming (two-pass programming) (for example, Figures 8A-8B). In Step 2, the control circuit programs the memory cell connected to word line WLn-2 using full sequence programming (one-pass programming). In Step 3, the control circuit programs the memory cell connected to word line WLn-3 using the fine pass of foggy fine programming (two-pass programming) (for example, Figures 8B-8C). The memory cell connected to word line WLn-3 has already experienced the foggy pass (before Step 1).

[0104] In step 4, the control circuit programs the memory cell connected to word line WLn+1 using the foggy pass of foggy fine programming (two-pass programming). In step 5, the control circuit programs the memory cell connected to word line WLn using full sequence programming (one-pass programming). In step 6, the control circuit programs the memory cell connected to word line WLn-1 using the fine pass of foggy fine programming (two-pass programming).

[0105] In step 7, the control circuit programs the memory cell connected to word line WLn+3 using the foggy pass of foggy fine programming (two-pass programming). In step 8, the control circuit programs the memory cell connected to word line WLn+2 using full sequence programming (one-pass programming). In step 9, the control circuit programs the memory cell connected to word line WLn+1 using the fine pass of foggy fine programming (two-pass programming).

[0106] In step 10, the control circuit programs the memory cell connected to word line WLn+5 using the foggy pass of foggy fine programming (two-pass programming). In step 11, the control circuit programs the memory cell connected to word line WLn+4 using full sequence programming (one-pass programming). In step 12, the control circuit programs the memory cell connected to word line WLn+3 using the fine pass of foggy fine programming (two-pass programming). This process can be repeated for any additional word lines in the block.

[0107] Because full sequence programming is executed in one pass, it can be completed much faster than foggy fine programming. Therefore, a strategy of programming some (e.g., half) word lines using full sequence programming (1 pass) and some (e.g., half) word lines using foggy fine programming (2 passes) can be executed significantly faster than if all word lines were programmed using foggy fine programming.

[0108] Figures 12 and 13 are tables illustrating a portion of the table in Figure 11 and can be used to show that the average effect of adjacent word line interference does not worsen when switching from all word lines programmed using foggy fine programming (2 passes) to the process described in Figures 9-11.

[0109] Figure 12 shows that in step 5, the memory cell connected to word line WLn (programmed using a one-pass programming process (e.g., full-sequence programming)) subsequently receives a fine pass (second pass) of foggy fine programming on the memory cells on adjacent word lines WLn-1 and WLn+1, as indicated by the shading. Thus, the memory cell on WLn experiences interference from adjacent word lines WLn-1 and WLn+1, but only in the case of the fine pass.

[0110] Figure 13 shows that a memory cell connected to word line WLn-1, programmed using two-pass programming including the fine pass in step 6, does not have any memory cells connected to adjacent word lines that are programmed later, because WLn-2 is programmed in step 2 and WLn is programmed in step 5 (both before step 6). Therefore, the memory cell of WLn-1 does not experience adjacent word line interference from WLn-2 and WLn. Together, Figures 12 and 13 teach that in the proposed programming of Figures 9-11, some word lines experience more adjacent word line interference than when all word lines are programmed using foggy fine programming, some word lines experience no adjacent word line interference, and on average, the adjacent word line interference is the same as or less than when all word lines are programmed using foggy fine programming.

[0111] A non-volatile memory is described that can program a large number of bits per memory cell at a faster rate than conventional systems.

[0112] One embodiment includes a non-volatile storage device, the non-volatile storage device comprising a first set of non-volatile memory cells and a second set of non-volatile memory cells, The system comprises a first set of word lines connected to a first set of nonvolatile memory cells, a second set of word lines connected to a second set of nonvolatile memory cells, wherein the first set of word lines is mixed with the second set of word lines, and a control circuit connected to the first set of nonvolatile memory cells, the second set of nonvolatile memory cells, the first set of word lines, and the second set of word lines. The control circuit is configured to program the first set of nonvolatile memory cells connected to the first set of word lines using a two-pass programming process, and to program the second set of nonvolatile memory cells connected to the second set of word lines using a one-pass programming process.

[0113] In one exemplary implementation, the word lines of the first set are arranged alternately with the word lines of the second set.

[0114] In one exemplary implementation, a first set of non-volatile memory cells and a second set of non-volatile memory cells are located within a first block, and the word lines of the first set and the word lines of the second set are located within the first block. In one alternative example, the word lines of the first set are half of all the word lines for the first block, and the word lines of the second set are half of all the word lines for the first block. In one alternative example, the word lines for the first block are arranged to alternate between the word lines of the first set and the word lines of the second set.

[0115] In one exemplary implementation, a two-pass programming process includes a first pass and a second pass, the first pass including a foggy pass that approximates the final programming, and the second pass including a fine pass that represents the final programming.

[0116] In one exemplary implementation, the foggy path creates a set of threshold voltage distributions, and the fine path tightens this set of threshold voltage distributions.

[0117] In one exemplary implementation, a first set of word lines includes a first word line and a third word line, a second set of word lines includes a second word line, and the control circuit is configured to program a first set of non-volatile memory cells connected to a first word line using a two-pass programming process, a second set of non-volatile memory cells connected to a second word line using a one-pass programming process, and a third set of non-volatile memory cells connected to a third word line using a two-pass programming process, wherein the second word line is located between the first and third word lines.

[0118] In one exemplary implementation, the first set of word lines includes a fourth word line, the second set of word lines includes a fifth word line, and the control circuit is further configured to program the first set of non-volatile memory cells connected to the first set of word lines using a two-pass programming process, and to program the second set of non-volatile memory cells connected to the second set of word lines using a one-pass programming process, wherein the fourth word line is located between the first and fifth word lines.

[0119] In one exemplary implementation, a two-pass programming process comprises a first pass and a second pass, and programming a non-volatile memory cell connected to a first word line using the two-pass programming process includes performing a first pass on the non-volatile memory cell connected to the first word line before programming the non-volatile memory cell connected to the second word line using a one-pass programming process, and performing a second pass on the non-volatile memory cell connected to the first word line after programming the non-volatile memory cell connected to the second word line using a one-pass programming process.

[0120] In one exemplary implementation, programming a non-volatile memory cell connected to a third word line using a two-pass programming process includes performing a first pass on the non-volatile memory cell connected to the third word line before programming the non-volatile memory cell connected to the second word line using a one-pass programming process, and performing a second pass on the non-volatile memory cell connected to the third word line after programming the non-volatile memory cell connected to the second word line using a one-pass programming process.

[0121] In one exemplary implementation, programming a non-volatile memory cell connected to a third word line using a two-pass programming process further includes performing a first pass on the non-volatile memory cell connected to the third word line before programming the non-volatile memory cell connected to the first word line using a first pass; and programming a non-volatile memory cell connected to a third word line using a two-pass programming process further includes performing a second pass on the non-volatile memory cell connected to the third word line after programming the non-volatile memory cell connected to the first word line using a first pass, and before programming the non-volatile memory cell connected to the first word line using a second pass.

[0122] Embodiments include a method comprising: programming a non-volatile memory cell connected to a first word line using a two-pass programming process; programming a non-volatile memory cell connected to a second word line using a one-pass programming process; and programming a non-volatile memory cell connected to a third word line using a two-pass programming process, wherein the second word line is located between the first and third word lines.

[0123] One exemplary embodiment further includes programming a non-volatile memory cell connected to a fourth word line using a one-pass programming process, and programming a non-volatile memory cell connected to a fifth word line using a two-pass programming process, wherein the fourth word line is located between the first word line and the fifth word line.

[0124] In one exemplary implementation, a two-pass programming process comprises a first pass and a second pass, and programming a non-volatile memory cell connected to a first word line using the two-pass programming process includes performing a first pass on the non-volatile memory cell connected to the first word line before programming the non-volatile memory cell connected to the second word line using a one-pass programming process, and performing a second pass on the non-volatile memory cell connected to the first word line after programming the non-volatile memory cell connected to the second word line using a one-pass programming process.

[0125] In one exemplary implementation, programming a non-volatile memory cell connected to a third word line using a two-pass programming process includes performing a first pass on the non-volatile memory cell connected to the third word line before programming the non-volatile memory cell connected to the second word line using a one-pass programming process, and performing a second pass on the non-volatile memory cell connected to the third word line after programming the non-volatile memory cell connected to the second word line using a one-pass programming process.

[0126] In one exemplary implementation, programming a non-volatile memory cell connected to a third word line using a two-pass programming process further includes performing a first pass on the non-volatile memory cell connected to the third word line before programming the non-volatile memory cell connected to the first word line using a first pass; and programming a non-volatile memory cell connected to a third word line using a two-pass programming process further includes performing a second pass on the non-volatile memory cell connected to the third word line after programming the non-volatile memory cell connected to the first word line using a first pass, and before programming the non-volatile memory cell connected to the first word line using a second pass.

[0127] In one exemplary implementation, a two-pass programming process includes a first pass and a second pass, the first pass including a foggy pass that approximates the final programming, and the second pass including a fine pass that represents the final programming.

[0128] In one exemplary implementation, the foggy path creates a set of threshold voltage distributions, and the fine path tightens this set of threshold voltage distributions.

[0129] One embodiment includes a non-volatile storage device comprising: non-volatile memory cells arranged in a block; word lines connected to the non-volatile memory cells; and means for programming the non-volatile memory cells of a first block connected to a first subset of word lines using a one-pass programming process, and for programming the non-volatile memory cells of the first block connected to a second subset of word lines using a two-pass programming process.

[0130] For the purposes of this specification, means for programming a first block of nonvolatile memory cells connected to a first subset of word lines using a one-pass programming process, and for programming a first block of nonvolatile memory cells connected to a second subset of word lines using a two-pass programming process, may be implemented by any of the control circuit embodiments described above (see also, for example, Figure 1, Figure 2A, or Figure 2B), which include the structure of Figure 9, perform the process of Figure 10, and implement the embodiment of Figure 11.

[0131] For the purposes of this specification, references herein to “embodiments,” “one embodiment,” “several embodiments,” or “another embodiment” may be used to describe different embodiments or the same embodiment.

[0132] For the purposes of this specification, a connection may be a direct connection or an indirect connection (e.g., through one or more other parts). Where it may be said that an element is connected or coupled to another element, that element may be directly connected to the other element or indirectly connected to the other element through one or more intervening elements. When an element is said to be directly connected to another element, there are no intervening elements between that element and the other element. Two devices are “communicating” if they are connected directly or indirectly so that electronic signals can be communicated between them.

[0133] For the purposes of this specification, the term "based on" may be read as "based at least in part on."

[0134] For the purposes of this specification, the use of numerical terms such as “first” object, “second” object, and “third” object, without additional context, may not imply an ordering of objects, but rather may be used for identifying purposes to distinguish different objects.

[0135] In this specification, the term “set” of objects may refer to one or more “sets” of objects.

[0136] The detailed description above is presented for illustrative and explanatory purposes. It is not intended to be exhaustive or to limit the disclosed form to the exact form. Many modifications and variations are possible in light of the above teachings. The embodiments described have been selected to best illustrate the principles of the proposed art and its practical application, thereby enabling other persons skilled in the art to make the best use of it in various embodiments and with various modifications suitable for the specific use to be intended. The scope is intended to be defined by the claims appended herein.

Claims

1. Non-volatile storage device, The first set of non-volatile memory cells, The second set of non-volatile memory cells, The word line of the first set connected to the nonvolatile memory cell of the first set, A second set of word lines connected to the second set of nonvolatile memory cells, wherein the first set of word lines is mixed with the second set of word lines, The system comprises a first set of non-volatile memory cells, a second set of non-volatile memory cells, a word line of the first set, and a control circuit connected to the word line of the second set, A non-volatile storage device in which the control circuit is configured to program the first set of non-volatile memory cells connected to the first set of word lines using a two-pass programming process, and to program the second set of non-volatile memory cells connected to the second set of word lines using a one-pass programming process.

2. The word lines of the first set are arranged alternately with the word lines of the second set. The non-volatile storage device according to claim 1.

3. The first set of non-volatile memory cells and the second set of non-volatile memory cells are located within the first block. The word lines of the first set and the word lines of the second set are located within the first block. The non-volatile storage device according to claim 1.

4. The word lines of the first set are half of all the word lines for the first block, The word lines of the second set are half of all the word lines for the first block. The non-volatile storage device according to claim 3.

5. The word lines for the first block are arranged to alternate between the first set of word lines and the second set of word lines. The non-volatile storage device according to claim 3.

6. The two-pass programming process includes a first pass and a second pass, The first pass includes a foggy pass that approximates the final programming, The second path includes a fine path representing the final programming. The non-volatile storage device according to claim 1.

7. The aforementioned foggy path creates a set of threshold voltage distributions, The fine path tightens the set of threshold voltage distributions. The non-volatile storage device according to claim 6.

8. The first set of word lines includes a first word line and a third word line, The second set of word lines includes the second word line, The control circuit, The two-pass programming process described above is used to program the non-volatile memory cell connected to the first word line, The non-volatile memory cell connected to the second word line is programmed using the aforementioned one-pass programming process, The system is configured to program a non-volatile memory cell connected to a third word line using the two-pass programming process, wherein the second word line is positioned between the first word line and the third word line, thereby programming a first set of non-volatile memory cells connected to a first set of word lines using the two-pass programming process, and programming a second set of non-volatile memory cells connected to a second set of word lines using the one-pass programming process. The non-volatile storage device according to claim 1.

9. The first set of word lines includes a fourth word line, The second set of word lines includes a fifth word line, The aforementioned control circuit The two-pass programming process described above is used to program the non-volatile memory cell connected to the fourth word line, The system is further configured to program a non-volatile memory cell connected to a fifth word line using the one-pass programming process, wherein the fourth word line is located between the first word line and the fifth word line, by programming the first set of non-volatile memory cells connected to the first set of word lines using the two-pass programming process, and to program the second set of non-volatile memory cells connected to the second set of word lines using the one-pass programming process. The non-volatile storage device according to claim 8.

10. The two-pass programming process includes a first pass and a second pass, Programming the non-volatile memory cell connected to the first word line using the two-pass programming process includes: performing the first pass on the non-volatile memory cell connected to the first word line before programming the non-volatile memory cell connected to the second word line using the one-pass programming process; and performing the second pass on the non-volatile memory cell connected to the first word line after programming the non-volatile memory cell connected to the second word line using the one-pass programming process. The non-volatile storage device according to claim 8.

11. Programming the non-volatile memory cell connected to the third word line using the two-pass programming process includes: performing the first pass on the non-volatile memory cell connected to the third word line before programming the non-volatile memory cell connected to the second word line using the one-pass programming process; and performing the second pass on the non-volatile memory cell connected to the third word line after programming the non-volatile memory cell connected to the second word line using the one-pass programming process. The non-volatile storage device according to claim 10.

12. Programming the non-volatile memory cells connected to the third word line using the two-pass programming process further includes performing the first pass on the non-volatile memory cells connected to the third word line before programming the non-volatile memory cells connected to the first word line using the first pass, Programming the non-volatile memory cell connected to the third word line using the two-pass programming process further includes performing the second pass on the non-volatile memory cell connected to the third word line after programming the non-volatile memory cell connected to the first word line using the first pass, and before programming the non-volatile memory cell connected to the first word line using the second pass. The non-volatile storage device according to claim 11.

13. It is a method, The two-pass programming process is used to program the non-volatile memory cell connected to the first word line, The one-pass programming process is used to program the non-volatile memory cell connected to the second word line, A method comprising programming a non-volatile memory cell connected to a third word line using a two-pass programming process, wherein the second word line is positioned between the first word line and the third word line.

14. The one-pass programming process described above is used to program the non-volatile memory cell connected to the fourth word line, The process further includes programming a non-volatile memory cell connected to a fifth word line using the two-pass programming process, wherein the fourth word line is located between the first word line and the fifth word line. The method according to claim 13.

15. The two-pass programming process includes a first pass and a second pass, Programming the non-volatile memory cell connected to the first word line using the two-pass programming process includes: performing the first pass on the non-volatile memory cell connected to the first word line before programming the non-volatile memory cell connected to the second word line using the one-pass programming process; and performing the second pass on the non-volatile memory cell connected to the first word line after programming the non-volatile memory cell connected to the second word line using the one-pass programming process. The method according to claim 13.

16. Programming the non-volatile memory cell connected to the third word line using the two-pass programming process includes: performing the first pass on the non-volatile memory cell connected to the third word line before programming the non-volatile memory cell connected to the second word line using the one-pass programming process; and performing the second pass on the non-volatile memory cell connected to the third word line after programming the non-volatile memory cell connected to the second word line using the one-pass programming process. The method according to claim 15.

17. Programming the non-volatile memory cells connected to the third word line using the two-pass programming process further includes performing the first pass on the non-volatile memory cells connected to the third word line before programming the non-volatile memory cells connected to the first word line using the first pass, Programming the non-volatile memory cell connected to the third word line using the two-pass programming process further includes performing the second pass on the non-volatile memory cell connected to the third word line after programming the non-volatile memory cell connected to the first word line using the first pass, and before programming the non-volatile memory cell connected to the first word line using the second pass. The method according to claim 16.

18. The two-pass programming process includes a first pass and a second pass, The first pass includes a foggy pass that approximates the final programming, The second path includes a fine path representing the final programming. The method according to claim 13.

19. The aforementioned foggy path creates a set of threshold voltage distributions, The fine path tightens the set of threshold voltage distributions. The method according to claim 18.

20. Non-volatile storage device, Non-volatile memory cells arranged within the block, A word line connected to the aforementioned non-volatile memory cell, A non-volatile storage device comprising: means for programming a first block of non-volatile memory cells connected to a first subset of the word lines using a one-pass programming process; and means for programming a first block of non-volatile memory cells connected to a second subset of the word lines using a two-pass programming process.

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