MOS transistor and method for manufacturing the same

Abstract

The present invention provides a MOS transistor and a method for manufacturing the same that can form an LDD region that contributes well to electric field relaxation even when the thickness of the gate electrode is reduced. [Solution] The MOS transistor 11 comprises a pair of first LDD regions 23a and 23b separated by a well 14 provided in the substrate 12 below the gate electrode 15 and connected to a source region 21 and a drain region 22, respectively, and having a depth greater than the film thickness Tg of the gate electrode 15, and a pair of second LDD regions 24a and 24b separated by the well 14 below the gate electrode 15, overlapping with the orthographic projection of the gate electrode 15 on the surface of the substrate 12 by a predetermined dimension OL, and connected to the corresponding first LDD regions 23a and 23b, respectively, and having a depth less than the film thickness Tg of the gate electrode 15.

Description

[Technical Field]

[0001] This invention relates to a MOS (metal-oxide-semiconductor) transistor and a method for manufacturing the same. [Background technology]

[0002] To prevent performance degradation due to hot carrier injection in MOS transistors, a technique is known to relax the electric field between the channel region and the drain region using a lightly doped drain (LDD) structure. Patent document 1 discloses a technique for forming LDDs before forming the gate electrode. Patent document 2 discloses a technique for forming deep and shallow LDDs in a self-aligned manner relative to the gate electrode. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Chinese Patent No. 109524307 Specification [Patent Document 2] Chinese Patent No. 104425359 Specification [Overview of the project] [Problems that the invention aims to solve]

[0004] As semiconductor process nodes become smaller, the thickness of the gate electrode is reduced to improve the performance of MOS transistors and avoid process problems. However, when the gate electrode is used as a mask to form a self-aligned LDD, a problem arises where implanted ions penetrate the gate electrode and enter the channel region. If the ion implantation energy is reduced to prevent ions from penetrating the electrode, it becomes impossible to form an LDD that can sufficiently relax the electric field between the channel region and the drain region.

[0005] The present invention aims to provide a MOS transistor and a method for manufacturing the same that can form an LDD region that contributes well to electric field relaxation even when the thickness of the gate electrode is reduced. [Means for solving the problem]

[0006] A method for manufacturing a MOS transistor according to one embodiment of the present invention comprises the steps of: forming a mask pattern on a well provided on a substrate; using the mask pattern as a mask, injecting ions into the well to form a pair of first LDD regions separated by the well; forming a gate insulating film and a gate electrode on the well between the pair of first LDD regions; using the gate electrode as a mask, injecting ions into the first LDD region to form a pair of second LDD regions separated by the well, wherein the orthographic projection of the gate electrode on the surface of the substrate and the pair of second LDD regions on both sides of it overlap by a predetermined dimension; and forming a sidewall on the side wall of the gate electrode, using the gate electrode and the sidewall as a mask, injecting ions into the second LDD region to form a source region and a drain region.

[0007] A MOS transistor according to one embodiment of the present invention comprises a pair of first LDD regions having a depth greater than the film thickness of the gate electrode, separated by a well provided in the substrate below the gate electrode and connected to the source region and drain region, respectively; and a pair of second LDD regions separated by the well below the gate electrode, wherein the orthographic projection of the gate electrode on the surface of the substrate and the pair of second LDD regions on both sides of it overlap by a predetermined dimension, and the pair of second LDD regions are individually connected to the corresponding first LDD regions and have a depth less than the film thickness of the gate electrode. [Effects of the Invention]

[0008] As described above, according to the form of disclosure, a MOS transistor is provided that can form an LDD region that contributes well to electric field relaxation even when the thickness of the gate electrode is reduced, and a method for manufacturing the same. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic diagram illustrating the cross-sectional structure of a medium-voltage MOS (metal oxide semiconductor) transistor according to an embodiment of the present invention. [Figure 2] This is a schematic diagram illustrating the cross-sectional structure of a medium-voltage MOS (metal oxide semiconductor) transistor related to another specific example. [Figure 3] This is a schematic diagram showing one step in the manufacturing process of a medium-voltage MOS transistor. [Figure 4] This is a schematic diagram showing one step in the manufacturing process of a medium-voltage MOS transistor. [Figure 5] This is a schematic diagram showing one step in the manufacturing process of a medium-voltage MOS transistor. [Figure 6] This is a schematic diagram showing one step in the manufacturing process of a medium-voltage MOS transistor. [Figure 7] This is a schematic diagram showing one step in the manufacturing process of a medium-voltage MOS transistor. [Figure 8] This graph shows the relationship between the amount of misalignment and the off-current ratio. [Figure 9] This is a schematic diagram showing the intensity distribution of interband tunneling current. [Figure 10] This graph shows the intensity of interband tunneling current. [Figure 11] This is a graph showing the LDD concentration ratio. [Modes for carrying out the invention]

[0010] One embodiment of the present invention will be described below with reference to the attached drawings.

[0011] Figure 1 schematically shows a cross-sectional structure of a semiconductor device according to an embodiment of the present invention, that is, a medium-voltage MOS (metal-oxide semiconductor) transistor 11. The MOS transistor 11 is, for example, a medium-voltage MOS transistor that operates at a relatively high power supply voltage of 6V to 8V and is mounted on a platform of a display driver IC. Hereinafter, the MOS transistor 11 will be described as an n-channel type MOS transistor.

[0012] The MOS transistor 11 is provided in a well 14 formed on the surface of a substrate 12. The substrate 12 is, for example, a silicon wafer. The well 14 is, for example, silicon doped with a p-type impurity boron (B).

[0013] A shallow trench isolation (STI) 13 is an insulating region for insulating adjacent elements. The STI 13 is provided so as to surround a source region 21, a drain region 22, first LDD regions 23a and 23b, second LDD regions 24a and 24b, and a gate insulating film 16. The STI 13 is formed of, for example, a silicon oxide film.

[0014] A gate insulating film 16 and a gate electrode 15 are formed on the surface of the well 14. The gate electrode 15 is formed of, for example, polysilicon. The polysilicon is doped with an n-type impurity phosphorus (P) or arsenic (As). The gate electrode 15 may be formed of a laminated structure of a metal layer, a metal silicide layer, a polysilicon layer, and a metal layer or a metal silicide layer.

[0015] The gate insulating film 16 is formed of, for example, a silicon oxide film. For example, the gate electrode 15 and the gate insulating film 16 form a flush side surface. The side surfaces of the gate electrode 15 and the gate insulating film 16 are covered with sidewall spacers 17. The sidewall spacers 17 are formed of, for example, a silicon oxide film or a silicon nitride film.

[0016] On the surface of the well 14, a source region 21 and a drain region 22 are formed, separated by the channel region 18 (well 14) below the gate electrode 15. The source region 21 and drain region 22 are doped with n-type impurities such as phosphorus and arsenic. The channel region 18 is provided on the surface of the well 14 below the gate electrode 15 and is a region doped with, for example, a p-type impurity such as boron to adjust the threshold voltage of the MOS transistor 11. The channel region 18 is separated from the gate electrode 15 by a gate insulating film 16.

[0017] A pair of first LDD regions 23a and 23b are formed on the surface of well 14, separated by the channel region 18 (well 14) below the gate electrode 15. Each of the first LDD regions 23a and 23b is connected to the source region 21 and the drain region 22, respectively. The first LDD regions 23a and 23b are doped with the n-type impurity phosphorus. The first LDD regions 23a and 23b extend from the surface of well 14 into well 14 and from the surface of well 14 to the junction with well 14. The first LDD regions 23a and 23b form a PN junction with well 14, and the distance in the vertical depth direction of this junction is defined as the depth Df of the first LDD regions 23a and 23b. If the film thickness of the gate electrode 15 is Tg, then Df > Tg.

[0018] On the surface of the well 14, a pair of second LDD regions 24a and 24b are formed below the gate electrode 15, separated by the channel region 18 (well 14). The positions of the second LDD regions 24a and 24b are determined by setting an overlap dimension OL. The set overlap dimension OL is the dimension by which the orthographic projection of the gate electrode 15 on the surface of the substrate 12 overlaps with the second LDD regions 24a and 24b on either side of it. The overlap dimension OL is set equally for the two second LDD regions 24a and 24b. Since the second LDD regions 24a and 24b are formed self-aligned with respect to the gate electrode 15, they are formed so that the overlap dimension OL between the second LDD region 24a and the gate electrode 15 is equal to the overlap dimension OL between the second LDD region 24b and the gate electrode 15. In the following description, the overlap between the orthographic projection of the gate electrode 15 on the surface of the substrate 12 and the LDD region may also be described as the overlap between the gate electrode 15 and the LDD region. The second LDD regions 24a and 24b are connected to their respective first LDD regions 23a and 23b. The second LDD regions 24a and 24b are doped with n-type impurities such as phosphorus and arsenic. The second LDD regions 24a and 24b extend from the surface of well 14 into well 14 and from the surface of well 14 to the junction with well 14. The second LDD regions 24a and 24b form a PN junction with well 14, and the distance in the vertical depth direction of this junction is defined as the depth Ds of the second LDD regions 24a and 24b. If the film thickness of the gate electrode 15 is Tg, then Ds <Tgとなっている。

[0019] The pair of first LDD regions 23a and 23b are formed before the gate electrode 15 is formed, and their overlap with the gate electrode 15 is greater than the overlapping dimension OL. In other words, the distance of the well 14 separating the pair of first LDD regions 23a and 23b is smaller than the distance of the well 14 separating the pair of second LDD regions 24a and 24b. That is, the distance between the first LDD region 23a and the first LDD region 23b is smaller than the distance between the second LDD region 24a and the second LDD region 24b. The first LDD regions 23a and 23b, with their large overlap with the gate electrode 15 and a depth Df greater than the film thickness Tg of the gate electrode 15, can sufficiently mitigate the electric field between the drain region 22 and the channel region 18.

[0020] The depths of the source region 21 and the drain region 22 are greater than the depth Df of the pair of first LDD regions 23a and 23b. The depth Df of the pair of first LDD regions 23a and 23b is greater than the depth Ds of the pair of second LDD regions 24a and 24b.

[0021] As shown in Figure 2, in the MOS transistor 11, the position of the gate electrode 15 may shift relative to the positions of the first LDD regions 23a and 23b due to misalignment between the photolithography process for forming the pair of first LDD regions 23a and 23b and the photolithography process for forming the gate electrode 15. In the MOS transistor 11, even in this case, the positional relationship of the gate electrode 15 with respect to the two second LDD regions 24a and 24b, the source region 21, and the drain region 22 is maintained constant. Since the second LDD regions 24a and 24b are formed self-aligned with respect to the gate electrode 15, the overlap dimension OL between the second LDD region 24a and the gate electrode 15 is equal to the overlap dimension OL between the second LDD region 24b and the gate electrode 15. Since the source region 21 and the drain region 22 are formed in a self-aligned manner with respect to the gate electrode 15 and the sidewall spacer 17, the distance between the source region 21 and the side of the gate electrode 15 on the source region 21 side is equal to the distance between the drain region 22 and the side of the gate electrode 15 on the drain region 22 side.

[0022] As described above, the first LDD regions 23a and 23b, which have a large overlap with the gate electrode 15 and a depth Df greater than the film thickness Tg of the gate electrode 15, sufficiently relax the electric field between the drain region 22 and the channel region 18. However, if the position of the gate electrode 15 shifts relative to the positions of the first LDD regions 23a and 23b, and the first LDD region 23b on the drain region 22 side does not overlap with the gate electrode 15, or if the overlap amount becomes small, the LDD ion concentration in the GIDL (Gate Induced Drain Leakage) generation region decreases significantly, and the effect of relaxing the electric field between the drain region 22 and the channel region 18 is not sufficiently obtained.

[0023] The second LDD regions 24a and 24b are formed overlapping the gate electrode 15 with a predetermined overlap dimension OL. The second LDD regions 24a and 24b are formed on the surface of the well 14 directly below the boundary between the gate electrode 15 and the sidewall spacer 17, which is the GIDL generation region, thereby suppressing GIDL. Even if the depth Ds of the second LDD regions 24a and 24b is smaller than the film thickness Tg of the gate electrode 15, the electric field in the GIDL generation region can be relaxed. Since the depth Ds of the second LDD regions 24a and 24b is smaller than the film thickness Tg of the gate electrode 15, even if ions are implanted into the gate electrode 15 in a self-aligned manner, the ions implanted in the formation of the second LDD regions 24a and 24b do not penetrate the gate electrode 15. No n-type impurities enter the channel region 18 between the source region 21 and the drain region 22, and there is no effect on the characteristics of the MOS transistor 11, such as the threshold voltage. The channel region 18 does not contain the ions contained in the second LDD regions 24a and 24b. Furthermore, since the first LDD regions 23a and 23b are formed before the gate electrode 15 is formed, the channel region 18 does not contain ions contained in the first LDD regions 23a and 23b.

[0024] Next, the manufacturing method of the MOS transistor 11 will be described. As shown in Figure 3, the STI 13 is formed on the substrate 12. A p-type silicon wafer is used for the substrate 12. P-type ions such as boron (B) are implanted into the substrate 12, annealing is performed, and wells 14 are formed.

[0025] As shown in Figure 4, first LDD regions 23a and 23b are formed on the substrate 12 prior to the formation of the gate electrode 15. An oxide film 32 is formed on the substrate 12 on which the STI 13 and well 14 are formed. For example, the oxide film 32 becomes the gate insulating film 16. The thickness of the oxide film 32 is, for example, 18 [nm]. A photoresist is coated and patterned on the oxide film 32. For each individual MOS transistor 11, a photoresist pattern 31 is formed that covers the area where the pair of first LDD regions 23a and 23b are not formed. In forming the first LDD regions 23a and 23b, n-type ions such as phosphorus are implanted by ion implantation using the photoresist pattern 31 as a mask. The implantation energy is set to, for example, 70 [keV]. The dose is, for example, 2.0E13 [ / cm]. 2 The ion implantation is set to 1.0E13[ / cm²]. Ions are implanted at an incidence angle α of 40° with respect to the vertical by oblique ion implantation. The ion implantation conditions are set to conditions that enable the formation of first LDD regions 23a and 23b in the MOS transistor 11, which can relax the electric field between the drain region 22 and the channel region 18 and reduce impact ionization. The implanted ion is preferably phosphorus. The implantation energy is preferably 50[keV] to 90[keV]. The dose is 1.0E13[ / cm²]. 2 ]~3.0E13[ / cm 2 ] is preferable. In order to relax the electric field between the drain region 22 and the channel region 18 and reduce impact ionization, the depth Df of the first LDD regions 23a and 23b is preferably 200 nm to 300 nm, and the concentration is 1.0E18 [ / cm³]. 3 ]~1.0E19[ / cm 3] is preferred. The preferred depth Df is greater than the film thickness Tg of the gate electrode 15, which will be described later. The pair of first LDD regions 23a and 23b are separated from each other by the well 14 at the bottom of the photoresist pattern 31.

[0026] As shown in Figure 5, on the substrate 12, for each individual MOS transistor 11, a gate insulating film 16 and a gate electrode 15 are formed on the well 14 between the first LDD regions 23a and 23b. For the formation of the gate electrode 15, a high-concentration n-type polysilicon film is formed on the oxide film 32 from which the photoresist pattern 31 has been removed. The thickness of the polysilicon film is set to be equal to the thickness of the gate electrode 15. Here, the thickness of the polysilicon film is set to, for example, 100 [nm]. Patterning of the gate electrode 15 and the gate insulating film 16 is performed by photolithography and etching processes. The thickness Tg of the gate electrode 15 is smaller than the depth Df of the first LDD regions 23a and 23b. Here, for example, the misalignment between the photolithography process for forming the photoresist pattern 31 and the photolithography process for forming the gate electrode 15 is kept within a predetermined control range. However, due to this misalignment, the overlap amount between the gate electrode 15 and the first LDD region 23a may differ from the overlap amount between the gate electrode 15 and the first LDD region 23b.

[0027] As shown in Figure 6, second LDD regions 24a and 24b are formed on the substrate 12. The second LDD regions 24a and 24b correspond to the first LDD regions 23a and 23b, respectively. In forming the second LDD regions 24a and 24b, n-type ions such as phosphorus and arsenic are implanted by self-alignment ion implantation using the gate electrode 15 as a mask. The implantation energy is set to, for example, 20 [keV]. The dose is, for example, 1.0E13 [ / cm²]. 2It is set to . It is implanted at an incident angle β of 30° with respect to the vertical direction by oblique ion implantation. The conditions for ion implantation are set to conditions that can form the second LDD regions 24a and 24b that can secure the LDD ion concentration in the GIDL generation region and relax the electric field between the drain region 22 and the channel region 18 in the MOS transistor 11. Phosphorus is preferable as the implanted ion. The implantation energy is preferably 10 [keV] to 30 [keV]. The dose amount is preferably 5.0E12 [ / cm 2 to 2.0E13 [ / cm 2 . In order to secure the LDD ion concentration in the GIDL generation region, the depth Ds of the second LDD regions 24a and 24b is preferably 40 [nm] to 80 [nm], and the concentration is 1.0E18 [ / cm 3 to 5.0E18 [ / cm 3 . The preferable depth Ds is smaller than the film thickness Tg of the gate electrode 15. The pair of second LDD regions 24a and 24b are separated from each other by the well 14 below the gate electrode 15. Since the second LDD regions 24a and 24b are formed self-aligned with respect to the gate electrode 15, they individually overlap the gate electrode 15 with a determined predetermined overlap dimension OL.

[0028] As shown in FIG. 7, a source region 21 and a drain region 22 are formed on the substrate 12. An insulating film such as a silicon oxide film is formed entirely on the substrate 12 on which the second LDD regions 24a and 24b are formed, and the insulating film is etched by anisotropic etching to form sidewall spacers 17 along the sides of the gate electrode 15 and the gate insulating film 16. N-type ions such as phosphorus and arsenic are implanted by self-aligned ion implantation using the gate electrode 15 and the sidewall spacers 17 as masks. The implantation energy is set to, for example, 20 [keV]. The dose amount is, for example, 5.0E15 [ / cm 2The source region 21 and drain region 22 are formed deeper than the depth Df of the first LDD regions 23a and 23b by simultaneously controlling the injected energy and dose. The source region 21 and drain region 22 are separated from the channel region 18 by a sidewall spacer 17. The first LDD regions 23a, 23b and the second LDD regions 24a and 24b are provided below the sidewall spacer 17 between the source region 21 and drain region 22 and the channel region 18. Since the source region 21 and drain region 22 are formed self-aligned with the sidewall spacer 17, they overlap with the sidewall spacer 17 by a predetermined overlap dimension. The first LDD regions 23a, 23b and the second LDD regions 24a and 24b are connected to the source region 21 and drain region 22 for each individual MOS transistor 11.

[0029] The characteristics of the MOS transistor 11 were verified by simulation. For the verification, a simulation model was used in accordance with this embodiment. As a comparative example, a simulation model in which the second LDD regions 24a and 24b were omitted was used. Figure 8 shows the relationship between the amount of misalignment of the first LDD regions 23a and 23b relative to the gate electrode and the off-current of the MOS transistor 11. The horizontal axis represents the dimension of the misalignment. The positive side represents the case where the first LDD regions 23a and 23b are shifted towards the drain region 22 relative to the gate electrode 15, as shown by the misalignment amount Sf in Figure 2, while the negative side represents the case where the first LDD regions 23a and 23b are shifted towards the source region 21 relative to the gate electrode 15. The vertical axis represents the off-current of the MOS transistor 11. The off-current is a value normalized to 1, where the current value is 1 when the misalignment amount Sf is zero. As shown in Figure 8, when the first LDD regions 23a and 23b are shifted toward the drain region 22 relative to the gate electrode 15, a tendency for the off-current to increase is observed. However, in this embodiment, the effect of the shift amount on the off-current is smaller compared to the comparative example. With a positional shift of 0.08 [μm] Sf, the off-current ratio in this embodiment was suppressed to about 1 / 10 of the off-current ratio in the comparative example. In the comparative example, the overlap amount between the first LDD region 23b and the gate electrode 15 decreased, and the off-current increased due to the electric field between the drain region 22 and the channel region 18. In contrast, in this embodiment, it is considered that the electric field between the drain region 22 and the channel region 18 is mitigated by the second LDD region 24b, thereby reducing the off-current.

[0030] Figure 9 shows the simulation results of the intensity distribution of interband tunneling current. Figure 10 shows a graph showing the intensity of interband tunneling current. Interband tunneling current causes GIDL. In both this embodiment and the comparative example, the displacement amount Sf was set to 0.08 [μm]. As shown in Figure 9, in this embodiment, the region where interband tunneling current occurs (light gray area) is significantly reduced compared to the comparative example. As shown in Figure 10, in this embodiment, the intensity of interband tunneling current is also reduced compared to the comparative example.

[0031] Figure 11 shows the simulation results of the LDD ion concentrations in the first LDD region 23a (23b), the second LDD region 24a (24b), and the source region 21 (or drain region 22) on the surface of the well 14. The LDD concentrations with respect to the lateral position on the surface of the well 14 are shown for the case where the misalignment amount Sf is zero in this embodiment, when the misalignment is in the direction that decreases the overlap dimension OL in this embodiment, when the misalignment amount Sf is zero in the comparative example, and when the misalignment is in the direction that decreases the overlap dimension OL in the comparative example. The LDD concentration is shown as a value normalized with the ion concentration in the source region 21 (or drain region 22) set to 1. As shown in Figure 11, the LDD concentration decreases as you move from the source region 21 (or drain region 22) towards the gate electrode 15. In the comparative example, the second LDD region 24a (24b) is omitted, so the LDD concentration is smaller than in this embodiment, but the decrease in LDD concentration is particularly significant when there is misalignment in the comparative example compared to when there is no misalignment. In this embodiment, it was confirmed that changes in the LDD concentration ratio are suppressed even when there is misalignment. The region on the surface of the well 14 directly below the boundary between the gate electrode 15 and the sidewall spacer 17 is the GIDL generation region, and it is necessary to increase the LDD concentration to suppress GIDL. In this embodiment, whether or not there is misalignment, the LDD concentration in the GIDL generation region is kept high at 1 / 3 or more of the ion concentration in the source region 21 (or drain region 22), and the effect of the second LDD region 24a (24b) was confirmed. [Explanation of Symbols]

[0032] 11 Medium-voltage MOS transistors 14 wells 15 Gate Shuttle 16 Gate insulating film 21 Source Area 22 Drain region 23a 1st LDD area 23b 1st LDD area 24a 2nd LDD area 24b 2nd LDD area Df (depth of the first LDD region) Ds (depth of the second LDD region) OL overlap dimensions Tg (gate electrode film thickness)

Claims

1. A step of forming a mask pattern on wells provided on a substrate, implanting ions into the wells with the mask pattern as a mask, and forming a pair of first LDD regions separated by the wells, A step of forming a gate insulating film and a gate electrode on the well between the pair of first LDD regions, A step of implanting ions into the first LDD region using the gate electrode as a mask to form a pair of second LDD regions separated by the well, wherein the orthographic projection of the gate electrode on the surface of the substrate and the pair of second LDD regions on both sides of it overlap by a predetermined dimension, The process involves forming a sidewall on the side wall of the gate electrode, implanting ions into the second LDD region using the gate electrode and the sidewall as a mask, and forming a source region and a drain region. A method for manufacturing MOS transistors.

2. A pair of first LDD regions, separated by a well provided in the substrate below the gate electrode and connected to the source region and drain region respectively, having a depth greater than the film thickness of the gate electrode, A pair of second LDD regions separated by the well below the gate electrode, wherein the orthographic projection of the gate electrode on the surface of the substrate and the pair of second LDD regions on both sides of it overlap by a predetermined dimension, and the pair of second LDD regions are individually connected to the corresponding first LDD region and have a depth smaller than the film thickness of the gate electrode. A MOS transistor equipped with the following features.

3. The well between the pair of first LDD regions does not contain ions contained in the first LDD region and the second LDD region. The MOS transistor according to claim 2.

4. The distance between the wells separating the pair of first LDD regions is smaller than the distance between the wells separating the pair of second LDD regions. The MOS transistor according to claim 2.

5. The depths of the source region and the drain region are greater than the depths of the pair of first LDD regions. A MOS transistor according to any one of claims 2 to 4.

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