Memory mapping method and related devices

Abstract

A memory mapping method and related device are provided. The memory mapping method includes the steps of: acquiring a memory fault row address of a first memory; acquiring an address mapping table by a match and search circuit, the address mapping table including a mapping relationship between the memory fault row address and a memory remapping row address corresponding to the memory fault row address; and, if the access target of the first memory is the memory fault row address, acquiring a memory remapping row address to which the memory fault row address is mapped based on the address mapping table, wherein the memory area indicated by the memory remapping row address is within a reserved space of the first memory. The match and search circuit can be integrated into any address command output circuit or driver circuit in the memory access path of the first memory, so that users can customize the integration location and the amount of redundant resources used for replacement to perform multiple reversible replacements based on the address mapping table, thereby significantly reducing the memory failure rate and improving memory reliability.

Description

Technical Field

[0001] This application claims the priority of Chinese Patent Application No. 202211521408.4, titled "Method for Multiple Row Replacements of DRAM", filed with the China National Intellectual Property Administration on November 30, 2022, and Chinese Patent Application No. 202211691518.5, titled "Memory Mapping Method and Related Devices", filed with the China National Intellectual Property Administration on December 27, 2022, and both are incorporated herein by reference in their entirety.

[0002] Embodiments of this application relate to the field of computers, and more particularly, to memory mapping methods and related devices.

Background Art

[0003] With the development of services such as high-performance computing, big data analysis, and in-memory databases, applications have increasingly urgent requirements regarding memory capacity and bandwidth.

[0004] Under the continuous progress of requirements regarding memory capacity density and bandwidth performance, the memory manufacturing process has been continuously scaled down, and the interface speed has been continuously increasing. Also, with the advancement of the manufacturing process, the probability of memory errors and the memory defect rate have gradually increased, posing a great risk to the reliability of the memory. Therefore, it is necessary to detect memory errors, and the detected memory faulty rows are replaced. For example, current memory device manufacturers set a replacement function in the memory device.

[0005] However, the setting of the replacement function in the memory device presets the redundant space used for replacement, and the redundant space cannot be changed. As a result, the number of memory exchanges is limited, accompanied by a loss of specific service performance, and the current memory failure requirements cannot be met.

Summary of the Invention

Means for Solving the Problems

[0006] Embodiments of this application provide a memory mapping method for flexibly defining the amount of redundant resources used for the integration and substitution of an address mapping table, and for performing multiple reversible substitutions of memory fault rows based on the address mapping table, thereby avoiding service performance loss, significantly reducing the memory failure rate, and improving memory reliability. Embodiments of this application further provide corresponding memory mapping circuits, computing devices, computer-readable storage media, chip systems, computer program products, and the like.

[0007] A first aspect of this application provides a memory mapping method. The method includes the steps of: obtaining the memory fault row address of a first memory (the first memory being, for example, a memory module, specifically one of a Rambus in-line memory module (RIMM), a single in-line memory module (SIMM), or a dual in-line memory module (DIMM)); obtaining an address mapping table by a matching and search circuit, wherein the address mapping table includes a mapping relationship between a memory fault row address and a memory remapping row address corresponding to the memory fault row address; and, if the access target of the first memory is a memory fault row address, obtaining a memory remapping row address to which the memory fault row address is mapped based on the address mapping table, wherein the memory region indicated by the memory remapping row address is within the reserved space of the first memory, and the matching and search circuit is integrated into an address command output circuit or drive circuit in the memory access path of the first memory.

[0008] In this application, an example is used in which the memory mapping method is performed by a computing device. To perform memory mapping, the lookup and search circuit must first be enabled to obtain an address mapping table, and the lookup and search circuit is integrated into an address command output circuit or drive circuit in the memory access path of the first memory. Specifically, the lookup and search circuit is integrated into any address command output circuit or drive circuit between the address mapping module of the memory controller and the memory chip. The memory access path of the first memory may be understood as the path for the memory controller in the processor of the computing device to access the memory chip in the first memory.

[0009] The memory region indicated by the memory remapping row address in this application lies within the reserved space of the first memory. The reserved space of the first memory may be derived from the user memory chip / device capacity within the first memory; in other words, the reserved space is visible to the user and must be reserved by using additional software methods. In addition, the reserved space may alternatively be derived from redundant space designed by the memory manufacturer beyond the nominal capacity of the first memory. The reserved space is beyond the addressing range of the memory controller and is invisible to the user.

[0010] The first memory in this application is mounted on a computing device, which may be any computer device, server, or storage device that uses memory.

[0011] In this application, the memory mapping method may be performed in the first memory production phase, the computing device startup phase, and the computing device execution phase. After the address mapping table is generated, memory addresses may be replaced based on the address mapping table.

[0012] One way to solve the problem of memory row address failures is for the memory device manufacturer to configure an address substitution function in the memory device; that is, to set up a mapping table for each memory device and, if the accessed memory address is a faulty address, to substitute the faulty address in the memory device with a new memory address based on the mapping table. However, since the devices are packaged by the memory manufacturer, the address substitution function configured in the memory device can only be pre-configured by the memory manufacturer, and the memory user cannot change the address substitution function, limiting the number of memory substitutions. Furthermore, because the substitution function is configured for each memory device, a degradation in memory performance becomes apparent.

[0013] In this application, the matching and search circuits are integrated into the address command output circuit or drive circuit within the memory access path of the first memory, and all of these circuits (for example, the matching and search circuits are located within the memory controller or register clock driver) are external to the device and can be controlled by the user. When a processing chip in the computing device (e.g., CPU, GPU, or NPU) accesses the memory, an access request from the mainboard's memory interface reaches the memory. The access request address then passes through the matching and search circuit, which replaces the faulty address. Finally, based on the replaced access address, the access request enters each memory device to perform data access.

[0014] Based on the solution provided in this application, it can be seen that each matching and search circuit is connected to multiple devices. Therefore, by setting up an address mapping table in only one matching and search circuit, multiple operating targets (devices) can be represented, and the repeated setting of the replacement function for each device can be avoided. In addition, since the matching and search circuit is a circuit that can be edited by the user, the user can also customize the size of the address mapping table that can be stored in the matching and search circuit. A larger address mapping table may replace more fault rows at memory addresses, and it is also possible to replace fault rows at memory addresses multiple times. Furthermore, since the matching and search circuit can be customized by the user, the replacement granularity can be expanded in this application, in other words, multiple devices can be used as a whole for replacement. When a fault row is detected in a single device, a replacement signal is sent simultaneously to the matching and search circuit (e.g., multiple devices positioned at the same rank) using the same memory address, causing fault row replacement in multiple devices. The advantage is that instead of each device corresponding to one record in the mapping table, one record in the mapping table is used together by multiple devices, thereby reducing the amount of data in the mapping table and saving the memory space that would otherwise need to be occupied by the mapping table. Furthermore, the memory region indicated by the memory remapping row address in this application lies within the reserved space of the first memory, in other words, the reserved space is visible to the user and may be managed by the user, and the user may need to independently determine the size of the reserved space. For example, if memory row failures occur infrequently, a small space is reserved. As the memory ages, its reliability gradually decreases, and a larger space is reserved. Thus, the solution in this application can improve memory utilization.

[0015] In the first embodiment, the memory fault row address of the first memory is obtained, and an address mapping table is obtained in the matching and search circuit. The address mapping table includes mapping relationships between the memory fault row address and the memory remapping row address corresponding to the memory fault row address. If the target of access in the first memory is the memory fault row address, the memory remapping row address to which the memory fault row address is mapped is obtained based on the address mapping table, and the memory region indicated by the memory remapping row address is in the reserved space of the first memory. Since the matching and search circuit can be integrated into any address command output circuit or drive circuit in the memory access path of the first memory, the user may customize the integration location and the amount of redundant resources used for substitution to perform multiple reversible substitutions based on the address mapping table, thereby significantly reducing the memory failure rate and improving memory reliability.

[0016] In a possible implementation of the first embodiment, the method further includes the steps of: obtaining a memory access address from outside the first memory; using the obtained memory access address, performing a match against the memory access address based on an address mapping table; and, if the memory access address matches a memory fault row address, translating the access to the memory access address to an access to a memory remapping row address.

[0017] In this possible implementation, after obtaining the address mapping table, the matching and search circuits may perform matching against memory access addresses based on the address mapping table. If the memory access address matches the memory fault row address in the address mapping table, the memory fault row address is remapped to the corresponding memory remapping row address, and finally the memory remapping row address is accessed to complete the replacement of the faulty memory address, thereby improving the feasibility of the solution.

[0018] In a possible implementation of the first embodiment, the first memory comprises a plurality of memory chips, and the matching and search circuit uses the plurality of memory chips collectively for row address translation. The aforementioned step of obtaining a memory remapping row address to which a memory fault row address is mapped, based on an address mapping table, specifically includes the step of translating row addresses in the plurality of memory chips to memory remapping row addresses based on an address mapping table, in the event that a fault row occurs in a single memory chip, wherein the translated row includes the fault row.

[0019] In this possible implementation, the first memory comprises one or more memory channels, and one or more dual in-line memory modules (DIMMs) may be inserted into one memory channel, and one DIMM may comprise one or more memory ranks. One rank comprises multiple memory chips (memory devices, chips), and the matching and search circuitry uses multiple memory chips as a whole for row address translation. If a faulty row occurs in a single memory chip, the matching and search circuitry is configured to translate row addresses in multiple memory chips to memory remapping row addresses based on the address mapping table, and the translated rows include the faulty row; in other words, the address mapping table operates on each chip. For example, if address A is matched in the address mapping table, the matching and search circuitry replaces address A in all chips, reducing the amount of data in the mapping table and saving the storage space that would otherwise be occupied by the mapping table.

[0020] In a possible implementation of the first embodiment, each of the plurality of memory chips includes a plurality of memory banks, and the reserved space of the first memory includes at least one row of storage units in each of the plurality of memory banks.

[0021] In this possible embodiment, a single chip includes multiple memory banks or multiple memory bank groups. A bank is an array containing multiple storage units. Rows of storage units within a bank may be represented by rows. The reserved space of a first memory includes at least one row of storage units within each bank; in other words, at least one row of storage units within each bank is used as reserved space, and as a result, the user can customize a larger reserved space to perform multiple reversible substitutions based on the address mapping table. When memory row failures occur infrequently, a small space is reserved. As memory ages, reliability gradually decreases, a larger space is reserved, and memory utilization improves.

[0022] In a possible implementation of the first embodiment, the address mapping table is stored in volatile memory within a lookup and search circuit, and the method further includes the steps of: writing the address mapping table from the lookup and search circuit to a first storage device before the first memory stops operating, the first storage device being non-volatile memory located within a computing device; and loading the address mapping table in the first storage device into the lookup and search circuit after the first memory has started functioning.

[0023] In this possible implementation, the address mapping table is stored in volatile memory within the lookup and search circuitry. Therefore, the address mapping table must be written to a first storage device in non-volatile memory for persistent storage. For example, during the execution phase of a computing device, the address mapping table is written from the lookup and search circuitry to the first storage device before the first memory stops operating, and after the first memory starts operating, the address mapping table in the first storage device is loaded into the lookup and search circuitry to avoid the problem of address mapping table loss.

[0024] In a possible implementation of the first aspect, in the startup process of a computing device equipped with a first memory, the method further includes the steps of reading an address mapping table from a first storage device and updating the address mapping table via the memory self-check of the computing device.

[0025] In this possible implementation, the permanently stored address mapping table may be read in the startup process of the computing device, and the address mapping table is updated based on the memory self-check function of the computing device, timely detecting faulty rows in the memory and timely replacing the faulty rows, thereby improving the reliability of the memory.

[0026] In a possible implementation of the first aspect, the volatile memory in the collation and search circuit is an associative memory, a ternary associative memory, or a fully associative cache.

[0027] In this possible implementation, the volatile memory in the collation and search circuit may specifically be any one of an associative memory, a ternary associative memory, or a fully associative cache in order to improve the feasibility of the solution.

[0028] In a possible implementation of the first aspect, the address mapping table is stored in the non-volatile memory in the collation and search circuit.

[0029] In this possible implementation, the address mapping table is stored in the non-volatile memory in the collation and search circuit. As a result, the address mapping table in the collation and search circuit can be permanently stored, thereby avoiding the problem of address mapping table loss.

[0030] In a possible implementation of the first embodiment, the aforementioned step of obtaining an address mapping table by a matching and search circuit includes, when a computing device equipped with the first memory is started, the step of generating an address mapping table and the step of synchronizing the address mapping table with the matching and search circuit before the computing device uses the first memory.

[0031] In this possible implementation, during the computing device startup phase, the address mapping table may be generated by self-checking, and before the computing device uses the first memory, the address mapping table is synchronized with the matching and lookup circuitry, avoiding the memory data movement problems that exist when synchronizing entries after the computing device has used the first memory.

[0032] In a possible implementation of the first aspect, the aforementioned step of obtaining the memory fault row address of the first memory includes: obtaining a first memory failure log of the first memory; extracting first memory failure characteristics from the first memory failure log; and performing a prediction based on the first memory failure characteristics in order to obtain the memory fault row address of the first memory.

[0033] In this possible implementation, during the execution phase of the computing device, out-of-band or in-band memory error information is aggregated for an offline training node to perform parameter training on a memory failure prediction model. The algorithms and models acquired through training may be used for online inference and real-time prediction of memory failure development trends, and the address mapping table is updated at the right time to reduce or even avoid the occurrence of uncorrectable errors.

[0034] In a possible implementation of the first aspect, the method further includes the steps of: performing an access test on a memory fault row address to determine whether the memory fault row address is an actual fault row address; and, if the memory fault row is not an actual fault row address, releasing the memory fault row address and the memory remapping row address corresponding to the memory fault row address from the address mapping table.

[0035] In this possible implementation, during the idle state of the computing device execution phase, the memory fault row address may be re-predicted using a memory failure prediction model to determine whether the previously predicted memory fault row address is the actual fault row address. If the memory fault row address is not the actual fault row address, the memory fault row address and the memory remapping row address corresponding to the memory fault row address are released from the address mapping table, saving redundant and reserved space in the matching and search circuits, enabling the system to have reversible isolation and release capabilities, reducing the requirements for prediction accuracy, and improving the reach of failure prediction.

[0036] In a possible implementation of the first aspect, the method further includes the step of sending a first command, the first command being used to enable the cessation of obtaining the memory fault row address of a first memory.

[0037] In this possible implementation, the enable switch may be set during the computing device startup phase. When the second command is sent, the enable switch is turned on, a self-check is initiated, and the acquisition of the memory fault row address of the first memory is enabled. If the memory is found to have failed, a replacement is performed in a timely manner. When the first command is sent, the enable switch is turned off, the self-check is disabled, and the acquisition of the memory fault row address of the first memory is stopped, in order to achieve the objective of quickly starting the computing device.

[0038] In a possible implementation of the first embodiment, the matching and search circuits are integrated into the memory controller or register clock driver within the address command output circuit or drive circuit.

[0039] In this possible implementation, the matching and search circuits are specifically integrated into the memory controller within the processor or the register clock driver within the rank to improve the feasibility of the solution.

[0040] A second aspect of this application provides a memory mapping circuit configured to perform a method according to the first aspect or one of the possible implementations of the first aspect. Specifically, the memory mapping circuit includes a circuit, module, or unit configured to perform a method according to the first aspect or one of the possible implementations of the first aspect, such as an acquisition circuit, a matching and search circuit, a read / write circuit, a generate circuit, a release circuit, and a transmit circuit.

[0041] A third aspect of this application provides a computing device, the computing device comprising a mainboard, a processor, memory, and a memory mapping circuit in any one of the second aspect or a possible implementation of the second aspect.

[0042] The mainboard is configured to perform memory fault row detection and send the memory fault row address to the memory mapping circuit. The memory mapping circuit is integrated into the processor or memory, and the memory is used as the primary memory for performing memory fault row address mapping.

[0043] A fourth aspect of this application provides a computer-readable storage medium for storing one or more computer-executable instructions. When the computer-executable instructions are executed by a processor, the processor performs a method according to the first aspect or any possible implementation of the first aspect.

[0044] A fifth aspect of this application provides a computer program product that stores one or more computer executable instructions. When the computer executable instructions are executed by a processor, the processor performs a method according to the first aspect or any possible implementation of the first aspect.

[0045] A chip system is provided according to a sixth aspect of this application. The chip system includes at least one processor and an interface. The interface is configured to receive data and / or signals. The at least one processor is configured to support a computer device in realizing a function according to the first aspect or any one of the possible implementations of the first aspect. In a possible design, the chip system may further include a storage device. The storage device is configured to store program instructions and data required by the computer device. The chip system may include a chip, or it may include a chip and other separate components.

[0046] In the embodiments of this application, the memory fault row address of the first memory is obtained, and an address mapping table is obtained by the matching and search circuit. The address mapping table includes mapping relationships between the memory fault row address and the memory remapping row address corresponding to the memory fault row address. If the access target of the first memory is the memory fault row address, the memory remapping row address to which the memory fault row address is mapped is obtained based on the address mapping table. The memory region indicated by the memory remapping row address is within the reserved space of the first memory. Since the matching and search circuit can be integrated into any address command output circuit or drive circuit in the memory access path of the first memory, the user may customize the integration location and the amount of redundant resources used for substitution to perform multiple reversible substitutions based on the address mapping table, thereby significantly reducing the memory failure rate and improving memory reliability. [Brief explanation of the drawing]

[0047] [Figure 1] This is a diagram of a computer system architecture. [Figure 2] This is a diagram illustrating one embodiment of a memory mapping method according to one embodiment of this application. [Figure 3] This is a schematic flowchart of the first memory production phase according to one embodiment of the present application. [Figure 4] This is a schematic flowchart of the computing device startup phase according to one embodiment of this application. [Figure 5] This is a schematic flowchart of the computing device execution phase according to one embodiment of this application. [Figure 6] This is a diagram of the application architecture of a memory mapping method according to one embodiment of this application. [Figure 7] This is a diagram of one embodiment of a bidirectional lookup table according to one embodiment of the present application. [Figure 8] This is a diagram illustrating the architecture of an address mapping table set within a memory controller according to one embodiment of this application. [Figure 9] This is a diagram illustrating the architecture of an address mapping table set in a register clock driver according to one embodiment of this application. [Figure 10] This is a diagram of one embodiment of a memory mapping circuit according to one embodiment of this application. [Figure 11] This is a diagram of one embodiment of a computing device according to one embodiment of the present application. [Modes for carrying out the invention]

[0048] The embodiments of this application will be described below with reference to the attached drawings. It will be apparent that the embodiments described are not all, but only a part, of the embodiments of this application. Those skilled in the art will know that with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0049] In the specification, claims, and accompanying drawings of this application, terms such as “first” and “second” are intended to distinguish similar subjects, but do not necessarily indicate a specific order or sequence. The data used in this manner are interchangeable in appropriate contexts, and it should be understood that the embodiments described herein may be carried out in an order other than that illustrated or described herein. In addition, the terms “includes” and “has,” and any other variations thereof, are intended to include non-exclusive inclusions. For example, a process, method, system, product, or device comprising a series of steps or units is not necessarily limited to the steps or units explicitly listed, and may include other steps or units not explicitly listed or specific to the process, method, product, or device.

[0050] In this specification, the specific term “example” means “used as an example, embodiment, or illustration.” Embodiments described as “example” in this specification are not necessarily described as superior or better than other embodiments.

[0051] Furthermore, in order to better illustrate this application, numerous specific details are provided in the following specific embodiments. Those skilled in the art should understand that this application can be carried out without some of the specific details. In some cases, methods, means, elements and circuits well known to those skilled in the art are not described in detail so as to emphasize the subject matter of this application.

[0052] Embodiments of this application provide a memory mapping method for flexibly defining the number of reserved redundant resources used for the integration and substitution of an address mapping table, and for performing multiple reversible substitutions of memory fault rows based on the address mapping table, thereby avoiding service performance loss, significantly reducing the memory failure rate, and improving memory reliability. Embodiments of this application further provide corresponding memory mapping circuits, computing devices, computer-readable storage media, chip systems, computer program products, etc. Details are described below individually.

[0053] In the following, we will use one example to illustrate the application scenario in the embodiments of this application.

[0054] As shown in Figure 1, a typical von Neumann computer system includes five components: computing components, control components, memory components, input components, and output components. The memory includes main memory and secondary memory (solid-state drives, hard disk drives, etc.). As an integral part of the von Neumann architecture, memory primarily functions as working memory, storing the instructions and data necessary for computer execution. With the development of services such as high-performance computing, big data analytics, and in-memory databases, applications have increasingly urgent requirements regarding memory capacity and bandwidth. Under the continuous advancement of requirements for memory capacity density and bandwidth performance, memory manufacturing processes are continuously shrinking, while interface speeds are continuously increasing. Furthermore, the memory failure rate is gradually increasing, posing a significant risk to memory reliability. Examples are as follows:

[0055] (1) Capacitance decreases. As the manufacturing process shrinks, the capacitor capacitance decreases (the capacitor capacitance of a 25 nm manufacturing process is 18 fF, while the capacitor capacitance of a 17 nm manufacturing process decreases to approximately 8 fF), and the amount of charge that can be stored in the capacitor decreases. As a result, the data retention characteristic gradually deteriorates.

[0056] (2) Leakage current increases. Due to the thinning of the capacitor insulating material and the subthreshold effect of the access transistor, leakage current increases. As a result, the data retention characteristics of the memory unit deteriorate.

[0057] (3) Coupling effects increase. Due to the size reduction, the capacitors, bit lines, and word lines become closer to each other, increasing coupling. As a result, the probability of data jumps due to mutual influence between adjacent spaces increases.

[0058] (4) The amount of row and column errors increases due to process defects. As the size decreases and capacity density increases, the demands on processing precision are constantly increasing. As a result, the processing defect density is continuously increasing, and this increase is manifested as an increase in the amount of premature failures in dynamic random access memory (DRAM), in particular a significant increase in the amount of failures where the row / column is the characteristic area of ​​failure.

[0059] (5) The probability of interface errors increases with increasing transmission rates. The interface speed of double data rate synchronous dynamic random-access memory (DDR SDRAM), or DDR for short, has been continuously increasing with each generation. Due to the use of parallel buses with single-ended signals and the influence of memory module sockets, the probability of data jumps on the interface also increases.

[0060] Based on statistical data collected on memory production failures and active network failures, it can be seen that with generational advancements, the increase in the number of memory failure lines exceeds the upper limit of memory repair capacity, the production outage rate increases with each generation, and the rate of active network failures continues to increase. However, memory failure areas are concentrated within a limited number of lines. Current memory device manufacturers implement a replacement function in memory devices. However, the implementation of the replacement function in memory devices pre-configures the redundant space used for replacement, and this redundant space cannot be changed. As a result, the number of memory replacements is limited, accompanied by a loss of certain service performance, and the current memory failure requirements cannot be met.

[0061] Based on this, embodiments of the present application provide a memory mapping method for flexibly defining the amount of reserved redundant resources used for the integration position and substitution of an address mapping table, and for performing multiple reversible substitutions of memory fault rows based on the address mapping table, thereby avoiding service performance loss, significantly reducing the memory failure rate, and improving memory reliability.

[0062] The memory mapping method provided in the embodiments of this application will be described below with reference to the application scenarios described above.

[0063] As shown in Figure 2, one embodiment of the memory mapping method provided in the present invention includes the following steps.

[0064] 200: The baseboard management controller (BMC) performs fault row detection on multiple memory locations of the computing device, and if it detects that a fault row exists in the first memory location, it provides the fault row address to the basic input / output system (BIOS).

[0065] In this embodiment of the present application, the BIOS shows a memory mapping circuit for a first memory for replacing faulty rows. The memory mapping circuit includes an acquisition circuit and a matching and search circuit. The matching and search circuit is integrated into an address command output circuit in the memory access path of the first memory or into a drive circuit of the first memory.

[0066] Both the BMC and BIOS are located on the mainboard of the computing device, and the mainboard provides memory slots for connecting multiple memory modules, including a first memory module. In this specification, "mainboard" includes a mainboard in a general sense, and also includes the combination of a mainboard and a backplane.

[0067] It should be noted that fault row detection may be performed on the first memory using a separate test device while the first memory is still in the production phase. During the computing device startup phase, fault row detection may be performed using the BIOS of the computing device. The entity performing fault row detection is not limited to this embodiment of the present application.

[0068] 201: The first memory acquisition circuit acquires the memory fault row address of the first memory from the main board and provides the acquired fault row address to the first memory matching and search circuit.

[0069] The first memory is a memory module. Each memory module contains multiple memory devices (memory chips), and each memory device contains multiple of Includes memory banks.

[0070] 202: The first memory lookup and search circuit obtains the address mapping table.

[0071] In this embodiment of the present application, the computing device first needs to enable a lookup circuit to acquire an address mapping table. The lookup circuit is integrated into a first memory, and a specific location of the lookup circuit is within a memory access path, such as an address command output circuit or drive circuit. Specifically, the lookup circuit is integrated into any address command output circuit or drive circuit between the address mapping module of the memory controller and the DRAM device (memory chip). The memory access path to the first memory may be understood as a path for the processor of a computing device to access the memory, for example, a path for a memory controller in a central processing unit (CPU), data processing unit (DPU), graphics processing unit (GPU), tensor processing unit (TPU), or embedded neural network processing unit (NPU) to access a DRAM device in the first memory. The address command output circuit or drive circuit in the memory access path includes a memory controller (DDR controller, DDRC) in the processor of the computing device, and further includes a registering clock driver (RCD) in the first memory. In this embodiment of the present application, an example in which matching and search circuits are integrated into the RCD is used for illustrative purposes.

[0072] Furthermore, the first memory is mounted on the computing device by using a memory slot provided by the computing device's mainboard. The computing device may be any computer device, server, or storage device that uses memory. The matching and search circuit may include volatile memory, such as associative memory (content addressable memory, CAM), ternary content addressable memory (TCAM), and a fully associative cache, i.e., a fully associative static random-access memory (SRAM) cache. Alternatively, the matching and search circuit may include non-volatile memory (NVM), such as one-time programmable memory (eFuse), programmable read-only memory (PROM), electrically erasable programmable read-only memory (E2PROM), and storage class memory (SCM). In this embodiment of the present application, an example in which the matching and search circuit includes a TCAM is used for illustrative purposes. In other words, the address mapping table is stored in the TCAM, and the TCAM is integrated into the RCD of the first memory.

[0073] Furthermore, the address mapping table includes a mapping relationship between a memory failure row address and a memory remapping row address corresponding to the memory failure row address. The address mapping table is used to remap the memory failure row address to the memory remapping row address when the first memory is accessed at the memory failure row address. The memory region indicated by the memory remapping row address is located within the reserved space of the first memory. The reserved space of the first memory may be derived from the user DRAM device capacity within the first memory; in other words, the reserved space is visible to the user and must be reserved using additional software methods. In addition, the reserved space may alternatively be derived from redundant space designed by the memory manufacturer beyond the nominal capacity of the first memory. The reserved space is beyond the addressing range of the memory controller and is invisible to the user. In this embodiment of the present application, an example in which the reserved space is derived from the user DRAM capacity within the first memory is used for illustrative purposes.

[0074] Furthermore, the first memory is specifically high-speed memory. For example, the first memory is DDR, low-power DDR (LPDDR), graphics DDR (GDDR), high-bandwidth memory (HBM), or SCM. In this embodiment of the present application, an example in which the first memory is DDR is used for illustrative purposes. The first memory comprises one or more memory channels, and one or more dual in-line memory modules (DIMMs) may be inserted into one memory channel, and one DIMM may comprise one or more memory ranks. One rank comprises multiple memory chips, and a memory chip is sometimes called a memory device. One chip comprises multiple memory banks (banks) or multiple memory bank groups. A bank is an array comprising multiple storage units. Rows of storage units within a bank may be represented by rows. When the memory medium is DRMA, a memory chip is also called a DRAM device.

[0075] Furthermore, the matching and search circuits use multiple memory chips as a single unit for row address translation. If a faulty row occurs in a single memory chip, the matching and search circuits translate the row addresses in multiple memory chips to memory remapping row addresses based on the address mapping table, and the translated rows include the faulty row. In other words, the address mapping table operates on each chip, and the matching and search circuits replace the memory faulty row addresses in all chips. In addition, the reserved space of the first memory includes at least one row from each of the multiple memory banks. In other words, at least one row of the storage units in each bank is used as reserved space, and as a result, the user can customize a larger reserved space to perform multiple reversible substitutions based on the address mapping table.

[0076] In this embodiment of the present application, the lookup and search circuits are integrated into the address command output or drive circuit in the memory access path of the first memory. Therefore, the user may customize the size and integration location of the lookup and search circuits in the address command output or drive circuit in the memory access path, in other words, the size and integration location of the address mapping table. A larger customized address mapping table indicates more memory remapping row addresses and a larger reserved space used as redundant resources. The size and location may be flexibly customized by the user based on requirements and actual circumstances.

[0077] In the memory mapping method provided in this embodiment of the present application, steps 201 and 202 may be performed independently in multiple scenarios. These are described separately below. Specifically, memory row mapping and replacement may be performed separately in the phase in which the memory manufacturer produces the memory, the computing device startup phase, and the computing device performs its services, achieving the corresponding technical effects. Memory row mapping and replacement may be performed by selecting one or more of the three scenarios.

[0078] I. First Memory Production Phase As shown in Figure 3, in the first memory production phase, the memory fault row address of the first memory may be obtained by using a test device (in this case, the test device is used as a computing device to perform embodiments of the method of this application). Specifically, a device sorting program test (smart memory test, SMT) is performed to induce early failures in advance based on a burn-in sorting algorithm. When a memory error is detected, the corresponding memory fault row address is recorded, a memory remapping row address is assigned to the memory fault row address, and an address mapping table is generated in the matching and search circuit based on a predetermined format to improve the first-pass yield of memory production.

[0079] Furthermore, since TCAM is volatile memory, an NVM, such as an eFuse, may be added to the first memory, and the address mapping table generated at this time is written to the eFuse in the RCD. The address mapping table generated during the production of the first memory is used as unique information of the first memory to perform persistent tracking using the built-in eFuse. In general, the eFuse programming interface is not opened to users on an active network to prevent user error. Since the eFuse is used to persistently store the address mapping table determined when the production of the first memory fails, the address mapping table also needs to be persistently stored in another non-volatile medium.

[0080] Specifically, after the first memory is installed in the computing device, the address mapping table in the eFuse needs to be further synchronized with the computing device's first storage device. The first storage device is an NVM, which may be integrated into an RCD chip, a module printed circuit board (PCB), a system mainboard, etc. The computing device's processor needs to detect whether the address mapping table in the eFuse has been synchronized with the computing device's NVM. The computing device can only use the first memory after successful synchronization. In this case, the first memory is ready for use.

[0081] The address mapping table obtained during the memory production phase may be stored in the non-volatile storage medium of the memory module. When the memory is used by a user, the user may retrieve the address mapping table from the non-volatile storage medium and add any newly discovered faulty rows to the address mapping table during the memory self-check in the computing device startup phase.

[0082] II. Computing Device Startup Phase As shown in Figure 4, the user installs the memory in the computing device, and the enable switch may be set in the computing device (where the first memory is installed). When the second command is sent, the enable switch is turned on, a self-check is initiated, and the acquisition of the memory fault row address of the first memory is enabled. If the memory is found to have failed, it is replaced within a time limit. When the first command is sent, in order to achieve the objective of quickly starting the computing device, the enable switch is turned off, the self-check is disabled, and the acquisition of the memory fault row address of the first memory is stopped.

[0083] When a computing device starts up, after the first command is sent, specifically during the pre-extensible firmware interface initialization (PEI) phase, the computing device's BIOS performs a full-space memory detection, such as a memory build-in-self test (Mbist). If a memory error is detected, the corresponding memory fault row address must be recorded, a memory remapping row address is allocated in the reserved space for the memory fault row address, an address mapping table is generated in the lookup and search circuit based on a predetermined format, and the address mapping table in the TCAM is synchronized to the system persistent NVM in the computing device for backup, such as the onboard serial peripheral interface (SPI) flash.

[0084] Furthermore, during the startup process of a computing device equipped with the first memory, the address mapping table is read from the first memory storage device, and the address mapping table is updated via the computing device's memory self-check. Specifically, during the PEI phase at computing device startup, the product serial number (SN) of the first memory is used as a unique identification mark, and the address mapping table in the computing device's first memory storage device NVM, the address mapping table recorded in the eFuse during the first memory production phase, and the address mapping table generated via the memory self-check during the PEI phase at computing device startup are read, and a combined set of their information is obtained. In the three recorded address mapping tables mentioned above, entries from different rows are directly merged (Rd-Merge). If a memory fault row address is replaced multiple times, specifically if row replacement information exists in two or more recording locations, the address mapping table with the higher reliability priority is used for overwriting: NVM reliability priority > eFuse reliability priority > PEI self-check reliability priority. For example, suppose the memory failure row address is A1, the memory remapping row address corresponding to the address mapping table recorded in the NVM is B1, the memory remapping row address corresponding to the address mapping table recorded in the eFuse is B2, and the memory remapping row address corresponding to the address mapping table recorded in the memory self-check during the PEI phase is B3. In this case, it is ultimately determined that the memory remapping row address corresponding to the memory failure row address A1 is B1, and the memory remapping row address is synchronized with the matching and search circuit TCAM. In this case, the computing device does not use the first memory, thereby avoiding the problem of memory data movement. Finally, the merged address mapping table is written to the first storage device NVM during the DXE phase.

[0085] Optionally, when the reserved space is from the user DRAM capacity in the first memory, during the BIOS memory mapping phase when the computing device is started, the system memory mapping relationships and memory segment attributes may be defined using memory descriptors and then transferred to the computing device's operating system (OS) via the advanced configuration and power interface (ACPI). The reserved space may be reported as the reserve attribute during the memory map phase. Note that the memory map is a startup service, and since the memory map is finished when the computing device is operating and cannot be woken up, reserved space cannot be set for memory that is hot-added during operation. If the reserved space is from redundant space designed by the memory manufacturer beyond the nominal capacity of the first memory, this step does not need to be performed when the computing device is started.

[0086] III. Computing Device Execution Phase As shown in Figure 5, when the computing device is operating, a first memory failure log is obtained for the first memory, first memory failure characteristics are extracted from the first memory failure log, and a prediction is made based on the first memory failure characteristics to obtain the memory failure row address of the first memory.

[0087] Specifically, as shown in Figure 6, the computing device includes an application (APP), an OS, a BIOS, and a CPU. A memory controller is located on the CPU. In-band information (management control information and service transmission information are transmitted over the same logical channel) collected by the OS's board management agent within the computing device, i.e., information collected over the data channel, and out-of-band information (transmitted over different logical channels) collected by the baseboard management controller (BMC) located in the computing device, i.e., information collected over additional channels other than the data channel, are aggregated in real time at the BMC as a first memory failure log, forming a federal diagnostic module (FDM) log. The FDM log records bit jump information for rows in the first memory. A memory failure prediction engine deployed at the BMC performs failure prediction using the first memory failure characteristics (memory instantaneous failure characteristics) extracted from the FDM log, predicting which rows in the first memory are faulty (which may be understood as rows at risk), and may ultimately obtain the memory fault row address of the first memory.

[0088] It should be understood that address mapping tables generated during the execution state of a computing device may be dynamically replaced and released, and are not persistent. Therefore, the requirements for the accuracy of fault prediction may be reduced, thereby improving reach.

[0089] If the memory failure prediction engine predicts that a row has a high risk of failure, the BMC records the row information at risk. During reliability, availability, and serviceability (RAS) interrupt handling, the BIOS queries the BMC via the intelligent platform management interface (IPMI) to see if there are any row warnings at risk. If the BMC has row warnings at risk, the BIOS initiates the row replacement process, allocating memory remapping row addresses within the reserved space for memory failure row addresses and generating a new address mapping table. In addition, performing row replacement in the address mapping table while the computing device is in use requires not only correcting the mapping relationships within the address mapping table but also performing data copying.

[0090] The media row address is reported by fault prediction, and the physical address that can be manipulated by the BIOS must be reverse-calculated. Since the sum of all DRAM capacities is equal to the DRAM space size reported by the BIOS, there is a one-to-one mapping relationship between physical addresses and media addresses. A reversible reverse mapping must exist in order to perform the conversion from media addresses to physical addresses. Therefore, the physical address corresponding to the row's start address may be calculated as the copy start address. In addition, the contiguous address range of the row is calculated based on the number of interleaved channels (ways). Data copying may also be performed by directly manipulating physical addresses using the BIOS's memory copy function (memcpy), with read, error correction, and write operations performed internally at cache line (CL) granularity, using the reverse-calculated physical address mentioned above as the copy start address, the contiguous address range as the copy length, and directly copying the data corresponding to the memory fault row address to the memory remapping row address to which it is allocated. After the copy is complete, the address mapping table is merged with the address mapping table recorded in the NVM in the first storage device based on a predefined format to generate a new address mapping table, which is then overwritten in the TCAM via the I3C bus and overwritten in the system NVM.

[0091] After the aforementioned operations are complete, it should be noted that when the computing device is running, you will find that the error is still being reported even after the memory fault row address has been replaced. This indicates that the memory remapping row address to which the row address is remapped has failed, and the memory remapping row address needs to be updated further, and the memory remapping row address is remapped to another redundant row. After the mapping relationship in the address mapping table has been successfully corrected, subsequent access to the memory fault row address is redirected to the memory remapping row address because the underlying mapping has been changed.

[0092] In this embodiment of the present application, the BMC aggregates out-of-band or in-band memory error information for offline training nodes to perform parameter training on a memory failure prediction model. The algorithms and models obtained through training may be used for online inference and real-time prediction of memory failure development trends, and the BIOS is notified in a timely manner to generate a new address mapping table in order to reduce or even avoid the occurrence of uncorrectable errors (UCEs).

[0093] Refer to Figure 6. It can be seen that the computing device accesses multiple DIMMs in the first memory by using a memory controller. A DIMM contains multiple memory chips (e.g., chip 0 to chip 10 in a rank), an RCD, and a serial presence detect hub (SPD Hub). Each memory chip contains multiple memory banks (e.g., bank 0). The TCAM and eFuse are located within the RCD. When the first memory starts operating / powers on, the TCAM loads the address mapping table from the eFuse. When the first memory stops operating / powers off, the TCAM synchronizes the address mapping table with the computing device's eFuse or system NVM to achieve persistent storage. Memory access addresses are sent from the memory controller to the TCAM in the RCD via the DIMM's edge connector for matching, and memory failure row addresses in a memory bank are remapped to memory remapping row addresses, after which access is performed. For example, a memory failure row address is remapped to a memory remapping row address in the same bank.

[0094] Furthermore, before the first memory stops working, in other words, before the computing device stops working, the address mapping table must be written from the lookup and search circuit to the first memory. After the first memory starts functioning, in other words, after the computing device starts functioning, the address mapping table in the first memory is loaded into the lookup and search circuit to enable persistent storage and updating of the address mapping table.

[0095] Furthermore, if the computing device system is idle, risk checking and release may be performed in the same way as obtaining memory failure row addresses; in other words, an access test is performed on the memory failure row address to obtain a second memory failure log for the first memory, then a second memory failure characteristic is extracted from the second memory failure log, and a prediction is performed based on the second memory failure characteristic to determine whether the memory failure row address is an actual failure row address. If the risk of row failure for the memory failure row address is predicted to be low, the memory failure row address is determined not to be an actual failure row address, and the memory failure row address and the memory remapping row address corresponding to the memory failure row address are released from the address mapping table, saving redundant space in the TCAM and reserved space, enabling the system to have reversible isolation and release capabilities, reducing the requirement for prediction accuracy, and improving the reach of failure prediction.

[0096] Optionally, a TCAM bypass switch may be further designed within the RCD for hazard confirmation and release. After the TCAM bypass switch is turned on through register activation configuration, the TCAM will not query or match for memory access. This may perform access to a replaced fault row address. In addition, as shown in Figure 7, a bidirectional lookup table may be further designed to automatically determine, based on the input address range, whether a service access or a hazard pressure test confirmation is performed. As an example, a bidirectional lookup table located on the RCD is used. If the input row address range is in the user addressing space (e.g., 0 to 10,000), a forward lookup is performed and the memory fault row address is mapped to a memory remapping row address. If the input row address range is in the reserved space address range (e.g., 10,000 to 11,000), a reverse lookup is performed and the memory remapping row address is mapped to the memory fault row address to determine whether the access can be successful. Next, based on this, a pressure test is performed on the memory fault row address to conduct a secondary risk check, thereby determining whether the memory fault row address is an actual row fault address and whether the memory fault row address needs to be freed.

[0097] As shown in Figure 8, the TCAM provided in this embodiment of the present application may be further integrated into the memory controller of the processor of the first device. The memory controller includes a RAS module, a scheduler, an address mapping module, and at least some parts of the physical layer (PHY). The memory controller is connected to HA. The RAS module implements the RAS functions of the memory subsystem. The scheduler is configured to schedule memory access tasks with high efficiency and high quality of service (QoS). The address mapping module performs the translation of system media addresses to DDR physical addresses so that memory access conforms to the DDR protocol. Memory access addresses are sent to the PHY using the DDR physical interface (DDR PHY Interface, DFI) protocol. The PHY is connected to off-chip DDR SDRAM via an input / output (I / O) interface, translates the DFI protocol to the DDR protocol, and maximizes the sampling window through fine-tuning of the interface time sequence and calibration of the interface function. Furthermore, the TCAM and NVM are located within the address mapping module. When the first memory unit starts operating / powers on, the TCAM loads the address mapping table from the NVM. When the first memory unit stops operating / powers off, the TCAM synchronizes the address mapping table with the NVM to achieve persistent storage.

[0098] 203: The first memory unit obtains a memory access address from outside the first memory unit.

[0099] Access is initiated by a processor within the computing device that has memory access permissions, and the processor used as an external visitor may be, for example, a CPU, GPU, DPU, or NPU.

[0100] 204: The memory mapping circuit uses the acquired memory access address to perform a match against the memory access address based on the address mapping table.

[0101] 205: If a memory access address matches a memory fault row address, the memory mapping circuit translates the access to the memory access address to the memory remapping row address.

[0102] In the case of a read access, in step 203, the data in the remapped row address is returned to the external visitor. In the case of a write access, the data is written to the remapped row address, and in step 203, a write success response is returned to the external visitor.

[0103] In step 202, the address mapping table generated in any phase must be used in a matching manner when memory is accessed. First, the memory access address from outside the first memory is obtained, which may be transmitted by the processor of the computing device, specifically, bank group information, bank information, or row information entered using an input command address (DCA), and then a match is performed against the memory access address based on the address mapping table. If the target of access in the first memory is a memory fault row address, the memory remapping row address to which the memory fault row address is mapped is obtained based on the address mapping table. Steps 202 to 205 are specifically performed by the matching and search circuits within the computing device.

[0104] For example, the address mapping table shown in Table 1 contains four mapping relationship groups, where A represents a faulty row in a bank in the first memory, and B represents the corresponding remapping row in the same bank in the first memory. For example, A1 represents the first row in bank0 (e.g., row1), and B1 represents the last row in bank0 (e.g., row100). A2 represents the second row in bank1, and B2 represents the last row in bank1. A3 represents the second row in bank2, and B3 represents the first to last row in bank2. A4 represents the first row in bank3, and B4 represents the second to last row in bank3.

[0105] [Table 1]

[0106] Specifically, as shown in Figure 9, a memory access address is entered into the first memory from the memory access path. When the memory access address reaches the TCAM in the RCD via the DDR C / A bus, a TCAM search is initiated. If the memory access address matches the memory fault row address in the address mapping table, for example, if the memory access address is A1, it can be understood that there is a row fail in the memory access address and a TCAM hit, i.e., the search was successful. The memory fault row address in the DRAM is remapped to the memory remapping row address B1 corresponding to the memory fault row address, and subsequent access targets are replaced with the memory remapping row address B1. In other words, the data corresponding to the memory remapping row address B1 is read via the DDR data bus. If the memory access address is A5, it may not be matched in the address mapping table and may be understood as a TCAM miss. The subsequent access target is still memory access address A5, and the data corresponding to memory access address A5 is read directly via the DDR data bus.

[0107] In this embodiment of the present application, the memory failure row address of the first memory is obtained. An address mapping table is generated in the lookup and search circuit. The address mapping table includes the memory failure row address and the memory remapping row address corresponding to the memory failure row address. If the first memory is accessed at the memory failure row address and the memory region indicated by the memory remapping row address is within the reserved space of the first memory, the address mapping table is used to remap the memory failure row address to the memory remapping row address. Since the lookup and search circuit is integrated into the address command output circuit or drive circuit in the memory access path of the first memory, the user may flexibly define the integration location of the address mapping table and the number of reserved redundant resources, and may perform multiple reversible substitutions based on the address mapping table without requiring a system restart. To avoid loss of service performance, significantly reduce the memory failure rate, and improve memory reliability, neither kernel mode nor user mode recognizes the substitution.

[0108] The memory mapping method provided in the embodiments of this application has been described above. The related devices provided in the embodiments of this application will now be described with reference to the attached drawings.

[0109] As shown in Figure 10, one embodiment of the memory mapping circuit 1000 provided in the embodiments of the present application includes an acquisition circuit 1001 configured to acquire a memory fault row address of a first memory, wherein the acquisition unit 1001 can perform step 201 in the embodiment of the method described above, and a matching and search circuit 1002 configured to acquire a memory fault row address from the acquisition circuit 1001, wherein the matching and search circuit 1002 is further configured to acquire an address mapping table, the address mapping table includes mapping relationships between memory fault row addresses and memory remapping row addresses corresponding to the memory fault row addresses. If the access target of the first memory is a memory fault row address, the matching and search circuit 1002 is configured to obtain a memory remapping row address to which the memory fault row address is mapped, based on the address mapping table, and the memory region indicated by the memory remapping row address is within the reserved space of the first memory, and the matching and search circuit is integrated into an address command output circuit or drive circuit in the memory access path of the first memory. The matching and search circuit 1002 may perform step 202 in the embodiment of the method described above.

[0110] Optionally, the memory mapping circuit 1000 is integrated into memory, which includes multiple memory chips configured to provide reserved space, or the memory mapping circuit 1000 is integrated into a processor, which is one of the following: a central processing unit CPU, a data processing unit DPU, an embedded neural network processing unit NPU, a graphics processing unit GPU, or a tensor processing unit TPU.

[0111] Optionally, the matching and searching circuit 1002 is further configured to obtain a memory access address from outside the first memory, to perform a match against the memory access address based on an address mapping table using the obtained memory access address, and, if the memory access address matches a memory fault row address, to convert the access to the memory access address to an access to a memory remapping row address.

[0112] Optionally, the first memory includes multiple memory chips, and the matching and search circuit 1002 uses the multiple memory chips as a whole for row address translation. Specifically, the matching and search circuit 1002 is configured to translate row addresses in the multiple memory chips to memory remapping row addresses based on the address mapping table when a faulty row occurs in a single memory chip, and the translated rows include the faulty row.

[0113] Optionally, each of the multiple memory chips includes multiple memory banks, and the reserved space of the first memory includes at least one row of each of the memory units in the multiple memory banks.

[0114] Optionally, the address mapping table is stored in volatile memory within the lookup and search circuit 1002. The memory mapping circuit 1000 further includes a read / write circuit 1003. The read / write circuit 1003 is configured to write the address mapping table from the lookup and search circuit 1002 to a first storage device before the first memory stops operating, the first storage device being non-volatile memory located within the computing device. The read / write unit 1004 is further configured to load the address mapping table from the first storage device into the lookup and search circuit 1002 after the first memory has started operating.

[0115] Optionally, during the startup process of a computing device equipped with a first memory, the read / write circuit 1003 is further configured to read an address mapping table from the first memory and update the address mapping table via a memory self-check of the computing device.

[0116] Optionally, the volatile memory within the matching and search circuit 1002 is an associative memory, a ternary associative memory, or a fully associative cache.

[0117] Optionally, the address mapping table is stored in non-volatile memory within the matching and search circuit 1002.

[0118] Optionally, the memory mapping circuit 1000 further includes a generation circuit 1004. The generation circuit 1004 is configured to generate an address mapping table when a computing device equipped with the first memory is started, and to synchronize the address mapping table with the lookup circuit 1002 before the computing device uses the first memory.

[0119] Optionally, the acquisition unit 1001 is configured to acquire a first memory failure log of the first memory, extract first memory failure characteristics from the first memory failure log, and perform a prediction based on the first memory failure characteristics in order to acquire the memory failure row address of the first memory.

[0120] Optionally, the memory mapping circuit 1000 further includes a release circuit 1005. The release circuit 1005 is configured to perform an access test on the memory fault row address to determine whether the memory fault row address is an actual fault row address, and, if the memory fault row address is not an actual fault row address, to release the memory fault row address and the memory remapping row address corresponding to the memory fault row address from the address mapping table.

[0121] Optionally, the memory mapping circuit 1000 further includes a transmission circuit 1006. The transmission circuit 1006 is configured to transmit a first command, which is used to enable the cessation of obtaining the memory fault row address of the first memory.

[0122] Optionally, the matching and search circuit 1002 is integrated into the memory controller or register clock driver within the address command output circuit or drive circuit.

[0123] For an understanding of the memory mapping circuit 1000 provided in this embodiment of the present application, please refer to the corresponding content of the previously described embodiment of the memory mapping method. Details will not be repeated here.

[0124] Figure 11 is a diagram of a possible logical structure of a computing device according to one embodiment of the present application. The computing device includes a main board 1101, a processor 1102, a memory 1103, and a memory mapping circuit 1104.

[0125] The main board 1101 is configured to perform memory fault row detection and send the memory fault row address to the memory mapping circuit 1104. The memory mapping circuit 1104 is integrated into the processor 1102 or memory 1103 (as shown in Figure 11, the memory mapping circuit 1104 is integrated into memory 1103). The memory mapping circuit 1104 is configured to perform the memory mapping method described in the embodiments described above in Figures 2 to 9. Memory 1103 is used as the first memory for performing memory fault row address mapping.

[0126] Specifically, memory 1103 is the first memory in the embodiment of the method. The memory mapping circuit 1104 includes a matching and search circuit in the embodiment of the method, specifically a memory controller or register clock driver. Alternatively, the memory mapping circuit 1104 includes an acquisition circuit 1001, a matching and search circuit 1002, a read / write circuit 1003, a generation circuit 1004, a release circuit 1005, and a transmit circuit 1006, as shown in Figure 10. The memory mapping circuit 1104 may perform the memory mapping method described above on memory 1103.

[0127] In another embodiment of this application, a computer-readable storage medium is further provided. The computer-readable storage medium stores computer-executable instructions. When at least one processor of the device executes a computer-executable instruction, the device performs the memory mapping method described in the aforementioned embodiments of Figures 2 to 9.

[0128] In another embodiment of this application, a computer program product is further provided. The computer program product includes computer executable instructions, which are stored in a computer-readable storage medium. At least one processor of the device may read the computer executable instructions from the computer-readable storage medium. When at least one processor executes the computer executable instructions, the device is enabled to perform the memory mapping method described in the above embodiments of Figures 2 to 9.

[0129] In another embodiment of this application, a chip system is further provided. The chip system includes at least one processor and an interface. The interface is configured to receive data and / or signals. At least one processor is configured to support the execution of the memory mapping method described in the above embodiments of Figures 2 to 9. In possible designs, the chip system may further include a storage device. The storage device is configured to store program instructions and data required for the computer device. The chip system may include a chip, or it may include a chip and other separate components.

[0130] Those skilled in the art will notice, in combination with the examples described in the embodiments disclosed herein, that the steps of the units and algorithms may be implemented by electronic hardware or by a combination of computer software and electronic hardware. Whether the functions are performed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for specific applications, but the implementations should not be considered to exceed the scope of the embodiments of this application.

[0131] For the sake of brevity and conciseness, it will be readily apparent to those skilled in the art that the detailed operating processes of the aforementioned systems, apparatus, and units are described by referring to the corresponding processes in the embodiments of the methods described above. Details are not repeated here.

[0132] It should be understood that in some embodiments provided in this application, the disclosed systems, apparatus, and methods may be implemented in other ways. For example, the embodiments of the apparatus described above are merely examples. For example, the division into units is merely a logical functional division, and there may be other divisions between actual implementation forms. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not performed. In addition, the mutual coupling, direct coupling, or communication connection indicated or considered may be implemented through some interface. Indirect coupling or communication connection between apparatus or units may be implemented in electronic, mechanical, or other forms.

[0133] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected based on the actual requirements for achieving the objectives of the solution of the embodiment.

[0134] In addition, the functional units in the embodiments of this application may be integrated into a single processing unit, each unit may exist physically independently, or two or more units may be integrated into a single unit. The integrated unit may be implemented in hardware form or in the form of a software functional unit.

[0135] If the integrated unit is implemented in the form of a software function unit and sold or used as an independent product, the integrated unit may be stored on a computer-readable storage medium. Based on such understanding, the technical solution of this application, or a portion that contributes to the prior art, or all or part of the technical solution, may be implemented in the form of a software product. A computer software product includes several instructions that are stored on a storage medium and instruct a computer device (which may be a personal computer, server, network device, etc.) to perform all or part of the steps of the method described in the embodiments of this application. The storage medium includes any medium capable of storing program code, such as a USB flash drive, removable hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk. [Explanation of symbols]

[0136] 1000 Memory Mapping Circuit 1001 Acquisition circuit, acquisition unit 1002 Matching and Search Circuit 1003 Read / Write Circuit 1004 Generation circuit 1005 Release circuit 1006 Transmitter Circuit 1101 Mainboard 1102 Processor 1103 memory 1104 Memory Mapping Circuit

Claims

1. A memory mapping method, A step of obtaining a memory failure row address of a first memory, wherein the step of obtaining a memory failure row address of a first memory includes: obtaining a first memory failure log of the first memory; extracting first memory failure characteristics from the first memory failure log; and performing a prediction based on the first memory failure characteristics in order to obtain the memory failure row address of the first memory. A step of obtaining an address mapping table by a matching and search circuit, wherein the address mapping table includes a mapping relationship between the memory fault row address and the memory remapping row address corresponding to the memory fault row address. If the access target of the first memory is the memory fault row address, the step of obtaining the memory remapping row address to which the memory fault row address is mapped, based on the address mapping table, wherein the memory region indicated by the memory remapping row address is within the reserved space of the first memory, and the matching and search circuit is integrated into an address command output circuit or drive circuit in the memory access path of the first memory. Methods that include...

2. The method described above is The steps include obtaining a memory access address from outside the first memory, The steps include using the acquired memory access address and performing a match against the memory access address based on the address mapping table, If the memory access address matches the memory fault row address, the step is to convert the access to the memory access address to the memory remapping row address. The method according to claim 1, further comprising:

3. The first memory includes a plurality of memory chips, the matching and search circuit uses the plurality of memory chips collectively for row address translation, and the step of obtaining the memory remapping row address to which the memory fault row address is mapped based on the address mapping table, specifically, If a faulty row occurs in a single memory chip, the step of converting row addresses in the plurality of memory chips to memory remapping row addresses based on the address mapping table, wherein the converted row includes the faulty row. The method according to claim 1, including the method described in claim 1.

4. The method according to claim 3, wherein each of the plurality of memory chips includes a plurality of memory banks, and the reserved space of the first memory includes at least one row of storage units of each of the plurality of memory banks.

5. The address mapping table is stored in the volatile memory within the matching and search circuit, and the method is The steps include: writing the address mapping table from the matching and searching circuit to the first storage device before the first memory stops operating, wherein the first storage device is a non-volatile memory; The steps include loading the address mapping table in the first storage device into the matching and search circuit after the first memory has started operating, and The method according to claim 1, further comprising:

6. The method described above is In the startup process of the computing device equipped with the first memory, the steps include reading the address mapping table from the first storage device and updating the address mapping table via a memory self-check of the computing device. The method according to claim 5, further comprising:

7. The step of obtaining an address mapping table by matching and searching circuits is as follows: When the computing device equipped with the first memory is started, the process includes the step of generating the address mapping table, The aforementioned method, The method according to claim 1, further comprising the step of synchronizing the address mapping table with the matching and search circuit before the computing device uses the first memory.

8. The method described above is The steps include: performing an access test on the memory fault row address in order to determine whether the memory fault row address is an actual fault row address; If the memory fault row address is not the actual fault row address, the steps include releasing the memory fault row address and the memory remapping row address corresponding to the memory fault row address from the address mapping table. The method according to claim 1, further comprising:

9. A memory mapping circuit, An acquisition circuit configured to acquire the memory fault row address of a first memory, wherein the acquisition circuit is configured to specifically acquire a first memory fault log of the first memory, extract a first memory fault characteristic from the first memory fault log, and perform a prediction based on the first memory fault characteristic in order to acquire the memory fault row address of the first memory, A matching and search circuit configured to acquire the memory fault row address from the acquisition circuit, wherein the matching and search circuit acquires an address mapping table, and the address mapping table is further configured to include a mapping relationship between the memory fault row address and the memory remapping row address corresponding to the memory fault row address. Includes, A circuit configured such that, when the access target of the first memory is the memory fault row address, the matching and search circuit obtains the memory remapping row address to which the memory fault row address is mapped, based on the address mapping table, the memory region indicated by the memory remapping row address is within the reserved space of the first memory, and the matching and search circuit is integrated into an address command output circuit or drive circuit in the memory access path of the first memory.

10. The memory mapping circuit is integrated into the memory, and the memory includes a plurality of memory chips configured to provide the reserved space, or The circuit according to claim 9, wherein the memory mapping circuit is integrated into a processor, and the processor is one of a central processing unit (CPU), a data processing unit (DPU), an embedded neural network processing unit (NPU), a graphics processing unit (GPU), or a tensor processing unit (TPU).

11. The circuit according to claim 9 or 10, wherein the matching and searching circuit is further configured to: obtain a memory access address from outside the first memory; use the obtained memory access address to perform a match against the memory access address based on the address mapping table; and, if the memory access address matches the memory fault row address, convert the access to the memory access address to the memory remapping row address.

12. The first memory includes a plurality of memory chips, and the matching and search circuit uses the plurality of memory chips as a single unit for row address translation. The matching and searching circuit is configured, specifically, to convert row addresses in the plurality of memory chips to memory remapping row addresses based on the address mapping table when a fault row occurs in a single memory chip, so that the converted row includes the fault row, according to claim 9 or 10.

13. The circuit according to claim 12, wherein each of the plurality of memory chips includes a plurality of memory banks, and the reserved space of the first memory includes at least one row of storage units in each of the plurality of memory banks.

14. The address mapping table is stored in the volatile memory within the matching and search circuit, and the circuit The first memory further includes a read / write circuit configured such that the address mapping table is written from the matching and search circuit to the first storage device before the first memory stops operating, and the first storage device is a non-volatile memory. The circuit according to claim 9 or 10, wherein the read / write circuit is further configured to load the address mapping table in the first storage device into the lookup and search circuit after the first memory has started operating.

15. The circuit according to claim 14, wherein, in the startup process of a computing device equipped with the first memory, the read / write circuit is further configured to read the address mapping table from the first storage device and update the address mapping table via a memory self-check of the computing device.

16. The aforementioned circuit, The circuit according to claim 9 or 10, further comprising a generation circuit configured to generate the address mapping table when a computing device equipped with the first memory is started, and to synchronize the address mapping table with the matching and search circuit before the computing device uses the first memory.

17. The aforementioned circuit, The circuit according to claim 9 or 10, further comprising a release circuit configured to perform an access test on the memory fault row address in order to determine whether the memory fault row address is an actual fault row address, and, if the memory fault row address is not an actual fault row address, to release the memory fault row address and the memory remapping row address corresponding to the memory fault row address from the address mapping table.

18. A computer-readable storage medium wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 8 is performed.

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