Indication device

Abstract

When supplying different signals to multiple pixels at the same time using multiple wires, Reduces differences in load capacitance formed in each wiring, thereby reducing display grayscale shifts and / or signal delays. The objective is to provide a display device that can reduce power consumption. [Solution] A first data line to the Nth (where N is 3 or more) for supplying different video signals. A selection of data lines (number) to connect to any one of the first to Nth data lines. A pixel having a transistor, and having any one of the first to the Nth data lines Then, the first data line to the Nth data line is crossed between one terminal of the selection transistor and the other terminal. By doing so, one of the first to Nth data lines is selected at one end of the transistor. It is placed and connected to the nearest neighbor of the child.

Description

Technical Field

[0001] The present invention relates to a display device. Or the present invention relates to a driving method of a display device. Or, the present invention relates to an electronic device including the display device.

Background Art

[0002] Display devices, such as liquid crystal display devices using liquid crystal elements, are becoming widespread, from large display devices such as television receivers to small display devices such as mobile phones. In the future, products with higher added value are required and development is underway. In the future, in order to further increase the added value, it may be possible to increase the number of wirings such as scanning lines or data lines that supply signals to each pixel of the display device, and to make the driving of the pixels more highly functional. For example, Patent Document 1 discloses a display device provided with a plurality of data lines. Patent Document 1 discloses a configuration in which each of the plurality of data lines is connected to a transistor of a pixel.

[0003] In the future, in order to further increase the added value, it may be possible to increase the number of wirings such as scanning lines or data lines that supply signals to each pixel of the display device, and to make the driving of the pixels more highly functional. For example, Patent Document 1 discloses a display device provided with a plurality of data lines. Patent Document 1 discloses a configuration in which each of the plurality of data lines is connected to a transistor of a pixel.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] When increasing the number of wirings such as scanning lines or data lines that supply signals to each pixel of the display device in the same manner as in Patent Document 1 above, the wiring is extended from a transistor of the pixel to supply a signal to the pixel. The configuration involves wiring and connections such as scan lines or data lines. In this configuration, the load capacity of each wiring... There is a problem where discrepancies in quantity occur, causing display malfunctions. The following will be explained with reference to the diagrams.

[0006] Figure 15(A) shows the circuit configuration of the pixels in the display device. In Figure 15(A), N Specifically, there are 3 data lines (also called signal lines) for each data line (N is a natural number greater than or equal to 3). This shows a circuit configuration for supplying different video signals from a single line to three different pixels. Pixel 1501A is connected to transistor 1504A (also called a selection transistor) and displays It has element section 1505A. The transistor 1504A of pixel 1501A has a gate terminal One of the terminals (1) is connected to scan line 1503A and will become either the source terminal or the drain terminal. One terminal (also called a connector) is connected to the first data line 1502A, and the other terminal is connected to the display element unit 150 It is connected to 5A. Pixel 1501B is connected to transistor 1504B (selected transistor). It has a (also called) and a display element section 1505B. The transistor 150 of the pixel 1501B 4B has its gate terminal connected to scan line 1503B and can be used as either a source or drain terminal. One terminal (also called the first terminal) is connected to the second data line 1502B, and the other terminal This is connected to the display element section 1505B. Pixel 1501C is connected to transistor 1504C. It has a (also called a selection transistor) and a display element section 1505C. Pixel 1501C Transistor 1504C has its gate terminal connected to scan line 1503C, and its source terminal also One of the terminals that serves as the drain terminal (also called the first terminal) is connected to the third data line 1502C. The other terminal is connected to the display element unit 1505C. Figure 15(A) described above. The circuit configuration shown in the image is, for example, based on the scanning signals of scan lines 1503A to 1503C. Transistors 1504A through 1504C are simultaneously in a conductive state (also known as the ON state). (u) The first data line 1502 is connected to the display element section 1505A to the display element section 1505C. When supplying separate video signals from data lines A to the third 1502C, this configuration is effective. be.

[0007] A detailed explanation of the display elements for display element sections 1505A to 1505C will be provided below. To put it simply, a liquid crystal display device has a configuration that includes liquid crystal elements and capacitive elements, and an EL element If available, the configuration should include a light-emitting element and a transistor for driving the light-emitting element. stomach.

[0008] When pixels are arranged in a matrix, the first data line 1502A to the third data Line 1502C is set in a direction approximately perpendicular to scan lines 1503A to 1503C. The data is then transmitted along the first data line 1502A to the third data line 1502C. Pixels 1501A to 1501C having transistors 1504A to 1504C Therefore, the first data line 1502A to the third data line 1502 When C is provided in parallel, one terminal of transistor 1504B and the second data line 1502 When connecting to B, the intersection 1506 shown in Figure 15(A) is formed. When connecting one terminal of transistor 1504C to the third data line 1502C, see Figure The intersection 1507 shown in 15(A) will be formed. The intersection 1506, intersection In 1507, an electrical short circuit occurred between the first data line 1502A and the third data line 1502C. To avoid a short circuit, a conductive layer is formed in another layer, and through the conductive layer, one terminal of the transistor 1504B is connected to the second data line 1502B, and one terminal of the transistor 15 04C is connected to the third data line 1502C as shown in the figure.

[0009] However, by connecting one terminal of the transistor 1504B to the second data line 1 502B through the conductive layer, and connecting one terminal of the transistor 1504C to the third data line 1502​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​The data lines of the above natural numbers are connected to any one of the data lines from the 1st to the Nth. A pixel having a selection transistor, and having a first data line to the Nth data line One of the terminals of the selection transistor intersects with the first to the Nth data line. By inserting it, one of the first to Nth data lines is selected by the transistor. This is a display device that is installed and connected to the nearest terminal.

[0012] In one embodiment of the present invention, the other terminal of the selection transistor is a display element having a liquid crystal element. It may also be a display device to which the child is connected.

[0013] In one embodiment of the present invention, the other terminal of the selection transistor is connected to an element and an element It may also be a display device to which a display element having a drive transistor for driving is connected.

[0014] In one embodiment of the present invention, the display device has scan lines, and a first data line to the Nth data line The intersection may be a display device provided using the same conductive layer as the scan lines.

[0015] In one aspect of the present invention, the guidance at the intersection of the first to Nth data lines The resistance formed by the electrochemical layer is uniformly formed across the first to the nth data lines. A display device would also suffice.

[0016] One aspect of the present invention relates to a first to Nth (where N is 3 or more) scan line for supplying different scan signals. A scan line (a natural number) and a selectable scan line connected to any one of the first to the Nth scan lines. A pixel having a lampistor, and having one of the first to the Nth scan lines, The gate terminal of a selector transistor is formed by crossing the first to the Nth scan lines. Select one of the data lines (1) to the Nth scan line and place it closest to the gate terminal of the transistor. It is a display device that is installed and connected.

[0017] In one embodiment of the present invention, one terminal of the selection transistor is connected to a first data line to the Nth data line. One of the data lines is connected, and the other terminal of the selection transistor has a liquid crystal element. It may also be a display device to which a display element is connected.

[0018] In one embodiment of the present invention, one terminal of the selection transistor is connected to a first data line to the Nth data line. One of the data lines is connected, and the other terminal of the selection transistor is connected to the light-emitting element and Even in a display device to which a display element having a drive transistor for driving a light-emitting element is connected good. [Effects of the Invention]

[0019] According to one aspect of the present invention, the difference in load capacitance formed in each wiring is reduced, and the shift in display grayscale is reduced. And / or signal delay can be reduced. [Brief explanation of the drawing]

[0020] [Figure 1] A circuit diagram in one embodiment of the present invention. [Figure 2] A circuit diagram in one embodiment of the present invention. [Figure 3] A top view of one embodiment of the present invention. [Figure 4] A circuit diagram in one embodiment of the present invention. [Figure 5] A circuit diagram in one embodiment of the present invention. [Figure 6] A circuit diagram in one embodiment of the present invention. [Figure 7] A circuit diagram in one embodiment of the present invention. [Figure 8] A circuit diagram in one embodiment of the present invention. [Figure 9] A circuit diagram and timing chart in one embodiment of the present invention. [Figure 10] Circuit diagram and block diagram in one embodiment of the present invention. [Figure 11] A timing chart diagram in one embodiment of the present invention. [Figure 12] A top view and a cross-sectional view in one embodiment of the present invention. [Figure 13] A cross-sectional view of one embodiment of the present invention. [Figure 14] A diagram illustrating an electronic device in one embodiment of the present invention. [Figure 15] A circuit diagram to explain the inverting drive mechanism. [Modes for carrying out the invention]

[0021] Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is largely... It is possible to carry out the invention in different ways, without departing from the spirit and scope of the present invention. It is easily understood by those skilled in the art that its form and details can be changed in various ways. This embodiment is not to be interpreted as being limited to the contents described below. In the structure of the invention, reference numerals indicating the same object shall be common across different drawings.

[0022] Furthermore, the size, layer thickness, signal waveform, or The area may be exaggerated in its representation for clarity. Therefore, it may not necessarily reflect the actual scale. Not limited to [specific type / method].

[0023] In this specification, the terms 1st, 2nd, 3rd, through nth (where n is a natural number) refer to the construction This is added to avoid confusion regarding the elements and does not imply a numerical limitation. ru.

[0024] (Embodiment 1) This embodiment describes the circuit configuration of the pixels of the display device. In the circuit diagram, multiple wires are used to supply different signals to multiple pixels at the same time. N data lines (also called signal lines) (where N is a natural number greater than or equal to 3) are used as the scan signal for the scan line. This section describes an example of supplying different video signals to multiple pixels.

[0025] Figure 1(A) shows the circuit configuration of pixels in a display device. In Figure 1(A), N lines ( N is a natural number greater than or equal to 3. Specifically, three data lines (also called signal lines) are used as data lines. This shows a circuit configuration for supplying different video signals to three different pixels. Pixel 101A consists of a transistor 104A (also called a selection transistor) and a display element section 1 It has 05A. The transistor 104A of pixel 101A has a gate terminal on scan line 103 One of the terminals connected to A, which becomes either the source terminal or the drain terminal (also called the first terminal) One terminal is connected to the first data line 102A, and the other terminal is connected to the display element unit 105A. Pixel 101B consists of transistor 104B (also called a selection transistor) and a display element section. It has 105B. The transistor 104B of pixel 101B has a gate terminal on scan line 10 One of the terminals connected to 3B, which becomes either the source terminal or the drain terminal (also called the first terminal). One terminal is connected to the second data line 102B, and the other terminal is connected to the display element unit 105B. Pixel 101C consists of transistor 104C (also called a selection transistor) and a display element. It has part 105C. The transistor 104C of pixel 101C has a gate terminal on scan line 1 One of the terminals connected to 03C, which becomes either the source terminal or the drain terminal (also called the first terminal). ) is connected to the third data line 102C, and the other terminal is connected to the display element unit 105C. Yes. The circuit configuration shown in Figure 1(A) described above is, for example, scan lines 103A to scan lines 1 03C simultaneously conducts transistors 104A and 104C (turns on and (Also known as) the first data line 102A is connected to the display element section 105A to the display element section 105C. This configuration is effective when supplying separate video signals via a third data line 102C.

[0026] When pixels are arranged in a matrix, the first data lines 102A to the third data lines 102C is provided in a direction approximately perpendicular to the scan lines 103A to 103C. Transistor 104A along the first data line 102A to the third data line 102C Pixels 101A to 101C having transistors 104C are provided. The difference between the circuit configuration shown in Figure 1(A) and the circuit configuration shown in Figure 15(A) above is the first In the region where data lines 102A to the third data line 102C are installed, the first data By providing an intersection of line 102A to the third data line 102C, the first data line 102 Each of the data lines A through the third, 102C, is connected to the corresponding pixels 101A through 101C. The goal is to place it in the closest proximity to one of the terminals of the included transistor. Connect one terminal of the device to the nearest data line.

[0027] Note that a pixel is the brightness of a single color element (for example, one of R (red), G (green), or B (blue)). It shall correspond to a display unit that can control the level of detail. Therefore, in the case of a color display device, The smallest display unit of a color image consists of three pixels: a red (R) pixel, a green (G) pixel, and a blue (B) pixel. The color elements for displaying a color image are not limited to three colors, but may include more than three colors. You can use the above, or you can use colors other than RGB.

[0028] Furthermore, a transistor has at least three terminals, including the gate, drain, and source. It is an element having a channel region between the drain region and the source region, and the drain Current can be passed through the channel region and the source region. Here, the source The source and drain vary depending on the transistor's structure and operating conditions, so which one is the source? It is difficult to determine whether it is a drain or not. Therefore, in this specification, The regions that function as both source and drain are sometimes not referred to as source or drain. In that case, one example would be to refer to them as "one terminal" and "the other terminal." Alternatively, they may be referred to as the first electrode (terminal) and the second electrode (terminal), respectively. Alternatively, they may be referred to as source area and drain area. Or, source terminal and drain It is sometimes referred to as a "rain terminal."

[0029] In this specification, when A and B are said to be connected, it means that A and B are not directly connected. This includes things that are electrically connected, in addition to things that are not connected. Here, A and B are electrically connected To be connected means that there is an object between A and B that has some kind of electrical effect. This represents the case where the part between A and B, which includes the object, becomes a node. Specifically, A and B are connected via switching elements such as transistors, and the switch When the conduction of the connecting element causes A and B to be at approximately the same potential, or when A and B are connected via a resistive element When B is connected, the potential difference generated across the resistor element affects the operation of the circuit including A and B. When considering the circuit operation, such as when the resonance is not noticeable, the part between A and B is the same This indicates a state where it is acceptable to treat it as a node.

[0030] Voltage is defined as the potential difference between a certain potential and a reference potential (for example, ground potential). It is often used to indicate these things. Therefore, voltage, potential, and potential difference are often rephrased as potential, voltage, and voltage difference, respectively. It is possible.

[0031] Regarding the structure of the transistors provided in the pixels, an inverse staggered structure is acceptable, or a forward staggered structure is also acceptable. A structure of this type is also acceptable. Alternatively, the channel region is divided into multiple regions and connected in series. A double-gate type structure is also acceptable. Alternatively, a design in which gate electrodes are provided above and below the channel region. A dual-gate structure is also acceptable. Furthermore, the semiconductor layers constituting the transistor can be arranged in multiple island-like configurations. It may also be formed from a semiconductor layer and used as a transistor element capable of performing switching operations.

[0032] In Figure 1(A), the intersection 106 is the second data line 102B and the third data line 102C This is the region where the two intersect. The intersection 107 is the region where the first data line 102A and the second data line This is the region where 102B intersects. Also, the intersection 108 is the region where the first data line 102A and the third This is the region where data line 102C intersects. The intersection 109 is the second data line 102B. This is the region where the first data line and the third data line 102C intersect. The intersection 110 is the region where the first data line This is the region where 102A and the second data line 102B intersect. The intersection 111 is the first This is the region where data line 102A and the third data line 102C intersect. The terminal wire 102A is located closest to one terminal of transistor 104A, and transistor 1 One terminal of 04A will be connected without crossing with other wiring. Data line 102B is located closest to one terminal of transistor 104B, One terminal of the ZISTA 104B will be connected without crossing any other wires. Furthermore, the third data line 102C is located closest to one terminal of transistor 104C. One terminal of transistor 104C is connected without crossing with other wires. And so it becomes.

[0033] The intersections 106 to 111 shown in Figure 1(A) are the first data lines 102A to the third data lines To avoid an electrical short circuit between data lines 102C, one of the intersecting data lines The other side will be formed using a different conductive layer. Intersection 106 to the intersection using the conductive layer In 111, a load capacitance is formed between intersecting data lines. The load capacitance is formed between intersecting data lines. The lines overlap to form a region, i.e., the first data line 102A to the third data line 102C. It is formed in the region where the conductive layer and another conductive layer at the intersection overlap.

[0034] Figure 1(B) shows the first data line 102A to the third data line 102 shown in Figure 1(A). This is a circuit diagram showing the intersections 106 to 111 by C as load capacitance. Figure 1(B In this case, similar to Figure 1(A), the first data line 102A is connected to the first pixel 101A. The second data line 102B is connected to the second pixel 101B, and the third data line 102C is It is connected to the third pixel 101C. Also, in Figure 1(B), the intersection 106 shown in Figure 1(A) The load capacitance resulting from is represented by the capacitive element 191, and the capacitance resulting from the intersection 107 shown in Figure 1(A) is represented by the capacitive element 191. The load capacitance is represented by the capacitive element 192, and the load capacitance caused by the intersection 108 shown in Figure 1(A) is Represented by capacitive element 193, the load capacitance caused by the intersection 109 shown in Figure 1(A) is represented by capacitive element 1 Represented by 94, the load capacitance caused by the intersection 110 shown in Figure 1(A) is represented by the capacitive element 195. The load capacitance resulting from the intersection 111 shown in Figure 1(A) is represented by the capacitive element 196.

[0035] As shown in Figure 1(B), the first data line 102A and the second data line 102B have a capacitance A load capacitance is formed by element 192 and capacitive element 195. Also, the second data line 10 Load capacitance by capacitive elements 191 and 194 between 2B and the third data line 102C A capacitive element is formed between the first data line 102A and the third data line 102C. A load capacitance is formed by 193 and the capacitive element 196. As mentioned above, the load capacitance is the first A conductive layer forming data lines 102A to the third data line 102C, and another conductive layer at the intersection. It is formed in the region where the electrolayer and the superimposed layer overlap. Therefore, in the configuration of this embodiment, the first The data lines 102A to the third data line 102C shall be data lines with equal wiring width. This allows for the formation of an evenly distributed load capacity on each of the data lines.

[0036] Therefore, in the configuration of this embodiment, the first data line 102A to the third data line 102C and Because the area of ​​the intersection formed by can be made equal, each data line can be treated equally. A load capacity can be formed. As a result, the first data line 102A to the third data The load capacitance between lines 102C can be equalized, and a signal of the desired potential can be supplied to each pixel. And the display device is affected by differences in load capacitance between the wires, resulting in a misalignment of the display grayscale and / or This can reduce signal delay.

[0037] Next, in Figures 2(A) and (B), the display element section 105A to the display element section shown in Figure 1(A) This section describes a specific example of a display element for the 105C. Note the explanations in Figures 2(A) and (B). Then, there is overlap with the configuration other than the display element section 105A to display element section 105C shown in Figure 1(A). I will omit the explanation for the parts that need to be done.

[0038] The circuit diagram shown in Figure 2(A) is the same as the display element section 105A to the display element section 10 shown in Figure 1(A). This shows an example of a configuration where 5C has a liquid crystal element. (Figure 2(A)) The display element section 105A serves as either the source terminal or the drain terminal of the transistor 104A. The liquid crystal element 121A and the capacitive element 122A are connected to one of the terminals (also called the second terminal). The display element section 105B shown in Figure 2(A) is connected to the source terminal of transistor 104B or The liquid crystal element 121B is connected to the other terminal (also called the second terminal), which serves as the drain terminal. It has a capacitance element 122B. The display element section 105C shown in Figure 2(A) is a transistor 1 Connect to the other terminal (also called the second terminal) which will be the source or drain terminal of 04C. It has liquid crystal elements 121C and capacitive elements 122C. Child 121C has one electrode (also called the pixel electrode or first electrode) connected to transistor 104A. It is connected to the other terminal of transistor 104C, and the other electrode (counter electrode, second electrode and The capacitive elements 122A to are connected to the common potential line (also called the common line). Capacitive element 122C has one electrode (also called the first electrode) connected to transistor 104A or to It is connected to the other terminal of the transistor 104C, and the other electrode (also called the second electrode) is capacitance It is connected to the wire. Capacitive elements 122A to 122C may be provided as needed. It can also be omitted.

[0039] The circuit diagram shown in Figure 2(B) is the same as the display element section 105A to the display element section 10 shown in Figure 1(A). 5C has a light-emitting element such as an EL (Electro-Luminescence) element. This shows an example of the case of production. The display element section 105A shown in Figure 2(B) is Transistor 124A for driving the optical element 123A and the light-emitting element 123A (drive transistor) It has a light-emitting element (also called a luminescent element). The display element section 105B shown in Figure 2(B) has a light-emitting element 123 Transistor 124B for driving B and light-emitting element 123B (also known as driving transistor) The display element section 105C shown in Figure 2(B) includes a light-emitting element 123C and a light-emitting element. It has a transistor 124C (also called a driving transistor) for driving child 123C. Note that transistors 124A to 124C have a gate terminal that is a transistor It is connected to the other terminal of transistor 104A or 104C, and is either the source terminal or the drain. One of the terminals (also called the first terminal) is connected to the light-emitting element 123A to 123C. It is connected to the current supply line (also called the power line) for conducting electric current, and is connected to the source terminal or drain. The other terminal (also called the second terminal) is a light-emitting element 123A to 123C It is connected to one of the electrodes (also called the first electrode). Light-emitting element 123A to light-emitting element 123 The other electrode of C (also called the second electrode) is connected to the ground line (also called the common potential line). The gate terminal of transistor 124A to transistor 124C and the first terminal are connected. A configuration in which a capacitive element is provided is also possible.

[0040] Next, the display element section 105A to the display element section 105C shown in Figure 2(A) has a liquid crystal element. The top view of the circuit diagram of the configuration is shown in detail, and the first data in one aspect of the present invention is shown. The area of ​​the intersection formed by line 102A to the third data line 102C is made equal, and the data We will now explain the advantage of being able to create an equal load capacity for each line.

[0041] The top view shown in Figure 3 corresponds to the top view of the circuit diagram shown in Figure 2(A). Note that in Figure 3, The capacitive elements 122A to 122C described in 2(A) will be omitted from this explanation, and the liquid crystal elements As a configuration corresponding to 121A to liquid crystal element 121C, liquid crystal element 121A to liquid crystal element 1 This shows one electrode 131A to the other electrode 131C (pixel electrode) of 21C. The first data line 102A to the third data line 102C shown in 3 are the scan lines 103A to In addition to the conductive layer (first conductive layer 141) arranged in a direction perpendicular to the line 103C, At intersections 106 to 111, the same conductive layer (second) as scan lines 103A to 103C It has a conductive layer 142).

[0042] In the top view shown in Figure 3, at intersections 106 to 111, the first conductive layer 141 and A load capacitance is formed in the region where the second conductive layer 142 is superimposed. Specifically, The first conductive layer 141 of the third data line 102C and the second conductive layer 141 of the second data line 102B A load capacitance is formed at the intersection 106 with the conductive layer 142 of the second data line. The first conductive layer 141 of 2A and the second conductive layer 142 of the second data line 102B A load capacitance is formed at the intersection 107 with the first data line 102A. The intersection 108 between the conductive layer 141 of the third data line 102C and the second conductive layer 142 of the third data line 102C A load capacitance is formed. Also, the first conductive layer 141 of the second data line 102B and A load capacitance is formed at the intersection 109 of the third data line 102C with the second conductive layer 142. It is done. Also, the first conductive layer 141 of the second data line 102B and the first data line 1 A load capacitance is formed at the intersection 110 with the second conductive layer 142 of 02A. The first conductive layer 141 of the third data line 102C and the third conductive layer 141 of the first data line 102A A load capacitance is formed at the intersection 111 with the conductive layer 142. Then the first data line 10 Between the 2A to the third data line 102C, the first conductive layer 141 and the second conductive layer 142 are used. The number of intersections formed (intersections 106 to 111) can be made equal. Therefore, the first data line 102A to the third data line 102C are wired with equal width. By using a single data line, it is possible to create an even load capacity on each of the data lines. Cut.

[0043] Therefore, in the configuration of this embodiment, the first data line 102A to the third data line 102C and Because the area of ​​the intersection formed by can be made equal, each data line can be treated equally. A load capacity can be formed. As a result, the first data line 102A to the third data The load capacitance between lines 102C can be equalized, and a signal of the desired potential can be supplied to each pixel. And the display device is affected by differences in load capacitance between the wires, resulting in a misalignment of the display grayscale and / or This can reduce signal delay.

[0044] Furthermore, in the first data line 102A to the third data line 102C shown in Figure 3, the first conductive By using conductive layers with different conductivity between layer 141 and the second conductive layer 142, the first data The wiring resistances of lines 102A through the third data line 102C are all different. Obtained. In Figure 4(A), the second conductive layer 142 in the top view shown in Figure 3 is used as a resistive element. This is the circuit diagram shown.

[0045] As shown in Figure 4(A), the second conductive layer 142 that constitutes the intersection 106 in Figure 3 is the second It is represented as the first resistive element 151B on the data line 102B. Also, the intersection in Figure 3 The second conductive layer 142 constituting the differential portion 107 has a second resistor that the second data line 102B has It is represented as the anti-element 152B. Also, the second conductive layer 1 that constitutes the intersection 108 in Figure 3 42 is represented as the first resistive element 151C of the third data line 102C. The second conductive layer 142 that constitutes the intersection 109 in Figure 3 has a third data line 102C. It is represented as the second resistive element 152C. Also, the second element that constitutes the intersection 110 in Figure 3 The conductive layer 142 of the second layer is represented as the first resistive element 151A of the first data line 102A. Furthermore, the second conductive layer 142 that constitutes the intersection 111 in Figure 3 is the first data line This is represented as the second resistive element 152A possessed by 102A.

[0046] As shown in Figure 4(A), in the configuration of this embodiment, the first data line 102A is the first resistor It has an anti-resistance element 151A and a second resistive element 152A, and the second data line 102B is the first resistive element It has an anti-resistance element 151B and a second resistive element 152B, and the third data line 102C is the first resistive element The configuration can include an anti-resistance element 151C and a second resistive element 152C. In the configuration of this embodiment, each of the first data line 102A to the third data line 102C The number of resistive elements in each can be made equal. Therefore, the second conductive layer 142 can be made the same By using electrical materials and constructing them with the same wiring width, the first data line 102A to the third data line 10 The wiring resistance of 2C can be made uniform.

[0047] Furthermore, the first resistor element 151 in the first data line 102A to the third data line 102C A to the first resistive element 151C and the second resistive element 152A to the second resistive element 152C It may be located at any point in the first data line 102A through the third data line 102C. For example, as shown in Figure 4(B), a second conductive layer 142 which acts as a resistive element is provided and formed. It can also be used as a composition.

[0048] In this embodiment, different signals are supplied to multiple pixels at the same timing. A display device configuration having a first data line to a third data line as multiple wirings for this purpose. As explained above, this method can be applied to other types of wiring as well. For example, as explained in Figure 2(B) In a configuration having light-emitting elements, current is passed through the light-emitting elements 123A to 123C. As shown in Figure 5, the current supply lines are the first current supply line 125A and the second current supply line 12 5B, the configuration is such that the third current supply line 125C is divided and crossing points 161 to 166 are provided. This may be done. First current supply line 125A, second current supply line 125B, third current supply line By providing intersections 161 to 166 in 125C, the first current supply Current supply line 125A to the third current supply line 125C to transistor 124A to transistor 1 It is placed in the closest vicinity of one terminal of 24C, and transistors 124A to 124 One terminal of C is connected to the first current supply line 125A to the third without crossing with other wiring. It can be connected to the current supply line 125C.

[0049] Therefore, in the configuration of this embodiment, the first data line 102A to the third data line 102C and Similarly, a uniform load capacity can be formed on each of the current supply lines. As a result, The load capacity of the first current supply line 125A to the third current supply line 125C is made equal, and each pixel It can supply a signal of the desired potential. The display device then detects the difference in load capacitance between the wires. This can reduce the misalignment of display gradations and / or signal delays caused by this.

[0050] As explained above, the goal is to reduce the difference in load capacity between data lines or current supply lines. This can be done. As a result, the misalignment of display grayscale and / or signal delay caused by differences in load capacity can be eliminated. It can be reduced.

[0051] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0052] (Embodiment 2) In this embodiment, a configuration different from that of Embodiment 1 will be explained in Figures 6 and 7. The configuration shown in this embodiment differs from the configuration shown in Figures 1 and 2 described in Embodiment 1 above. The key point is that multiple scan lines are provided as multiple wirings. Specifically, in this embodiment... The circuit diagram shows multiple wires for supplying different signals to multiple pixels at the same time. Using N scan lines (where N is a natural number greater than or equal to 3), different scan signals are supplied to multiple pixels. Let's explain with an example.

[0053] Figure 6(A) shows the circuit configuration of the pixels in the display device. In Figure 6(A), N lines Specifically, three scan lines supply different scan signals to three different pixels. The circuit configuration in this case is shown. Pixel 201A is a transistor 204A (selected It has a transistor (also called a transistor) and a display element section 205A. 204A has its gate terminal connected to the first scan line 203A, and its source terminal or drain. One terminal (also called the first terminal) is connected to data line 202A, and the other terminal This is connected to the display element section 205A. Pixel 201B is connected to transistor 204B (selected). It has a transistor (also called a transistor) and a display element section 205B. The transistor of pixel 201B T204B has its gate terminal connected to the second scan line 203B, and its source terminal or drag terminal One terminal, which will be the terminal (also called the first terminal), is connected to data line 202B, and the other terminal The child is connected to the display element section 205B. Pixel 201C is connected to transistor 204C (select It has a selector transistor (also called a selector transistor) and a display element section 205C. The transistor of the pixel 201C The st 204C has its gate terminal connected to the third scan line 203C, and the source terminal or DRE One terminal, which is the input terminal (also called the first terminal), is connected to data line 202C, and the other terminal is The terminal is connected to the display element unit 205C. The circuit configuration shown in Figure 6(A) described above is For example, the scanning signals of the first scan line 203A to the third scan line 203C cause the transistors By individually setting transistors 204A through 204C to be in a conductive state (also called the ON state), the table Data lines 202A to 202C are connected to the display element section 205A to the display element section 205C. This configuration is effective when supplying video signals.

[0054] When pixels are arranged in a matrix, the first scan line 203A to the third scan line 20 3C is provided in a direction approximately perpendicular to data lines 202A to 202C. Transistors 204A to 203C along the first scan line 203A to the third scan line 203C Pixels 201A to 201C, each having a transistor 204C, will be provided. The circuit configuration shown in Figure 6(A) is at the intersection of the first scan line 203A to the third scan line 203C. By providing this, each of the first scan line 203A to the third scan line 203C is corresponding to Displaced in the nearest vicinity of the gate terminal of the transistor included in pixels 201A to 201C Then, the gate terminal of the transistor is connected to the scan line located in the nearest vicinity.

[0055] In Figure 6(A), the intersection 206 is where the second scan line 203B and the third scan line 203C meet. This is the intersecting region. The intersection 207 is the first scan line 203A and the second scan line 203B. This is the region where the two lines intersect. The intersection 208 is the region where the first scan line 203A and the third scan line 20 This is the region where 3C intersects. The intersection 209 is the region where the second scan line 203B and the third scan line This is the region where 203C intersects. The intersection 210 is the region where the first scan line 203A and the second scan line intersect. This is the region where scan line 203B intersects. The intersection 211 is where the first scan line 203A and the third scan line 203A intersect. This is the region where scan line 203C intersects. And the first scan line 203A is a transistor It is located closest to the gate terminal of transistor 204A, and the gate terminal of transistor 204A is located near other terminals The connection will be made without crossing the line. Also, the second scan line 203B is a transistor It is located in the closest proximity to the gate terminal of transistor 204B, and the gate terminal of transistor 204B is The connection will be made without crossing with other wiring. Also, the third scan line 203C is It is located closest to the gate terminal of transistor 204C, and the gate of transistor 204C The terminals will be connected without crossing over other wires.

[0056] The intersections 206 to 211 shown in Figure 6(A) are the first scan line 203A to the third scan line To avoid an electrical short circuit between scan lines 203C, one of the intersecting scan lines is separated. The conductive layer will be used to form the intersection 206 to intersection 211 Then, a load capacitance is formed between the intersecting scan lines. The load capacitance is formed when the intersecting scan lines are superimposed. A conductive layer that forms the region, i.e., the first scan line 203A to the third scan line 203C, It is formed in the region where it overlaps with another conductive layer at the intersection.

[0057] Figure 6(B) shows the first scan line 203A to the third scan line 203C shown in Figure 6(A). This is a circuit diagram showing the intersections 206 to 211 as load capacitance. Similar to Figure 6(A), the first scan line 203A is connected to the first pixel 201A, and the second Scan line 203B is connected to the second pixel 201B, and the third scan line 203C is connected to the third pixel It is connected to 201C. Also, in Figure 6(B), the intersection 206 shown in Figure 6(A) is The load capacitance is represented by the capacitive element 291, and the load capacitance at the intersection 207 shown in Figure 6(A) is The capacitive element 292 represents the load capacitance caused by the intersection 208 shown in Figure 6(A), and the capacitive element 2 Represented by 93, the load capacitance caused by the intersection 209 shown in Figure 6(A) is represented by the capacitive element 294. The load capacitance caused by the intersection 210 shown in Figure 6(A) is represented by the capacitive element 295. The load capacitance caused by the intersection 211 shown by ) is represented by the capacitive element 296.

[0058] As shown in Figure 6(B), the first scan line 203A and the second scan line 203B are used to scan the capacitive element. A load capacitance is formed by 292 and the capacitive element 295. Also, the second scan line 203B and With the third scan line 203C, a load capacitance is formed by the capacitive elements 291 and 294. Furthermore, the first scan line 203A and the third scan line 203C are used to control the capacitance element 293 and the capacitance. A load capacitance is formed by the quantitative element 296. As mentioned above, the load capacitance is formed by the first scan line 20 A conductive layer forming 3A to the third scan line 203C is superimposed on another conductive layer at the intersection. It is formed in the region. Therefore, in the configuration of this embodiment, the first scan line 203A By making the third scan line 203C a scan line with the same width as the wiring, each of the scan lines This allows for the formation of an evenly distributed load capacity.

[0059] Therefore, in the configuration of this embodiment, the intersection with the first scan line 203A to the third scan line 203C Since the area of ​​the difference can be made equal, a load capacitance can be formed evenly on each of the scan lines. This is possible. As a result, the load between the first scan line 203A and the third scan line 203C is reduced. By equalizing the capacity, the scanning signal can be supplied to each pixel at the desired timing. The display device can reduce the delay of the scanning signal caused by differences in load capacitance between wirings. .

[0060] Next, in Figures 7(A) and (B), the display element section 205A to the display element section shown in Figure 6(A) This section describes a specific example of a display element for the 205C. Note the explanations for Figures 7(A) and (B). Then, there is overlap with the configuration other than the display element section 205A to display element section 205C shown in Figure 6(A). I will omit the explanation for the parts that need to be done.

[0061] The circuit diagram shown in Figure 7(A) is the same as the display element section 205A to the display element section 20 shown in Figure 6(A) This shows an example of a configuration where 5C has a liquid crystal element. (Figure 7(A)) The display element section 205A serves as either the source terminal or the drain terminal of the transistor 204A. The liquid crystal element 221A and the capacitive element 222A are connected to one of the terminals (also called the second terminal). The display element section 205B shown in Figure 7(A) is connected to the source terminal of transistor 204B or The liquid crystal element 221B is connected to the other terminal (also called the second terminal), which serves as the drain terminal. It has a capacitance element 222B. The display element section 205C shown in Figure 7(A) has a transistor 2 Connect to the other terminal (also called the second terminal) which will be the source or drain terminal of 04C. It has liquid crystal elements 221C and capacitive elements 222C. Child 221C has one electrode (also called the pixel electrode or first electrode) connected to transistor 204A. It is connected to the other terminal of transistor 204C, and the other electrode (counter electrode, second electrode and The capacitive elements 222A to are connected to the common potential line (also called the common line). Capacitive element 222C has one electrode (also called the first electrode) connected to transistor 204A or to It is connected to the other terminal of the transistor 204C, and the other electrode (also called the second electrode) is capacitance It is connected to the wire. Capacitive elements 222A to 222C may be provided as needed. It can also be omitted.

[0062] The circuit diagram shown in Figure 7(B) is the same as the display element section 205A to the display element section 20 shown in Figure 6(A) 5C has a light-emitting element such as an EL (Electro-Luminescence) element. This shows an example of the case of production. The display element section 205A shown in Figure 7(B) is Transistor 224A for driving the optical element 223A and the light-emitting element 223A (drive transistor) It has a light-emitting element (also called a luminescent element). The display element section 205B shown in Figure 7(B) has a light-emitting element 223 Transistor 224B (also known as driving transistor) for driving B and the light-emitting element 223B The display element section 205C shown in Figure 7(B) includes a light-emitting element 223C and a light-emitting element. It has a transistor 224C (also called a driving transistor) for driving the child 223C. Note that transistors 224A to 224C have a gate terminal that is a transistor It is connected to the other terminal of transistor 204A or 204C, and is either the source terminal or the drain. One of the terminals (also called the first terminal) is connected to the light-emitting element 223A to 223C. It is connected to the current supply line (also called the power line) for conducting electric current, and is connected to the source terminal or drain. The other terminal (also called the second terminal) is a light-emitting element 223A to 223C It is connected to one of the electrodes (also called the first electrode). Light-emitting element 223A to light-emitting element 223 The other electrode of C (also called the second electrode) is connected to the ground line (also called the common potential line). The gate terminal of transistor 224A to transistor 224C and the first terminal are connected. A configuration in which a capacitive element is provided is also possible.

[0063] Based on the above, the difference in load capacitance of scan lines can be reduced. As a result, the difference in load capacitance This can reduce the delay in the scanning signal caused by differences.

[0064] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0065] (Embodiment 3) In this embodiment, the field sequential method is used with the circuit configuration described in Embodiment 1. An example of a display device that performs the display will be explained with reference to Figures 8 to 11. In this explanation of a display device, we will describe it as a liquid crystal display device that uses liquid crystal elements as display elements.

[0066] <Example configuration of a liquid crystal display device> Figure 8(A) shows an example of the configuration of a liquid crystal display device. The liquid crystal display device shown in Figure 8(A) is , pixel section 30, scan line drive circuit 31, data line drive circuit 32 (also called signal line drive circuit) (u) Each is arranged in parallel or approximately parallel, and the potential is controlled by the scan line drive circuit 31. 3n scan lines 33 (where n is a natural number greater than or equal to 2) are arranged parallel or approximately parallel to each other. Furthermore, the potential is controlled by the data line drive circuit 32, and m lines (where m is a natural number greater than or equal to 2) ) First data line 341, m second data lines 342, and m third data lines 3 It has 43 and

[0067] Furthermore, the pixel section 30 is divided into three regions (regions 301 to 303), and each region It has multiple pixels arranged in a matrix (n rows x m columns). Each scan line 33 is a pixel Among the multiple pixels arranged in a matrix (3n rows x m columns) in the element part 30, any one It is connected to m pixels arranged in the row. Also, each first data line 341 is connected to region 30 In 1, among the multiple pixels 351 arranged in a matrix (n rows m columns), any It is connected to n pixels arranged in a column. Also, each second data line 342 is connected to region 302 In the above, among the multiple pixels 352 arranged in a matrix (n rows m columns), any of the columns It is connected to n pixels arranged in the region. In addition, each third data line 343 is connected to region 303. In the matrix (n rows, m columns), among the multiple pixels 353 arranged in a matrix, in any of the columns It is connected to the n pixels that are arranged. 43 is provided with an intersection 361 as described in the first embodiment above, and the first data Data lines 341 to the third data line 343 are connected to the transistors of pixels in regions 301 to 303. This configuration involves placing it in the nearest vicinity of one of the terminals. Therefore, the first data line 341 to the third A load capacity can be evenly formed on each of the data lines 343. As a result, each It is possible to supply a video signal of the desired potential to the pixel, which is due to differences in load capacitance between data lines. This can reduce the misalignment of display gradations and / or signal delays.

[0068] Furthermore, the scan line drive circuit 31 receives a start signal (GSP) for the scan line drive circuit from an external source. Clock signal (GCK) for the drive circuit, and drive power supply such as high power supply potential and low power supply potential. The following is input. In addition, the data line drive circuit 32 receives a start signal from an external source. Signal (SSP), clock signal for data line drive circuit (SCK), image signal (data1~ Signals such as data3) and drive power supplies such as high power supply potential and low power supply potential are input.

[0069] Figures 8(B) through 8(D) show examples of pixel circuit configurations. Specifically, Figure 8(B) Figure 8(C) is a diagram showing an example of the circuit configuration of a pixel 351 arranged in region 301, and Figure 8(C) is This figure shows an example of the circuit configuration of pixel 352 located in region 302, and Figure 8(D) shows region 3 This figure shows an example of the circuit configuration of pixel 353 located at 03. Pixel 351 is shown in Figure 8(B). In this configuration, the gate terminal is connected to the scan line 33, and one of the source and drain terminals is connected to the first data A transistor 3511 connected to wire 341, and one electrode of transistor 3511 A capacitive element connected to the source and the other terminal of the drain, with the other electrode connected to the capacitance line. 3512 and one electrode (pixel electrode) are the source and drain of transistor 3511. One terminal is connected to one electrode of the capacitive element 3512, and the other electrode (counter electrode) is connected to the opposite It includes a liquid crystal element 3514 connected to a wiring that supplies a potential shift.

[0070] The circuit configuration of pixel 352 shown in Figure 8(C) and pixel 353 shown in Figure 8(D) is the same as that of Figure 8( It is identical to pixel 351 shown in B). However, in pixel 352 shown in Figure 8(C), If either the source or drain of ZISTA 3521 is the second data line instead of the first data line 341 The point connected to line 342 is different from pixel 351 shown in Figure 8(B), and is shown in Figure 8(D). In component 353, one of the source and drain of transistor 3531 is connected to the first data line 34 Unlike pixel 351 shown in Figure 8(B), it is connected to the third data line 343 instead of line 1. .

[0071] <Example of configuration of scan line drive circuit 31> Figure 9(A) shows an example of the configuration of the scan line driving circuit 31 in the liquid crystal display device shown in Figure 8(A). This is a diagram. The scan line drive circuit 31 shown in Figure 9(A) has n output terminals. It has a zista 311 to a shift register 313. Each output terminal is connected to one of the n scan lines 33 arranged in region 301. Each of the output terminals of the shift register 312 is connected to n lines arranged in region 302 Each of the output terminals of the shift register 313, connected to one of the scan lines 33, is It is connected to one of the n scan lines 33 arranged in region 303. That is, shift Register 311 is a shift register that supplies a scan signal in region 301, and shift The shift register 312 is a shift register that supplies a scan signal in region 302, The shift register 313 is a shift register that supplies a scan signal in region 303. Specifically, the shift register 311 receives a starter input for the scan line drive circuit from an external source. The signal (GSP) triggers the sequential scanning starting from scan line 33 located on the first line. Shift the scan signal (scan line 33 every 1 / 2 cycle of the clock signal (GCK) for the scan line drive circuit) The shift register 312 has the function of sequentially selecting the scan line drive input from an external source. The scan line located in the (n+1)th row is triggered by the circuit start pulse signal (GSP). The shift register 313 has the function of sequentially shifting the scan signal starting from 33, and the shift register 313 is external The start pulse signal (GSP) for the scan line drive circuit input from 2n It has the function of sequentially shifting the scan signal starting from scan line 33 located on the first row.

[0072] <Example of operation of scan line drive circuit 31> An example of the operation of the scan line driving circuit 31 described above will be explained with reference to Figure 9(B). 9(B) contains the clock signal (GCK) for the scan line drive circuit and the shift register 311. The signal output from n output terminals (SR311out), the shift register 312 The signals output from the n output terminals (SR312out), and the shift register 31 This shows the signals (SR313out) output from the n output terminals of unit 3.

[0073] During the sampling period (T1), the shift register 311 receives the data placed in the first row. Starting from scan line 33, a high-level potential is 1 / 2 cross-sectional up to scan line 33 located in the nth row. The data is shifted sequentially with each scan period (horizontal scan period), and in the shift register 312, the (n+1)th row... Starting from the installed scan line 33, a high level of electricity is transmitted to the scan line 33 located in the 2nth row. The position shifts sequentially every 1 / 2 clock cycle (horizontal scan period), and in the shift register 313 Starting from scan line 33 located in row 2n+1, to scan line 33 located in row 3n Therefore, the high-level potential shifts sequentially every 1 / 2 clock cycle (horizontal scanning period). Therefore, the scan line drive circuit 31 drives m pixels 351 arranged in the first row via the scan line 33. The m pixels 351 located in row n are selected sequentially, and the pixels located in row n+1 are selected sequentially. From the m pixels 352 that have been selected, the m pixels 352 located in the 2n row are selected sequentially, and 2n+ Starting with m pixels 353 in the first row, then sequentially, m pixels 353 in the 3n row. A selection will be made. That is, the scan line drive circuit 31 will select three different lines for each horizontal scanning period. It is possible to supply scanning signals to 3m pixels that are arranged in a grid.

[0074] During sampling period (T2) and sampling period (T3), shift register 31 The operation of shift register 313 is the same as the sampling period (T1). The scan line drive circuit 31 specifies, for each horizontal scanning period, similar to the sampling period (T1). It is possible to supply scanning signals to 3m pixels arranged in 3 rows.

[0075] <Example configuration of data line drive circuit 32> Figure 10(A) shows an example configuration of the data line driving circuit 32 in the liquid crystal display device shown in Figure 8(A). This is a diagram. The data line drive circuit 32 shown in Figure 10(A) has m output terminals. A shift register 320, m transistors 321, m transistors 322, It has m transistors 323 and, The gate terminal of transistor 321 is The j-th output terminal (where j is a natural number between 1 and m) of the sub-register 320 is connected to the j-th output terminal. And one of the source and drain terminals is connected to the wiring that supplies the first image signal (data1). The source and drain terminals are connected, and the other terminals are located in the j-th column of the pixel section 30. It is connected to data line 341. Also, the gate terminal of transistor 322 is shifted. It is connected to the j-th output terminal (where j is a natural number between 1 and m) of the ZISTA 320, One of the terminals of the drain and the other of the cable is connected to the wiring that supplies the second image signal (data2). The other terminal of the source and drain is located in the j-th column of the pixel section 30. It was connected to line 342. Also, the gate terminal of transistor 323 is connected to the shift register. It is connected to the j-th output terminal (where j is a natural number between 1 and m) of 320, and the source and One terminal of the drain is connected to the wiring that supplies the third image signal (data3), and The other terminal of the drain and the third data line are located in the j-th column of the pixel section 30. 343 is connected.

[0076] In this case, the first image signal (data1) is obtained during the sampling period (T1). , the red (R) image signal (held in the pixel when the backlight illuminates red (R) The image signal is supplied to the first data line 341, and during the sampling period (T2), green The image signal (G) is supplied to the first data line 341, and during the sampling period (T3) The blue (B) image signal will be supplied to the first data line 341. Also, the second image The signal (data2) is the blue (B) image signal during the sampling period (T1). The data line 342 is supplied with the red (R) image signal during the sampling period (T2). The second data line 342 is supplied, and during the sampling period (T3), the green (G) image signal is transmitted. The signal will be supplied to the second data line 342. Also, the third image signal (data3) During the sampling period (T1), the green (G) image signal is transmitted to the third data line 343. During the sampling period (T2), the blue (B) image signal is supplied to the third data line 34. The signal is supplied to 3, and during the sampling period (T3), the red (R) image signal is transmitted to the third data line. It will be supplied to 343.

[0077] <Example of backlight configuration> Figure 10(B) shows the back panel located behind the pixel section 30 of the liquid crystal display device shown in Figure 8(A). This is a diagram showing an example of a light configuration. The backlight shown in Figure 10(B) is red (R), green (G It has multiple backlight units 36 equipped with light sources that emit three colors: blue (A), blue (B), and blue (B). Multiple backlight units 36 are arranged in a matrix and in a specific area It is possible to control the lighting of each individual pixel. Here, multiple pixels arranged in 3n rows and m columns As for the backlight, at least every k rows and m columns (here, k is n / 4) A backlight unit 36 ​​is provided, and the illumination of the backlight unit 36 ​​is independently controlled. This is possible. That is, the backlight illuminates at least the pixels of rows 1 through k. Backlight unit for pixels in rows 2n + 3k + 1 to 3n It has a mechanism that allows for independent control of the illumination of each backlight unit.

[0078] <Example of liquid crystal display operation> Figure 11 shows the scanning of the scanning signal and the timing of the backlight illumination in the liquid crystal display device described above. This is a diagram showing the process. The liquid crystal display device processes one line during the sampling period (T1). Select m pixels 351 located in the eye, then sequentially select m pixels 351 located in the nth row. , and m pixels 352 located in row n+1 to m pixels 3 located in row 2n Select 52 sequentially, and place m pixels 353 located in row 2n+1 into row 3n. By sequentially selecting m pixels 353, it is possible to input an image signal to each pixel. That is the case.

[0079] Furthermore, the scanning of the scanning signal in the liquid crystal display device shown in Figure 11 and the timing of the backlight illumination The area is defined as (rows 1 through n, row (n+1) through 2n, and row (2n+1) through 3n) Each eye scans the scanning signal and a backlight unit that displays a specific color (red (R), green (G) It is possible to set the timing to simultaneously illuminate the (B) or (C) light. In the liquid crystal display device of this embodiment, the sampling period (T1) to the sampling period (T3) The operation performed in ) forms an image in the pixel section 30. In this liquid crystal display device, the sampling period (T1) to the sampling period (T3) is 1 This corresponds to the frame duration.

[0080] <Regarding the liquid crystal display device of this embodiment> The liquid crystal display device of this embodiment has a first data line to which the configuration of Embodiment 1 can be applied. The 341 to the third data line 343 shall form an equal load capacity on each of the wires. This makes it possible to supply a video signal of the desired potential to each pixel, and between the data lines. This can reduce the misalignment of display gradations and / or signal delays caused by differences in load capacity. ru.

[0081] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0082] (Embodiment 4) In this embodiment, the plan view and cross-sectional view of the pixels of a display device, in this case a liquid crystal display device. An example will be explained using a diagram.

[0083] Figure 12(A) shows a plan view of one of the multiple pixels of the display panel. Figure 12(B) ) is a cross-sectional view along the dashed line AB in Figure 12(A).

[0084] In Figure 12(A), the wiring layers that will become the first to third data lines (source electrode layers) 1201A (including the source electrode layer 1201C and the drain electrode layer 1202) is shown in the upper and lower parts of the figure. They are arranged to extend in the direction (column direction). The wiring layer that becomes the scan line (gate electrode layer 1) (Including 203) are roughly orthogonal to source electrode layer 1201A to source electrode layer 1201C It is arranged to extend in the direction (left-right direction (row direction) in the diagram). Capacitive wiring layer 1204 This is in a direction that is approximately parallel to the gate electrode layer 1203, and is parallel to the source electrode layer 1201A. It extends in a direction roughly perpendicular to the source electrode layer 1201C (left-right direction (row direction) in the figure). They are arranged as follows. Note that the intersection 1209 is between the gate electrode layer 1203 and the capacitive wiring layer 12 Source electrode layers 1201B and 1201C intersect due to a wiring layer formed from the same layer as 04. It shows the process of doing so.

[0085] In Figure 12(A), the pixels of the display panel have a transient having a gate electrode layer 1203. A transistor 1205 is provided. On transistor 1205, there is an insulating film 1227, an insulating film 1228 and an interlayer film 1229 are provided.

[0086] The pixels of the display panel shown in Figures 12(A) and 12(B) are connected to transistor 1205. The transistor 1205 has a transparent electrode layer 1208 as the first electrode layer. Openings (contact holes) are formed in 1227, the insulating film 1228, and the interlayer film 1229. It is done. In the opening (contact hole), the transparent electrode layer 1208 and transistor 1 It is connected to 205.

[0087] The transistor 1205 shown in Figures 12(A) and 12(B) is connected via the gate insulating layer 1212. The semiconductor layer 1206 is disposed on the gate electrode layer 1203, and the semiconductor layer 1206 It has a source electrode layer 1201A and a drain electrode layer 1202 in contact with it. Also, a capacitive wiring layer 1204, gate insulating layer 1212, and drain electrode layer 1202 are stacked to form a capacitive element 1 It forms 207.

[0088] In addition, the first substrate 1218 on which the transistor 1205 is formed is arranged so as to overlap with the second substrate 1219 with the liquid crystal layer 1217 interposed therebetween. It is arranged so as to overlap with the second substrate 1219 with the liquid crystal layer 1217 interposed therebetween.

[0089] In FIG. 12(B), an example of using an inverted staggered transistor with a bottom gate structure as the transistor 1205 is shown, but the structure of the transistor applicable to the liquid crystal display device disclosed in this specification is not particularly limited. For example, a transistor with a top gate structure in which a gate electrode layer is arranged above a semiconductor layer via a gate insulating layer, and a staggered transistor and a planar transistor with a bottom gate structure in which a gate electrode layer is arranged below a semiconductor layer via a gate insulating layer can be used. Although an example of using an inverted staggered transistor with a bottom gate structure as the transistor 1205 is shown in FIG. 12(B), the structure of the transistor applicable to the liquid crystal display device disclosed in this specification is not particularly limited. For example, a transistor with a top gate structure in which a gate electrode layer is arranged above a semiconductor layer via a gate insulating layer, and a staggered transistor and a planar transistor with a bottom gate structure in which a gate electrode layer is arranged below a semiconductor layer via a gate insulating layer can be used. A transistor with a top gate structure in which a gate electrode layer is arranged above a semiconductor layer via a gate insulating layer, and a staggered transistor and a planar transistor with a bottom gate structure in which a gate electrode layer is arranged below a semiconductor layer via a gate insulating layer can be used. A staggered transistor and a planar transistor with a bottom gate structure in which a gate electrode layer is arranged below a semiconductor layer via a gate insulating layer can be used. And a planar transistor can be used.

[0090] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0091] (Embodiment 5) In this embodiment, examples of transistors applicable to the liquid crystal display device disclosed in this specification are shown. The structure of the transistor applicable to the liquid crystal display device disclosed in this specification is not particularly limited. For example, a top gate structure in which a gate electrode is arranged above a semiconductor layer via a gate insulating layer, or a staggered or planar bottom gate structure in which a gate electrode is arranged below a semiconductor layer via a gate insulating layer can be used. [[ID=..]] In addition, the transistor may have a single gate structure in which one channel formation region is formed, a double gate structure in which two are formed, or a triple gate structure in which three are formed. The transistor may have a single gate structure in which one channel formation region is formed, a double gate structure in which two are formed, or a triple gate structure in which three are formed. Or a triple gate structure in which three are formed. A dual gate having two gate electrode layers arranged via a gate insulating layer above and below it It may be of the type. An example of the cross-sectional structure of a transistor is shown below in FIGS. 13(A) to 13(D). as follows

[0092] Note that the transistors shown in FIGS. 13(A) to 13(D) use an oxide semiconductor as the semiconductor layer The merit of using an oxide semiconductor is that in the on state of the transistor, it has a high field-effect mobility (maximum value of 5 cm / Vsec or more, preferably a maximum value of 1 2 0 cm / Vsec to 150 cm 2 / Vsec), and in the off state of the transistor, it has a low 2 off current per unit channel width (for example, the off current per unit channel width is less than 1 aA / μm, more preferably less than 10 zA / μm, and less than 100 zA / μm at 85°C μm). That is, such characteristics can be obtained

[0093] The transistor 410 shown in FIG. 13(A) is one of the transistors with a bottom gate structure and is also called an inverse staggered transistor

[0094] The transistor 410 includes a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, a source electrode layer 405a, and a drain electrode layer 40 5b on a substrate 400 having an insulating surface. Further, an insulating film 407 that covers the transistor 410 and is laminated on the oxide semiconductor layer 403 is provided . A protective insulating layer 409 is further formed on the insulating film 407 .

[0095] The transistor 420 shown in FIG. 13(B) is a channel protection type (also called a channel stop type)[[ID=4⑨]] ​It is a type of bottom-gate structure called a (u) and is also known as an inverse staggered transistor.

[0096] The transistor 420 has a gate electrode layer 401 and a gate on a substrate 400 having an insulating surface. The insulating layer 402, the oxide semiconductor layer 403, and the channel formation region of the oxide semiconductor layer 403 An insulating layer 427 that functions as a channel protection layer, a source electrode layer 405a, and a drain electrode It includes layer 405b. Furthermore, a protective insulating layer 409 is formed covering transistor 420. ru.

[0097] The transistor 430 shown in Figure 13(C) is a bottom-gate type transistor, and has an insulating table. A gate electrode layer 401, a gate insulating layer 402, and a source electrode layer 4 are placed on a substrate 400 having a surface. It includes 05a, a drain electrode layer 405b, and an oxide semiconductor layer 403. Also, Transis An insulating film 407 is provided that covers the 430 and is in contact with the oxide semiconductor layer 403. A protective insulating layer 409 is further formed on 407.

[0098] In transistor 430, the gate insulating layer 402 is connected to the substrate 400 and the gate electrode layer 40 1 is provided in contact with the gate insulating layer 402, and the source electrode layer 405a and drain electrode layer 405b is provided in contact with it. And the gate insulating layer 402 and the source electrode layer 40 5a. An oxide semiconductor layer 403 is provided on the drain electrode layer 405b.

[0099] The transistor 440 shown in Figure 13(D) is one of the top-gate transistors. The transistor 440 has an insulating layer 437 and an oxide semiconductor layer on a substrate 400 having an insulating surface. Conductor layer 403, source electrode layer 405a, drain electrode layer 405b, gate insulating layer 402, and includes a gate electrode layer 401, and wiring layers 436a and 436b are provided in contact with and connected to a source electrode layer 405a and a drain electrode layer 405b, respectively. respectively.

[0100] In this embodiment, as described above, an oxide semiconductor layer 403 is used as the semiconductor layer. The oxide semiconductor used for the oxide semiconductor layer 403 may be a quaternary metal oxide such as an In-Sn- Ga-Zn-O-based oxide semiconductor, a ternary metal oxide such as an In-Ga-Zn-O-based oxide semiconductor, an In-Sn-Zn-O-based oxide semiconductor, an In-Al-Zn-O-based oxide semiconductor , a Sn-Ga-Zn-O-based oxide semiconductor, an Al-Ga-Zn-O-based oxide semiconductor, Sn- Al-Zn-O-based oxide semiconductor, a binary metal oxide such as an In-Zn-O-based oxide semiconductor , a Sn-Zn-O-based oxide semiconductor, an Al-Zn-O-based oxide semiconductor, a Zn-Mg-O-based oxide semiconductor, a Sn-Mg-O-based oxide semiconductor, an In-Mg-O-based oxide semiconductor, or an In -O-based oxide semiconductor, a Sn-O-based oxide semiconductor, a Zn-O-based oxide semiconductor, an In-Ga- O-based oxide semiconductor, etc. can be used. Further, the above oxide semiconductor may contain SiO2. Here, for example, the In-Ga-Zn-O-based oxide semiconductor means an oxide film having indium (I n), gallium (Ga), and zinc (Zn), and its stoichiometric ratio is not particularly limited. Further, elements other than In, Ga, and Zn may be included.

[0101] Further, for the oxide semiconductor layer 403, a thin film represented by the chemical formula InMO3(ZnO) m (m>0) can be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, as M, Ga, Ga and Al, Ga and Mn, or Ga and Co, etc. Other examples include Ga and Co.

[0102] Transistors 410, 420, and transistors using oxide semiconductor layer 403 Transistors 430 and 440 are designed to reduce the current value in the off state (off current value). Therefore, the capacitive element for holding electrical signals such as video signals in a pixel can be made smaller. It can be designed to be more efficient. Therefore, the aperture ratio of the pixels can be improved, and thus This has the effect of reducing power consumption.

[0103] Furthermore, transistors 410, 420, and transistors using the oxide semiconductor layer 403 are also included. Transistors 430 and 440 can reduce the off-current. Therefore, In basic operation, the retention time of electrical signals such as video signals can be extended, and the writing interval can also be extended. It can be set to be longer. Therefore, the period of one frame can be made longer, and the still image display period This reduces the frequency of refresh operations, resulting in a greater reduction in power consumption. It can be made more expensive. Also, the above transistors can be manufactured on the same substrate in either the drive circuit section or the pixel section. Because it can be manufactured in a single step, the number of components in a liquid crystal display device can be reduced.

[0104] There are no major restrictions on the substrates that can be used for the substrate 400 having an insulating surface, however Glass substrates such as borosilicate glass or aluminobrosilicate glass are used.

[0105] In transistors 410, 420, and 430 with a bottom gate structure... Alternatively, an insulating film that serves as an underlayer may be provided between the substrate and the gate electrode layer. These have the function of preventing the diffusion of impurity elements, such as silicon nitride film, silicon oxide film, and silicon nitride film. A laminated structure consisting of one or more films selected from silicon oxide films or silicon oxidnitride films. It can be formed in this way.

[0106] The materials for the gate electrode layer 401 are molybdenum, titanium, chromium, tantalum, tungsten, Metal materials such as aluminum, copper, neodymium, scandium, or compounds mainly composed of these materials It can be formed using gold material, either as a single layer or in layers.

[0107] The gate insulating layer 402 is formed using plasma CVD or sputtering, etc. A layer, silicon nitride layer, silicon oxide nitride layer, silicon nitride oxide layer, aluminum oxide layer , aluminum nitride layer, aluminum oxide nitride layer, aluminum oxide nitride layer, or aluminum oxide The humium layer can be formed as a single layer or in multiple layers. For example, the first gate insulating layer and Then, a silicon nitride layer (SiN) with a thickness of 50 nm to 200 nm is formed by plasma CVD. y (y>0)) is formed, and a second gate insulating layer with a thickness of 5 nm is applied on the first gate insulating layer. Above is a silicon oxide layer (SiO) of 300 nm or less. x (x>0)) is stacked, for a total film thickness of 20 The gate insulating layer is 0 nm thick.

[0108] Examples of conductive films used for the source electrode layer 405a and drain electrode layer 405b include Al A metal film containing an element selected from Cr, Cu, Ta, Ti, Mo, W, or the above Metal nitride films composed of these elements (titanium nitride film, molybdenum nitride film, tungsten nitride film) A film (or similar material) can be used. Also, either the underside or the topside of a metal film such as Al or Cu. Both sides have high melting point metal films such as Ti, Mo, and W, or metal nitride films of those metals (titanium nitride film). A configuration in which molybdenum nitride film and tungsten nitride film are stacked is also possible.

[0109] Wiring layer 436a and wiring layer 43 connected to source electrode layer 405a and drain electrode layer 405b The conductive film, such as 6b, is made of the same material as the source electrode layer 405a and the drain electrode layer 405b. It can be used.

[0110] Furthermore, source electrode layer 405a, drain electrode layer 405b (wiring formed from the same layer) The conductive film (including the layer) may be formed from a conductive metal oxide. Examples of oxides include indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO2). ), indium tin oxide alloy (In2O3-SnO2, abbreviated as ITO), zinc oxide alloy (In2O3-ZnO) or these metal oxide materials with silicon oxide Products containing corn can be used.

[0111] Insulating films 407 and 427 are provided above the oxide semiconductor layer, and an insulating layer 43 is provided below it. 7 is typically a silicon oxide film, a silicon oxide nitride film, an aluminum oxide film, or an acid Inorganic insulating films, such as aluminum nitride films, can be used.

[0112] Furthermore, the protective insulating layer 409 provided above the oxide semiconductor layer is made of silicon nitride film, a silicon nitride film, and Inorganic insulating films such as luminium film, silicon nitride film, and aluminum nitride film are used. It is possible.

[0113] Furthermore, a planarizing insulating film is used on the protective insulating layer 409 to reduce surface irregularities caused by transistors. A planarizing insulating film may be formed. Polyimide, acrylic, benzocyclobutene Organic materials such as the above can be used. In addition to the above organic materials, low dielectric constant materials (low -k material) etc. can be used. Multiple insulating films formed from these materials can be stacked. A planar insulating film may be formed by doing so.

[0114] A transistor containing an oxide semiconductor layer fabricated using this embodiment removes hydrogen and moisture. By removing impurities, the purity is increased, which reduces the off-current. The modified oxide semiconductor layer can be fabricated without undergoing processes such as laser irradiation, and is suitable for large-area substrates. This is preferable because it allows for the formation of transistors.

[0115] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0116] (Embodiment 6) The display devices disclosed herein can be applied to various electronic devices (including gaming machines). Yes, it is possible. Examples of electronic devices include television equipment (televisions, or television receivers). Monitors for computers, digital cameras, and digital video cameras (also known as digital cameras or digital video cameras) Cameras, digital photo frames, mobile phones (also called mobile phones or mobile phone devices), etc. portable game consoles, personal digital assistants, audio playback devices, and large game machines such as pachinko machines, etc. Examples of electronic devices equipped with the display device described in the above embodiment will be explained. ru.

[0117] Figure 14(A) shows an example of an e-book. The e-book shown in Figure 14(A) is housed in a casing 1 It consists of two enclosures, enclosure 700 and enclosure 1701. Enclosure 1700 and enclosure 1701 It is integrated by hinge 1704 and can be opened and closed. This allows it to perform actions similar to those of a book.

[0118] The display unit 1702 is incorporated into the housing 1700, and the display unit 1703 is incorporated into the housing 1701. It is included. Display units 1702 and 1703 are also configured to display a continuation screen. Yes, or you can configure it to display different screens. For example, text is displayed in the display unit on the right (display unit 1702 in Figure 14(A)), and the table on the left... An image can be displayed on the display unit (display unit 1703 in Figure 14(A)).

[0119] Furthermore, Figure 14(A) shows an example in which the housing 1700 is equipped with an operating section, etc. Unit 1700 is equipped with a power input terminal 1705, operation keys 1706, speaker 1707, etc. It is located on the same surface as the display unit of the casing. The page can be turned using operation key 1706. The configuration may also include a keyboard, pointing device, etc. Also, the back of the casing... On the side, there are external connection terminals (earphone terminal, USB terminal, and various cables such as USB cables). The device may also be configured to include terminals that can be connected to a cable, a recording medium insertion section, etc. Furthermore, Figure The e-book shown in 14(A) may be configured to function as an electronic dictionary.

[0120] Figure 14(B) shows an example of a digital photo frame using a display device. The digital photo frame shown in Figure 14(B) has a display unit 1712 integrated into the housing 1711. It is included. The display unit 1712 is capable of displaying various images, for example, digital By displaying image data taken with a digital camera, etc., it functions just like a regular photo frame. It can be done.

[0121] The digital photo frame shown in Figure 14(B) includes an operating unit and an external connection terminal (USB). It is equipped with terminals, terminals that can connect to various cables such as USB cables, a recording medium insertion section, etc. The configuration shall be such that these components may be incorporated on the same surface as the display unit, but may also be on the sides or back. Placing it on the surface is preferable because it improves the design. For example, the markings on a digital photo frame. Insert a memory device containing image data taken with a digital camera into the recording medium insertion slot and the image will be displayed. The system can import data and display the imported image data on the display unit 1712.

[0122] Figure 14(C) shows an example of a television system using a display device. The television device shown has a display unit 1722 incorporated into the housing 1721. With 1722, it is possible to display images. Also, here, stand 1723 This shows a configuration in which the housing 1721 is supported. The display unit 1722 is in the above embodiment. The displayed display device can be applied.

[0123] The television equipment shown in Figure 14(C) is operated using the control switches provided on the housing 1721, This can be done using a separate remote control unit. The remote control unit has operation keys. It allows you to control the channel and volume, and to operate the image displayed on the display unit 1722. It is possible to display the information output from the remote control unit on the remote control unit. A display unit may also be provided.

[0124] Figure 14(D) shows an example of a mobile phone using a display device. The mobile phone includes a display unit 1732 built into the casing 1731, as well as operation buttons 1733, Control buttons 1737, external connection port 1734, speaker 1735, and microphone 1736 It is equipped with the following features.

[0125] The mobile phone shown in Figure 14(D) has a touch panel display unit 1732, which can be touched by fingers, etc. The display content of the display unit 1732 can be operated by touch. In addition, telephone calls can be made, or For example, creating emails can be done by touching the display unit 1732 with a finger or the like.

[0126] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case. [Explanation of Symbols]

[0127] 101A pixels 101B pixels 101C pixels 102A First data line 102B Second data line 102C Third data line 103A scan line 103B scan line 103C scan line 104A Transistor 104B transistor 104C transistor 105A Display element section 105B Display element section 105C Display element section 106 Intersection 107 Intersection 108 Intersection 109 Intersection 110 Intersection 111 Intersection 121A Liquid Crystal Element 121B Liquid Crystal Element 121C liquid crystal element 122A Capacitive element 122B Capacitive element 122C Capacitive element 123A Light-emitting element 123B Light-emitting element 123C light-emitting element 124A Transistor 124B Transistor 124C Transistor 125A First current supply line 125B Second current supply line 125C Third current supply line 131A One electrode 131B One electrode 131C One electrode 141 First conductive layer 142 Second conductive layer 161 Intersection 162 Intersection 163 Intersection 164 Intersection 165 Intersection 166 Intersection 191 Capacitive element 192 Capacitive elements 193 Capacitive elements 194 Capacitive elements 195 Capacitive element 196 Capacitive elements 201A pixels 201B pixels 201C pixels 202A Data Line 202B data line 202C data line 203A First scan line 203B Second scan line 203C Third scan line 204A Transistor 204B transistor 204C Transistor 205A Display element section 205B Display Element Section 205C Display Element Section 206 Intersection 207 Intersection 208 Intersection 209 Intersection 210 Intersection 211 Intersection 221A Liquid Crystal Element 221B Liquid Crystal Element 221C liquid crystal element 222A Capacity 222B Capacitance element 222C Capacitive Sensor 223A Light-emitting element 223B Light-emitting element 223C light-emitting element 224A Transistor 224B transistor 224C Transistor 291 Capacitive elements 292 Capacitive elements 293 Capacitive elements 294 Capacitive elements 295 Capacitive element 296 Capacitive elements 30-pixel section 31 Scan line drive circuit 32 Data Line Drive Circuit 33 scan lines 301 area 302 areas 303 areas 311 Shift Register 312 Shift Register 313 Shift Register 320 Shift Registers 321 Transistors 322 transistors 323 Transistors 341 First data line 342 Second data line 343 Third data line 351 pixels 352 pixels 353 pixels 3511 Transistor 3512 Capacitive element 3514 Liquid crystal element 3521 Transistor 3531 Transistors 36 Backlight Units 361 Intersection 400 circuit boards 401 Guard Layer 402 Gate Insulation Layer 403 Oxide semiconductor layer 405a Source electrode layer 405b Drain electrode layer 407 Insulating film 409 Protective insulating layer 410 transistors 420 transistors 427 Insulating layer 430 transistors 436a Wiring layer 436b wiring layer 437 Insulating layer 440 transistors 1201A Source electrode layer 1201B Source electrode layer 1201C Source Electrode Layer 1202 Drain electrode layer 1203 Guard Layer 1204 Capacitive wiring layer 1205 Transistor 1206 Semiconductor layer 1207 Capacitive element 1208 Transparent electrode layer 1209 Intersection 1212 Gate Insulation Layer 1217 Liquid crystal layer 1218 First substrate 1219 Second substrate 1227 Insulating film 1228 Insulating film 1229 Interlaminar 1501A pixels 1501B pixels 1501C pixels 1502A Data line 1 1502B Second data line 1502C Third data line 1503A scan line 1503B scan line 1503C scan line 1504A Transistor 1504B Transistor 1504C Transistor 1505A Display element section 1505B Display element section 1505C Display Element Section 1506 Intersection 1507 Intersection 1516 Load capacity 1517A load capacity 1517B load capacity 151A Resistor 151B Resistor 151C Resistor 152A Resistor 152B Resistor 152C Resistor 1700 cabinets 1701 Casing 1702 Display section 1703 Display section 1704 Hinge 1705 Power input terminal 1706 Operation Keys 1707 Speaker 1711 cabinet 1712 Display section 1721 cabinet 1722 Display section 1723 Stand 1731 cabinet 1732 Display section 1733 Operation Buttons 1734 External connection port 1735 Speaker 1736 Mike 1737 Operation Buttons

Claims

1. It has a first pixel and a second pixel arranged adjacent to each other, a first data line and a second data line, The first pixel comprises a first transistor and a first display element, The second pixel comprises a second transistor and a second display element, The source or drain of the first transistor is electrically connected to the first data line. The source or drain of the second transistor is electrically connected to the second data line in a display device, A first conductive film having a region that functions as a first data line and extends in a first direction, A second conductive film having a function as a second data line and a region extending in the first direction, It has a third conductive film that is electrically connected to the second conductive film and intersects with the first conductive film, The third conductive film is arranged in the pixel portion. In a plan view, the first conductive film has a region positioned between the third conductive film and the first pixel electrode of the first display element. In a plan view, the second conductive film has a region positioned between the first conductive film and the second pixel electrode of the second display element. Display device.

2. It has a first pixel and a second pixel arranged adjacent to each other, a first data line and a second data line, The first pixel comprises a first transistor and a first display element, The second pixel comprises a second transistor and a second display element, The source or drain of the first transistor is electrically connected to the first data line. The source or drain of the second transistor is electrically connected to the second data line in a display device, A first conductive film having a region that functions as a first data line and extends in a first direction, A second conductive film having a function as a second data line and a region extending in the first direction, It has a third conductive film that is electrically connected to the second conductive film and intersects with the first conductive film, The third conductive film is arranged in the pixel portion. The first conductive film and the second conductive film are arranged to be separated from each other in a plan view. In a plan view, the first conductive film has a region positioned between the third conductive film and the first pixel electrode of the first display element. In a plan view, the second conductive film has a region positioned between the first conductive film and the second pixel electrode of the second display element. Display device.

3. It has a first pixel and a second pixel arranged adjacent to each other, a first data line and a second data line, The first pixel comprises a first transistor and a first display element, The second pixel comprises a second transistor and a second display element, The source or drain of the first transistor is electrically connected to the first data line. The source or drain of the second transistor is electrically connected to the second data line in a display device, A first conductive film having a region that functions as a first data line and extends in a first direction, A second conductive film having a function as a second data line and a region extending in the first direction, It has a third conductive film that is electrically connected to the second conductive film and intersects with the first conductive film, The third conductive film is arranged in the pixel portion. The first conductive film and the second conductive film each have a region disposed on an insulating surface. The first conductive film and the second conductive film are arranged to be separated from each other in a plan view. In a plan view, the first conductive film has a region positioned between the third conductive film and the first pixel electrode of the first display element. In a plan view, the second conductive film has a region positioned between the first conductive film and the second pixel electrode of the second display element. Display device.

4. It has a first pixel and a second pixel arranged adjacent to each other, a first data line and a second data line, The first pixel comprises a first transistor and a first display element, The second pixel comprises a second transistor and a second display element, The source or drain of the first transistor is electrically connected to the first data line. The source or drain of the second transistor is electrically connected to the second data line in a display device, A first conductive film having a region that functions as a first data line and extends in a first direction, A second conductive film having a function as a second data line and a region extending in the first direction, It has a third conductive film that is electrically connected to the second conductive film and intersects with the first conductive film, The third conductive film is arranged in the pixel portion. The first conductive film and the second conductive film are arranged to be separated from each other in a plan view. The second conductive film has a region, in a plan view, that is located between the first conductive film and the semiconductor film of the second transistor. In a plan view, the first conductive film has a region positioned between the third conductive film and the first pixel electrode of the first display element. In a plan view, the second conductive film has a region positioned between the first conductive film and the second pixel electrode of the second display element. Display device.

5. It has a first pixel and a second pixel arranged adjacent to each other, a first data line and a second data line, The first pixel comprises a first transistor and a first display element, The second pixel comprises a second transistor and a second display element, The source or drain of the first transistor is electrically connected to the first data line. The source or drain of the second transistor is electrically connected to the second data line in a display device, A first conductive film having a region that functions as a first data line and extends in a first direction, A second conductive film having a function as a second data line and a region extending in the first direction, It has a third conductive film that is electrically connected to the second conductive film and intersects with the first conductive film, The third conductive film is arranged in the pixel portion. The first conductive film and the second conductive film each have a region disposed on an insulating surface. The first conductive film and the second conductive film are arranged to be separated from each other in a plan view. The second conductive film has a region, in a plan view, that is located between the first conductive film and the semiconductor film of the second transistor. In a plan view, the first conductive film has a region positioned between the third conductive film and the first pixel electrode of the first display element. In a plan view, the second conductive film has a region positioned between the first conductive film and the second pixel electrode of the second display element. Display device.

6. In any one of claims 1 to 5, The first conductive film intersects with the scan line electrically connected to the gate of the first transistor. Display device.

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