Semiconductor devices and semiconductor modules
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- FUJI ELECTRIC CO LTD
- Filing Date
- 2022-03-30
- Publication Date
- 2026-08-04
Smart Images
Figure 0007899562000001 
Figure 0007899562000002 
Figure 0007899562000003
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor device and a semiconductor module.
Background Art
[0002] Patent Document 1 describes that "a clip CL is electrically connected to an anode electrode AE via a plating film NP and solder SO2". [Prior Art Document] [Patent Document] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2014-099444 Patent Document 2: Japanese Unexamined Patent Application Publication No. 2016-111290 Patent Document 3: Japanese Unexamined Patent Application Publication No. 2017-059720 Patent Document 4: Japanese Unexamined Patent Application Publication No. 2007-115853 Patent Document 5: Japanese Unexamined Patent Application Publication No. 2013-234343 Patent Document 6: Japanese Unexamined Patent Application Publication No. 2003-297868 Patent Document 7: Japanese Unexamined Patent Application Publication No. 2003-324120
[0003] A semiconductor device that suppresses the occurrence of cracks is provided.
Summary of the Invention
[0004] In a first aspect of the present invention, a front surface side metal layer provided above a semiconductor substrate, a plating layer provided on the upper surface of the front surface side metal layer, a barrier layer provided on the upper surface of the front surface side metal layer and directly contacting the plating layer on the upper surface of the front surface side metal layer, and an insulating protection layer provided above the barrier layer are provided, and a semiconductor device is provided.
[0005] The thickness of the front surface side metal layer may be thicker than the thickness of the plating layer and thicker than the thickness of the barrier layer in the depth direction of the semiconductor substrate.
[0006] The thickness of the metal layer on the front side may be 1.0 μm or more and 6.0 μm or less in the depth direction of the semiconductor substrate.
[0007] The material of the metal layer on the front side may include at least one of an aluminum-silicon alloy, an aluminum-silicon-copper alloy, or an aluminum-neodymium alloy.
[0008] The thickness of the barrier layer may be thinner than the thickness of the plating layer in the depth direction of the semiconductor substrate.
[0009] The thickness of the barrier layer may be 30.0 nm or more and 300.0 nm or less in the depth direction of the semiconductor substrate.
[0010] The barrier layer material may include at least one of TiN, TiW, W, Cr, Mo, Ta, Nb, or Si3N4.
[0011] The thickness of the plating layer may be 3.0 μm or more and 6.0 μm or less in the depth direction of the semiconductor substrate.
[0012] The aforementioned plating layer may be a nickel plating layer.
[0013] The plating layer may be provided in a direction parallel to the front surface of the semiconductor substrate, extending from the upper surface of the front-side metal layer to the upper surface of the barrier layer.
[0014] The thickness of the insulating protective layer may be greater than the thickness of the barrier layer in the depth direction of the semiconductor substrate.
[0015] The thickness of the insulating protective layer may be 1.0 μm or more and 10.0 μm or less in the depth direction of the semiconductor substrate.
[0016] The insulating protective layer material may include at least one of polyimide or polybenzoxazole.
[0017] The insulating protective layer may be provided to overlap from above the barrier layer to above the plating layer in a direction parallel to the front surface of the semiconductor substrate. An end portion of the insulating protective layer may terminate above the plating layer.
[0018] The area where the insulating protective layer overlaps the plating layer provided in the opening of the barrier layer may be larger than 0% and 10% or less of the contact area between the plating layer and the front surface side metal layer.
[0019] The distance where the insulating protective layer overlaps the plating layer provided in the opening of the barrier layer may be equal to or greater than the thickness of the plating layer.
[0020] The insulating protective layer may be provided with an opening extending from above the front surface side metal layer to above the barrier layer in a direction parallel to the front surface of the semiconductor substrate.
[0021] The barrier layer may be provided with an opening above the front surface side metal layer. The opening end of the insulating protective layer and the opening end of the barrier layer may be separated by a distance equal to or greater than the thickness of the plating layer in a direction parallel to the front surface of the semiconductor substrate. [[ID=1 [Figure 1] An example of a cross-sectional view of the semiconductor device 100 is shown. [Figure 2] An example of the configuration of the semiconductor module 200 is shown. [Figure 3] A modified example of the configuration of the semiconductor module 200 is shown. [Figure 4A] An example of the configuration of the semiconductor module 500 of the comparative example is shown. [Figure 4B] An example of the configuration of the semiconductor module 500 of the comparative example is shown. [Figure 5A] It is a cross-sectional view during the manufacturing process of the semiconductor device 100 shown in FIG. 2. [Figure 5B] It is a cross-sectional view during the manufacturing process of the semiconductor device 100 shown in FIG. 2. [Figure 5C] It is a cross-sectional view during the manufacturing process of the semiconductor device 100 shown in FIG. 2. [Figure 5D] It is a cross-sectional view during the manufacturing process of the semiconductor device 100 shown in FIG. 2. [Figure 5E] It is a cross-sectional view during the manufacturing process of the semiconductor device 100 shown in FIG. 2. [Figure 5F] It is a cross-sectional view during the manufacturing process of the semiconductor module 200 shown in FIG. 2. [Figure 6A] It is a cross-sectional view during the manufacturing process of the semiconductor device 100 shown in FIG. 3. [Figure 6B] It is a cross-sectional view during the manufacturing process of the semiconductor device 100 shown in FIG. 3. [Figure 6C] It is a cross-sectional view during the manufacturing process of the semiconductor device 100 shown in FIG. 3. [Figure 6D] It is a cross-sectional view during the manufacturing process of the semiconductor device 100 shown in FIG. 3. [Figure 6E] It is a cross-sectional view during the manufacturing process of the semiconductor device 100 shown in FIG. 3. [Figure 6F] It is a cross-sectional view during the manufacturing process of the semiconductor module 200 shown in FIG. 3.
Embodiments for Carrying Out the Invention
[0026] The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.
[0027] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top," "bottom," "front," and "back" are not limited to the direction of gravity or the direction of attachment to the substrate, etc., when mounting a semiconductor device.
[0028] In this specification, technical matters may be described using the orthogonal coordinate axes of the X, Y, and Z axes. In this specification, the plane parallel to the top surface of the semiconductor substrate is defined as the XY plane, and the depth direction of the semiconductor substrate is defined as the Z axis. In this specification, the view of the semiconductor substrate in the Z-axis direction is referred to as a plan view.
[0029] In each embodiment, an example is shown where the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment will have opposite polarities.
[0030] In this specification, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower doping concentrations, respectively, compared to layers or regions without these prefixes.
[0031] Figure 1 shows an example of a cross-sectional view of a semiconductor device 100. The semiconductor device 100 comprises a source region 12, a base region 14, a contact region 15, a drift region 18, and a first conductivity region 20, all of which are provided on a semiconductor substrate 10.
[0032] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 has a front surface 21 and a back surface 23.
[0033] The front-side metal layer 52 is provided above the semiconductor substrate 10. A portion of the front-side metal layer 52 may be in contact with the front surface 21. The front-side metal layer 52 may be a metal film of Al (aluminum) or an alloy containing Al. The material of the front-side metal layer 52 may include at least one of an aluminum-silicon alloy, an aluminum-silicon-copper alloy, or an aluminum-neodymium alloy. The front-side metal layer 52 may also be a laminated film in which a metal film of Al or an alloy containing Al is laminated on a barrier metal layer such as Ti (titanium).
[0034] The back-side metal layer 24 is provided below the semiconductor substrate 10. In this example, the back-side metal layer 24 is provided in contact with the back surface 23. The back-side metal layer 24 is formed of a material containing metal. The back-side metal layer 24 may be a metal film of Al or an alloy containing Al. The material of the back-side metal layer 24 may include at least one of an aluminum-silicon alloy, an aluminum-silicon-copper alloy, or an aluminum-neodymium alloy. The back-side metal layer 24 may be a laminated film in which a metal film of Al or an alloy containing Al is laminated on a barrier metal layer such as Ti (titanium). Alternatively, the back-side metal layer 24 may be a laminated film in which a titanium layer is formed first, followed by metal films of nickel and gold in that order. The back-side metal layer 24 may also be a laminated film of titanium, nickel, and silver.
[0035] The drift region 18 is a region of a first conductivity type provided on the semiconductor substrate 10. In this example, the drift region 18 is N-type. The drift region 18 may be a region remaining on the semiconductor substrate 10 without other doping regions being formed. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.
[0036] The base region 14 is a second conductivity type region provided on the front surface 21 of the semiconductor substrate 10. In this example, the base region 14 is P-type.
[0037] The source region 12 is a region of a first conductivity type provided on the front surface 21 of the semiconductor substrate 10. In this example, the source region 12 is of the N+ type. The source region 12 is provided above the base region 14.
[0038] The contact region 15 is a second conductivity type region provided on the front surface 21 of the semiconductor substrate 10. The doping concentration of the contact region 15 is greater than that of the base region 14. In this example, the contact region 15 is P+ type. The contact region 15 is provided inside the base region 14. In this example, the contact region 15 is provided between two adjacent source regions 12, in contact with the two source regions 12.
[0039] The first conductivity type region 20 is provided on the semiconductor substrate 10 on the back surface 23 side of the drift region 18. The doping concentration of the first conductivity type region 20 is greater than that of the drift region 18. In this example, the first conductivity type region 20 is N+ type. The first conductivity type region 20 may be a seed crystal substrate of the semiconductor substrate 10. The drift region 18 may be formed on the first conductivity type region 20 by epitaxial growth.
[0040] The gate electrode 44 is provided with a gate insulating film 42 sandwiched between it and the semiconductor substrate 10. An interlayer insulating film 46 is provided on the top and side surfaces of the gate electrode 44. That is, the periphery of the gate electrode 44 may be covered with the gate insulating film 42 and the interlayer insulating film 46. The gate electrode 44 may be provided between a plurality of source regions 12 in a direction parallel to the front surface 21. A base region 14 and a drift region 18 may be provided below the gate electrode 44.
[0041] The semiconductor device 100 may be a power semiconductor device for controlling power, etc. The semiconductor device 100 in this example may have a vertical semiconductor structure with a back-side metal layer 24 on the back surface 23 side of the semiconductor substrate 10. However, the semiconductor device 100 may also have a horizontal semiconductor structure without a metal layer on the back surface 23 side.
[0042] In this example, a planar gate MOSFET is used as an example of semiconductor device 100. However, semiconductor device 100 may be a trench gate MOSFET or another semiconductor device such as a diode. Semiconductor device 100 may also be a wide bandgap MOSFET made of SiC or GaN.
[0043] If the semiconductor substrate 10 is SiC, the N-type dopant may be one or more elements from N (nitrogen) and P (phosphorus), and the P-type dopant may be one or more elements from Al and B (boron). If the semiconductor substrate 10 is GaN, the N-type dopant may be one or more elements from Si (silicon), Ge (germanium), S (sulfur), and O (oxygen), and the P-type dopant may be one or more elements from Mg (magnesium), Ca (calcium), Be (beryllium), and Zn (zinc).
[0044] Figure 2 shows an example of the configuration of a semiconductor module 200. The semiconductor module 200 in this example includes a semiconductor device 100. The semiconductor device 100 in this example includes a barrier layer 60, a plating layer 62, and an insulating protective layer 38 above the front-side metal layer 52 shown in Figure 1. The semiconductor module 200 also includes an adhesive layer 210, a lead frame 220, and a filling layer 230.
[0045] The barrier layer 60 is provided on the upper surface of the front metal layer 52. The barrier layer 60 has an opening 160 above the front metal layer 52. This exposes the upper surface of the front metal layer 52, allowing the plating layer 62 to grow. As described later, the plating layer 62 may grow in a direction parallel to the front surface 21. The barrier layer 60 may be provided in direct contact with the plating layer 62 on the upper surface of the front metal layer 52. The end E60 of the barrier layer 60 may be provided above the front metal layer 52, below the plating layer 62, or below the insulating protective layer 38.
[0046] The barrier layer 60 may contain conductive materials or insulating materials. The material of the barrier layer 60 may not be a catalyst for growing the plating layer 62. The material of the barrier layer 60 may be different from the material of the front metal layer 52. The material of the barrier layer 60 may contain at least one of TiN, TiW, W, Cr, Mo, Ta, Nb, or Si3N4.
[0047] The plating layer 62 is provided on the upper surface of the front-side metal layer 52. The plating layer 62 constitutes the pad electrodes on the upper surface of the semiconductor device 100. The plating layer 62 is formed by growing starting from the upper surface of the front-side metal layer 52. That is, the plating layer 62 does not grow beyond the region where the upper surface of the front-side metal layer 52 is covered by the barrier layer 60. However, the plating layer 62 may grow in a direction parallel to the front surface 21 of the semiconductor substrate 10, and may grow to cover the upper surface of the barrier layer 60. The barrier layer 60 and the plating layer 62 may be provided adjacent to each other in a direction parallel to the front surface 21. The end E62 of the plating layer 62 may be provided above the front-side metal layer 52, above the barrier layer 60, and below the insulating protective layer 38.
[0048] The plating layer 62 contains a conductive material. The material of the plating layer 62 may be different from the material of the front metal layer 52 and may be different from the material of the barrier layer 60. The plating layer 62 may be a nickel plating layer. The plating layer 62 may be another plating layer, such as a copper plating layer.
[0049] The insulating protective layer 38 is provided above the barrier layer 60. The insulating protective layer 38 may be provided on the upper surface of the plating layer 62, in contact with the plating layer 62. In this example, the insulating protective layer 38 extends from the upper surface of the barrier layer 60 to the upper surface of the plating layer 62. The material of the insulating protective layer 38 may include at least one of polyimide (PI) or polybenzoxazole (PBO). The end E38 of the insulating protective layer 38 is provided spaced apart from the end E62 of the plating layer 62. The end E38 of the insulating protective layer 38 may be provided above the front side metal layer 52, or above the plating layer 62. The end E38 may be located inside the end E60 of the barrier layer 60 on the front surface 21 of the semiconductor substrate 10. The end E38 may be located inside the end E62 of the plating layer 62 on the front surface 21 of the semiconductor substrate 10. In this cross-sectional view, "inside" refers to the positive side in the X-axis direction with the plating layer 62 as the center, and "outside" refers to the negative side in the X-axis direction with the plating layer 62 as the center.
[0050] The adhesive layer 210 is provided between the lead frame 220 and the semiconductor device 100. The adhesive layer 210 connects the front-side metal layer 52 and the lead frame 220. The adhesive layer 210 may electrically connect the lead frame 220 and the semiconductor device 100. The adhesive layer 210 may physically connect the lead frame 220 and the semiconductor device 100. The adhesive layer 210 may be solder connecting the front-side metal layer 52 and the lead frame 220. In this example, the adhesive layer 210 connects the lead frame 220 and the plating layer 62.
[0051] The lead frame 220 is connected to an external connection terminal for connecting to the outside of the semiconductor module 200. The lead frame 220 is provided above the front-side metal layer 52. The lead frame 220 is provided above the plating layer 62. The lead frame 220 may be a plate-shaped member made of copper or the like. By using the lead frame 220, it is possible to make the semiconductor module 200 smaller and lighter and improve its long-term reliability in high-temperature operating environments compared to when a wire frame is used.
[0052] The filler layer 230 is a filler for filling the housing of the semiconductor module 200. The material of the filler layer 230 may be a resin. The filler layer 230 may contain any filler. The filler layer 230 is provided above the insulating protective layer 38. The filler layer 230 is provided so as to cover the semiconductor device 100, the adhesive layer 210, and the lead frame 220.
[0053] Figure 3 shows a modified configuration of the semiconductor module 200. This example differs from the semiconductor module 200 in Figure 2 in that the insulating protective layer 38 is separated from the plating layer 62. The differences between this example and the semiconductor module 200 in Figure 2 will be explained in particular.
[0054] The insulating protective layer 38 is provided above the barrier layer 60. The insulating protective layer 38 has an end E38 above the barrier layer 60. The end E38 may be located outside the end E60 of the barrier layer 60 on the front surface 21 of the semiconductor substrate 10. The end E38 may be located outside the end E62 of the plating layer 62 on the front surface 21 of the semiconductor substrate 10. The insulating protective layer 38 is provided with an opening 138 that extends from above the front-side metal layer 52 to above the barrier layer 60 in a direction parallel to the front surface 21 of the semiconductor substrate 10. In this way, the insulating protective layer 38 may be provided without overlapping the plating layer 62.
[0055] The plating layer 62 is provided in a direction parallel to the front surface 21, extending from the upper surface of the front surface metal layer 52 to the upper surface of the barrier layer 60. The end E62 of the plating layer 62 may be provided on the upper surface of the barrier layer 60. The end E62 of the plating layer 62 may be provided spaced apart from the end E38 of the insulating protective layer 38 on the upper surface of the barrier layer 60. The end E62 of the plating layer 62 may be provided spaced apart from the end E60 of the barrier layer 60.
[0056] Figure 4A shows an example of the configuration of a comparative semiconductor module 500. This example of the semiconductor module 500 differs from the embodiments in Figures 2 and 3 in that it does not have a barrier layer 60. An insulating protective layer 538 is provided on the upper surface of the front metal layer 52. After the insulating protective layer 538 is formed, a plating layer 62 grows in the area not covered by the insulating protective layer 538. This forms a so-called triple point P1 where the three types of components—the front metal layer 52, the insulating protective layer 538, and the plating layer 62—are concentrated.
[0057] During soldering, if a gap forms at the interface between the plating layer 62 and the insulating protective layer 538 due to differences in thermal expansion coefficients, the adhesive layer 210 may penetrate in a wedge shape, causing a crack to form starting from the triple point P1. If the crack penetrates into the interior of the surface metal layer 52, it may cause failure of the semiconductor device 100.
[0058] Figure 4B shows an example of the configuration of a comparative semiconductor module 500. This example semiconductor module 500 differs from the embodiments in Figures 2 and 3 in that it has multiple insulating protective layers instead of a barrier layer 60. This example semiconductor module 500 includes insulating protective layers 538 and 539 as multiple insulating protective layers.
[0059] The insulating protective layer 538 is provided on the upper surface of the front-side metal layer 52. The plating layer 62 grows from the upper surface of the front-side metal layer 52 exposed at the opening of the insulating protective layer 538. The insulating protective layer 539 is provided on the upper surfaces of the insulating protective layer 538 and the plating layer 62 after the insulating protective layer 538 and the plating layer 62 have been formed. The insulating protective layer 539 prevents the adhesive layer 210 from penetrating between the insulating protective layer 538 and the plating layer 62. In this example, although crack formation can be suppressed, it is necessary to transport the product between processes, such as from the plating process back to the insulating protective layer formation process, which increases the number of manufacturing steps. Also, if the curing temperature of the insulating protective layer 539 is set lower than that of the insulating protective layer 538 in order to suppress cracks, adhesive residue may occur during the manufacturing process due to the difference in the degree of polymerization of the polyimide, which may cause appearance defects and device failure.
[0060] In contrast, the semiconductor device 100 can suppress the penetration of the adhesive layer 210 into the triple point by providing a barrier layer 60. Therefore, the manufacturing process can be simplified without providing multiple insulating protective layers 38. Furthermore, by using only one insulating protective layer 38, the degree of polymerization of the insulating protective layer 38 can be uniformly formed, thereby suppressing the occurrence of defects.
[0061] Figure 5A is a cross-sectional view of the semiconductor device 100 shown in Figure 2 during the manufacturing process. In this example, it shows a cross-section of the semiconductor device 100 after the formation of the barrier layer 60.
[0062] The front-side metal layer 52 is formed on the front surface 21 of the semiconductor substrate 10 using any method such as sputtering. The thickness D52 of the front-side metal layer 52 may be such that even if a portion of it is lost due to the effects of a chemical solution such as a zincate bath, it will not affect the operation of the semiconductor device 100. The thickness D52 of the front-side metal layer 52 may be such that it can be processed within a practical etching time. The thickness D52 of the front-side metal layer 52 may be thicker than the thickness D60 of the barrier layer 60 in the depth direction of the semiconductor substrate 10. The thickness D52 of the front-side metal layer 52 may be 1.0 μm or more and 6.0 μm or less, and 2.0 μm or more and 5.5 μm or less in the depth direction of the semiconductor substrate 10.
[0063] The barrier layer 60 is formed on the upper surface of the front metal layer 52. The barrier layer 60 may be deposited by any method, such as sputtering. If the barrier layer 60 is insulating, it may be deposited using a deposition technique such as CVD. The barrier layer 60 may be made of a material that is easily etched and resistant to the chemicals of the zincate bath and nickel plating bath. For example, the barrier layer 60 is made of TiN.
[0064] The thickness D60 of the barrier layer 60 may be such that it prevents the zincate bath chemical from penetrating into the surface metal layer 52. The thickness D60 of the barrier layer 60 may be such that it allows for processing within a practical etching time. The thickness D60 of the barrier layer 60 may be thinner than the thickness of the plating layer 62 in the depth direction of the semiconductor substrate 10. The thickness D60 of the barrier layer 60 may be 30.0 nm or more and 300.0 nm or less in the depth direction of the semiconductor substrate 10. The thickness D60 of the barrier layer 60 may be 50.0 nm or more and 100.0 nm or less in the depth direction of the semiconductor substrate 10.
[0065] Figure 5B is a cross-sectional view of the semiconductor device 100 shown in Figure 2 during the manufacturing process. In this example, it shows a cross-section of the semiconductor device 100 after etching of the barrier layer 60. Etching of the barrier layer 60 forms an opening 160, exposing the upper surface of the front-side metal layer 52. Edge E60 indicates the edge of the barrier layer 60 on the front-side metal layer 52. If the barrier layer 60 is made of TiN, it may be etched using a Cl2 / BCl3 dry etching system.
[0066] An etching mask may be formed before etching and removed after etching. By continuously depositing the front metal layer 52 and the barrier layer 60, the adhesion between the barrier layer 60 and the front metal layer 52 can be improved. Continuously depositing the front metal layer 52 and the barrier layer 60 means that no patterning step is included between the deposit process of the front metal layer 52 and the deposit process of the barrier layer 60.
[0067] Figure 5C is a cross-sectional view of the semiconductor device 100 shown in Figure 2 during the manufacturing process. In this example, it shows a cross-section of the semiconductor device 100 after the formation of the replacement layer 61.
[0068] The substitution layer 61 is provided on the upper surface of the front metal layer 52. The substitution layer 61 may be Zn which has been substituted for Al in the front metal layer 52 by a zincate bath. Since Zn has a lower ionization tendency than Al, the zincate bath causes substitution of Al for Zn at the outermost surface of the front metal layer 52. On the other hand, in the region where the barrier layer 60 exists, the zincate bath solution is blocked by the barrier layer 60 and cannot reach the front metal layer 52, so substitution of Al for Zn does not occur. As a result, the substitution layer 61 is formed only on the outermost surface of the front metal layer 52. The substitution layer 61 may also be formed by a double zincate process in which the zincate bath is repeated twice.
[0069] Figure 5D is a cross-sectional view of the semiconductor device 100 shown in Figure 2 during the manufacturing process. In this example, it shows a cross-section of the semiconductor device 100 after the formation of the plating layer 62.
[0070] The plating layer 62 is formed by growing from the upper surface of the front-side metal layer 52. In addition to growing in the depth direction of the semiconductor substrate 10, the plating layer 62 also grows in a direction parallel to the front surface 21. The plating layer 62 may extend from the upper surface of the front-side metal layer 52 to the upper surface of the barrier layer 60 in a direction parallel to the front surface 21 of the semiconductor substrate 10. In this example, the plating layer 62 covers the upper surface of the end E62 of the barrier layer 60. The distance over which the plating layer 62 covers the upper surface of the barrier layer 60 may be greater than or equal to the thickness D62 of the plating layer 62.
[0071] The plating layer 62 is formed by a plating bath of nickel or the like. The plating layer 62 may be formed using a Ni-P-based electroless plating bath. Whether or not the plating layer 62 is formed by the plating process can be determined by analyzing the amount of P (phosphorus) contained in the plating layer 62. The plating layer 62 may be formed in an electroless plating bath or in an electrolytic plating bath.
[0072] In electroless plating baths, the reaction proceeds by immersion in a chemical solution, making it convenient and safe. Since Ni has a lower ionization tendency than Zn, performing Ni plating baths causes substitution of Zn and Ni near the substitution layer 61, and the substituted Ni itself acts as a catalyst to promote the growth of the plating layer 62. The thickness D62 of the plating layer 62 may be determined according to the magnitude of the power handled by the semiconductor device 100. The thickness D62 of the plating layer 62 may be a thickness that can suppress the diffusion of Sn, the main component of solder, into the surface metal layer 52. The thickness D62 of the plating layer 62 may be 3.0 μm or more and 6.0 μm or less in the depth direction of the semiconductor substrate 10. The thickness D52 of the surface metal layer 52 may be thicker than the thickness D62 of the plating layer 62 in the depth direction of the semiconductor substrate 10.
[0073] Figure 5E is a cross-sectional view of the semiconductor device 100 shown in Figure 2 during the manufacturing process. In this example, it shows a cross-section of the semiconductor device 100 after the formation of the insulating protective layer 38.
[0074] The insulating protective layer 38 is formed on the upper surfaces of the barrier layer 60 and the plating layer 62. In this example, the insulating protective layer 38 is provided overlapping from above the barrier layer 60 to above the plating layer 62 in a direction parallel to the front surface 21 of the semiconductor substrate 10. The insulating protective layer 38 may have openings 138 in which the plating layer 62 is exposed. The end E38 of the insulating protective layer 38 may be terminated above the plating layer 62. The thickness D38 of the insulating protective layer 38 may be thicker than the thickness D60 of the barrier layer 60 in the depth direction of the semiconductor substrate 10. The thickness D38 of the insulating protective layer 38 may be 1.0 μm or more and 10.0 μm or less in the depth direction of the semiconductor substrate 10.
[0075] The insulating protective layer 38 may be a coated film using a method such as spin coating. The material of the insulating protective layer 38 may be a non-photosensitive polyimide. The insulating protective layer 38 may be patterned using a photoresist as an etching mask to provide openings 138 in the insulating protective layer 38. The photoresist may be removed after use. The insulating protective layer 38 may be fired in a nitrogen atmosphere at a temperature of less than 300°C.
[0076] In the process shown in this figure, the manufacturing process for the semiconductor device 100 may be completed. If a semiconductor module 200 is to be manufactured using the semiconductor device 100, further manufacturing processes such as the bonding layer 210, lead frame 220, and filling layer 230 may be performed.
[0077] Figure 5F is a cross-sectional view of the semiconductor module 200 shown in Figure 2 during the manufacturing process. In this example, it shows a cross-section of the semiconductor module 200 after the formation of the packed layer 230.
[0078] The adhesive layer 210 and the lead frame 220 are provided on the upper surface of the plating layer 62. The lead frame 220 is fixed to the upper surface of the plating layer 62 via the adhesive layer 210. The lead frame 220 is provided spaced apart from the insulating protective layer 38 and the plating layer 62. The housing of the semiconductor module 200 may be filled with a filler layer 230 made of resin or the like.
[0079] In this example, the insulating protective layer 38 is provided overlapping the plating layer 62. Distance L1 is the distance over which the insulating protective layer 38 overlaps the plating layer 62 provided at the opening 160 of the barrier layer 60. Distance L1 may be the distance from the end E60 of the barrier layer 60 to the end E38 of the insulating protective layer 38 in a direction parallel to the front surface 21. Distance L1 may be such that the adhesive layer 210 cannot penetrate to the interface between the plating layer 62 and the insulating protective layer 38 and reach the vicinity of the front surface metal layer 52. Distance L1 may be greater than or equal to the thickness D62 of the plating layer 62.
[0080] The upper limit of the area in which the insulating protective layer 38 overlaps the plating layer 62 provided in the opening 160 of the barrier layer 60 may be determined to satisfy the required electrical characteristics of the semiconductor device 100. The lower limit of the area in which the insulating protective layer 38 overlaps the plating layer 62 provided in the opening 160 of the barrier layer 60 may be determined from the viewpoint of suppressing the penetration of the adhesive layer 210 into the interface between the plating layer 62 and the insulating protective layer 38. The area in which the insulating protective layer 38 overlaps the plating layer 62 provided in the opening 160 of the barrier layer 60 may be greater than 0% of the contact area between the plating layer 62 and the front side metal layer 52, and 10% or less.
[0081] Figure 6A is a cross-sectional view of the semiconductor device 100 shown in Figure 3 during the manufacturing process. In this example, it shows a cross-section of the semiconductor device 100 after the formation of the barrier layer 60. The state after the process of forming the barrier layer 60 on the upper surface of the front metal layer 52 may be the same as in the embodiment shown in Figure 5A.
[0082] Figure 6B is a cross-sectional view of the semiconductor device 100 shown in Figure 3 during the manufacturing process. In this example, it shows a cross-section of the semiconductor device 100 after etching of the barrier layer 60. The state after the process of forming the opening 160 in the barrier layer 60 may be the same as in the embodiment shown in Figure 5B.
[0083] Figure 6C is a cross-sectional view of the semiconductor device 100 shown in Figure 3 during the manufacturing process. In this example, a cross-section of the semiconductor device 100 after the formation of the insulating protective layer 38 is shown. This example differs from the embodiment in Figure 5C in that the insulating protective layer 38 is formed before the formation of the replacement layer 61.
[0084] The insulating protective layer 38 is formed after the barrier layer 60 is formed. The insulating protective layer 38 may be formed before the plating layer 62 is formed. The insulating protective layer 38 may be formed after the replacement layer 61 is formed and before the plating layer 62 is formed. In this example, the insulating protective layer 38 is not formed on top of the plating layer 62, so it can be formed before the plating layer 62 is formed. The insulating protective layer 38 may be formed by the same method as described in Figure 5E. However, the insulating protective layer 38 may be formed after the plating layer 62 is formed.
[0085] The insulating protective layer 38 may be annealed in a nitrogen atmosphere at a temperature of 300°C to 400°C. However, if the plating layer 62 is annealed at a high temperature, cracks may occur. By forming the insulating protective layer 38 before the plating layer 62, it can be annealed at a relatively high temperature regardless of the heat resistance of the plating layer 62. Alternatively, the insulating protective layer 38 may be annealed in a nitrogen atmosphere at a temperature of less than 300°C.
[0086] Figure 6D is a cross-sectional view of the semiconductor device 100 shown in Figure 3 during the manufacturing process. In this example, a cross-section of the semiconductor device 100 after the formation of the replacement layer 61 is shown. In this example, the replacement layer 61 is formed on the upper surface of the front-side metal layer 52 after the insulating protective layer 38 is formed on the upper surface of the barrier layer 60. Even in this case, the replacement layer 61 is not formed on the upper surfaces of the insulating protective layer 38 and the barrier layer 60, but only on the upper surface of the front-side metal layer 52. The method for forming the replacement layer 61 may be the same as the method described in Figure 5C. Note that the replacement layer 61 may be formed before the insulating protective layer 38 is formed.
[0087] Figure 6E is a cross-sectional view of the semiconductor device 100 shown in Figure 3 during the manufacturing process. In this example, it shows a cross-section of the semiconductor device 100 after the formation of the plating layer 62. In this example, the plating layer 62 is formed on the upper surface of the front-side metal layer 52 after the insulating protective layer 38 is formed on the upper surface of the barrier layer 60. In this example, the insulating protective layer 38 is provided without overlapping the plating layer 62. The plating layer 62 may be provided overlapping the barrier layer 60.
[0088] Figure 6F is a cross-sectional view of the semiconductor module 200 shown in Figure 3 during the manufacturing process. In this example, it shows a cross-section of the semiconductor module 200 after the formation of the packed layer 230.
[0089] Distance L2 is the distance between the end E38 of the insulating protective layer 38 and the end E60 of the barrier layer 60 in a direction parallel to the front surface 21. That is, distance L2 corresponds to the distance between the open end of the insulating protective layer 38 and the open end of the barrier layer 60 in a direction parallel to the front surface 21 of the semiconductor substrate 10. Distance L2 may be greater than or equal to the thickness D62 of the plating layer 62. By making distance L2 greater than or equal to the thickness D62 of the plating layer 62, the insulating protective layer 38 and the plating layer 62 can be separated even if the plating layer 62 grows laterally. Separating the insulating protective layer 38 and the plating layer 62 can suppress the occurrence of cracks.
[0090] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.
[0091] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of symbols]
[0092] 10...Semiconductor substrate, 12...Source region, 14...Base region, 15...Contact region, 18...Drift region, 20...First conductivity region, 21...Front surface, 23...Back surface, 24...Back side metal layer, 38...Insulating protective layer, 42...Gate insulating film, 44...Gate electrode, 46...Interlayer insulating film, 52...Front side metal layer, 60...Barrier layer, 61...Replacement layer, 62...Plating layer, 100...Semiconductor device, 138...Aperture, 160...Aperture, 200...Semiconductor module, 210...Adhesive layer, 220...Lead frame, 230...Filling layer, 500...Semiconductor module, 538...Insulating protective layer, 539...Insulating protective layer
Claims
1. A metal layer on the front side, located above the semiconductor substrate, A plating layer provided on the upper surface of the aforementioned front-side metal layer, A barrier layer provided on the upper surface of the front-side metal layer and in direct contact with the plating layer on the upper surface of the front-side metal layer, An insulating protective layer provided above the barrier layer, Equipped with, The barrier layer comprises a conductive material, The plating layer is provided in a direction parallel to the front surface of the semiconductor substrate, extending from the upper surface of the front-side metal layer to the upper surface of the barrier layer. A semiconductor device in which the upper surface of the barrier layer is in contact with the plating layer.
2. The thickness of the metal layer on the front side is greater than the thickness of the plating layer and greater than the thickness of the barrier layer in the depth direction of the semiconductor substrate. The semiconductor device according to claim 1.
3. The thickness of the metal layer on the front side is 1.0 μm or more and 6.0 μm or less in the depth direction of the semiconductor substrate. The semiconductor device according to claim 1 or 2.
4. The material of the metal layer on the front side includes at least one of an aluminum-silicon alloy, an aluminum-silicon-copper alloy, or an aluminum-neodymium alloy. The semiconductor device according to any one of claims 1 to 3.
5. The thickness of the barrier layer is thinner than the thickness of the plating layer in the depth direction of the semiconductor substrate. The semiconductor device according to any one of claims 1 to 4.
6. The thickness of the barrier layer is 30.0 nm or more and 300.0 nm or less in the depth direction of the semiconductor substrate. The semiconductor device according to any one of claims 1 to 5.
7. The barrier layer material includes at least one of TiN, TiW, W, Cr, Mo, Ta, or Nb. The semiconductor device according to any one of claims 1 to 6.
8. The thickness of the plating layer is 3.0 μm or more and 6.0 μm or less in the depth direction of the semiconductor substrate. The semiconductor device according to any one of claims 1 to 7.
9. The aforementioned plating layer is a nickel plating layer. The semiconductor device according to any one of claims 1 to 8.
10. The thickness of the insulating protective layer is greater than the thickness of the barrier layer in the depth direction of the semiconductor substrate. A semiconductor device according to any one of claims 1 to 9.
11. The thickness of the insulating protective layer is 1.0 μm or more and 10.0 μm or less in the depth direction of the semiconductor substrate. The semiconductor device according to any one of claims 1 to 10.
12. The insulating protective layer material comprises at least one of polyimide or polybenzoxazole. The semiconductor device according to any one of claims 1 to 11.
13. A metal layer on the front side provided above the semiconductor substrate, A plating layer provided on the upper surface of the aforementioned front-side metal layer, A barrier layer provided on the upper surface of the front-side metal layer and in direct contact with the plating layer on the upper surface of the front-side metal layer, An insulating protective layer provided above the barrier layer, Equipped with, The barrier layer comprises a conductive material, The insulating protective layer is provided overlapping from above the barrier layer to above the plating layer in a direction parallel to the front surface of the semiconductor substrate. The end of the insulating protective layer terminates above the plating layer. Semiconductor equipment.
14. The area in which the insulating protective layer overlaps the plating layer provided in the opening of the barrier layer is greater than 0% of the contact area between the plating layer and the front-side metal layer, and less than or equal to 10%. The semiconductor device according to claim 13.
15. The distance over which the insulating protective layer overlaps the plating layer provided at the opening of the barrier layer is greater than or equal to the thickness of the plating layer. The semiconductor device according to claim 13 or 14.
16. A metal layer on the front side provided above the semiconductor substrate, A plating layer provided on the upper surface of the aforementioned front-side metal layer, A barrier layer provided on the upper surface of the front-side metal layer and in direct contact with the plating layer on the upper surface of the front-side metal layer, An insulating protective layer provided above the barrier layer, Equipped with, The barrier layer comprises a conductive material, The insulating protective layer is provided with an opening that extends in a direction parallel to the front surface of the semiconductor substrate, from above the front surface metal layer to above the barrier layer. The barrier layer has an opening above the front-side metal layer. The open end of the insulating protective layer and the open end of the barrier layer are spaced apart in a direction parallel to the front surface of the semiconductor substrate by more than the thickness of the plating layer. Semiconductor equipment.
17. The semiconductor substrate has a vertical semiconductor structure with a back-side metal layer on its back side. The semiconductor device according to any one of claims 1 to 16.
18. A semiconductor device according to any one of claims 1 to 17, A lead frame provided above the aforementioned front-side metal layer, An adhesive layer for connecting the aforementioned front-side metal layer and the lead frame, A semiconductor module equipped with the following features.