Image forming apparatus

Abstract

To achieve an image forming apparatus that can control a heater with simple control.SOLUTION: A control unit (45) controls to determine an on-period according to input of an edge of a zero-cross signal, and cause an output circuit (46) to output a pulse signal based on the determined on-period according to input of a next edge.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to an image forming apparatus.

Background Art

[0002] Conventionally, an image forming apparatus including a fixing device that has a heater and fixes a developer image on a sheet is known. In Patent Document 1, the heater is connected to an AC power supply via a switching element such as a triac, and the image forming apparatus controls energization of the heater so that the temperature of the fixing device reaches a target temperature by switching the switching element based on the timing at which the zero-cross point of the AC voltage supplied from the AC power supply is detected.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the image forming apparatus of Patent Document 1, since the timing for outputting a control signal to the switching element is determined based on the detected zero-cross point timing, it is difficult control that requires a high-performance control unit.

[0005] The present disclosure has been made in view of the above problems, and an object thereof is to realize an image forming apparatus capable of controlling a heater by simple control.

Means for Solving the Problems

[0006] To solve the above problems, an image forming apparatus according to one aspect of the present disclosure comprises: a fuser having a heater that generates heat by an AC voltage supplied from an AC power source and fixing a developer image onto a sheet; a switching element that switches the AC voltage supplied to the heater, and switches between an ON state in which the AC power source and the heater are electrically connected and an OFF state in which the AC power source and the heater are not electrically connected; a zero-crossing circuit that outputs a zero-crossing signal indicating the zero-crossing point of the AC voltage; a control unit; and an output circuit that outputs a pulse signal to the switching element, wherein the pulse signal is the rising edge of the zero-crossing signal. or Depending on the falling edge, the switching element is set to the ON state for the duration of the ON period, and then set to the OFF state. The control unit determines the ON period in response to the input of the edge of the zero-crossing signal, and controls the output circuit to output a pulse signal based on the determined ON period in response to the input of the next edge.

[0007] The control unit determines the on-period of the pulse signal output by the output circuit in accordance with the next edge, prior to the input of the next edge of the zero-crossing signal. Then, at the timing of the actual next zero-crossing signal edge, it controls the output circuit to output a pulse signal that keeps the switching element ON for the determined on-period. Because the on-period is determined prior to the input of the next edge, the heater can be controlled more easily than in conventional systems.

[0008] Furthermore, in an image forming apparatus according to one aspect of the present disclosure, a temperature sensor for detecting the temperature of the fuser is provided, and the control unit controls the output circuit using a control pattern determined for each half-wave of the AC voltage to determine whether to set the state of the switching element to the ON state or the OFF state based on the detected temperature detected by the temperature sensor, and at the timing when the input of the edge of the zero-crossing signal is detected, if the control pattern is determined to set the state of the switching element to the ON state when the next edge is input, and to set the state of the switching element to the OFF state when the next edge is input, the control unit determines to shorten the ON period to a predetermined period.

[0009] If the control pattern specifies that the switching element should be turned ON when the next edge input is detected, and then turned OFF when the next edge input is detected, shortening the ON period can prevent the switching element from remaining in the OFF state due to fluctuations in the AC voltage waveform.

[0010] Furthermore, in an image forming apparatus according to one aspect of the present disclosure, the control unit, at the timing of detecting the input of the edge of the zero-crossing signal, determines to make the ON period longer than the predetermined period if the control pattern specifies that the state of the switching element should be turned ON when the next edge is input, and that the state of the switching element should be turned ON when the next edge is input.

[0011] If the control pattern specifies that the switching element should be turned on when the next edge input is detected, and again when the next edge input is detected, then by extending the on period, the switching element can be kept continuously on, i.e., AC voltage can be continuously supplied to the heater, thereby suppressing the generation of noise.

[0012] Furthermore, in an image forming apparatus according to one aspect of the present disclosure, the control unit, at the timing of detecting the input of the edge of the zero-crossing signal, writes the determined ON period information to the storage unit of the output circuit, and the output circuit outputs the pulse signal in response to the input of the next edge based on the ON period information stored in the storage unit.

[0013] Furthermore, in an image forming apparatus according to one aspect of the present disclosure, a temperature sensor for detecting the temperature of the fuser is provided, and the control unit controls the output circuit using a control pattern determined for each half-wave of the AC voltage to determine whether to set the state of the switching element to the ON state or the OFF state based on the temperature detected by the temperature sensor, and when the control pattern is determined to set the state of the switching element to the ON state at the time the input of the edge of the zero-crossing signal is detected, and to set the state of the switching element to the ON state at the time of the input of the next edge, the control unit controls the output circuit to output a pulse signal without delay in response to the input of the next edge.

[0014] If the control pattern specifies that the switching element should be turned on when an edge input is detected, and that the switching element should be turned on again when the next edge input is detected, the output circuit can output a pulse signal without delay, thereby continuously turning on the switching element, i.e., continuously supplying AC voltage to the heater. Since there is no off state in the pulse signal, noise generation can be prevented.

[0015] Furthermore, in an image forming apparatus according to one aspect of the present disclosure, if the control unit detects the input of the edge of the zero-crossing signal, and the control pattern specifies that the state of the switching element at the time of detection of the input of the edge is set to the off state, and the state of the switching element at the time of input of the next edge is set to the on state, the control unit controls the output circuit to output a pulse signal with a delay in response to the input of the next edge.

[0016] Furthermore, in an image forming apparatus according to one aspect of the present disclosure, if the control pattern specifies that when the input of the edge of the zero-crossing signal is detected, the control unit makes the ON period longer than the half-wave period of the AC voltage, when the control unit detects the input of the edge, the state of the switching element at the time of detection of the input of the edge is turned ON, and the state of the switching element at the time of input of the next edge is turned ON.

[0017] Furthermore, in an image forming apparatus according to one aspect of the present disclosure, the control unit, at the timing of detecting the input of the edge of the zero-crossing signal, writes the determined ON period information to the storage unit of the output circuit, and the output circuit outputs the pulse signal in response to the input of the next edge based on the ON period information stored in the storage unit.

[0018] Furthermore, in an image forming apparatus according to one aspect of the present disclosure, the output circuit has a plurality of output units that output a PWM signal to the switching element in which the switching element is in the ON state for an ON period in accordance with the rising or falling edge of the zero-crossing signal, and thereafter the switching element is in the OFF state. The plurality of output units sequentially output PWM signals in accordance with the input of the edge of the zero-crossing signal, and the pulse signal is generated by superimposing the PWM signals output by the plurality of output units of the output circuit.

[0019] Furthermore, in an image forming apparatus according to one aspect of the present disclosure, the output circuit has three output units, and each of the three output units further has a storage unit that writes information of a determined on-period at the timing when the input of the edge of the zero-crossing signal is detected, and the three output units output the pulse signal in response to the input of the next edge based on the on-period information stored in the corresponding storage unit. [Effects of the Invention]

[0020] According to one aspect of the present disclosure, an image forming apparatus capable of controlling a heater by simple control can be realized.

Brief Description of the Drawings

[0021] [Figure 1] It is a side sectional view showing a schematic configuration of an image forming apparatus according to Embodiment 1 of the present disclosure. [Figure 2] It is a functional block diagram showing a schematic configuration of an image forming apparatus according to Embodiment 1 of the present disclosure. [Figure 3] It is a diagram showing the relationship between a heater and a circuit board according to Embodiment 1 of the present disclosure. [Figure 4] It is a block diagram showing a schematic configuration of the timing generator in FIG. 2 and a diagram showing an example of a first PWM signal. [Figure 5] It is a flowchart regarding the operation of the first PWM block in FIG. 4. [Figure 6] It is a flowchart regarding the control of the heater. [Figure 7] It is a diagram showing an example of a control pattern. [Figure 8] It is a flowchart regarding the heater lighting determination in FIG. 6. [Figure 9] It is a flowchart regarding the second register writing process in FIG. 8 in Embodiment 1 of the present disclosure. [Figure 10] It is a timing chart used for explaining the relationship between the control pattern and the output signal of the timing generator in Embodiment 1 of the present disclosure. [Figure 11] It is a flowchart regarding the first register writing process in FIG. 8 in Embodiment 1 of the present disclosure. [Figure 12] It is a flowchart regarding the first and second register writing processes in FIG. 8 in Embodiment 2 of the present disclosure. [Figure 13] It is a timing chart used for explaining the relationship between the control pattern and the output signal of the timing generator in Embodiment 2 of the present disclosure.

Modes for Carrying Out the Invention

[0022] [Embodiment 1] One embodiment of this disclosure will be described in detail below.

[0023] Figure 1 is a schematic diagram showing a longitudinal section of an image forming apparatus 1 according to Embodiment 1 of the present disclosure.

[0024] The image forming apparatus 1 forms a developer image on a sheet 5 supplied from a tray 3 or manual feed tray 4 located at the bottom of the main housing 2 using the image forming unit 6. Subsequently, the image forming apparatus 1 heats the sheet 5 on which the developer image has been formed using the fixing unit 7 to perform a fixing process, and finally, the image forming apparatus 1 uses a paper discharge roller to discharge the sheet into a paper discharge tray 8 located at the top of the main housing 2.

[0025] The image forming unit 6 includes a laser unit 10, a developing cartridge 13, a photosensitive drum 17, a charging device 18, a transfer unit 19, and the like.

[0026] The laser unit 10 is located at the top of the main housing 2 and includes a laser light-emitting unit (not shown), a polygon mirror 11, multiple reflectors 12, and multiple lenses (not shown). The laser unit 10 irradiates the surface of the photosensitive drum 17 with laser light emitted from the laser light-emitting unit at high speed, as shown by the dashed line, via the polygon mirror 11, reflectors 12, and lenses.

[0027] The developing cartridge 13 is detachably mounted on the main body 2 and contains a developer inside. A developing roller 14 and a supply roller 15 are positioned opposite each other at the developer supply port of the developing cartridge 13. The developer in the developing cartridge 13 is supplied to the developing roller 14 by the rotation of the supply roller 15 and is then carried on the developing roller 14.

[0028] A charging device 18 is positioned above the photosensitive drum 17 at a distance. Below the photosensitive drum 17, a transfer unit 19 is positioned opposite the photosensitive drum 17. The surface of the photosensitive drum 17 is rotated and first uniformly charged, for example, with positive polarity, by the charging device 18. Then, an electrostatic latent image is formed on the photosensitive drum 17 by laser light from the laser unit 10.

[0029] Subsequently, as the photosensitive drum 17 rotates in contact with the developing roller 14, the developer supported on the developing roller 14 is supplied to and supported by the electrostatic latent image on the surface of the photosensitive drum 17, thereby forming a developer image. The developer image is then transferred to the sheet 5 by a transfer bias applied to the transfer unit 19 as the sheet 5 passes between the photosensitive drum 17 and the transfer unit 19.

[0030] The fixing unit 7 fixes the image created by the developer onto the sheet 5. The fixing unit 7 is located downstream of the image forming unit 6 in the sheet transport direction and includes a fixing roller 22, a pressure roller 23 that presses against the fixing roller 22, and a heater 31 that heats the fixing roller 22.

[0031] The heater 31 is, for example, a halogen heater, connected to the circuit board 25, and its power supply is controlled by an on / off signal from the circuit board 25. The image forming apparatus 1 comprises the heater 31, the circuit board 25, and the panel unit 27.

[0032] Figure 2 is a functional block diagram showing the schematic configuration of the image forming apparatus 1. As shown in Figure 2, the image forming apparatus 1 comprises an image forming unit 6, a fixing unit 7, a circuit board 25, and a panel unit 27.

[0033] The circuit board 25 includes a main board 40 and a low-voltage power supply 41. The main board 40 includes an SOC (System on Chip) 44, a DC / DC converter 48, an interface 50, a LAN interface 51, and a USB interface 52. The low-voltage power supply 41 includes a triac 42 and a zero-crossing circuit 43.

[0034] The low-voltage power supply 41 receives power from the AC power supply and supplies the AC voltage Vin to the heater 31 of the fixing unit 7. The low-voltage power supply 41 also converts the AC voltage Vin to a predetermined DC voltage and supplies it to the main board 40. In Figure 2, the low-voltage power supply 41 converts the AC voltage Vin to a DC voltage of 24V.

[0035] The triac 42 of the low-voltage power supply 41 is an example of a switching element, and switches the AC voltage Vin supplied to the heater 31 of the fixing unit 7 based on an on / off signal described later. When the AC voltage Vin is supplied to the heater 31, it generates heat and heats the fixing roller 22. The thermistor 32 is an example of a temperature sensor, and detects the temperature of the heater 31. In Figure 2, the thermistor 32 is shown as part of the fixing unit 7, but the thermistor 32 only needs to be able to detect the temperature of the heater 31 and may be provided outside the fixing unit 7. Furthermore, the temperature sensor that detects the temperature of the heater 31 is not limited to the thermistor 32. For example, a thermocouple or a resistance thermometer may be used as the temperature sensor that detects the temperature of the heater 31.

[0036] Furthermore, the switching element that switches the AC voltage Vin supplied to the heater 31 of the fixing unit 7 is not limited to the triac 42. For example, an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) may be used to switch the AC voltage Vin supplied to the heater 31 of the fixing unit 7.

[0037] The zero-crossing circuit 43 outputs a zero-crossing signal that indicates the zero-crossing point of the AC voltage Vin supplied to the heater 31 of the fixing unit 7. The zero-crossing signal falls from a high level to a low level when the absolute value of the AC voltage Vin falls below a predetermined threshold voltage Vth, and rises from a low level to a high level when the absolute value of the AC voltage exceeds the threshold voltage Vth. The zero-crossing signal is input to the timing generator 46 and latch circuit 47 of the main board 40. Hereinafter, the falling of the zero-crossing signal will be referred to as the input of an edge.

[0038] The SOC44 on the main board 40 includes at least a CPU (Central Processing Unit) 45, a timing generator 46, and a latch circuit 47. The CPU 45 is an example of a control unit and controls the timing generator 46 of the SOC44, as well as the panel unit 27, the image forming unit 6, and other parts of the image forming apparatus 1 by executing a program stored in a memory unit (not shown). The SOC44 may also be used as the control unit, or a CPU provided outside the SOC44 may be used as the control unit.

[0039] The timing generator 46 is an example of an output circuit and has multiple registers REG. The multiple registers REG are an example of a memory unit, and information is written to them by the CPU 45. Based on the information written to the multiple registers REG, the timing generator 46 generates an on / off signal, which is an example of a pulse signal, and outputs the on / off signal to the low-voltage power supply 41 in response to the input of the edge of the zero-crossing signal. The method for generating the on / off signal will be described in detail later.

[0040] The latch circuit 47 holds edge-on information indicating that an edge input has been detected when the edge input of the zero-crossing signal is detected, that is, when the zero-crossing signal falls.

[0041] The DC / DC converter 48 steps down the DC voltage supplied from the low-voltage power supply 41 to a predetermined DC voltage and supplies the stepped-down DC voltage to the SOC 44. In Figure 2, the DC / DC converter 48 steps down the 24V DC voltage supplied from the low-voltage power supply 41 to a DC voltage of 3.3V. Note that the input and output voltage values ​​of the DC / DC converter 48 shown in Figure 2 are merely examples and are not limited thereto.

[0042] The SOC44 is connected to the panel unit 27 via interface 50. The panel unit 27 includes, for example, a power switch 53, a panel 54 with multiple operation keys, and a liquid crystal display 55. The SOC44 can also be connected to a LAN via LAN interface 51 and to USB storage devices (not shown) via USB interface 52.

[0043] Figure 3 shows the relationship between the heater 31 and the circuit board 25. In Figure 3, zero-crossing signals are input to the CPU 45 and the timing generator 46. The input of the zero-crossing signal to the CPU 45 means reading edge-on information via a latch circuit 47, which is not shown in Figure 3.

[0044] The zero-crossing circuit 43 comprises a rectifier circuit 60, a photocoupler 61, and a transistor 62. The photocoupler 61 has a light-emitting diode 61A and a light-receiving element 61B. The AC voltage Vin is full-wave rectified by the rectifier circuit 60 and converted into an optical signal by the light-emitting diode 61A. Current flows through the photocoupler 61 to the light-receiving element 61B when the signal obtained by full-wave rectifying the AC voltage Vin is greater than or equal to the threshold voltage Vth. As current flows through the photocoupler 61, current does not flow between the emitter and collector of the transistor 62, and the zero-crossing signal becomes high level. In other words, the zero-crossing signal becomes high level when the absolute value of the AC voltage Vin is greater than or equal to the threshold voltage Vth.

[0045] On the other hand, when the signal obtained by full-wave rectifying the AC voltage Vin is less than the threshold voltage Vth, no current flows through the photocoupler 61B. As a result, base current flows through transistor 62, causing current to flow between the emitter and collector of transistor 62, and the zero-crossing signal becomes low level. In other words, the zero-crossing signal becomes low level when the absolute value of the AC voltage Vin is less than the threshold voltage Vth.

[0046] The on / off signal output from the timing generator 46 of SOC44 is input to the triac coupler 63. The triac 42 switches the AC voltage Vin supplied to the heater 31 of the fixing unit 7 via the triac coupler 63. The triac 42 is in the on state when the on / off signal is at a high level, i.e., when the on / off signal is on, and conducts between the heater 31 and the AC power supply shown in Figure 2, supplying the AC voltage Vin to the heater 31. Conversely, the triac 42 is in the off state when the on / off signal is at a low level, i.e., when the on / off signal is off, and does not conduct between the heater 31 and the AC power supply, thus not supplying the AC voltage Vin to the heater 31.

[0047] Figure 4 shows a block diagram 1000 of the timing generator 46. The timing generator 46 has a first PWM block BL1, a second PWM block BL2, and a third PWM block BL3. The first PWM block BL1, the second PWM block BL2, and the third PWM block BL3 are examples of output sections. The first PWM block BL1 has a first register REG1. The second PWM block BL2 has a second register REG2. The third PWM block BL3 has a third register REG3. The first register REG1, the second register REG2, and the third register REG3 are examples of the multiple REGs shown in Figure 2.

[0048] The CPU 45 writes information regarding the delay time DLY, on-time WID, and time PER to the first register REG1 at the timing of detecting the input of the x-th edge of the zero-crossing signal. The first PWM block BL1 generates the first PWM signal at the timing of detecting the input of the (x+1)-th edge of the zero-crossing signal, based on the information regarding the delay time DLY, on-time WID, and time PER written to the first register REG1. An example of the waveform of the first PWM signal is shown in waveform diagram 1001 of Figure 4. The first PWM signal is delayed by the delay time DLY from the timing of detecting the input of the edge of the zero-crossing signal, then turns on for the on-time WID, and turns off for the time PER-WID.

[0049] CPU45 writes information about the delay time DLY, on time WID, and time PER to the second register REG2 when it detects the input of the (x+1)th edge of the zero-crossing signal. The second PWM block BL2 generates the second PWM signal based on the information written to the second register REG2 when it detects the input of the (x+2)th edge of the zero-crossing signal.

[0050] CPU45 writes information about the delay time DLY, on time WID, and time PER to the third register REG3 when it detects the input of the (x+2) edge of the zero-crossing signal. The third PWM block BL3 generates the third PWM signal when it detects the input of the (x+3) edge of the zero-crossing signal, based on the information written to the third register REG3.

[0051] When the CPU 45 detects the input of the (x+3)th edge of the zero-crossing signal, it again writes information about the delay time DLY, on-time WID, and time PER to the first register REG1. Thereafter, in response to the edge input of the zero-crossing signal, the CPU 45 switches the register REG to which it writes information about the delay time DLY, on-time WID, and time PER in the order of the second register REG2, the third register REG3, and the first register REG1.

[0052] The first PWM signal and the second PWM signal are input to the OR circuit OR1. The OR circuit OR1 outputs a high-level signal when either the first PWM signal or the second PWM signal is high, and outputs a low-level signal when both the first and second PWM signals are low.

[0053] Furthermore, the output signal of OR1 and the third PWM signal are input to OR2. OR2 outputs a high-level signal when the output signal of OR1 or the third PWM signal is high, and outputs a low-level signal when the output signal of OR1 and the third PWM signal are low.

[0054] The output of the OR2 circuit becomes the aforementioned on / off signal. That is, the on / off signal is a superposition of the first PWM signal, the second PWM signal, and the third PWM signal. Note that the method of superimposing the first PWM signal, the second PWM signal, and the third PWM signal is not limited to the OR1 and OR2 circuits. For example, it could be constructed using a single 3-input type OR circuit, or it could be constructed using a NAND gate, etc.

[0055] In the following explanation, the period during which the on / off signal output by the timing generator 46 is high level and the triac 42 is in the on state will be referred to as the on period. Furthermore, the information regarding the delay time DLY, on time WID, and time PER that the CPU 45 writes to the register REG will be referred to as the on period information.

[0056] As mentioned above, an on / off signal is an example of a pulse signal. Furthermore, the first PWM signal, second PWM signal, and third PWM signal, which constitute an on / off signal when superimposed, are also examples of pulse signals.

[0057] Figure 5 is a flowchart showing an example of operation of the first PWM block BL1. When the edge of a zero-crossing signal is input to the first PWM block BL1 (S100: YES), it reads information about the on-period, i.e., the delay time DLY, on-time WID, and time PER, from the first register REG1 (S101). In the following description, it is assumed that the edge of the zero-crossing signal input in S100 is the (x+1)th edge mentioned above.

[0058] The first PWM block BL1 determines that if the WID read in S101 is greater than 0 (S102: YES), the CPU 45 has written the on-period information to the first register REG1 at the timing when the x-th edge is input, and outputs the first pulse signal (S103). The first pulse signal output in S103 is delayed by the delay time DLY read in S101 from the timing when the edge was input in S100, then turns on for the on-time WID read in S101, and turns off for time PER-WID. The first PWM block BL1 proceeds to S104 when time DLY+PER has elapsed since the timing when the (x+1)th edge was detected, that is, when the output of the first pulse signal is complete.

[0059] In S102, if the on-time WID read in S101 is 0 (S102: NO), the first PWM block BL1 determines that the on-time information has not been written to the first register REG1 by the CPU 45, and proceeds to S105.

[0060] In S104, the first PWM block BL1 clears the information written to the first register REG1 in preparation for the CPU 45 to write information about the on-time to the first register REG1 when the input of the (x+3) edge is detected. For example, it sets the value of the on-time WID stored in the first register REG1 to 0. From then on, the judgment in S102 is rejected until the CPU 45 writes a value greater than 0 as the on-time WID to the first register REG1.

[0061] The first PWM block BL1 proceeds to S100 if the power to the image forming apparatus 1 is on (S105: NO), and completes the process shown in Figure 5 if the power to the image forming apparatus 1 is turned off, for example, by operating the power switch 53 in Figure 2 (S105: YES). The operation of the second PWM block BL2 and the third PWM block BL3 is the same as the operation of the first PWM block BL1 shown in Figure 5.

[0062] Figure 6 is a flowchart relating to the control of the heater 31 by the CPU 45. When the CPU 45 receives a print job, for example via interface 50, LAN interface 51, or USB interface 52, it starts the control shown in Figure 6. In S200, the CPU 45 sets the variable N to 1. The variable N determines which of the three registers REG1, REG2, and REG3 the CPU 45 writes the on-period information to. When N=1, the CPU 45 writes the on-period information to the first register REG1. When N=2, the CPU 45 writes the on-period information to the second register REG2. When N=3, the CPU 45 writes the on-period information to the third register REG3.

[0063] In S201, the CPU 45 initializes the register REG of the timing generator 46. More specifically, the CPU 45 initializes the first register REG1, the second register REG2, and the third register REG3. For example, the CPU 45 sets the ON-Time WID values ​​stored in the first register REG1, the second register REG2, and the third register REG3 to 0.

[0064] In S202, the CPU 45 obtains the temperature detected by the thermistor 32 of the heater 31.

[0065] In S203, the CPU 45 determines the control pattern for the triac 42 according to the temperature detected in S202. The control pattern is defined for each half-wave of the AC voltage Vin, determining whether the triac 42 is in the ON state or the OFF state.

[0066] Figure 7 shows a table 70 illustrating an example of the relationship between the detected temperature of the heater 31 detected by the thermistor 32 and the control pattern of the triac 42. In the table 70 shown in Figure 7, the leftmost column shows levels corresponding to the difference between the target temperature and the detected temperature of the heater 31 detected by the thermistor 32, and the rightmost column shows examples of control patterns corresponding to those levels. The target temperature is the temperature of the heater 31 suitable for fixing the image with developer onto the sheet 5 by the fixing unit 7. The level increases as the detected temperature falls below the target temperature. For example, the level is 1 when the detected temperature is equal to or greater than the target temperature, and the level increases as the difference Td (the difference between the target temperature and the detected temperature) increases by a predetermined temperature.

[0067] The control pattern defines whether the state of the triac 42 should be ON or OFF for each half-wave of the AC voltage Vin, i.e., each half-wave of the AC voltage Vin, corresponding to the period during which the edge input from the zero-crossing signal is detected. In the control pattern shown in Figure 7, half-waves that turn the triac 42 ON are represented as "ON," and half-waves that turn it OFF are represented as "OFF," with the state transitions of the triac 42 represented by the "ON" and "OFF" columns.

[0068] The control pattern is designed so that the heater 31 heats the fixing roller 22 more strongly as the level increases, that is, as the temperature detected by the heater 31 falls significantly below the target temperature. The half-wavenumbers of "ON" included in each control pattern are shown in the third column from the left in Figure 7, and the half-wavenumbers of "OFF" are shown in the fourth column from the left in Figure 7. The second column from the left in Table 70 shows the proportion of "ON" half-wavenumbers included in that control pattern and the heating intensity (power) of the heater 31.

[0069] For example, in S203 of Figure 6, if the CPU 45 determines that the detected temperature of the heater 31 is "Level 4", it sets the control pattern to "ON ON OFF". In this case, the state of the triac 42 transitions to the ON state at the timing of the next half-wave when an edge input is detected, for example, the half-wave when the (x+1)th edge input is detected. Furthermore, the state of the triac 42 transitions to the ON state again at the next half-wave when an edge input is detected, for example, the half-wave when the (x+2)th edge input is detected. And then, it transitions to the OFF state at the next half-wave when an edge input is detected again, for example, the half-wave when the (x+3)th edge input is received.

[0070] When the CPU 45 determines the control pattern in S203 in Figure 6, it waits until edge-on information is held in the latch circuit 47 (S205:YES) (S204). More specifically, in S204, the CPU 45 waits for a predetermined period, for example, 5ms. If edge-on information is held in the latch circuit 47 during the wait in S204 (S205:YES), the CPU 45 initializes the latch circuit 47 (S206) and starts executing the heater lighting determination shown in Figure 8 (S207). On the other hand, if edge-on information is not held in the latch circuit 47 during the wait in S204 (S205:NO), the CPU 45 proceeds to S204 and waits for a predetermined period again.

[0071] Figure 8 is a flowchart of the heater activation determination performed by the CPU 45 in S207 of Figure 6. In S300 of Figure 8, the CPU 45 determines whether it is in the final control of the control pattern. For example, if the control pattern was just determined to be "ON ON OFF" in S203 of Figure 6, the CPU 45 determines that it is not the final control of the control pattern, "OFF" in "ON ON OFF" (S300: NO), and executes the second register write process shown in Figure 9 (S301). For example, if the control pattern was determined to be "ON" in S203, the CPU 45 determines that it is the final control of the control pattern (S300: YES), and proceeds to S302.

[0072] In the following, the case where the control pattern is determined to be "ON ON OFF" in S203 of Figure 6 will be explained using Figures 9, 10, and 11. Figure 9 is a flowchart of the second register write process executed by the CPU 45 in S301 of Figure 8. Figure 10 is a timing chart of the on / off signals output from the timing generator 46 when the control pattern is determined to be "ON ON OFF". Figure 11 is a flowchart of the first register write process executed by the CPU 45 in S304 of Figure 8.

[0073] In S400 of Figure 9, the CPU 45 determines whether the ON period information to be written to register REG will turn on the state of the triac 42 at the timing of detecting the input of the next edge E1. For example, based on the "ON" at the beginning of the control pattern "ON ON OFF", the CPU 45 determines that the ON period information to be written to register REG will turn on the state of the triac 42 at the timing of detecting the input of the next edge E1 (S400: YES), and proceeds to S401.

[0074] In S401, the CPU 45 determines whether the ON period information to be written to register REG at the timing of detecting the input of the next edge E1 will turn the state of the triac 42 ON at the timing of detecting the input of the next edge E2. For example, based on the second "ON" of the control pattern "ON ON OFF", the CPU 45 determines that the ON period information to be written to register REG at the timing of detecting the input of the next edge E1 will turn the state of the triac 42 ON at the timing of detecting the input of the next edge E2 (S401: YES), and proceeds to S402.

[0075] In S402, the CPU 45 writes information about the on-period to register REG. Since variable N has not been updated since setting it to 1 in S200 in Figure 6, the CPU 45 writes information to the first register REG1. The on-period information written to the first register REG1 in S402 is denoted as delay time DLY1, on-period WID1, and time PER1, respectively. In S402, the CPU 45 sets the on-period WID1 to a time longer than a predetermined time T. The predetermined time T is, for example, the half-wave period of the AC voltage Vin. By writing the on-period information to the first register REG1, the on-period during which the state of the triac 42 is ON at the timing of detecting the input of the next edge E1 is determined. In the example in Figure 10, the half-wave period of the AC voltage Vin is 10ms. After writing the information to the first register REG1, the CPU 45 proceeds to S305 in Figure 8.

[0076] In S305 of Figure 8, the CPU 45 increments the value of variable N by 1. This operation makes N=2, and the next register to which the ON period information is written becomes the second register REG2. Since the variable N does not exceed the number of registers REG provided in the timing generator 46 (S306: NO), the CPU 45 finishes the heater lighting check in Figure 8 and proceeds to S208 in Figure 6.

[0077] In S208 of Figure 6, the CPU 45 has not yet finished controlling the heater 31 for the control pattern "ON ON OFF" determined in S203, so it proceeds to S204 and waits until edge-on information is held in the latch circuit 47 (S204, S205: NO). When edge-on information is held in the latch circuit 47 (S205: YES), that is, when the input of the next edge E1 of the zero-crossing signal is detected, the CPU 45 initializes the latch circuit 47 (S206) and starts executing the heater lighting determination shown in Figure 8 (S207). Meanwhile, at this timing when the input of the next edge E1 of the zero-crossing signal is detected (S100 in Figure 5: YES), the first PWM block BL1 reads the ON period information, delay time DLY1, ON time WID1, and time PER1 written in S402 of Figure 9 (S101) and outputs the first PWM signal (S103). An example of the first PWM signal output in S103 is shown in Figure 10.

[0078] As shown in Figure 10, the first PWM signal is delayed by a delay time DLY1 from the moment the input edge E1 of the zero-crossing signal is detected, and is high level for an on time WID1. Because the first PWM signal is high level, the on / off signal, which is the superposition of the first to third PWM signals, is also high level due to the OR circuits OR1 and OR2 in Figure 4. Therefore, as indicated by the "ON" at the beginning of the control pattern "ON ON OFF", the state of the triac 42 is in the ON state.

[0079] Let's return to the explanation of the control of the heater 31 by the CPU 45. The CPU 45 restarts the heater lighting determination shown in Figure 8. Since the CPU 45 is controlling the first "ON" of the control pattern "ON ON OFF", it determines that it is not the last control of the control pattern, "OFF" of "ON ON OFF" (S300: NO), and executes the second register write process shown in Figure 9 (S301). In S400 of Figure 9, the CPU 45 determines, based on the second "ON" of the control pattern "ON ON OFF", that the ON period information to be written to register REG this time will turn on the state of the triac 42 at the timing of detecting the input of the next edge E2 (S400: YES), and proceeds to S401.

[0080] In S401, the CPU 45 determines, based on the last "OFF" in the control pattern "ON ON OFF", that the ON period information to be written to register REG at the timing when the next edge input is detected will not turn on the state of the triac 42 at the timing when the next edge E3 input is detected (S401: NO), and proceeds to S403.

[0081] In S403, the CPU 45 writes the on-period information to the second register REG2 because the variable N is 2. The on-period information written to the second register REG2 in S403 is designated as the delay time DLY2, the on-period WID2, and the on-period PER2, respectively. The CPU 45 sets the on-period WID2 to a time shorter than the predetermined time T. By writing the on-period information to the second register REG2, the on-period during which the state of the triac 42 is on at the timing of detecting the input of the next edge E2 is determined. After writing the information to the second register REG2, the CPU 45 proceeds to S305 in Figure 8.

[0082] In S305 of Figure 8, the CPU 45 increments the value of variable N by 1. This operation makes N=3, and the next register to which the ON period information is written becomes the third register, REG3. Since the variable N does not exceed the number of registers REG provided in the timing generator 46 (S306: NO), the CPU 45 finishes the heater lighting check in Figure 8 and proceeds to S208 in Figure 6.

[0083] In S208 of Figure 6, the CPU 45 has not yet finished controlling the heater 31 for the control pattern "ON ON OFF" determined in S203, so it proceeds to S204 and waits until the latch circuit 47 holds edge-on information (S204, S205: NO). When the latch circuit 47 holds edge-on information (S205: YES), the CPU 45 initializes the latch circuit 47 (S206) and starts executing the heater lighting determination shown in Figure 8 (S207). At this timing when the input of the next edge E2 of the zero-crossing signal is detected, the second PWM block BL2 reads the ON period information written in S403 of Figure 9 using the same control as in Figure 5 (S101) and outputs the second PWM signal (S103). An example of the second PWM signal output in S103 is shown in Figure 10.

[0084] As shown in Figure 10, the second PWM signal is delayed by a delay time DLY2 from the moment the input of the zero-crossing signal edge E2 is detected, and is high level for an on time WID2. Because the second PWM signal is high level, the on / off signal, which is the superposition of the first to third PWM signals, also becomes high level due to the OR circuits OR1 and OR2 in Figure 4. Therefore, as indicated by the second "ON" in the control pattern "ON ON OFF", the state of the triac 42 is in the ON state.

[0085] Because the on-time WID1 of the first PWM signal is set to be longer than half a wave of the AC voltage Vin, both the first and second PWM signals are at a high level when the input of edge E2 is detected. If the first PWM signal goes to a low level earlier than the timing when the input of edge E2 is detected, the on / off signal will briefly become low, which may generate noise. In the image forming apparatus 1 of Embodiment 1, the on-time WID1 of the first PWM signal is set to be longer than half a wave of the AC voltage Vin, so the on / off signal does not temporarily become low, and thus noise generation is suppressed.

[0086] The CPU 45 restarts the heater activation check shown in Figure 8. Since the CPU 45 is performing the second "ON" control of the control pattern "ON ON OFF", it determines that it is not the last control of the control pattern, "OFF" of "ON ON OFF" (S300: NO), and executes the second register write process shown in Figure 9 (S301). In S400 of Figure 9, the CPU 45 determines, based on the last "OFF" of the control pattern "ON ON OFF", that the information to be written to register REG this time will not turn on the state of the triac 42 when the next edge E3 input is detected (S400: NO), and terminates the process in Figure 9 without writing any information to the third register REG3, proceeding to S305 in Figure 8.

[0087] In S305 of Figure 8, the CPU 45 increments the value of variable N by 1. This operation results in N=4. Since the value of variable N exceeds the number of registers REG provided in the timing generator 46 (S306: YES), the CPU 45 initializes variable N to 1 (S307). Therefore, the next register REG to which the ON period information is written becomes the first register REG1. After initializing variable N (S307), the CPU 45 completes the heater lighting determination in Figure 8 and proceeds to S208 in Figure 6.

[0088] In S208 of Figure 6, the CPU 45 has not yet finished controlling the heater 31 for the control pattern "ON ON OFF" determined in S203, so it proceeds to S204 and waits until the latch circuit 47 holds edge-on information (S204, S205: NO). When the latch circuit 47 holds edge-on information (S205: YES), the CPU 45 initializes the latch circuit 47 (S206) and starts executing the heater lighting determination shown in Figure 8 (S207). At this timing, when the input of the next edge E3 of the zero-crossing signal is detected, the third PWM block BL3 reads information from the third register REG3 using the same control as in Figure 5 (S101). Since the CPU 45 has not written information to the third register REG3, and the WID written to the third register REG3 remains at the cleared value of 0 (S102: NO), the third PWM block BL3 does not output the third PWM signal, as shown in Figure 10. Therefore, as indicated by the "OFF" at the end of the control pattern "ON ON OFF", the state of the triac 42 will be the OFF state.

[0089] In Figure 10, the on-time WID2 of the second PWM signal is set to be shorter than half a wave of the AC voltage Vin, so the on / off signal is at a low level when the input of edge E3 is detected. Therefore, the triac 42 is in the off state when the input of edge E3 is detected. If the on-time WID2 of the second PWM signal were set to be longer than half a wave of the AC voltage Vin, similar to the second PWM signal, the on / off signal would be at a high level until timing T1 shown in Figure 10. If the on / off signal of the triac 42 is at a high level when the input of edge E3 is detected, it may not be able to remain in the off state until the next edge input is detected, and the heater 31 may not be controlled according to the control pattern. Some AC power supplies have unstable half-wave periods. As shown in Figure 10, if the period of the half-wave immediately preceding the half-wave that turns the triac 42 off becomes shorter than usual, there is a high possibility that the heater 31 will not be controlled according to the control pattern. In S403, the CPU 45 sets the on-time WID to a time shorter than half a wave of the AC voltage Vin, thereby enabling the triac 42 to be properly turned off even if the AC power supply cycle is unstable.

[0090] The CPU 45 restarts the heater ignition determination shown in Figure 8. The CPU 45 determines that it is the final "OFF" control of the control pattern "ON ON OFF" (S300: YES) and obtains the detected temperature of the heater 31 from the thermistor 32 (S302). In S303, the CPU 45 determines the next control pattern of the triac 42 according to the detected temperature obtained in S302. In the following explanation, it will be assumed that the next control pattern of the triac 42 has been determined to be "ON OFF". Note that at the time of S302, the control pattern of the triac 42 does not immediately transition to the next control pattern.

[0091] When CPU 45 determines the next control pattern "ON OFF", it proceeds to S304. In S304, CPU 45 executes the first register write process shown in Figure 11. In S500 of Figure 11, CPU 45 determines, based on the "ON" at the beginning of the next control pattern "ON OFF" determined in S303 of Figure 8, that the ON period information to be written to register REG this time will turn on the state of triac 42 at the timing when the next edge input is detected (S500: YES), and proceeds to S501.

[0092] In S501, the CPU 45, based on the "OFF" in the next control pattern "ON OFF" determined in S303, determines that the ON period information to be written to register REG at the timing when the next edge E3 input is detected will not turn on the state of the triac 42 at the timing when the next edge input is detected (S501: NO), and proceeds to S503.

[0093] In S503, since the variable N is 1, the CPU 45 writes the on-time information to the first register REG1. The CPU 45 sets the on-time WID to a time shorter than half a wave of the AC voltage Vin. After writing the information to the first register REG1, the CPU 45 proceeds to S305 in Figure 8.

[0094] In S305 of Figure 8, the CPU 45 increments the value of variable N by 1. This operation results in N=2. Since the value of variable N does not exceed the number of registers REG in the timing generator 46 (S306: NO), the CPU 45 finishes the heater lighting determination in Figure 8 and proceeds to S208 in Figure 6. Since the CPU 45 has finished controlling the control pattern "ON ON OFF" determined in S203 (S208: YES), it updates the control pattern to the next control pattern "ON OFF" determined in S303 of Figure 8 (S209).

[0095] In S210, the CPU 45 determines whether to finish controlling the heater 31 and turn off the power to the heater 31. For example, if printing is completed for a print job received via interface 50, LAN interface 51, or USB interface 52, the CPU 45 determines to finish controlling the heater 31 and turn off the power (S210: YES), and terminates the control of the heater 31 as shown in Figure 6. On the other hand, if printing is not yet complete, for example, the CPU 45 determines to continue controlling the heater 31 (S210: NO), proceeds to S204, and controls the heater 31 using the updated control pattern "ON OFF".

[0096] The following provides supplementary information regarding the first register write process shown in Figure 11. In S501, if the CPU 45 determines, based on the next control pattern determined in S303, that the ON period information to be written to register REG at the timing when the next edge input is detected will turn on the state of the triac 42 at the timing when the next edge input is detected (S501: YES), then proceed to S502.

[0097] In S502, the CPU 45 writes information about the on-time to register REG, which corresponds to the variable N. In S502, the CPU 45 writes a time longer than half a wave of the AC voltage Vin to register REG as the on-time WID. After the CPU 45 has finished writing the information to register REG, which corresponds to the variable N, it proceeds to S305 in Figure 8.

[0098] [Effects of Embodiment 1] According to the image forming apparatus 1 of Embodiment 1 described above, the CPU 45 determines an ON period for turning on the state of the triac 42 in response to an input such as the edge E1 of a zero-crossing signal, and controls the timing generator 46 to output a first PWM signal, a second PWM signal, a third PWM signal, and an ON / OFF signal based on the determined ON period in response to the next input such as the edge E2 (Figures 9 and 11). According to the above configuration, the CPU 45 determines the on-periods of the first PWM signal, the second PWM signal, the third PWM signal, and the on-off signal that the timing generator 46 outputs in accordance with the next edge E2 of the zero-crossing signal, prior to the input of the next edge E2, and controls the timing generator 46 to output an on-off signal that keeps the triac 42 in the on state for the determined on-period at the timing of the actual next edge E2 of the zero-crossing signal. Because the on-period is determined prior to the input of the next edge E2, the heater 31 can be controlled more easily than in the conventional method.

[0099] Furthermore, the image forming apparatus 1 is further equipped with a thermistor 32 that detects the temperature of the heater 31 of the fixing unit 7. Based on the temperature of the heater 31 detected by the thermistor 32, the CPU 45 controls the timing generator 46 using a control pattern (such as "ON ON OFF" as defined by the table 70 in Figure 7) that is defined for each half-wave of the AC voltage Vin, to determine whether to turn the triac 42 on or off. When the CPU detects an input such as the edge E1 of a zero-crossing signal, and the control pattern is defined to turn the triac 42 on when the next edge E2 is input, and to turn the triac 42 off when the next edge E2 is input, the CPU 45 decides to make the WID shorter than a predetermined period T. According to the above configuration, if the control pattern specifies that the triac 42 should be turned ON when the next input such as edge E2 is detected, and then turned OFF when the next input such as edge E3 is detected, shortening the WID can prevent the triac 42 from being turned OFF due to fluctuations in the waveform of the AC voltage Vin.

[0100] Furthermore, when the CPU 45 detects an input such as the edge E1 of a zero-crossing signal, if the control pattern specifies that the state of the triac 42 should be turned on when the next edge E2 is input, and then again when the next edge E2 is input, the CPU 45 decides to make the WID longer than a predetermined period T. According to the above configuration, if the control pattern specifies that the state of the triac 42 should be turned on when the next input such as edge E1 is detected, and then when the next input such as edge E2 is detected, increasing the WID (Wireless Indicator) allows the state of the triac 42 to be continuously turned on, that is, AC voltage to be continuously supplied to the heater, thereby suppressing the generation of noise.

[0101] [Embodiment 2] Other embodiments of this disclosure are described below. For the sake of clarity, components having the same function as those described in the above embodiments are denoted by the same reference numerals, and their descriptions are not repeated.

[0102] In Embodiment 2, the second register write process (Figure 9) executed in S301 in Figure 8 and the first register write process (Figure 11) executed in S304 are both the processes shown in Figure 12. Figure 12 is a flowchart relating to the first register write process and the second register write process in Embodiment 2.

[0103] In S600, the CPU 45 makes the same determination as in S400 in Figure 9. That is, based on the control pattern, the CPU 45 determines whether the information to be written to register REG will turn on the state of triac 42 at the timing of detecting the input of the next edge. If the information to be written to register REG will turn on the state of triac 42 at the timing of detecting the input of the next edge (S600: YES), the CPU 45 proceeds to S601. On the other hand, if the information to be written to register REG will not turn on the state of triac 42 at the timing of detecting the input of the next edge (S600: NO), the CPU 45 proceeds to S604.

[0104] In S601, the CPU 45 determines, based on the control pattern, whether the information previously written to register REG turned the triac 42 to the ON state. For example, if, at the time of detecting the input of the (x-1) edge in the previous step, information was written to the second register REG2 based on the second "ON" of the control pattern "ON ON OFF", the CPU 45 will affirm S601 at the time of detecting the input of the x-th edge in the current step. If the CPU 45 affirms S601 (S601:YES), it proceeds to S602; if it denies S601 (S601:NO), it proceeds to S603.

[0105] In S602, the CPU 45 writes information about the on-time to the register REG corresponding to the variable N. At this time, the CPU 45 sets the delay time DLY to 0 and sets the on-time WID to a time longer than the predetermined time T.

[0106] In S603, the CPU 45 writes information about the on-time to the register REG corresponding to the variable N. At this time, the CPU 45 sets the delay time DLY to a time longer than 0 and the on-time WID to a time shorter than the predetermined time T.

[0107] In S604, the CPU 45 stores in a memory unit (not shown) information on whether the ON period information written to register REG this time resulted in the triac 42 being in an ON state or an OFF state. When the next edge is detected, the stored information will indicate whether the ON period information previously written to register REG resulted in the triac 42 being in an ON state. In S601, the CPU 45 may also determine, based on this information, whether the information previously written to register REG resulted in the triac 42 being in an ON state.

[0108] Figure 13 is a diagram illustrating the information about the ON period set in S602 and S603 of Figure 12. In Figure 13, the zero-crossing signal edges E4-E8 are input sequentially. When the input of edges E4 and E8 is detected, the state of the triac 42 is turned OFF based on the control pattern. When the input of edges E5-E7 is detected, the state of the triac 42 is turned ON based on the control pattern. The variable N is assumed to be N=1 when edge E4 is detected.

[0109] (Detection timing of input at edge E4) At the detection timing of the input of edge E4, the information on the on-period that the CPU 45 writes to the register REG is to turn on the state of the triac 42 at the detection timing of the input of edge E5. And at the detection timing of the input of the edge immediately before edge E4, the information on the on-period that the CPU 45 wrote to the register REG is to turn off the state of the triac 42 at the detection timing of the input of edge E4. Therefore, at the detection timing of the input of edge E4, the CPU 45 makes an affirmative determination for S600 in FIG. 12 and a negative determination for S601. The CPU 45 writes the delay time DLY3, the on-time WID3, and the time PER3 to the first register REG1 in S603. The delay time DLY3 is set to a value greater than 0. The on-time WID3 is set to a time shorter than the predetermined time T. For example, the on-time WID3 is set such that T - DLY3 < WID3 < T.

[0110] (Detection timing of edge E5) At the detection timing of the input of edge E5, the first PWM block BL1 reads the delay time DLY3, the on-time WID3, and the time PER3 from the first register REG1 (S101 in FIG. 5) and outputs the first PWM signal (S103). Also, at the detection timing of the input of edge E5, the information on the on-period that the CPU 45 writes to the register REG is to turn on the state of the triac 42 at the detection timing of the input of edge E6. And at the detection timing of the input of edge E4, which is the edge immediately before edge E5, the information that the CPU 45 wrote to the first register REG1 is to turn on the state of the triac 42 at the detection timing of the input of edge E5. Therefore, at the detection timing of the input of edge E5, the CPU 45 makes an affirmative determination for S600 and S601 in FIG. 12. The CPU 45 writes the delay time DLY4, the on-time WID4, and the time PER4 to the second register REG2 in S603. The delay time DLY4 is set to 0. The on-time WID4 is set to a time longer than the predetermined time T.

[0111] (Detection timing of edge E6) At the detection timing of edge E6, the second PWM block BL2 reads the delay time DLY4, on time WID4, and time PER4 from the second register REG2 (S101 in Figure 5) and outputs the second PWM signal (S103). Also, at the detection timing of the input of edge E6, the on-period information that the CPU 45 writes to register REG will turn on the state of the triac 42 at the detection timing of the input of edge E7. Then, at the detection timing of the input of edge E5, which is one edge before edge E6, the on-period information that the CPU 45 wrote to the second register REG2 will turn on the state of the triac 42 at the detection timing of the input of edge E6. Therefore, at the detection timing of the input of edge E6, the CPU 45 affirms S600 and S601 in Figure 12. In S603, the CPU 45 writes the delay time DLY5, on time WID5, and time PER5 to the third register REG3. The delay time DLY5 is set to 0. The ON time WID5 is set to a time longer than the predetermined time T.

[0112] (Edge E7 detection timing) At the detection timing of edge E7, the third PWM block BL3 reads the delay time DLY5, on time WID5, and time PER5 from the third register REG3 (S101 in Figure 5), and outputs the third PWM signal (S103). Also, at the detection timing of the input of edge E7, the on-period information that the CPU 45 writes to register REG will turn off the state of the triac 42 at the detection timing of the input of edge E8. Then, at the detection timing of the input of edge E6, which is one edge before edge E7, the on-period information that the CPU 45 wrote to the third register REG3 will turn on the state of the triac 42 at the detection timing of the input of edge E7. Therefore, at the detection timing of the input of edge E7, the CPU 45 negates S600 in Figure 12 and does not write any information to register REG.

[0113] By setting the on-time WID3 to be longer than T-DLY3 and the delay time DLY4 to 0, it is possible to prevent the on / off signal from temporarily becoming low level near the detection timing of the edge E6 input, thereby preventing the generation of noise. Furthermore, by setting the on-time WID4 to be longer than the predetermined time T and the delay time DLY5 to 0, it is possible to prevent the on / off signal from temporarily becoming low level near the detection timing of the edge E7 input, thereby preventing the generation of noise.

[0114] [Effects of Embodiment 2] In the image forming apparatus 1 according to Embodiment 2 described above, the CPU 45 controls the timing generator 46 to output a pulse signal without delay in response to the input of the next edge E6, if the control pattern at the timing of detecting the input of edge E5, etc. of a zero-crossing signal specifies that when it detects the input of edge E4, etc., the state of the triac 42 at the time of detection of the input of edge E5, etc. is set to ON, and the state of the triac 42 at the time of the input of the next edge E6, etc. is set to ON. According to the above configuration, for example, if the control pattern specifies that the state of the triac 42 is turned ON when the input of edge E5 is detected, and then the state of the triac 42 is turned ON when the input of edge E6 is detected, the second PWM block BL2 of the timing generator 46 of edge E6 outputs the second PWM signal without delay (delay time DLY4=0), thereby keeping the triac in an ON state continuously, that is, continuously supplying AC voltage to the heater, and since there is no OFF state in the pulse signal, the generation of noise can be prevented.

[0115] [Variation] In Embodiments 1 and 2 described above, the zero-crossing circuit 43 is configured such that the zero-crossing signal falls from a high level to a low level when the absolute value of the AC voltage Vin falls below a predetermined threshold voltage Vth, and rises from a low level to a high level when the absolute value of the AC voltage exceeds the threshold voltage Vth. However, the circuit configuration of the zero-crossing circuit 43 is not limited to this. For example, the zero-crossing circuit 43 may be configured such that the zero-crossing signal rises from a low level to a high level when the absolute value of the AC voltage Vin exceeds a predetermined threshold voltage Vth, and falls from a high level to a low level when the absolute value of the AC voltage exceeds the threshold voltage Vth. In this case, the latch circuit 47 should hold edge-on information at the timing when the rising edge of the zero-crossing signal is detected. The timing generator 46 should output an on / off signal to the low-voltage power supply 41 according to the rising edge of the zero-crossing signal.

[0116] In the above embodiments 1 and 2, the timing generator 46 has a first PWM block BL1, a second PWM block BL2, and a third PWM block BL3, each of which is an example of an output unit. The timing generator 46 also has a register REG, which is an example of a storage unit, in each of the first PWM block BL1, the second PWM block BL2, and the third PWM block BL3. Having three output units in the timing generator 46 is effective when the period during which the CPU 45 accesses the latch circuit 47 is long. However, the number of output units and storage units in the timing generator 46 is not limited to three each. The timing generator 46 may have four or more output units and storage units, or it may have only the first PWM block BL1 and the second PWM block BL2.

[0117] When the timing generator 46 is configured with a first PWM block BL1 and a second PWM block BL2, the CPU 45 checks whether the output of the PWM signal based on the information written to register REG has been completed at the timing of detecting past edge inputs before writing new information to register REG. The CPU 45 writes new information to register REG at the timing of detecting edge inputs after the output of the PWM signal based on the information written to register REG has been completed.

[0118] In Embodiments 1 and 2 described above, the control pattern was determined according to the detected temperature of the heater 31 detected by the thermistor 32, as shown in Figure 7. However, the control pattern of the heater 31 is not limited to that shown in Figure 7. For example, a control pattern other than the one shown in Figure 7 may be used, or the control pattern may be determined according to the difference Td between the detected temperature of the heater 31 and the target temperature of the heater 31.

[0119] This disclosure is not limited to the embodiments described above, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of this disclosure. [Explanation of symbols]

[0120] 1. Image forming apparatus 7 Fixing section 31 Heater 32 Thermistor 41 Low-voltage power supply 42 Triac 43 Zero-crossing circuits 44 SOC 45 CPU 46 Timing Generator 70 tables DLY, DLY1, DLY2, DLY3, DLY4, DLY5 Delay time E1, E2, E3, E4, E5, E6, E7, E8 Edge WID, WID1, WID2, WID3, WID4, WID5 On time REG register REG1 First Register REG2 Second Register REG3 Third Register T predetermined time Vin AC voltage Vth threshold voltage

Claims

1. A fuser having a heater that generates heat from the AC voltage supplied from an AC power source, which fixes the developer image onto a sheet, A switching element for switching the AC voltage supplied to the heater, the switching element switching between an ON state, which is a state in which the AC power supply and the heater are electrically connected, and an OFF state, which is a state in which the AC power supply and the heater are not electrically connected. A zero-crossing circuit that outputs a zero-crossing signal indicating the zero-crossing point of the AC voltage, Control unit and The switching element is provided with an output circuit that outputs a pulse signal, The pulse signal causes the switching element to be in the ON state for a period of time, depending on the rising or falling edge of the zero-crossing signal, and then the switching element to be in the OFF state. The control unit, The ON period is determined in response to the input of the edge of the zero-crossing signal, and the output circuit is controlled to output a pulse signal based on the determined ON period in response to the input of the next edge. An image forming apparatus characterized by the following features.

2. Furthermore, it is equipped with a temperature sensor that detects the temperature of the fuser, The control unit, Based on the temperature detected by the temperature sensor, the output circuit is controlled using a control pattern defined for each half-wave of the AC voltage to determine whether to set the switching element to the ON state or the OFF state. When the input of the edge of the zero-crossing signal is detected, if the control pattern specifies that the state of the switching element should be set to the ON state when the next edge is input, and the state of the switching element should be set to the OFF state when the next edge is input, then it is determined that the ON period should be shorter than a predetermined period. The image forming apparatus according to feature 1.

3. The control unit, When the input of the edge of the zero-crossing signal is detected, if the control pattern specifies that the state of the switching element should be turned on when the next edge is input, and that the state of the switching element should be turned on when the next edge is input, then the ON period is determined to be longer than the predetermined period. The image forming apparatus according to feature 2.

4. The control unit, At the timing when the input of the edge of the zero-crossing signal is detected, the determined ON period information is written to the storage unit of the output circuit. The output circuit described above is Based on the ON-period information stored in the memory unit, the pulse signal is output in response to the next edge input. The image forming apparatus according to feature 3.

5. Furthermore, it is equipped with a temperature sensor that detects the temperature of the fuser, The control unit, Based on the temperature detected by the temperature sensor, the output circuit is controlled using a control pattern defined for each half-wave of the AC voltage to determine whether to set the switching element to the ON state or the OFF state. If the control pattern specifies that when the input of the edge of the zero-crossing signal is detected, the state of the switching element at the time of detection of the input of that edge is set to the ON state, and the state of the switching element at the time of the input of the next edge is set to the ON state, then the output circuit is controlled to output a pulse signal without delay in response to the input of the next edge. The image forming apparatus according to feature 1.

6. The control unit, If the control pattern specifies that when the input of the edge of the zero-crossing signal is detected, the state of the switching element at the time of detection of the edge input is set to the off state, and the state of the switching element at the time of the next edge input is set to the on state, then the output circuit is controlled to output a pulse signal with a delay in response to the input of the next edge. The image forming apparatus according to feature 5.

7. The control unit, If the control pattern specifies that when the input of the edge of the zero-crossing signal is detected, the state of the switching element at the time of detection of the edge input is set to the ON state, and the state of the switching element at the time of the next edge input is set to the ON state, then the ON period is made longer than the half-wave period of the AC voltage. The image forming apparatus according to feature 5.

8. The control unit, At the timing when the input of the edge of the zero-crossing signal is detected, the determined ON period information is written to the storage unit of the output circuit. The output circuit described above is Based on the ON-period information stored in the memory unit, the pulse signal is output in response to the next edge input. The image forming apparatus according to feature 6.

9. The output circuit described above is The switching element has multiple output units that output a PWM signal in which the switching element is in the ON state for a period of time in accordance with the rising or falling edge of the zero-crossing signal, and then the switching element is in the OFF state. The plurality of output units sequentially output PWM signals in response to the input of the edge of the zero-crossing signal. The pulse signal is generated by superimposing the PWM signals output by the multiple output units of the output circuit. The image forming apparatus according to feature 1.

10. The output circuit described above is The aforementioned plurality of output units consist of three output units. Each of the three output units has a storage unit in which information about the determined ON period is written at the timing when the input of the edge of the zero-crossing signal is detected. The three output units output the pulse signal in response to the next edge input, based on the ON period information stored in the corresponding memory unit. The image forming apparatus according to feature 9.

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