FIR filter, FIR filter filtering method, and control program

Abstract

To provide an FIR filter, filtering method by the FIR filter, and a control program, capable of restricting increase in circuit scale.SOLUTION: An FIR filter includes an address signal generation unit for generating an address signal with an address value corresponding to k pieces of bit values corresponding to filter coefficients of k (k is an integer of 2 or more) pieces having symmetry, a storage unit for storing a table in which a plurality of address values and a plurality of calculation results are associated, and an extraction unit for extracting a calculation result corresponding to an address value indicated by an address signal generated by the address signal generation unit from the table, and in the table, a plurality of address values are associated with the plurality of calculation results having common calculation results that show the same value, among calculation results of k-th power of 2 obtained by adding k multiplication results, which are the results of multiplying each of the k filter coefficients with symmetry by the k bit values corresponding to the k filter coefficients.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a FIR filter, a filtering method using the FIR filter, and a control program.

Background Art

[0002] In recent years, in a FIR filter which is a type of digital filter, in order to meet the requirement of improving processing performance, the number of taps has a tendency to increase, and accordingly, the circuit scale has increased dramatically.

[0003] A solution to this problem is disclosed in, for example, Patent Document 1. The digital filter arithmetic processing circuit disclosed in Patent Document 1 reduces the number of multiplications by half as compared with the case where the filter coefficients do not have symmetry by making the filter coefficients have symmetry. Thereby, since the number of multiplication circuits can be reduced, an increase in the circuit scale can be suppressed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, the processing circuit disclosed in Patent Document 1 has a problem that since the scale of each multiplication circuit is large, the circuit scale as a whole still becomes large.

[0006] One object of the present disclosure is to provide a FIR filter, a filtering method using the FIR filter, and a control program that solve the above-described problems.

Means for Solving the Problems

[0007] An FIR filter according to one aspect of the present disclosure includes: an address signal generation unit that generates an address signal corresponding to k bit values ​​corresponding to k symmetrical filter coefficients (where k is an integer of 2 or more); a storage unit that stores a table associated with a plurality of address values ​​and a plurality of calculation results; and an extraction unit that extracts from the table a calculation result corresponding to the address value indicated by the address signal generated by the address signal generation unit, wherein the table associates a plurality of calculation results with a plurality of address values, where the k multiplication results are obtained by multiplying each of the k symmetrical filter coefficients and the k bit values ​​corresponding to the k filter coefficients, resulting in a total of 2 to the power of k possible calculation results, of which sets of calculation results showing the same value are common.

[0008] A filtering method using an FIR filter according to one aspect of the present disclosure is a filtering method using an FIR filter, which generates an address signal corresponding to k bit values ​​corresponding to k symmetrical filter coefficients (where k is an integer of 2 or more), and extracts the calculation result corresponding to the address value indicated by the generated address signal from a table stored in a memory device, in which a plurality of address values ​​and a plurality of calculation results are associated, wherein the table associates a plurality of calculation results with a plurality of address values, where the k multiplication results are obtained by multiplying each of the k symmetrical filter coefficients and the k bit values ​​corresponding to the k filter coefficients, resulting in a total of 2 to the power of k possible calculation results, of which sets of calculation results showing the same value are common.

[0009] A control program according to one aspect of the present disclosure is a control program that causes a computer to perform the following steps: generate an address signal corresponding to k bit values ​​corresponding to k symmetrical filter coefficients (where k is an integer of 2 or more); and extract the calculation result corresponding to the address value indicated by the generated address signal from a table stored in a memory device, which associates a plurality of address values ​​with a plurality of calculation results, wherein the table associates a plurality of calculation results with a plurality of address values, where the k multiplication results are obtained by multiplying each of the k symmetrical filter coefficients and the k bit values ​​corresponding to the k filter coefficients, resulting in 2 to the power of k possible calculation results, of which pairs of calculation results showing the same value are common. [Effects of the Invention]

[0010] This disclosure provides an FIR filter, a filtering method using an FIR filter, and a control program that can suppress an increase in circuit size. [Brief explanation of the drawing]

[0011] [Figure 1] This figure shows an example configuration of an FIR filter according to Embodiment 1. [Figure 2] This figure shows a specific example of the configuration of the FIR filter according to Embodiment 1. [Figure 3] This diagram illustrates how to determine the settings of the table used in the FIR filter according to Embodiment 1. [Figure 4] This figure shows an example of the settings for the table used in the FIR filter according to Embodiment 1. [Figure 5] This figure shows the correspondence between the input value, address value, and calculation result in the FIR filter according to Embodiment 1. [Figure 6] This figure illustrates how to determine the settings of the table used in the first modified example of the FIR filter according to Embodiment 1. [Figure 7]It is a diagram showing an example of the setting content of the table used in the first modification of the FIR filter according to Embodiment 1. [Figure 8] It is a diagram showing the correspondence relationship among the input value, the address value, and the calculation result in the first modification of the FIR filter according to Embodiment 1. [Figure 9] It is a diagram showing an example of the setting content of the table used in the second modification of the FIR filter according to Embodiment 1. [Figure 10] It is a diagram showing the correspondence relationship among the input value, the address value, and the calculation result in the second modification of the FIR filter according to Embodiment 1. [Figure 11] It is a diagram for explaining the concept of the FIR filter according to Embodiment 2. [Figure 12] It is a diagram showing a configuration example of the FIR filter in the conceptual stage. [Figure 13] It is a diagram showing a modification example of the FIR filter shown in FIG. 12. [Figure 14] It is a diagram showing a configuration example of the FIR filter in the conceptual stage. [Figure 15] It is a diagram showing a modification example of the FIR filter shown in FIG. 14. [Figure 16] It is a diagram showing an example of the setting content of the table used in the FIR filter shown in FIG. 15. [Figure 17] It is a diagram for explaining the processing flow by the FIR filter shown in FIG. 15.

Mode for Carrying Out the Invention

[0012] Hereinafter, embodiments will be described with reference to the drawings. Note that since the drawings are simplified, the technical scope of the embodiments should not be narrowly interpreted based on the description of these drawings. Also, the same elements are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0013] In the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is related to a partial or total modification example, application example, detailed description, supplementary explanation, etc. of the other. Also, in the following embodiments, when referring to the number of elements, etc. (including the number, numerical value, quantity, range, etc.), unless otherwise specified and unless it is clearly limited to a specific number in principle, it is not limited to that specific number, and it may be more than or less than the specific number.

[0014] Furthermore, in the following embodiments, the constituent elements (including operation steps, etc.) are not necessarily essential unless otherwise specified and unless it is clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the constituent elements, unless otherwise specified and unless it is clearly considered otherwise in principle, it includes those substantially approximating or similar to the shape, etc. This also applies to the above numbers, etc. (including the number, numerical value, quantity, range, etc.).

[0015] <Pre - examination by the inventors> Before explaining the FIR (Finite Impulse Response) filter 1 according to Embodiment 1, the content pre - examined by the inventors will be explained.

[0016] <Explanation of the FIR filter 50 in the conceptual stage> FIG. 12 is a diagram showing a configuration example of the FIR filter 50 in the conceptual stage. Hereinafter, the case where the number of taps (the number of filter coefficients) k of the FIR filter 50 is 4 will be explained, but it is not limited thereto, and k may be any integer of 2 or more.

[0017] As shown in Figure 12, the FIR filter 50 is an FIR-type digital filter that filters input data X(n) and outputs output data Y(n), and comprises three latch circuits 511 to 513 corresponding to k-1, four multiplier circuits 520 to 523 corresponding to k, and three adder circuits 531 to 533 corresponding to k-1.

[0018] The FIR filter 50 receives four input data points D3, D2, D1, and D0 in order as input data X(n) for a predetermined period up to time n. In the example in Figure 12, four input data points "2", "3", "4", and "5" are received in order as input data X(n) for a predetermined period up to time n.

[0019] Latch circuits 511-513 constitute a shift register, shifting input data D3, D2, D1, and D0 to nodes N53, N52, N51, and N50, respectively. Multiplier circuits 520-523 perform multiplication of the filter coefficients d0-d3 and the input data D0-D3, respectively. Adder circuit 531 performs addition of the multiplication result from multiplier circuit 520 and the multiplication result from multiplier circuit 521. Adder circuit 532 performs addition of the addition result from adder circuit 531 and the multiplication result from multiplier circuit 522. Adder circuit 533 performs addition of the addition result from adder circuit 532 and the multiplication result from multiplier circuit 523, and outputs the sum as output data Y(n). In the example in Figure 12, D0=5, D1=4, D2=3, and D3=2, so the output data Y(n) is expressed as follows.

[0020] Y(n)=d0×D0+d1×D1+d2×D2+d3×D3 = 5·d0 + 4·d1 + 3·d2 + 2·d3

[0021] Figure 13 shows a modified version of the FIR filter 50, designated as FIR filter 50a. The FIR filter 50a has symmetry in its filter coefficients d0 to d3 and, compared to the FIR filter 50, includes additional adders 540 and 541, while lacking multipliers 522 and 523 and adders 532 and 533. In other words, the FIR filter 50a effectively has half the number of multipliers compared to the FIR filter 50. Note that the symmetry in the filter coefficients d0 to d3 means that d0 = d3 and d1 = d2.

[0022] The adder circuit 540 adds input data D0 and input data D3. The adder circuit 541 adds input data D1 and input data D2. The multiplier circuit 520 multiplies the filter coefficient d0 (=d3) and the summation result D0+D3 from the adder circuit 540. The multiplier circuit 521 multiplies the filter coefficient d1 (=d2) and the summation result D1+D2 from the adder circuit 541. The adder circuit 531 adds the multiplication result from the multiplier circuit 520 and the multiplication result from the multiplier circuit 521, and outputs the summation result as output data Y(n). In the example in Figure 13, D0=5, D1=4, D2=3, D3=2, and d0=d3, d1=d2, so the output data Y(n) is expressed as follows.

[0023] Y(n)=d0×D0+d1×D1+d2×D2+d3×D3 =d0×(D0+D3)+d1×(D1+D2) = 7·d0 + 7·d1

[0024] Thus, by introducing symmetry to the filter coefficients d0 to d3, the FIR filter 50a can be constructed using fewer multiplication circuits than the FIR filter 50, thereby reducing the circuit size. However, the FIR filter 50a still suffers from the problem that the overall circuit size remains large due to the large size of each multiplication circuit. As a solution to this problem, the inventors then considered an FIR filter employing distributed arithmetic.

[0025] <Explanation of the FIR filter 60 in the conceptual stage> Figure 14 shows an example configuration of an FIR filter 60 employing distributed arithmetic. In the following explanation, we will use the case where the number of taps k of the FIR filter 60 is 4, as in the case of FIR filters 50 and 50a, as an example, but k is not limited to this and can be any integer greater than or equal to 2.

[0026] As shown in Figure 14, the FIR filter 60 is an FIR-type digital filter employing distributed arithmetic, and comprises three latch circuits 611-613, four multiplier circuits 620-623, three adder circuits 631-633, and an accumulator 641. The latch circuits 611-613 correspond to the latch circuits 511-513, the multiplier circuits 620-623 correspond to the multiplier circuits 520-523, and the adder circuits 631-633 correspond to the adder circuits 531-533.

[0027] The FIR filter 60 receives four input data points D3, D2, D1, and D0 in order as input data X(n) for a predetermined period up to time n. In the example in Figure 14, four input data points "2", "3", "4", and "5" are received in order as input data X(n) for a predetermined period up to time n.

[0028] The latch circuits 611-613 constitute a shift register, shifting input data D3, D2, D1, and D0 to nodes N63, N62, N61, and N60, respectively.

[0029] Multiplication circuits 620 to 623 each multiply the filter coefficients d0 to d3 by the bit values ​​b0 to b3 of the input data D0 to D3, which are represented in binary and have a width of m (where m is an integer greater than or equal to 1) bits.

[0030] Adder circuit 631 performs the addition of the multiplication result from multiplier circuit 620 and the multiplication result from multiplier circuit 621. Adder circuit 632 performs the addition of the addition result from adder circuit 631 and the multiplication result from multiplier circuit 622. Adder circuit 633 performs the addition of the addition result from adder circuit 632 and the multiplication result from multiplier circuit 623, and outputs the sum to accumulator 641.

[0031] The accumulator 641 takes a total of m operation results (outputs of the adder circuit 632) for the m bit values ​​b0 to b3 at the same bit position, from the 1st bit to the mth bit, of each of the m-bit wide input data D0 to D3 represented in binary, shifts the bits according to the bit position in each of the input data D0 to D3, and then cumulatively adds them up, outputting them as output data Y(n).

[0032] In the example in Figure 14, D0=5, D1=4, D2=3, and D3=2, which can be expressed in binary as D0=101, D1=100, D2=011, and D3=010.

[0033] First, the multiplier circuits 620-623 each multiply the filter coefficients d0-d3 by the bit value of the first bit (least significant bit) of the input data D0-D3, which is represented in binary, which is 1,0,1,0. The adder circuit 633 adds these multiplication results together and outputs them to the accumulator 641. The output result of the adder circuit 633 at this time is: (d0×1)+(d1×0)+(d2×1)+(d3×0)=d0+d2 This is the result.

[0034] Next, multiplier circuits 620-623 each multiply the filter coefficients d0-d3 by the second bit value of the input data D0-D3, which is represented in binary, which is 0,0,1,1. Adder circuit 633 adds these multiplication results together and outputs them to accumulator 641. The output result of adder circuit 633 at this time is: (d0×0)+(d1×0)+(d2×1)+(d3×1)=d2+d3 This is the result.

[0035] Next, multiplier circuits 620-623 each multiply the filter coefficients d0-d3 by the bit value of the third bit (most significant bit) of the input data D0-D3, which is represented in binary, which is 1, 1, 0, 0. Adder circuit 633 adds these multiplication results together and outputs them to accumulator 641. The output result of adder circuit 633 at this time is: (d0×1)+(d1×1)+(d2×0)+(d3×0)=d0+d1 This is the result.

[0036] Accumulator 641 holds the calculation result "d0 + d2" for the first bit value b0 to b3 of each input data D0 to D3 without bit shifting. Accumulator 641 then performs cumulative addition after bit shifting the calculation result "d2 + d3" for the second bit value b0 to b3 of each input data D0 to D3 one digit to the left. Furthermore, Accumulator 641 performs cumulative addition after bit shifting the calculation result "d0 + d1" for the third bit value b0 to b3 of each input data D0 to D3 two digits to the left. Finally, Accumulator 641 outputs the result of the cumulative addition as output data Y(n).

[0037] Here, the number of combinations between bit values ​​b0 to b3 and the results of operations performed by multiplier circuits 620 to 623 and adder circuits 631 to 633 is limited to 2 to the power of 4, or 16 combinations. Therefore, instead of using multiplier circuits 620 to 623 and adder circuits 631 to 633 to perform filtering, the FIR filter 60 can be further reduced in size by using a table 603 that contains multiple combinations of bit values ​​b0 to b3 and their corresponding operation results to perform filtering.

[0038] <Modified version of the FIR filter 60 in the conceptual stage> Figure 15 shows a modified example of the FIR filter 60, referred to as FIR filter 60a. As shown in Figure 15, the FIR filter 60a comprises a storage unit (memory device) 602 and an extraction unit 604.

[0039] The memory unit 602 stores a table 603 containing multiple combinations of bit values ​​b0 to b3 and the results of operations performed on them.

[0040] Figure 16 shows an example of the settings in Table 603. As shown in Figure 16, Table 603 contains 16 possible combinations of bit values ​​b0 to b3 (shown in the order of b3, b2, b1, b0 in Figure 16) and their corresponding calculation results.

[0041] The extraction unit 604 extracts a total of m calculation results from table 603 corresponding to the bit values ​​b0 to b3 at the same bit position for a total of m bits (3 bits in this example) from the 1st bit to the mth bit (3rd bit in this example) of the input data D0 to D3. Each result is bit-shifted according to its bit position in the input data D0 to D3 and then cumulatively added. The extraction unit 604 then outputs the result of the cumulative addition as output data Y(n).

[0042] Specifically, the extraction unit 604 comprises an acquisition unit 605 and an accumulator 606. The accumulator 606 includes, for example, a shifter 607, an adder circuit 608, and a latch circuit 609.

[0043] The acquisition unit 605 reads the calculation result of the address value indicated by bit values ​​b0 to b3 from the table 603 stored in the storage unit 102. Alternatively, the acquisition unit 605 may be a selector that selects and outputs the calculation result corresponding to bit values ​​b0 to b3 from among the 16 possible calculation results set in the table 603.

[0044] In the accumulator 606, the shifter 607 bit-shifts the calculation result acquired by the acquisition unit 605 according to the bit position of the bit values ​​b0 to b3 in the input data D0 to D3. For example, if the acquisition unit 605 acquires the calculation result "d0 + d2" corresponding to the bit value b0 to b3 of the first bit (least significant bit), the shifter 607 does not bit-shift the calculation result (see step S101 in Figure 17). Also, if the acquisition unit 605 acquires the calculation result "d2 + d3" corresponding to the bit value b0 to b3 of the second bit, the shifter 607 bit-shifts the calculation result one digit to the left (see step S102 in Figure 17). Furthermore, if the acquisition unit 605 acquires the calculation result "d0+d1" corresponding to the bit value b0~b3 of the third bit (the most significant bit in this example), the shifter 607 shifts the calculation result two digits to the left (see step S103 in Figure 17). The adder circuit 608 and latch circuit 609 then cumulatively add the calculation results after the bit shift by the shifter 607. In this example, the adder circuit 608 and latch circuit 609 cumulatively add the calculation results after the three bit shifts and output them as output data Y(n).

[0045] Thus, the FIR filter 60a can further reduce the circuit size by performing filtering using a table 603 instead of multiplying circuits 620-623 and adder circuits 631-633. However, the FIR filter 60a still suffers from a problem in that the overall circuit size remains large due to the large size of the table 603. Note that the size of the table 603 increases exponentially with increasing taps. Also, if a selector is used as the acquisition unit 605, the size of the selector will increase as the size of the table 603 increases.

[0046] Therefore, the inventors have discovered an FIR filter 1 that can further reduce the circuit size by performing filtering using a common table of calculation results that show the same value by giving symmetry to multiple filter coefficients, instead of using multiplication and addition circuits for filtering.

[0047] <Embodiment 1> Figure 1 shows an example configuration of the FIR filter 1 according to Embodiment 1. In the following explanation, unless otherwise specified, the case in which the number of taps k of the FIR filter 1 is 4 will be used as an example, but it is not limited to this, and k may be any integer greater than or equal to 2.

[0048] As shown in Figure 1, FIR filter 1, like FIR filter 60a, is an FIR-type digital filter employing distributed arithmetic. Instead of using multiplication and addition circuits for filtering, it uses table 103. Furthermore, in FIR filter 1, the filter coefficients d0 to d3 are symmetrical; that is, d0=d3 and d1=d2. Below, we will mainly describe the configuration and operation of FIR filter 1 that differ from FIR filter 60a.

[0049] As shown in Figure 1, the FIR filter 1 comprises an address signal generation unit 101, a storage unit 102, and an extraction unit 104.

[0050] The address signal generation unit 101 sequentially generates address signals that represent address values ​​corresponding to the m bit values ​​b0 to b3 at the same bit position, from the 1st bit to the mth bit (the 3rd bit in this example) of each input data D0 to D3, which is m bit wide and represented in binary.

[0051] More specifically, first, the address signal generation unit 101 generates an address signal indicating an address value corresponding to the first bit value b0 to b3 of each of the input data D0 to D3. Next, the address signal generation unit 101 generates an address signal indicating an address value corresponding to the second bit value b0 to b3 of each of the input data D0 to D3. Next, the address signal generation unit 101 generates an address signal indicating an address value corresponding to the third bit value b0 to b3 of each of the input data D0 to D3.

[0052] The memory unit 102 stores a table 103 containing multiple combinations of address values ​​indicated by address signals and their corresponding calculation results (corresponding to the output results of the adder circuit 633 in the FIR filter 60). Here, table 103 contains 10 calculation results, which are common to sets of calculation results that show the same value, out of the 16 (2 to the power of k) calculation results set in table 603. In other words, the size of table 103 is smaller than that of table 603. Details of the settings in table 103 will be described later.

[0053] The extraction unit 104 sequentially extracts a total of m (3 in this example) calculation results corresponding to the address values ​​indicated by the address signals generated by the address signal generation unit 101 from the table 103, and then performs a cumulative summation of each result after bit shifting them according to their bit positions in the input data D0 to D3. The extraction unit 104 then outputs the result of the cumulative summation as data Y(n).

[0054] Thus, the FIR filter 1 according to this embodiment can further reduce the circuit size compared to the FIR filter 60a by performing the filtering of symmetrical filter coefficients using a table 103 with optimized size, instead of using multiplication or addition circuits.

[0055] Figure 2 shows a more specific configuration example of the FIR filter 1. As shown in Figure 2, in the FIR filter 1, table 103 is composed of table 1031 and table 1032. Hereinafter, table 1031 will be referred to as the asymmetric table 1031, and table 1032 will be referred to as the symmetric table 1032. The extraction unit 104 includes acquisition units 1041 and 1042, a selector 1043, and an accumulator (ACC) 1044.

[0056] The address signal generation unit 101 generates address signals AD1 and AD2 corresponding to the bit values ​​b0 to b3. Hereinafter, the address signal representing the address value AD1 will also be referred to as address signal AD1. The address signal representing the address value AD2 will also be referred to as address signal AD2. The address signal generation unit 101 also outputs a selection signal S1 corresponding to the bit values ​​b0 to b3.

[0057] Figure 3 is a diagram illustrating how the settings for Table 103 are determined. Figure 3 also shows an example of the settings for Table 603. As already explained, in FIR filter 1, the filter coefficients d0 to d3 have symmetry; that is, d0=d3 and d1=d2.

[0058] Therefore, for example, the calculation result "d0" when bit values ​​b3, b2, b1, b0 = "0001" and the calculation result "d3" when bit values ​​b3, b2, b1, b0 = "1000" represent the same value and can be common. Also, the calculation result "d1" when bit values ​​b3, b2, b1, b0 = "0010" and the calculation result "d2" when bit values ​​b3, b2, b1, b0 = "0100" represent the same value and can be common. Furthermore, the calculation result "d1 + d0" when bit values ​​b3, b2, b1, b0 = "0011" and the calculation result "d3 + d2" when bit values ​​b3, b2, b1, b0 = "1100" represent the same value and can be common. Furthermore, the calculation result "d2+d0" when bit values ​​b3,b2,b1,b0 = "0101" and the calculation result "d3+d1" when bit values ​​b3,b2,b1,b0 = "1010" represent the same value and are therefore common. Furthermore, the calculation result "d2+d1+d0" when bit values ​​b3,b2,b1,b0 = "0111" and the calculation result "d3+d2+d1" when bit values ​​b3,b2,b1,b0 = "1110" represent the same value and are therefore common. Furthermore, the calculation result "d3+d1+d0" when bit values ​​b3,b2,b1,b0 = "1011" and the calculation result "d3+d2+d0" when bit values ​​b3,b2,b1,b0 = "1101" represent the same value and are therefore common.

[0059] Figure 4 shows an example of the settings for table 103. As already explained, table 103 is composed of an asymmetric table 1031 and a symmetric table 1032. In the asymmetric table 1031, six pairs of calculation results that show the same value out of the 16 calculation results set in table 603 shown in Figure 3 are common to six calculation results and are set after being combined with different address values ​​AD1. In the symmetric table 1032, the remaining four calculation results other than the six pairs that show the same value out of the 16 calculation results set in table 603 shown in Figure 3 are set after being combined with different address values ​​AD2.

[0060] Specifically, the asymmetrical table 1031 contains: The combination of address value AD1 = "000" and calculation result "d0", The combination of address value AD1 = "001" and calculation result "d1", The combination of address value AD1 = "010" and calculation result "d1 + d0", The combination of address value AD1 = "011" and calculation result "d2 + d0", The combination of address value AD1 = "100" and calculation result "d2 + d1 + d0", and The combination of address value AD1 = "101" and calculation result "d3 + d1 + d0", Each of these is set accordingly.

[0061] Furthermore, the symmetrical table 1032 contains: The combination of address value AD2 = "00" and calculation result "0 (none)", The combination of address value AD2 = "01" and calculation result "d2 + d1", The combination of address value AD2 = "10" and calculation result "d3 + d0", and Each of the following combinations is set: address value AD2 = "11" and calculation result "d3 + d2 + d1 + d0".

[0062] Figure 5 is a diagram showing the correspondence between the input value, address value, and calculation result in the FIR filter 1. As shown in Figure 5, the address signal generation unit 101 assigns a different address value AD1 to each of the 6 pairs of bit values ​​b0 to b3 that produce the same calculation result out of the 16 possible bit values ​​b0 to b3. In addition, the address signal generation unit 101 assigns a different address value AD2 to each of the remaining 4 pairs of bit values ​​b0 to b3 out of the 16 possible bit values ​​b0 to b3.

[0063] Specifically, in the address signal generation unit 101, For each of the bit values ​​b3, b2, b1, and b0, which are "0001" and "1000", a common address value AD1 = "000" is assigned. For each of the bit values ​​b3, b2, b1, and b0 = "0010" and "0100", a common address value AD1 = "001" is assigned. For each of the bit values ​​b3, b2, b1, and b0, which are "0011" and "1100", a common address value AD1 = "010" is assigned. For each of the bit values ​​b3, b2, b1, and b0, which are "0101" and "1010", a common address value AD1 = "011" is assigned. For each of the bit values ​​b3, b2, b1, and b0, which are "0111" and "1110", a common address value AD1 = "100" is assigned. For each of the bit values ​​b3, b2, b1, and b0 = "1011" and "1101", a common address value AD1 = "101" is assigned.

[0064] Furthermore, in the address signal generation unit 101, The bit values ​​b3, b2, b1, b0 = "0000" are assigned to the address value AD2 = "00". The bit values ​​b3, b2, b1, b0 = "0110" are assigned to the address value AD2 = "01". The bit values ​​b3, b2, b1, b0 = "1001" are assigned to the address value AD2 = "10". The bit values ​​b3, b2, b1, b0 = "1111" are assigned to the address value AD2 = "11".

[0065] Here, the correspondence between the 16 bit values ​​b0 to b3 linked via address values ​​AD1 and AD2 in Figure 5 and their calculation results is essentially the same as the correspondence between the 16 bit values ​​b0 to b3 and their calculation results in Table 603 shown in Figure 3.

[0066] The acquisition unit 1041 reads the calculation result of the address value AD1 indicated by the address signal AD1 from the table 1031 stored in the storage unit 102. Alternatively, the acquisition unit 1041 may be a selector that selects and outputs the calculation result corresponding to the address value AD1 indicated by the address signal AD1 from among the multiple calculation results set in the table 1031.

[0067] The acquisition unit 1042 reads the calculation result of the address value AD2 indicated by the address signal AD2 from the table 1032 stored in the storage unit 102. Alternatively, the acquisition unit 1042 may be a selector that selects and outputs the calculation result corresponding to the address value AD2 indicated by the address signal AD2 from among the multiple calculation results set in the table 1032.

[0068] The selector 1043 selects and outputs either the calculation result acquired by the acquisition unit 1041 or the calculation result acquired by the acquisition unit 1042, based on the selection signal S1. In other words, the selection signal S1 indicates whether the address signal generated by the address signal generation unit 101 represents the address value of the asymmetric table 1031 or the address value of the symmetric table 1032.

[0069] The accumulator 1044 has essentially the same configuration as the accumulator 606. The accumulator 1044 takes the calculation result selected by the selector 1043, shifts the bits according to the bit positions of the bit values ​​b0 to b3 in the input data D0 to D3, and then cumulatively adds them up. In this example, the accumulator 1044 cumulatively adds up the calculation results after three (m) bit shifts, corresponding to the bit width of each input data D0 to D3, and outputs them as output data Y(n).

[0070] Thus, the FIR filter 1 according to this embodiment can further reduce the circuit size compared to the FIR filter 60a by using a table 103 with optimized size to perform filtering of symmetrical filter coefficients, instead of using multiplication or addition circuits. Furthermore, when selectors are used as acquisition units 1041 and 1042, the size of tables 1031 and 1032 that constitute table 103 becomes smaller, and consequently, the size of acquisition units 1041 and 1042 also becomes smaller.

[0071] The number of elements in the symmetric table 1032 (the number of calculation results set in the symmetric table 1032) α can be expressed as shown in equation (1), where k is the number of taps.

[0072]

number

[0073] Furthermore, the number of elements in the asymmetric table 1031 (the number of calculation results set in the asymmetric table 1031) β can be expressed as shown in equation (2).

[0074]

number

[0075] For example, when the number of taps k is 4, from equations (1) and (2), the number of elements α in the symmetric table 1032 and the number of elements β in the asymmetric table 1031 are, respectively,

number

number

[0076] That is, when the number of taps k is 4, the number of elements in the table before the combinations of operation results showing the same value are shared (the table before sharing) is 16 (= 2^4), whereas the numbers of elements α and β of the two tables after the combinations of operation results showing the same value are shared (the two tables after sharing) are 4 and 6, respectively. That is, the total size of the two tables after sharing is smaller than the size of the table before sharing.

[0077] Also, when the number of taps k is 5, from Expressions (1) and (2), the number of elements α of the symmetric table 1032 and the number of elements β of the asymmetric table 1031 are respectively

Equation

Equation

[0078] That is, when the number of taps k is 5, the number of elements in the table before the combinations of operation results showing the same value are shared (the table before sharing) is 32 (= 2^5), whereas the numbers of elements α and β of the two tables after the combinations of operation results showing the same value are shared (the two tables after sharing) are 8 and 12, respectively. That is, the total size of the two tables after sharing is smaller than the size of the table before sharing.

[0079] <Description of the First Modified Example of the FIR Filter 1> Note that when the number of taps k is odd, a table in which a plurality of combinations of k - 1 input values (bit values) for which multiplication with k - 1 filter coefficients other than the central filter coefficient is performed and the corresponding operation results are set may be stored in the storage unit 102. In this case, the addition process of the operation result extracted from the table and the operation result using the central filter coefficient is performed separately.

[0080] For example, if the number of taps k is 5, a table 603a is first prepared containing 16 combinations of input values ​​(bit values) b0, b1, b3, b4 that are multiplied with the filter coefficients d0, d1, d3, d4 (excluding the central filter coefficient d2) out of the five filter coefficients d0 to d4, and the corresponding calculation results (see Figure 6). This table 603a is equivalent to the table 603 shown in Figure 3, where b3 and b2 are replaced with b4 and b3 respectively, and the calculation results d3 and d2 are replaced with d4 and d3 respectively. Subsequently, table 603a is optimized into table 103a, which consists of an asymmetric table 1031a and a symmetric table 1032a, through the same procedure as in the optimization from table 603 to table 103 (see Figure 7). Furthermore, asymmetric table 1031a and symmetric table 1032a are equivalent to asymmetric table 1031 and symmetric table 1032, respectively, where b3 and b2 are replaced with b4 and b3, and the calculation results d3 and d2 are replaced with d4 and d3, respectively.

[0081] Figure 8 shows the correspondence between input values, address values, and calculation results in FIR filter 1a, which is a first modification of FIR filter 1. As shown in Figure 8, in address signal generation unit 101a, which is a first modification of address signal generation unit 101, different address values ​​AD1 are assigned to each of the 6 pairs of bit values ​​b0, b1, b3, b4 that produce the same calculation result out of the 16 possible bit values ​​b0, b1, b3, b4. In addition, in address signal generation unit 101a, different address values ​​AD2 are assigned to each of the remaining 4 pairs of bit values ​​b0, b1, b3, b4 out of the 16 possible bit values ​​b0, b1, b3, b4.

[0082] Here, the correspondence between the 16 bit values ​​b0, b1, b3, b4 linked via address values ​​AD1, AD2 in Figure 8 and their calculation results is substantially the same as the correspondence between the 16 bit values ​​b0, b1, b3, b4 and their calculation results in Table 603a shown in Figure 6.

[0083] The multiplication result of the operation result extracted from the asymmetric table 1031a or the symmetric table 1032a, the central filter coefficient d2, and the bit value b2 are separately added in the subsequent addition circuit. Regarding other configurations of the FIR filter 1a, since they are the same as those of the FIR filter 1, the description thereof is omitted.

[0084] In the FIR filter 1a, since the number of elements α of the symmetric table 1032a is 4 and the number of elements β of the asymmetric table 1031a is 6, the table size is further reduced.

[0085] <Description of the second modification example of the FIR filter Ⅰ> Also, in the asymmetric table 1031 shown in FIG. 4, further commonization of sets of operation results showing the same value is possible.

[0086] FIG. 9 is a diagram showing an example of the setting content of the asymmetric table 1031b used in the FIR filter 1b which is the second modification example of the FIR filter 1. As shown in FIG. 9, in the asymmetric table 1031, since the operation result "d1 + d0" and the operation result "d2 + d0" show the same value because d3 = d0 and d2 = d1, they can be commonized. Therefore, in the asymmetric table 1031b, the operation result "d1 + d0" and the operation result "d2 + d0" are commonized as the operation result "d1 + d0".

[0087] Specifically, in the asymmetric table 1031b, The combination of the address value AD1 = "000" and the operation result "d0", The combination of the address value AD1 = "001" and the operation result "d1", The combination of the address value AD1 = "010" and the operation result "d1 + d0", The combination of the address value AD1 = "011" and the operation result "d2 + d1 + d0", and The combination of the address value AD1 = "100" and the operation result "d3 + d1 + d0", are respectively set.

[0088] Figure 10 is a diagram showing the correspondence between the input value, address value, and calculation result in the FIR filter 1b. As shown in Figure 10, in the address signal generation unit 101b, which is a second modified example of the address signal generation unit 101, different address values ​​AD1 are assigned to each of the four pairs of bit values ​​b0 to b3 that produce the same calculation result out of the 16 possible bit values ​​b0 to b3. In addition, in the address signal generation unit 101b, different address values ​​AD2 are assigned to each of the remaining four pairs of bit values ​​b0 to b3 out of the 16 possible bit values ​​b0 to b3.

[0089] Here, the correspondence between the 16 bit values ​​b0 to b3 linked via address values ​​AD1 and AD2 in Figure 10 and their calculation results is essentially the same as the correspondence between the 16 bit values ​​b0 to b3 and their calculation results in Table 603 shown in Figure 3.

[0090] The other configurations of FIR filter 1b are the same as those of FIR filter 1, so their explanation will be omitted. In FIR filter 1b, the number of elements α in the symmetric table 1032a is 4, and the number of elements β in the asymmetric table 1031b is 5, so the table size is further reduced.

[0091] <Embodiment 2> Figure 11 is a diagram illustrating the concept of the FIR filter 2 according to Embodiment 2. As the number of taps k increases, the number of elements in the table also increases exponentially. For example, when the number of taps k is 12, from equations (1) and (2), the number of elements α in the symmetric table 1032 becomes 64, and the number of elements β in the asymmetric table 1031 becomes 2016. Therefore, in this embodiment, table 103 is divided into multiple subtables, each containing multiple calculation results for multiple symmetric filter coefficients.

[0092] In the example shown in Figure 11, table 103, which contains multiple calculation results for 12 filter coefficients d0 to d11, is divided into three subtables 203_1 to 203_3. The calculation results extracted from each of the subtables 203_1 to 203_3 are added together by a subsequent adder circuit.

[0093] Specifically, subtable 203_1 contains multiple calculation results for four symmetrical filter coefficients d0, d1, d10, and d11. Subtable 203_2 contains multiple calculation results for four symmetrical filter coefficients d2, d3, d8, and d9. Subtable 203_3 contains multiple calculation results for four symmetrical filter coefficients d4, d5, d6, and 7. Here, each subtable 203_1 to 203_3 is composed of a symmetrical table with α=4 elements and an asymmetrical table with β=6 elements, similar to the example table shown in Figure 4.

[0094] In other words, before being divided into three subtables, the table consisted of one symmetric table with 64 elements α and one asymmetric table with 2016 elements β. In contrast, after being divided into three subtables, the table consists of three symmetric tables with 4 elements α and three asymmetric tables with 6 elements β, resulting in a reduction in table size.

[0095] Furthermore, this disclosure can be implemented by having a CPU (Central Processing Unit) execute a computer program to implement part or all of the FIR filter.

[0096] Specifically, the program described above includes a set of instructions (or software code) for causing the computer to perform one or more of the functions described in the embodiments when loaded into the computer. The program may be stored in a non-temporary computer-readable medium or a physical storage medium. Examples, but not limited to, include RAM (Random-Access Memory), ROM (Read-Only Memory), flash memory, SSD (Solid-State Drive), or other memory technologies, CD-ROM, DVD (Digital Versatile Disc), Blu-ray® disc, or other optical disc storage, magnetic cassette, magnetic tape, magnetic disk storage, or other magnetic storage devices. The program may be transmitted over a temporary computer-readable medium or a communication medium. Examples, but not limited to, include temporary computer-readable medium or a communication medium that includes electrically, optically, acoustically, or otherwise propagating signals.

[0097] Although the embodiments of this disclosure have been described in detail above with reference to the drawings, the specific configuration is not limited to those described above, and various design changes are possible without departing from the gist of this disclosure. [Explanation of symbols]

[0098] 1 FIR filter 1a FIR filter 1b FIR filter 2 FIR filters 50 FIR filters 50a FIR filter 60 FIR filters 60a FIR filter 101 Address signal generation unit 101a Address signal generation unit 101b Address signal generation unit 102 Storage section 103 Table 103a Table 104 Extraction part 203_1 Subtable 203_2 Subtable 203_3 Subtable 602 Storage section 603 Table 603a Table 604 Extraction part 605 Acquisition Department 606 Accumulator 607 Shifta 608 Adder Circuit 609 Latch Circuit 1031 Asymmetrical Table 1031a Asymmetrical Table 1031b Asymmetrical Table 1032 Symmetrical Table 1032a Symmetrical Table 1032b Symmetrical Table 1041 Acquisition Department 1042 Acquisition Department 1043 Selector 1044 Accumulator

Claims

1. An address signal generation unit generates an address signal corresponding to k bit values ​​that correspond to k filter coefficients (where k is an integer of 2 or more) that have symmetry, and A storage unit that stores a table in which multiple address values ​​and multiple calculation results are associated, An extraction unit extracts from the table the calculation result corresponding to the address value indicated by the address signal generated by the address signal generation unit, Equipped with, In the table, the k multiplication results obtained by multiplying k symmetrical filter coefficients and k corresponding bit values ​​are associated with the k multiplication results, which are the sum of 2 to the power of k possible operation results. The table then associates the k multiplication results with the k address values, where pairs of identical operation results are shared among the k multiplication results obtained by summing these results. FIR filter.

2. The aforementioned table is, An asymmetric table is set in which, among the multiple calculation results, there are multiple first calculation results which are common to multiple calculation results, and among the multiple address values, there are multiple first address values ​​associated with the multiple first calculation results, A symmetric table is set in which multiple second calculation results, which are multiple calculation results that are not standardized from the above multiple calculation results, and multiple second address values, which are multiple address values ​​associated with the above multiple second calculation results from the above multiple address values, It is composed of, The address signal generation unit further outputs selection signals corresponding to the k bit values, The extraction unit selects and outputs either the first calculation result extracted from the asymmetric table or the second calculation result extracted from the symmetric table based on the selection signal. The FIR filter according to claim 1.

3. If α is the number of second calculation results set in the symmetric table and β is the number of first calculation results set in the asymmetric table, then α and β are: [Number 7] [Number 8] It is expressed as follows: The FIR filter according to claim 2.

4. The aforementioned plurality of first calculation results are, among the calculation results of 2 to the power of k, a plurality of calculation results in which sets of calculation results showing the same value are common, and further, a plurality of calculation results in which sets of calculation results showing the same value are common. The FIR filter according to claim 2.

5. The k bit values ​​are the values ​​at the same bit position in each of the k m (where m is an integer greater than or equal to 1) bit-width input data, A shifter that performs m operations on the k bit values ​​at each bit position from the 1st bit to the mth bit of each of the k input data, according to the bit position, An adder that adds m operation results that have been bit-shifted by the shifter, It also has, The FIR filter according to claim 1.

6. The k symmetrical filter coefficients are composed of p (where p is an integer greater than or equal to 2) symmetrical filter coefficients and q (where p is an integer greater than or equal to 2, and k = p + q) symmetrical second filter coefficients. The aforementioned table is, A first subtable associates multiple operation results that share the same value from among the p multiplication results obtained by multiplying each of p symmetrical filter coefficients and p bit values ​​corresponding to the p filter coefficients, resulting in 2 to the power of p operation results, and multiple address values ​​corresponding to the multiple operation results. A second subtable associates multiple operation results that share the same value from among the q multiplication results obtained by multiplying each of q symmetrical filter coefficients and q bit values ​​corresponding to the q filter coefficients, with a number of address values ​​corresponding to these multiple operation results. It is composed of, The extraction unit adds the calculation result extracted from the first subtable and the calculation result extracted from the second subtable and outputs the result. The FIR filter according to claim 1.

7. An address signal is generated with address values ​​corresponding to k bit values ​​that correspond to k (where k is an integer greater than or equal to 2) filter coefficients having symmetry. The calculation result corresponding to the address value indicated by the generated address signal is extracted from a table stored in the memory device, which associates multiple address values ​​with multiple calculation results. A filtering method using an FIR filter, In the table, the k multiplication results obtained by multiplying k symmetrical filter coefficients and k corresponding bit values ​​are associated with the k multiplication results, which are the sum of 2 to the power of k possible operation results. The table then associates the k multiplication results with the k address values, where pairs of identical operation results are shared among the k multiplication results obtained by summing these results. A filtering method using an FIR filter.

8. A process to generate an address signal with an address value corresponding to k bit values ​​that correspond to k filter coefficients (where k is an integer greater than or equal to 2) that have symmetry, The process involves extracting the calculation result corresponding to the address value indicated by the generated address signal from a table stored in a memory device, which associates multiple address values ​​with multiple calculation results. A control program that causes a computer to execute, In the table, the k multiplication results obtained by multiplying k symmetrical filter coefficients and k corresponding bit values ​​are associated with the k multiplication results, which are the sum of 2 to the power of k possible operation results. The table then associates the k multiplication results with the k address values, where pairs of identical operation results are shared among the k multiplication results obtained by summing these results. Control program.

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