Switching control circuit, power factor correction circuit

Abstract

To provide a switching control circuit capable of suppressing increase in a peak value of an inductor current when a load current increases.SOLUTION: A switching control circuit that is provided with an inductor to which a rectified voltage according to an AC voltage is applied, and a transistor for controlling an inductor current that flows to the inductor, and controls switching of the transistor of a power factor correction circuit that generates an output voltage at a target level from the AC voltage comprises: a drive-signal output circuit that outputs a drive signal for allowing the power factor correction circuit to operate in a critical mode when a peak value of the inductor current in a half cycle of the AC voltage is less than a first predetermined value, and outputs the drive signal for allowing the power factor correction circuit to operate in a continuous mode when the peak value in the half cycle is larger than the first predetermined value; and a drive circuit for driving the transistor on the basis of the drive signal.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a switching control circuit and a power factor correction circuit.

Background Art

[0002] There is a power factor correction circuit as a power supply circuit that generates an output voltage at a target level from an AC voltage (see, for example, Patent Documents 1 to 6).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in a general power factor correction circuit operating in critical mode, when the load current flowing through the load increases, the peak value of the inductor current in the power factor correction circuit also increases. As a result, magnetic saturation may occur in the inductor of the power factor correction circuit.

[0005] The present invention has been made in view of the above conventional problems, and an object thereof is to provide a switching control circuit capable of suppressing an increase in the peak value of the inductor current when the load current increases.

Means for Solving the Problems

[0006] The first aspect of the present invention, which is the main aspect of solving the aforementioned problems, is a switching control circuit for controlling the switching of the transistor of a power factor correction circuit that generates an output voltage of a target level from the AC voltage, the switching control circuit comprising an inductor to which a rectified voltage corresponding to an AC voltage is applied, and a transistor for controlling the inductor current flowing through the inductor, the switching control circuit comprising a drive signal output circuit that outputs a drive signal to operate the power factor correction circuit in critical mode when the peak value of the inductor current in half a cycle of the AC voltage is smaller than a first predetermined value, and the drive signal output circuit that outputs the drive signal to operate the power factor correction circuit in continuous mode when the peak value in half a cycle is larger than the first predetermined value, and a drive circuit that drives the transistor based on the drive signal.

[0007] A second aspect of the present invention, which is the main aspect for solving the aforementioned problems, is a power factor correction circuit comprising: an inductor to which a rectified voltage corresponding to an AC voltage is applied; a transistor for controlling the inductor current flowing through the inductor; and a switching control circuit for controlling the switching of the transistor, wherein the switching control circuit comprises: a drive signal output circuit that outputs a drive signal to operate the power factor correction circuit in critical mode when the peak value of the inductor current in half a cycle of the AC voltage is smaller than a first predetermined value, and a drive circuit that outputs the drive signal to operate the power factor correction circuit in continuous mode when the peak value in half a cycle is larger than the first predetermined value; and a drive circuit that drives the transistor based on the drive signal. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a switching control circuit that can suppress the increase in the peak value of the inductor current when the load current increases. [Brief explanation of the drawing]

[0009] [Figure 1] This figure shows an example of a power factor correction circuit 10. [Figure 2]It is a diagram showing an example of the power factor improvement IC 25a. [Figure 3] It is a diagram showing a partial configuration of the power factor improvement circuit 10. [Figure 4] It is a diagram showing an example of the main waveforms of the power factor improvement circuit 10. [Figure 5] It is a diagram showing an example of the main waveforms of the power factor improvement IC 25a. [Figure 6] It is a diagram for explaining the inductor current IL. [Figure 7] It is a diagram for explaining the inductor current IL when the load current Iout increases. [Figure 8] It is a diagram showing an example of the power factor improvement IC 25b. [Figure 9] It is a diagram showing an example of the command value output circuit 56.

Embodiments for Carrying Out the Invention

[0010] From the descriptions in this specification and the attached drawings, at least the following matters become clear. Also, here, the same or equivalent components, members, etc. shown in each drawing are given the same reference numerals, and repeated explanations are omitted as appropriate.

[0011] In this embodiment, "connection" means a state of being electrically connected unless otherwise specified. For this reason, "connection" includes cases where two components are connected not only by wiring but also, for example, through a resistor.

[0012] =====This Embodiment===== <<<Configuration of the Power Factor Improvement Circuit 10>>> FIG. 1 is a diagram showing an example of the configuration of a power factor improvement circuit 10 according to an embodiment of the present invention. The power factor improvement circuit 10 is a boost chopper type power supply circuit (here, an AC - DC converter) that generates an output voltage Vout at a target level from the AC voltage Vac of a commercial power supply while improving the power factor.

[0013] Also, although details will be described later, the power factor improvement circuit 10 of the present embodiment operates in "critical mode" or "continuous mode". Here, the "critical mode" is an operating mode in which the power transistor is turned on when the inductor current IL described later becomes zero. The "continuous mode" is an operating mode in which the power transistor is turned on at a value where the inductor current IL is greater than zero, that is, an operating mode in which the inductor current IL flows continuously.

[0014] Note that the load 11 is a step-down power supply circuit that generates a predetermined voltage (for example, 15V) when the output voltage Vout (for example, 400V) is applied. In the present embodiment, the current flowing through the load 11 is defined as the load current Iout.

[0015] The power factor improvement circuit 10 includes a full-wave rectifier circuit 20, capacitors 21 and 27, an inductor 22, an NMOS transistor 23, resistors 24, 28, and 29, a power factor improvement IC 25, and a diode 26.

[0016] The full-wave rectifier circuit 20 full-wave rectifies the input predetermined AC voltage Vac and applies it as the rectified voltage Vrec to the capacitors 21 and the inductor 22. The AC voltage Vac is, for example, a voltage with an effective value of 140 to 240V and a frequency of 50 to 60Hz.

[0017] Hereinafter, in the present embodiment, the voltage is basically the potential difference with respect to the reference point (GND in FIG. 1), but the AC voltage Vac indicates the voltage between terminals. Also, the current input from the AC power supply to the power factor improvement circuit 10 is defined as the input current Iin.

[0018] The capacitor 21 is an element that removes the noise of the rectified voltage Vrec and smoothes the rectified voltage Vrec.

[0019] The inductor 22, together with the NMOS transistor 23, diode 26, and capacitor 27, constitutes a boost chopper circuit. Therefore, the charging voltage of the capacitor 27 becomes the DC output voltage Vout (for example, 400V). In this embodiment, the current flowing through the inductor 22 is defined as the inductor current IL. The voltage at the node where the inductor 22 and the NMOS transistor 23 are connected (i.e., the voltage at the drain electrode of the NMOS transistor 23) is defined as the voltage Vsw.

[0020] The NMOS transistor 23 is a switching element for controlling the power supplied to the load 11 by the power factor correction circuit 10. In this embodiment, the NMOS transistor 23 is an N-type MOS (Metal Oxide Semiconductor) transistor, but it could also be a bipolar transistor, for example. The gate electrode of the NMOS transistor 23 is connected to the OUT terminal of the power factor correction IC 25, which will be described later.

[0021] Resistor 24 is used to detect the inductor current IL flowing through inductor 22. One end is connected to the source electrode of NMOS transistor 23, and the other end is connected to terminal CS of power factor correction IC 25. In this embodiment, when NMOS transistor 23 is turned on, the inductor current IL flows through resistor 24 via NMOS transistor 23. When NMOS transistor 23 is turned off, the inductor current IL flows through resistor 24 via diode 26 and capacitor 27.

[0022] The power factor correction IC25 is an integrated circuit that controls the switching of the NMOS transistor 23 so that the output voltage Vout level reaches a target level (e.g., 400V) while improving the power factor. Specifically, the power factor correction IC25 drives the NMOS transistor 23 based on the inductor current IL and the feedback voltage Vfb (described later).

[0023] Details of the power factor correction IC 25 will be described later, but the power factor correction IC 25 is provided with terminals CS, FB, and OUT. In this embodiment, terminals other than terminal CS of the power factor correction IC 25 are omitted for convenience. The power factor correction IC corresponds to a "switching control circuit" that controls the switching of the NMOS transistor 23.

[0024] Resistors 28 and 29 form a voltage divider circuit that divides the output voltage Vout, generating the feedback voltage Vfb used when switching the NMOS transistor 23. The feedback voltage Vfb generated at the node to which resistors 28 and 29 are connected is applied to terminal FB.

[0025] <<<Configuration of Power Factor Correction IC25a>>> Figure 2 shows an example of a first embodiment of the power factor correction IC25. The power factor correction IC25a is composed of a command value output circuit 50, a command value correction circuit 51, an ON signal output circuit 52, a signal output circuit 53, a drive circuit 54, and a determination circuit 55. In this embodiment, the command value output circuit 50, the command value correction circuit 51, the ON signal output circuit 52, and the signal output circuit 53 correspond to the "drive signal output circuit".

[0026] As mentioned above, the voltage Vcs is the voltage obtained by converting the inductor current IL through the resistor 24. For example, when the ON signal output circuit 52 uses the voltage Vcs, it is sometimes said, for convenience, that the ON signal output circuit 52 uses the inductor current IL.

[0027] Furthermore, although omitted for convenience, terminal FB of this embodiment is provided with an AD converter that converts the voltage Vfb to a digital value, and terminal CS is provided with an AD converter that converts the voltage Vcs to a digital value. Therefore, each circuit of the power factor correction IC25 in this embodiment is a circuit that processes digital values ​​unless otherwise specified.

[0028] ==Command Value Output Circuit 50== The command value output circuit 50 outputs a command value V1 to set the output voltage Vout to the target level, based on the feedback voltage Vfb and the reference voltage Vref, which corresponds to the output voltage Vout at the target level.

[0029] In this embodiment, the command value V1 is a voltage at which the level increases when the feedback voltage Vfb is less than the reference voltage Vref, and decreases when the feedback voltage Vfb is greater than the reference voltage Vref. Hereafter, the "command value" described in this embodiment is a voltage at which the level changes, similar to the command value V1.

[0030] Furthermore, as will be described in detail later, in this embodiment, when the level of the command value V1 increases, the on-period of the NMOS transistor 23 becomes longer, and when the level of the command value V1 increases, the on-period of the NMOS transistor 23 becomes shorter. Hereinafter, the on-period of the NMOS transistor 23 corresponding to the command value V1 will be referred to as "on-period Ton1".

[0031] The command value output circuit 50 includes a subtractor 100 and a voltage regulator (AVR) 101. The subtractor 100 subtracts the feedback voltage Vfb from the reference voltage Vref and calculates the error E1 between the reference voltage Vref and the feedback voltage Vfb.

[0032] The voltage regulator 101 outputs a command value V1 to match the level of the feedback voltage Vfb to the level of the reference voltage Vref, according to the error E1. The subtractor 100 and the voltage regulator 101 correspond to so-called error amplification circuits, for example, which amplify and integrate the error E1.

[0033] The command value output circuit 50 corresponds to the "first command value output circuit," the command value V1 corresponds to the "first command value," and the ON period Ton1 corresponds to the "first period."

[0034] ==Overview of Command Value Correction Circuit 51== The command value correction circuit 51 corrects the command value V1 so that the on-period of the NMOS transistor 23 is shortened, for example, when the state of the load 11 becomes overloaded. Here, "overload" means that the load current Iout flowing through the load 11 is greater than the rated current. Specifically, for example, if the rated current is 8A, "overload" means that the load current Iout is greater than 8A.

[0035] Furthermore, "no load" for load 11 means that the load current Iout is zero, and "light load" means that the load current Iout is less than a predetermined value (e.g., 1A) that is sufficiently smaller than the rated current. Also, "rated load" for load 11 means that the load current Iout flows at a predetermined rated current (e.g., 8A).

[0036] Incidentally, when the load 11 becomes overloaded, the output voltage Vout decreases, so the command value output circuit 50 described above outputs a command value V1 that lengthens the period during which the NMOS transistor 23 is ON. Now, referring to Figures 3 and 4, the relationship between the ON period of the NMOS transistor 23 and the peak value of the inductor current IL will be explained.

[0037] <<Example of waveforms for the main nodes of the power factor correction circuit 10>> Figure 3 shows a partial configuration of the power factor correction circuit 10, and Figure 4 shows an example of the waveforms of the main nodes of the power factor correction circuit 10. Note that this shows an example of the waveform when the power factor correction circuit 10 is operating in so-called critical mode.

[0038] In this embodiment, as shown in Figure 3, a rectified voltage Vrec, obtained by full-wave rectifying an AC voltage Vac, is applied to the inductor 22. Therefore, if the inductance of the inductor 22 is L and the on-period of the NMOS transistor 23 is Ton, the peak value Ip of the inductor current IL is given by the following equation (1). Ip = (Vrec / L) × Ton ···(1) The rectified voltage Vrec changes according to sinθ, where θ is the phase angle of the AC voltage Vac.

[0039] Figure 4 shows an overview of the waveform of the AC voltage Vac over half a period (i.e., in the phase angle θ range of 0° to 180°), and the envelope of the peak value Ip is drawn as a dashed line. The peak value Ip is maximum when the phase angle θ is 90° during half a period of the AC voltage Vac.

[0040] Furthermore, during the off period Toff when the NMOS transistor 23 is turned off, the inductor current IL decreases from its peak value Ip to zero. Therefore, the following equation (2) holds true. Ip=((Vout-Vrec) / L)×Toff...(2)

[0041] Then, using equations (1) and (2), the following equation (3) holds. Toff / (Ton+Toff)=Vrec / Vout...(3)

[0042] Therefore, in the power factor correction circuit 10, as is clear from equation (3) and the bottom row of Figure 4, the rectified voltage Vrec can be determined from the duty cycle (Toff / (Ton+Toff)) of the off period Toff when the NMOS transistor 23 is turned off. Note that the duty cycle of the off period Toff is determined by the proportion of the off period Toff that is occupied by the switching period (Ton+Toff).

[0043] <<Regarding the peak value Tp and on-duration Ton when load 11 is overloaded>> Incidentally, for example, if the load 11 becomes overloaded and the on-time Ton lengthens, the peak value Ip increases, as is clear from Figure 4 and equation (1). As a result, magnetic saturation may occur in the inductor 22.

[0044] Therefore, if the peak value Ip exceeds a predetermined value I1, for example, when the load 11 is overloaded, it is necessary to shorten the on-period Ton to suppress the rise in the peak value Ip. The command value correction circuit 51 in Figure 2 processes the command value V1 to shorten the on-period of the NMOS transistor 23 when the load 11 is overloaded and the on-period Ton1 becomes longer than the predetermined period Tx. As will be explained in more detail later, the on-period of the NMOS transistor 23 obtained by the power factor correction IC 25a in Figure 2 will be described below as "Ton1" or "Ton2".

[0045] Here, the "predetermined period Tx" is the on-period when the peak value Ip becomes the predetermined value I1, as shown in equation (4). Note that Vrec in equation (4) is the value when the phase angle θ is 90°. Tx=I1×(L / Vrec(θ=90°))...(4)

[0046] In this embodiment, when the load 11 becomes overloaded, the ON period Ton1 indicated by the command value V1 becomes a predetermined period Tx. Therefore, the command value correction circuit 51 does not directly compare the peak value Ip with the predetermined value I1, but compares the ON period Ton1 with the predetermined period Tx corresponding to the predetermined value I1. The predetermined period Tx corresponds to the "first predetermined period," and the predetermined value I1 corresponds to the "first predetermined value."

[0047] ==Details of Command Value Correction Circuit 51== As shown in Figure 2, the command value correction circuit 51 is configured to include a limiter 110, subtractors 111 and 113, and an amplifier 112.

[0048] The limiter 110 limits the on-period Ton1 indicated by the command value V1 to the predetermined period Tx if it is longer than the predetermined period Tx. Specifically, the limiter 110 outputs a command value V3 for the on-period Ton1 indicated by the command value V1 if it is shorter than the predetermined period Tx. Also, if the on-period Ton1 indicated by the command value V1 is longer than the predetermined period Tx, the limiter 110 outputs a command value V3 for the on-period Tx.

[0049] In this embodiment, the limiter 110 operates in the same way as when the ON period Ton1 is shorter than the predetermined period Tx, even when the ON period Ton1 is equal to the predetermined period Tx. Therefore, the limiter 110 will essentially output the command value V3 for the ON period Ton1 if the ON period Ton1 indicated by the command value V1 is less than or equal to the predetermined period Tx.

[0050] Here, in the notation shown in Figure 2, for example, "V3(Ton1 / Tx)", the value to the left of the slash (in this case, the " / " mark) in the parentheses indicates the value when the limiter 110 is not operating, and the value to the right of the slash indicates the value when the limiter 110 is operating. The same applies to the notation within the slash in the parentheses in the drawings of this embodiment.

[0051] The subtractor 111 subtracts the command value V3 from the command value V1 and outputs a subtraction result Vs1 (=V1-V3) that shows the difference between the on period Ton1 and the predetermined period Tx. Note that if the on period Ton1 is shorter than the predetermined period Tx, the on period of the command value V3 becomes the on period Ton1. Therefore, in this case, the subtraction result Vs1 is 0 (zero).

[0052] If the on-period Ton1 is longer than the predetermined period Tx, the amplifier 112 amplifies the subtraction result Vs1 with a predetermined gain A1 and outputs it as a voltage Va. Here, the voltage Va is the value obtained by amplifying the difference between the on-period Ton1 and the predetermined period Tx with a predetermined gain A1. Therefore, the voltage Va, like the command value V1, is a value corresponding to the on-period of the NMOS transistor 23. In this embodiment, the on-period indicated by the voltage Va is the on-period Tona.

[0053] The subtractor 113 subtracts the voltage Va, which represents the on-period Tona, from the command value V3 and outputs the command value V2. Here, if the on-period Ton1 is shorter than the predetermined period Tx, the voltage Va is zero, so the subtractor 113 outputs a command value V2 in which the on-period Ton2 is equal to the on-period Ton1.

[0054] On the other hand, if the ON period Ton1 is longer than the predetermined period Tx, the subtractor 113 outputs a command value V2 such that the ON period Ton2 is (Tx - Tona). Therefore, in this case, the subtractor 113 outputs a command value V2 to turn on the NMOS transistor 23 for a period shorter than the predetermined period Tx.

[0055] The command value correction circuit 51 corresponds to the "second command value output circuit," the command value V2 corresponds to the "second command value," and the on period Ton2 corresponds to the "second period." The command value V3 output by the limiter 110 corresponds to the "third command value," the subtractor 111 corresponds to the "first subtractor," and the subtractor 113 corresponds to the "second subtractor."

[0056] ==ON signal output circuit 52== The ON signal output circuit 52 outputs a high-level (hereinafter referred to as H-level) signal Von to turn on the NMOS transistor 23 when the inductor current IL becomes current Ib (described later). The ON signal output circuit 52 is composed of a current output circuit 120, a waveform output circuit 121, a multiplier 122, and a comparator (CMP) 123.

[0057] The current output circuit 120 outputs a reference current Iref, which serves as the reference for the current Ib (described later), based on the voltage Va. Although it is stated here for convenience that the current output circuit 120 outputs the reference current Iref, the voltage output circuit 120 actually outputs a digital voltage representing the reference current Iref. Unless otherwise specified, in the power factor correction IC 25a, "current" means "voltage representing current."

[0058] Furthermore, in this embodiment, the current output circuit 120 performs a predetermined calculation to compensate for the power shortage when the on-period Ton1 is limited and power to the load 11 is insufficient. Specifically, the current output circuit 120 converts the voltage Va, i.e., the output Ton1 of the command value output circuit 50, into an effective value of the resulting input current Iin shortage, according to the amount corresponding to the on-period shortage of Ton2 output by the command value correction circuit 51. This can be determined by multiplying by the proportionality constant P, since the current peak value Ip is proportional to the on-period and the average value is also proportional to the on-period.

[0059] For example, if the effective value of the rectified voltage Vrec is Vrec_rms, then the proportionality constant P is mVrec_rms / 2L. The coefficient 2 in the denominator of the above equation is due to the fact that half of the peak value reached for a given on-period is the average value within the switching period. By using such a proportionality constant P, the on-period can be converted to a current value. When converting the current value back to the on-period, one can use, for example, the reciprocal of the proportionality constant P.

[0060] As a result, when the on-period Ton1 is shorter than the predetermined period Tx and the voltage Va is zero, the current output circuit 120 outputs a reference current Iref with a value of zero. Also, when the on-period Ton1 is longer than the predetermined period Tx and the voltage Va represents the on-period Tona, the current output circuit 120 outputs a reference current Iref with a value obtained by multiplying the voltage Va by a constant P (in this case, a positive value greater than zero).

[0061] The waveform output circuit 121 outputs a waveform Vr that is similar in shape to the rectified voltage Vrec, based on the signal Vqi output from the signal output circuit 53 (described later) which is at a high level during the period when the NMOS transistor 23 is off. As shown in the bottom row of Figure 4, the waveform output circuit 121 generates the waveform Vr by averaging the signal Vqi, which is similar to the voltage Vsw, for, for example, several switching cycles.

[0062] The multiplier 122 multiplies the reference current Iref by the waveform Vr and outputs a voltage representing the current Ib (instantaneous value). For convenience, the multiplier 122 will be described here assuming that it outputs the current Ib. In this embodiment, if the value of the reference current Iref is zero, the current Ib is also zero. On the other hand, when the reference current Iref is determined by the voltage Va and the constant P, the current Ib is given by Ib = Iref × Vr = Va × P × Vr, so the waveform of current Ib is similar to that of the rectified voltage Vrec. In this case, the current that is insufficient because the on-period Ton2 is shorter than the on-period Ton1 is compensated for by adding current Ib, so the input current Iin of the power factor correction circuit 10 is maintained at its original value (i.e., the value when the NMOS transistor 23 was turned on during the on-period Ton1).

[0063] Comparator 123 compares the inductor current IL and current Ib based on the voltage Vcs and the voltage indicating current Ib. Comparator 123 outputs a low-level signal Von if the inductor current IL is greater than current Ib. On the other hand, comparator 123 outputs a high-level signal Von if the inductor current IL is less than current Ib.

[0064] In this embodiment, the current output circuit 120, the waveform output circuit 121, and the multiplier 122 correspond to the "first output circuit," and the comparator 123 corresponds to the "second output circuit." Furthermore, the current output circuit 120 corresponds to the "reference current output circuit," and the multiplier 122 corresponds to the "arithmetic circuit." A current Ib where Ib=0 (a predetermined value) corresponds to the "first current," and a current Ib where Ib=Iref×Vr (=Va×P×Vr) corresponds to the "second current."

[0065] ==Signal output circuit 53== The signal output circuit 53 outputs a drive signal Vdr for driving the NMOS transistor 23 based on the signal Von and the command value V2. The signal output circuit 53 is comprised of an SR flip-flop 130, an oscillator (OSC) 131, and a comparator 132.

[0066] The SR flip-flop 130 changes the drive signal Vdr, which is the Q output, to a high level based on the high-level signal Von, and changes the drive signal Vdr to a low level based on the high-level signal Voff (described later). The SR flip-flop 130 also outputs a signal Vqi, which is the inverted logic level of the Q output.

[0067] When the drive signal Vdr reaches a high level, oscillator 131 outputs a ramp wave Vrmp whose amplitude rises from zero. When the drive signal Vdr reaches a low level, oscillator 131 changes the amplitude of the ramp wave Vrmp to zero.

[0068] The comparator 132 compares the command value V2 with the ramp wave Vrmp and outputs a high-level signal Voff to turn off the NMOS transistor 23. Specifically, if the ramp wave Vrmp is less than the command value V2, the comparator 132 outputs a low-level signal Voff. On the other hand, if the ramp wave Vrmp is greater than the command value V2, the comparator 132 outputs a high-level signal Voff to turn off the NMOS transistor 23.

[0069] As a result, the comparator 132 can turn off the NMOS transistor 23 after the on-period Ton2 indicated by the command value V2 has elapsed, following the on-period V2.

[0070] ==Drive Circuit 54== The drive circuit 54 is a buffer circuit that drives the NMOS transistor 23 based on the drive signal Vdr. When the drive signal Vdr becomes high, the drive circuit 54 sets the signal Vo to high to turn on the NMOS transistor 23, and when the drive signal Vdr becomes low, it sets the signal Vo to low to turn off the NMOS transistor 23.

[0071] ==Judgment circuit 55== The determination circuit 55 determines, based on the voltage Va, whether the period during which the load 11 is in an overload state, that is, the period during which the on-period Ton1 is longer than the predetermined period Tx, is longer than the predetermined period Ty (for example, 5ms). As mentioned above, the voltage Va becomes positive when the on-period Ton1 is longer than the predetermined period Tx.

[0072] Furthermore, the determination circuit 55 controls the drive circuit 54 so that the NMOS transistor 23 turns off if the period during which the voltage Va is positive is longer than a predetermined period Ty. As a result, in this embodiment, if the period during which the load 11 is in an overload state becomes long, the switching of the NMOS transistor 23 is stopped, and the supply of power to the load 11 is also stopped. This prevents, for example, the power factor correction circuit 10 from being destroyed by heat in this embodiment. The predetermined period Ty corresponds to the "second predetermined period".

[0073] <<<Operation of power factor correction IC25a>>> The operation of the power factor correction IC25a will be explained with reference to Figures 1, 2, and 5-7. Figure 5 is a diagram illustrating the waveforms of the main signals of the power factor correction IC25a. Figure 6 is a diagram illustrating the inductor current IL when the power factor correction circuit 10 is operating in critical mode, and Figure 7 is a diagram illustrating the inductor current IL when the power factor correction circuit 10 is operating in continuous mode.

[0074] Here, we will sequentially explain the operation of the power factor correction IC25a as the state of load 11 changes from light load to rated load and then to overload.

[0075] ==When Load 11 is under light load conditions== The command value output circuit 50 in Figure 2 outputs a command value V1 based on the feedback voltage Vfb and the reference voltage Vref so that the output voltage Vout reaches the target level. Here, when the state of the load 11 is light load, the on period Ton1 indicated by the command value V1 is shorter than the predetermined period Tx when the state of the load 11 becomes overload. Therefore, the command value correction circuit 51 outputs a command value V2 indicating the on period Ton1.

[0076] Furthermore, since the command value V3 output from the limiter 110 is equal to the command value V1, the voltage Va output from the amplifier 112 is zero. Therefore, the multiplier 122 outputs a current Ib, which is zero, to the comparator 123.

[0077] Here, after the NMOS transistor 23 is turned off, for example, at time t10 in Figure 5, when the inductor current IL decreases and the current Ib becomes (=0), the comparator 123 outputs a high-level signal Von.

[0078] As a result, the SR flip-flop 130 outputs a high-level drive signal Vdr, causing the NMOS transistor 23 to turn on. Furthermore, when a high-level drive signal Vdr is output, the amplitude of the ramp wave Vrmp from the oscillator 131 increases.

[0079] Then, at time t11, when the amplitude level of the ramp wave Vrmp reaches the level of the command value V2, the comparator 132 changes the signal Voff to a high level. As a result, the SR flip-flop 130 is reset and outputs a low-level drive signal Vdr, so the NMOS transistor 23 turns off. Furthermore, the period from time t10 to t11 will be the ON period Ton2, as indicated by the command value V2.

[0080] Then, when the NMOS transistor 23 is turned off, the inductor current IL decreases, and the operation from time t10 to t12 is repeated from time t12 onwards. As a result, when the load 11 is a light load, the power factor correction circuit 10 operates in critical mode, and the peak value Ip of the inductor current IL becomes the waveform shown by the dashed line in Figure 6(a), for example. Here, the peak value Ip is a current value I0 that is smaller than the predetermined value I1, which is the peak value Ip at the rated load as described above. The dotted line in Figure 6(a) is the average value Iave of the inductor current IL.

[0081] ==When Load 11 is under rated load== When the state of load 11 increases from light load to rated load, the ON period Ton1 indicated by the command value V1 becomes the predetermined period Tx when the state of load 11 becomes overload. At this time, as described above, the limiter 110 outputs the command value V1 indicating the ON period Ton1.

[0082] Therefore, in this case as well, the power factor correction circuit 10 operates in critical mode, as shown in Figure 6(b), similar to the case where the load 11 is a light load. In Figure 6(b), the peak value Ip of the inductor current IL is shown by a dashed line, and the average value Iave of the inductor current IL is shown by a dotted line. Also, in Figure 6(b), the peak value Ip increases from the current value I0 to a predetermined value I1.

[0083] ==When Load 11 is under overload conditions== Even when the load 11 is overloaded, the main signals of the power factor correction IC25a change in the same way as when the load 11 is light load, as shown in Figure 5. However, since the ON period Ton1 indicated by the command value V1 is longer than the predetermined period Tx, the voltage Va becomes a positive value. Here, overload is explained using, for example, a state in which a current 1.5 times the rated current (e.g., 12A) flows.

[0084] As a result, the command value correction circuit 51 outputs a command value V2 with an on-period Ton2 that is shorter than the on-period Ton1, and the on-signal output circuit 52 outputs an on-signal Von at a high level when the inductor current IL becomes current Ib (=Iref × Vr).

[0085] Therefore, when the load 11 is overloaded, as shown in Figure 6(c), the peak value Ip (dotted-dotted line) of the inductor current IL and the bottom value current Ib (double-dotted line) of the inductor current IL both have waveforms Vr similar to the rectified voltage Vrec. In this way, when the load 11 is overloaded, the power factor correction circuit 10 operates in continuous mode.

[0086] Furthermore, in this embodiment, when the power factor correction circuit 10 is operated in continuous mode during an overload, the bottom value of the inductor current IL increases from zero. Therefore, the peak value Ip (dotted line) current value I2 in this case is smaller than the peak value Ip (dotted line) current value I3 when the power factor correction circuit 10 is operated in critical mode. This is because, in critical mode, in order to increase the average value Iave by the desired amount, it is necessary to increase the peak value Ip by twice that amount, whereas in continuous mode, the added current Ib directly becomes the increase in the average value Iave. Therefore, by using this embodiment, the increase in the peak value Ip of the inductor current IL can be suppressed.

[0087] <<Simulation Results>> Figure 7 shows the simulation results when the load current Iout is increased in the power factor correction circuit 10 using the power factor correction IC25a. In Figure 7, the inductor current IL, input current Iin, and input power of the AC power supply are sequentially shown from top to bottom.

[0088] In Figure 7, at time 0ms, the load current Iout of load 11 is set to 0A, and as the load current Iout is gradually increased, the input power also increases. Then, at approximately 90ms, the load current Iout becomes the rated current (i.e., load 11 is at its rated load), and thereafter, the load current Iout is increased beyond the rated current. Note that in Figure 7, the rated load is indicated as the rated power.

[0089] As shown in Figure 7, the power factor correction circuit 10 operates in critical mode from time 0ms until time 90ms when the load current Iout becomes the rated current. Therefore, the peak value Ip of the inductor current IL increases in proportion to the increase in the load current Iout (or input power).

[0090] Then, at approximately 90ms, the load current Iout becomes the rated current, and the power factor correction circuit 10 operates in continuous mode. Therefore, even if the load current Iout increases, the bottom value of the inductor current IL increases, and as a result, the increase in the peak value Ip is suppressed. Thus, in this embodiment, even if the load 11 becomes overloaded, the peak value Ip of the inductor current IL can be kept small.

[0091] <<<Configuration of Power Factor Correction IC25b>>> Figure 8 shows an example of a second embodiment of the power factor correction IC25. Similar to the power factor correction IC25a, the power factor correction IC25b is a circuit that operates the power factor correction circuit 10 from critical mode to continuous mode when the load 11 becomes overloaded.

[0092] The power factor correction IC25a is a circuit that shortens the on-period of the NMOS transistor 32 and increases the current Ib when the on-period Ton1 of the command value V1 becomes longer than a predetermined period Tx. On the other hand, the power factor correction IC25b is a circuit that increases the current Ib and shortens the on-period of the NMOS transistor 32 when the peak value Ip of the inductor current IL becomes larger than a predetermined value I1.

[0093] The power factor correction IC25b is composed of a command value output circuit 50, a signal output circuit 53, a drive circuit 54, an ON signal output circuit 60, a command value correction circuit 61, and a determination circuit 62. In this embodiment, the command value output circuit 50, the signal output circuit 53, the ON signal output circuit 60, and the command value correction circuit 61 correspond to the "drive signal output circuit".

[0094] Circuits with the same reference numerals in the power factor correction IC25b in Figure 8 and the power factor correction IC25a in Figure 2 are the same. Therefore, the ON signal output circuit 60, the command value correction circuit 61, and the determination circuit 62 will be described here.

[0095] ==ON signal output circuit 60== The ON signal output circuit 60 includes a sample-and-hold circuit (S / H) 200, an averaging circuit 201, a subtractor 202, a current output circuit 203, a waveform output circuit 204, a multiplier 205, and a comparator (CMP) 206.

[0096] The sample-and-hold circuit 200 is a circuit that samples the inductor current IL at the timing when the NMOS transistor 23 is turned off. Specifically, when the signal Vqi becomes high level, the sample-and-hold circuit 200 acquires and holds the inductor current IL. As a result, the sample-and-hold circuit 200 acquires the peak value Ip of the inductor current IL each time the NMOS transistor 23 is switched. The sample-and-hold circuit 200 corresponds to a "holding circuit".

[0097] The averaging circuit 201 calculates the average value Ipav of the peak value Ip over a half-cycle period of the AC voltage Vac.

[0098] The subtractor 202 is a circuit that subtracts a predetermined value Ipr from the average value Ipav. Here, the "predetermined value Ipr" is the average value Ipv when the load 11 is overloaded and the peak value Ip in a half-cycle becomes the predetermined value I1. Therefore, when the average value Ipav becomes greater than the predetermined value Ipr, and the subtraction result of the subtractor 202 is a positive value, it means that the load 11 is overloaded. The predetermined value Ipr corresponds to the "second predetermined value".

[0099] The current output circuit 203 outputs a reference current Iref of a different value based on the subtraction result of the subtractor 202. Specifically, if the state of the load 11 is less than the rated load and the subtraction result of the subtractor 202 is a value of zero or less (including negative values), the current output circuit 203 outputs a reference current Iref of zero in order to operate the power factor correction circuit 10 in critical mode.

[0100] On the other hand, the current output circuit 203 outputs a reference current Iref, which increases in value according to the subtraction result, in order to operate the power factor correction circuit 10 in continuous mode when the load 11 is overloaded and the subtraction result of the subtractor 202 is positive.

[0101] The waveform output circuit 204, multiplier 205, and comparator 206 are the same as the waveform output circuit 121, multiplier 122, and comparator 123 in Figure 2. Therefore, when the inductor current IL becomes current Ib, comparator 206 outputs a high-level signal Von to turn on the NMOS transistor 23.

[0102] In this embodiment, the current output circuit 203, the waveform output circuit 204, and the multiplier 205 correspond to the "first output circuit," and the comparator 206 corresponds to the "second output circuit." Furthermore, the current output circuit 203 corresponds to the "reference current output circuit," and the multiplier 205 corresponds to the "arithmetic circuit." The current Ib where Ib=0 (a predetermined value) corresponds to the "first current," and the current Ib where Ib=Iref×Vr corresponds to the "second current." Here, the reference current Iref is a current that increases according to the difference between the average value Ipav and the predetermined value Ipr.

[0103] ==Command Value Correction Circuit 61== The command value correction circuit 61 corrects the command value V1 so that the ON period of the NMOS transistor 23 is shortened, for example, when the state of the load 11 becomes overloaded. The command value correction circuit 61 is composed of a correction circuit 210 and a subtractor 211. The command value correction circuit 61 corresponds to the "second command value output circuit".

[0104] The correction circuit 210 outputs a correction value Vc to correct the command value V1 by multiplying the reference current Iref output from the current output circuit 203 by a predetermined value. Therefore, the correction circuit 210 outputs a correction value Vc that is zero when the amplitude of the reference current Iref is zero. On the other hand, the correction circuit 210 outputs a correction value Vc that has a positive value when the amplitude of the reference current Iref is a positive value.

[0105] The subtractor 211 subtracts the correction value Vc from the command value V1 and outputs the subtraction result as the command value V2. Therefore, if the amplitude of the reference current Iref is zero and the correction value Vc is also zero, the subtractor 211 will output the command value V1 as the command value V2. As a result, in this case, the on-period of the NMOS transistor 23 indicated by the command value V2 becomes the on-period Ton1 of the command value V1.

[0106] On the other hand, if the correction circuit 210 outputs a positive correction value Vc, the subtractor 211 will output the command value V2 as the value obtained by subtracting the correction value Vc from the command value V1. As a result, in this case, the on-period of the NMOS transistor 23 indicated by the command value V2 will be shorter than the on-period Ton1.

[0107] Therefore, when using the power factor correction IC25b of this embodiment, if the load 11 becomes overloaded, the bottom value of the inductor current IL is increased while the on-period of the NMOS transistor 23 is shortened. As a result, the peak current (peak value Ip) due to switching ripple can be reduced while maintaining the required input current Iin, thus suppressing the overall peak current.

[0108] ==Judgment circuit 62== The determination circuit 62 determines whether the period during which the load 11 is in an overload state is longer than a predetermined period Ty (for example, 5ms), based on the difference between the average value Ipav and a predetermined value Ipr. As described above, when the load 11 is in an overload state, the difference between the average value Ipav and the predetermined value Ipr becomes a positive value. Therefore, the determination circuit 62 determines whether the period during which the difference between the average value Ipav and the predetermined value Ipr is a positive value is longer than the predetermined period Ty.

[0109] Furthermore, the determination circuit 62 controls the drive circuit 54 so that the NMOS transistor 23 is turned off if the period during which the difference between the average value Ipav and a predetermined value Ipr is positive is longer than a predetermined period Ty. As a result, in this embodiment, if the period during which the load 11 is in an overload state becomes long, the switching of the NMOS transistor 23 is stopped, and the power supply to the load 11 is also stopped. This prevents, for example, the power factor correction circuit 10 from being destroyed by heat.

[0110] ==Summary of Power Factor Correction IC25b== Thus, when the load 11 becomes overloaded, the power factor correction IC 25b causes the power factor correction circuit 10 to operate in continuous mode. Compared to the case where the power factor correction circuit 10 is continuously operating in critical mode, the peak value Ip of the inductor current IL can be reduced.

[0111] ==Other (Variations of command value correction circuit 51)== The command value correction circuit 51 in Figure 2 is configured to include a limiter 110, subtractors 111 and 113, and an amplifier 112, but is not limited to this configuration. For example, the command value correction circuit 56 shown in Figure 9 may be used instead of the command value correction circuit 51.

[0112] The command value correction circuit 56 does not use the amplifier 112 of the command value correction circuit 51, but instead outputs the subtraction result of the subtractor 111 directly to the subtractor 113. Even with this configuration, the peak value Ip of the inductor current IL can be reduced, similar to the embodiment. The command value correction circuit 56 corresponds to the "second command value output circuit".

[0113] ===Summary=== The power factor correction circuit 10 of this embodiment has been described above. For example, the power factor correction ICs 25a and 25b operate the power factor correction circuit 10 in critical mode until the load 11 becomes overloaded, and then operate the power factor correction circuit 10 in continuous mode once the load 11 becomes overloaded. As a result, in this embodiment, even when the load current Iout increases, the rise in the peak value Ip of the inductor current IL can be suppressed.

[0114] Furthermore, the power factor correction IC25a in Figure 2 operates the power factor correction circuit 10 in critical mode when the ON period Ton1 of the command value V1 becomes longer than a predetermined period Tx.

[0115] Furthermore, even when using the command value correction circuit 56 shown in Figure 9, for example, when the load 11 is in an overload state, the rise in the peak value Ip of the inductor current IL can be suppressed. However, the command value correction circuit 51 includes an amplifier 112 in addition to the limiter 110. Therefore, when the on-period Ton1 of the command value V1 becomes longer than a predetermined period Tx, the on-period of the NMOS transistor 23 can be shortened compared to when there is no amplifier 112. Consequently, the peak value Ip can be made smaller when the load current Iout increases.

[0116] Furthermore, until the load 11 reaches its rated load, the comparator 123 outputs a high-level signal Von to turn on the NMOS transistor 23 when the inductor current IL becomes zero. Then, when the load 11 becomes overloaded, the comparator 123 outputs a high-level signal Von to turn on the NMOS transistor 23 when the inductor current IL becomes a positive value Ib. As a result, the power factor correction IC 25a can operate the power factor correction circuit 10 in critical mode or continuous mode.

[0117] Furthermore, when the load 11 is overloaded, the multiplier 122 changes the current Ib according to the waveform Vr. Therefore, the bottom value of the inductor current IL can be changed sinusoidally.

[0118] Furthermore, the waveform output circuit 121 generates the waveform Vr based on the duty cycle at which the NMOS transistor 23 is turned off. Therefore, for example, the current Ib can be changed sinusoidally without using a voltage divider circuit to divide the rectified voltage Vrec.

[0119] Furthermore, the determination circuit 55 turns off the NMOS transistor 23 in the drive circuit 54 if the period during which the load 11 is in an overload state becomes longer than a predetermined period Ty. As a result, in this embodiment, it is possible to prevent the power factor correction circuit 10 from being destroyed by heat.

[0120] Furthermore, the power factor correction IC25b in Figure 8 operates the power factor correction circuit 10 in critical mode when the peak value Ip becomes higher than a predetermined value I1. Even when using such a power factor correction IC25b, the increase in the peak value Ip of the inductor current IL can be suppressed when the load current Iout increases.

[0121] Furthermore, similar to comparator 123, comparator 206 outputs a high-level signal Von to turn on the NMOS transistor 23 when the inductor current IL becomes current Ib. As a result, power factor correction IC 25a can operate the power factor correction circuit 10 in critical mode or continuous mode.

[0122] Furthermore, the waveform output circuit 204, like the waveform output circuit 121, generates the waveform Vr based on the duty cycle at which the NMOS transistor 23 is turned off. Therefore, for example, the current Ib can be changed sinusoidally without using a voltage divider circuit to divide the rectified voltage Vrec.

[0123] Furthermore, the command value correction circuit 61 includes a subtractor 211 that subtracts a correction value Vc from the command value V1 when the load 11 is in an overload state. As a result, the power factor correction IC 25b can shorten the on-period of the NMOS transistor 23 in response to an increase in the load current Iout.

[0124] Furthermore, the determination circuit 62 turns off the NMOS transistor 23 in the drive circuit 54 when the peak value Ip becomes larger than a predetermined value I1, and the period during which the difference between the average value Ipav and the predetermined value Ipr is positive becomes longer than a predetermined period Ty. This prevents the power factor correction circuit 10 from being destroyed by heat.

[0125] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit its interpretation. Furthermore, the present invention may be modified or improved without departing from its spirit, and it goes without saying that the present invention includes equivalents thereof. [Explanation of symbols]

[0126] 10 Power Factor Correction Circuit 11 Load 20 Full wave rectifier circuit 21,27 Capacitors 22 Inductors 23 NMOS transistors 24, 28, 29 resistors 25 Power Factor Correction IC 26 diodes 50 Command value output circuit 51, 56, 61 Command value correction circuit 52,60 ON signal output circuit 53 Signal Output Circuit 54 Drive Circuit 55,62 Judgment circuit 100,111,113,202 Subtractor 101 Voltage Regulator 110 Limiter 112 Amplifier 120,203 Current output circuit 121,204 Waveform output circuit 122,205 multiplier 123,132,206 comparators 130 SR Flip-Flop 131 Oscillator 200 Sample-and-Hold Circuit 201 Averaging circuit

Claims

1. A switching control circuit for controlling the switching of the transistor in a power factor correction circuit that generates an output voltage of a target level from the AC voltage, comprising an inductor to which a rectified voltage corresponding to an AC voltage is applied, and a transistor that controls the inductor current flowing through the inductor, wherein the power factor correction circuit generates an output voltage of a target level from the AC voltage, A drive signal output circuit that outputs a drive signal to operate the power factor correction circuit in critical mode when the peak value of the inductor current in half a cycle of the AC voltage is less than a first predetermined value, and outputs the drive signal to operate the power factor correction circuit in continuous mode when the peak value in half a cycle is greater than the first predetermined value, A drive circuit that drives the transistor based on the aforementioned drive signal, Equipped with, The aforementioned drive signal output circuit is A first command value output circuit outputs a first command value for turning on the transistor for a first period based on a feedback voltage corresponding to the output voltage and a reference voltage, A second command value output circuit outputs a second command value to turn on the transistor for the first period if the first period is shorter than a first predetermined period, and outputs a second command value to turn on the transistor for a second period that is less than or equal to the first predetermined period if the first period is longer than a first predetermined period. If the first period is shorter than the first predetermined period, an ON signal output circuit outputs an ON signal to turn on the transistor when the inductor current becomes a first current corresponding to the critical mode, and if the first period is longer than the first predetermined period, an ON signal output circuit outputs the ON signal when the inductor current becomes a second current corresponding to the continuous mode. A signal output circuit that outputs the drive signal based on the second command value and the ON signal, Includes, The first predetermined period is the period during which the transistor is turned on when the peak value in the half-cycle reaches the first predetermined value. Switching control circuit.

2. A switching control circuit according to claim 1, The second command value output circuit is, A limiter that outputs a third command value to turn on the transistor for the first period if the first period is shorter than the first predetermined period, and outputs the third command value to turn on the transistor for the first predetermined period if the first period is longer than the first predetermined period, A first subtractor that outputs a subtraction result obtained by subtracting the third command value from the first command value, An amplifier that amplifies the subtraction result with a predetermined gain, A second subtractor subtracts the output of the amplifier from the third command value and outputs it as the second command value, A switching control circuit including a switch.

3. A switching control circuit according to claim 1 or claim 2, The aforementioned ON signal output circuit is A first output circuit that outputs a first current when the first period is shorter than the first predetermined period, and outputs a second current corresponding to the difference between the first period and the first predetermined period when the first period is longer than the first predetermined period, The second output circuit outputs the ON signal when the inductor current becomes the current output from the first output circuit, A switching control circuit including a switch.

4. A switching control circuit according to claim 3, The first output circuit is, A reference current output circuit that outputs a reference current of a predetermined value when the first period is shorter than the first predetermined period, and outputs the reference current of a value corresponding to the difference when the first period is longer than the first predetermined period, A calculation circuit outputs a first current based on a predetermined value of the reference current when the first period is shorter than the first predetermined period, and outputs a second current having an amplitude corresponding to the difference and similar to the waveform of the rectified voltage, based on the reference current with a value corresponding to the difference and the waveform of the rectified voltage. A switching control circuit including a switch.

5. A switching control circuit according to claim 4, The first output circuit is, The circuit includes a waveform output circuit that outputs the waveform of the rectified voltage based on the off period of the switching cycle of the transistor. Switching control circuit.

6. A switching control circuit according to claim 1, A determination circuit that determines whether a second predetermined period has elapsed during which the first period is longer than the first predetermined period, Includes, The aforementioned drive circuit is When the period during which the first period is longer than the first predetermined period has elapsed for the second predetermined period, the transistor is turned off. Switching control circuit.

7. A switching control circuit according to claim 1, The aforementioned drive signal output circuit is A first command value output circuit outputs a first command value for turning on the transistor for a first period based on a feedback voltage corresponding to the output voltage and a reference voltage, A second command value output circuit outputs a second command value to turn on the transistor for a first period if the peak value is smaller than the first predetermined value, and outputs the second command value to turn on the transistor for a second period shorter than the first period if the peak value is larger than the first predetermined value. An on-signal output circuit outputs an on signal to turn on the transistor when the peak value is smaller than the first predetermined value and the inductor current becomes a first current corresponding to the critical mode, and when the peak value is larger than the first predetermined value and the inductor current becomes a second current corresponding to the continuous mode, A signal output circuit that outputs the drive signal based on the second command value and the ON signal, A switching control circuit including a switch.

8. A switching control circuit according to claim 7, The aforementioned ON signal output circuit is Each time the transistor turns off, a holding circuit is used to hold the inductor current, An averaging circuit that calculates the average value of the inductor current held by the holding circuit over the half-period, A first output circuit that outputs the first current when the average value becomes smaller than a second predetermined value corresponding to the first predetermined value, and outputs the second current corresponding to the difference between the average value and the second predetermined value when the average value becomes larger than the second predetermined value, The second output circuit outputs the ON signal when the inductor current becomes the current output from the first output circuit, A switching control circuit including a switch.

9. A switching control circuit according to claim 8, The first output circuit is, A reference current output circuit that outputs a reference current of a predetermined value when the average value is less than the second predetermined value, and outputs a reference current of a value corresponding to the difference when the average value is greater than the second predetermined value, A calculation circuit that outputs the first current based on the predetermined value of the reference current, and outputs the second current having an amplitude corresponding to the difference and similar to the waveform of the reference current and the rectified voltage, based on the waveform of the reference current and the rectified voltage corresponding to the difference, A switching control circuit including a switch.

10. A switching control circuit according to claim 9, The first output circuit is, The circuit includes a waveform output circuit that outputs the waveform of the rectified voltage based on the off period of the switching cycle of the transistor. Switching control circuit.

11. A switching control circuit according to any one of claims 7 to 10, The second command value output circuit is, A correction circuit that outputs a correction value to shorten the period during which the transistor is ON, when the peak value is greater than the first predetermined value, When the correction value is output, a subtractor subtracts the correction value from the first command value and outputs it as the second command value, A switching control circuit including a switch.

12. A switching control circuit according to claim 7, A determination circuit that determines whether a predetermined period has elapsed during which the peak value is greater than the first predetermined value, Includes, The aforementioned drive circuit is If the period during which the peak value exceeds the first predetermined value has elapsed, the transistor is turned off. Switching control circuit.

13. An inductor to which a rectified voltage corresponding to an AC voltage is applied, A transistor that controls the inductor current flowing through the aforementioned inductor, A switching control circuit for controlling the switching of the transistor, A power factor correction circuit comprising, The aforementioned switching control circuit is A drive signal output circuit that outputs a drive signal to operate the power factor correction circuit in critical mode when the peak value of the inductor current in half a cycle of the AC voltage is less than a first predetermined value, and outputs the drive signal to operate the power factor correction circuit in continuous mode when the peak value in half a cycle is greater than the first predetermined value, A drive circuit that drives the transistor based on the aforementioned drive signal, Equipped with, The aforementioned drive signal output circuit is A first command value output circuit outputs a first command value for turning on the transistor for a first period based on a feedback voltage corresponding to the output voltage and a reference voltage, A second command value output circuit outputs a second command value to turn on the transistor for the first period if the first period is shorter than a first predetermined period, and outputs a second command value to turn on the transistor for a second period that is less than or equal to the first predetermined period if the first period is longer than a first predetermined period. If the first period is shorter than the first predetermined period, an ON signal output circuit outputs an ON signal to turn on the transistor when the inductor current becomes a first current corresponding to the critical mode, and if the first period is longer than the first predetermined period, an ON signal output circuit outputs the ON signal when the inductor current becomes a second current corresponding to the continuous mode. A signal output circuit that outputs the drive signal based on the second command value and the ON signal, Includes, The first predetermined period is the period during which the transistor is turned on when the peak value in the half-cycle reaches the first predetermined value. Power factor correction circuit.

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