Semiconductor and electronic equipment

Abstract

To provide a semiconductor device capable of generating, by a small-scale circuit, a signal required for detecting a failure of a sound reproduction device.SOLUTION: There is provided a semiconductor device. In a first operation mode, a first modulated signal is input to a plurality of inverter circuits provided in a first amplifier circuit, and a second modulated signal is input to a plurality of inverter circuits provided in a second amplifier circuit. In a second operation mode, a test signal generation circuit modulates a test signal to generate a third modulated signal and a fourth modulated signal, the third modulated signal is input to some of the plurality of inverter circuits provided in the first amplifier circuit and outputs of other inverter circuits have high impedances, and the fourth modulated signal is input to some of the plurality of inverter circuits provided in the second amplifier circuit and outputs of other inverter circuits have high impedances. A peak frequency detection circuit detects a frequency range including a frequency of the test signal at which an impedance of a sound reproduction device has a peak.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to semiconductor devices and electronic equipment. [Background technology]

[0002] Patent Document 1 describes a speaker failure notification device in which a control unit measures the impedance that changes with structural changes in the speaker, determines whether the measured impedance is within a predetermined range, and notifies that the speaker is malfunctioning if it is determined that the impedance is not within that range. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2012-199854 [Overview of the project] [Problems that the invention aims to solve]

[0004] In the speaker fault detection device described in Patent Document 1, when measuring the impedance of a speaker, the control unit does not use an amplifier that increases or decreases the level of the analog audio signal and outputs it to the speaker. Instead, it applies an AC voltage of a predetermined frequency to the speaker via a dedicated physical quantity measuring instrument and measures the current flowing through the speaker, and determines the impedance from the voltage / current ratio. Therefore, in the speaker fault detection device described in Patent Document 1, a dedicated physical quantity measuring instrument is required to apply an AC voltage of a predetermined frequency to the speaker and measure the current, resulting in a large circuit for measuring the impedance of the speaker. [Means for solving the problem]

[0005] One aspect of the semiconductor device according to the present invention is The first output terminal is connected to the first terminal of the sound playback device, A second output terminal connected to the second terminal of the sound playback device, A modulation circuit that modulates a signal based on a sound source signal and outputs a first modulated signal and a second modulated signal, In the first operating mode, a first amplification circuit outputs a first amplified signal obtained by amplifying the first modulated signal to the first output terminal, In the first operating mode, a second amplification circuit outputs a second amplified signal, obtained by amplifying the second modulated signal, to the second output terminal, In the second operating mode, a test signal generation circuit generates a third modulated signal and a fourth modulated signal by modulating a test signal whose frequency is varied within a preset frequency band, In the second operating mode, a peak frequency detection circuit measures the potential difference between the first output terminal and the second output terminal and detects a frequency range that includes the peak frequency, which is the frequency of the test signal at which the impedance of the sound reproduction device peaks. Equipped with, In the second operating mode, the first amplification circuit outputs the third amplified signal, obtained by amplifying the third modulated signal, to the second output terminal. In the second operating mode, the second amplification circuit outputs the fourth amplified signal, obtained by amplifying the fourth modulated signal, to the second output terminal. The first amplification circuit has a plurality of inverter circuits, each of which is connected to the first output terminal. The second amplification circuit has a plurality of inverter circuits, each of which is connected to the second output terminal. In the first operating mode, The first modulation signal is input to each input terminal of the plurality of inverter circuits of the first amplification circuit, and the second modulation signal is input to each input terminal of the plurality of inverter circuits of the second amplification circuit. In the second operating mode, The third modulation signal is input to the input terminals of some of the inverter circuits of the plurality of inverter circuits of the first amplification circuit, and the output terminals of other of the inverter circuits of the plurality of inverter circuits of the first amplification circuit become high impedance. The fourth modulation signal is input to the input terminals of some of the inverter circuits of the plurality of inverter circuits of the second amplification circuit, and the output terminals of other of the inverter circuits of the plurality of inverter circuits of the second amplification circuit become high impedance.

[0006] One aspect of the electronic device according to the present invention is: One embodiment of the semiconductor device, The sound reproduction device and, It is equipped with. [Brief explanation of the drawing]

[0007] [Figure 1] A diagram showing an example configuration of a semiconductor device according to the first embodiment. [Figure 2] A diagram showing an example of pulse width modulation for generating a pulse width modulated signal (DOP). [Figure 3] A diagram showing an example of pulse width modulation for generating the pulse width modulated signal DON. [Figure 4] A diagram showing an example of the difference between pulse width modulated signal DOP and pulse width modulated signal DON. [Figure 5] A diagram illustrating an example of the relationship between speaker condition and impedance characteristics. [Figure 6] A diagram showing an example configuration of a Class D amplifier, a peak frequency detection circuit, and its peripheral circuits. [Figure 7] A diagram showing an example configuration of a Class D amplifier, a peak frequency detection circuit, and its peripheral circuits. [Figure 8] A diagram showing an example configuration of a differential low-pass filter and comparator. [Figure 9] A diagram showing the truth table of the encoder's output signal. [Figure 10] A flowchart illustrating an example of a procedure for measuring the start and end times of a frequency range that includes a peak frequency. [Figure 11] A figure showing an example of test signal generation and measurement of start and end times in the first embodiment. [Figure 12] A figure showing an example of test signal generation and measurement of start and end times in the first embodiment. [Figure 13] A figure showing an example of test signal generation and measurement of start and end times in the first embodiment. [Figure 14] A figure showing an example of test signal generation and measurement of start and end times in the second embodiment. [Figure 15] A figure showing an example of test signal generation and measurement of start and end times in the third embodiment. [Figure 16] A diagram showing an example configuration of the semiconductor device according to the fourth embodiment. [Figure 17] A flowchart illustrating an example of the processing procedure performed by a fault detection circuit. [Figure 18] A diagram showing another example of pulse width modulation for generating the pulse width modulated signal DON. [Figure 19] A diagram showing another example of the difference between pulse-width modulated signal DOP and pulse-width modulated signal DON. [Figure 20] Functional block diagram of the electronic device of this embodiment. [Figure 21] A diagram showing an example configuration of a warning device, which is an example of an electronic device. [Modes for carrying out the invention]

[0008] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. The embodiments described below are not intended to unduly limit the scope of the present invention as described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0009] 1. Semiconductor equipment 1-1. First Embodiment Figure 1 is a diagram showing an example configuration of a semiconductor device according to the first embodiment. As shown in Figure 1, the semiconductor device 1 of the first embodiment includes a communication interface circuit 10, a memory 20, switches 81 and 82, a sound source playback circuit 100, and a test circuit 110. The semiconductor device 1 may be a single-chip semiconductor integrated circuit device, or it may be composed of multiple-chip semiconductor integrated circuit devices, or at least a part of it may be composed of electronic components other than semiconductor integrated circuit devices.

[0010] Memory 20 stores n sound source data 21-1 to 21-n, where n is an integer greater than or equal to 1. Memory 20 may be, for example, flash memory. Each of the sound source data 21-1 to 21-n may be, for example, pulse code modulated speech data or adaptive difference pulse code modulated speech data. The sound source data 21-1 to 21-n may be, for example, data that forms the basis of various sounds such as voices that mimic human speech, mechanical warning sounds, and sound effects.

[0011] The communication interface circuit 10 is a circuit that communicates data with the microcontroller unit 2. The communication interface circuit 10 may be, for example, an SPI interface circuit or an I2C interface circuit. SPI stands for Serial Peripheral Interface, and I2C stands for Inter-Integrated Circuit.

[0012] The communication interface circuit 10 receives various commands transmitted from the microcontrol unit 2 and generates various control signals corresponding to the received commands. For example, when the communication interface circuit 10 receives a command to switch the operating mode of the semiconductor device 1 to normal operating mode or inspection mode, it generates a control signal to switch the connection of switches 41 and 42 according to the operating mode. Also, when the communication interface circuit 10 receives a sound source playback command for one of the sound source data 21-i, which is one of the sound source data 21-1 to 21-n stored in the memory 20, it reads the sound source data 21-i from the memory 20 and inputs it as a sound source signal DI to the sound source playback circuit 100, and also instructs the sound source playback circuit 100 to play the sound. Also, for example, when the communication interface circuit 10 receives a sound source stop command for sound source data 21-i that is currently playing, it instructs the sound source playback circuit 100 to stop playback. Also, for example, when the communication interface circuit 10 receives various setting commands related to sound source playback, it performs various settings on the sound source playback circuit 100.

[0013] In this embodiment, the sound source signal DI input to the sound source playback circuit 100 is a pulse code modulated signal. If the sound source data 21-1 to 21-n are compressed audio data or adaptive difference pulse code modulated audio data, the sound source data 21-i to be played back is converted into a pulse code modulated signal, the sound source signal DI, by a decoder (not shown).

[0014] The sound source playback circuit 100 converts the sound source signal DI into amplified signals DOXP and DOXN, which are sound signals, and outputs them to the sound playback device 3 connected to the semiconductor device 1. As a result, the sound playback device 3 outputs sounds corresponding to the amplified signals DOXP and DOXN. For example, the sound playback device 3 may be a speaker or a buzzer. The sound output from the sound playback device 3 may be, for example, a voice that mimics a person speaking, or various sounds such as mechanical warning sounds or sound effects.

[0015] As shown in Figure 1, in this embodiment, the sound source playback circuit 100 includes a modulation circuit 30, switches 41 and 42, and an amplification circuit 50.

[0016] The modulation circuit 30 receives the sound source signal DI as input, modulates the signal based on the sound source signal DI, and outputs pulse width modulation signals DOP and DON. The signal based on the sound source signal DI may be the sound source signal DI itself, or it may be a signal that has undergone some processing on the sound source signal DI. In this embodiment, the modulation circuit 30 includes a digital filter 31, a sigma-delta modulation circuit 32, and a pulse width modulation circuit 33.

[0017] The digital filter 31 is a low-pass filter that receives the sound source signal DI as input and outputs a signal DF with the high-frequency noise contained in the sound source signal DI reduced. The sigma-delta modulation circuit 32 receives the signal DF from the digital filter 31 as input and outputs a sigma-delta modulated signal DS with noise biased towards the high-frequency band by oversampling the signal DF by a sampling ratio of n times. n is an integer of 2 or more. Therefore, if the sampling frequency of the sound source signal DI is fs, the sampling frequency of the signal DF output from the digital filter 31 is fs, and the sampling frequency of the sigma-delta modulated signal DS is n × fs. The digital filter 31 functions as an anti-aliasing filter that reduces high-frequency noise folded back into the signal band by the oversampling of the sigma-delta modulation circuit 32.

[0018] The pulse width modulation circuit 33 pulse-width modulates the sigma-delta modulated signal DS and outputs pulse width modulated signals DOP and DON. Each of the pulse width modulated signals DOP and DON is a 1-bit digital signal. If the sampling frequency of the sigma-delta modulated signal DS is n × fs, then the sampling frequency of the pulse width modulated signals DOP and DON is n × m × fs. Here, if the number of bits in the sigma-delta modulated signal DS is M, then m = 2 M That is the case.

[0019] Thus, the modulation circuit 30 digitally filters the sound source signal DI, modulates the resulting signal with sigma-delta modulation, and then pulse-width modulates it to output pulse-width modulated signals DOP and DON.

[0020] The pulse width modulation used to generate the pulse width modulated signal DOP and the pulse width modulated signal DON use different methods. Figure 2 shows an example of pulse width modulation used to generate the pulse width modulated signal DOP. Figure 3 shows an example of pulse width modulation used to generate the pulse width modulated signal DON. Figures 2 and 3 are examples where the number of bits M of the sigma-delta modulated signal DS is 4. In Figures 2 and 3, the sigma-delta modulated signal DS is updated with a period T as its period, and the pulse width modulated signals DOP and DON are high-level or low-level in each of the 16 sections T1 to T16 into which the period T is divided. That is, the length of the period T is 1 / (n × fs), and the length of each section T1 to T16 is 1 / (n × m × fs).

[0021] As shown in Figure 2, the pulse width modulation signal DOP has a longer high-level duration as the value of the sigma-delta modulation signal DS increases. For example, when the sigma-delta modulation signal DS is "-7" in decimal, or "1001" in binary, the pulse width modulation signal DOP has one high-level section T1 and 15 low-level sections T2 to T16. Also, for example, when the sigma-delta modulation signal DS is "0" in decimal, or "0000" in binary, the pulse width modulation signal DOP has 8 high-level sections T1 to T8 and 8 low-level sections T9 to T16. Furthermore, for example, when the sigma-delta modulation signal DS is "7" in decimal, or "0111" in binary, the pulse width modulation signal DOP has 15 high-level sections T1 to T15 and one low-level section T16.

[0022] As shown in Figure 3, the pulse width modulated signal DON becomes shorter in high-level periods as the value of the sigma-delta modulated signal DS increases. For example, when the sigma-delta modulated signal DS is "-7" in decimal, or "1001" in binary, the pulse width modulated signal DON has 15 high-level sections T1 to T15 and one low-level section T16. Also, for example, when the sigma-delta modulated signal DS is "0" in decimal, or "0000" in binary, the pulse width modulated signal DON has 8 high-level sections T1 to T8 and 8 low-level sections T9 to T16. Furthermore, for example, when the sigma-delta modulated signal DS is "7" in decimal, or "0111" in binary, the pulse width modulated signal DON has one high-level section T1 and 15 low-level sections T2 to T16.

[0023] Therefore, for example, when the sigma-delta modulated signal DS is the decimal values ​​"-7", "0", and "7", the difference between the pulse-width modulated signal DOP and the pulse-width modulated signal DON will be as shown in Figure 4.

[0024] Returning to the explanation of Figure 1, switch 41 outputs either the pulse-width modulated signal DOP or the pulse-width modulated signal TP to the Class D amplifier 51P of the amplification circuit 50, depending on the control signal output from the communication interface circuit 10. Specifically, when the operating mode of the semiconductor device 1 is the normal operating mode, switch 41 outputs the pulse-width modulated signal DOP to the Class D amplifier 51P, and when the operating mode of the semiconductor device 1 is the test mode, switch 41 outputs the pulse-width modulated signal TP to the Class D amplifier 51P.

[0025] Furthermore, switch 42 outputs either the pulse-width modulated signal DON or the pulse-width modulated signal TN to the Class D amplifier 51N of the amplification circuit 50, depending on the control signal output from the communication interface circuit 10. Specifically, when the semiconductor device 1 is in normal operation mode, switch 42 outputs the pulse-width modulated signal DON to the Class D amplifier 51N, and when the semiconductor device 1 is in test mode, switch 42 outputs the pulse-width modulated signal TN to the Class D amplifier 51N.

[0026] In normal operation mode, the amplification circuit 50 receives pulse width modulated signals DOP and DON as input and outputs amplified signals DOXP and DOXN, obtained by amplifying the pulse width modulated signals DOP and DON, to the output terminals 91 and 92 of the semiconductor device 1. In test mode, the amplification circuit 50 receives pulse width modulated signals TP and TN as input and outputs amplified signals DOXP and DOXN, obtained by amplifying the pulse width modulated signals TP and TN, to the output terminals 91 and 92 of the semiconductor device 1.

[0027] In this embodiment, the amplification circuit 50 includes two Class D amplifiers 51P and 51N. In normal operation mode, Class D amplifier 51P outputs an amplified signal DOXP, obtained by amplifying the pulse width modulated signal DOP, to output terminal 91, and in test mode, it outputs an amplified signal DOXP, obtained by amplifying the pulse width modulated signal TP, to output terminal 91. In normal operation mode, Class D amplifier 51N outputs an amplified signal DOXN, obtained by amplifying the pulse width modulated signal DON, to output terminal 92, and in test mode, it outputs an amplified signal DOXN, obtained by amplifying the pulse width modulated signal TN, to output terminal 92. Output terminal 91 is connected to terminal P1 of the sound reproduction device 3, and output terminal 92 is connected to terminal P2 of the sound reproduction device 3. The sound reproduction device 3 then reproduces a sound of a magnitude corresponding to the voltage difference between the amplified signal DOXP and the amplified signal DOXN.

[0028] The inspection circuit 110 is a circuit for inspecting the sound reproduction device 3.

[0029] Figure 5 shows an example of the relationship between the speaker's state and its impedance characteristics. In Figure 5, the horizontal axis represents the frequency of the speaker's input signal, and the vertical axis represents the speaker's impedance value. G1 is an example of the impedance characteristics when the speaker is functioning normally. The peak frequency f0, which is the input signal frequency at which the speaker's impedance peaks, varies depending on the type of speaker. However, when a speaker is functioning correctly, it falls within a frequency range that is at least above 20Hz (the lower limit of human hearing) and below 3kHz (the frequency used for buzzer warning sounds). G2 is an example of the impedance characteristics when the speaker's magnet is damaged and detached. When the magnet is removed, the speaker is left with only the coil, so the impedance value slowly increases as the frequency increases, and the peak frequency f0 disappears. G3 is an example of the impedance characteristics when the speaker's cone is torn. When the cone, which is the vibrating surface of the speaker, is torn, bass is lost, and the peak frequency f0 shifts to the higher frequency side.

[0030] Thus, the peak frequency f0 changes depending on the state of the speaker. Therefore, in this embodiment, the test circuit 110 detects the frequency range F0 that includes the peak frequency f0 in the test mode. In this embodiment, the test circuit 110 includes a test signal generation circuit 60 and a peak frequency detection circuit 70.

[0031] In the test mode, the test signal generation circuit 60 modulates a test signal whose frequency has been varied within a preset frequency band to generate modulated signals TP and TN. The frequency band in which the test signal generation circuit 60 changes the frequency of the test signal can be arbitrarily set by the microcontroller unit 2, and may be, for example, a frequency band of 10 Hz to 3 kHz. In this embodiment, the test signal generation circuit 60 generates pulse-width modulated signals TP and TN by pulse-width modulating the test signal. The pulse-width modulation method used by the test signal generation circuit 60 is the same as the pulse-width modulation method used by the pulse-width modulation circuit 33.

[0032] In test mode, the peak frequency detection circuit 70 measures the potential difference between output terminal 91 and output terminal 92 and detects the frequency range F0 that includes the peak frequency f0, which is the frequency of the test signal at which the impedance of the sound reproduction device 3 peaks.

[0033] Switch 81 switches between electrically connecting or disconnecting the output terminal 91 of the semiconductor device 1 and the peak frequency detection circuit 70 in accordance with the control signal output from the communication interface circuit 10. Specifically, when the operating mode of the semiconductor device 1 is the normal operating mode, switch 81 electrically disconnects the output terminal 91 and the peak frequency detection circuit 70, and when the operating mode of the semiconductor device 1 is the test mode, switch 81 electrically connects the output terminal 91 and the peak frequency detection circuit 70.

[0034] Furthermore, the switch 82 switches between electrically connecting or disconnecting the output terminal 92 of the semiconductor device 1 and the peak frequency detection circuit 70 in accordance with the control signal output from the communication interface circuit 10. Specifically, when the operating mode of the semiconductor device 1 is the normal operating mode, the switch 82 electrically disconnects the output terminal 92 and the peak frequency detection circuit 70, and when the operating mode of the semiconductor device 1 is the test mode, the switch 82 electrically connects the output terminal 92 and the peak frequency detection circuit 70.

[0035] Thus, the peak frequency detection circuit 70, via switches 81 and 82, has output terminals 91 and 9 in normal operation mode. 2 And it is electrically disconnected, and in test mode output terminals 91, 9 2 The system is electrically connected to the output terminals 91 and 92, and measures the potential difference between them to detect the frequency range F0 that includes the peak frequency f0.

[0036] When the communication interface circuit 10 receives a command from the microcontroller unit 2 to read the frequency range F0 which includes the peak frequency f0, it obtains the frequency range F0 from the peak frequency detection circuit 70 and transmits it to the microcontroller unit 2. For example, based on the frequency range F0, the microcontroller unit 2 detects a fault in the sound playback device 3. It can determine the presence or absence of a problem and the failure mode.

[0037] Figures 6 and 7 show example configurations of the Class D amplifiers 51P and 51N, the peak frequency detection circuit 70, and their peripheral circuits. Figure 6 shows the configuration in normal operation mode, and Figure 7 shows the configuration in test mode.

[0038] As shown in Figures 6 and 7, the Class D amplifier 51P has a plurality of inverter circuits 201-1 to 201-n, and the Class D amplifier 51N has a plurality of inverter circuits 202-1 to 202-n. n is an integer of 2 or more, for example, it may be around 10 to 100. Each of the inverter circuits 201-1 to 201-n is composed of a pair of PMOS transistors and NMOS transistors, and the output terminal, which is a node where the drains of the PMOS transistor and the drain of the NMOS transistor are connected, is connected to output terminal 91. Similarly, each of the inverter circuits 202-1 to 202-n is composed of a pair of PMOS transistors and NMOS transistors, and the output terminal, which is a node where the drains of the PMOS transistor and the drain of the NMOS transistor are connected, is connected to output terminal 92.

[0039] As shown in Figure 6, in normal operation mode, the modulation signal DOP is input to each input terminal of inverter circuits 201-1 to 201-n of the Class D amplifier 51P via switch 41, and the modulation signal DON is input to each input terminal of inverter circuits 202-1 to 202-n of the Class D amplifier 51N via switch 42. That is, in normal operation mode, the inverter circuits 201-1 to 201-n of the Class D amplifier 51P are connected in parallel between the modulation circuit 30 and the output terminal 91 of the semiconductor device 1, and the inverter circuits 202-1 to 202-n of the Class D amplifier 51N are connected in parallel between the modulation circuit 30 and the output terminal 92 of the semiconductor device 1. As a result, the on-resistance R of the Class D amplifier 51P onP This is 1 / n of the on-resistance of inverter circuit 201-1, and the on-resistance R of class D amplifier 51N. onN This is 1 / n of the on-resistance of inverter circuit 202-1.

[0040] Then, the amplifier circuit 50 outputs an amplified signal DOXP obtained by amplifying the modulation signal DOP to the output terminal 91, and outputs an amplified signal DOXN obtained by amplifying the modulation signal DON to the output terminal 92. The output terminals 91 and 92 are respectively connected to the terminals P1 and P2 of the sound playback device 3. The impedance R between the terminal P1 and the terminal P2 sp is, for example, 4Ω to 128Ω, and in the normal operation mode, the on-resistance R of the class-D amplifier 51P onP and the on-resistance R of the class-D amplifier 51N onN are about 1 / 10 to 1 / 100 of the impedance R of the sound playback device 3 sp .

[0041] Also, as shown in FIG. 6, Normal operation in the mode, the switches 81 and 82 are non-conductive, and the peak frequency detection circuit 70 is electrically disconnected from the output terminals 91 and 92 of the semiconductor device 1.

[0042] On the other hand, as shown in FIG. 7, in the inspection mode, the modulation signal TP is input to each input terminal of some of the inverter circuits of the inverter circuits 201-1 to 201-n included in the class-D amplifier 51P via the switch 41, and each output terminal of the other some of the inverter circuits of the inverter circuits 201-1 to 201-n becomes a high impedance. For example, in the inspection mode, the modulation signal TP is input to the input terminal of the inverter circuit 201-1, and each output terminal of the inverter circuits 201-2 to 201-n becomes a high impedance. Similarly, the modulation signal TN is input to each input terminal of some of the inverter circuits of the inverter circuits 202-1 to 202-n included in the class-D amplifier 51N via the switch 42, and each output terminal of the other some of the inverter circuits of the inverter circuits 202-1 to 202-n becomes a high impedance. For example, in the inspection mode, the modulation signal TN is input to the input terminal of the inverter circuit 202-1, and each output terminal of the inverter circuits 202-2 to 202-n becomes a high impedance. As a result, for example, the on-resistance R of the class-D amplifier 51P onP and the on-resistance R of the class-D amplifier 51N onN are the impedance R spIt will be about the same level as that.

[0043] Furthermore, as shown in Figure 7, in the test mode, switches 81 and 82 conduct, and the peak frequency detection circuit 70 is electrically connected to the output terminals 91 and 92 of the semiconductor device 1.

[0044] The peak frequency detection circuit 70 includes a differential low-pass filter 71, a comparator 72, and a peak time measurement circuit 73.

[0045] In test mode, the differential low-pass filter 71 receives the voltages from output terminals 91 and 92 via switches 81 and 82. Specifically, the differential low-pass filter 71 receives the amplified signals DOXP and DOXN, reduces the high-frequency noise components superimposed on the amplified signals DOXP and DOXN by pulse width modulation, and outputs a voltage V' corresponding to the potential difference between the amplified signals DOXP and DOXN. The cutoff frequency of the differential low-pass filter 71 is higher than the maximum frequency of the frequency band in which the test signal generation circuit 60 changes the frequency of the test signal. For example, if the test signal generation circuit 60 changes the frequency of the test signal in a frequency band from 10 Hz to 3 kHz, the cutoff frequency of the differential low-pass filter 71 is higher than 3 kHz. Since the cutoff frequency of the differential low-pass filter 71 is higher than the maximum frequency of the frequency band in which the frequency of the test signal changes, the differential low-pass filter 71 does not attenuate the frequency components included in that frequency band.

[0046] The comparator 72 compares the output voltage of the differential low-pass filter 71 with at least one threshold voltage and outputs data DT indicating the comparison result. For example, the comparator 72 m - This could be an analog-to-digital conversion circuit that outputs an m-bit digital signal compared to a threshold voltage, where m is an integer greater than or equal to 1.

[0047] The peak time measurement circuit 73 measures a range that includes the time when the potential difference between output terminal 91 and output terminal 92 is maximum, based on the data DT which is the output signal of the comparator 72. For example, the peak time measurement circuit 73 defines the range that includes the time when the potential difference between output terminal 91 and output terminal 92 is maximum as the start time t of that range. start and end time t stop The following can be measured: If the frequency of the test signal increases over time in the frequency band between 10 Hz and 3 kHz, the start time t start The frequency of the test signal at this point corresponds to the lower limit of the frequency range F0, and the end time t stop The frequency of the test signal corresponds to the upper limit of the frequency range F0.

[0048] Thus, in the test mode, the peak frequency detection circuit 70 detects the frequency range F0 that includes the peak frequency f0 by measuring the range that includes the time when the potential difference between output terminal 91 and output terminal 92 is maximum. The frequency range F0 detected by the peak frequency detection circuit 70 is the range that includes the time when the potential difference between output terminal 91 and output terminal 92 is maximum, starting from the start time t start and end time t stop Alternatively, the peak frequency detection circuit 70 may use the following as the frequency range F0: start time t start and end time t stop The frequency range of the corresponding test signal may be calculated.

[0049] Figure 8 shows an example configuration of a differential low-pass filter 71 and a comparator 72. As shown in Figure 8, the differential low-pass filter 71 includes an operational amplifier 211, five resistors 212, 213, 214, 216, and 218, and three capacitors 215, 217, and 219.

[0050] In test mode, the amplified signal DOXP, output to output terminal 91 of semiconductor device 1, is input to one end of resistor 212. The amplified signal DOXN, output to output terminal 92 of semiconductor device 1, is input to one end of resistor 213. The other end of resistor 212 and the other end of resistor 214... The terminal of resistor 213 and one end of capacitor 215 are connected to the non-inverting input terminal of operational amplifier 211. The other end of resistor 213, one end of resistor 216, one end of capacitor 217, one end of resistor 218, and one end of capacitor 219 are connected to the inverting input terminal of operational amplifier 211.

[0051] The other end of resistor 214 and the other end of capacitor 215 are connected to the output terminal of operational amplifier 211. The other end of resistor 216 and the other end of capacitor 217 are grounded, and the power supply voltage is supplied to the other end of resistor 218 and the other end of capacitor 219.

[0052] The differential low-pass filter 71, configured in this way, reduces high-frequency noise components superimposed on the amplified signals DOXP and DOXN by pulse width modulation, and outputs a voltage V' from the output terminal of the operational amplifier 211 corresponding to the potential difference between the amplified signals DOXP and DOXN, i.e., the potential difference between output terminal 91 and output terminal 92. When the power supply voltage is VDD and the ground voltage is 0V, if the potential difference between output terminal 91 and output terminal 92, from which high-frequency noise components have been reduced, is positive, the voltage V' will be higher than VDD × 1 / 2, and if the potential difference between output terminal 91 and output terminal 92, from which high-frequency noise components have been reduced, is negative, the voltage V' will be lower than VDD × 1 / 2.

[0053] Then, the amplitude voltage V'(pp) of the voltage V' and the impedance R of the sound reproduction device 3 are used. sp , Class D amplifier 51P on-resistance R onP and the on-resistance R of the Class D amplifier 51N onN The relationship between them is given by equation (1). From equation (1), the impedance R sp The larger the impedance R, the larger the amplitude of the voltage V' becomes. sp The amplitude of voltage V' is maximum when it reaches its peak.

[0054]

number

[0055] The comparator 72 includes eight resistors 221-228, seven comparators 231-237, six logic elements 241-247, and an encoder 250.

[0056] Resistors 221-228 are connected in series between the power supply and ground. Resistors 222-227 have the same resistance value. Resistors 221 and 228 are adjusted to match the maximum set value of the amplitude voltage V'(pp) of the voltage V'. For the sake of simplicity, we will assume here that resistors 221-228 all have the same resistance value. Assuming the power supply voltage is VDD and the ground voltage is 0V, the voltage at the connection node between resistor 221 and resistor 222 is VDD × 7 / 8, the voltage at the connection node between resistor 222 and resistor 223 is VDD × 6 / 8, the voltage at the connection node between resistor 223 and resistor 224 is VDD × 5 / 8, the voltage at the connection node between resistor 224 and resistor 225 is VDD × 4 / 8, the voltage at the connection node between resistor 225 and resistor 226 is VDD × 3 / 8, the voltage at the connection node between resistor 226 and resistor 227 is VDD × 2 / 8, and the voltage at the connection node between resistor 227 and resistor 228 is VDD × 1 / 8.

[0057] The output signal of comparator 231 is low when the voltage V' is higher than VDD × 7 / 8, which is the voltage at the connection node between resistors 221 and 222, and high otherwise. The output signal of comparator 232 is low when the voltage V' is higher than VDD × 6 / 8, which is the voltage at the connection node between resistors 222 and 223, and high otherwise. The output signal of comparator 233 is low when the voltage V' is higher than VDD × 5 / 8, which is the voltage at the connection node between resistors 223 and 224, and high otherwise. The output signal of comparator 234 is low when the voltage V' The output signal of comparator 235 is low when the voltage V' is higher than VDD × 4 / 8, which is the voltage at the connection node between resistors 224 and 225, and high otherwise. The output signal of comparator 236 is low when the voltage V' is higher than VDD × 3 / 8, which is the voltage at the connection node between resistors 225 and 226, and high otherwise. The output signal of comparator 237 is low when the voltage V' is higher than VDD × 2 / 8, which is the voltage at the connection node between resistors 226 and 227, and high otherwise.

[0058] Logic element 241 outputs a low level signal when the output signal of comparator 231 is high level and the output signal of comparator 232 is low level, and a high level signal otherwise. Logic element 242 outputs a low level signal when the output signal of comparator 232 is high level and the output signal of comparator 233 is low level, and a high level signal otherwise. Logic element 243 outputs a low level signal when the output signal of comparator 233 is high level and the output signal of comparator 234 is low level, and a high level signal otherwise. Logic element 244 outputs a low level signal when the output signal of comparator 234 is high level and the output signal of comparator 235 is low level, and a high level signal otherwise. Logic element 245 outputs a low level signal when the output signal of comparator 235 is high level and the output signal of comparator 236 is low level, and a high level signal otherwise. Logic element 246 outputs a signal that is low level when the output signal of comparator 236 is high level and the output signal of comparator 237 is low level, and high level otherwise.

[0059] Therefore, when the voltage V' is higher than VDD × 7 / 8, the output signals of logic elements 241 to 247 are at a high level. Also, when the voltage V' is higher than VDD × 6 / 8 and lower than VDD × 7 / 8, the output signal of logic element 241 is at a low level, and the output signals of logic elements 242 to 247 are at a high level. Also, when the voltage V' is higher than VDD × 5 / 8 and lower than VDD × 6 / 8, the output signals of logic elements 241 and 242 are at a low level, and the output signals of logic elements 243 to 247 are at a high level. Also, when the voltage V' is higher than VDD × 4 / 8 and lower than VDD × 5 / 8, the output signals of logic elements 241 to 243 are at a low level, and the output signals of logic elements 244 to 247 are at a high level. Furthermore, when the voltage V' is higher than VDD × 3 / 8 and lower than VDD × 4 / 8, the output signals of logic elements 241 to 244 become low, and the output signals of logic elements 245 to 247 become high. Also, when the voltage V' is higher than VDD × 2 / 8 and lower than VDD × 3 / 8, the output signals of logic elements 241 to 245 become low, and the output signals of logic elements 246 and 247 become high. Also, when the voltage V' is higher than VDD × 1 / 8, the output signals of logic elements 241 to 246 become low, and only the output signal of logic element 247 becomes high.

[0060] The output signals of logic elements 241 to 247 are denoted as signals D1 to D7, respectively, and the encoder 250 encodes signals D1 to D7 into 3-bit data DT[2:0] according to the table in Figure 9.

[0061] As shown in Figure 9, when signals D1 to D7 are high levels, data DT[2:0] is 011. Also, when signal D1 is low level and signals D2 to D7 are high levels, data DT[2:0] is 010. Also, when signals D1 and D2 are low levels and signals D3 to D7 are high levels, data DT[2:0] is 001. When signals D1 to D3 are low level and signals D4 to D7 are high level, data DT[2:0] is 000. Also, when signals D1 to D4 are low level and signals D5 to D7 are high level, data DT[2:0] is 100. Also, when signals D1 to D5 are low level and signals D6 and D7 are high level, data DT[2:0] is 101. Also, when signals D1 to D6 are low level and signal D7 is high level, data DT[2:0] is 110. Also, when signals D1 to D7 are low level, data DT[2:0] is 111.

[0062] DT[2] represents the sign of the voltage V', being low level when the voltage V' is higher than VDD × 1 / 2, and high level when the voltage V' is lower than VDD × 1 / 2. DT[1:0] represents the amplitude of the voltage V', and can take four values: 00, 01, 10, and 11.

[0063] The peak time measurement circuit 73, for example, based on 2-bit data DT[1:0], determines the start time t of the range that includes the time when the potential difference between output terminal 91 and output terminal 92 is maximum. start and end time t stop It can be measured.

[0064] Figure 10 shows the peak time measurement circuit 73 starting at time t start and end time t stop This is a flowchart illustrating an example of the procedure for measuring [something]. In the example in Figure 10, it is assumed that N data points DT[1:0], from data DT(0)[1:0] to data DT(N-1)[1:0], are input to the peak time measurement circuit 73.

[0065] As shown in Figure 10, first, in step S1, the peak time measurement circuit 73 initializes the variable i, which indicates the number of data DT[1:0], to 0, and the variable DT[1:0], which indicates the maximum value of data DT[1:0] max Initialize to 00, and start time t start and end time t stop Initialize both to 0.

[0066] Next, in step S2, the peak time measurement circuit 73 determines that the data DT(i)[1:0] is variable DT[1:0] max Determine whether it is greater than or equal to. Then, in step S2, the data DT(i)[1:0] is equal to the variable DT[1:0] max If it is greater than, in process S3, the peak time measurement circuit 73 measures the variable DT[1:0] max Update the data DT(i)[1:0] and the start time t start and end time t stop Update both to i.

[0067] On the other hand, in process S2, the data DT(i)[1:0] is the variable DT[1:0] max If equal to the above, in step S4, the peak time measurement circuit 73 determines that the data DT(i)[1:0] is equal to the variable DT[1:0] max Determine whether it is equal to or not. Then, in step S4, if the data DT(i)[1:0] is equal to the variable DT[1:0] max If equal to, in step S5, the peak time measurement circuit 73 determines the end time t stop Update to i.

[0068] Next, in step S6, the peak time measurement circuit 73 determines whether the variable i is less than N-1. If, in step S6, the variable i is less than N-1, then in step S7, the peak time measurement circuit 73 updates the variable i to i+1 and repeats the process from step S2 onward until the variable i reaches N-1. When the variable i reaches N-1, the peak time measurement circuit 73 terminates the process.

[0069] Figures 11-13 show the generation of the test signal by the test circuit 110 and the start time t. start and end time t stop This figure shows an example of measurement. Figure 11 is an example where the impedance characteristic of the sound reproduction device 3 is G1 in Figure 5. Figure 12 is an example where the impedance characteristic of the sound reproduction device 3 is G2 in Figure 5. Figure 13 is an example where the impedance characteristic of the sound reproduction device 3 is G3 in Figure 5. In the examples of Figures 11 to 13, the test signal generation cycle Circuit 60 continuously changes the frequency of the test signal within a frequency band of 10 Hz to 3 kHz while maintaining the amplitude of the test signal at a constant voltage V1.

[0070] In the example in Figure 11, the amplitude of the output voltage V' of the differential low-pass filter 71 is maximum at the peak frequency f0 of the test signal. The maximum value of the data DT[1:0] output by the comparator 72 is 10, and the peak time measurement circuit 73 determines the variable i when the data DT[1:0] first becomes 10 at the start time t start The measurement is performed, and the variable i is defined as the point at which the data DT[1:0] finally becomes 10 at the end time t. stop Measure it as follows.

[0071] In the example in Figure 12, the data DT[1:0] output by the comparator 72 is always 00, and its maximum value is also 00. Therefore, the peak time measurement circuit 73 determines that the variable i=0 when the data DT[1:0] first becomes 10 is at the start time t start The measurement is performed, and the variable i=N-1 at the end time t is defined as the point when the data DT[1:0] finally reaches 10. stop The peak frequency detection circuit 70 measures the start time t. start From end time t stop The entire frequency band F0 of the test signal corresponding to the time until the specified time is detected, ranging from 10 Hz to 3 kHz.

[0072] In the example in Figure 13, the maximum value of the data DT[1:0] output by the comparator 72 is 01, and the peak time measurement circuit 73 determines the variable i when the data DT[1:0] first becomes 01 at the start time t start The measurement is performed, and the variable i=N-1 at the end time t is defined as the point when the data DT[1:0] finally reaches 10. stop The peak frequency detection circuit 70 measures the start time t. start From end time t stop The frequency range F0 of the test signal corresponding to the time until is detected.

[0073] When the communication interface circuit 10 receives a command from the microcontroller unit 2 to read the frequency range F0 which includes the peak frequency f0, it reads the frequency range F0 from the peak frequency detection circuit 70 and the start time t start and end time t stop The system acquires and transmits the data to the microcontroller unit 2. Alternatively, the peak frequency detection circuit 70 determines the start time t start From end time t stop The communication interface circuit 10 may calculate the frequency range F0 of the test signal corresponding to the time until the end of the test, acquire this frequency range F0, and transmit it to the microcontroller unit 2. The microcontroller unit 2 acquires the frequency range F0 via the communication interface circuit 10 and can determine whether the sound reproduction device 3 is faulty and what the fault mode is based on the frequency range F0. The microcontroller unit 2 determines that the sound reproduction device 3 is normal if the lower and upper limits of the frequency range F0 are within a predetermined range, and that it is faulty otherwise. Furthermore, if the sound reproduction device 3 is faulty, the microcontroller unit 2 determines the fault mode based on the lower and upper limits of the frequency range F0.

[0074] For example, in the example shown in Figure 11, the microcontroller 2 sets the start time t corresponding to the lower limit of the frequency range F0. start The end time t is included in the first reference range and corresponds to the upper limit of the frequency range F0. stop Since it falls within the second reference range, the sound reproduction device 3 is determined to be normal. Also, in the examples of Figure 12 and Figure 13, the microcontroller unit 2 determines the start time t corresponding to the lower limit of the frequency range F0. start If the end time t is not included in the first reference range, or if it corresponds to the upper limit of the frequency range F0, stop Since it does not fall within the second reference range, it can be determined that the sound playback device 3 is malfunctioning. Also, in the example in Figure 12, the microcontroller unit 2 determines that the start time t start The value is 0, and the end time t stop Since N-1, the test signal must be between 10Hz and 3kHz. belowEven if the frequency band changes, the failure mode in which the voltage V' gradually changes, that is, the failure mode in which the impedance characteristics become like G2 in Figure 5, can be determined to be a failure mode in which the magnet of the speaker of the sound reproduction device 3 is damaged and detached. Also, in the example in Figure 13, the microcontroller unit 2 starts at time t start The value is close to N-1, and the end time t stop Since N-1, it can be determined that this is a failure mode in which the peak frequency f0 shifts to a frequency higher than 3kHz, that is, a failure mode in which the cone paper of the sound reproduction device 3 is torn, and the impedance characteristics become as shown by G3 in Figure 5.

[0075] In the first embodiment, terminal P1 of the sound reproduction device 3 is an example of a "first terminal," and terminal P2 of the sound reproduction device 3 is an example of a "second terminal." Also, output terminal 91 of the semiconductor device 1 is an example of a "first output terminal," and output terminal 92 of the semiconductor device 1 is an example of a "second output terminal." Furthermore, pulse width modulated signal DOP is an example of a "first modulated signal," and pulse width modulated signal DON is an example of a "second modulated signal." Also, pulse width modulated signal TP is an example of a "third modulated signal," and pulse width modulated signal TN is an example of a "fourth modulated signal." Furthermore, amplified signal DOXP, obtained by amplified pulse width modulated signal DOP, is an example of a "first amplified signal," and amplified signal DOXN, obtained by amplified pulse width modulated signal DON, is an example of a "second amplified signal." Furthermore, amplified signal DOXP, obtained by amplified pulse width modulated signal TP, is an example of a "third amplified signal," and amplified signal DOXN, obtained by amplified pulse width modulated signal TN, is an example of a "fourth amplified signal." Furthermore, the Class D amplifier 51P is an example of a "first amplification circuit," and the Class D amplifier 51N is an example of a "second amplification circuit." Also, the normal operating mode is an example of a "first operating mode," and the test mode is an example of a "second operating mode."

[0076] The semiconductor device 1 of the first embodiment is configured to output sound to one sound playback device 3, but it may also be configured to output sound to multiple sound playback devices.

[0077] As described above, according to the semiconductor device 1 of the first embodiment, in the normal operating mode, the Class D amplifier 51P outputs an amplified signal DOXP, which is obtained by amplifying the pulse width modulated signal DOP based on the sound source signal DI, to the output terminal 91, and the Class D amplifier 51N outputs an amplified signal DOXN, which is obtained by amplifying the pulse width modulated signal DON based on the sound source signal DI, to the output terminal 92, thereby enabling the sound reproduction device 3 to reproduce sound. Specifically, in the normal operating mode, the inverter circuits 201-1 to 201-n of the Class D amplifier 51P are connected in parallel, and the inverter circuits 202-1 to 202-n of the Class D amplifier 51N are connected in parallel. Therefore, the on-resistance R of the Class D amplifier 51P onP and the on-resistance R of the Class D amplifier 51N onN The impedance R of the sound playback device 3 sp This makes the noise level significantly lower, allowing the sound playback device 3 to reproduce sound properly.

[0078] On the other hand, in test mode, the Class D amplifier 51P outputs an amplified signal DOXP, which is obtained by amplifying the pulse width modulated signal TP based on the test signal, to output terminal 91, and the Class D amplifier 51N outputs an amplified signal DOXN, which is obtained by amplifying the pulse width modulated signal TN based on the test signal, to output terminal 92. As a result, the peak frequency detection circuit 70 measures the potential difference between output terminal 91 and output terminal 92 and can detect the frequency range F0 that includes the peak frequency f0 at which the impedance of the sound reproduction device 3 peaks. Specifically, in test mode, some outputs of the inverter circuits 201-1 to 201-n of the Class D amplifier 51P become high impedance, and some outputs of the inverter circuits 202-1 to 202-n of the Class D amplifier 51N become high impedance. Therefore, the on-resistance R of the Class D amplifier 51P onP and the on-resistance R of the Class D amplifier 51N onN As R increases, from the above equation (1), the impedance R of the sound reproduction device 3 sp The change in on-resistance R causes a large change in the potential difference between output terminal 91 and output terminal 92. onP ,R onN The impedance R sp If you make it roughly the same, then impedance Rsp Since the change in the potential difference between output terminal 91 and output terminal 92 is the most sensitive to changes in the frequency, the peak frequency detection circuit 70 can accurately detect the frequency range F0 that includes the peak frequency f0. Therefore, the microcontroller unit 2 estimates the impedance characteristics of the sound reproduction device 3 based on the frequency range F0 that includes the peak frequency f0, and determines whether or not there is a malfunction in the sound reproduction device 3 and the mode of the malfunction. It is possible.

[0079] In other words, in the semiconductor device 1 of the first embodiment, the Class D amplifier 51P and the Class D amplifier 51N are used for both generating the amplification signals DOXP and DOXN for generating sound in the sound reproduction device 3 in the normal operation mode, and generating the amplification signals DOXP and DOXN necessary for detecting the frequency range F0 which includes the peak frequency f0 in the test mode. Furthermore, in the test mode, the impedance R of the sound reproduction device 3 is used. sp Because the change in potential difference between output terminal 91 and output terminal 92 due to the change is large, the size of the peak frequency detection circuit 70 is reduced. Therefore, according to the semiconductor device 1 of the first embodiment, the signal necessary to detect a malfunction in the sound reproduction device 3 can be generated with a small circuit.

[0080] Furthermore, according to the semiconductor device 1 of the first embodiment, the impedance R of the sound reproduction device 3 sp Since the potential difference between output terminal 91 and output terminal 92 also peaks when the peak frequency f0 occurs, the frequency range F0 containing the peak frequency f0 can be detected by measuring the range that includes the time when the potential difference between output terminal 91 and output terminal 92 is at its maximum.

[0081] Furthermore, according to the semiconductor device 1 of the first embodiment, in the peak frequency detection circuit 70, the differential low-pass filter 71 reduces high-frequency noise components superimposed on the amplified signals DOXP and DOXN by modulating the test signal, the comparator 72 converts the output voltage of the differential low-pass filter 71 into data DT, and the peak time measurement circuit 73 can easily perform highly accurate measurements.

[0082] Furthermore, according to the semiconductor device 1 of the first embodiment, the impedance R of the sound reproduction device 3 sp Since this does not depend on the magnitude of the amplified signals DOXP and DOXN, in the test mode, the sound playback device 3 can detect the frequency range F0 that includes the peak frequency f0 while playing back a minute sound that is inaudible to the human ear.

[0083] 1-2. Second Embodiment Hereinafter, regarding the semiconductor device 1 of the second embodiment, the same reference numerals will be used for components similar to those in the first embodiment, descriptions similar to those in the first embodiment will be omitted or simplified, and the main differences from the first embodiment will be described.

[0084] The configuration of the semiconductor device 1 in the second embodiment is the same as in Figure 1, so its illustration is omitted. In the semiconductor device 1 of the second embodiment, the test signal generated by the test signal generation circuit 60 is different from that of the first embodiment.

[0085] In this embodiment, the test signal generation circuit 60 generates modulated signals TP and TN by modulating a test signal obtained in the test mode by changing the frequency in a first frequency band F1 included in a preset frequency band, and then changing the frequency in a second frequency band F2 other than the first frequency band F1 included in the preset frequency band. The first frequency band F1 includes the peak frequency f0 when the sound reproduction device 3 is functioning normally. The first frequency band F1 and the second frequency band F2 may be arbitrarily set by the microcontroller unit 2. Similar to the first embodiment, the test signal generation circuit 60 generates pulse-width modulated signals TP and TN by pulse-width modulating the test signal. The pulse-width modulation method by the test signal generation circuit 60 is the same as the pulse-width modulation method by the pulse-width modulation circuit 33.

[0086] The other configurations and functions of the semiconductor device 1 in the second embodiment are the same as those in the first embodiment, so their description will be omitted.

[0087] Figure 14 shows the generation and start time of the test signal by the test circuit 110 in the second embodiment. t start and end time t stop This figure shows an example of measurement. Figure 14 shows an example where the impedance characteristic of the sound reproduction device 3 is G1 in Figure 5. In the example in Figure 14, the test signal generation circuit 60 maintains the amplitude of the test signal at a constant voltage V1 while gradually changing the frequency of the test signal in seven different frequencies included in the frequency band from 10 Hz to 3 kHz. Specifically, the test signal generation circuit 60 gradually changes the frequency of the test signal in four different frequencies included in the first frequency band F1, and then gradually changes it in three different frequencies included in the second frequency band F2, which is not included in the first frequency band F1. By gradually changing the frequency of the test signal in this way, the circuit size of the test signal generation circuit 60 and the peak frequency detection circuit 70 can be reduced.

[0088] In the example shown in Figure 14, the amplitude of the output voltage V' of the differential low-pass filter 71 is maximum at the peak frequency f0 included in the first frequency band F1. The maximum value of the data DT[1:0] output by the comparator 72 is 10, and the peak time measurement circuit 73 determines the variable i when the data DT[1:0] first becomes 10 at the start time t start The measurement is performed, and the variable i is defined as the point at which the data DT[1:0] finally becomes 10 at the end time t. stop Measure it as follows.

[0089] Start time t in the example in Figure 14 start and end time t stop This is the start time t in Figure 11. start and end time t stop This is an earlier time. In other words, the peak frequency detection circuit 70 in the second embodiment can detect the frequency range F0 in a shorter time than in the first embodiment. Note that in the example in Figure 14, the test signal generation circuit 60 changes the frequency of the test signal in steps, so the frequency range F0 includes only the peak frequency f0.

[0090] If the peak frequency detection circuit 70 detects a frequency range F0 in the first frequency band F1, the test signal generation circuit 60 and the peak frequency detection circuit 70 may stop operating and output a test completion interrupt signal to the microcontroller unit 2. In that case, the microcontroller unit 2 receives the test completion interrupt signal, obtains the frequency range F0 via the communication interface circuit 10, and can determine whether or not there is a malfunction in the sound playback device 3 and the mode of the malfunction based on the frequency range F0.

[0091] In the second embodiment, terminal P1 of the sound reproduction device 3 is an example of a "first terminal," and terminal P2 of the sound reproduction device 3 is an example of a "second terminal." Also, output terminal 91 of the semiconductor device 1 is an example of a "first output terminal," and output terminal 92 of the semiconductor device 1 is an example of a "second output terminal." Furthermore, pulse width modulated signal DOP is an example of a "first modulated signal," and pulse width modulated signal DON is an example of a "second modulated signal." Also, pulse width modulated signal TP is an example of a "third modulated signal," and pulse width modulated signal TN is an example of a "fourth modulated signal." Furthermore, amplified signal DOXP, obtained by amplified pulse width modulated signal DOP, is an example of a "first amplified signal," and amplified signal DOXN, obtained by amplified pulse width modulated signal DON, is an example of a "second amplified signal." Furthermore, amplified signal DOXP, obtained by amplified pulse width modulated signal TP, is an example of a "third amplified signal," and amplified signal DOXN, obtained by amplified pulse width modulated signal TN, is an example of a "fourth amplified signal." Furthermore, the Class D amplifier 51P is an example of a "first amplification circuit," and the Class D amplifier 51N is an example of a "second amplification circuit." Also, the normal operating mode is an example of a "first operating mode," and the test mode is an example of a "second operating mode."

[0092] The semiconductor device 1 of the second embodiment is configured to output sound to one sound playback device 3, but it may also be configured to output sound to multiple sound playback devices.

[0093] The semiconductor device 1 of the second embodiment described above provides the same effects as the semiconductor device 1 of the first embodiment. Furthermore, the semiconductor device 1 of the second embodiment prioritizes the first frequency band F1 which includes the peak frequency f0 when the sound reproduction device 3 is functioning normally, and the test signal By changing the frequency, the frequency range F0 containing the peak frequency f0 can be detected in a short amount of time.

[0094] 1-3. Third Embodiment Hereinafter, with respect to the semiconductor device 1 of the third embodiment, the same reference numerals will be used for components similar to those in the first or second embodiment, descriptions similar to those in the first or second embodiment will be omitted or simplified, and the differences from the first and second embodiments will be described primarily.

[0095] The configuration of the semiconductor device 1 in the third embodiment is the same as in Figure 1, so its illustration is omitted. In the semiconductor device 1 of the third embodiment, the test signal generated by the test signal generation circuit 60 is different from that of the first and second embodiments.

[0096] In this embodiment, the test signal generation circuit 60 generates modulated signals TP and TN by modulating a test signal whose frequency is simultaneously changed in two different first frequency bands F1 and F2 included in a preset frequency band, in the test mode. The first frequency band F1 may include the peak frequency f0 when the sound reproduction device 3 is functioning normally. The first frequency band F1 and the second frequency band F2 may be arbitrarily set by the microcontroller unit 2. Similar to the first embodiment, the test signal generation circuit 60 generates pulse-width modulated signals TP and TN by pulse-width modulating the test signal. The pulse-width modulation method used by the test signal generation circuit 60 is the same as the pulse-width modulation method used by the pulse-width modulation circuit 33.

[0097] The other configurations and functions of the semiconductor device 1 in the third embodiment are the same as those in the first embodiment, so their description will be omitted.

[0098] FIG. 15 shows an example of generation of a test signal by the inspection circuit 110 and measurement of start time t start and end time t stop in the third embodiment. FIG. 15 shows an example when the impedance characteristic of the sound playback device 3 is G1 in FIG. 5. In the example of FIG. 15, the test signal generation circuit 60 simultaneously and stepwise changes the frequency of the test signal in the first frequency band F1 and the second frequency band F2 included in the frequency band of 10 Hz or more and 3 kHz or less while maintaining the amplitude of the test signal at a constant voltage V1. Specifically, the test signal generation circuit 60 stepwise changes the frequency of the test signal at four frequencies included in the first frequency band F1 in parallel with stepwise changing the frequency of the test signal at three frequencies included in the second frequency band F2 other than the first frequency band F1. By thus stepwise changing the frequency of the test signal, the circuit scale of the test signal generation circuit 60 and the peak frequency detection circuit 70 can be reduced.

[0099] In the example of FIG. 15, the amplitude of the output voltage V' of the differential low-pass filter 71 becomes maximum at the peak frequency f0 included in the first frequency band F1. The maximum value of the data DT[1:0] output by the comparator 72 is 10, and the peak time measurement circuit 73 measures the variable i when the data DT[1:0] first becomes 10 as the start time t start and measures the variable i when the data DT[1:0 last becomes 10 as the end time t stop .

[0100] The start time t start [[ID=2,0]]and end time t[[ID=,21]] stop in the example of FIG. 15 are earlier times than the start time t start and end time t stop in FIG. 11. That is, the peak frequency detection circuit 70 in the third embodiment has a shorter time for changing the frequency of the test signal and a shorter detection time for the frequency range F0 compared to the first embodiment. In the example of FIG. 15, since the test signal generation circuit 60 stepwise changes the frequency of the test signal, only the peak frequency f0 is included in the frequency range F0.

[0101] The microcontrol unit 2 can acquire the frequency range F0 via the communication interface circuit 10 and determine whether or not there is a malfunction in the sound playback device 3 and the mode of the malfunction based on the frequency range F0.

[0102] In the third embodiment, terminal P1 of the sound reproduction device 3 is an example of a "first terminal," and terminal P2 of the sound reproduction device 3 is an example of a "second terminal." Also, output terminal 91 of the semiconductor device 1 is an example of a "first output terminal," and output terminal 92 of the semiconductor device 1 is an example of a "second output terminal." Furthermore, pulse width modulated signal DOP is an example of a "first modulated signal," and pulse width modulated signal DON is an example of a "second modulated signal." Also, pulse width modulated signal TP is an example of a "third modulated signal," and pulse width modulated signal TN is an example of a "fourth modulated signal." Furthermore, amplified signal DOXP, obtained by amplified pulse width modulated signal DOP, is an example of a "first amplified signal," and amplified signal DOXN, obtained by amplified pulse width modulated signal DON, is an example of a "second amplified signal." Furthermore, amplified signal DOXP, obtained by amplified pulse width modulated signal TP, is an example of a "third amplified signal," and amplified signal DOXN, obtained by amplified pulse width modulated signal TN, is an example of a "fourth amplified signal." Furthermore, the Class D amplifier 51P is an example of a "first amplification circuit," and the Class D amplifier 51N is an example of a "second amplification circuit." Also, the normal operating mode is an example of a "first operating mode," and the test mode is an example of a "second operating mode."

[0103] The semiconductor device 1 of the third embodiment is configured to output sound to one sound playback device 3, but it may also be configured to output sound to multiple sound playback devices.

[0104] The semiconductor device 1 of the third embodiment described above provides the same effects as the semiconductor device 1 of the first or second embodiment. Furthermore, the semiconductor device 1 of the third embodiment generates test signals having multiple frequencies simultaneously, thereby shortening the time required to change the frequency of the test signals. This allows for the detection of the frequency range F0, which includes the peak frequency f0, in a shorter time.

[0105] 1-4. Fourth Embodiment Hereinafter, regarding the semiconductor device 1 of the fourth embodiment, the same reference numerals will be used for components similar to those in any of the first to third embodiments, descriptions similar to those in any of the first to third embodiments will be omitted or simplified, and the description will mainly focus on aspects that differ from any of the first to third embodiments.

[0106] Figure 16 shows an example configuration of the semiconductor device 1 of the fourth embodiment. As shown in Figure 16, the semiconductor device 1 of the fourth embodiment differs from the semiconductor device 1 of the first embodiment shown in Figure 1 in that it includes an amplification circuit 50a, a fault detection circuit 120, and six switches 41a, 42a, 43, 44, 121, and 122.

[0107] Switch 43 outputs a pulse width modulated signal DOP to either switch 41 or switch 41a in response to a control signal output from the fault detection circuit 120. Switch 44 also outputs a pulse width modulated signal DON to either switch 42 or switch 42a in response to a control signal output from the fault detection circuit 120.

[0108] Switch 41a outputs either the signal from switch 43 or the pulse width modulated signal TP to the Class D amplifier 51Pa of the amplification circuit 50a, depending on the control signal output from the communication interface circuit 10. Specifically, when switch 43 outputs the pulse width modulated signal DOP to switch 41a, switch 41a outputs the pulse width modulated signal DOP to the Class D amplifier 51Pa when the operating mode of the semiconductor device 1 is the normal operating mode. Also, when the operating mode of the semiconductor device 1 is the test mode, switch 41a outputs the Class D amplifier 51Pa. A pulse width modulated signal TP is output to 51 Pa.

[0109] Furthermore, switch 42a outputs either the signal from switch 44 or the pulse width modulated signal TN to the Class D amplifier 51Na of the amplification circuit 50a, depending on the control signal output from the communication interface circuit 10. Specifically, when switch 44 outputs the pulse width modulated signal DON to switch 42a, switch 42a outputs the pulse width modulated signal DON to the Class D amplifier 51Na when the operating mode of the semiconductor device 1 is the normal operating mode. Also, when the operating mode of the semiconductor device 1 is the test mode, switch 42a outputs the pulse width modulated signal TN to the Class D amplifier 51Na.

[0110] When switches 43 and 44 output pulse width modulated signals DOP and DON to switches 41a and 42a, the amplification circuit 50a, in normal operation mode, receives the pulse width modulated signals DOP and DON as input and outputs the amplified signals DOXPa and DOXNa, which are obtained by amplifying the pulse width modulated signals DOP and DON, to the output terminals 93 and 94 of the semiconductor device 1. In addition, the amplification circuit 50a, in test mode, receives the pulse width modulated signals TP and TN as input and outputs the amplified signals DOXPa and DOXNa, which are obtained by amplifying the pulse width modulated signals TP and TN, to the output terminals 93 and 94 of the semiconductor device 1.

[0111] In this embodiment, the amplification circuit 50a includes two Class D amplifiers 51Pa and 51Na. In normal operation mode, Class D amplifier 51Pa outputs an amplified signal DOXPa, obtained by amplifying the pulse width modulated signal DOP, to output terminal 93, and in test mode, it outputs an amplified signal DOXPa, obtained by amplifying the pulse width modulated signal TP, to output terminal 9 3 Outputs to the following. The Class D amplifier 51Na operates normally. In the operation mode, an amplified signal DOXNa, obtained by amplifying the pulse width modulated signal DON, is output to output terminal 94. In the test mode, an amplified signal DOXNa, obtained by amplifying the pulse width modulated signal TN, is output to output terminal 94. Output terminal 93 is connected to terminal P1a of the sound playback device 3a, and output terminal 94 is connected to terminal P2a of the sound playback device 3a. The sound playback device 3a then reproduces a sound of a magnitude corresponding to the voltage difference between the amplified signal DOXP and the amplified signal DOXN.

[0112] The fault detection circuit 120 detects a fault in the sound playback device 3 based on the frequency range F0 detected by the peak frequency detection circuit 70. Specifically, the fault detection circuit 120 determines that the sound playback device 3 is functioning normally if the lower limit of the frequency range F0 is included in the first reference range and the upper limit of the frequency range F0 is included in the second reference range, and determines that it is faulty otherwise. For example, the communication interface circuit 10 may set the first and second reference ranges by receiving a command transmitted from the microcontroller unit 2.

[0113] Then, when the fault detection circuit 120 detects a fault in the sound playback device 3, the amplification circuit 50a amplifies the modulation signals DOP and DON respectively to produce an amplified signal DO X Pa,DO X Na is output to sound playback device 3a, which is different from sound playback device 3. Specifically, if the fault detection circuit 120 detects a fault in sound playback device 3, a pulse is generated. width The modulated signal DOP is amplified by the Class D amplifier 51 of the amplification circuit 50a. P Switch 43 is switched so that the output is output to a, and pulse width Modulated signal DON is amplified by a Class D amplifier 50a 1N Switch 44 is switched so that the output is output to a. This stops the sound output from the sound playback device 3 and also pulses width The modulated signals DON and DOP are amplified into the amplified signal DOXP. a ,DOXN a The signal is output to output terminals 93 and 94, and sound is output from the sound playback device 3a. For example, the sound playback device 3a may be a speaker or a buzzer. The sound output from the sound playback device 3a may be, for example, a voice that mimics a person speaking, or various sounds such as mechanical warning sounds or sound effects.

[0114] Switch 121 connects one end of switch 81 to either output terminal 91 or output terminal 93 of semiconductor device 1, in accordance with the control signal output from fault detection circuit 120. In response to the control signal output from the fault detection circuit 120, switch 122 connects one end of switch 82 to either output terminal 92 or output terminal 94 of semiconductor device 1.

[0115] Switch 81 switches between electrically connecting or disconnecting the output terminals 91 and 93 of the semiconductor device 1 and the peak frequency detection circuit 70, according to the control signal output from the communication interface circuit 10. When the semiconductor device 1 is in normal operation mode, switch 81 electrically disconnects the output terminals 91 and 93 and the peak frequency detection circuit 70. When the semiconductor device 1 is in test mode, switch 81 electrically connects either one of the output terminals 91 or 93 to the peak frequency detection circuit 70 via switch 121.

[0116] Furthermore, switch 82 switches between electrically connecting either one of the output terminals 92 or 94 of the semiconductor device 1 to the peak frequency detection circuit 70, or disconnecting the output terminals 92 or 94 of the semiconductor device 1 to the peak frequency detection circuit 70, depending on the control signal output from the communication interface circuit 10. Specifically, when the operating mode of the semiconductor device 1 is the normal operating mode, switch 82 electrically disconnects the output terminals 92 or 94 to the peak frequency detection circuit 70, and when the operating mode of the semiconductor device 1 is the test mode, it electrically connects either one of the output terminals 92 or 94 to the peak frequency detection circuit 70 via switch 122.

[0117] Until the fault detection circuit 120 detects a fault in the sound playback device 3, the peak frequency detection circuit 70 measures the potential difference between output terminal 91 and output terminal 92 in inspection mode and detects the frequency range F0 that includes the peak frequency f0, which is the frequency of the test signal at which the impedance of the sound playback device 3 peaks. After the fault detection circuit 120 detects a fault in the sound playback device 3, the peak frequency detection circuit 70 measures the potential difference between output terminal 92 and output terminal 94 in inspection mode and detects the frequency range F0 that includes the peak frequency f0, which is the frequency of the test signal at which the impedance of the sound playback device 3a peaks.

[0118] FIG. 17 is a flowchart showing an example of the procedure of the process by the failure detection circuit 120.

[0119] As shown in FIG. 17, first, in step S11, the failure detection circuit 120 determines whether or not the start time t measured by the peak time measurement circuit 73 is included in the first reference range of t1 or more and t2 or less. Also, in step S12, the failure detection circuit 120 determines whether or not the end time t measured by the peak time measurement circuit 73 is included in the second reference range of t3 or more and t4 or less. As described above, for example, the start time t start corresponds to the lower limit of the frequency range F0, and the end time t stop corresponds to the upper limit of the frequency range F0. start is included in the first reference range, and the end time t stop is included in the second reference range, in step S13, the failure detection circuit 120 controls the switches 43 and 44 to output the amplified signals DOXP and DOXN obtained by amplifying the pulse width modulation signals DOP and DON to the sound playback device 3. On the other hand, when the start time t

[0120] is not included in the first reference range, or the end time t start is not included in the second reference range, in step S14, the failure detection circuit 120 controls the switches 43 and 44 to output the amplified signals DOXPa and DOXNa obtained by amplifying the pulse width modulation signals DOP and DON to the sound playback device 3a. stop is included in the first reference range, and the end time t start is included in the second reference range, in step S13, the failure detection circuit 120 controls the switches 43 and 44 to output the amplified signals DOXP and DOXN obtained by amplifying the pulse width modulation signals DOP and DON to the sound playback device 3. On the other hand, when the start time t stop is not included in the first reference range, or the end time t

[0121] The other configurations of the semiconductor device 1 of the fourth embodiment are the same as those in FIG. 1, and thus the description thereof is omitted.

[0122] In the fourth embodiment, the terminal P1 of the sound playback device 3 is an example of the "first terminal", and the terminal P2 of the sound playback device 3 is an example of the "second terminal". Also, the output terminal 9 of the semiconductor device 1 1 is an example of a "first output terminal," and output terminal 92 of semiconductor device 1 is an example of a "second output terminal." Also, pulse width modulated signal DOP is an example of a "first modulated signal," and pulse width modulated signal DON is an example of a "second modulated signal." Also, pulse width modulated signal TP is an example of a "third modulated signal," and pulse width modulated signal TN is an example of a "fourth modulated signal." Furthermore, amplified signal DOXP, obtained by amplifying pulse width modulated signal DOP, is an example of a "first amplified signal," and amplified signal DOXN, obtained by amplifying pulse width modulated signal DON, is an example of a "second amplified signal." Furthermore, amplified signal DOXP, obtained by amplifying pulse width modulated signal TP, is an example of a "third amplified signal," and amplified signal DOXN, obtained by amplifying pulse width modulated signal TN, is an example of a "fourth amplified signal." Also, Class D amplifier 51P is an example of a "first amplified circuit," and Class D amplifier 51N is an example of a "second amplified circuit." Furthermore, the normal operating mode is an example of the "first operating mode," and the inspection mode is an example of the "second operating mode."

[0123] The semiconductor device 1 of the fourth embodiment is configured to output sound to two sound reproduction devices 3, 3a, but it may also be configured to output sound to three or more sound reproduction devices.

[0124] The semiconductor device 1 of the fourth embodiment described above provides the same effects as any of the semiconductor device 1 of the first to third embodiments. Furthermore, in the semiconductor device 1 of the fourth embodiment, the fault detection circuit 120 detects a fault in the sound reproduction device 3, and even if the sound reproduction device 3 fails, the sound reproduction device 3a can still generate normal sound.

[0125] 1-5. Variations The present invention is not limited to this embodiment, and various modifications can be implemented within the scope of the gist of the present invention.

[0126] For example, in each of the embodiments described above, an example was given in which, while a system comprising a semiconductor device 1, a microcontrol unit 2, and a sound reproduction device 3 is in operation, the microcontrol unit 2 determines whether or not there is a malfunction in the sound reproduction device 3 based on the frequency range F0 detected by the semiconductor device 1. However, the cases in which the semiconductor device 1 detects the frequency range F0 are not limited to this. For example, in the inspection process before the system is put into operation, the semiconductor device 1 may transmit the detected frequency range F0 to an inspection device, and the inspection device may check whether or not the sound reproduction device 3 is functioning normally based on the frequency range F0.

[0127] Furthermore, for example, in each of the above embodiments, a memory 20 storing sound source data 21-1 to 21-n is built into the semiconductor device 1. However, instead of memory 20, an external memory storing sound source data 21-1 to 21-n may be connected to the semiconductor device 1, and the semiconductor device 1 may read sound source data 21-i, which is the sound source signal DI, from the external memory. Alternatively, instead of memory 20, a microcontroller unit 2 may have a built-in memory storing sound source data 21-1 to 21-n, and the microcontroller unit 2 may read sound source data 21-i from the memory and transmit it to the semiconductor device 1 as the sound source signal DI.

[0128] Furthermore, in the embodiments described above, examples of modulation methods by the pulse width modulation circuit 33 were given in Figures 2 to 4, but other modulation methods may also be used. For example, the pulse width modulation for generating the pulse width modulation signal DOP may be the same as in Figure 2, and the pulse width modulation for generating the pulse width modulation signal DON may be the method shown in Figure 18. In the example in Figure 18, the pulse width modulation signal DON is a signal obtained by inverting the logic level of the pulse width modulation signal DOP shown in Figure 2, and the larger the value of the sigma-delta modulation signal DS, the shorter the high-level time. For example, when the sigma-delta modulation signal DS is "-7" in decimal, that is, "1001" in binary, the pulse width modulation signal DON is in one interval T 1 isThe signal is low level, with 15 sections T2 to T16 being high level. Also, for example, when the sigma-delta modulated signal DS is the decimal number "0", i.e., the binary number "0000", the pulse-width modulated signal DON has 8 sections T1 to T8 being low level and 8 sections T9 to T16 being high level. Also, for example, when the sigma-delta modulated signal DS is the decimal number "7", i.e., the binary number "0111", the pulse-width modulated signal DON has 15 sections T1 to T15 being low level and one section T16 being high level. Therefore, for example, when the sigma-delta modulated signal DS is the decimal numbers "-7", "0", and "7", the difference between the pulse-width modulated signal DOP and the pulse-width modulated signal DON is as shown in Figure 19.

[0129] 2.Electronic equipment Figure 20 is a functional block diagram showing an example of the configuration of the electronic device of this embodiment using the semiconductor device 1 of this embodiment.

[0130] As shown in Figure 20, the electronic device 300 of this embodiment includes a semiconductor device 1, m sound reproduction devices 3-1 to 3-m, a processing unit 310, an operation unit 320, a storage unit 330, and a display unit 340. Note that the electronic device 300 of this embodiment may have some of the components shown in Figure 20 omitted or modified, or other components added.

[0131] The processing unit 310 performs control processing for various parts of the electronic device 300 and various data processing. For example, the processing unit 310 sends various commands to the semiconductor device 1 to control its operation. The processing unit 310 also performs various processing in response to operation signals from the operation unit 320, and processes to send display signals to display various information on the display unit 340. For example, the processing unit 310 may be the aforementioned microcontroller unit 2.

[0132] The operation unit 320 is an input device consisting of operation keys, button switches, etc., and outputs operation signals to the processing unit 310 in response to user operations.

[0133] The storage unit 330 stores programs, data, and other information for the processing unit 310 to perform various calculation and control processes. The storage unit 330 can be implemented, for example, by a hard disk, flexible disk, MO, MT, various types of memory, CD-ROM, or DVD-ROM.

[0134] The display unit 340 is a display device composed of an LCD or the like, and displays various information based on the input display signal. LCD stands for Liquid Crystal Display. The display unit 340 may also be provided with a touch panel that functions as an operation unit 320.

[0135] The semiconductor device 1 generates an audio signal based on various commands transmitted from the processing unit 310 and outputs it to the sound playback device 3-1. The sound playback device 3-1 corresponds to the sound playback device 3 described above. The semiconductor device 1 may also inspect the sound playback device 3-1 and transmit the inspection results to the processing unit 310, which may determine whether the sound playback device 3-1 is faulty and what the fault mode is. If the sound playback device 3-1 is faulty, the processing unit 310 may, for example, play an audio message to one of the sound playback devices 3-2 to 3-m to notify them that the sound playback device 3-1 is faulty, or it may switch the output destination of the audio signal from the sound playback device 3-1 to one of the sound playback devices 3-2 to 3-m. Alternatively, if the semiconductor device 1 detects a fault in the sound playback device 3-1, it may switch the output destination of the audio signal from the sound playback device 3-1 to the sound playback device 3-2. The sound playback device 3-2 corresponds to the sound playback device 3a described above.

[0136] Since the semiconductor device 1 can generate the signals necessary to detect a malfunction in the sound reproduction device 3-1, a highly reliable electronic device 300 can be realized.

[0137] Such electronic devices 300 can include a variety of electronic devices, such as warning devices, rice cookers, induction cooktops, vacuum cleaners, washing machines and other household electrical appliances, electronic clocks, personal computers such as mobile, laptop, and tablet types, mobile terminals such as smartphones and mobile phones, digital cameras, inkjet printers and other inkjet ejection devices, storage area network equipment such as routers and switches, local area network equipment, equipment for mobile terminal base stations, televisions, video cameras, video recorders, car navigation systems, real-time clock devices, pagers, electronic organizers, electronic dictionaries, calculators, electronic game devices, game controllers, word processors, workstations, video phones, security television monitors, electronic binoculars, POS terminals, electronic thermometers, blood pressure monitors, blood glucose meters, electrocardiogram measuring devices, ultrasound diagnostic equipment, medical devices such as electronic endoscopes, fish finders, various measuring instruments, instruments for vehicles, aircraft, ships, flight simulators, head-mounted displays, motion trace, motion tracking, motion controllers, pedestrian autonomous navigation systems, and the like.

[0138] Figure 21 shows an example of the configuration of a warning device 300A, which is an example of an electronic device 300. In Figure 21, the same components as in Figure 20 are denoted by the same reference numerals. The warning device 300A shown in Figure 21 is mounted on a vehicle 400. Sound playback device 3-1 is a speaker, and sound playback devices 3-2 to 3-5 are buzzers, respectively.

[0139] The processing unit 310 transmits various sound playback commands, etc., to the semiconductor device 1 based on signals from various sensors (not shown). These sounds include, for example, voice-like sounds and warning sounds to notify of abnormalities such as brakes, engine oil, power steering, and brake override system malfunctions, driving with a door ajar, erratic driving, driving with the parking brake not released, not wearing a seatbelt, and approaching a preceding vehicle, as well as sound effects to notify of turn signals, hazard lights, and reversing.

[0140] The semiconductor device 1 generates an audio signal based on a portion of multiple audio source data corresponding to various sounds, based on a command from the processing unit 310, and outputs it to the sound playback device 3-1. The semiconductor device 1 may also inspect the sound playback device 3-1 and send the inspection results to the processing unit 310, which may determine whether the sound playback device 3-1 is faulty and what the fault mode is. If the sound playback device 3-1 is faulty, the processing unit 310 may, for example, play an audio message to one of the sound playback devices 3-2 to 3-5 to notify them that the sound playback device 3-1 is faulty, or it may switch the output destination of the audio signal from the sound playback device 3-1 to one of the sound playback devices 3-2 to 3-5. Alternatively, if the semiconductor device 1 detects a fault in the sound playback device 3-1, it may switch the output destination of the audio signal from the sound playback device 3-1 to the sound playback device 3-2.

[0141] Since the semiconductor device 1 can generate the signal necessary to detect a malfunction in the sound reproduction device 3-1, a highly reliable warning device 300A can be realized.

[0142] The present invention is not limited to this embodiment, and various modifications can be implemented within the scope of the gist of the present invention.

[0143] The embodiments and variations described above are examples only and are not limited thereto. For example, each embodiment and each variation can be combined as appropriate.

[0144] The present invention includes configurations substantially identical to those described in the embodiments, for example, configurations with the same function, method, and results, or configurations with the same purpose and effect. Furthermore, the present invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Furthermore, the present invention includes configurations that produce the same effects or achieve the same purpose as those described in the embodiments. Furthermore, the present invention includes configurations that add known technology to the configurations described in the embodiments. Includes.

[0145] The following can be derived from the embodiments and modifications described above.

[0146] One aspect of a semiconductor device is: The first output terminal is connected to the first terminal of the sound playback device, A second output terminal connected to the second terminal of the sound playback device, A modulation circuit that modulates a signal based on a sound source signal and outputs a first modulated signal and a second modulated signal, In the first operating mode, a first amplification circuit outputs a first amplified signal obtained by amplifying the first modulated signal to the first output terminal, In the first operating mode, a second amplification circuit outputs a second amplified signal, obtained by amplifying the second modulated signal, to the second output terminal, In the second operating mode, a test signal generation circuit generates a third modulated signal and a fourth modulated signal by modulating a test signal whose frequency is varied within a preset frequency band, In the second operating mode, a peak frequency detection circuit measures the potential difference between the first output terminal and the second output terminal and detects a frequency range that includes the peak frequency, which is the frequency of the test signal at which the impedance of the sound reproduction device peaks. Equipped with, In the second operating mode, the first amplification circuit outputs the third amplified signal, obtained by amplifying the third modulated signal, to the second output terminal. In the second operating mode, the second amplification circuit outputs the fourth amplified signal, obtained by amplifying the fourth modulated signal, to the second output terminal. The first amplification circuit has a plurality of inverter circuits, each of which is connected to the first output terminal. The second amplification circuit has a plurality of inverter circuits, each of which is connected to the second output terminal. In the first operating mode, The first modulation signal is input to each input terminal of the plurality of inverter circuits of the first amplification circuit, and the second modulation signal is input to each input terminal of the plurality of inverter circuits of the second amplification circuit. In the second operating mode, The third modulation signal is input to the input terminals of some of the inverter circuits of the plurality of inverter circuits of the first amplification circuit, and the output terminals of other of the inverter circuits of the plurality of inverter circuits of the first amplification circuit become high impedance. The fourth modulation signal is input to the input terminals of some of the inverter circuits of the plurality of inverter circuits of the second amplification circuit, and the output terminals of other of the inverter circuits of the plurality of inverter circuits of the second amplification circuit become high impedance.

[0147] According to this semiconductor device, in the first operating mode, the first amplifier circuit amplifies the first modulated signal based on the sound source signal and outputs the first amplified signal to the first output terminal, while the second amplifier circuit amplifies the second modulated signal based on the sound source signal and outputs the second amplified signal to the second output terminal, thereby enabling the sound reproduction device to reproduce sound. Specifically, in the first operating mode, multiple inverter circuits of the first amplifier circuit are connected in parallel, as are multiple inverter circuits of the second amplifier circuit. As a result, the on-resistance of the first amplifier circuit and the on-resistance of the second amplifier circuit become sufficiently smaller than the impedance of the sound reproduction device, enabling the sound reproduction device to reproduce sound properly.

[0148] On the other hand, in the second operating mode, the first amplification circuit amplifies the third modulated signal based on the test signal and outputs the third amplified signal to the first output terminal, while the second amplification circuit amplifies the test signal By outputting the fourth amplified signal, obtained by amplifying the fourth modulated signal, to the second output terminal, the peak frequency detection circuit can measure the potential difference between the first and second output terminals and detect the frequency range that includes the peak frequency at which the impedance of the sound reproduction device peaks. Specifically, in the second operating mode, some outputs of the multiple inverter circuits of the first amplification circuit become high impedance, and some outputs of the multiple inverter circuits of the second amplification circuit also become high impedance. As a result, the on-resistance of the first amplification circuit and the on-resistance of the second amplification circuit increases, and the amount of change in the potential difference between the first and second output terminals due to the change in the impedance of the sound reproduction device becomes larger, so that the peak frequency detection circuit can accurately detect the frequency range that includes the peak frequency. Therefore, for example, an external device can estimate the impedance characteristics of the sound reproduction device based on the frequency range that includes the peak frequency and determine whether or not there is a malfunction in the sound reproduction device and the mode of the malfunction.

[0149] In other words, in this semiconductor device, the first and second amplification circuits are used for both generating the first and second amplification signals for generating sound in the sound reproduction device in the first operating mode, and generating the third and fourth amplification signals necessary for detecting the frequency range containing the peak frequency in the second operating mode. Furthermore, in the second operating mode, the change in potential difference between the first and second output terminals due to the change in impedance of the sound reproduction device is large, so the size of the peak frequency detection circuit is reduced. Therefore, with this semiconductor device, the signals necessary to detect a malfunction in the sound reproduction device can be generated with a small circuit.

[0150] In one embodiment of the semiconductor device, The peak frequency detection circuit may detect the frequency range by measuring a range that includes the time when the potential difference between the first output terminal and the second output terminal is maximum in the second operating mode.

[0151] According to this semiconductor device, when the impedance of the sound reproduction device reaches its peak, the potential difference between the first output terminal and the second output terminal also reaches its peak. Therefore, by measuring the range that includes the time when the potential difference between the first output terminal and the second output terminal is at its maximum, the frequency range that includes the peak frequency can be detected.

[0152] In one embodiment of the semiconductor device, The aforementioned peak frequency detection circuit is A differential low-pass filter to which the voltage of the first output terminal and the voltage of the second output terminal are input, A comparator that compares the output voltage of the differential low-pass filter with at least one threshold voltage, A peak time measurement circuit that measures a range including the time when the potential difference between the first output terminal and the second output terminal is maximum, based on the output signal of the comparator, It may include.

[0153] According to this semiconductor device, the differential low-pass filter reduces high-frequency noise components superimposed on the third and fourth amplified signals by modulating the test signal, the comparator converts the output voltage of the differential low-pass filter into a digital value, and the peak time measurement circuit can easily perform highly accurate measurements.

[0154] In one embodiment of the semiconductor device, The cutoff frequency of the differential low-pass filter may be higher than the maximum frequency of the frequency band.

[0155] According to this semiconductor device, the cutoff frequency of the differential low-pass filter is the test signal Since the frequency is higher than the maximum frequency of the frequency band being varied, the differential low-pass filter does not attenuate the frequency components included in that frequency band, allowing the peak time measurement circuit to perform highly accurate measurements.

[0156] In one embodiment of the semiconductor device, In the second operating mode, the test signal generation circuit modulates the test signal, which has been modified in a first frequency band included in the frequency band and then in a second frequency band other than the first frequency band included in the frequency band, to generate the third modulated signal and the fourth modulated signal. The first frequency band may include the peak frequency when the sound reproduction device is functioning normally.

[0157] This semiconductor device prioritizes the first frequency band containing the peak frequency when the sound playback device is functioning correctly, and changes the frequency of the test signal accordingly, allowing the frequency range containing the peak frequency to be detected in a short time.

[0158] In one embodiment of the semiconductor device, In the second operating mode, the test signal generation circuit may generate the third modulated signal and the fourth modulated signal by modulating the test signal, whose frequency is simultaneously changed in two different first and second frequency bands included in the frequency band.

[0159] This semiconductor device allows for the simultaneous generation of test signals with multiple frequencies, thereby shortening the time required to change the frequency of the test signals. This enables the detection of a frequency range containing a peak frequency in a short amount of time.

[0160] One embodiment of the semiconductor device is, The system includes a fault detection circuit that detects a malfunction in the sound reproduction device based on the frequency range detected by the peak frequency detection circuit, The fault detection circuit may, when it detects a fault in the sound playback device, output an amplified signal of the first modulation signal and an amplified signal of the second modulation signal to a sound playback device other than the sound playback device.

[0161] This semiconductor device allows for the generation of normal sound from other sound playback devices even if one sound playback device malfunctions.

[0162] One aspect of electronic equipment is, One embodiment of the semiconductor device, The sound reproduction device and, It is equipped with.

[0163] This electronic device includes a semiconductor device that can generate the necessary signals to detect malfunctions in the sound playback device, thereby improving its reliability. [Explanation of Symbols]

[0164] 1...Semiconductor device, 2...Microcontrol unit, 3,3a,3-1~3-m...Sound playback device, 10...Communication interface circuit, 20...Memory, 21-1~21-n...Sound source data, 30...Modulation circuit, 31...Digital filter, 32...Sigma-delta modulation circuit, 33...Pulse width modulation circuit, 41,41a...Switch, 42,42a...Switch, 43...Switch, 44...Switch, 50,50a...Amplification circuit, 51P,51N...Class D amplifier, 60...Test signal generation circuit, 70...Peak frequency detection circuit, 71...Differential low-pass filter, 7 2... Comparator, 73... Peak time measurement circuit, 81... Switch, 82... Switch, 91... Output terminal, 92... Output terminal, 93... Output terminal, 94... Output terminal, 100... Sound source playback circuit, 110... Test circuit, 120... Fault detection circuit, 121... Switch, 122... Switch, 201-1~201-n... Inverter circuit, 201-1~201-n... Inverter circuit, 202-1~202-n... Inverter circuit, 211...Operational amplifier, 212,213,214...Resistor, 215...Capacitor, 216...Resistor, 217...Capacitor, 218...Resistor, 219...Capacitor, 221~228...Resistor, 231~237...Comparator, 241~246...Logic element, 250...Encoder, 300...Electronic device, 300A...Warning device, 310...Processing unit, 320...Operation unit, 330...Storage unit, 340...Display unit, 400...Vehicle

Claims

1. The first output terminal is connected to the first terminal of the sound playback device, A second output terminal connected to the second terminal of the sound playback device, A modulation circuit that modulates a signal based on a sound source signal and outputs a first modulated signal and a second modulated signal, In the first operating mode, a first amplification circuit outputs a first amplified signal obtained by amplifying the first modulated signal to the first output terminal, In the first operating mode, a second amplification circuit outputs a second amplified signal, obtained by amplifying the second modulated signal, to the second output terminal, In the second operating mode, a test signal generation circuit generates a third modulated signal and a fourth modulated signal by modulating a test signal whose frequency is varied within a preset frequency band, In the second operating mode, a peak frequency detection circuit measures the potential difference between the first output terminal and the second output terminal and detects a frequency range that includes the peak frequency, which is the frequency of the test signal at which the impedance of the sound reproduction device peaks. Equipped with, In the second operating mode, the first amplification circuit outputs the third amplified signal, obtained by amplifying the third modulated signal, to the first output terminal. In the second operating mode, the second amplification circuit outputs the fourth amplified signal, obtained by amplifying the fourth modulated signal, to the second output terminal. The first amplification circuit has a plurality of inverter circuits, each of which is connected to the first output terminal. The second amplification circuit has a plurality of inverter circuits, each of which is connected to the second output terminal. In the first operating mode, The first modulation signal is input to each input terminal of the plurality of inverter circuits of the first amplification circuit, and the second modulation signal is input to each input terminal of the plurality of inverter circuits of the second amplification circuit. In the second operating mode, Each of the inverter circuits of some of the plurality of inverter circuits that the first amplification circuit has A semiconductor device in which the third modulation signal is input to an input terminal, the output terminals of some of the other inverter circuits of the plurality of inverter circuits of the first amplification circuit become high impedance, and the fourth modulation signal is input to the input terminals of some of the inverter circuits of the plurality of inverter circuits of the second amplification circuit, and the output terminals of some of the other inverter circuits of the plurality of inverter circuits of the second amplification circuit become high impedance.

2. In claim 1, The semiconductor device includes a peak frequency detection circuit that, in the second operating mode, detects the frequency range by measuring a range that includes the time when the potential difference between the first output terminal and the second output terminal is maximum.

3. In claim 2, The aforementioned peak frequency detection circuit is A differential low-pass filter to which the voltage of the first output terminal and the voltage of the second output terminal are input, A comparator that compares the output voltage of the differential low-pass filter with at least one threshold voltage, A peak time measurement circuit that measures a range including the time when the potential difference between the first output terminal and the second output terminal is maximum, based on the output signal of the comparator, Semiconductor equipment, including

4. In claim 3, A semiconductor device wherein the cutoff frequency of the differential low-pass filter is higher than the maximum frequency of the frequency band.

5. In claim 1, In the second operating mode, the test signal generation circuit modulates the test signal, which has been modified by changing the frequency in a first frequency band included in the frequency band and then changing the frequency in a second frequency band other than the first frequency band included in the frequency band, to generate the third modulated signal and the fourth modulated signal. A semiconductor device wherein the first frequency band includes the peak frequency when the sound reproduction device is functioning normally.

6. In claim 1, The test signal generation circuit is a semiconductor device that, in the second operating mode, modulates the test signal, whose frequency is simultaneously changed in two different first and second frequency bands included in the frequency band, to generate the third modulated signal and the fourth modulated signal.

7. In claim 1, The system includes a fault detection circuit that detects a malfunction in the sound reproduction device based on the frequency range detected by the peak frequency detection circuit, The fault detection circuit is a semiconductor device that, when it detects a fault in the sound reproduction device, outputs an amplified signal of the first modulation signal and an amplified signal of the second modulation signal to a sound reproduction device different from the sound reproduction device.

8. A semiconductor device according to any one of claims 1 to 7, The sound reproduction device and, An electronic device equipped with the following features.

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