SiC substrates and SiC epitaxial wafers

Abstract

To provide an SiC substrate and an SiC epitaxial wafer, which are difficult to cause defects.SOLUTION: In an SiC substrate according to this embodiment, when an inner periphery is supported by an inner periphery supporting face at a position overlapping with a circumference with 17.5 mm radius from a center, a face of a top face for connecting a first point overlapping with the inner periphery supporting face seen from a thickness direction serves as a first reference face. When a part upper than the first reference face is positive, BOW is less than 40 μm.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a SiC substrate and a SiC epitaxial wafer.

Background Art

[0002] Silicon carbide (SiC) has a breakdown electric field that is one order of magnitude larger and a bandgap that is three times larger than that of silicon (Si). In addition, silicon carbide (SiC) has characteristics such as a thermal conductivity that is about three times higher than that of silicon (Si). Therefore, silicon carbide (SiC) is expected to be applied to power devices, high-frequency devices, high-temperature operation devices, etc. For this reason, in recent years, SiC epitaxial wafers have been used for semiconductor devices as described above.

[0003] A SiC epitaxial wafer is obtained by laminating a SiC epitaxial layer on the surface of a SiC substrate cut out from a SiC ingot. Hereinafter, the substrate before laminating the SiC epitaxial layer is referred to as a SiC substrate, and the substrate after laminating the SiC epitaxial layer is referred to as a SiC epitaxial wafer.

[0004] SiC substrates and SiC epitaxial wafers may bend during processes such as conveyance. Bending may cause defects such as poor detection or adsorption by sensors. For example, Patent Document 1 describes suppressing bending during conveyance by supporting a SiC substrate warped so that the center is above the outer periphery. Patent Document 2 also describes supporting the wafer flat with a support to suppress unevenness during heat treatment and prevent bending.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

[0006] There are various methods for supporting wafers, and these methods may be constrained by other configurations. While the methods described in Patent Documents 1 and 2 can suppress the occurrence of defects in certain wafer support cases, they could not sufficiently reduce defects when supporting wafers using, for example, inner circumference support.

[0007] This invention has been made in view of the above problems, and aims to provide a SiC substrate and a SiC epitaxial wafer that are less prone to defects. [Means for solving the problem]

[0008] The inventors have found that by fabricating a SiC substrate in which the BOW and WARP, which define the shape and deflection of the wafer, are within a predetermined range, defects during transport can be reduced by using such a SiC substrate. In other words, the present invention provides the following means to solve the above problem.

[0009] (1) In the SiC substrate according to the first embodiment, when the inner circumference is supported by an inner circumference support surface located at a position that coincides with the circumference with a radius of 17.5 mm from the center, the surface on the upper surface that connects the first points that coincide with the inner circumference support surface when viewed from the thickness direction is defined as the first reference plane, and the area above the first reference plane is defined as positive, the BOW is less than 40 μm.

[0010] (2) The SiC substrate according to the above embodiment may have a WARP of less than 60 μm when supported by the inner peripheral support surface.

[0011] (3) In the SiC substrate according to the above embodiment, when the outer circumference is supported by an outer circumference support surface located 7.5 mm inward from the outermost circumference and overlapping with the outer circumference support surface, the surface on the upper surface that connects the second point that overlaps with the outer circumference support surface when viewed from the thickness direction is defined as the second reference plane, and the area above the second reference plane is defined as positive, the BOW may be greater than -40 μm.

[0012] (4) In the SiC substrate according to the above embodiment, when the outer circumference is supported by the outer circumference support surface, the BOW with respect to the second reference surface may be 0 μm or less.

[0013] (5) The SiC substrate according to the above embodiment may have a WARP of less than 60 μm when supported by the outer peripheral support surface.

[0014] (6) The SiC substrate according to the above embodiment may have a diameter of 145 mm or more.

[0015] (7) The SiC substrate according to the above embodiment may have a diameter of 195 mm or more.

[0016] (8) The SiC epitaxial wafer according to the second embodiment comprises a SiC substrate according to the above embodiment and a SiC epitaxial layer laminated on one surface of the SiC substrate. [Effects of the Invention]

[0017] The SiC substrate and SiC epitaxial wafer according to the above embodiment are less prone to defects. [Brief explanation of the drawing]

[0018] [Figure 1] This is a plan view of the SiC substrate according to this embodiment. [Figure 2] This is a cross-sectional view illustrating a method for evaluating the back-of-warp (BOW) when the SiC substrate according to this embodiment is supported on the inner circumference. [Figure 3] This is a cross-sectional view illustrating a method for evaluating WARP when the SiC substrate according to this embodiment is supported on the inner circumference. [Figure 4] This is a cross-sectional view illustrating a method for evaluating the bounding box (BOW) when the SiC substrate according to this embodiment is supported on its outer periphery. [Figure 5] This is a cross-sectional view illustrating a method for evaluating WARP when the SiC substrate according to this embodiment is supported on its outer periphery. [Figure 6] This is a schematic diagram illustrating the sublimation method, which is an example of a manufacturing apparatus for SiC ingots. [Figure 7] This is a cross-sectional view of a SiC epitaxial wafer according to this embodiment.

Embodiments for Carrying out the Invention

[0019] Hereinafter, the SiC substrate and the like according to this embodiment will be described in detail with appropriate reference to the drawings. The drawings used in the following description may show, for the sake of clarity, the characteristic parts enlarged for convenience, and the dimensional ratios of each component may be different from the actual ones. The materials, dimensions, etc. exemplified in the following description are merely examples, and the present invention is not limited thereto, and it can be appropriately modified and implemented without changing the gist thereof.

[0020] 「First Embodiment」 FIG. 1 is a plan view of a SiC substrate 10 according to this embodiment as viewed in plan from the thickness direction of the SiC substrate 10. The SiC substrate 10 is made of SiC. The polytype of the SiC substrate 10 is not particularly limited and may be any of 2H, 3C, 4H, and 6H. The SiC substrate 10 is, for example, 4H-SiC.

[0021] The plan view shape of the SiC substrate 10 is substantially circular. The SiC substrate 10 may have an orientation flat OF or a notch for grasping the direction of the crystal axis. The diameter of the SiC substrate 10 is, for example, 145 mm or more, preferably 195 mm or more. The larger the diameter of the SiC substrate 10, the larger the absolute amount of deflection even with the same curvature. A SiC epitaxial wafer with a large deflection has a great influence on the subsequent process, and suppression of deflection is required. In other words, the SiC substrate 10 satisfying the configuration of the present invention is more useful as the diameter is larger.

[0022] The SiC substrate 10 may be supported on the inner circumference or the outer circumference, for example, in a process such as conveyance. Inner circumference support is a method of supporting the SiC substrate 10 on the inner circumference support surface 1 near the center C of the SiC substrate 10, and outer circumference support is a method of supporting the SiC substrate 10 on the outer circumference support surface 2 near the outermost circumference E of the SiC substrate 10.

[0023] The position of the inner circumferential support surface 1 is not uniquely defined, but for example, it is located at a position that coincides with the circumference of a circle with a radius of 17.5 mm from the center C. The inner circumferential support surface 1 may be an annular support surface located at a position that coincides with the circumference of a circle with a radius of 17.5 mm from the center C, or it may be multiple support surfaces scattered along the circle. The inner circumferential support surface 1 is the upper surface of the support.

[0024] The position of the outer peripheral support surface 2 is not uniquely defined, but for example, it is located at a position that coincides with the circumference 7.5 mm inward from the outermost circumference E. The outer peripheral support surface 2 may be an annular support surface located at a position that coincides with the circumference 7.5 mm inward from the outermost circumference E, or it may be multiple support surfaces scattered along the said circle. The outer peripheral support surface 2 is the upper surface of the support. For example, if the diameter of the SiC substrate 10 is 150 mm, the outer peripheral support surface 2 is located at a position that coincides with the circumference with a radius of 67.5 mm from the center C. For example, if the diameter of the SiC substrate 10 is 200 mm, the outer peripheral support surface 2 is located at a position that coincides with the circumference with a radius of 92.5 mm from the center C. For example, if the diameter of the SiC substrate 10 is 300 mm, the outer peripheral support surface 2 is located at a position that coincides with the circumference with a radius of 142.5 mm from the center C. For example, if the diameter of the SiC substrate 10 is 450 mm, the outer peripheral support surface 2 is located at a position that coincides with the circumference of a circle with a radius of 217.5 mm from the center C.

[0025] In this embodiment, when the SiC substrate 10 is supported on the inner circumference support surface 1 located at a position that coincides with the circumference with a radius of 17.5 mm from the center C, the BOW is less than 40 μm, preferably 20 μm or less, and more preferably 10 μm or less. When the BOW of the inner circumference support satisfies the above range, transport errors can be reduced. Transport errors include, for example, sensor detection failures, suction failures, and contact with other components.

[0026] Figure 2 is a cross-sectional view illustrating the evaluation method for the back-of-warp (BOW) when the SiC substrate 10 according to this embodiment is supported on its inner circumference. As shown in Figure 2, when the SiC substrate 10 is supported on its inner circumference support surface 1, the center C of the SiC substrate 10 is located further away from the flat surface F than the outermost circumference. That is, the SiC substrate 10 bends upward when supported on its inner circumference.

[0027] BOW measures the height of the wafer's center C, and this height is defined by a signed distance to a three-point reference plane. A value of positive indicates a value above the three-point reference plane, and a value of negative indicates a value below it. The reference plane for inner circumference support is called the first reference plane Sr1. The first reference plane Sr1 is the plane connecting the first point p1 on the upper surface 10a that overlaps with the inner circumference support surface 1 when viewed from the thickness direction. The first point p1 is, for example, the part that overlaps with the inner circumference support surface 1 when viewed from the thickness direction. There are multiple first points p1 if there are multiple inner circumference support surfaces 1. For example, the first reference plane Sr1 is the plane connecting multiple first points p1. In the case of inner circumference support, BOW is determined as the height position of the center C on the upper surface 10a relative to the first reference plane Sr1. In the case of inner circumference support, the absolute value of BOW can be determined as the distance between the first plane S1, which passes through the center C and is parallel to the first reference plane Sr1 (flat plane F), and the three-point reference plane (first reference plane Sr1).

[0028] In this embodiment, the SiC substrate 10 preferably has a WARP of 60 μm or less when supported on the inner circumference, more preferably has a WARP of 30 μm or less, and even more preferably has a WARP of 20 μm or less.

[0029] Figure 3 is a cross-sectional view illustrating a method for evaluating WARP when the SiC substrate 10 according to this embodiment is supported on the inner circumference.

[0030] WARP is the sum of the distances from the three-point reference plane to the highest point hp and the lowest point lp on the upper surface 10a, and is always a positive value. WARP can be calculated, for example, as the distance between the second surface S2, which passes through the highest point hp and is parallel to the three-point reference plane (first reference plane Sr1) (flat surface F), and the third surface S3, which passes through the lowest point lp and is parallel to the three-point reference plane (first reference plane Sr1) (flat surface F). In the case of inner circumference support, the highest point hp may coincide with the center C, in which case the first surface S1 and the second surface S2 coincide. The larger the WARP, the more the SiC substrate 10 is judged to be deformed.

[0031] Furthermore, in the SiC substrate 10 according to this embodiment, the BOW when supported on the outer periphery is preferably greater than -40 μm, more preferably 0 μm or less, and even more preferably -20 μm or more and -5 μm or less. A BOW greater than -40 μm means that the absolute value is less than 40 μm.

[0032] If the BOW (Body Opening) in the case of outer perimeter support is within the above range, transport errors can be suppressed in both the case of inner perimeter support and outer perimeter support of the SiC substrate 10. In other words, a SiC substrate whose BOW is within the predetermined range in both the case of inner perimeter support and outer perimeter support is highly versatile, as it is less likely to cause transport errors even when passing through a transport process where the support method must be changed during transport. In addition, in automated transport equipment, when transporting a wafer on a stage, the wafer is lifted using push-up pins or the like, and a robot hand enters the gap and lifts it for transport. If the BOW is not within the predetermined range, the robot hand and the wafer may collide, or the wafer may not be within the stroke range of the robot hand, causing transport failures.

[0033] Figure 4 is a cross-sectional view illustrating a method for evaluating the bounding box (BOW) when the SiC substrate 10 according to this embodiment is supported on its outer periphery. As shown in Figure 4, when the SiC substrate 10 is supported on its outer periphery by the outer periphery support surface 2, the center C of the SiC substrate 10 is located, for example, closer to the flat surface F than to the outermost periphery. That is, the SiC substrate 10 bends downward, for example, when supported on its outer periphery.

[0034] The reference plane for perimeter support is called the second reference plane Sr2. The second reference plane Sr2 is the plane connecting the second point p2 on the upper surface 10a that overlaps with the perimeter support surface 2 when viewed from the thickness direction. The second point p2 is, for example, the part that overlaps with the radial center of the perimeter support surface 2 when viewed from the thickness direction. There are multiple second points p2 if there are multiple perimeter support surfaces 2. The second reference plane Sr2 is, for example, the plane connecting multiple second points p2. In the case of perimeter support, the BOW is determined as the position in the height direction of the center C of the upper surface 10a with respect to the three-point reference plane (second reference plane Sr2). The absolute value of the BOW in the case of perimeter support is determined as the distance between the first surface S1, which passes through the center C and is parallel to the second reference plane Sr2 (flat surface F), and the three-point reference plane (second reference plane Sr2).

[0035] Figure 5 is a cross-sectional view illustrating a method for evaluating WARP when the SiC substrate 10 according to this embodiment is supported on its outer periphery.

[0036] As described above, WARP is the sum of the distances from the three-point reference plane to the highest point hp and the lowest point lp on the upper surface 10a. WARP can be calculated, for example, as the distance between the second surface S2, which passes through the highest point hp and is parallel to the three-point reference plane (second reference plane Sr2) (flat surface F), and the third surface S3, which passes through the lowest point lp and is parallel to the three-point reference plane (second reference plane Sr2) (flat surface F). In the case of outer perimeter support, the lowest point lp may coincide with the center C, in which case the first surface S1 and the third surface S3 will coincide.

[0037] The BOW and WARP of the SiC substrate 10 in the case of inner and outer circumferential support are affected by the strain generated in the SiC substrate 10 itself and the deflection generated in the SiC substrate 10 due to gravity. The strain generated in the SiC substrate 10 itself is caused, for example, by internal stress. The strain generated in the SiC substrate 10 itself can be controlled during the manufacturing process.

[0038] Next, an example of a method for manufacturing the SiC substrate 10 according to this embodiment will be described. The SiC substrate 10 is obtained by slicing a SiC ingot. The SiC ingot can be obtained, for example, by sublimation.

[0039] Figure 6 is a schematic diagram illustrating the sublimation method, which is an example of a SiC ingot manufacturing apparatus 30. In Figure 6, the direction perpendicular to the surface of the base 32 is the z direction, one direction perpendicular to the z direction is the x direction, and the direction perpendicular to both the z and x directions is the y direction.

[0040] The sublimation method involves placing a seed crystal 33 made of a single SiC crystal on a base 32 placed inside a graphite crucible 31, and heating the crucible 31 to supply sublimation gas, which is produced by sublimation from the raw material powder 34 inside the crucible 31, to the seed crystal 33, thereby growing the seed crystal 33 into a larger SiC ingot 35. The crucible 31 is heated, for example, using a coil 36.

[0041] By controlling the crystal growth conditions in the sublimation method, the BOW and WARP of the SiC substrate 10 obtained from the SiC ingot 35 can be controlled.

[0042] For example, when growing SiC ingot 35 on the c-plane, the temperature of the center and the temperature of the outer periphery of the crystal growth surface are controlled. The crystal growth surface is the surface during the crystal growth process. For example, when growing SiC ingot 35 on the c-plane, the temperature of the outer periphery of the crystal growth surface is lower than the temperature of the center. Furthermore, crystal growth is performed so that the difference in growth rate between the center and the outer periphery within the xy plane is between 0.001 mm / h and 0.05 mm / h. Here, the growth rate in the center within the xy plane is slower than the growth rate at the outer periphery. The growth rate can be changed by changing the temperature of the crystal growth surface.

[0043] The temperature of the crystal growth surface can be adjusted by controlling the z-direction position of the heating center of the crucible 31 using the coil 36. The z-direction position of the heating center of the crucible 31 can be changed by changing the z-direction position of the coil 36. The z-direction position of the heating center of the crucible 31 and the z-direction position of the crystal growth surface are controlled to be separated by 0.5 mm / h. Here, the z-direction position of the heating center of the crucible 31 is controlled to be lower (towards the raw material powder 34) relative to the z-direction position of the crystal growth surface.

[0044] Next, the SiC ingot 35 produced under these conditions is processed into a SiC substrate 10. In general processing methods, the stress on the single crystal changes between the state of the SiC ingot 35 and the state of the SiC substrate 10. For example, in the molding process, when processing a SiC ingot 35 with a diameter of 180 mm into a SiC substrate 10 with a diameter of 150 mm, the diameter needs to be reduced. Also, for example, in the multi-wire cutting process, surface waviness occurs and needs to be removed. Through such processes, for example, areas with high stress in the SiC ingot 35 may be removed or the shape of the crystal lattice plane may change, and the stress in the state of the SiC ingot 35 may be released in the state of the SiC substrate 10. The processing is carried out so that the SiC substrate 10 takes over the stress on the single crystal in the state of the SiC ingot 35. The stress on the SiC substrate 10 is one of the factors that cause the deflection of the SiC substrate 10, and the deflection of the SiC substrate can be adjusted by adjusting the stress. As a result, it becomes possible to suppress the bending of the SiC substrate 10 by utilizing the stress that is transferred to the SiC substrate 10.

[0045] For example, damage-free processing is applied to one side of a SiC ingot 35, then it is cut with a single wire saw, and the damaged-free processed side is adsorbed and further damage-free processing is applied to the cut surface. By performing damage-free processing on both sides of the SiC substrate 10, some of the stress generated in the SiC ingot is transferred to the SiC substrate 10. Damage-free processing is, for example, CMP processing. By processing the substrate in this way, while preserving the lattice plane shape of the SiC ingot 35, the stress of the SiC ingot 35 is transferred to the SiC substrate 10. Subsequently, the deflection of the SiC substrate 10 can be adjusted by performing a molding process to adjust the diameter.

[0046] Thus, by manufacturing the SiC substrate 10 using the above manufacturing method, the BOW and WARP in the case of inner circumference support can be reduced. Furthermore, by manufacturing the SiC substrate 10 using the above manufacturing method, it is also possible to reduce the BOW and WARP in the case of outer circumference support.

[0047] The SiC substrate 10 according to this embodiment is manufactured to satisfy predetermined conditions, resulting in small BOW and WARP when supported on the inner circumference. Therefore, transport errors are less likely to occur even when supported internally. Furthermore, the SiC substrate 10 also has small BOW and WARP when supported on the outer circumference, making transport errors less likely in both inner and outer circumference support cases, thus offering high versatility for the process.

[0048] "Second Embodiment" Figure 7 is a cross-sectional view of a SiC epitaxial wafer 20 according to a second embodiment. The SiC epitaxial wafer 20 comprises a SiC substrate 10 and a SiC epitaxial layer 11. The SiC epitaxial layer 11 is laminated on one surface of the SiC substrate 10. For example, the SiC epitaxial layer 11 is laminated on the upper surface 10a of the SiC substrate 10.

[0049] To obtain high-quality SiC capable of operating a device, a SiC epitaxial layer 11 is laminated onto the SiC substrate 10. Furthermore, mechanical processing such as polishing is often performed before laminating the SiC epitaxial layer 11. In this case, a processed and altered layer is formed on the upper surface 10a of the SiC substrate 10. When the SiC epitaxial layer 11 is laminated or a processed and altered layer is formed on one surface of the SiC substrate 10, the SiC epitaxial wafer 20 may warp.

[0050] The surface of the SiC substrate 10 is often ground. The surface roughness (Ra) of the upper surface 10a of the SiC substrate 10 is preferably, for example, 1 nm or less. The upper surface 10a is, for example, the surface on which the SiC epitaxial layer 11 is laminated.

[0051] The upper surface 10a and lower surface 10b of the SiC substrate 10 may both be ground. The upper surface 10a may be, for example, the Si surface, and the lower surface 10b may be, for example, the C surface. The relationship between the upper surface 10a and the lower surface 10b may be reversed. Both the upper surface 10a and the lower surface 10b may be mirror-polished surfaces with residual scratches, etc., or may be CMP-treated surfaces that have been chemically mechanically polished, and the degree of polishing may differ between the upper surface 10a and the lower surface 10b. A processing-altered layer is formed on mirror-polished surfaces with residual scratches, etc., while almost no processing-altered layer is formed on CMP-treated surfaces. The processing-altered layer is a part that has been damaged by processing, and is a part where the crystal structure has been disrupted.

[0052] For example, if the upper surface 10a is a mirror-polished surface and the lower surface 10b is a CMP-treated surface, the Twymann effect occurs in the SiC substrate 10 due to the difference in surface conditions between the two surfaces. The Twymann effect is a phenomenon in which a force acts to compensate for the difference in residual stress between the two surfaces when there is a difference in residual stress between the two surfaces of the substrate. The Twymann effect can cause warping of the SiC epitaxial wafer 20.

[0053] Furthermore, the SiC epitaxial wafer 20 after lamination of the SiC epitaxial layer 11 preferably has a WARP of 50 μm or less, and more preferably a WARP of 30 μm or less. Furthermore, the SiC epitaxial wafer 20 after lamination of the SiC epitaxial layer 11 preferably has a BOW of 30 μm or less when supported on the inner circumference, and more preferably 10 μm or less. Furthermore, when supported on the outer circumference, the BOW is preferably -30 μm or more.

[0054] In the second embodiment, the SiC epitaxial wafer 20 is less prone to warping even after the SiC epitaxial layer 11 is stacked, because the warp and bounding angle of the SiC substrate 10 are within a predetermined range. Therefore, the SiC epitaxial wafer 20 is also less prone to transport errors.

[0055] Although preferred embodiments of the present invention have been described in detail above, the present invention is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the gist of the present invention as described in the claims. [Examples]

[0056] (Example 1) SiC ingot 35 was fabricated by sublimation. During the fabrication of SiC ingot 35, the z-direction position of the heating center of the crucible 31 and the z-direction position of the crystal growth surface were controlled to separate by 0.5 mm / h. The temperature of the outer periphery of the crystal growth surface was lower than the temperature of the center, and crystal growth was performed so that the difference in growth rate between the center and the periphery in the xy plane was between 0.001 mm / h and 0.05 mm / h.

[0057] The fabricated SiC ingot 35 was then cut with a multi-wire saw and both sides were CMP polished. Through the above process, a SiC substrate 10 with a thickness of 348.15 μm and a diameter of 150 mm was prepared.

[0058] The fabricated SiC substrate 10 was supported by multiple inner circumferential support surfaces 1 arranged on a circle with a radius of 17.5 mm from the center C, and the BOW and WARP were measured. The BOW was 9.468 μm. The WARP was 18.416 μm.

[0059] The SiC substrate 10 was then transported along a predetermined transport path. The height of the transport path was set to 2 mm. The thickness of the robot hand in the transport path was set to 1.5 mm, the stroke width to 50 μm, and the upper limit of the thickness of the wafer being transported to 375 μm. Under these conditions, when multiple SiC substrates 10 of Example 1 were transported, the transport error rate for the SiC substrates 10 of Example 1 was 0%.

[0060] (Example 2) In Example 2, the growth conditions for fabricating the SiC ingot 35 were the same as in Example 1, but the thickness of the cut SiC substrate 10 differed from that of Example 1. When fabricating the SiC substrate 10 in Example 2, the temperature of the outer periphery was lower than the temperature of the center of the crystal growth surface, so that the difference in growth rate between the center and the periphery in the xy plane was between 0.001 mm / h and 0.05 mm / h, and the position of the heating center of the crucible 31 in the z direction and the position of the crystal growth surface in the z direction were controlled to separate by 0.5 mm / h.

[0061] Furthermore, similar to Example 1, the SiC substrate 10 of Example 2 was supported on the inner peripheral support surface 1, and the BOW and WARP were measured. When supported on the inner peripheral support surface 1, the BOW was 35.744 μm and the WARP was 51.174 μm. The transport error rate when the SiC substrate 10 of Example 2 was transported under the same conditions as in Example 1 was 20%.

[0062] (Comparative Example 1, Comparative Example 2) Comparative Examples 1 and 2 differ from Example 1 in that the growth conditions for producing the SiC ingot 35 were changed. In Comparative Examples 1 and 2, the temperature conditions during crystal growth were not specifically controlled.

[0063] Furthermore, similar to Example 1, the BOW and WARP were measured when the SiC substrates 10 of Comparative Examples 1 and 2 were supported on the inner peripheral support surface 1.

[0064] When the SiC substrate 10 of Comparative Example 1 was supported on the inner peripheral support surface 1, the BOW was 74.027 μm and the WARP was 103.705 μm. Furthermore, when the SiC substrate 10 of Comparative Example 1 was transported under the same conditions as in Example 1, the transport error rate was 100%.

[0065] When the SiC substrate 10 of Comparative Example 2 was supported on the inner peripheral support surface 1, the BOW was -30.164 μm and the WARP was 282.608 μm. Furthermore, when the SiC substrate 10 of Comparative Example 2 was transported under the same conditions as in Example 1, the transport error rate was 100%.

[0066] The results of Examples 1 and 2 and Comparative Examples 1 and 2 are summarized in Table 1 below.

[0067] [Table 1]

[0068] Examples 1 and 2, in which the manufacturing temperature was precisely controlled, showed small BOW and WARP even with inner circumference support. Furthermore, the SiC substrates of Examples 1 and 2, which had small BOW and WARP, had a lower transport error rate compared to the SiC substrates of Comparative Examples 1 and 2. In addition, the BOW and WARP of Example 1 were both smaller than those of Example 2. Example 1 has a thicker SiC substrate 10 than Example 2. By increasing the substrate thickness, BOW and WARP can be reduced. [Explanation of symbols]

[0069] 1...Inner circumferential support surface, 2...Outer circumferential support surface, 10...SiC substrate, 10a...Top surface, 10b...Bottom surface, 11...SiC epitaxial layer, 20...SiC epitaxial wafer, 30...Manufacturing equipment, 31...Crucible, 32...Base, 33...Seed crystal, 34...Raw material powder, 35...SiC ingot, 36...Coil, C...Center, F...Flat surface, hp...Highest point, lp...Lowest point, p1...First point, p2...Second point, S1...First surface, S2...Second surface, S3...Third surface, Sr1...First reference surface, Sr2...Second reference surface

Claims

1. When the inner circumference is supported by an inner circumference support surface located at a position that coincides with the circumference of a circle with a radius of 17.5 mm from the center, The surface connecting the first point on the upper surface that overlaps with the inner circumferential support surface when viewed from the thickness direction is defined as the first reference surface, and when the area above the first reference surface is defined as positive, the BOW is less than 40 μm. The thickness is 375 μm or less. A SiC substrate with a diameter of 145 mm or more.

2. The SiC substrate according to Claim 1, wherein the thickness is 348.15 μm or less.

3. The SiC substrate according to Claim 1, wherein the diameter is 195 mm or more.

4. The SiC substrate according to claim 1, comprising a single crystal.

5. The SiC substrate according to claim 1, wherein the BOW when supported by the inner circumferential support surface is 20 μm or less.

6. The SiC substrate according to claim 1, wherein the BOW when supported by the inner circumferential support surface is 10 μm or less.

7. The SiC substrate according to claim 1, wherein the WARP when supported by the inner circumferential support surface is 60 μm or less.

8. The SiC substrate according to claim 1, wherein the WARP when supported by the inner circumferential support surface is 30 μm or less.

9. The SiC substrate according to claim 1, wherein the WARP when supported by the inner circumferential support surface is 20 μm or less.

10. The SiC substrate according to claim 6, wherein the WARP when supported by the inner circumferential support surface is 20 μm or less.

11. When the outer circumference is supported by the outer circumference support surface located 7.5 mm inward from the outermost circumference and overlapping with the circumference, The SiC substrate according to any one of claims 1 to 10, wherein the surface connecting the second point on the upper surface that overlaps with the outer peripheral support surface when viewed from the thickness direction is defined as the second reference plane, and when the area above the second reference plane is defined as positive, the BOW is greater than -40 μm.

12. When the outer circumference is supported by the outer circumference support surface located 7.5 mm inward from the outermost circumference and overlapping with the circumference, The SiC substrate according to claim 11, wherein the surface connecting the second point on the upper surface that overlaps with the outer peripheral support surface when viewed from the thickness direction is defined as the second reference surface, and when the area above the second reference surface is defined as positive, BOW is 0 or less.

13. When the outer circumference is supported by the outer circumference support surface located 7.5 mm inward from the outermost circumference and overlapping with the circumference, The SiC substrate according to claim 12, wherein the surface connecting the second point on the upper surface that overlaps with the outer peripheral support surface when viewed from the thickness direction is defined as the second reference surface, and when the area above the second reference surface is defined as positive, the BOW is -20 μm or more and -5 μm or less.

14. The SiC substrate according to any one of claims 1 to 10, wherein the WARP when supported by an outer peripheral support surface located at a position overlapping with the circumference 7.5 mm inward from the outermost edge is less than 60 μm.

15. A SiC epitaxial wafer having a SiC substrate according to any one of claims 1 to 10 and a SiC epitaxial layer laminated on one surface of the SiC substrate.

16. A SiC epitaxial wafer having a SiC substrate as described in claim 11 and a SiC epitaxial layer laminated on one surface of the SiC substrate.

17. A SiC epitaxial wafer having a SiC substrate as described in claim 12 and a SiC epitaxial layer laminated on one surface of the SiC substrate.

18. A SiC epitaxial wafer having a SiC substrate as described in claim 13 and a SiC epitaxial layer laminated on one surface of the SiC substrate.

19. A SiC epitaxial wafer having a SiC substrate as described in claim 14 and a SiC epitaxial layer laminated on one surface of the SiC substrate.

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