Semiconductor equipment

Abstract

To provide a semiconductor device capable of improving reliability of a gate pad region by eliminating concentration of an avalanche current in the gate pad region.SOLUTION: A semiconductor device comprises a semiconductor substrate 1 of a first conductivity type including an active part 40 and a gate pad part 50, a first semiconductor layer 2 of the first conductivity type, and a second semiconductor layer 6 of a second conductivity type. The active part 40 comprises a first semiconductor region 7 of the first conductivity type, a first trench 16a, a gate insulation film 9b, a first gate electrode 10, an interlayer insulation film 11, and a second semiconductor region 3 of the second conductivity type. The gate pad part 50 comprises a second trench 16b, an insulation film 9b, a second gate electrode 10b, a fourth semiconductor region 3b of the second conductivity type, and a gate electrode pad 14. A polycrystalline silicon film is provided between the gate electrode pad 14 and the semiconductor substrate 1.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is expected to be the next-generation semiconductor material to replace silicon (Si). Semiconductor devices using silicon carbide as the semiconductor material (hereinafter referred to as silicon carbide semiconductor devices) have various advantages compared to conventional semiconductor devices using silicon as the semiconductor material, such as being able to reduce the resistance of the device in the ON state to a fraction of that of silicon, and being usable in environments with higher temperatures (above 200°C). This is due to the inherent characteristics of the material itself, such as the fact that the band gap of silicon is about three times larger than that of silicon, and the dielectric breakdown field strength is nearly an order of magnitude greater than that of silicon.

[0003] To date, silicon carbide semiconductor devices that have been commercialized include Schottky barrier diodes (SBDs) and vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) with planar gate or trench gate structures.

[0004] A planar gate structure is a MOS gate structure in which a MOS gate is provided in a flat plate shape on the front surface of a semiconductor substrate. A trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed on the front surface of a semiconductor substrate (semiconductor chip), and a channel (inversion layer) is formed along the side wall of the trench in a direction perpendicular to the front surface of the semiconductor substrate. Therefore, compared to a planar gate structure in which the channel is formed along the front surface of the semiconductor substrate, the unit cell (elementary component) density per unit area can be increased, and the current density per unit area can be increased, making it advantageous in terms of cost.

[0005] The structure of a conventional silicon carbide semiconductor device will be described by taking a trench-type MOSFET as an example. FIG. 15 is a cross-sectional view showing the structure of an active region of a conventional silicon carbide semiconductor device. In FIG. 15, the structure of an active region 140 through which current flows during the on-state is shown. As shown in FIG. 15, in the trench-type MOSFET 170, an n + -type silicon carbide epitaxial layer 102 is deposited on the front surface of an n - -type silicon carbide substrate 101. An n - -type high-concentration region 105 is provided on the surface side opposite to the n + -type silicon carbide substrate 101 side of the n - -type silicon carbide epitaxial layer 102. In the n + -type silicon carbide epitaxial layer 102, a first p

[0006] -type base region 103 is selectively provided so as to cover the entire bottom surface of the trench 116. + Also, as a MOS structure part, a p-type silicon carbide epitaxial layer 106, an n + -type source region 107, a p + -type contact region 108, a gate insulating film 109, a gate electrode 110, an interlayer insulating film 111, a source electrode 112, a back surface electrode 113, a trench 116, a source electrode pad (not shown), and a drain electrode pad (not shown) are provided. The source electrode 112 is provided on the n

[0007] -type source region 107 and the p-type silicon carbide epitaxial layer 106, and a source electrode pad is provided on the source electrode 112. By providing the first p + -type base region 103 on the bottom surface of the trench 116, concentration of an electric field on the bottom surface of the trench 116 is prevented, and the gate insulating film 109 is protected. On the other hand, in order to maintain the breakdown voltage, the first p + -type base region 103 needs to be installed at the same potential as the source electrode 112 instead of being floating. For this reason, a structure in which a second p + -type base region 104 is selectively provided on a part of the side wall of the channel of the trench 116 is known. Thereby, punch-through can be prevented and the breakdown voltage can be maintained. The second p +The mold base region 104 is provided on the side wall of the m-face of the trench 116, allowing the a-face with high mobility to be used as a channel. Furthermore, the second p + By providing it in the mold base region 104, it becomes unnecessary to provide a p-type region between the trenches 116, and the cell pitch can be reduced.

[0008] Furthermore, a semiconductor device is known in which an electric field relaxation region is provided so as to be in contact with the bottom surface of the gate trench, thereby mitigating the electric field applied to the bottom surface of the gate trench when the semiconductor device is in the off state (see Patent Document 1 below). In addition, a semiconductor device is known in which a second trench is provided in the non-element region, the bottom surface of which reaches the drift layer, and a low-resistance region is provided in the second trench via an internal insulating film to form a capacitance, thereby suppressing the magnitude of the potential drop caused by the displacement current when high-speed switching occurs, as the displacement current passing through the second relaxation region below the second trench is branched to the low-resistance region (see Patent Document 2 below). [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 2019-195081 [Patent Document 2] International Publication No. 2019 / 159351 [Overview of the project] [Problems that the invention aims to solve]

[0010] Figure 16 is a cross-sectional view showing the first structure of the gate pad region of a conventional silicon carbide semiconductor device. Figure 17 is a cross-sectional view showing the second structure of the gate pad region of a conventional silicon carbide semiconductor device. In the gate pad region 150, similar to the active region 140, n + On the front surface of the silicon carbide substrate 101, n -A p-type silicon carbide epitaxial layer 102 and a p-type silicon carbide epitaxial layer 106 are provided. A gate electrode pad 114 is provided on the p-type silicon carbide epitaxial layer 106 via an interlayer insulating film 111. As shown in Figure 17, a gate electrode wiring 115 may be provided in the interlayer insulating film 111. + A back electrode 113 is provided on the back surface of the silicon carbide substrate 101.

[0011] As shown in Figures 16 and 17, in the conventional trench structure, the gate pad area 150 does not have a trench structure. Therefore, the first p + Type base region 103 and 2p + It is not possible to provide the base region 104. As a result, in the gate pad region 150, the p-type silicon carbide epitaxial layer 106 and n - The pn interface with the p-type silicon carbide epitaxial layer 102 is located shallower from the surface of the p-type silicon carbide epitaxial layer 106 than the active region 140, causing the electric field to concentrate at the pn interface of the gate pad region 150. As a result, avalanche yielding occurs in the gate pad region 150, the breakdown voltage cannot be maintained, and the reliability of the gate pad region 150 deteriorates.

[0012] The purpose of this invention is to provide a semiconductor device that can improve the reliability of the gate pad region by eliminating the concentration of avalanche current in the gate pad region, in order to solve the problems of the prior art described above. [Means for solving the problem]

[0013] To solve the above-mentioned problems and achieve the objectives of the present invention, the semiconductor device according to this invention has the following features. The semiconductor device is a semiconductor device including an active portion and a gate pad portion, comprising: a first semiconductor layer of a first conductivity type; and a second semiconductor layer of a second conductivity type selectively provided on the front surface of the first semiconductor layer. The active portion comprises: a source electrode provided on the surface of the second semiconductor layer; a first trench provided below the source electrode and extending in a first direction; and a source region of a first conductivity type selectively provided on the surface layer of the second semiconductor layer and in contact with a part of the side wall of the first trench. The gate pad portion comprises: a gate electrode pad provided above the second semiconductor layer; a second trench provided below the gate electrode pad and extending in a first direction; and a first base region of a second conductivity type provided so as to be in contact with the bottom surface of the second trench. Both the first trench and the second trench are gate trenches. The second trench is before The second semiconductor layer is connected to the first trench and is provided continuously from the active portion to the gate pad portion.

[0014] According to the invention described above, the gate pad area also includes a trench and a first p covering the bottom surface of the trench. + A base region (second semiconductor region of the second conductivity type) is provided. This allows n to be formed between the active region and the gate pad region. - Silicon carbide epitaxial layer (first semiconductor layer of the first conductivity type) and first p + The pn interface with the base region is at the same depth from the surface of the silicon carbide semiconductor substrate. As a result, avalanche current does not concentrate in the gate pad region, the breakdown voltage of the gate pad region can be maintained, and the reliability of the gate insulating film can be improved. [Effects of the Invention]

[0015] The semiconductor device according to the present invention has the effect of eliminating the concentration of avalanche current in the gate pad region and improving the reliability of the gate pad region. [Brief explanation of the drawing]

[0016] [Figure 1] This is a cross-sectional view showing the structure of the active region of the silicon carbide semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view showing the first structure of the gate pad region of the silicon carbide semiconductor device according to Embodiment 1. [Figure 3] This is a cross-sectional view showing the second structure of the gate pad region of the silicon carbide semiconductor device according to Embodiment 1. [Figure 4] This is a cross-sectional view showing the third structure of the gate pad region of the silicon carbide semiconductor device according to Embodiment 1. [Figure 5] This is a cross-sectional view showing the fourth structure of the gate pad region of the silicon carbide semiconductor device according to Embodiment 1. [Figure 6] This is a cross-sectional view showing a fifth structure in the gate pad region of the silicon carbide semiconductor device according to Embodiment 1. [Figure 7] This is a top view showing the structure of a silicon carbide semiconductor device according to Embodiment 1. [Figure 8] This is a cross-sectional view (part 1) showing the state of a silicon carbide semiconductor device during the manufacturing process according to Embodiment 1. [Figure 9] This is a cross-sectional view (part 2) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of manufacturing. [Figure 10] This is a cross-sectional view (part 3) showing the silicon carbide semiconductor device in the process of being manufactured according to Embodiment 1. [Figure 11] This is a cross-sectional view (part 4) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of manufacturing. [Figure 12] This is a cross-sectional view (part 5) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 13] This is a cross-sectional view showing the structure of the active region and gate pad region of the silicon carbide semiconductor device according to Embodiment 2. [Figure 14] This is a top view showing the structure of a silicon carbide semiconductor device according to Embodiment 2. [Figure 15] This is a cross-sectional view showing the structure of the active region of a conventional silicon carbide semiconductor device. [Figure 16] This is a cross-sectional view showing the first structure of the gate pad region of a conventional silicon carbide semiconductor device. [Figure 17] This is a cross-sectional view showing the second structure of the gate pad region of a conventional silicon carbide semiconductor device. [Modes for carrying out the invention]

[0017] Preferred embodiments of the semiconductor device according to this invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - prefixes to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these prefixes. In the following description of embodiments and accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. In this specification, in the notation of Miller indices, "-" indicates a bar attached to the exponent immediately following it, and a "-" before the exponent indicates a negative exponent. Furthermore, it is preferable to include up to 5% variation when describing them as the same or equivalent, taking into account manufacturing variations.

[0018] (Embodiment 1) The semiconductor device according to the present invention is constructed using a wide-bandgap semiconductor. In Embodiment 1, a silicon carbide semiconductor device fabricated (manufactured) using silicon carbide (SiC) as the wide-bandgap semiconductor will be described using a trench-type MOSFET 70 as an example. Figure 1 is a cross-sectional view showing the structure of the active region of the silicon carbide semiconductor device according to Embodiment 1.

[0019] In the silicon carbide semiconductor device according to Embodiment 1, an edge termination region and a gate pad region 50 connected to the gate electrode are provided around the outer periphery of the active region 40 through which the main current flows, to maintain the breakdown voltage. Figure 1 shows only the active region 40 of the trench-type MOSFET 70.

[0020] As shown in Figure 1, the trench-type MOSFET 70 is equipped with a trench gate structure MOS gate on the front side of the semiconductor substrate (the side facing the p-type silicon carbide epitaxial layer 6, which will be described later). The silicon carbide semiconductor substrate is made of n-type silicon carbide. + n - The material is formed by sequentially epitaxially growing n-type silicon carbide epitaxial layers (first semiconductor layers of the first conductivity type) 2. Alternatively, the n-type high-concentration region 5 may be epitaxially grown on the n-type silicon carbide epitaxial layer 2.

[0021] The trench gate structure of the MOS gate consists of a p-type silicon carbide epitaxial layer (second semiconductor layer of the second conductivity type) 6, n + Type source region (first semiconductor region of the first conductivity type) 7, p + It consists of a type contact region 8, a trench (first trench) 16a, a gate insulating film 9, and a gate electrode (first gate electrode) 10. + The type contact area 8 does not need to be provided.

[0022] Specifically, the trench 16a penetrates the p-type silicon carbide epitaxial layer 6 in the depth direction y from the front surface of the semiconductor substrate, and forms an n-type high-concentration region 5 (if an n-type high-concentration region 5 is not provided, then n - The silicon carbide epitaxial layer 2 (hereinafter referred to as (2)) is reached. The depth direction y is the direction from the front surface to the back surface of the semiconductor substrate. The trenches 16a are arranged in a stripe pattern (see Figure 7).

[0023] Inside the trench 16a, a gate insulating film 9 is provided along the inner wall of the trench 16a, and a gate electrode 10 is provided on the gate insulating film 9 so as to be embedded inside the trench 16a. One unit cell of the main semiconductor element is formed by the gate electrode 10 in one trench 16a and the adjacent mesa region 17a (the region between adjacent trenches 16a) on either side of the gate electrode 10. Although only three trench MOS structures are shown in Figure 1, many more trench MOS gate (insulating gate structure consisting of metal-oxide-semiconductor) structures may be arranged in parallel.

[0024] n - An n-type region (hereinafter referred to as the n-type high-concentration region) 5 may be provided on the source side (source electrode 12 side, described later) surface layer of the p-type silicon carbide epitaxial layer 2 so as to be in contact with the p-type silicon carbide epitaxial layer 6. The n-type high-concentration region 5 is a so-called current spreading layer (CSL) that reduces carrier spreading resistance. This n-type high-concentration region 5 is provided uniformly in a direction parallel to the substrate surface (front surface of the semiconductor substrate) so as to cover the inner wall of the trench 16a. The n-type high-concentration region 5 is provided from the interface with the p-type silicon carbide epitaxial layer 6 to a position that does not reach the bottom surface of the trench 16a. The n-type high-concentration region 5 is deeper than the bottom surface of the trench 16a and is the first p-type region described later. + It may be provided to a position shallower than the bottom surface of the mold base region 3.

[0025] n - Inside the silicon carbide epitaxial layer 2, the first p + A type base region (second semiconductor region of the second conductivity type) 3 may be selectively provided. 1p + The mold base region 3 covers at least the bottom surface of the trench 16a, including the bottom surface and the bottom surface corners. The bottom surface corners of the trench 16a refer to the boundary between the bottom surface of the trench 16a and the side walls.

[0026] 1st p. + Type base region 3 and n -The pn junction with the silicon carbide epitaxial layer 2 is formed at a position deeper on the drain side than the bottom surface of trench 16a. + The depth position of the drain-side end of the base region 3 is the first p + Type base region 3 and n - The pn junction with the silicon carbide epitaxial layer 2 only needs to be located deeper on the drain side than the bottom surface of the trench 16a, and can be modified in various ways according to the design conditions. + The mold base region 3 prevents a high electric field from being applied to the gate insulating film 9 in the portion along the bottom surface of the trench 16a.

[0027] n - If a n-type high-concentration region 5 is provided, n - Within the n-type silicon carbide epitaxial layer 2 and the n-type high-concentration region 5 (hereinafter referred to as (2, 5)), the second p + A base region (third semiconductor region of the second conductivity type) 4 may be provided. One trench sidewall may be an m-plane or an a-plane.

[0028] 2nd p. + The base region (third semiconductor region of the second conductivity type) 4 consists of a p-type silicon carbide epitaxial layer 6 and the first p + It is provided so as to be in contact with the base region 3. As shown in Figure 1, the second p + Type base region 4 has a bottom surface that is the first p + At the same depth as the base region 3, n - It is in contact with the silicon carbide epitaxial layer 2, and the upper surface is n, which will be described later. + It may be adjacent to type source region 7. 2p + Type base region 4, 1p + The type base region 3 and the p-type silicon carbide epitaxial layer 6 are electrically connected, and the first p + The base region 3 of the mold is not floating, but is at the same potential as the source electrode 12. This prevents punch-through and maintains the voltage withstand capability.

[0029] 2nd p. + Type base region 4 is n - In the silicon carbide epitaxial layer 2(2,5), multiple trenches may be provided at intervals in a first direction parallel to the extension direction of the trench 16a. In this case, one side wall of the trench 16a in the first direction is the second p + Type base region 4 and n - The silicon carbide epitaxial layer 2 (2, 5) alternates in contact with the other layers.

[0030] Also, page 2 + The mold base region 4 may be provided one at a time on one side wall of the trench 16a without any gaps. In this case, one side wall of the trench 16a in the first direction is the second p + It becomes adjacent to type base region 4.

[0031] Inside the p-type silicon carbide epitaxial layer 6, n + Type source area 7 and p + A type contact region 8 is selectively provided. + The mold source region 7 is in contact with the gate insulating film 9 on the side wall of the trench 16a and faces the gate electrode 10 via the gate insulating film 9 on the side wall of the trench 16a.

[0032] The interlayer insulating film 11 is provided over the entire front surface of the semiconductor substrate so as to cover the gate electrode 10. Contact holes are opened in the interlayer insulating film 11, penetrating the film in the depth direction y and reaching the front surface of the substrate.

[0033] The source electrode (first electrode) 12 is located within a contact hole opened in the interlayer insulating film 11 and is connected to the semiconductor substrate (n + It is in ohmic contact with the source region 7) and is electrically insulated from the gate electrode 10 by the interlayer insulating film 11. A source electrode pad (not shown) is provided on the source electrode 12. + Type source area 7 and p + The contact area 8 makes ohmic contact with the p +If a type contact region 8 is not provided, the source electrode 12 is n + The p-type source region 7 and the p-type silicon carbide epitaxial layer 6 are in ohmic contact.

[0034] A back electrode (second electrode) 13, which serves as a drain electrode, is provided on the back surface of the semiconductor substrate. A drain electrode pad (not shown) is provided on the back electrode 13.

[0035] Figure 2 is a cross-sectional view showing the first structure of the gate pad region of the silicon carbide semiconductor device according to Embodiment 1. In the gate pad region 50, similar to the active region 40, n + On the front surface of the silicon carbide substrate 1, n - A p-type silicon carbide epitaxial layer 2 and a p-type silicon carbide epitaxial layer 6 are provided. n in the gate pad region 50 + Silicon carbide substrate 1, n - The thickness and impurity concentration of the p-type silicon carbide epitaxial layer 2 and the p-type silicon carbide epitaxial layer 6 are as follows: + Silicon carbide substrate 1, n - The p-type silicon carbide epitaxial layer 2 is the same as the p-type silicon carbide epitaxial layer 6. Furthermore, the p-type silicon carbide epitaxial layer 6 in the gate pad region 50 is connected to the p-type silicon carbide epitaxial layer 6 in the active region 40.

[0036] In Embodiment 1, a trench gate structure consisting of a trench (second trench) 16b, a gate insulating film (insulating film) 9b, and a gate electrode (second gate electrode) 10b is provided in the gate pad region 50. The width and depth of the trench 16b in the gate pad region 50 are the same as the width and depth of the trench 16a in the active region 40. In addition, in the gate pad region 50, the gate insulating film 16b is also provided on the surface of the semiconductor substrate in the mesa region 17b between adjacent trenches 16b.

[0037] Also, n - Inside the silicon carbide epitaxial layer 2, the first p +A type base region (fourth semiconductor region of the second conductivity type) 3b may be selectively provided. 1p + The base region 3b, like the active region 40, covers at least the bottom surface of the trench 16b, including the bottom surface and bottom corners. The first p in the gate pad region 50 + The width and depth of the base region 3b are the same as the first p in the active region 40. + It is the same as the width and depth of type base region 3.

[0038] The interlayer insulating film 11 is provided across the entire front surface of the semiconductor substrate via the gate insulating film 9b, and a gate electrode pad 14 that is electrically connected to the gate electrode 10 is provided on the interlayer insulating film 11. A back electrode 13, which serves as a drain electrode, is provided on the back surface of the semiconductor substrate. A drain electrode pad (not shown) is provided on the back electrode 13. - An n-type high-concentration region 5 may be provided on the source-side surface layer of the p-type silicon carbide epitaxial layer 2 so as to be in contact with the p-type silicon carbide epitaxial layer 6.

[0039] Thus, in Embodiment 1, a trench 16b is also provided in the gate pad area 50, and a first p covers the bottom surface of the trench 16b. + A type base region 3b is provided. This allows the active region 40 and the gate pad region 50 to form n - Silicon carbide epitaxial layer 2 and 1p + The pn interface with the base regions 3 and 3b is at the same depth from the surface of the silicon carbide semiconductor substrate. As a result, avalanche current does not concentrate in the gate pad region 50, the breakdown voltage of the gate pad region 50 can be maintained, and the reliability of the gate insulating film 9 can be improved.

[0040] Here, the trench 16b in the gate pad region 50 may or may not be connected to the trench 16a in the active region 40. If trench 16b is connected to trench 16a, the first p + Type base region 3b is the 1p of the active region 40 + By connecting it to type base region 3, the first p +The base region 3b can be brought to the same potential as the source electrode 12. If trench 16b is not connected to trench 16a, the width and depth of trench 16b can be made larger than those of trench 16a. Also, the first p + The impurity concentration in the base region 3b is the 1p of the active region 40. + It can be made higher than the mold base region 3. This makes it easier to concentrate holes in the trench 16b and makes hole control easier.

[0041] Figure 3 is a cross-sectional view showing the second structure of the gate pad region of the silicon carbide semiconductor device according to Embodiment 1. As shown in Figure 3, in the gate pad region 50, the interlayer insulating film 11A is provided over the entire surface of the front of the semiconductor substrate via the gate insulating film 9b so as to cover the p-type silicon carbide epitaxial layer 6. Contact holes are opened in the interlayer insulating film 11A, penetrating the interlayer insulating film 11A in the depth direction y and reaching the front surface of the substrate. In the gate pad region 50, a gate electrode wiring (polycrystalline silicon film) 15 made of polycrystalline silicon (Poly-Si) is provided over the entire surface of the front of the semiconductor substrate. In addition to polycrystalline silicon, the gate electrode wiring 15 may also be made of high-melting-point metals such as titanium or tungsten, or their silicides, nitrides, or multilayer films thereof. The gate electrode wiring 15 makes ohmic contact with the gate electrode 10 within the contact holes provided in the interlayer insulating film 11A, and is electrically insulated from the p-type silicon carbide epitaxial layer 6 by the interlayer insulating film 11A.

[0042] A gate electrode pad 14 is provided on the gate electrode wiring 15 via an interlayer insulating film 11B. In other words, the gate electrode pad 14 and n +A polycrystalline silicon film is provided over the entire surface as a gate electrode wiring 15 between the substrate 1 of silicon carbide. The gate electrode wiring 15 and the gate electrode pad 14 are electrically connected. In FIG. 3, a contact hole is not provided in the interlayer insulating film 11B of the gate pad region 50, and the gate electrode wiring 15 and the gate electrode pad 14 are connected in a portion other than the gate pad region 50. In this case, there is an advantage that the bonding area when bonding a wire to the gate electrode pad 14 does not decrease. Further, since there is always the interlayer insulating film 11B directly under the gate electrode pad 14, damage to the lower element structure is small. It is also possible to provide a contact hole in the interlayer insulating film 11B of the gate pad region 50 and electrically connect the gate electrode wiring 15 and the gate electrode pad 14 through the contact hole. In this case, the interlayer insulating film 11B between the gate electrode pad 14 and the gate electrode wiring 15 can be largely opened, and the contact resistance between the gate electrode pad 14 and the gate electrode wiring 15 can be reduced.

[0043] As described above, in the gate pad region 50, by providing the gate electrode wiring 15 over the entire lower surface of the gate electrode pad 14, the surface of the gate electrode pad 15 can be flattened, and the bonding area when bonding a wire to the gate electrode pad 14 can be increased. Further, since the cross-sectional area of the gate electrode wiring 15 under the gate electrode pad 14 becomes large, the gate resistance (Rg) can be reduced.

[0044] FIG. 4 is a cross-sectional view showing a third structure of the gate pad region of the silicon carbide semiconductor device according to Embodiment 1. As shown in FIG. 4, also in the gate pad region 50, a part of the side wall of the trench 16b has a second p + type base region (fifth semiconductor region of the second conductivity type) 4b selectively provided. The second p + type base region 4b is provided so as to contact the p-type silicon carbide epitaxial layer 6 and the first p + type base region 3b. The width and depth of the second p + type base region 4b in the gate pad region 50 are the second p in the active region 40 +It is the same as the width and depth of the p-type base region 4.

[0045] The p-type silicon carbide epitaxial layer 6 of the gate pad region 50 is continuously connected to the p-type silicon carbide epitaxial layer 6 of the active region 40 in the first direction (z direction) (see FIG. 7). Therefore, similar to the active region 40, the second p + type base region 4b electrically connects the first p + type base region 3b and the p-type silicon carbide epitaxial layer 6, and makes the first p + type base region 3b have the same potential as the source electrode 12 instead of being floating. This prevents punch-through and maintains the breakdown voltage.

[0046] In the same manner as the active region 40, the second p + type base region 4b may be provided in a plurality of forms spaced apart in the first direction parallel to the extending direction of the trench 16b within the n - type silicon carbide epitaxial layer 2. In this case, one side wall of the trench 16b in the first direction is the second p + type base region 4b and the n - type silicon carbide epitaxial layer 2 are alternately in contact. Also, the second p + type base region 4b may be provided on one side wall of the trench 16b without spacing. In this case, one side wall of the trench 16b in the first direction is in contact with the second p + type base region 4b.

[0047] FIG. 5 is a cross-sectional view showing a fourth structure of the gate pad region of the silicon carbide semiconductor device according to Embodiment 1. As shown in FIG. 5, in the gate pad region 50, the gate electrode wiring 15 is provided on the entire front surface of the semiconductor substrate, and the second p + type base region 4b is selectively provided on a part of the side wall of the trench 16b. Thus, the fourth structure has the characteristics of the second structure and the third structure, and has the effects of both the second structure and the third structure.

[0048] Figure 6 is a cross-sectional view showing the fifth structure of the gate pad region of the silicon carbide semiconductor device according to Embodiment 1. As shown in Figure 6, the second p is located on both sides of the side wall of the trench 16b. + A type base region 4b is selectively provided. The trench 16b of the gate pad region 50 does not function as a MOS gate and does not need to form a channel, and a second p is provided on both sides of the side wall. + A mold base region 4b can be provided. This prevents punch-through and maintains voltage resistance better than the third structure in Figure 4. Although not shown, in the structure of Figure 6, it is also possible to provide gate electrode wiring 15 across the entire front surface of the semiconductor substrate in the gate pad region 50.

[0049] Figure 7 is a top view showing the structure of a silicon carbide semiconductor device according to Embodiment 1. In Figure 7, the region below the source electrode 12 is the active region 40, and the region below the gate electrode pad 14 is the gate pad region 50. The p-type silicon carbide epitaxial layer 6 of the gate pad region 50 is connected to the p-type silicon carbide epitaxial layer 6 of the active region 40. As shown in Figure 7, it is preferable that the extension direction (x direction) of the trench 16b in the gate pad region 50 is the same as the extension direction of the trench 16a in the active region 40. Furthermore, it is preferable that the extension direction of the trench 16b in the gate pad region 50 is parallel to the direction of the wire connected to the gate electrode pad 14. For example, one end of this wire is at position A on the outside in the x direction of the trench-type MOSFET 70, and position A and the gate electrode pad 14 are connected by the wire. This prevents shell cracks, such as the destruction of the interlayer insulating film 11, from occurring when the wire is joined to the gate electrode pad 14.

[0050] (Method for manufacturing a silicon carbide semiconductor device according to Embodiment 1) Next, a method for manufacturing a silicon carbide semiconductor device according to Embodiment 1 will be described. Figures 8 to 12 are cross-sectional views showing the silicon carbide semiconductor device during the manufacturing process according to Embodiment 1.

[0051] First, n made of n-type silicon carbide+ Prepare a silicon carbide substrate 1. Then, this n + On the front surface of the silicon carbide substrate 1, a lower n made of silicon carbide is doped with n-type impurities, such as nitrogen atoms. - The silicon carbide epitaxial layer 2a is grown epitaxially. The state up to this point is shown in Figure 8.

[0052] Next, lower n - An ion implantation mask with predetermined openings is formed on the surface of the silicon carbide epitaxial layer 2a, for example, using an oxide film, by photolithography. Then, p-type impurities such as aluminum are implanted into the openings of the oxide film, and the first p + They form type base regions 3 and 3b.

[0053] Next, lower n - On the surface of the silicon carbide epitaxial layer 2a, an upper silicon carbide layer is formed by doping with n-type impurities such as nitrogen. - A silicon carbide epitaxial layer 2b is grown epitaxially. Lower n - Silicon carbide epitaxial layer 2a and upper n - Combined with the silicon carbide epitaxial layer 2b, n - This forms a silicon carbide epitaxial layer 2.

[0054] Next, a portion of the ion implantation mask is removed, and n-type impurities such as nitrogen are ion-implanted into the opening. - A high-concentration n-type region 5 may be formed on a portion of the surface area of ​​the silicon carbide epitaxial layer 2. However, this high-concentration n-type region 5 may or may not be formed across the entire substrate. This state is shown in Figure 9.

[0055] Next, n -A p-type silicon carbide epitaxial layer 6 is formed on the surface of a p-type silicon carbide epitaxial layer 2 by epitaxial growth. After the p-type silicon carbide epitaxial layer 6 is formed by epitaxial growth, p-type impurities such as aluminum may be further implanted into the channel region of the p-type silicon carbide epitaxial layer 6 by ion implantation.

[0056] Next, an ion implantation mask with predetermined openings is formed on the surface of the p-type silicon carbide epitaxial layer 6 by photolithography, for example, using an oxide film. n-type impurities such as nitrogen (N) and phosphorus (P) are ion-implanted into these openings, thereby implanting n into a portion of the surface of the p-type silicon carbide epitaxial layer 6. + Forms type source region 7. + The type source region 7 is formed only in the active region 40. Next, n + Remove the ion implantation mask used to form the type source region 7. Form a new ion implantation mask and implant p-type impurities such as aluminum (Al) and boron (B) using ion implantation, thereby creating adjacent n + During type source region 7, p + Forms a type contact region 8. + The type contact region 8 is formed only in the active region 40. This state is shown in Figure 10.

[0057] Next, a trench-forming mask with predetermined openings is formed on the surface of the p-type silicon carbide epitaxial layer 6 by photolithography, for example, using an oxide film. Then, the p-type silicon carbide epitaxial layer 6 is penetrated by dry etching, n - Trenches 16a and 16b are formed, reaching the silicon carbide epitaxial layer 2. The bottom of trenches 16a and 16b is n - The first p formed in the silicon carbide epitaxial layer 2 + The mold base region 3 is reached. Trench 16a is formed in the active region 40, and trench 16b is formed in the gate pad region 50. Next, the trench formation mask is removed.

[0058] Next, p-type impurities such as aluminum are obliquely ion-implanted from the opening of trench 16a, and a second p-type impurity is implanted into a portion of the side wall of trench 16a. + A mold base region 4 is formed. The second p is located on the side wall of the trench 16b. + The type base region 4b may be formed at the same time.

[0059] Next, heat treatment (annealing) is performed in an inert gas atmosphere at approximately 1700°C, and the first p + Mold base area 3, 3b, 2nd p + Type base region 4, p + Type contact area 8 and n + The type source region 7 is activated. As mentioned above, each ion implantation region may be activated together in a single heat treatment, or the heat treatment may be performed each time ion implantation is performed to activate them. The state up to this point is shown in Figure 11.

[0060] Next, n + A gate insulating film 9 is formed along the surface of the mold source region 7 and the bottom and side walls of the trenches 16a and 16b. This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1000°C in an oxygen atmosphere. Alternatively, this gate insulating film 9 may be formed by deposition by a chemical reaction such as high-temperature oxidation (HTO).

[0061] Next, a polycrystalline silicon film doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon film may be formed to fill the trenches 16a and 16b. The gate electrode 10 is formed by patterning this polycrystalline silicon film using photolithography and leaving it inside the trenches 16a and 16b. The state up to this point is shown in Figure 12.

[0062] Next, a film of, for example, phosphorus glass is deposited to a thickness of about 1 μm to cover the gate insulating film 9 and the gate electrode 10, thereby forming an interlayer insulating film 11. The interlayer insulating film 11 and the gate insulating film 9 are patterned by photolithography. +Contact holes are formed that expose the type source region 7 and the p-type silicon carbide epitaxial layer 6. Then, heat treatment (reflow) is performed to planarize the interlayer insulating film 11. Alternatively, after forming contact holes in the interlayer insulating film 11, a barrier metal consisting of titanium (Ti), titanium nitride (TiN), or a laminate of titanium and titanium nitride may be formed. In this case, the barrier metal also contains n + A contact hole is provided to expose the type source region 7. When forming the gate wiring electrode 15, a step is added afterward to form, for example, a polycrystalline silicon film doped with phosphorus atoms and, for example, phosphorus glass as an interlayer insulating film 11B with a thickness of about 1 μm.

[0063] Next, a conductive film that will serve as the source electrode 12 is formed inside the contact holes provided in the interlayer insulating film 11 and on the interlayer insulating film 11. The conductive film is, for example, a nickel (Ni) film. Then, heat treatment is performed at a temperature of, for example, about 970°C to silicide the nickel film inside the contact holes to form the source electrode 12. After that, the unreacted nickel film is selectively removed, leaving the source electrode 12 only inside the contact holes, for example.

[0064] Next, a source electrode pad (not shown) is formed to fill the contact hole. A portion of the metal layer deposited to form the source electrode pad may also be used as the gate electrode pad 14. + On the back surface of the silicon carbide substrate 1, a metal film such as a nickel (Ni) film or a titanium (Ti) film is formed in the contact area of ​​the back electrode 13 using sputter deposition or the like. This metal film may be a combination of multiple Ni and Ti films stacked together. Subsequently, annealing such as rapid thermal annealing (RTA) is performed so that the metal film silicides and forms an ohmic contact. After that, a thick film, such as a multilayer film in which a Ti film, Ni film, and gold (Au) are stacked in order, is formed by electron beam (EB) deposition or the like to form the back electrode 13.

[0065] In the epitaxial growth and ion implantation described above, n-type impurities (n-type dopants) can be, for example, nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb), which are n-type relative to silicon carbide. For p-type impurities (p-type dopants), for example, boron (B), aluminum (Al), gallium (Ga), indium (In), or thallium (Tl), which are p-type relative to silicon carbide, can be used. In this way, the trench-type MOSFET 70 shown in Figure 1 is completed. Here, an example of the gate pad region 50 for the second structure is shown, but other structures can be formed in the same way.

[0066] As described above, according to Embodiment 1, the gate pad area also has a trench and a first p covering the bottom surface of the trench + A type base region is provided. This allows n to be formed between the active region and the gate pad region. - Type silicon carbide epitaxial layer and 1p + The pn interface with the base region is at the same depth from the surface of the silicon carbide semiconductor substrate. As a result, avalanche current does not concentrate in the gate pad region, the breakdown voltage of the gate pad region can be maintained, and the reliability of the gate insulating film can be improved.

[0067] (Embodiment 2) Figure 13 is a cross-sectional view showing the structure of the active region and gate pad region of the silicon carbide semiconductor device according to Embodiment 2. Figure 14 is a top view showing the structure of the silicon carbide semiconductor device according to Embodiment 2. Figure 13 is a cross-sectional view of the section A-A' in Figure 14. The silicon carbide semiconductor device according to Embodiment 2 differs from the silicon carbide semiconductor device according to Embodiment 1 in that the width of the trench 16b in the gate pad region 50 is wider than the width of the trench 16a in the active region 40, and only one trench 16b is provided in the gate pad region 50.

[0068] In the trench 16b of the gate pad region 50, the size of the trench 16b is slightly larger than that of the gate electrode pad 14. That is, the width of the trench 16b is slightly wider than that of the gate electrode pad 14, and the depth (length in the z direction) of the trench 16b is slightly longer than that of the gate electrode pad 14. On the back electrode 13 side of the gate electrode pad 14, a polycrystalline silicon film extends across the entire surface as the gate electrode 10 in the trench 16b via the interlayer insulating film 11. The gate electrode 10 may be slightly smaller than that of the gate electrode pad 14. For example, if each side of the gate electrode 10 is about 10% smaller than that of the gate electrode pad 14, it can be considered that the polycrystalline silicon film extends across the entire surface below the gate electrode pad 14 in effect. In addition to polycrystalline silicon, high-melting-point metals such as titanium and tungsten, their silicides, nitrides, and multilayer films thereof can be used for the gate electrode 10. Here, contact holes may be provided in the interlayer insulating film 11, and the gate electrode 10 in the trench 16b and the gate electrode pad 14 may be electrically connected. This results in the first p at the bottom of trench 16b. + Contact with the mold base region 3 is facilitated, and the protective capability of the gate insulating film 9 in the gate pad region 50 is higher than in Embodiment 1. In the trench 16b of the gate pad region 50, as in the third structure of Embodiment 1, the second p is added to one side wall. + The mold base region 4 may be selectively provided. Also, as in the fifth structure of Embodiment 1, the second p on both side walls + A type base region 4 may be selectively provided.

[0069] Furthermore, the outermost trench 16a of the active region 40 is on the gate pad region 40 side n + The type source region 7 is not provided and is in contact with the p-type silicon carbide epitaxial layer 6. As a result, the first p of the gate pad region 50 + Holes can be easily extracted from the mold base region 3.

[0070] The entire bottom of trench 16b is covered by 1p +A mold base region 3b is provided. Due to the wide width of the trench 16b, the first p formed below the trench 16b + The type base region 3b is formed below the trench 16a of the active region 40. + The impurity concentration is higher in the base region 3 than in the base region 3. This is because, even if trench 16b is formed using the same method as trench 16a, the proportion of impurities implanted by ion implantation that are absorbed by the sidewall of the mask is lower. Furthermore, because trench 16b is wider, it is formed deeper than trench 16a. Thus, the first p region has a high impurity concentration and is deep. + By providing the mold base region 3b, holes tend to concentrate in the trench 16b, making it easier to control the holes. For example, in Figure 13, there is only one wide trench 16b, but there may be two or more wide trenches 16b. In this case, a structure for drawing out holes can be provided in the region between the trenches 16b, allowing for hole control.

[0071] (Method for manufacturing a silicon carbide semiconductor device according to Embodiment 2) The silicon carbide semiconductor device according to Embodiment 2 can be manufactured by forming one or more trenches 16b in the gate pad region 50, which are wider than the trenches 16a in the active region 40, in the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1. Furthermore, in the ion implantation shown in Figure 9, the first p + Instead of the process of forming the base region 3b, ion implantation is performed on the bottom surface of trenches 16a and 16b after the formation of trenches 16a and 16b, resulting in a first p region with a high impurity concentration and deep depth. + It is possible to form a type base region 3b.

[0072] As described above, Embodiment 2 provides the same effects as Embodiment 1. Furthermore, in Embodiment 2, the width of the trench in the gate pad region is wider than the width of the trench in the active region. As a result, the first p at the bottom of the trench +This facilitates contact with the mold base region and improves the protective capability of the gate insulating film in the gate pad region compared to Embodiment 1.

[0073] As described above, the present invention can be modified in various ways without departing from the spirit of the invention, and in each of the embodiments described above, for example, the dimensions of each part, the impurity concentration, etc. can be set in various ways according to the required specifications. Furthermore, although the above embodiments are described using silicon carbide as the wide bandgap semiconductor as an example, the present invention can also be applied to wide bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN). Furthermore, the present invention can also be applied to semiconductors other than wide bandgap semiconductors, such as silicon (Si) and germanium (Ge). In addition, although the first conductivity type is n-type and the second conductivity type is p-type in each embodiment, the present invention can also be similarly applied if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial applicability]

[0074] As described above, the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, and igniters for automobiles. [Explanation of symbols]

[0075] 1, 101 n + Silicon carbide substrate 2, 102 n - Silicon carbide epitaxial layer 2a bottom n - Silicon carbide epitaxial layer 2b top n - Silicon carbide epitaxial layer 3, 3b, 103 1st p. + Type-based domain 4, 4b, 104 2nd p. + Type-based domain 5, 105 n-type high concentration region 6, 10⁶ p-type silicon carbide epitaxial layer 7, 107 n+ Type source area 8, 108 p + Type Contact Area 9, 9b, 109 Gate Insulator 10, 10b, 110 gate electrodes 11, 111 Interlayer insulating film 12, 112 Source electrodes 13, 113 Backside electrodes 14, 114 Token Pads 15, 115 Gate circuit wiring 16a, 16b, 116 Trench 40 140 Active area 50 150 Gate pad area 70, 170 Trench-type MOSFETs

Claims

1. A semiconductor device comprising an active portion and a gate pad portion, A first semiconductor layer of the first conductivity type, A second semiconductor layer of a second conductivity type is selectively provided on the front surface of the first semiconductor layer, Equipped with, The active portion is A source electrode provided on the surface of the second semiconductor layer, A first trench is provided below the source electrode and extends in the first direction, A source region of a first conductivity type is selectively provided on the surface layer of the second semiconductor layer and is in contact with a part of the side wall of the first trench, Equipped with, The gate pad portion is A gate electrode pad provided above the second semiconductor layer, A second trench is provided below the gate electrode pad and extends in the first direction, A first base region of a second conductivity type is provided so as to be in contact with the bottom surface of the second trench, Equipped with, Both the first trench and the second trench are gate trenches, and the second trench is connected to the first trench. The semiconductor device is characterized in that the second semiconductor layer is provided continuously from the active portion to the gate pad portion.

2. A semiconductor device comprising an active portion and a gate pad portion, A first semiconductor layer of the first conductivity type, A second semiconductor layer of a second conductivity type is selectively provided on the front surface of the first semiconductor layer, Equipped with, The active portion is A source electrode provided on the surface of the second semiconductor layer, A first trench is provided below the source electrode and extends in the first direction, A source region of a first conductivity type is selectively provided on the surface layer of the second semiconductor layer and is in contact with a part of the side wall of the first trench, A first electrode is provided inside the first trench via an insulating film, Equipped with, The gate pad portion is A gate electrode pad provided above the second semiconductor layer, A second trench is provided below the gate electrode pad and extends in the first direction, A first base region of a second conductivity type is provided so as to be in contact with the bottom surface of the second trench, A second electrode is provided inside the second trench via an insulating film, An interlayer insulating film covering the adjacent second electrode, Equipped with, The first electrode and the second electrode are an electrode interface, The second trench is connected to the first trench, The second semiconductor layer is provided continuously from the active portion to the gate pad portion, The side wall of the second trench further comprises a second base region of a second conductivity type that connects the second semiconductor layer and the first base region. A semiconductor device characterized in that the impurity concentrations in both the first base region and the second base region are higher than the impurity concentration in the second semiconductor layer.

3. The semiconductor device according to claim 1, further comprising a second base region of a second conductivity type connecting the second semiconductor layer and the first base region on the side wall of the second trench.

4. The semiconductor device according to claim 2 or 3, characterized in that the second base region is provided on the side walls on both sides of the second trench.

5. The semiconductor device according to claim 2 or 3, characterized in that the second base region is provided in multiple locations in the first direction.

6. The semiconductor device according to claim 2 or 3, characterized in that the second base region is provided continuously with one side wall of the second trench.

7. The semiconductor device according to claim 2 or 3, further comprising a third base region of a second conductivity type provided so as to be in contact with the bottom of the first trench.

8. The semiconductor device according to claim 7, characterized in that the third base region is continuously connected to the first base region.

9. The semiconductor device according to claim 7, further comprising a fourth base region of second conductivity type connecting the second semiconductor layer and the third base region on the side wall of the first trench.

10. The semiconductor device according to claim 9, characterized in that the fourth base region is provided in multiple locations in the first direction.

11. The semiconductor device according to claim 1 or 2, characterized in that the source electrode sandwiches the gate electrode pad in the first direction when viewed from above.

12. The semiconductor device according to claim 1 or 2, characterized in that the second trench is connected to the first trench at both ends.

13. A semiconductor device comprising an active portion and a gate pad portion, A first semiconductor layer of the first conductivity type, A second semiconductor layer of a second conductivity type is selectively provided on the front surface of the first semiconductor layer, Equipped with, The active portion is A source electrode provided on the surface of the second semiconductor layer, A first trench is provided below the source electrode and extends in the first direction, A source region of a first conductivity type is selectively provided on the surface layer of the second semiconductor layer and is in contact with a part of the side wall of the first trench, Equipped with, The gate pad portion is A gate electrode pad provided above the second semiconductor layer, A second trench is provided below the gate electrode pad and extends in the first direction, A first base region of a second conductivity type is provided so as to be in contact with the bottom surface of the second trench, Equipped with, The second trench is connected to the first trench, The second semiconductor layer is provided continuously from the active portion to the gate pad portion, The device further comprises a wire connected to the gate electrode pad, A semiconductor device characterized in that the wire is substantially parallel to the first direction.

14. A first electrode is provided inside the first trench via an insulating film, A second electrode is provided inside the second trench via an insulating film, In the gate pad portion, an interlayer insulating film covers the adjacent second electrode, The semiconductor device according to claim 1, characterized by being equipped with the following features.

15. The semiconductor device according to claim 2 or 14, characterized in that the interlayer insulating film is always located directly beneath the gate electrode pad.

16. The semiconductor device according to claim 14, characterized in that the first electrode and the second electrode are gate electrodes.

17. The semiconductor device according to claim 2 or 14, characterized in that the first electrode and the second electrode are polycrystalline silicon films.

18. The semiconductor device according to claim 2 or 14, characterized in that the first electrode and the second electrode contain a high-melting-point metal.

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