Structure, qubit, quantum computing device, and method for manufacturing the structure

Abstract

A method for producing a structure according to the present invention comprises: a step for forming an s-wave superconductor layer on a base material; a step for forming a first transition metal dichalcogenide layer, which contains a van der Waals layered substance, on the s-wave superconductor layer; and a step for forming a second transition metal dichalcogenide layer on the first transition metal dichalcogenide layer.

Description

[Technical Field]

[0001] This disclosure relates to a structure, a qubit, a quantum computing device, and a method for manufacturing the structure. [Background technology]

[0002] Research is being conducted on quantum computing devices using Majorana particles. A structure combining a two-dimensional topological insulator and an s-wave superconductor has been proposed as a structure for generating Majorana particles. As the two-dimensional topological insulator, a monolayer of WTe2, a layered material of transition metal dichalcogenide, is being used. Furthermore, research is also being conducted on higher-order topological insulator layers consisting of WTe2 multilayer films. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 02-097485 [Patent Document 2] Special Publication No. 2020-511780 [Patent Document 3] U.S. Patent Application Publication No. 2014 / 0174343 [Patent Document 4] U.S. Patent No. 10,403,809 [Patent Document 5] U.S. Patent Application Publication No. 2019 / 0131129 [Patent Document 6] Japanese Patent Publication No. 2018-9201 [Non-patent literature]

[0004] [Non-Patent Document 1] N. Read and D. Green, Phys. Rev. B 61, 10267 (2000) [Non-Patent Document 2] V. Mourik et al., Science 336, 25 (2012)

Non-Patent Document 3

Non-Patent Document 4

Non-Patent Document 5

Non-Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0005] Although theoretical proposals have been made so far, it is not easy to stably obtain transition metal dichalcogenide layers such as WTe2 with good crystallinity.

[0006] An object of the present disclosure is to provide a structure, a quantum bit, a quantum computing device, and a method for manufacturing the structure capable of obtaining good crystallinity in a transition metal dichalcogenide layer.

Means for Solving the Problems

[0007] According to one aspect of the present disclosure, there is provided a method for manufacturing a structure including a step of forming an s-wave superconductor layer on a substrate, a step of forming a first transition metal dichalcogenide layer including a van der Waals layer material on the s-wave superconductor layer, and a step of forming a second transition metal dichalcogenide layer on the first transition metal dichalcogenide layer.

Effects of the Invention

[0008] According to the present disclosure, good crystallinity can be obtained in a transition metal dichalcogenide layer.

Brief Description of the Drawings

[0009] [Figure 1] Figure 1 is a cross-sectional view showing a structure according to the first embodiment. [Figure 2] Figure 2 is a cross-sectional view (part 1) showing a method for manufacturing a structure according to the first embodiment. [Figure 3] Figure 3 is a cross-sectional view (part 2) showing a manufacturing method for the structure according to the first embodiment. [Figure 4] Figure 4 is a cross-sectional view (part 3) showing a method for manufacturing the structure according to the first embodiment. [Figure 5] Figure 5 is a cross-sectional view (part 4) showing a method for manufacturing the structure according to the first embodiment. [Figure 6] Figure 6 is a cross-sectional view (part 5) showing a method for manufacturing the structure according to the first embodiment. [Figure 7] Figure 7 shows the results of the STEM observation (part 1). [Figure 8] Figure 8 is a diagram (part 2) showing the results of STEM observations. [Figure 9] Figure 9 shows the results of Raman spectroscopy measurements according to the first embodiment. [Figure 10] Figure 10 is a top view showing a qubit according to the second embodiment. [Figure 11] Figure 11 is a cross-sectional view (part 1) showing a qubit according to the second embodiment. [Figure 12] Figure 12 is a cross-sectional view (part 2) showing a qubit according to the second embodiment. [Figure 13] Figure 13 is a perspective view showing a higher-order topological insulator layer. [Figure 14] Figure 14 is a top view (part 1) showing a method for manufacturing a qubit according to the second embodiment. [Figure 15] Figure 15 is a top view (part 2) showing a method for manufacturing a qubit according to the second embodiment. [Figure 16] Figure 16 is a top view (part 3) showing a method for manufacturing a qubit according to the second embodiment. [Figure 17]Figure 17 is a top view (part 4) showing a method for manufacturing a qubit according to the second embodiment. [Figure 18] Figure 18 is a top view (part 5) showing a method for manufacturing a qubit according to the second embodiment. [Figure 19] Figure 19 is a top view (part 6) showing a method for manufacturing a qubit according to the second embodiment. [Figure 20] Figure 20 is a cross-sectional view (part 1) showing a method for manufacturing a qubit according to the second embodiment. [Figure 21] Figure 21 is a cross-sectional view (part 2) showing a method for manufacturing a qubit according to the second embodiment. [Figure 22] Figure 22 is a cross-sectional view (part 3) showing a method for manufacturing a qubit according to the second embodiment. [Figure 23] Figure 23 is a cross-sectional view (part 4) showing a method for manufacturing a qubit according to the second embodiment. [Figure 24] Figure 24 is a cross-sectional view (part 5) showing a method for manufacturing a qubit according to the second embodiment. [Figure 25] Figure 25 is a cross-sectional view (part 6) showing a method for manufacturing a qubit according to the second embodiment. [Figure 26] Figure 26 shows a quantum computing device according to the third embodiment. [Modes for carrying out the invention]

[0010] Embodiments of this disclosure will be described in detail below with reference to the attached drawings. In this specification and drawings, components having substantially the same functional configuration will be denoted by the same reference numerals to avoid redundant explanations. In this disclosure, the X1-X2 direction, Y1-Y2 direction, and Z1-Z2 direction are mutually orthogonal directions. A plane including the X1-X2 direction and the Y1-Y2 direction is described as the XY plane, a plane including the Y1-Y2 direction and the Z1-Z2 direction is described as the YZ plane, and a plane including the Z1-Z2 direction and the X1-X2 direction is described as the ZX plane. For convenience, the Z1-Z2 direction is considered the up and down direction, with the Z1 side being the upper side and the Z2 side being the lower side. Furthermore, a plan view means viewing the object from the Z1 side, and a planar shape means the shape of the object as viewed from the Z1 side.

[0011] (First Embodiment) First, the first embodiment will be described. The first embodiment relates to a structure. Figure 1 is a cross-sectional view showing the structure according to the first embodiment.

[0012] The structure 100 according to the first embodiment includes a substrate 110, an s-wave superconductor layer 120, a first transition metal dichalcogenide layer 130, and a second transition metal dichalcogenide layer 140. The s-wave superconductor layer 120 is formed on the substrate 110. The first transition metal dichalcogenide layer 130 is formed on the s-wave superconductor layer 120. The second transition metal dichalcogenide layer 140 is formed on the first transition metal dichalcogenide layer 130.

[0013] The substrate 110 is, for example, a single crystal substrate with a surface Miller index of (100). The material of the substrate 110 is, for example, MgO. In the first embodiment, the substrate 110 is an example of a base material.

[0014] The s-wave superconductor layer 120 is, for example, an Nb layer with a surface Miller index of (100). The thickness of the s-wave superconductor layer 120 is, for example, about 40 nm.

[0015] The first transition metal dichalcogenide layer 130 contains a van der Waals layered material, which is a two-dimensional material. The van der Waals layered material is, for example, NbTe2. The first transition metal dichalcogenide layer 130 has multiple layers of NbTe2, for example, three layers. The thickness of the first transition metal dichalcogenide layer 130 is, for example, 1 nm to 5 nm.

[0016] The second transition metal dichalcogenide layer 140 includes, for example, a multilayer film of WTe2. For example, the second transition metal dichalcogenide layer 140 has multiple layers of WTe2, which is a two-dimensional material. The thickness of the second transition metal dichalcogenide layer 140 is, for example, 1 nm to 5 nm.

[0017] Next, a method for manufacturing the structure 100 according to the first embodiment will be described. Figures 2 to 6 are cross-sectional views showing the method for manufacturing the structure 100 according to the first embodiment. Here, a MgO single crystal substrate with a Miller index of (100) is used as the substrate 110, an Nb layer is formed as the s-wave superconductor layer 120, an NbTe2 layer is formed as the first transition metal dichalcogenide layer 130, and a WTe2 multilayer film is formed as the second transition metal dichalcogenide layer 140.

[0018] First, as shown in Figure 2, a substrate 110 (MgO single crystal substrate) is prepared and annealed at approximately 1200°C for 3 to 4 hours under an oxygen atmosphere at atmospheric pressure. Next, the substrate 110 is immersed in methanol for 20 to 30 minutes and rinsed with ultrapure water. These processes improve the surface flatness of the substrate 110. For example, the surface of the substrate 110 will have atomic-level flatness.

[0019] Subsequently, as shown in Figure 3, an s-wave superconductor layer 120 (Nb layer) is formed on the substrate 110. The s-wave superconductor layer 120 can be epitaxially grown, for example, by pulse laser deposition (PLD). For example, the thickness of the s-wave superconductor layer 120 is set to about 40 nm.

[0020] When forming the s-wave superconductor layer 120 by the PLD method, for example, the basic vacuum level is set to 5 × 10⁻⁶. -6 The temperature can be kept below Pa, and a KrF excimer laser (λ=248nm) can be used as the laser light source. When forming the s-wave superconductor layer 120, for example, a pure Nb metal target can be used as the target. When forming the s-wave superconductor layer 120, for example, the temperature of the substrate 110 can be maintained at approximately 950°C, and the laser energy density can be set to 2.0 J / cm². 2 The irradiation frequency is set to 10 Hz, the distance between the substrate 110 and the target is approximately 5 cm, and the film deposition rate is 1.0 nm / min. The Nb layer is epitaxially grown on the substrate 110, which is maintained at approximately 950°C, while oriented in the

[0100] direction. After epitaxial growth, it is preferable to perform post-annealing at 1100°C to 1200°C for 10 minutes. Post-annealing can improve the surface flatness of the s-wave superconductor layer 120. For example, the surface of the s-wave superconductor layer 120 will have atomic-level flatness.

[0021] Next, as shown in Figure 4, a chalcogen layer 131 is formed on the s-wave superconductor layer 120, and a metal layer 132 containing a transition metal is formed on the chalcogen layer 131. Here, a Te layer is formed as the chalcogen layer 131, and an Nb layer is formed as the metal layer 132. For example, the thickness of the chalcogen layer 131 is 20 nm, and the thickness of the metal layer 132 is 2 nm.

[0022] When forming the chalcogen layer 131 by the PLD method, for example, the basic vacuum level is set to 5 × 10⁻⁶. -6 The temperature can be kept below Pa, and a KrF excimer laser (λ=248nm) can be used as the laser light source. When forming the chalcogen layer 131, for example, a Te pure metal target can be used as the target. When forming the chalcogen layer 131, for example, the temperature of the substrate 110 can be kept at room temperature, and the laser energy density can be set to 1.0 J / cm². 2 The irradiation frequency is set to 1 Hz, the distance between the substrate 110 and the target is approximately 5 cm, and the film deposition rate is 10.0 nm / min.

[0023] When forming the metal layer 132 by the PLD method, for example, the basic vacuum level is set to 5 × 10⁻⁶. -6 The temperature can be kept below Pa, and a KrF excimer laser (λ=248nm) can be used as the laser light source. When forming the metal layer 132, for example, a pure Nb metal target can be used as the target. When forming the metal layer 132, for example, the temperature of the substrate 110 can be kept at room temperature, and the laser energy density can be set to 2.0 J / cm². 2 The irradiation frequency is set to 10 Hz, the distance between the substrate 110 and the target is approximately 5 cm, and the film deposition rate is 1.0 nm / min.

[0024] After the formation of the metal layer 132, post-annealing is performed at 250°C to 350°C for 1 hour. In other words, the chalcogen layer 131 and the metal layer 132 are heated. As a result, as shown in Figure 5, NbTe2, a van der Waals layered material, is generated from the Te contained in the chalcogen layer 131 and the Nb contained in the metal layer 132, and a first transition metal dichalcogenide layer 130 (NbTe2 layer) containing NbTe2 is formed. Nb contained in the s-wave superconductor layer 120 may also be used in the formation of the first transition metal dichalcogenide layer 130. In addition, a part of the chalcogen layer 131 may remain after the formation of the first transition metal dichalcogenide layer 130. Although the vapor pressure of Te is relatively low, since the metal layer 132 is formed on top of the chalcogen layer 131, the metal layer 132 functions as a capping layer, and the rapid evaporation of Te in the chalcogen layer 131 due to heating is suppressed. The first transition metal dichalcogenide layer 130 is formed in a layered manner on the s-wave superconductor layer 120, and the crystal structure of the first transition metal dichalcogenide layer 130 exhibits a 1T structure. The thickness of the first transition metal dichalcogenide layer 130 is, for example, 1 nm to 5 nm.

[0025] Next, as shown in Figure 6, a second transition metal dichalcogenide layer 140 (a multilayer film of WTe2) is formed on the first transition metal dichalcogenide layer 130. The second transition metal dichalcogenide layer 140 can be epitaxially grown, for example, by PLD. For example, the thickness of the second transition metal dichalcogenide layer 140 is about 1 nm to 5 nm.

[0026] When forming the second transition metal dichalcogenide layer 140 by the PLD method, for example, the basic vacuum level is set to 5 × 10⁻⁶. -6 The thermal pressure can be kept below Pa, and a KrF excimer laser (λ=248nm) can be used as the laser light source. When forming the second transition metal dichalcogenide layer 140, for example, a WTe2 sintered target can be used as the target. When forming the second transition metal dichalcogenide layer 140, for example, the temperature of the substrate 110 can be maintained at approximately 325°C, and the laser energy density can be set to 1.0 J / cm². 2 The irradiation frequency is set to 10 Hz, the distance between the substrate 110 and the target is approximately 5 cm, and the film deposition rate is 1.0 nm / min. The second transition metal dichalcogenide layer 140 is epitaxially grown on the first transition metal dichalcogenide layer 130. The crystal structure of the second transition metal dichalcogenide layer 140 exhibits a Td structure.

[0027] The s-wave superconductor layer 120 and the second transition metal dichalcogenide layer 140 can be epitaxially grown in situ, for example, within the same vacuum chamber. The s-wave superconductor layer 120, chalcogen layer 131, metal layer 132, and second transition metal dichalcogenide layer 140 can be formed by physical vapor deposition in a single vacuum process. The method for forming the s-wave superconductor layer 120, chalcogen layer 131, metal layer 132, and second transition metal dichalcogenide layer 140 is not limited to the PLD method. For example, they may be formed by molecular beam epitaxy (MBE), sputtering, or vapor deposition.

[0028] In this way, the structure 100 according to the first embodiment can be manufactured.

[0029] In structure 100, the first transition metal dichalcogenide layer 130 functions as a seed layer for forming the second transition metal dichalcogenide layer 140. Therefore, good crystallinity can be obtained in the second transition metal dichalcogenide layer 140. In other words, in this embodiment, the first transition metal dichalcogenide layer 130 contains van der Waals layered material, and the upper surface of the first transition metal dichalcogenide layer 130 is an inert surface with suppressed dangling bonds. Therefore, a second transition metal dichalcogenide layer 140 with good crystallinity can be grown heteroepitaxially.

[0030] It is preferable to perform post-annealing at approximately 300°C for 30 minutes to 1 hour after forming the second transition metal dichalcogenide layer 140. This is because it improves the crystallinity of the second transition metal dichalcogenide layer 140.

[0031] Next, the results of scanning transmission electron microscope (STEM) observations performed by the inventors on the first embodiment will be described. In this observation, a sample was prepared in accordance with the first embodiment, and STEM observation was performed on this sample. A three-layer NbTe2 laminate was formed as the first transition metal dichalcogenide layer 130, and a three-layer WTe2 laminate was formed as the second transition metal dichalcogenide layer 140. Figures 7 and 8 show the results of the STEM observations. Figure 7 shows a wide-area image obtained by the high-angle annular dark field (HAADF) method, and Figure 8 shows a narrow-area image obtained by the high-resolution HAADF method. In Figures 7 and 8, "Nb(100)" indicates that the s-wave superconductor layer 120 is an Nb layer with a Miller index of (100) on its surface (top surface).

[0032] As shown in Fig. 7, a second transition metal dichalcogenide layer 140 that grew uniformly over at least several tens of nm in a plane parallel to the surface of the s-wave superconductor layer 120 was observed. Also, as shown in Fig. 8, on the s-wave superconductor layer 120, a first transition metal dichalcogenide layer 130 (NbTe2 layer) and a second transition metal dichalcogenide layer 140 (WTe2 layer) that grew epitaxially in three-layer increments were observed. There is a contrast difference between the first transition metal dichalcogenide layer 130 and the second transition metal dichalcogenide layer 140. Note that the thickness of one layer of NbTe2 and the thickness of one layer of WTe2 are both approximately 0.7 nm.

[0033] Next, the results of Raman spectroscopy measurements regarding the first embodiment conducted by the present inventor will be described. In this measurement, a sample (first sample) similar to the sample used for STEM observation was produced, and Raman spectroscopy measurements were performed on the first sample. Also, second and third samples were produced, and Raman spectroscopy measurements were performed on the second and third samples as well. The second sample is a sample in which the number of layers of the WTe2 layer included in the second transition metal dichalcogenide layer 140 is 12 layers. The third sample is a sample in which a second transition metal dichalcogenide layer 140 (12 layers of WTe2) was formed on the s-wave superconductor layer 120 without forming the first transition metal dichalcogenide layer 130. The other configurations of the second and third samples are the same as those of the first sample. Fig. 9 is a diagram showing the results of Raman spectroscopy measurements regarding the first embodiment.

[0034] As shown in Fig. 9, in the first sample, in addition to the phonon modes of A1 2 (213 cm -1 ) and A1 5 (164 cm -1 ) derived from WTe2, the phonon modes of A 1g (159 cm -1 ) and E g (103 cm -1 ) derived from NbTe2 were also observed. In the second sample, compared to the first sample, due to the increase in the number of layers of WTe2, the peak intensities of A1 2 and A1 5 increased. On the other hand, in the third sample, although the number of layers of WTe2 is large, A12 and A1 5 The peak intensity was low. This result indicates that the crystallinity of the second transition metal dichalcogenide layer 140 in the third sample is lower than that of the second sample. From these results, it can be said that the first transition metal dichalcogenide layer 130 contributes to the improvement of the crystallinity of the second transition metal dichalcogenide layer 140.

[0035] (Second Embodiment) Next, a second embodiment will be described. The second embodiment relates to a qubit. The qubit according to the second embodiment is used in a quantum computing device such as a quantum computer. Figure 10 is a top view showing a qubit according to the second embodiment. Figures 11 and 12 are cross-sectional views showing a qubit according to the second embodiment. Figure 11 corresponds to a cross-sectional view along the line XI-XI in Figure 10. Figure 12 corresponds to a cross-sectional view along the line XII-XII in Figure 10.

[0036] The qubit 1 according to the second embodiment includes a substrate 90, an s-wave superconductor layer 10, a transition metal dichalcogenide layer 70, a higher-order topological insulator layer 20, a first ferromagnetic insulator layer 31, a second ferromagnetic insulator layer 32, and a third ferromagnetic insulator layer 33. The qubit 1 further includes a first gate electrode 41, a second gate electrode 42, a third gate electrode 43, a first superconducting quantum interference device (SQUID) 61, a second SQUID 62, and a third SQUID 63.

[0037] The substrate 90 is, for example, a single-crystal substrate with a surface Miller index of (100). Examples of materials for the substrate 90 include MgO, mica, sapphire, and SiC. The substrate 90 may also be a Si substrate with a thermal oxide film.

[0038] The s-wave superconductor layer 10 is provided on a part of the surface of the substrate 90. The s-wave superconductor layer 10 is, for example, an Nb layer with a Miller index of (100) on its surface. The thickness of the s-wave superconductor layer 10 is, for example, about 40 nm. The planar shape of the s-wave superconductor layer 10 is a rectangle with two sides parallel to the X1-X2 direction and two sides parallel to the Y1-Y2 direction.

[0039] The transition metal dichalcogenide layer 70 is provided on the s-wave superconductor layer 10. The transition metal dichalcogenide layer 70 contains a van der Waals layered material, which is a two-dimensional material. The van der Waals layered material is, for example, NbTe2. The transition metal dichalcogenide layer 70 has multiple layers of NbTe2. The thickness of the transition metal dichalcogenide layer 70 is, for example, 2 nm. The transition metal dichalcogenide layer 70 is also an example of a first transition metal dichalcogenide layer.

[0040] The higher-order topological insulator layer 20 is provided on the transition metal dichalcogenide layer 70. The higher-order topological insulator layer 20 includes, for example, a multilayer film of WTe2. For example, the higher-order topological insulator layer 20 has multiple layers of WTe2, which is a two-dimensional material. The thickness of the higher-order topological insulator layer 20 is, for example, 10 nm. The higher-order topological insulator layer 20 is also an example of a second-order transition metal dichalcogenide layer.

[0041] Figure 13 is a perspective view showing the higher-order topological insulator layer 20. The shape of the higher-order topological insulator layer 20 is approximately a rectangular parallelepiped. The a-axis direction of the higher-order topological insulator layer 20 is parallel to the Y1-Y2 direction, the b-axis direction is parallel to the X1-X2 direction, and the c-axis direction is parallel to the Z1-Z2 direction. The Miller index of the top surface of the higher-order topological insulator layer 20 is (001), the Miller index of the Y2 side surface is (100), and the Miller index of the X1 side surface is (010).

[0042] A T-shaped groove 50 is formed on the surface of the higher-order topological insulator layer 20 in a plan view. The groove 50 has a first groove 51, a second groove 52, and a third groove 53. For example, the width of the first groove 51, the second groove 52, and the third groove 53 is 20 nm, and the depth is 5 nm. The first groove 51 and the third groove 53 extend parallel to the X1-X2 direction, and the second groove 52 extends parallel to the Y1-Y2 direction. The first groove 51 is located near the center of the higher-order topological insulator layer 20 in the Y1-Y2 direction and extends from the X2 side end of the higher-order topological insulator layer 20 to the center in the X1-X2 direction. The third groove 53 is located near the center of the higher-order topological insulator layer 20 in the Y1-Y2 direction and extends from the X1 side end of the higher-order topological insulator layer 20 to the center in the X1-X2 direction. Therefore, the first groove 51 and the third groove 53 are formed in a straight line. The second groove 52 is provided near the center of the higher-order topological insulator layer 20 in the X1-X2 direction and extends from the Y1 side end of the higher-order topological insulator layer 20 to the center in the Y1-Y2 direction. Therefore, the second groove 52 is perpendicular to the first groove 51 and the third groove 53.

[0043] The higher-order topological insulator layer 20 has a first region 21 on the Y2 side of the first groove 51 and the third groove 53. The higher-order topological insulator layer 20 has a second region 22 on the Y1 side of the first groove 51 and on the X2 side of the second groove 52. The higher-order topological insulator layer 20 has a third region 23 on the Y1 side of the third groove 53 and on the X1 side of the second groove 52.

[0044] The first region 21, the second region 22, and the third region 23 each have a hinge helical channel on one of two intersection lines between a plane perpendicular to the a-axis and a plane perpendicular to the c-axis. The hinge helical channel is parallel to the b-axis. Specifically, the first region 21 has a first hinge helical channel 11 at the intersection line (edge) between the top surface and the side surface on the Y1 side. The second region 22 has a second hinge helical channel 12 at the intersection line between the side surface on the Y2 side and the bottom surface of the first groove 51. The third region 23 has a third hinge helical channel 13 at the intersection line between the side surface on the Y2 side and the bottom surface of the third groove 53. The first hinge helical channel 11 may be located at the intersection of the Y1-side surface of the first region 21 and the bottom surface of the groove 50, the second hinge helical channel 12 may be located at the intersection of the top surface of the second region 22 and the Y2-side surface, and the third hinge helical channel 13 may be located at the intersection of the top surface of the third region 23 and the Y2-side surface.

[0045] The first ferromagnetic insulator layer 31 is provided on the first region 21, the second region 22, and a portion of the groove 50, and covers a portion of the first hinge helical channel 11 and the second hinge helical channel 12. The second ferromagnetic insulator layer 32 is provided on the second region 22, the third region 23, and a portion of the groove 50, and covers a portion of the second hinge helical channel 12 and the third hinge helical channel 13. The third ferromagnetic insulator layer 33 is provided on the third region 23, the first region 21, and a portion of the groove 50, and covers a portion of the third hinge helical channel 13 and the first hinge helical channel 11. Examples of materials for the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 include Cr2Ga2Te6. The materials for the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 may be other dilution magnetic semiconductors. The thicknesses of the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, and the third ferromagnetic insulator layer 33 are, for example, about 30 nm.

[0046] The second ferromagnetic insulator layer 32 is located on the second hinge helical channel 12, away from the first ferromagnetic insulator layer 31 towards the X1 side in the X1-X2 direction. The third ferromagnetic insulator layer 33 is located on the third hinge helical channel 13, away from the second ferromagnetic insulator layer 32 towards the X1 side in the X1-X2 direction. The third ferromagnetic insulator layer 33 is located on the first hinge helical channel 11, away from the first ferromagnetic insulator layer 31 towards the X1 side in the X1-X2 direction.

[0047] The first gate electrode 41 is provided on the first ferromagnetic insulator layer 31. The second gate electrode 42 is provided on the second ferromagnetic insulator layer 32. The third gate electrode 43 is provided on the third ferromagnetic insulator layer 33. Au is an example of a material for the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43. The thickness of the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 is, for example, about 50 nm.

[0048] The first SQUID 61 has a lower superconductor layer 61A, a lower superconductor layer 61B, a tunnel barrier layer 61C, and an upper superconductor layer 61D.

[0049] The lower superconductor layers 61A and 61B protrude from the X2-side of the s-wave superconductor layer 10 towards the X2 direction. The lower superconductor layer 61A is located on the Y2 side of the lower superconductor layer 61B. In a plan view, the lower superconductor layer 61A protrudes from the first region 21 towards the X2 direction, and the lower superconductor layer 61B protrudes from the second region 22 towards the X2 direction. The lower superconductor layers 61A and 61B are formed integrally with the s-wave superconductor layer 10 from the same material. The lower superconductor layers 61A and 61B are connected to the s-wave superconductor layer 10. The lower superconductor layers 61A and 61B are, for example, Nb layers with a thickness of about 40 nm.

[0050] The tunnel barrier layer 61C and the upper superconductor layer 61D have a U-shaped planar structure. The material for the tunnel barrier layer 61C is NbO xExamples include Nb as the material for the upper superconductor layer 61D. The thickness of the tunnel barrier layer 61C is, for example, about 1 nm to 5 nm, and the thickness of the upper superconductor layer 61D is, for example, about 40 nm. One end of the tunnel barrier layer 61C is in contact with the lower superconductor layer 61A, and the other end is in contact with the lower superconductor layer 61B. The upper superconductor layer 61D is provided on top of the tunnel barrier layer 61C.

[0051] Tunnel barrier layers 61C are sandwiched between the lower superconductor layer 61A and the upper superconductor layer 61D, and between the lower superconductor layer 61B and the upper superconductor layer 61D. The first SQUID 61 is constructed using such Josephson junctions. The first SQUID 61 detects changes in magnetic flux between the first hinge helical channel 11 and the second hinge helical channel 12.

[0052] The second SQUID62 has a lower superconductor layer 62A, a lower superconductor layer 62B, a tunnel barrier layer 62C, and an upper superconductor layer 62D.

[0053] The lower superconductor layers 62A and 62B protrude from the Y1 side of the s-wave superconductor layer 10 toward the Y1 direction. The lower superconductor layer 62A is located on the X2 side of the lower superconductor layer 62B. In a plan view, the lower superconductor layer 62A protrudes toward the Y1 direction from the second region 22, and the lower superconductor layer 62B protrudes toward the Y1 direction from the third region 23. The lower superconductor layers 62A and 62B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10. The lower superconductor layers 62A and 62B are connected to the s-wave superconductor layer 10. The lower superconductor layers 62A and 62B are, for example, Nb layers with a thickness of about 40 nm.

[0054] The tunnel barrier layer 62C and the upper superconductor layer 62D have a U-shaped planar shape. The material of the tunnel barrier layer 62C is NbO xExamples include Nb as the material for the upper superconductor layer 62D. The thickness of the tunnel barrier layer 62C is, for example, about 1 nm to 5 nm, and the thickness of the upper superconductor layer 62D is, for example, about 40 nm. One end of the tunnel barrier layer 62C is in contact with the lower superconductor layer 62A, and the other end is in contact with the lower superconductor layer 62B. The upper superconductor layer 62D is provided on top of the tunnel barrier layer 62C.

[0055] Tunnel barrier layers 62C are sandwiched between the lower superconductor layer 62A and the upper superconductor layer 62D, and between the lower superconductor layer 62B and the upper superconductor layer 62D. The second SQUID 62 is constructed using such Josephson junctions. The second SQUID 62 detects changes in magnetic flux between the second hinge helical channel 12 and the third hinge helical channel 13.

[0056] The third SQUID 63 has a lower superconductor layer 63A, a lower superconductor layer 63B, a tunnel barrier layer 63C, and an upper superconductor layer 63D.

[0057] The lower superconductor layers 63A and 63B protrude from the X1-side of the s-wave superconductor layer 10 toward the X1 direction. The lower superconductor layer 63A is located on the Y1 side of the lower superconductor layer 63B. In a plan view, the lower superconductor layer 63A protrudes toward the X1 direction from the third region 23, and the lower superconductor layer 63B protrudes toward the X1 direction from the first region 21. The lower superconductor layers 63A and 63B are formed integrally with the s-wave superconductor layer 10 from the same material as the s-wave superconductor layer 10. The lower superconductor layers 63A and 63B are connected to the s-wave superconductor layer 10. The lower superconductor layers 63A and 63B are, for example, Nb layers with a thickness of about 40 nm.

[0058] The tunnel barrier layer 63C and the upper superconductor layer 63D have a U-shaped planar shape. The material of the tunnel barrier layer 63C is NbO xExamples include Nb as the material for the upper superconductor layer 63D. The thickness of the tunnel barrier layer 63C is, for example, about 1 nm to 5 nm, and the thickness of the upper superconductor layer 63D is, for example, about 40 nm. One end of the tunnel barrier layer 63C is in contact with the lower superconductor layer 63A, and the other end is in contact with the lower superconductor layer 63B. The upper superconductor layer 63D is provided on top of the tunnel barrier layer 63C.

[0059] Tunnel barrier layers 63C are sandwiched between the lower superconductor layer 63A and the upper superconductor layer 63D, and between the lower superconductor layer 63B and the upper superconductor layer 63D. The third SQUID 63 is constructed using such Josephson junctions. The third SQUID 63 detects changes in magnetic flux between the third hinge helical channel 13 and the first hinge helical channel 11.

[0060] In the qubit 1 configured in this way, four Majorana particles γ1, γ2, γ3, and γ4 are expressed. For example, Majorana particle γ1 is stably expressed near the first gate electrode 41 of the first hinged helical channel 11, and Majorana particle γ4 is stably expressed near the third gate electrode 43 of the first hinged helical channel 11. Also, for example, Majorana particle γ2 is stably expressed between the first gate electrode 41 and the second gate electrode 42 of the second hinged helical channel 12, and Majorana particle γ3 is stably expressed between the second gate electrode 42 and the third gate electrode 43 of the third hinged helical channel 13. The exchange of Majorana particles γ1 to γ4 is carried out by the change in electrostatic potential due to the application of gate voltages to the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43.

[0061] For example, during the exchange of Majorana particle γ1 and Majorana particle γ2, an electric field is applied from the first gate electrode 41, and the minute change in magnetic flux during the exchange of Majorana particles γ1 and γ2 is detected as a minute change in voltage signal by the first SQUID 61. During the exchange of Majorana particle γ2 and Majorana particle γ3, an electric field is applied from the second gate electrode 42, and the minute change in magnetic flux during the exchange of Majorana particles γ2 and γ3 is detected as a minute change in voltage signal by the second SQUID 62. Furthermore, during the exchange of Majorana particle γ3 and Majorana particle γ4, an electric field is applied from the third gate electrode 43, and the minute change in magnetic flux during the exchange of Majorana particles γ3 and γ4 is detected as a minute change in voltage signal by the third SQUID 63.

[0062] Monolayer films of WTe2, a layered material of transition metal dichalcogenide, are easily oxidized, and their properties change when exposed to air. While it is possible to suppress oxidation by sandwiching the WTe2 monolayer film with chemically stable materials such as hexagonal boron nitride (h-BN) or graphene, this complicates the qubit manufacturing process. Furthermore, adjusting the size of the WTe2 monolayer film is difficult. In contrast, in this embodiment, a higher-order topological insulator layer 20 containing a multilayer film of WTe2 or the like is used, so no configuration is required to suppress oxidation. Moreover, adjusting the size of the higher-order topological insulator layer 20 is easier compared to adjusting the size of the WTe2 monolayer film.

[0063] Furthermore, it is possible to create a multi-qubit system by providing multiple qubits 1 on the substrate 90, or to mount a semiconductor integrated circuit on the substrate 90. Therefore, according to this embodiment, research and development toward the realization of a practical error-tolerant quantum computer can be accelerated.

[0064] Next, a method for manufacturing the qubit 1 according to the second embodiment will be described. Figures 14 to 19 are top views showing the method for manufacturing the qubit 1 according to the second embodiment. Figures 20 to 25 are cross-sectional views showing the method for manufacturing the qubit 1 according to the second embodiment.

[0065] First, as shown in Figures 14 and 20, the substrate 90 is prepared and annealed at approximately 1200°C for 3 to 4 hours under an oxygen atmosphere at atmospheric pressure. Next, the substrate 90 is immersed in methanol for 20 to 30 minutes and rinsed with ultrapure water. These processes improve the flatness of the substrate 90 surface. Figure 20 corresponds to a cross-sectional view along the line XX-XX in Figure 14.

[0066] Subsequently, an s-wave superconductor layer 19 is formed on the substrate 90, a first transition metal dichalcogenide layer 79 is formed on the s-wave superconductor layer 19, and a higher-order topological insulator layer 29 is formed on the first transition metal dichalcogenide layer 79. For example, an Nb layer is formed as the s-wave superconductor layer 19, an NbTe2 layer is formed as the first transition metal dichalcogenide layer 79, and a WTe2 multilayer film is formed as the higher-order topological insulator layer 29. The s-wave superconductor layer 19, the first transition metal dichalcogenide layer 79, and the higher-order topological insulator layer 29 can be formed by the same method as the s-wave superconductor layer 120, the first transition metal dichalcogenide layer 130, and the second transition metal dichalcogenide layer 140 in the first embodiment, respectively.

[0067] After the formation of the higher-order topological insulator layer 29, as shown in Figures 15 and 21, the s-wave superconductor layer 19, the first transition metal dichalcogenide layer 79, and the higher-order topological insulator layer 29 are processed to form the s-wave superconductor layer 10, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B from the s-wave superconductor layer 19. Figure 21 corresponds to a cross-sectional view along the line XXI-XXI in Figure 15.

[0068] When processing the s-wave superconductor layer 19, the first transition metal dichalcogenide layer 79, and the higher-order topological insulator layer 29, first, a first electron beam resist is spin-coated onto the higher-order topological insulator layer 29. Next, a first mask pattern is formed from the first electron beam resist by electron beam lithography. The first mask pattern covers the portion of the s-wave superconductor layer 19 where the s-wave superconductor layer 10, lower superconductor layer 61A, lower superconductor layer 61B, lower superconductor layer 62A, lower superconductor layer 62B, lower superconductor layer 63A, and lower superconductor layer 63B are to be formed, from above the higher-order topological insulator layer 29, leaving the other portions exposed. As the first electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) in a 1:1 ratio can be used. After the formation of the first mask pattern, the s-wave superconductor layer 19, the first transition metal dichalcogenide layer 79, and the higher-order topological insulator layer 29 are fabricated by Ar ion milling. For Ar ion milling, for example, the beam acceleration voltage is set to 280V and the beam current to 150mA.

[0069] After processing the s-wave superconductor layer 19, the first transition metal dichalcogenide layer 79, and the higher-order topological insulator layer 29, the first mask pattern is removed, and as shown in Figures 16 and 22, the higher-order topological insulator layer 29 and the first transition metal dichalcogenide layer 79 are processed to form a higher-order topological insulator layer 29A with a rectangular planar shape and a flat top surface from the higher-order topological insulator layer 29, and a transition metal dichalcogenide layer 70 with a rectangular planar shape from the first transition metal dichalcogenide layer 79. Figure 22 corresponds to a cross-sectional view along the line XXII-XXII in Figure 16.

[0070] When processing the higher-order topological insulator layer 29 and the first transition metal dichalcogenide layer 79, first, a second electron beam resist is spin-coated onto the higher-order topological insulator layer 29 and the substrate 90. Next, a second mask pattern is formed from the second electron beam resist by electron beam lithography. The second mask pattern covers the portion of the higher-order topological insulator layer 29 over the s-wave superconductor layer 10, exposing the portions over the lower superconductor layers 61A, 61B, 62A, 62B, 63A, and 63B. As the second electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) in a 1:1 ratio can be used. After the formation of the second mask pattern, the higher-order topological insulator layer 29 and the first transition metal dichalcogenide layer 79 are processed by Ar ion milling. As a result, the higher-order topological insulator layer 29A and the transition metal dichalcogenide layer 70 are formed, and the lower superconductor layers 61A, 61B, 62A, 62B, 63A, and 63B are exposed from the higher-order topological insulator layer 29A and the transition metal dichalcogenide layer 70. In Ar ion milling, for example, the beam acceleration voltage is set to 280V and the beam current to 150mA.

[0071] After the formation of the higher-order topological insulator layer 29A and the transition metal dichalcogenide layer 70, the second mask pattern is removed, and the higher-order topological insulator layer 29A is processed as shown in Figures 17 and 23 to form a higher-order topological insulator layer 20 comprising a first region 21, a second region 22, and a third region 23 from the higher-order topological insulator layer 29A. Figure 23 corresponds to a cross-sectional view along the line XXIII-XXIII in Figure 17.

[0072] When processing the higher-order topological insulator layer 29A, first, a third electron beam resist is spin-coated onto the higher-order topological insulator layer 29A, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B. Next, a third mask pattern is formed from the third electron beam resist by electron beam lithography. The third mask pattern exposes the portion of the higher-order topological insulator layer 29A where the groove 50 is to be formed, and covers the other portions. As the third electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) in a 1:1 ratio can be used. After the formation of the third mask pattern, the higher-order topological insulator layer 29A is processed by Ar ion milling. As a result, a groove 50 having a first groove 51, a second groove 52, and a third groove 53 is formed, and a higher-order topological insulator layer 20 having a first region 21, a second region 22, and a third region 23 is obtained. The first region 21 has a first hinged helical channel 11, the second region 22 has a second hinged helical channel 12, and the third region 23 has a third hinged helical channel 13 (see Figure 13). In Ar ion milling, for example, the beam acceleration voltage is set to 280V and the beam current to 150mA.

[0073] After the formation of the higher-order topological insulator layer 20, the third mask pattern is removed, and the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 are formed, as shown in Figures 18 and 24. Figure 24 corresponds to a cross-sectional view along the line XXIV-XXIV in Figure 18.

[0074] When forming the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43, first, a fourth electron beam resist is spin-coated onto the higher-order topological insulator layer 20, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, and the lower superconductor layer 63B. Next, a fourth mask pattern is formed from the fourth electron beam resist by electron beam lithography. The fourth mask pattern exposes the areas where the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 are to be formed, while covering the other areas. As the fourth electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) in a 1:1 ratio with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) can be used. After the formation of the fourth mask pattern, a Cr2Ga2Te6 layer and an Au layer are formed by the PLD method.

[0075] When forming a Cr2Ga2Te6 layer by PLD, for example, the temperature of the substrate 90 is maintained at 200°C, and the laser energy density is 1.0 J / cm². 2 ~2.0J / cm 2 The irradiation frequency is set to 1 Hz, the distance between the substrate 90 and the target is approximately 5 cm, and the film deposition rate is set to 1.0 nm / min to 2.0 nm / min.

[0076] When forming the Au layer using the PLD method, for example, the temperature of the substrate 90 is kept at room temperature, and the laser energy density is set to 1.0 J / cm². 2 ~2.0J / cm 2 The irradiation frequency is set to 5 Hz, the distance between the substrate 90 and the target is approximately 5 cm, and the film deposition rate is set to 5.0 nm / min to 10.0 nm / min.

[0077] After the formation of the Cr2Ga2Te6 layer and the Au layer, the fourth mask pattern is removed along with the Cr2Ga2Te6 layer and Au layer deposited thereon. In other words, a lift-off is performed. As a result, the first ferromagnetic insulator layer 31, the second ferromagnetic insulator layer 32, the third ferromagnetic insulator layer 33, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43 are obtained. In addition, four Majorana particles γ1, γ2, γ3, and γ4 are expressed.

[0078] Next, as shown in Figures 19 and 25, tunnel barrier layers 61C-63C and upper superconductor layers 61D-63D are formed. Figure 25 corresponds to a cross-sectional view along the XXV-XXV line in Figure 19.

[0079] When forming the tunnel barrier layers 61C-63C and the upper superconductor layers 61D-63D, first, a fifth electron beam resist is spin-coated onto the higher-order topological insulator layer 20, the substrate 90, the lower superconductor layer 61A, the lower superconductor layer 61B, the lower superconductor layer 62A, the lower superconductor layer 62B, the lower superconductor layer 63A, the lower superconductor layer 63B, the first gate electrode 41, the second gate electrode 42, and the third gate electrode 43. Next, a fifth mask pattern is formed from the fifth electron beam resist by electron beam lithography. The fifth mask pattern exposes the areas where the tunnel barrier layers 61C-63C and the upper superconductor layers 61D-63D are to be formed, and covers the other areas. As the fifth electron beam resist, for example, a resist obtained by diluting ZEP 520A (manufactured by Nippon Zeon Co., Ltd.) in a 1:1 ratio with ZEP-A (manufactured by Nippon Zeon Co., Ltd.) can be used. After the formation of the fifth mask pattern, NbO is processed by the PLD method. x Forms a layer and an Nb layer.

[0080] NbO x When forming the layer by the PLD method, for example, an Nb metal target is used, the temperature of the substrate 90 is maintained at room temperature, and the oxygen partial pressure in the vacuum chamber is adjusted to about 50 Pa to 55 Pa. The Nb layer can be formed under the same conditions as the s-wave superconductor layer 19.

[0081] NbO xAfter the formation of the layer and the Nb layer, the fifth mask pattern was applied to the NbO deposited thereon. x The layers and Nb layers are removed together. In other words, a lift-off is performed. As a result, tunnel barrier layers 61C to 63C and upper superconductor layers 61D to 63D are obtained, and the first SQUID 61, second SQUID 62, and third SQUID 63 are formed.

[0082] In this way, the qubit 1 according to the second embodiment can be manufactured.

[0083] In this disclosure, the material of the s-wave superconductor layer is not limited to Nb. The material of the s-wave superconductor layer may be Pb. The material of the chalcogen layer is not limited to Te. The material of the chalcogen layer may be S or Se. The material of the chalcogen layer may be the same type of chalcogen element as that contained in the second transition metal dichalcogenide layer. The material of the metal layer is not limited to Nb. The material of the metal layer may be Pb. It is preferable that the transition metal contained in the s-wave superconductor layer and the transition metal contained in the metal layer are the same type, but they may be different. If the transition metal contained in the s-wave superconductor layer and the transition metal contained in the metal layer are the same type, the transition metal dichalcogenide contained in the first transition metal dichalcogenide layer is likely to be of one type. On the other hand, if the transition metal contained in the s-wave superconductor layer and the transition metal contained in the metal layer are different, the transition metal dichalcogenide contained in the first transition metal dichalcogenide layer may be of two or more types. Even if the first transition metal dichalcogenide layer contains two or more types of transition metal dichalcogenides, good crystallinity can be obtained in the second transition metal dichalcogenide layer. The chalcogen elements contained in the first transition metal dichalcogenide layer and the chalcogen elements contained in the second transition metal dichalcogenide layer may be of the same type.

[0084] In this disclosure, the material of the second transition metal dichalcogenide layer (including the higher-order topological insulator layer) is not limited to WTe2. The second transition metal dichalcogenide layer may contain Mo, Nb, W, Ta, Ti, Zr, Fe, Pd, Ir, or Pt, or any combination thereof, as the transition metal. The layered material contained in the second transition metal dichalcogenide layer may be a single layer.

[0085] (Third embodiment) Next, a third embodiment will be described. The third embodiment relates to a quantum computing device including the qubit 1 according to the second embodiment. Figure 26 is a diagram showing the quantum computing device according to the third embodiment.

[0086] The quantum computing device 2 according to the third embodiment, as shown in Figure 26, includes a qubit chip 81, a signal generator 82, a signal demodulator 83, and a cryogenic dilution refrigerator 84. The qubit chip 81 contains a plurality of qubits 1 according to the second embodiment. The qubit chip 81 is housed in the cryogenic dilution refrigerator 84 and cooled to a temperature of 10 mK or less. The signal generator 82 generates a microwave pulse signal, and the microwave pulse signal is input to the qubit chip 81. The qubit chip 81 outputs a signal corresponding to the microwave pulse signal, and the signal demodulator 83 demodulates the signal output from the qubit chip 81. The signal generator 82 and the signal demodulator 83 are used at a temperature of, for example, room temperature.

[0087] Since the quantum computing device 2 according to the third embodiment includes the qubit 1 according to the second embodiment, Majorana particles can be stably generated, and stable computations can be performed.

[0088] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims. [Explanation of symbols]

[0089] 1: Quantum bit 2: Quantum computing device 10: s-wave superconductor layer 11: First hinged helical channel 12: Second hinged helical channel 13: Third hinged helical channel 20: Higher-order topological insulator layer 21:First area 22:Second area 23: Third area 31: First ferromagnetic insulator layer 32: Second ferromagnetic insulator layer 33: Third ferromagnetic insulator layer 41: First gate 42: Second gate electrode 43: Third Gate 50: Groove 51: 1st groove 52:Second groove 53: Third groove 61: First SQUID 62:2nd SQUID 63: Third SQUID 70: Transition metal dichalcogenide layer 100: Structure 110: Circuit board 120: S-wave superconductor layer 130: First transition metal dichalcogenide layer 131: Chalcogen layer 132: Metal layer 140: Second transition metal dichalcogenide layer

Claims

1. A process of forming an s-wave superconductor layer on a substrate, A step of forming a first transition metal dichalcogenide layer containing a van der Waals layered material on the s-wave superconductor layer, A step of forming a second transition metal dichalcogenide layer on the first transition metal dichalcogenide layer, A method for manufacturing a structure, characterized by having the following features.

2. The method for manufacturing the structure according to claim 1, characterized in that the second transition metal dichalcogenide layer is a higher-order topological insulator layer comprising a plurality of transition metal dichalcogenides laminated on the first transition metal dichalcogenide layer.

3. The step of forming the first transition metal dichalcogenide layer is as follows: The process of forming a chalcogen layer on the s-wave superconductor layer, A step of forming a metal layer containing a transition metal on the chalcogen layer, A step of heating the chalcogen layer and the metal layer, A method for manufacturing the structure according to claim 1 or 2, characterized by having the following:

4. The method for manufacturing the structure according to claim 3, characterized in that the chalcogen layer contains S, Se, Te, or any combination thereof.

5. The method for manufacturing the structure according to claim 3, characterized in that the s-wave superconductor layer is composed of the same type of transition metal as the transition metal contained in the metal layer.

6. Substrate and An s-wave superconductor layer provided on the substrate, A first transition metal dichalcogenide layer containing a van der Waals layered material is provided on the aforementioned s-wave superconductor layer, A second transition metal dichalcogenide layer is provided on the first transition metal dichalcogenide layer, A structure characterized by having the following features.

7. The structure according to claim 6, characterized in that the second transition metal dichalcogenide layer is a higher-order topological insulator layer containing a plurality of transition metal dichalcogenides laminated on the first transition metal dichalcogenide layer.

8. The structure according to claim 6 or 7, characterized in that the first transition metal dichalcogenide layer comprises S, Se, or Te, or any combination thereof.

9. The structure according to claim 6 or 7, characterized in that the s-wave superconductor layer is composed of the same type of transition metal as the transition metal contained in the first transition metal dichalcogenide layer.

10. s-wave superconductor layer, A transition metal dichalcogenide layer containing a van der Waals layered material is provided on the aforementioned s-wave superconductor layer, A higher-order topological insulator layer is provided on the transition metal dichalcogenide layer, A first ferromagnetic insulator layer is provided on the aforementioned higher-order topological insulator layer, A first gate electrode provided on the first ferromagnetic insulator layer, It has, The aforementioned higher-order topological insulating layer is A first region having a first hinged helical channel, A second region having a second hinge helical channel located away from the first hinge helical channel, It has, A qubit characterized in that the first ferromagnetic insulator layer covers the first hinged helical channel and the second hinged helical channel.

11. The qubit according to claim 10, characterized by having a first superconducting quantum interferometer for detecting changes in magnetic flux between the first hinged helical channel and the second hinged helical channel.

12. The higher-order topological insulator layer has a third region comprising a third hinge helical channel separated from the first hinge helical channel and the second hinge helical channel. A second ferromagnetic insulator layer covering the second hinge helical channel and the third hinge helical channel, A second gate electrode provided on the second ferromagnetic insulator layer, The third hinge helical channel and the third ferromagnetic insulator layer covering the first hinge helical channel, A third gate electrode provided on the third ferromagnetic insulator layer, A qubit according to claim 10 or 11, characterized by having the following features.

13. The second superconducting quantum interferometer, The third superconducting quantum interferometer, It has, The second superconducting quantum interferometer detects the change in magnetic flux between the second hinged helical channel and the third hinged helical channel, The qubit according to claim 12, characterized in that the third superconducting quantum interferometer detects a change in magnetic flux between the third hinged helical channel and the first hinged helical channel.

14. In the aforementioned higher-order topological insulating layer, A first groove that defines the first region and the second region, A second groove that defines the second region and the third region, A third groove that defines the third region and the first region, The qubit according to claim 12, characterized in that a qubit is formed.

15. The first groove and the third groove extend in a common first direction, The second groove extends in a second direction perpendicular to the first direction, The qubit according to claim 14, characterized in that the first groove, the second groove, and the third groove are connected.

16. A quantum computing device characterized by including the qubit described in claim 10 or 11.

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